what and where is FreeRTOS home?

[jaaaaaaaaan]

Hello. Once more I need to ask for help.
When I was reading README.md from demo_FreeRTOS I have been told to customize the FREERTOS_HOME variable to point to my FreeRTOS home folder. But what is this folder? I have cloned FreeRTOS repo and it's submodules, then set this variable to FreeRTOS repo or FreeRTOS/FreeRTOS and it gives me :

main.c:57:10: fatal error: FreeRTOS.h: No such file or directory
   57 | #include <FreeRTOS.h>
      |          ^~~~~~~~~~~~
compilation terminated.
make: *** [makefile:176: main.c.o] Error 1

which (according to said README.md) indicates that path ito freertos is invalid, and I don't know where it should be pointing to.
Can someobe point out what I'm missing here?

[stnolting]

I have not tested that example in a long time - seems like the makefile is missing all the freeRTOS-related stuff... This is my fault, sorry for that. I will fix that ASAP! 😉

This is what you need to adapt in the fixed sw/example/demo_freeRTOS/makefile

# FreeRTOS home folder (adapt this!)
FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOSv10.4.1

[stnolting]

To get this demo to compile I had to increase size of 'ram' section in neorv32.ld linker script (alongside MEM_INT_DMEM_SIZE in top entity of course), as ld complains about 'ram' region being overflowed by 720 bytes.

That's right. You should use at least 16kB of DMEM for the freeRTOS demos and maybe 32kB of IMEM. You could simplify the RTOS config in terms of static memory allocation to make it consume less memory. But be aware that the demos do not use the NEORV32 runtime environment for catching traps (like memory exceptions) so memory issues (like stack overflows) are hard to detect.

I have one more question too. If I have enabled extensions A, C, M, and Zicsr should I modify MARCH variable to rv32imaczicsr? If I do so compilation ends with these warnings:

Oh this is a complex question! 😄

Short answer: Always enable the core's CPU_EXTENSION_RISCV_Zicsr extensions and never use Zicsr in the compiler's MARCH variable. So in your case, compile with MARCH=-march=rv32imac.

Long answer:

The compiler will always assume that the "privileged architecture" of the CPU is available (see RISC-V priv. arch. spec), but it will never emit according instructions if these instructions are not explicitly "encoded". This applies to all privileged architecture CPU extensions: Zicsr, Zifencei, PMP, HPM, ...

Example: the Zicsr extension defines CSR (control and status registers) access instructions. The compiler will never emit those instructions if they are not explicitly encoded via inline assembly or by linking according libraries.

However, I really should put a note regarding this in the data sheet / user guide... 😉

[jaaaaaaaaan]

But be aware that the demos do not use the NEORV32 runtime environment for catching traps (like memory exceptions) so memory issues (like stack overflows) are hard to detect.

Oh, so to get interrupts to work under FreeRTOS based on the given example I need to do something like that?

void SystemIrqHandler(uint32_t mcause)
{
  if (mcause = TRAP_CODE_FIRQ_8) {
    switch (XIRQ_SCR)
      {
      case <some_source>:
	//...//
      default:
	break;
	
      }
  } else
  neorv32_uart_printf("freeRTOS: Unknown interrupt (0x%x)\n", mcause);
}

Or do it like it is done in xirq demo?

[stnolting]

The RISC-V port of freeRTOS 10.4.1 only supports the RISC-V timer interrupt and the RISC-V external interrupt (assuming a core-local interrupt controller (CLIC) there). Without kernel modifications, freeRTOS cannot use any of the NEORV32-specififc interrupt sources (they will stall the kernel).

So SystemIrqHandler only gets called if there is an IRQ on the processor's mext_irq_i signal (= RISC-V external interrupt , note that the interrupt source has to enabled in mie CSR).

---

You could modify the OS kernel if you want so that SystemIrqHandler will get called on any interrupt request except for the machine timer interrupt or the environment call exception:

This is a cut-out of the RISC-V kernel port (.../FreeRTOS/Source/portable/GCC/RISC-V/portASM.S):

	test_if_external_interrupt:			/* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
		addi t1, t1, 4					/* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
		bne a0, t1, as_yet_unhandled	/* Something as yet unhandled. */

#endif /* portasmHAS_MTIME */

	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
	jal portasmHANDLE_INTERRUPT			/* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
	j processed_source

If you remove the lines

		addi t1, t1, 4					/* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
		bne a0, t1, as_yet_unhandled	/* Something as yet unhandled. */

all additional interrupts will be delegated to portasmHANDLE_INTERRUPT which is an alias for SystemIrqHandler (see the makefile in the NEORV32 freeRTOS example folder).

[jaaaaaaaaan]

I really hate to bother you more, but I can't get this demo to work. Uart itself works only from bootloader (I use the same settings for bootloader and program).
When I tried to simulate it (with setting INT_BOOTLOADER_EN => false and checking twice that new application_image file created by make USER_FLAGS+=-DRUN_FREERTOS_DEMO clean_all all ) I have got these results:

• At the very beginning
  

• Some time later, when uart attempts to transmit (it repeats over and over):
  
  I have noticed that some of p_bus signals right before are 'X'd, so that's why it is spitting out this nastiness (zoomed on p_bus.wdata around blue marker from before):
  .
  This signal comes from neorv32_busswitch_inst, and while some of i_cache signals are undefined (.fence .priv[1:0] .src) rest of them seems ok.

Now when I actually implemented it (tried both with bootloader and without) then no matter what demo is loaded and running uart does not transmit anything at all (even TX led won't flash), except when bootloader is "in charge". When I examined non-rtos blinker and rtos blinker I have noticed that the non-rtos version does blink, and in exception of uart, works fine,
but when it comes to rtos blinker it seems that tasks are hanging up.The scheduler seems to work, the program execution won't get past the vTaskStartScheduler(); call and task creation functions both return pdPASS, however it does not blink.
Would you be so kind to help me with that? I really have no clue why this is happening.

here is my top module (test bench is trivial, just CLK & RST generation processes ):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library neorv32;
use neorv32.neorv32_package.all;

library Wishbone;
use Wishbone.Wishbone_pkg.all;


entity neorv32_ProcessorTop_Test is
  generic ( WITH_BOOTLOADER : boolean := true );
  port (
    -- Global control --
    clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
    rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
    
    -- UART0 --
    uart0_txd_o : out std_ulogic; -- UART0 send data
    uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
    -- leds
    led_o      : out std_ulogic_vector(3 downto 0);
    -- RGB leds --
    rled_o : out std_ulogic_vector(3 downto 0);
    gled_o : out std_ulogic_vector(3 downto 0);
    bled_o : out std_ulogic_vector(3 downto 0);
    -- motors --
    encoder_ab1_i : in std_ulogic_vector(1 downto 0);
    motor1_dir_o : out std_ulogic;
    motor1_pwm_o : out std_ulogic;
    encoder_ab2_i : in std_ulogic_vector(1 downto 0);
    motor2_dir_o : out std_ulogic;
    motor2_pwm_o : out std_ulogic;
    -- ADC signals --
    vauxp15: in  STD_LOGIC:= '0';                         -- Auxiliary Channel 1
    vauxn15: in  STD_LOGIC:= '0';
    vauxp7: in  STD_LOGIC:= '0';                         -- Auxiliary Channel 2
    vauxn7: in  STD_LOGIC:= '0';
    vauxp4 : in  STD_LOGIC:= '0';                         -- Auxiliary Channel 4
    vauxn4 : in  STD_LOGIC:= '0';
    vauxp5 : in  STD_LOGIC:= '0';                         -- Auxiliary Channel 5
    vauxn5 : in  STD_LOGIC:= '0';
    vauxp6 : in  STD_LOGIC:= '0';                         -- Auxiliary Channel 6
    vauxn6 : in  STD_LOGIC:= '0';
    -- IR LED's mux --
    IR_LED_MUX_O : out STD_ULOGIC_VECTOR (4 downto 0) );
end entity;

architecture neorv32_ProcessorTop_rtl of neorv32_ProcessorTop_Test is
  --Addresses of peripherals--
  constant led_addr : STD_ULOGIC_VECTOR(31 downto 0) := x"A0000000";
  constant motor1_addr : STD_ULOGIC_VECTOR (31 downto 0) := x"A0000004";
  constant motor2_addr : STD_ULOGIC_VECTOR (31 downto 0) := x"A0000008";
  constant sensor1_addr : STD_ULOGIC_VECTOR (31 downto 0) := x"A000000C";
  constant sensor2_addr : STD_ULOGIC_VECTOR (31 downto 0) := x"A0000010";
  constant sensor3_addr : STD_ULOGIC_VECTOR (31 downto 0) := x"A0000014";
  constant sensor4_addr : STD_ULOGIC_VECTOR (31 downto 0) := x"A0000018";
  constant sensor5_addr : STD_ULOGIC_VECTOR (31 downto 0) := x"A000001C";
 
  -- gpio output --
  signal gpio_out : std_ulogic_vector(63 downto 0) := (others => '0');
  -- Wishbone bus interface --
  signal wb_adr_o : std_ulogic_vector (31 downto 0) := (others => '0');
  signal wb_dat_i : std_ulogic_vector (31 downto 0) := (others => '0');
  signal wb_dat_o : std_ulogic_vector (31 downto 0) := (others => '0');
  signal wb_we_o  : std_ulogic := '0'; 
  signal wb_sel_o : std_ulogic_vector (3 downto 0) := (others => '0');
  signal wb_stb_o : std_ulogic := '0';    
  signal wb_cyc_o : std_ulogic := '0';    
  signal wb_ack_i : std_ulogic := '0';
  -- Peripherals --
   --leds
  signal reg_leds : std_ulogic_vector(31 downto 0) := (others => '0');
  signal wb_leds_d_o : std_ulogic_vector(31 downto 0) := (others => '0');
  signal wb_leds_ack_o : std_ulogic := '0';
   --motors and encoders
  signal wb_motor1_d_o : std_ulogic_vector(31 downto 0) := (others => '0');
  signal wb_motor1_ack_o : std_ulogic := '0';
  signal motor1_irq_o : std_ulogic := '0';
  signal wb_motor2_d_o : std_ulogic_vector(31 downto 0) := (others => '0');
  signal wb_motor2_ack_o : std_ulogic := '0';
  signal motor2_irq_o : std_ulogic := '0';
  --sensors
  signal wb_sensor1_o : std_ulogic_vector (31 downto 0) := (others => '0');
  signal wb_sensor1_ack_o : std_ulogic := '0';
  signal wb_sensor2_o : std_ulogic_vector (31 downto 0) := (others => '0');
  signal wb_sensor2_ack_o : std_ulogic := '0';
  signal wb_sensor3_o : std_ulogic_vector (31 downto 0) := (others => '0');
  signal wb_sensor3_ack_o : std_ulogic := '0';
  signal wb_sensor4_o : std_ulogic_vector (31 downto 0) := (others => '0');
  signal wb_sensor4_ack_o : std_ulogic := '0';
  signal wb_sensor5_o : std_ulogic_vector (31 downto 0) := (others => '0');
  signal wb_sensor5_ack_o : std_ulogic := '0';
  signal sensor_mux_irq_o : std_ulogic := '0';

  signal rgb_led_pwm : std_ulogic := '0';
  signal dummy_irq : std_ulogic := '0';
  signal mtime : std_ulogic_vector (63 downto 0) := (others => '0');  
begin

  -- The Core Of The Problem ----------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  neorv32_top_inst: neorv32_top
  generic map (
    -- General --
    CLOCK_FREQUENCY              => 100000000,   -- clock frequency of clk_i in Hz
    INT_BOOTLOADER_EN            => WITH_BOOTLOADER,        -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
    USER_CODE                    => x"00000000", -- custom user code
    HW_THREAD_ID                 => 0,           -- hardware thread id (hartid)
    -- On-Chip Debugger (OCD) --
    ON_CHIP_DEBUGGER_EN          => true,       -- implement on-chip debugger
    -- RISC-V CPU Extensions --
    CPU_EXTENSION_RISCV_A        => true,        -- implement atomic extension?
    CPU_EXTENSION_RISCV_C        => true,        -- implement compressed extension?
    CPU_EXTENSION_RISCV_E        => false,       -- implement embedded RF extension?
    CPU_EXTENSION_RISCV_M        => true,        -- implement muld/div extension?
    CPU_EXTENSION_RISCV_U        => false,        -- implement user mode extension?
    CPU_EXTENSION_RISCV_Zfinx    => false,       -- implement 32-bit floating-point extension (using INT reg!)
    CPU_EXTENSION_RISCV_Zicsr    => true,        -- implement CSR system?
    CPU_EXTENSION_RISCV_Zifencei => false,       -- implement instruction stream sync.?
    -- Extension Options --
    FAST_MUL_EN                  => true,       -- use DSPs for M extension's multiplier
    FAST_SHIFT_EN                => true,       -- use barrel shifter for shift operations
    CPU_CNT_WIDTH                => 64,          -- total width of CPU cycle and instret counters (0..64)
    -- Physical Memory Protection (PMP) --
    PMP_NUM_REGIONS              => 0,           -- number of regions (0..64)
    PMP_MIN_GRANULARITY          => 64*1024,     -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
    -- Hardware Performance Monitors (HPM) --
    HPM_NUM_CNTS                 => 4,           -- number of implemented HPM counters (0..29)
    HPM_CNT_WIDTH                => 40,          -- total size of HPM counters (0..64)
    -- Internal Instruction memory --
    MEM_INT_IMEM_EN              => true,        -- implement processor-internal instruction memory
    MEM_INT_IMEM_SIZE            => 32*1024,     -- size of processor-internal instruction memory in bytes
    -- Internal Data memory --
    MEM_INT_DMEM_EN              => true,        -- implement processor-internal data memory
    MEM_INT_DMEM_SIZE            => 16*1024,      -- size of processor-internal data memory in bytes
    -- Internal Cache memory --
    ICACHE_EN                    => false,       -- implement instruction cache
    ICACHE_NUM_BLOCKS            => 4,           -- i-cache: number of blocks (min 1), has to be a power of 2
    ICACHE_BLOCK_SIZE            => 64,          -- i-cache: block size in bytes (min 4), has to be a power of 2
    ICACHE_ASSOCIATIVITY         => 1,           -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
    -- External memory interface --
    MEM_EXT_EN                   => true,       -- implement external memory bus interface?
    MEM_EXT_TIMEOUT              => 0,           -- cycles after a pending bus access auto-terminates (0 = disabled)
    -- Processor peripherals --
    IO_GPIO_EN                   => true,        -- implement general purpose input/output port unit (GPIO)?
    IO_MTIME_EN                  => true,        -- implement machine system timer (MTIME)?
    IO_UART0_EN                  => true,        -- implement primary universal asynchronous receiver/transmitter (UART0)?
    IO_UART1_EN                  => false,       -- implement secondary universal asynchronous receiver/transmitter (UART1)?
    IO_SPI_EN                    => false,       -- implement serial peripheral interface (SPI)?
    IO_TWI_EN                    => false,       -- implement two-wire interface (TWI)?
    IO_PWM_NUM_CH                => 0,           -- number of PWM channels to implement (0..60); 0 = disabled
    IO_WDT_EN                    => true,        -- implement watch dog timer (WDT)?
    IO_TRNG_EN                   => false,       -- implement true random number generator (TRNG)?
    IO_CFS_EN                    => false,       -- implement custom functions subsystem (CFS)?
    IO_CFS_CONFIG                => x"00000000", -- custom CFS configuration generic
    IO_CFS_IN_SIZE               => 32,          -- size of CFS input conduit in bits
    IO_CFS_OUT_SIZE              => 32,          -- size of CFS output conduit in bits
    IO_NEOLED_EN                 => false,        -- implement NeoPixel-compatible smart LED interface (NEOLED)?
    --- interrupts --
    XIRQ_NUM_CH                  => 0,      -- number of external IRQ channels (0..32)
    XIRQ_TRIGGER_TYPE            => (others => '0') -- trigger type: 0=level, 1=edge

  )
  port map (
    -- Global control --
    clk_i       => clk_i,           -- global clock, rising edge
    rstn_i      => rstn_i,          -- global reset, low-active, async
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
    jtag_trst_i => '0',             -- low-active TAP reset (optional)
    jtag_tck_i  => '0',             -- serial clock
    jtag_tdi_i  => '0',             -- serial data input
    jtag_tdo_o  => open,            -- serial data output
    jtag_tms_i  => '0',             -- mode select
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
    wb_tag_o    => open,            -- tag
    wb_adr_o    => wb_adr_o,            -- address
    wb_dat_i    => wb_dat_i, -- read data
    wb_dat_o    => wb_dat_o,            -- write data
    wb_we_o     => wb_we_o,            -- read/write
    wb_sel_o    => wb_sel_o,            -- byte enable
    wb_stb_o    => wb_stb_o,            -- strobe
    wb_cyc_o    => wb_cyc_o,            -- valid cycle
    wb_lock_o   => open,            -- exclusive access request
    wb_ack_i    => wb_ack_i,             -- transfer acknowledge
    wb_err_i    => '0',             -- transfer error
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
    fence_o     => open,            -- indicates an executed FENCE operation
    fencei_o    => open,            -- indicates an executed FENCEI operation
    -- GPIO (available if IO_GPIO_EN = true) --
    gpio_o      => gpio_out,        -- parallel output
    gpio_i      => (others => '0'), -- parallel input
    -- primary UART0 (available if IO_UART0_EN = true) --
    uart0_txd_o => uart0_txd_o,     -- UART0 send data
    uart0_rxd_i => uart0_rxd_i,     -- UART0 receive data
    uart0_rts_o => open,            -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
    uart0_cts_i => '1',             -- hw flow control: UART0.TX allowed to transmit, low-active, optional
    -- secondary UART1 (available if IO_UART1_EN = true) --
    uart1_txd_o => open,            -- UART1 send data
    uart1_rxd_i => '0',             -- UART1 receive data
    uart1_rts_o => open,            -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
    uart1_cts_i => '0',             -- hw flow control: UART1.TX allowed to transmit, low-active, optional
    -- SPI (available if IO_SPI_EN = true) --
    spi_sck_o   => open,            -- SPI serial clock
    spi_sdo_o   => open,            -- controller data out, peripheral data in
    spi_sdi_i   => '0',             -- controller data in, peripheral data out
    spi_csn_o   => open,            -- SPI CS
    -- TWI (available if IO_TWI_EN = true) --
    twi_sda_io  => open,            -- twi serial data line
    twi_scl_io  => open,            -- twi serial clock line
    -- PWM (available if IO_PWM_NUM_CH > 0) --
    pwm_o       => open,            -- pwm channels
    -- Custom Functions Subsystem IO --
    cfs_in_i    => (others => '0'), -- custom inputs
    cfs_out_o   => open,            -- custom outputs
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
    neoled_o    => open,            -- async serial data line
    -- System time --
    mtime_i     => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
    mtime_o     => mtime,            -- current system time from int. MTIME (if IO_MTIME_EN = true)
    -- Interrupts --
    nm_irq_i    => '0',             -- non-maskable interrupt
    mtime_irq_i => '0',             -- machine timer interrupt, available if IO_MTIME_EN = false
    msw_irq_i   => '0',             -- machine software interrupt
    mext_irq_i  => '0' --dummy_irq,             -- machine external interrupt
    );

  wb_iconn : component wb_interconnect
    generic map ( ADDR0 => led_addr,
                  ADDR1 => motor1_addr,
                  ADDR2 => motor2_addr,
                  ADDR3 => sensor1_addr,
                  ADDR4 => sensor2_addr,
                  ADDR5 => sensor3_addr,
                  ADDR6 => sensor4_addr,
                  ADDR7 => sensor5_addr )
    port map ( D_OUT => wb_dat_i,
               D_IN0 => wb_leds_d_o,
               D_IN1 => wb_motor1_d_o,
               D_IN2 => wb_motor2_d_o,
               D_IN3 => wb_sensor1_o,
               D_IN4 => wb_sensor2_o,
               D_IN5 => wb_sensor3_o,
               D_IN6 => wb_sensor4_o,
               D_IN7 => wb_sensor5_o,
              
               ACK_OUT => wb_ack_i,
               ACK_IN0 => wb_leds_ack_o,
               ACK_IN1 => wb_motor1_ack_o,
               ACK_IN2 => wb_motor2_ack_o,
               ACK_IN3 => wb_sensor1_ack_o,
               ACK_IN4 => wb_sensor2_ack_o,    
               ACK_IN5 => wb_sensor3_ack_o,
               ACK_IN6 => wb_sensor4_ack_o,
               ACK_IN7 => wb_sensor5_ack_o,
          
               ADDR_IN => wb_adr_o );
  
  wb_leds : component wb_slave_node
    generic map( ADDR => led_addr )
    port map( RST_I => rstn_i,
              CLK_I => clk_i,
              WE_I => wb_we_o,
              STB_I => wb_stb_o,
              CYC_I => wb_cyc_o,
              ACK_O => wb_leds_ack_o,
              SEL_I => wb_sel_o,
              ADDR_I => wb_adr_o,
              D_I => wb_dat_o,
              D_O => wb_leds_d_o,
              REG_O => reg_leds,
              REG_I => reg_leds );

  wb_mctrl1 : entity work.motor_controler(motor_controler_rtl)
    generic map( ADDR => motor1_addr )
    port map ( RST_I => rstn_i,
               CLK_I => clk_i,
               D_I => wb_dat_o,
               D_O => wb_motor1_d_o,
               ADDR_I => wb_adr_o,
               ACK_O => wb_motor1_ack_o,
               STB_I => wb_stb_o,
               WE_I => wb_we_o,
               SEL_I => wb_sel_o,
               CYC_I => wb_cyc_o,
               ENCODER_AB_I => encoder_ab1_i,
               PWM_O => motor1_pwm_o,
               DIR_O => motor1_dir_o,
               INT_O => motor1_irq_o);
  
  wb_mctrl2 : entity work.motor_controler(motor_controler_rtl)
    generic map( ADDR => motor2_addr )
    port map ( RST_I => rstn_i,
               CLK_I => clk_i,
               D_I => wb_dat_o,
               D_O => wb_motor2_d_o,
               ADDR_I => wb_adr_o,
               ACK_O => wb_motor2_ack_o,
               STB_I => wb_stb_o,
               WE_I => wb_we_o,
               SEL_I => wb_sel_o,
               CYC_I => wb_cyc_o,
               ENCODER_AB_I => encoder_ab2_i,
               PWM_O => motor2_pwm_o,
               DIR_O => motor2_dir_o,
               INT_O => motor2_irq_o);
  s_mux : entity work.sensor_mux
     generic map ( ADDR_S1 => sensor1_addr,
                   ADDR_S2 => sensor2_addr,
                   ADDR_S3 => sensor3_addr,
                   ADDR_S4 => sensor4_addr,
                   ADDR_S5 => sensor5_addr )
    port map ( RST_I => rstn_i,    
               CLK_I => clk_i,
               D_O1 => wb_sensor1_o,
               ACK_O1 => wb_sensor1_ack_o,
               D_O2 => wb_sensor2_o,
               ACK_O2 => wb_sensor2_ack_o,
               D_O3 => wb_sensor3_o,
               ACK_O3 => wb_sensor3_ack_o,
               D_O4 => wb_sensor4_o,
               ACK_O4 => wb_sensor4_ack_o,
               D_O5 => wb_sensor5_o,
               ACK_O5 => wb_sensor5_ack_o,
               D_I => wb_dat_o,
               ADDR_I => wb_adr_o,
               STB_I => wb_stb_o,
               WE_I => wb_we_o,
               SEL_I => wb_sel_o,
               CYC_I => wb_cyc_o,
               INT_O => sensor_mux_irq_o,
               vauxp15 => vauxp15,
               vauxn15 => vauxn15,
               vauxp7 => vauxp7,
               vauxn7 => vauxn7,
               vauxp4 => vauxp4,
               vauxn4 => vauxn4,
               vauxp5 => vauxp5,
               vauxn5 => vauxn5,
               vauxp6 => vauxp6,
               vauxn6 => vauxn6,
               IR_LED_MUX_O => IR_LED_MUX_O );
  rgb_led_dimmer : process (clk_i)
    variable pwm_counter : integer range 0 to 65535 := 0;
  begin
    if rising_edge(clk_i) then
      if pwm_counter < 65535 then
        pwm_counter := pwm_counter + 1;
      else
        pwm_counter := 0;
      end if;
      if pwm_counter < 65535/8 then
        rgb_led_pwm <= not rgb_led_pwm;
      end if;
    end if;
    
  end process rgb_led_dimmer;
  
  -- outputs --
  --rled_o <= reg_leds(15 downto 12) when rgb_led_pwm = '1' else (others => '0');
  --gled_o <= reg_leds(11 downto 8) when rgb_led_pwm = '1' else (others => '0');
  --bled_o <= reg_leds(7 downto 4) when rgb_led_pwm = '1' else (others => '0');
  --led_o(3 downto 0) <= reg_leds(3 downto 0);

  rled_o <= mtime (63 downto 60);
  gled_o <= mtime (59 downto 56);
  bled_o <= mtime (23 downto 20);
  led_o <= gpio_out(3 downto 0);
 

end architecture;

Oh and one more thing, I have modified `-march' variable in the makefile.

[stnolting]

Hmm, strange...

What version of the NEORV32 are you using? I have just tested the freeRTOS blink example using the current repo version and it works as expected:

Awaiting neorv32_exe.bin... OK
CMD:> e
Booting...

FreeRTOS V10.4.1 on NEORV32 Demo

Blink
Blink
Blink
Blink
Blink
Blink

Your processor configuration seems fine. But you should tie uart0_cts_i to 0 since "clear to send" is low-active (just in case). Also you should set ON_CHIP_DEBUGGER_EN to false if you are not using the OCD (which you are not since the JTAG port is not used).

Have you modified any of the constants in the processor's VHDL package? What executable size do you get when compiling the freeRTOS default (=blinky) example?

[stnolting]

This is my executable for the processor:
neorv32_exe.zip

It requires 32kB IMEM and 16kB DMEM so it should run on your setup.

[jaaaaaaaaan]

Your executable worked so it appears that I messed up something with my toolchain setup, I've downloaded your precompiled one and I was able to compile and run this demo without any problems. I wonder where I made my mistake when compiling the toolchain...
This way or another I owe you next one, thanks!

[stnolting]

Maybe it is an extension configuration problem.
Please run neorv32/sw/example/blink_led$ make check using your toolchain. This is the output when using the prebuild toolchain:

---------------- Check: riscv32-unknown-elf-gcc ----------------
Using built-in specs.
COLLECT_GCC=riscv32-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/opt/riscv32i/bin/../libexec/gcc/riscv32-unknown-elf/10.2.0/lto-wrapper
Target: riscv32-unknown-elf
Configured with: /home/stnolting/tmp/riscv-gnu-toolchain/riscv-gcc/configure --target=riscv32-unknown-elf --prefix=/tmp/riscv --disable-shared --disable-threads --enable-languages=c,c++ --with-system-zlib --enable-tls --with-newlib --with-sysroot=/tmp/riscv/riscv32-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=.././riscv-gcc --disable-multilib --with-abi=ilp32 --with-arch=rv32i --with-tune=rocket 'CFLAGS_FOR_TARGET=-Os   -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-Os   -mcmodel=medlow'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 10.2.0 (GCC)

The most important flags when compiling the toolchain from scratch are: --with-newlib --with-abi=ilp32 --with-arch=rv32i. This will generate a plain rv32i toolchain (RISC-V ISA extensions are supported anyway).