Potential Modification to Architecture Diagram

[DS-567]

Hey Stephan,

The documentation for neorv32 is amazing - never seen anything like it before. Also the HDL source code is also great :)

This is just a very minor suggestion that I am interested in:

For a paper I am including this architectural diagram of the CPU and I am discussing the instruction register and instruction decoding logic as well as the program counter. The program counter is shown within the execute engine but the other two are not. Obviously I can add this in myself but it would be more creditable if it is actually done that way in the documentation.

I am not sure if this will benefit anyone else, but it might be useful to include. I have shown a modified image below.

[stnolting]

The documentation for neorv32 is amazing - never seen anything like it before. Also the HDL source code is also great :)

Thank you very much! :)

This is just a very minor suggestion that I am interested in:

The current CPU diagram is really not good... 🙈 It's too detailed for a rough block diagram, but too many details are missing for a detailed description. Furthermore, some things are simply outdated.

I started drawing a new (hopefully better) one some time ago, but so far it's nothing more than a rough sketch. I'll try to make something useful out of it this weekend.

For a paper I am including this architectural diagram of the CPU and I am discussing the instruction register and instruction decoding logic as well as the program counter.

That sounds great! Could you give some more details? 😉

[DS-567]

The current CPU diagram is really not good... 🙈 It's too detailed for a rough block diagram, but too many details are missing for a detailed description. Furthermore, some things are simply outdated.

I actually like that CPU diagram :) Think its detailed enough for a high level overview and contains most of the key parts of the architecture. Maybe another more detailed diagram can be created in the documentation.

I'll try to make something useful out of it this weekend.

Thanks, no rush by the way.

That sounds great! Could you give some more details? 😉

Ah its nothing to complex, just a basic overview of the execute engine. I can drop you an email with more details if you're interested. I have an AI design working on Neorv32 so will do a show and tell on here soon hopefully when it is presented.

[stnolting]

Maybe another more detailed diagram can be created in the documentation.

Absolutely! I am planning to rework the CPU architecture diagram and also to add a more illustrative diagram showing the layout/interface of the CPU co-processors.

Thanks, no rush by the way.

I am still working on this... I already have a draft sketch on my old-school analog notepad - now I "just" need to make a digital version 😉

I can drop you an email with more details if you're interested. I have an AI design working on Neorv32 so will do a show and tell on here soon hopefully when it is presented.

So its still non-disclosed? Anyway, that would be very nice!