Suggestions, guidelines or known issues about implementing NEORV32 on silicon (Cadence, 28 nm)

[valeriopagliarino]

Hello,
thanks to this amazing community for this great project. I am considering the implementation of the Neorv32 core on a 28 nm technology for an academic project, part of my PhD. I see plenty of information about how to run the core on FPGA, but far less material is available when considering the silicon workflow (Cadence). Are there any suggestions, guidelines or known issues I should be aware of, before attempting this implementation? The VHDL sources seem to be fully platform-independent and this is a good starting point. I have some doubts about how to properly infer the memories.
Thank you very much in advance,
Valerio

[stnolting]

thanks to this amazing community for this great project.

Thank you on behalf of the entire community! 😉

I am considering the implementation of the Neorv32 core on a 28 nm technology for an academic project, part of my PhD.

That sounds great! Can you give some more details?

Are there any suggestions, guidelines or known issues I should be aware of, before attempting this implementation? The VHDL sources seem to be fully platform-independent and this is a good starting point.

Very good questions... 😅 In general, HDL can be synthesized for any technology (e.g. ASIC or FPGA). But of course there are a lots and lots of constraints. NEORV32 is written in technology-agnostic VHDL and I have already synthesized and at least simulated the core myself for ASIC technologies (also using Cadence tools). So at least in theory, this should not be a problem.

I have some doubts about how to properly infer the memories.

This highly depends on your PDK , the different primitives it offers and the availability of a RAM compiler. Of course you can try to built the entire code as-is from standard cells, but this will be large, slow and energy hungry.

For example, I have re-implemented the processor-internal data and instruction memories (DMEM and IMEM) using cascaded 512*8-bit RAM primitives.

[jannotari]

Hello,
I am currently working on my Master Thesis on doing an ASIC implementation of the NEORV32 for educational purposes. Till now I only used the NEORV32 on FPGA for testing and analyzing it in a previous semester project. As @valeriopagliarino already mentioned, the documentation and the HDL of the NEORV32 are really great and I was amazed on how good it was when I was working on it before.
@stnolting Have you done any other adjustments for the ASIC simulation of the core, apart from re-implementing the DMEM and IMEM? Are the results and the adaptions made for the simulations accessible on the git repository?
I am happy to hear that I am not the only one working on such an ASIC implementation and I am looking forward to contribute my little part for this community!
Thank you very much in advance for any help and for providing such a great project,
Jan

[stnolting]

@valeriopagliarino

Sorry for the late reply 🙈

I work in a research group in Torino (Italy) where we design sensor readout ASICs for large high-energy physics experiments and related applications. I plan to start the development of a mixed-signal data acquisition chip, embedding a programmable SoC for digital signal processing.

That sounds really interesting! Could you tell us some more about those experiments? Somehow I am just thinking about CERN and that large collider ring 😅

While comparing the available open-source RISC-V cores, I've been impressed by the quality of the NEORV32 project and its documentation.

Thank your very much!

Our PDK should have a SRAM IP core suitable for the implementation of DMEM and IMEM, but I need to write proper glue logic.

That glue logic should not bee too complicated to implement. The processor's bus interface is quite "user friendly" supporting arbitrary read/write latencies.

I opened this discussion to understand whether any previous work in this direction has been done and I am very happy to hear that you have been able to synthesize and simulate the core successfully.

I am also working with ASIC setups (open-source and proprietary). Hopefully, I can share some of my more in-depth findings here.

At this point, I will start the porting, the simulation and the synthesis in the next months and if any more specific questions would emerge, I will kindly post them here. I will eventually report here any result that can be useful to this amazing community for implementing the NEORV32 on silicon. Thank you!

That would be very great!

If you have any questions, please do not hesitate to ask them here.

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@jannotari

I am currently working on my Master Thesis on doing an ASIC implementation of the NEORV32 for educational purposes.

That's cool! Are you setting up some kind of "lab for students"?!

As @valeriopagliarino already mentioned, the documentation and the HDL of the NEORV32 are really great and I was amazed on how good it was when I was working on it before.

Thanks again! :)

Have you done any other adjustments for the ASIC simulation of the core, apart from re-implementing the DMEM and IMEM?

Yes, but nothing to spectacular. Replacing IMEM, DMEM and the boot ROM is the obvious part. I've also been experimenting with automatic clock-gating (also replacing the deafult clock gating switch). Furthermore, I've added an "IO ring" that register all incoming/outgoing signals (maybe adding another scan chain to do boundary-scan-like things). Replacing the multiplier with some specific IP is also on my agenda.

Are the results and the adaptions made for the simulations accessible on the git repository?

Unfortunately, I cannot make ASIC-specific code public here - at least not at the moment. But I'll try to commit all core modifications targeting an ASIC-optimized setup.

[valeriopagliarino]

@stnolting Yes! The team actually designs ASICs and sensors targeting some big experiments running at the LHC, at CERN. But not only, also other experiments (neutrino physics etc.) in USA and other countries! There are projects about ASICs for medical applications of accelerated particles too. It is a public research institution, not a company. Currently, it is too early to disclose specific details about the project where I would like to embed the NEORV32, but in case of successful implementation, I will keep the community posted and obviously properly acknowledged for the use of the core also in our publications. I will report any issue or result that could be useful to the community. Thank you!

[jannotari]

That's cool! Are you setting up some kind of "lab for students"?!

@stnolting On FPGA the NEORV32 will already be used in the labs of a SOC course by one of my professors next semester. Now when everything will work out with the ASIC implementation, it will maybe even be used in other courses or other context as a physical processor. Furthermore this will also help to establish a working ASIC design flow in our department that can be used for other future ASIC projects.

Unfortunately, I cannot make ASIC-specific code public here - at least not at the moment. But I'll try to commit all core modifications targeting an ASIC-optimized setup.

Are you planning to commit these adaptions in the near future? As an ASIC novice it would be great to have some base to start on. Thanks again :)

[stnolting]

That sounds really cool!! Are any resources publicly available? 😉

Are you planning to commit these adaptions in the near future?

Absolutely! At least everything that is related to the "base core" in its current state (so without any application-specific stuff and of course without any vendor- or technology-specific IPs).