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#toc{border:0!important;text-align:left!important;padding:0!important;margin:0!important} +body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-break-before:always} +.listingblock code[data-lang]::before{display:block} +#footer{padding:0 .9375em} +.hide-on-print{display:none!important} +.print-only{display:block!important} +.hide-for-print{display:none!important} +.show-for-print{display:inherit!important}} +@media amzn-kf8,print{#header>h1:first-child{margin-top:1.25rem} +.sect1{padding:0!important} +.sect1+.sect1{border:0} +#footer{background:none} +#footer-text{color:rgba(0,0,0,.6);font-size:.9em}} +@media amzn-kf8{#header,#content,#footnotes,#footer{padding:0}} +</style> +<link rel="stylesheet" href="https://cdnjs.cloudflare.com/ajax/libs/font-awesome/4.7.0/css/font-awesome.min.css"> +</head> +<body class="book toc2 toc-left"> +<div id="header"> +<h1>The NEORV32 RISC-V Processor - Datasheet</h1> +<div class="details"> +<span id="revnumber">version v1.10.5-r58-gf1069d11</span> +</div> +<div id="toc" class="toc2"> +<div id="toctitle">Table of Contents</div> +<ul class="sectlevel1"> +<li><a href="#_overview">1. Overview</a> +<ul class="sectlevel2"> +<li><a href="#_rationale">1.1. Rationale</a></li> +<li><a href="#_project_key_features">1.2. Project Key Features</a></li> +<li><a href="#_project_folder_structure">1.3. Project Folder Structure</a></li> +<li><a href="#_vhdl_file_hierarchy">1.4. VHDL File Hierarchy</a> +<ul class="sectlevel3"> +<li><a href="#_file_list_files">1.4.1. File-List Files</a></li> +</ul> +</li> +<li><a href="#_vhdl_coding_style">1.5. VHDL Coding Style</a></li> +<li><a href="#_fpga_implementation_results">1.6. FPGA Implementation Results</a></li> +<li><a href="#_cpu_performance">1.7. CPU Performance</a></li> +</ul> +</li> +<li><a href="#_neorv32_processor_soc">2. NEORV32 Processor (SoC)</a> +<ul class="sectlevel2"> +<li><a href="#_processor_top_entity_signals">2.1. Processor Top Entity - Signals</a></li> +<li><a href="#_processor_top_entity_generics">2.2. Processor Top Entity - Generics</a></li> +<li><a href="#_processor_clocking">2.3. Processor Clocking</a> +<ul class="sectlevel3"> +<li><a href="#_clock_gating">2.3.1. Clock Gating</a></li> +<li><a href="#_peripheral_clocks">2.3.2. Peripheral Clocks</a></li> +</ul> +</li> +<li><a href="#_processor_reset">2.4. Processor Reset</a></li> +<li><a href="#_processor_interrupts">2.5. Processor Interrupts</a> +<ul class="sectlevel3"> +<li><a href="#_risc_v_standard_interrupts">2.5.1. RISC-V Standard Interrupts</a></li> +<li><a href="#_neorv32_specific_fast_interrupt_requests">2.5.2. NEORV32-Specific Fast Interrupt Requests</a></li> +</ul> +</li> +<li><a href="#_address_space">2.6. Address Space</a> +<ul class="sectlevel3"> +<li><a href="#_bus_system">2.6.1. Bus System</a></li> +<li><a href="#_bus_gateway">2.6.2. Bus Gateway</a></li> +<li><a href="#_reservation_set_controller">2.6.3. Reservation Set Controller</a></li> +<li><a href="#_io_switch">2.6.4. IO Switch</a></li> +<li><a href="#_boot_configuration">2.6.5. Boot Configuration</a></li> +</ul> +</li> +<li><a href="#_processor_internal_modules">2.7. Processor-Internal Modules</a> +<ul class="sectlevel3"> +<li><a href="#_instruction_memory_imem">2.7.1. Instruction Memory (IMEM)</a></li> +<li><a href="#_data_memory_dmem">2.7.2. Data Memory (DMEM)</a></li> +<li><a href="#_bootloader_rom_bootrom">2.7.3. Bootloader ROM (BOOTROM)</a></li> +<li><a href="#_processor_internal_instruction_cache_icache">2.7.4. Processor-Internal Instruction Cache (iCACHE)</a></li> +<li><a href="#_processor_internal_data_cache_dcache">2.7.5. Processor-Internal Data Cache (dCACHE)</a></li> +<li><a href="#_direct_memory_access_controller_dma">2.7.6. Direct Memory Access Controller (DMA)</a></li> +<li><a href="#_processor_external_bus_interface_xbus">2.7.7. Processor-External Bus Interface (XBUS)</a></li> +<li><a href="#_stream_link_interface_slink">2.7.8. Stream Link Interface (SLINK)</a></li> +<li><a href="#_general_purpose_input_and_output_port_gpio">2.7.9. General Purpose Input and Output Port (GPIO)</a></li> +<li><a href="#_cyclic_redundancy_check_crc">2.7.10. Cyclic Redundancy Check (CRC)</a></li> +<li><a href="#_watchdog_timer_wdt">2.7.11. Watchdog Timer (WDT)</a></li> +<li><a href="#_machine_system_timer_mtime">2.7.12. Machine System Timer (MTIME)</a></li> +<li><a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">2.7.13. Primary Universal Asynchronous Receiver and Transmitter (UART0)</a></li> +<li><a href="#_secondary_universal_asynchronous_receiver_and_transmitter_uart1">2.7.14. Secondary Universal Asynchronous Receiver and Transmitter (UART1)</a></li> +<li><a href="#_serial_peripheral_interface_controller_spi">2.7.15. Serial Peripheral Interface Controller (SPI)</a></li> +<li><a href="#_serial_data_interface_controller_sdi">2.7.16. Serial Data Interface Controller (SDI)</a></li> +<li><a href="#_two_wire_serial_interface_controller_twi">2.7.17. Two-Wire Serial Interface Controller (TWI)</a></li> +<li><a href="#_one_wire_serial_interface_controller_onewire">2.7.18. One-Wire Serial Interface Controller (ONEWIRE)</a></li> +<li><a href="#_pulse_width_modulation_controller_pwm">2.7.19. Pulse-Width Modulation Controller (PWM)</a></li> +<li><a href="#_true_random_number_generator_trng">2.7.20. True Random-Number Generator (TRNG)</a></li> +<li><a href="#_custom_functions_subsystem_cfs">2.7.21. Custom Functions Subsystem (CFS)</a></li> +<li><a href="#_smart_led_interface_neoled">2.7.22. Smart LED Interface (NEOLED)</a></li> +<li><a href="#_external_interrupt_controller_xirq">2.7.23. External Interrupt Controller (XIRQ)</a></li> +<li><a href="#_general_purpose_timer_gptmr">2.7.24. General Purpose Timer (GPTMR)</a></li> +<li><a href="#_execute_in_place_module_xip">2.7.25. Execute In Place Module (XIP)</a></li> +<li><a href="#_system_configuration_information_memory_sysinfo">2.7.26. System Configuration Information Memory (SYSINFO)</a></li> +</ul> +</li> +</ul> +</li> +<li><a href="#_neorv32_central_processing_unit_cpu">3. NEORV32 Central Processing Unit (CPU)</a> +<ul class="sectlevel2"> +<li><a href="#_risc_v_compatibility">3.1. RISC-V Compatibility</a></li> +<li><a href="#_cpu_top_entity_signals">3.2. CPU Top Entity - Signals</a></li> +<li><a href="#_cpu_top_entity_generics">3.3. CPU Top Entity - Generics</a></li> +<li><a href="#_architecture">3.4. Architecture</a> +<ul class="sectlevel3"> +<li><a href="#_cpu_register_file">3.4.1. CPU Register File</a></li> +<li><a href="#_cpu_arithmetic_logic_unit">3.4.2. CPU Arithmetic Logic Unit</a></li> +<li><a href="#_cpu_bus_unit">3.4.3. CPU Bus Unit</a></li> +<li><a href="#_cpu_control_unit">3.4.4. CPU Control Unit</a></li> +<li><a href="#_sleep_mode">3.4.5. Sleep Mode</a></li> +<li><a href="#_full_virtualization">3.4.6. Full Virtualization</a></li> +</ul> +</li> +<li><a href="#_bus_interface">3.5. Bus Interface</a> +<ul class="sectlevel3"> +<li><a href="#_bus_interface_protocol">3.5.1. Bus Interface Protocol</a></li> +<li><a href="#_atomic_accesses">3.5.2. Atomic Accesses</a></li> +</ul> +</li> +<li><a href="#_instruction_sets_and_extensions">3.6. Instruction Sets and Extensions</a> +<ul class="sectlevel3"> +<li><a href="#_b_isa_extension">3.6.1. <code>B</code> ISA Extension</a></li> +<li><a href="#_c_isa_extension">3.6.2. <code>C</code> ISA Extension</a></li> +<li><a href="#_e_isa_extension">3.6.3. <code>E</code> ISA Extension</a></li> +<li><a href="#_i_isa_extension">3.6.4. <code>I</code> ISA Extension</a></li> +<li><a href="#_m_isa_extension">3.6.5. <code>M</code> ISA Extension</a></li> +<li><a href="#_u_isa_extension">3.6.6. <code>U</code> ISA Extension</a></li> +<li><a href="#_x_isa_extension">3.6.7. <code>X</code> ISA Extension</a></li> +<li><a href="#_zalrsc_isa_extension">3.6.8. <code>Zalrsc</code> ISA Extension</a></li> +<li><a href="#_zifencei_isa_extension">3.6.9. <code>Zifencei</code> ISA Extension</a></li> +<li><a href="#_zfinx_isa_extension">3.6.10. <code>Zfinx</code> ISA Extension</a></li> +<li><a href="#_zicntr_isa_extension">3.6.11. <code>Zicntr</code> ISA Extension</a></li> +<li><a href="#_zicond_isa_extension">3.6.12. <code>Zicond</code> ISA Extension</a></li> +<li><a href="#_zicsr_isa_extension">3.6.13. <code>Zicsr</code> ISA Extension</a></li> +<li><a href="#_zihpm_isa_extension">3.6.14. <code>Zihpm</code> ISA Extension</a></li> +<li><a href="#_zba_isa_extension">3.6.15. <code>Zba</code> ISA Extension</a></li> +<li><a href="#_zbb_isa_extension">3.6.16. <code>Zbb</code> ISA Extension</a></li> +<li><a href="#_zbs_isa_extension">3.6.17. <code>Zbs</code> ISA Extension</a></li> +<li><a href="#_zbkb_isa_extension">3.6.18. <code>Zbkb</code> ISA Extension</a></li> +<li><a href="#_zbkc_isa_extension">3.6.19. <code>Zbkc</code> ISA Extension</a></li> +<li><a href="#_zbkx_isa_extension">3.6.20. <code>Zbkx</code> ISA Extension</a></li> +<li><a href="#_zkn_isa_extension">3.6.21. <code>Zkn</code> ISA Extension</a></li> +<li><a href="#_zknd_isa_extension">3.6.22. <code>Zknd</code> ISA Extension</a></li> +<li><a href="#_zkne_isa_extension">3.6.23. <code>Zkne</code> ISA Extension</a></li> +<li><a href="#_zknh_isa_extension">3.6.24. <code>Zknh</code> ISA Extension</a></li> +<li><a href="#_zks_isa_extension">3.6.25. <code>Zks</code> ISA Extension</a></li> +<li><a href="#_zksed_isa_extension">3.6.26. <code>Zksed</code> ISA Extension</a></li> +<li><a href="#_zksh_isa_extension">3.6.27. <code>Zksh</code> ISA Extension</a></li> +<li><a href="#_zkt_isa_extension">3.6.28. <code>Zkt</code> ISA Extension</a></li> +<li><a href="#_zmmul_isa_extension">3.6.29. <code>Zmmul</code> - ISA Extension</a></li> +<li><a href="#_zxcfu_isa_extension">3.6.30. <code>Zxcfu</code> ISA Extension</a></li> +<li><a href="#_smpmp_isa_extension">3.6.31. <code>Smpmp</code> ISA Extension</a></li> +<li><a href="#_sdext_isa_extension">3.6.32. <code>Sdext</code> ISA Extension</a></li> +<li><a href="#_sdtrig_isa_extension">3.6.33. <code>Sdtrig</code> ISA Extension</a></li> +</ul> +</li> +<li><a href="#_custom_functions_unit_cfu">3.7. Custom Functions Unit (CFU)</a> +<ul class="sectlevel3"> +<li><a href="#_cfu_instruction_formats">3.7.1. CFU Instruction Formats</a></li> +<li><a href="#_using_custom_instructions_in_software">3.7.2. Using Custom Instructions in Software</a></li> +<li><a href="#_cfu_control_and_status_registers_cfu_csrs">3.7.3. CFU Control and Status Registers (CFU-CSRs)</a></li> +<li><a href="#_custom_instructions_hardware">3.7.4. Custom Instructions Hardware</a></li> +</ul> +</li> +<li><a href="#_control_and_status_registers_csrs">3.8. Control and Status Registers (CSRs)</a> +<ul class="sectlevel3"> +<li><a href="#_floating_point_csrs">3.8.1. Floating-Point CSRs</a></li> +<li><a href="#_machine_trap_setup_csrs">3.8.2. Machine Trap Setup CSRs</a></li> +<li><a href="#_machine_trap_handling_csrs">3.8.3. Machine Trap Handling CSRs</a></li> +<li><a href="#_machine_configuration_csrs">3.8.4. Machine Configuration CSRs</a></li> +<li><a href="#_machine_physical_memory_protection_csrs">3.8.5. Machine Physical Memory Protection CSRs</a></li> +<li><a href="#_custom_functions_unit_cfu_csrs">3.8.6. Custom Functions Unit (CFU) CSRs</a></li> +<li><a href="#_machine_counter_and_timer_csrs">3.8.7. (Machine) Counter and Timer CSRs</a></li> +<li><a href="#_hardware_performance_monitors_hpm_csrs">3.8.8. Hardware Performance Monitors (HPM) CSRs</a></li> +<li><a href="#_machine_counter_setup_csrs">3.8.9. Machine Counter Setup CSRs</a></li> +<li><a href="#_machine_information_csrs">3.8.10. Machine Information CSRs</a></li> +<li><a href="#_neorv32_specific_csrs">3.8.11. NEORV32-Specific CSRs</a></li> +</ul> +</li> +<li><a href="#_traps_exceptions_and_interrupts">3.9. Traps, Exceptions and Interrupts</a> +<ul class="sectlevel3"> +<li><a href="#_memory_access_exceptions">3.9.1. Memory Access Exceptions</a></li> +<li><a href="#_custom_fast_interrupt_request_lines">3.9.2. Custom Fast Interrupt Request Lines</a></li> +<li><a href="#_neorv32_trap_listing">3.9.3. NEORV32 Trap Listing</a></li> +</ul> +</li> +</ul> +</li> +<li><a href="#_software_framework">4. Software Framework</a> +<ul class="sectlevel2"> +<li><a href="#_compiler_toolchain">4.1. Compiler Toolchain</a></li> +<li><a href="#_core_libraries">4.2. Core Libraries</a></li> +<li><a href="#_application_makefile">4.3. Application Makefile</a> +<ul class="sectlevel3"> +<li><a href="#_makefile_targets">4.3.1. Makefile Targets</a></li> +<li><a href="#_makefile_configuration">4.3.2. Makefile Configuration</a></li> +<li><a href="#_default_compiler_flags">4.3.3. Default Compiler Flags</a></li> +<li><a href="#_custom_compiler_flags">4.3.4. Custom (Compiler) Flags</a></li> +</ul> +</li> +<li><a href="#_executable_image_format">4.4. Executable Image Format</a> +<ul class="sectlevel3"> +<li><a href="#_linker_script">4.4.1. Linker Script</a></li> +<li><a href="#_ram_layout">4.4.2. RAM Layout</a></li> +<li><a href="#_c_standard_library">4.4.3. C Standard Library</a></li> +<li><a href="#_executable_image_generator">4.4.4. Executable Image Generator</a></li> +<li><a href="#_start_up_code_crt0">4.4.5. Start-Up Code (crt0)</a></li> +</ul> +</li> +<li><a href="#_bootloader">4.5. Bootloader</a> +<ul class="sectlevel3"> +<li><a href="#_bootloader_soccpu_requirements">4.5.1. Bootloader SoC/CPU Requirements</a></li> +<li><a href="#_bootloader_flash_requirements">4.5.2. Bootloader Flash Requirements</a></li> +<li><a href="#_bootloader_console">4.5.3. Bootloader Console</a></li> +<li><a href="#_auto_boot_sequence">4.5.4. Auto Boot Sequence</a></li> +<li><a href="#_bootloader_error_codes">4.5.5. Bootloader Error Codes</a></li> +</ul> +</li> +<li><a href="#_neorv32_runtime_environment">4.6. NEORV32 Runtime Environment</a> +<ul class="sectlevel3"> +<li><a href="#_rte_operation">4.6.1. RTE Operation</a></li> +<li><a href="#_using_the_rte">4.6.2. Using the RTE</a></li> +<li><a href="#_default_rte_trap_handlers">4.6.3. Default RTE Trap Handlers</a></li> +<li><a href="#_application_context_handling">4.6.4. Application Context Handling</a></li> +</ul> +</li> +</ul> +</li> +<li><a href="#_on_chip_debugger_ocd">5. On-Chip Debugger (OCD)</a> +<ul class="sectlevel2"> +<li><a href="#_debug_transport_module_dtm">5.1. Debug Transport Module (DTM)</a></li> +<li><a href="#_debug_module_dm">5.2. Debug Module (DM)</a> +<ul class="sectlevel3"> +<li><a href="#_dm_registers">5.2.1. DM Registers</a></li> +<li><a href="#_dm_cpu_access">5.2.2. DM CPU Access</a></li> +</ul> +</li> +<li><a href="#_cpu_debug_mode">5.3. CPU Debug Mode</a> +<ul class="sectlevel3"> +<li><a href="#_cpu_debug_mode_csrs">5.3.1. CPU Debug Mode CSRs</a></li> +</ul> +</li> +<li><a href="#_trigger_module">5.4. Trigger Module</a> +<ul class="sectlevel3"> +<li><a href="#_trigger_module_csrs">5.4.1. Trigger Module CSRs</a></li> +</ul> +</li> +</ul> +</li> +<li><a href="#_legal">6. Legal</a> +<ul class="sectlevel2"> +<li><a href="#_about">About</a></li> +<li><a href="#_license">License</a></li> +<li><a href="#_proprietary_notice">Proprietary Notice</a></li> +<li><a href="#_disclaimer">Disclaimer</a></li> +<li><a href="#_limitation_of_liability_for_external_links">Limitation of Liability for External Links</a></li> +<li><a href="#_citing">Citing</a></li> +<li><a href="#_acknowledgments">Acknowledgments</a></li> +</ul> +</li> +</ul> +</div> +</div> +<div id="content"> +<div id="preamble"> +<div class="sectionbody"> +<div class="imageblock text-center"> +<div class="content"> +<a class="image" href="https://github.com/stnolting/neorv32"><img src="img/neorv32_logo.png" alt="neorv32 logo"></a> +</div> +</div> +<div class="imageblock text-center"> +<div class="content"> +<a class="image" href="https://riscv.org/"><img src="img/riscv_logo.png" alt="riscv logo" width="350"></a> +</div> +</div> +<div class="paragraph text-center"> +<p><a href="https://github.com/stnolting/neorv32"><span class="image"><img src="https://img.shields.io/badge/GitHub-stnolting%2Fneorv32-ffbd00?style=flat-square&amp;logo=github&amp;" alt="GitHub stnolting%2Fneorv32 ffbd00?style=flat square&amp;logo=github&amp;" title="homepage"></span></a> +<a href="https://github.com/stnolting/neorv32/blob/main/LICENSE"><span class="image"><img src="https://img.shields.io/github/license/stnolting/neorv32?longCache=true&amp;style=flat-square" alt="neorv32?longCache=true&amp;style=flat square" title="license"></span></a> +<a href="https://github.com/stnolting/neorv32/releases/tag/nightly"><span class="image"><img src="https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&amp;style=flat-square&amp;logo=asciidoctor" alt="data%20sheet PDF ffbd00?longCache=true&amp;style=flat square&amp;logo=asciidoctor" title="datasheet (pdf)"></span></a> +<a href="https://github.com/stnolting/neorv32/releases/tag/nightly"><span class="image"><img src="https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&amp;style=flat-square&amp;logo=asciidoctor" alt="user%20guide PDF ffbd00?longCache=true&amp;style=flat square&amp;logo=asciidoctor" title="userguide (pdf)"></span></a> +<a href="https://stnolting.github.io/neorv32/ug"><span class="image"><img src="https://img.shields.io/badge/-HTML-ffbd00?longCache=true&amp;style=flat-square" alt=" HTML ffbd00?longCache=true&amp;style=flat square" title="userguide (html)"></span></a> +<a href="https://stnolting.github.io/neorv32/sw/files.html"><span class="image"><img src="https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&amp;style=flat-square&amp;logo=Doxygen" alt="doxygen HTML ffbd00?longCache=true&amp;style=flat square&amp;logo=Doxygen" title="doxygen"></span></a><br> +<a href="https://github.com/stnolting/neorv32/releases"><span class="image"><img src="https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&amp;style=flat-square&amp;logo=GitHub" alt="neorv32?longCache=true&amp;style=flat square&amp;logo=GitHub" title="release"></span></a> +<a href="https://github.com/stnolting/neorv32/releases"><span class="image"><img src="https://img.shields.io/github/commits-since/stnolting/neorv32/latest?longCache=true&amp;style=flat-square&amp;logo=GitHub" alt="latest?longCache=true&amp;style=flat square&amp;logo=GitHub" title="release-commits"></span></a></p> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_overview">1. Overview</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 RISC-V Processor is an open-source RISC-V compatible processor system that is intended as +<strong>ready-to-go</strong> auxiliary processor within a larger SoC designs or as stand-alone custom / customizable +microcontroller.</p> +</div> +<div class="paragraph"> +<p>The system is highly configurable and provides optional common peripherals like embedded memories, +timers, serial interfaces, general purpose IO ports and an external bus interface to connect custom IP like +memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb +compatible on-chip debugger accessible via JTAG.</p> +</div> +<div class="paragraph"> +<p>Special focus is paid on <strong>execution safety</strong> to provide defined and predictable behavior at any time. +Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions +are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.</p> +</div> +<div class="paragraph"> +<p>The software framework of the processor comes with application makefiles, software libraries for all CPU +and processor features, a bootloader, a runtime environment and several example programs - including a port +of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as +default toolchain (<a href="https://github.com/stnolting/riscv-gcc-prebuilt">prebuilt toolchains are also provided</a>).</p> +</div> +<div class="paragraph"> +<p>Check out the processor&#8217;s <strong><a href="https://stnolting.github.io/neorv32/ug">online User Guide</a></strong> +that provides hands-on tutorials to get you started.</p> +</div> +<div class="paragraph"> +<p><strong>Structure</strong></p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="2"> +<li> +<p><a href="#_neorv32_processor_soc">NEORV32 Processor (SoC)</a></p> +</li> +<li> +<p><a href="#_neorv32_central_processing_unit_cpu">NEORV32 Central Processing Unit (CPU)</a></p> +</li> +<li> +<p><a href="#_software_framework">Software Framework</a></p> +</li> +<li> +<p><a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a></p> +</li> +<li> +<p><a href="#_legal">Legal</a></p> +</li> +</ol> +</div> +<div class="paragraph"> +<p><strong>Annotations Types</strong></p> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +Warning +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Important +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Note +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +Tip +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +<div class="sect2"> +<h3 id="_rationale">1.1. Rationale</h3> +<h4 id="_why_did_you_make_this" class="discrete">Why did you make this?</h4> +<div class="paragraph"> +<p>Processor and CPU architecture designs are fascinating things: they are the magic frontier where software meets hardware. +This project started as something like a <em>journey</em> into this magic realm to understand how things actually work +down on this very low level and evolved over time to a capable system on chip.</p> +</div> +<div class="paragraph"> +<p>But there is more: when I started to dive into the emerging RISC-V ecosystem I felt overwhelmed by the complexity. +As a beginner it is hard to get an overview - especially when you want to setup a minimal platform to tinker with&#8230;&#8203; +Which core to use? How to get the right toolchain? What features do I need? How does booting work? How do I +create an actual executable? How to get that into the hardware? How to customize things? <strong><em>Where to start???</em></strong></p> +</div> +<div class="paragraph"> +<p>This project aims to provide a <em>simple to understand</em> and <em>easy to use</em> yet <em>powerful</em> and <em>flexible</em> platform +that targets FPGA and RISC-V beginners as well as advanced users.</p> +</div> +<h4 id="_why_a_soft_core_processor" class="discrete">Why a <em>soft-core</em> processor?</h4> +<div class="paragraph"> +<p>As a matter of fact soft-core processors <em>cannot</em> compete with discrete (like FPGA hard-macro) processors in terms +of performance, energy efficiency and size. But they do fill a niche in FPGA design space: for example, soft-core +processors allow to implement the <em>control flow part</em> of certain applications (e.g. communication protocol handling) +using software like plain C. This provides high flexibility as software can be easily changed, re-compiled and +re-uploaded again.</p> +</div> +<div class="paragraph"> +<p>Furthermore, the concept of flexibility applies to all aspects of a soft-core processor. The user can add +<em>exactly</em> the features that are required by the application: additional memories, custom interfaces, specialized +co-processors and even user-defined instructions.</p> +</div> +<h4 id="_why_risc_v" class="discrete">Why RISC-V?</h4> +<div class="imageblock text-left"> +<div class="content"> +<img src="img/riscv_logo.png" alt="riscv logo" width="250"> +</div> +</div> +<div class="quoteblock"> +<blockquote> +<div class="paragraph"> +<p>RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.</p> +</div> +</blockquote> +<div class="attribution"> +&#8212; RISC-V International<br> +<cite>https://riscv.org/about/</cite> +</div> +</div> +<div class="paragraph"> +<p>Open-source is a great thing! +While open-source has already become quite popular in <em>software</em>, hardware-focused projects still need to catch up. +Admittedly, there has been quite a development, but mainly in terms of <em>platforms</em> and <em>applications</em> (so +schematics, PCBs, etc.). Although processors and CPUs are the heart of almost every digital system, having a true +open-source silicon is still a rarity. RISC-V aims to change that - and even it is <em>just one approach</em>, it helps paving +the road for future development.</p> +</div> +<div class="paragraph"> +<p>Furthermore, I highly appreciate the community aspect of RISC-V. The ISA and everything beyond is developed in direct +contact with the community: this includes businesses and professionals but also hobbyist, amateurs and people +that are just curious. Everyone can join discussions and contribute to RISC-V in their very own way.</p> +</div> +<div class="paragraph"> +<p>Finally, I really like the RISC-V ISA itself. It aims to be a clean, orthogonal and "intuitive" ISA that +resembles with the basic concepts of <em>RISC</em>: simple yet effective.</p> +</div> +<h4 id="_yet_another_risc_v_core_what_makes_it_special" class="discrete">Yet another RISC-V core? What makes it special?</h4> +<div class="paragraph"> +<p>The NEORV32 is not based on another RISC-V core. It was build entirely from ground up (just following the official +ISA specs). The project does not intend to replace certain RISC-V cores or +just beat existing ones like <a href="https://github.com/SpinalHDL/VexRiscv">VexRISC</a> in terms of performance or +<a href="https://github.com/olofk/serv">SERV</a> in terms of size. It was build having a different design goal in mind.</p> +</div> +<div class="paragraph"> +<p>The project aims to provide <em>another option</em> in the RISC-V / soft-core design space with a different performance +vs. size trade-off and a different focus: <em>embrace</em> concepts like documentation, platform-independence / portability, +RISC-V compatibility, <em>extensibility &amp; customization</em> and <em>ease of use</em> (see the <a href="#_project_key_features">Project Key Features</a> below).</p> +</div> +<div class="paragraph"> +<p>Furthermore, the NEORV32 pays special focus on <em>execution safety</em> using <a href="#_full_virtualization">Full Virtualization</a>. The CPU aims to +provide fall-backs for <em>everything that could go wrong</em>. This includes malformed instruction words, privilege escalations +and even memory accesses that are checked for address space holes and deterministic response times of memory-mapped +devices. Precise exceptions allow a defined and fully-synchronized state of the CPU at every time an in every situation.</p> +</div> +<h4 id="_a_multi_cycle_architecture" class="discrete">A multi-cycle architecture?!</h4> +<div class="paragraph"> +<p>Most mainstream CPUs out there are pipelined architectures to increase throughput. In contrast, most CPUs used for +teaching are single-cycle designs since they are probably the most easiest to understand. But what about the +multi-cycle architectures?</p> +</div> +<div class="paragraph"> +<p>In terms of energy, throughput, area and maximal clock frequency multi-cycle architectures are somewhere in between +single-cycle and fully-pipelined designs: they provide higher throughput and clock speed when compared to their +single-cycle counterparts while having less hardware complexity (= area) then a fully-pipelined designs. I decided to +use the multi-cycle approach because of the following reasons:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Multi-cycle architecture are quite small! There is no need for pipeline hazard detection and resolution logic +(e.g. forwarding). Furthermore, you can "re-use" parts of the core to do several tasks (e.g. the ALU is used for the +actual data processing, but also for address generation, branch condition check and branch target computation).</p> +</li> +<li> +<p>Single-cycle architectures require memories that can be read asynchronously - a thing that is not feasible to implement +in real world applications (i.e. FPGA block RAM is entirely synchronous). Furthermore, such design usually have a very +long critical path tremendously reducing maximal operating frequency.</p> +</li> +<li> +<p>Pipelined designs increase performance by having several instruction "in fly" at the same time. But this also means +there is some kind of "out-of-order" behavior: if an instruction at the end of the pipeline causes an exception +all the instructions in earlier stages have to be invalidated. Potential architecture state changes have to be made <em>undone</em> +requiring additional (exception-handling) logic. In a multi-cycle architecture this situation cannot occur because only a +single instruction is "in fly" at a time.</p> +</li> +<li> +<p>Having only a single instruction in fly does not only reduce hardware costs, it also simplifies +simulation/verification/debugging, state preservation/restoring during exceptions and extensibility (no need to care +about pipeline hazards) - but of course at the cost of reduced throughput.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>To counteract the loss of performance implied by a <em>pure</em> multi-cycle architecture, the NEORV32 CPU uses a <em>mixed</em> +approach: instruction fetch (front-end) and instruction execution (back-end) are de-coupled to operate independently +of each other. Data is interchanged via a queue building a simple 2-stage pipeline. Each "pipeline" stage in terms is +implemented as multi-cycle architecture to simplify the hardware and to provide <em>precise</em> state control (e.g. during +exceptions).</p> +</div> +<h4 id="_design_goals" class="discrete">Design Goals</h4> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>RISC-V-compliance and -compatibility</p> +</li> +<li> +<p>Functionality and features</p> +</li> +<li> +<p>Safety and security</p> +</li> +<li> +<p>Minimal area</p> +</li> +<li> +<p>Short critical paths, high operating clock</p> +</li> +<li> +<p>Low-power design</p> +</li> +<li> +<p>High overall performance</p> +</li> +<li> +<p>Simplicity / easy to understand</p> +</li> +</ol> +</div> +</div> +<div class="sect2"> +<h3 id="_project_key_features">1.2. Project Key Features</h3> +<div class="paragraph"> +<p><strong>Project</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>all-in-one package: <strong>CPU</strong> + <strong>SoC</strong> + <strong>Software Framework &amp; Tooling</strong></p> +</li> +<li> +<p>completely described in behavioral, platform-independent VHDL - no vendor- or technology-specific primitives, attributes, macros, libraries, etc. are used at all</p> +</li> +<li> +<p>all-Verilog "version" available (auto-generated by GHDL)</p> +</li> +<li> +<p>extensive configuration options for adapting the processor to the requirements of the application</p> +</li> +<li> +<p>highly extensible hardware - on CPU, SoC and system level</p> +</li> +<li> +<p>aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off</p> +</li> +<li> +<p>FPGA friendly (e.g. all internal memories can be mapped to block RAM - including the register file)</p> +</li> +<li> +<p>optimized for high clock frequencies to ease timing closure and integration</p> +</li> +<li> +<p>from zero to <em>"hello world!"</em> - completely open source and documented</p> +</li> +<li> +<p>easy to use even for FPGA/RISC-V starters โ€“ intended to <em>work out of the box</em></p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>NEORV32 CPU (the core)</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>32-bit RISC-V CPU</p> +</li> +<li> +<p>fully compatible to the RISC-V ISA specs. - checked by the <a href="https://github.com/stnolting/neorv32-riscof">official RISCOF architecture tests</a></p> +</li> +<li> +<p>base ISA + privileged ISA + several optional standard and custom ISA extensions</p> +</li> +<li> +<p>option to add user-defined RISC-V instructions as custom ISA extension</p> +</li> +<li> +<p>rich set of customization options (ISA extensions, design goal: performance / area / energy, tuning options, &#8230;&#8203;)</p> +</li> +<li> +<p><a href="#_full_virtualization">Full Virtualization</a> capabilities to increase execution safety</p> +</li> +<li> +<p>official RISC-V open source architecture ID</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>NEORV32 Processor (the SoC)</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>highly-configurable full-scale microcontroller-like processor system</p> +</li> +<li> +<p>based on the NEORV32 CPU</p> +</li> +<li> +<p>optional standard serial interfaces (UART, TWI, SPI (host and device), 1-Wire)</p> +</li> +<li> +<p>optional timers and counters (watchdog, system timer)</p> +</li> +<li> +<p>optional general purpose IO and PWM; a native NeoPixel(c)-compatible smart LED interface</p> +</li> +<li> +<p>optional embedded memories and caches for data, instructions and bootloader</p> +</li> +<li> +<p>optional external memory interface for custom connectivity</p> +</li> +<li> +<p>optional execute in-place (XIP) module to execute code directly form an external SPI flash</p> +</li> +<li> +<p>optional DMA controller for CPU-independent data transfers</p> +</li> +<li> +<p>optional CRC module to check data integrity</p> +</li> +<li> +<p>on-chip debugger compatible with OpenOCD and gdb including hardware trigger module</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>Software framework</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>GCC-based toolchain - <a href="https://github.com/stnolting/riscv-gcc-prebuilt">prebuilt toolchains available</a>; application compilation based on GNU makefiles</p> +</li> +<li> +<p>internal bootloader with serial user interface (via UART)</p> +</li> +<li> +<p>core libraries and HAL for high-level usage of the provided functions and peripherals</p> +</li> +<li> +<p>processor-specific runtime environment and several example programs</p> +</li> +<li> +<p>doxygen-based documentation of the software framework; a deployed version is available at <a href="https://stnolting.github.io/neorv32/sw/files.html" class="bare">https://stnolting.github.io/neorv32/sw/files.html</a></p> +</li> +<li> +<p>FreeRTOS port + demos available</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>Extensibility and Customization</strong></p> +</div> +<div class="paragraph"> +<p>The NEORV32 processor is designed to ease customization and extensibility and provides several options for adding +application-specific custom hardware modules and accelerators. The three most common options for adding custom +on-chip modules are listed below.</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_processor_external_bus_interface_xbus">Processor-External Bus Interface (XBUS)</a> to attach processor-external IP modules (memories and peripherals)</p> +</li> +<li> +<p><a href="#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a> for tightly-coupled processor-internal co-processors</p> +</li> +<li> +<p><a href="#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a> for custom RISC-V instructions</p> +</li> +</ul> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +A more detailed comparison of the extension/customization options can be found in section +<a href="https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules">Adding Custom Hardware Modules</a> +of the user guide. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_project_folder_structure">1.3. Project Folder Structure</h3> +<div class="paragraph"> +<p>The root directory of the repository is considered the NEORV32 base or home folder (i.e. <code>neorv32/</code>).</p> +</div> +<div class="literalblock"> +<div class="title">Folder Structure</div> +<div class="content"> +<pre>neorv32 - Project home folder +โ”‚ +โ”œdocs - Project documentation +โ”‚โ”œdatasheet - AsciiDoc sources for the NEORV32 data sheet +โ”‚โ”œfigures - Figures and logos +โ”‚โ”œreferences - Data sheets and RISC-V specs +โ”‚โ”œsources - Sources for the images in 'figures/' +โ”‚โ””userguide - AsciiDoc sources for the NEORV32 user guide +โ”‚ +โ”œrtl - VHDL sources +โ”‚โ”œcore - Core sources of the CPU &amp; SoC +โ”‚โ”œprocessor_templates - Pre-configured SoC wrappers +โ”‚โ”œsystem_integration - System wrappers and bridges for advanced connectivity +โ”‚โ””test_setups - Minimal test setup "SoCs" used in the User Guide +โ”‚ +โ”œsim - Simulation files +โ”‚ +โ””-sw - Software framework + โ”œbootloader - Sources of the processor-internal bootloader + โ”œcommon - Linker script, crt0.S start-up code and central makefile + โ”œexample - Example programs for the core and the SoC modules + โ”‚โ”œeclipse - Pre-configured Eclipse IDE project + โ”‚โ””... - Several example programs + โ”œlib - Processor core library + โ”‚โ”œinclude - NEORV32 core library header files (*.h) + โ”‚โ””source - NEORV32 core library source files (*.c) + โ”œimage_gen - Helper program to generate executables &amp; memory images + โ”œocd_firmware - Firmware for the on-chip debugger's "park loop" + โ”œopenocd - OpenOCD configuration files + โ””svd - Processor system view description file (CMSIS-SVD)</pre> +</div> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_vhdl_file_hierarchy">1.4. VHDL File Hierarchy</h3> +<div class="paragraph"> +<p>All required VHDL hardware source files are located in the project&#8217;s <code>rtl/core</code> folder.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">VHDL Library</div> +All core VHDL files from the list below have to be assigned to a <strong>new library</strong> named <code>neorv32</code>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Compilation Order</div> +See section <a href="#_file_list_files">File-List Files</a> for more information. +</td> +</tr> +</table> +</div> +<div class="literalblock"> +<div class="title">RTL File List and Hierarchy</div> +<div class="content"> +<pre>neorv32_top.vhd - NEORV32 PROCESSOR/SOC TOP ENTITY +โ”‚ +โ”œneorv32_cpu.vhd - NEORV32 CPU TOP ENTITY +โ”‚โ”œneorv32_cpu_alu.vhd - Arithmetic/logic unit +โ”‚โ”‚โ”œneorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.) +โ”‚โ”‚โ”œneorv32_cpu_cp_cfu.vhd - Custom instructions co-processor (Zxcfu ext.) +โ”‚โ”‚โ”œneorv32_cpu_cp_cond.vhd - Integer conditional co-processor (Zicond ext.) +โ”‚โ”‚โ”œneorv32_cpu_cp_crypto.vhd - Scalar cryptographic co-processor (Zk*/Zbk* ext.) +โ”‚โ”‚โ”œneorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.) +โ”‚โ”‚โ”œneorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M ext.) +โ”‚โ”‚โ””neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor (base ISA) +โ”‚โ”œneorv32_cpu_control.vhd - CPU control, exception system and CSRs +โ”‚โ”‚โ””neorv32_cpu_decompressor.vhd - Compressed instructions decoder (C ext.) +โ”‚โ”œneorv32_cpu_lsu.vhd - Load/store unit +โ”‚โ”œneorv32_cpu_pmp.vhd - Physical memory protection unit (Smpmp ext.) +โ”‚โ””neorv32_cpu_regfile.vhd - Data register file +โ”‚ +โ”œneorv32_boot_rom.vhd - Bootloader ROM +โ”‚โ””neorv32_bootloader_image.vhd - Bootloader ROM memory image +โ”œneorv32_bus.vhd - SoC bus infrastructure modules +โ”œneorv32_cache.vhd - Generic cache module +โ”œneorv32_cfs.vhd - Custom functions subsystem +โ”œneorv32_clockgate.vhd - Generic clock gating switch +โ”œneorv32_crc.vhd - Cyclic redundancy check unit +โ”œneorv32_debug_dm.vhd - on-chip debugger: debug module +โ”œneorv32_debug_dtm.vhd - on-chip debugger: debug transfer module +โ”œneorv32_dma.vhd - Direct memory access controller +โ”œneorv32_dmem.vhd - Generic processor-internal data memory +โ”œneorv32_fifo.vhd - Generic FIFO component +โ”œneorv32_gpio.vhd - General purpose input/output port unit +โ”œneorv32_gptmr.vhd - General purpose 32-bit timer +โ”œneorv32_imem.vhd - Generic processor-internal instruction memory +โ”‚โ””neorv32_application_image.vhd - IMEM application initialization image +โ”œneorv32_mtime.vhd - Machine system timer +โ”œneorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface +โ”œneorv32_onewire.vhd - One-Wire serial interface controller +โ”œneorv32_package.vhd - Main VHDL package file +โ”œneorv32_pwm.vhd - Pulse-width modulation controller +โ”œneorv32_sdi.vhd - Serial data interface controller (SPI device) +โ”œneorv32_slink.vhd - Stream link interface +โ”œneorv32_spi.vhd - Serial peripheral interface controller (SPI host) +โ”œneorv32_sys.vhd - System infrastructure modules +โ”œneorv32_sysinfo.vhd - System configuration information memory +โ”œneorv32_trng.vhd - True random number generator +โ”œneorv32_twi.vhd - Two wire serial interface controller +โ”œneorv32_uart.vhd - Universal async. receiver/transmitter +โ”œneorv32_wdt.vhd - Watchdog timer +โ”œneorv32_xbus.vhd - External (Wishbone) bus interface gateways +โ”œneorv32_xip.vhd - Execute in place module +โ””neorv32_xirq.vhd - External interrupt controller</pre> +</div> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Replacing Modules for Customization or Optimization</div> +Any module of the core can be replaced by the user for customization purpose. For example, the default IMEM and DMEM +modules as well as the CPU&#8217;s register file can be replaced by technology-specific primitives to optimize energy, speed +and area utilization. The module, which are dedicated for customization, i.e. CFS and CFU can be replaced by +user-defined modules to implement application-specific functionality. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_file_list_files">1.4.1. File-List Files</h4> +<div class="paragraph"> +<p>Most of the RTL sources use <strong>entity instantiation</strong>. Hence, the RTL compile order might be relevant (depending on +the synthesis/simulation tool. Therefore, two file-list files are provided in the <code>rtl</code> folder that list all required +HDL files for the CPU core and for the entire processor and also represent their recommended compile order. +These file-list files can be consumed by EDA tools to simplify project setup.</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>file_list_cpu.f</code> - HDL files and compile order for the CPU core; top module: <code>neorv32_cpu</code></p> +</li> +<li> +<p><code>file_list_soc.f</code> - HDL files and compile order for the entire processor/SoC; top module: <code>neorv32_top</code></p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>A simple bash script <code>generate_file_lists.sh</code> is provided for regenerating the file-lists (using GHDL&#8217;s <em>elaborate</em> command). +This script can also be invoked using the default application makefile (see <a href="#_makefile_targets">Makefile Targets</a>).</p> +</div> +<div class="paragraph"> +<p>By default, the file-list files include a <strong>placeholder</strong> in the path of each included hardware source file. +These placeholders need to be replaced by the actual path before being used. Example:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>default: <code>NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_package.vhd</code></p> +</li> +<li> +<p>adjusted: <code>path/to/neorv32/rtl/core/neorv32_package.vhd</code></p> +</li> +</ul> +</div> +<div class="listingblock"> +<div class="title">Listing 1. Example: Processing the File-List Files in a Makefile</div> +<div class="content"> +<pre class="highlight"><code class="language-makefile" data-lang="makefile">NEORV32_HOME = path/to/neorv32 <i class="conum" data-value="1"></i><b>(1)</b> +NEORV32_SOC_FILE = $(shell cat $(NEORV32_HOME)/rtl/file_list_soc.f) <i class="conum" data-value="2"></i><b>(2)</b> +NEORV32_SOC_SRCS = $(subst NEORV32_RTL_PATH_PLACEHOLDER, $(NEORV32_HOME)/rtl, $(NEORV32_SOC_FILE))) <i class="conum" data-value="3"></i><b>(3)</b></code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td>Path to the NEORV32 home folder (i.e. the root folder of the GitHub repository).</td> +</tr> +<tr> +<td><i class="conum" data-value="2"></i><b>2</b></td> +<td>Load the content of the <code>file_list_soc.f</code> file-list into a new variable <code>NEORV32_SOC_FILE</code>.</td> +</tr> +<tr> +<td><i class="conum" data-value="3"></i><b>3</b></td> +<td>Substitute the file-list file&#8217;s path placeholder &#8220;NEORV32_RTL_PATH_PLACEHOLDER&#8221; by the actual path.</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="title">Listing 2. Example: Processing the File-List Files in a TCL Script</div> +<div class="content"> +<pre class="highlight"><code class="language-tcl" data-lang="tcl">set file_list_file [read [open "$neorv32_home/rtl/file_list_soc.f" r]] +set file_list [string map [list "NEORV32_RTL_PATH_PLACEHOLDER" "$neorv32_home/rtl"] $file_list_file] +puts "NEORV32 source files:" +puts $file_list</code></pre> +</div> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">File-List Usage Examples</div> +The provided file-list files are used by the GHDL-based simple simulation setup (<code>sim/tb_simple/ghdl.setup.sh</code>) as +well as by the Vivado IP packager script (<code>rtl/system_integration/neorv32_vivado_ip.tcl</code>). +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_vhdl_coding_style">1.5. VHDL Coding Style</h3> +<div class="ulist"> +<ul> +<li> +<p>The entire processor including the CPU core is written in platform-/technology-independent VHDL. +The code makes minimal use of VHDL 2008 features to provide compatibility even for older EDA tools.</p> +</li> +<li> +<p>A single package / library file (<code>neorv32_package.vhd</code>) is used to provide global defines and helper +functions. The specific user-defined configuration is done entirely by the generics of the top entity.</p> +</li> +<li> +<p>Internally, the generics are checked to ensure a correct configuration. Asserts and "sanity checks" are used +to inform the user about the actual processor configuration and potential illegal setting.</p> +</li> +<li> +<p>The code uses <em>entity instation</em> for all internal modules. However, if several "submodules" are specified +within the same file <em>component instantiation</em> is used for those.</p> +</li> +<li> +<p>When instantiating the processor top module (<code>neorv32_top.vhd</code>) in a custom design either entity instantiation or +component instantiation can be used as the NEORV32 package file / library already provides an according component declaration.</p> +</li> +</ul> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Verilog Version</div> +A GHDL-generated all-Verilog version of the processor is available at <a href="https://github.com/stnolting/neorv32-verilog" class="bare">https://github.com/stnolting/neorv32-verilog</a>. +The provided setup generates a synthesizable Verilog netlist for a custom processor configuration. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_fpga_implementation_results">1.6. FPGA Implementation Results</h3> +<div class="paragraph"> +<p>This section shows <strong>exemplary</strong> FPGA implementation results for the NEORV32 CPU and NEORV32 Processor modules.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +The results are generated by manual synthesis runs. Hence, they might not represent the latest version of the processor. +</td> +</tr> +</table> +</div> +<h4 id="_cpu" class="discrete">CPU</h4> +<table class="tableblock frame-all grid-topbot stretch"> +<colgroup> +<col style="width: 20%;"> +<col style="width: 80%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">HW version:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1.7.8.5</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rtl/core/neorv32_cpu.vhd</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">FPGA:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Intel Cyclone IV E <code>EP4CE22F17C6</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Toolchain:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Quartus Prime Lite 21.1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Constraints:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>no timing constraints</strong>, "balanced optimization", f<sub>max</sub> from "<em>Slow 1200mV 0C Model</em>"</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<colgroup> +<col style="width: 54.5454%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.091%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">CPU ISA Configuration</th> +<th class="tableblock halign-right valign-top">LEs</th> +<th class="tableblock halign-right valign-top">FFs</th> +<th class="tableblock halign-right valign-top">MEM bits</th> +<th class="tableblock halign-right valign-top">DSPs</th> +<th class="tableblock halign-right valign-top"><em>f<sub>max</sub></em></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32i_Zicsr</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1223</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">607</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">130 MHz</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32i_Zicsr_Zicntr</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1578</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">773</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">130 MHz</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32im_Zicsr_Zicntr</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2087</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">983</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">130 MHz</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32imc_Zicsr_Zicntr</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2338</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">992</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">130 MHz</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32imcb_Zicsr_Zicntr</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">3175</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1247</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">130 MHz</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32imcbu_Zicsr_Zicntr</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">3186</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1254</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">130 MHz</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32imcbu_Zicsr_Zicntr_Zifencei</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">3187</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1254</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">130 MHz</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32imcbu_Zicsr_Zicntr_Zifencei_Zfinx</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">4450</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1906</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">123 MHz</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rv32imcbu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">4825</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2018</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">123 MHz</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Goal-Driven Optimization</div> +The CPU provides further options to reduce the area footprint or to increase performance. +See section <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a> for more information. Also, take a look at the User Guide section +<a href="https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration">Application-Specific Processor Configuration</a>. +</td> +</tr> +</table> +</div> +<h4 id="_processor_modules" class="discrete">Processor - Modules</h4> +<table class="tableblock frame-all grid-topbot stretch"> +<colgroup> +<col style="width: 20%;"> +<col style="width: 80%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">HW version:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1.8.6.7</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rtl/core/neorv32_top.vhd</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">FPGA:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Intel Cyclone IV E <code>EP4CE22F17C6</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Toolchain:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Quartus Prime Lite 21.1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Constraints:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>no timing constraints</strong>, "balanced optimization"</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 1. Hardware utilization by processor module</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 53.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 13.3333%;"> +<col style="width: 6.6669%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Module</th> +<th class="tableblock halign-left valign-top">Description</th> +<th class="tableblock halign-right valign-top">LEs</th> +<th class="tableblock halign-right valign-top">FFs</th> +<th class="tableblock halign-right valign-top">MEM bits</th> +<th class="tableblock halign-right valign-top">DSPs</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">BOOT ROM</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Bootloader ROM (4kB)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">32768</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Bus switch (core)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>SoC bus infrastructure</em></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">28</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">15</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Bus switch (DMA)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>SoC bus infrastructure</em></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">159</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">9</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CFS</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Custom functions subsystem (depends on custom design logic)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">-</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CRC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Cyclic redundancy check unit</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">130</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">117</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">dCACHE</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Data cache (4 blocks, 64 bytes per block)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">300</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">167</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2112</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">DM</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">On-chip debugger - debug module</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">377</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">241</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">DTM</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">On-chip debugger - debug transfer module (JTAG)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">262</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">220</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">DMA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Direct memory access controller</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">365</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">291</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">DMEM</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Processor-internal data memory (8kB)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">6</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">65536</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Gateway</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>SoC bus infrastructure</em></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">215</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">91</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">GPIO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">General purpose input/output ports</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">102</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">98</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">GPTMR</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">General Purpose Timer</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">150</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">105</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">IO Switch</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>SoC bus infrastructure</em></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">217</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">iCACHE</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction cache (2x4 blocks, 64 bytes per block)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">458</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">296</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">4096</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">IMEM</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Processor-internal instruction memory (16kB)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">131072</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">MTIME</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine system timer</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">307</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">166</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">NEOLED</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Smart LED Interface (NeoPixel/WS28128) (FIFO_depth=1)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">171</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">129</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ONEWIRE</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-wire interface</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">105</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">77</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">PWM</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Pulse_width modulation controller (4 channels)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">91</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">81</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reservation Set</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reservation set controller for LR/SC instructions</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">52</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">33</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">SDI</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Serial data interface</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">103</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">77</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">512</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">SLINK</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Stream link interface (RX/TX FIFO depth=32)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">96</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">73</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">2048</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Serial peripheral interface</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">137</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">97</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">SYSINFO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">System configuration information memory</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">TRNG</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">True random number generator</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">140</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">108</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">512</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">TWI</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Two-wire interface</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">93</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART0, UART1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Universal asynchronous receiver/transmitter 0/1 (FIFO_depth=1)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">222</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">142</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">WDT</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Watchdog timer</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">107</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">89</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">WISHBONE</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">External memory interface</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">122</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">112</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">XIP</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Execute in place module</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">369</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">276</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">XIRQ</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">External interrupt controller (4 channels)</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">35</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">29</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">0</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_cpu_performance">1.7. CPU Performance</h3> +<div class="paragraph"> +<p>The performance of the NEORV32 was tested and evaluated using the <a href="https://www.eembc.org/coremark/">Core Mark CPU benchmark</a>. +The according sources can be found in the <code>sw/example/coremark</code> folder. +The resulting CoreMark score is defined as CoreMark iterations per second per MHz.</p> +</div> +<table class="tableblock frame-all grid-topbot stretch"> +<caption class="title">Table 2. Configuration</caption> +<colgroup> +<col style="width: 20%;"> +<col style="width: 80%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">HW version:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1.5.7.10</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">32kB int. IMEM, 16kB int. DMEM, no caches, 100MHz clock</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CoreMark:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">2000 iterations, MEM_METHOD is MEM_STACK</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Compiler:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RISCV32-GCC 10.2.0 (compiled with <code>march=rv32i mabi=ilp32</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Compiler flags:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">default but with <code>-O3</code>, see makefile</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 3. CoreMark results</caption> +<colgroup> +<col style="width: 62.5%;"> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">CPU</th> +<th class="tableblock halign-center valign-top">CoreMark Score</th> +<th class="tableblock halign-center valign-top">CoreMarks/MHz</th> +<th class="tableblock halign-center valign-top">Average CPI</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>small</em> (<code>rv32i_Zicsr_Zifencei</code>)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">33.89</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>0.3389</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>4.04</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>medium</em> (<code>rv32imc_Zicsr_Zifencei</code>)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">62.50</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>0.6250</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>5.34</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>performance</em> (<code>rv32imc_Zicsr_Zifencei</code> + perf. options)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">95.23</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>0.9523</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>3.54</strong></p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of +several consecutive micro operations. The average CPI (cycles per instruction) depends on the instruction +mix of a specific applications and also on the available CPU extensions. More information regarding the execution +time of each implemented instruction can be found in section <a href="#_instruction_sets_and_extensions">Instruction Sets and Extensions</a>.</p> +</div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_neorv32_processor_soc">2. NEORV32 Processor (SoC)</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral +interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.</p> +</div> +<div class="imageblock text-center"> +<div class="content"> +<img src="img/neorv32_processor.png" alt="neorv32 processor"> +</div> +<div class="title">Figure 1. The NEORV32 Processor (Block Diagram)</div> +</div> +<div class="paragraph"> +<p><strong>Section Structure</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_processor_top_entity_signals">Processor Top Entity - Signals</a> and <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a></p> +</li> +<li> +<p><a href="#_processor_clocking">Processor Clocking</a> and <a href="#_processor_reset">Processor Reset</a></p> +</li> +<li> +<p><a href="#_processor_interrupts">Processor Interrupts</a></p> +</li> +<li> +<p><a href="#_address_space">Address Space</a> and <a href="#_boot_configuration">Boot Configuration</a></p> +</li> +<li> +<p><a href="#_processor_internal_modules">Processor-Internal Modules</a></p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>Key Features</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p><em>optional</em> processor-internal data and instruction memories (<a href="#_data_memory_dmem"><strong>DMEM</strong></a>/<a href="#_instruction_memory_imem"><strong>IMEM</strong></a>)</p> +</li> +<li> +<p><em>optional</em> caches (<a href="#_processor_internal_instruction_cache_icache"><strong>I-CACHE</strong></a>, <a href="#_processor_internal_data_cache_dcache"><strong>D-CACHE</strong></a>, +<a href="#_execute_in_place_module_xip"><strong>XIP-CACHE</strong></a>, <a href="#_processor_external_bus_interface_xbus"><strong>XBUS-CACHE</strong></a>)</p> +</li> +<li> +<p><em>optional</em> internal bootloader (<a href="#_bootloader_rom_bootrom"><strong>BOOTROM</strong></a>) with UART console &amp; SPI flash boot option</p> +</li> +<li> +<p><em>optional</em> machine system timer (<a href="#_machine_system_timer_mtime"><strong>MTIME</strong></a>), RISC-V-compatible</p> +</li> +<li> +<p><em>optional</em> two independent universal asynchronous receivers and transmitters (<a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0"><strong>UART0</strong></a>, +<a href="#_secondary_universal_asynchronous_receiver_and_transmitter_uart1"><strong>UART1</strong></a>) with optional hardware flow control (RTS/CTS)</p> +</li> +<li> +<p><em>optional</em> serial peripheral interface host controller (<a href="#_serial_peripheral_interface_controller_spi"><strong>SPI</strong></a>) with 8 dedicated CS lines</p> +</li> +<li> +<p><em>optional</em> 8-bit serial data device interface (<a href="#_serial_data_interface_controller_spi"><strong>SDI</strong></a>)</p> +</li> +<li> +<p><em>optional</em> two wire serial interface controller (<a href="#_two_wire_serial_interface_controller_twi"><strong>TWI</strong></a>), compatible to the IยฒC standard</p> +</li> +<li> +<p><em>optional</em> general purpose parallel IO port (<a href="#_general_purpose_input_and_output_port_gpio"><strong>GPIO</strong></a>), 64xOut, 64xIn</p> +</li> +<li> +<p><em>optional</em> 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<a href="#_processor_external_bus_interface_xbus"><strong>XBUS</strong></a>)</p> +</li> +<li> +<p><em>optional</em> watchdog timer (<a href="#_watchdog_timer_wdt"><strong>WDT</strong></a>)</p> +</li> +<li> +<p><em>optional</em> PWM controller with up to 16 individual channels (<a href="#_pulse_width_modulation_controller_pwm"><strong>PWM</strong></a>)</p> +</li> +<li> +<p><em>optional</em> ring-oscillator-based true random number generator (<a href="#_true_random_number_generator_trng"><strong>TRNG</strong></a>)</p> +</li> +<li> +<p><em>optional</em> custom functions subsystem for custom co-processor extensions (<a href="#_custom_functions_subsystem_cfs"><strong>CFS</strong></a>)</p> +</li> +<li> +<p><em>optional</em> NeoPixel&#8482;/WS2812-compatible smart LED interface (<a href="#_smart_led_interface_neoled"><strong>NEOLED</strong></a>)</p> +</li> +<li> +<p><em>optional</em> external interrupt controller with up to 32 channels and programmable interrupt triggers (<a href="#_external_interrupt_controller_xirq"><strong>XIRQ</strong></a>)</p> +</li> +<li> +<p><em>optional</em> general purpose 32-bit timer (<a href="#_general_purpose_timer_gptmr"><strong>GPTMR</strong></a>)</p> +</li> +<li> +<p><em>optional</em> execute in-place module (<a href="#_execute_in_place_module_xip"><strong>XIP</strong></a>)</p> +</li> +<li> +<p><em>optional</em> 1-wire serial interface controller (<a href="#_one_wire_serial_interface_controller_onewire"><strong>ONEWIRE</strong></a>), compatible to the 1-wire standard</p> +</li> +<li> +<p><em>optional</em> autonomous direct memory access controller (<a href="#_direct_memory_access_controller_dma"><strong>DMA</strong></a>)</p> +</li> +<li> +<p><em>optional</em> stream link interface (<a href="#_stream_link_interface_slink"><strong>SLINK</strong></a>), AXI4-Stream compatible</p> +</li> +<li> +<p><em>optional</em> cyclic redundancy check unit (<a href="#_cyclic_redundancy_check_crc"><strong>CRC</strong></a>)</p> +</li> +<li> +<p><em>optional</em> on-chip debugger with JTAG TAP (<a href="#_on_chip_debugger_ocd"><strong>OCD</strong></a>)</p> +</li> +<li> +<p><em>optional</em> system configuration information memory to determine hardware configuration via software (<a href="#_system_configuration_information_memory_sysinfo"><strong>SYSINFO</strong></a>)</p> +</li> +</ul> +</div> +<div style="page-break-after: always;"></div> +<div class="sect2"> +<h3 id="_processor_top_entity_signals">2.1. Processor Top Entity - Signals</h3> +<div class="paragraph"> +<p>The following table shows all interface signals of the processor top entity (<code>rtl/core/neorv32_top.vhd</code>). +All signals are of type <code>std_ulogic</code> or <code>std_ulogic_vector</code>, respectively.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Default Values of Inputs</div> +All <em>optional</em> input signals provide default values in case they are not explicitly assigned during instantiation. +The weak driver strengths of VHDL (<code>'L'</code> and <code>'H'</code>) are used to model a pull-down or pull-up resistor. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Variable-Sized Ports</div> +Some peripherals allow to configure the number of channels to-be-implemented by a generic (for example the number +of PWM channels). The according input/output signals have a fixed sized regardless of the actually configured +amount of channels. If less than the maximum number of channels is configured, only the LSB-aligned channels are used: +in case of an <em>input port</em> the remaining bits/channels are left unconnected; in case of an <em>output port</em> the remaining +bits/channels are hardwired to zero. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Tri-State Interfaces</div> +Some interfaces (like the TWI and the 1-Wire bus) require explicit tri-state drivers in the final top module. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Input/Output Registers</div> +By default all output signals are driven by register and all input signals are synchronized into the processor&#8217;s +clock domain also using registers. However, for ASIC implementations it is recommended to add another register state +to all inputs and output so the synthesis tool can insert an explicit IO (boundary) scan chain. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 4. NEORV32 Processor Signal List</caption> +<colgroup> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 7.1428%;"> +<col style="width: 7.1428%;"> +<col style="width: 57.1431%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Name</th> +<th class="tableblock halign-center valign-top">Width</th> +<th class="tableblock halign-center valign-top">Direction</th> +<th class="tableblock halign-center valign-top">Default</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong>Global Control (<a href="#_processor_clocking">Processor Clocking</a> and <a href="#_processor_reset">Processor Reset</a>)</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>clk_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">global clock line, all registers triggering on rising edge</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rstn_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">global reset, asynchronous, <strong>low-active</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong>JTAG Access Port for <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>jtag_tck_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial clock</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>jtag_tdi_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>jtag_tdo_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>jtag_tms_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">mode select</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_processor_external_bus_interface_xbus">Processor-External Bus Interface (XBUS)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_adr_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">destination address</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_dat_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">read data</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_tag_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">access tag</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_we_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">write enable ('0' = read transfer)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_sel_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">byte enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_stb_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">strobe</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_cyc_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">valid cycle</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_dat_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">write data</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_ack_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">transfer acknowledge</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_err_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">transfer error</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_stream_link_interface_slink">Stream Link Interface (SLINK)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_dat_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX data</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_src_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX source routing information</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_val_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX data valid</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_lst_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX last element of stream</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_rdy_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX ready to receive</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_dat_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX data</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_dst_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX destination routing information</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_val_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX data valid</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_lst_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX last element of stream</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_rdy_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX allowed to send</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip_csn_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">chip select, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip_clk_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial clock</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip_dat_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip_dat_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_general_purpose_input_and_output_port_gpio">General Purpose Input and Output Port (GPIO)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>gpio_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">general purpose parallel output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>gpio_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">general purpose parallel input</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">Primary Universal Asynchronous Receiver and Transmitter (UART0)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart0_txd_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial transmitter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart0_rxd_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial receiver</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart0_rts_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX ready to receive new char</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart0_cts_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX allowed to start sending, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_secondary_universal_asynchronous_receiver_and_transmitter_uart1">Secondary Universal Asynchronous Receiver and Transmitter (UART1)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart1_txd_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial transmitter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart1_rxd_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial receiver</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart1_rts_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX ready to receive new char</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart1_cts_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX allowed to start sending, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_serial_peripheral_interface_controller_spi">Serial Peripheral Interface Controller (SPI)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>spi_clk_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">controller clock line</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>spi_dat_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>spi_dat_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>spi_csn_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">select (low-active)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_serial_data_interface_controller_sdi">Serial Data Interface Controller (SDI)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sdi_clk_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">controller clock line</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sdi_dat_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sdi_dat_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sdi_csn_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'H'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">chip select, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_two_wire_serial_interface_controller_twi">Two-Wire Serial Interface Controller (TWI)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>twi_sda_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'H'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data line sense input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>twi_sda_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data line output (pull low only)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>twi_scl_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'H'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial clock line sense input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>twi_scl_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial clock line output (pull low only)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_one_wire_serial_interface_controller_onewire">One-Wire Serial Interface Controller (ONEWIRE)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>onewire_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'H'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-wire bus sense input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>onewire_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-wire bus output (pull low only)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_pulse_width_modulation_controller_pwm">Pulse-Width Modulation Controller (PWM)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>pwm_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">pulse-width modulated channels</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>cfs_in_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom CFS input signal conduit</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>cfs_out_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom CFS output signal conduit</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_smart_led_interface_neoled">Smart LED Interface (NEOLED)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neoled_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">asynchronous serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mtime_time_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">MTIME system time output</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_external_interrupt_controller_xirq">External Interrupt Controller (XIRQ)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xirq_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">external interrupt requests</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong>RISC-V Machine-Mode <a href="#_processor_interrupts">Processor Interrupts</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mtime_irq_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine timer interrupt (RISC-V), high-level-active; for chip-internal usage only</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>msw_irq_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine software interrupt (RISC-V), high-level-active; for chip-internal usage only</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mext_irq_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>'L'</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine external interrupt (RISC-V), high-level-active; for chip-internal usage only</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_processor_top_entity_generics">2.2. Processor Top Entity - Generics</h3> +<div class="paragraph"> +<p>This section lists all configuration generics of the NEORV32 processor top entity (<code>rtl/neorv32_top.vhd</code>). +These generics allow to configure the system according to your needs. The generics are +used to control implementation of certain CPU extensions and peripheral modules and even allow to +optimize the system for certain design goals like minimal area or maximum performance.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Default Values</div> +All <em>optional</em> configuration generics provide default values in case they are not explicitly assigned during instantiation. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Software Discovery of Configuration</div> +Software can determine the actual CPU configuration via the <a href="#_misa"><strong><code>misa</code></strong></a> and <a href="#_mxisa"><strong><code>mxisa</code></strong></a> CSRs. The Soc/Processor +and can be determined via the <a href="#_system_configuration_information_memory_sysinfo">SYSINFO</a> memory-mapped registers. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Excluded Modules and Extensions</div> +If optional modules (like CPU extensions or peripheral devices) are not enabled the according hardware +will not be synthesized at all. Hence, the disabled modules do not increase area and power requirements +and do not impact timing. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Table Abbreviations</div> +The generic type &#8220;suv(x:y)&#8221; is an abbreviation for &#8220;std_ulogic_vector(x downto y)&#8221;. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 5. NEORV32 Processor Generic List</caption> +<colgroup> +<col style="width: 20%;"> +<col style="width: 13.3333%;"> +<col style="width: 13.3333%;"> +<col style="width: 53.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Name</th> +<th class="tableblock halign-center valign-top">Type</th> +<th class="tableblock halign-center valign-top">Default</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>General</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CLOCK_FREQUENCY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The clock frequency of the processor&#8217;s <code>clk_i</code> input port in Hertz (Hz).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CLOCK_GATING_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable clock gating when CPU is in sleep mode (see sections <a href="#_sleep_mode">Sleep Mode</a> and <a href="#_processor_clocking">Processor Clocking</a>).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>INT_BOOTLOADER_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the processor-internal <a href="#_bootloader_rom_bootrom">Bootloader ROM (BOOTROM)</a>, pre-initialized with the default <a href="#_bootloader">Bootloader</a> image.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>HART_ID</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">suv(31:0)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0x00000000</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The hart thread ID of the CPU (passed to <a href="#_mhartid"><strong><code>mhartid</code></strong></a> CSR).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>JEDEC_ID</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">suv(10:0)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0b00000000000</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">JEDEC ID; continuation codes plus vendor ID (passed to <a href="#_mvendorid"><strong><code>mvendorid</code></strong></a> CSR and to the <a href="#_debug_transport_module_dtm">Debug Transport Module (DTM)</a>).</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong><a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ON_CHIP_DEBUGGER_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the on-chip debugger and the CPU debug mode.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DM_LEGACY_MODE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug module spec. version: <code>false</code> = v1.0, <code>true</code> = v0.13 (legacy mode).</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>CPU <a href="#_instruction_sets_and_extensions">Instruction Sets and Extensions</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_C</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_c_isa_extension"><code>C</code> ISA Extension</a> (compressed instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_E</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_e_isa_extension"><code>E</code> ISA Extension</a> (reduced register file size).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_M</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_m_isa_extension"><code>M</code> ISA Extension</a> (hardware-based integer multiplication and division).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_U</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_u_isa_extension"><code>U</code> ISA Extension</a> (less-privileged user mode).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zalrsc</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a> (atomic reservation-set operations).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zba</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zba_isa_extension"><code>Zba</code> ISA Extension</a> (shifted-add bit-manipulation instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zbb</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zbb_isa_extension"><code>Zbb</code> ISA Extension</a> (basic bit-manipulation instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zbkb</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zbkb_isa_extension"><code>Zbkb</code> ISA Extension</a> (scalar cryptography bit manipulation instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zbkc</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zbkc_isa_extension"><code>Zbkc</code> ISA Extension</a> (scalar cryptography carry-less multiplication instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zbkx</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zbkx_isa_extension"><code>Zbkx</code> ISA Extension</a> (scalar cryptography crossbar permutations).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zbs</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zbs_isa_extension"><code>Zbs</code> ISA Extension</a> (single-bit bit-manipulation instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zfinx</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zfinx_isa_extension"><code>Zfinx</code> ISA Extension</a> (single-precision floating-point unit).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zicntr</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">true</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zicntr_isa_extension"><code>Zicntr</code> ISA Extension</a> (CPU base counters).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zicond</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zicond_isa_extension"><code>Zicond</code> ISA Extension</a> (integer conditional instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zihpm</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zihpm_isa_extension"><code>Zihpm</code> ISA Extension</a> (hardware performance monitors).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zknd</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zknd_isa_extension"><code>Zknd</code> ISA Extension</a> (scalar cryptography NIST AES decryption instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zkne</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zkne_isa_extension"><code>Zkne</code> ISA Extension</a> (scalar cryptography NIST AES encryption instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zknh</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zknh_isa_extension"><code>Zknh</code> ISA Extension</a> (scalar cryptography NIST hash instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zksed</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zksed_isa_extension"><code>Zksed</code> ISA Extension</a> (scalar cryptography ShangMi block cyphers).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zksh</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zksh_isa_extension"><code>Zksh</code> ISA Extension</a> (scalar cryptography ShangMi hash functions).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zmmul</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable <a href="#_zmmul_isa_extension"><code>Zmmul</code> - ISA Extension</a> (hardware-based integer multiplication).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Zxcfu</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable NEORV32-specific <a href="#_zxcfu_isa_extension"><code>Zxcfu</code> ISA Extension</a> (custom RISC-V instructions).</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>CPU <a href="#_architecture">Architecture</a> Tuning Options</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>FAST_MUL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <a href="#_cpu_arithmetic_logic_unit">CPU Arithmetic Logic Unit</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>FAST_SHIFT_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement fast but large full-parallel barrel shifters; see section <a href="#_cpu_arithmetic_logic_unit">CPU Arithmetic Logic Unit</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>REGFILE_HW_RST</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement full hardware reset for register file (use individual FFs instead of BRAM); see section <a href="#_cpu_register_file">CPU Register File</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Physical Memory Protection (<a href="#_smpmp_isa_extension"><code>Smpmp</code> ISA Extension</a>)</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>PMP_NUM_REGIONS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of implemented PMP regions (0..16).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>PMP_MIN_GRANULARITY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Minimal region granularity in bytes. Has to be a power of two, min 4.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>PMP_TOR_MODE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">true</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement support for top-of-region (TOR) mode.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>PMP_NAP_MODE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">true</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement support for naturally-aligned power-of-two (NAPOT &amp; NA4) modes.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Hardware Performance Monitors (<a href="#_zihpm_isa_extension"><code>Zihpm</code> ISA Extension</a>)</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>HPM_NUM_CNTS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of implemented hardware performance monitor counters (0..13).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>HPM_CNT_WIDTH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">40</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Total LSB-aligned size of each HPM counter. Min 0, max 64.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Internal <a href="#_instruction_memory_imem">Instruction Memory (IMEM)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM_INT_IMEM_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the processor-internal instruction memory.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM_INT_IMEM_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">16*1024</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Size in bytes of the processor internal instruction memory (use a power of 2).</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Internal <a href="#_data_memory_dmem">Data Memory (DMEM)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM_INT_DMEM_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the processor-internal data memory.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM_INT_DMEM_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8*1024</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Size in bytes of the processor-internal data memory (use a power of 2).</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong><a href="#_processor_internal_instruction_cache_icache">Processor-Internal Instruction Cache (iCACHE)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ICACHE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the instruction cache.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ICACHE_NUM_BLOCKS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of blocks ("lines") Has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ICACHE_BLOCK_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Size in bytes of each block. Has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong><a href="#_processor_internal_data_cache_dcache">Processor-Internal Data Cache (dCACHE)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DCACHE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the data cache.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DCACHE_NUM_BLOCKS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of blocks ("lines"). Has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DCACHE_BLOCK_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Size in bytes of each block. Has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong><a href="#_processor_external_bus_interface_xbus">Processor-External Bus Interface (XBUS)</a> (Wishbone b4 protocol)</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the external bus interface.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_TIMEOUT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">255</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_REGSTAGE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement XBUS register stages to ease timing closure.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_CACHE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the external bus cache.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_CACHE_NUM_BLOCKS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of blocks ("lines"). Has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_CACHE_BLOCK_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Size in bytes of each block. Has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong><a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the execute in-place module.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_CACHE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement XIP cache.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_CACHE_NUM_BLOCKS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of blocks in XIP cache. Has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_CACHE_BLOCK_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">256</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of bytes per XIP cache block. Has to be a power of two, min 4.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong><a href="#_external_interrupt_controller_xirq">External Interrupt Controller (XIRQ)</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIRQ_NUM_CH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of channels of the external interrupt controller. Valid values are 0..32.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Peripheral/IO Modules</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_DISABLE_SYSINFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Disable <a href="#_system_configuration_information_memory_sysinfo">System Configuration Information Memory (SYSINFO)</a> module; โš ๏ธ not recommended - for advanced users only!</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_GPIO_NUM</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of general purpose input/output pairs of the <a href="#_general_purpose_input_and_output_port_gpio">General Purpose Input and Output Port (GPIO)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_MTIME_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_UART0_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">Primary Universal Asynchronous Receiver and Transmitter (UART0)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_UART0_RX_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART0 RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_UART0_TX_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART0 TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_UART1_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_secondary_universal_asynchronous_receiver_and_transmitter_uart1">Secondary Universal Asynchronous Receiver and Transmitter (UART1)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_UART1_RX_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART1 RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_UART1_TX_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART1 TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SPI_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_serial_peripheral_interface_controller_spi">Serial Peripheral Interface Controller (SPI)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SPI_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Depth of the <a href="#_serial_peripheral_interface_controller_spi">Serial Peripheral Interface Controller (SPI)</a> FIFO. Has to be a power of two, min 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SDI_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_serial_data_interface_controller_sdi">Serial Data Interface Controller (SDI)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SDI_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Depth of the <a href="#_serial_data_interface_controller_sdi">Serial Data Interface Controller (SDI)</a> FIFO. Has to be a power of two, min 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_TWI_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_two_wire_serial_interface_controller_twi">Two-Wire Serial Interface Controller (TWI)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_TWI_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Depth of the <a href="#_two_wire_serial_interface_controller_twi">Two-Wire Serial Interface Controller (TWI)</a> FIFO. Has to be a power of two, min 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_PWM_NUM_CH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of channels of the <a href="#_pulse_width_modulation_controller_pwm">Pulse-Width Modulation Controller (PWM)</a> to implement (0..16).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_WDT_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_watchdog_timer_wdt">Watchdog Timer (WDT)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_TRNG_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_true_random_number_generator_trng">True Random-Number Generator (TRNG)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_TRNG_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Depth of the TRNG data FIFO. Has to be a power of two, min 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CFS_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CFS_CONFIG</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">suv(31:0)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0x00000000</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Conduit" generic to pass user-defined flags to the <a href="#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CFS_IN_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Size of the <a href="#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a> input signal conduit (<code>cfs_in_i</code>).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CFS_OUT_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Size of the <a href="#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a> output signal conduit (<code>cfs_out_o</code>).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_NEOLED_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_smart_led_interface_neoled">Smart LED Interface (NEOLED)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_NEOLED_TX_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO depth of the the <a href="#_smart_led_interface_neoled">Smart LED Interface (NEOLED)</a>. Has to be a power of two, min 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_GPTMR_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_general_purpose_timer_gptmr">General Purpose Timer (GPTMR)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_ONEWIRE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_one_wire_serial_interface_controller_onewire">One-Wire Serial Interface Controller (ONEWIRE)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_DMA_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_direct_memory_access_controller_dma">Direct Memory Access Controller (DMA)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SLINK_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_stream_link_interface_slink">Stream Link Interface (SLINK)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SLINK_RX_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SLINK RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SLINK_TX_FIFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">natural</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SLINK TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CRC_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">false</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement the <a href="#_cyclic_redundancy_check_crc">Cyclic Redundancy Check (CRC)</a> unit.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_processor_clocking">2.3. Processor Clocking</h3> +<div class="paragraph"> +<p>The processor is implemented as fully-synchronous logic design using a single clock domain that is driven entirely +by the top&#8217;s <code>clk_i</code> signal. This clock signal is used by all internal registers and memories. All of them trigger +on the <strong>rising edge</strong> of this clock signal - the only exception it the default <a href="#_clock_gating">Clock Gating</a> module. External +"clocks" like the OCD&#8217;s JTAG clock or the SDI&#8217;s serial clock are synchronized into the processor&#8217;s clock domain +before being used as "general logic signal" (and not as a dedicated clock).</p> +</div> +<div class="sect3"> +<h4 id="_clock_gating">2.3.1. Clock Gating</h4> +<div class="paragraph"> +<p>The single clock domain of the processor can be split into an always-on clock domain and a switchable clock domain. +The switchable clock domain is used to clock the CPU core, the CPU&#8217;s bus switch and - if implemented - the caches. +This domain can be deactivated to reduce power consumption. The always-on clock domain is used to clock all other +processor modules like peripherals, memories and IO devices. Hence, these modules can continue operation (e.g. a +timer keeps running) even if the CPU is shut down.</p> +</div> +<div class="paragraph"> +<p>The splitting into two clock domain is enabled by the <code>CLOCK_GATING_EN</code> generic (<a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a>). +When enabled, a generic clock switching gate is added to decouple the switchable clock from the always-on clock domain +(VHDL file <code>neorv32_clockgate.vhd</code>). Whenever the CPU enters <a href="#_sleep_mode">Sleep Mode</a> the CPU clock domain ist shut down.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Clock Switch Hardware</div> +By default, a generic clock gate is used (<code>rtl/core/neorv32_clockgate.vhd</code>) to shut down the CPU clock. +Especially for FPGA setups it is highly recommended to replace this default version by a technology-specific primitive +or macro wrapper to improve efficiency (clock skew, global clock tree usage, etc.). +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_peripheral_clocks">2.3.2. Peripheral Clocks</h4> +<div class="paragraph"> +<p>Many processor modules like the UARTs or the timers provide a programmable time base for operations. In order to simplify +the hardware, the processor implements a global "clock generator" (<code>neorv32_sys.vhd</code>) that provides single-cycle <em>clock enables</em> +for certain frequencies which are derived from the main clock. These clock enable signals are synchronous to the system&#8217;s +main clock. The processor modules can use these enables for sub-main-clock operations while still providing a single +clock domain only.</p> +</div> +<div class="paragraph"> +<p>In total, 8 sub-main-clock signals are available. All processor modules, which feature a time-based configuration, provide a +programmable three-bit prescaler select in their control register to select one of the 8 available clocks. The +mapping of the prescaler select bits to the according clock source is shown in the table below. Here, <em>f</em> represents the +processor main clock from the top entity&#8217;s <code>clk_i</code> signal.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<colgroup> +<col style="width: 27.2727%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.091%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Prescaler bits:</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0b000</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0b001</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0b010</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0b011</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0b100</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0b101</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0b110</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0b111</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting clock:</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>f/2</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>f/4</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>f/8</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>f/64</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>f/128</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>f/1024</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>f/2048</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>f/4096</em></p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Power Saving</div> +If no peripheral modules requires a clock signal from the internal clock generator (all according modules are disabled by +clearing the enable bit in the according module&#8217;s control register) the generator is automatically deactivated to reduce +dynamic power consumption. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_processor_reset">2.4. Processor Reset</h3> +<div class="paragraph"> +<p>The NEORV32 processor includes a central reset sequencer (<code>neorv32_sys.vhd</code>) that handles all reset requests +and controls the internal reset nets. The processor-wide reset (aka "system reset") can be triggered by any +of the following sources:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>the asynchronous low-active <code>rstn_i</code> top entity input signal (External source)</p> +</li> +<li> +<p>the <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a> (internal source)</p> +</li> +<li> +<p>the <a href="#_watchdog_timer_wdt">Watchdog Timer (WDT)</a> (internal source)</p> +</li> +</ul> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Processor Reset Signal</div> +Make sure to connect the processor&#8217;s reset signal <code>rstn_i</code> to a valid reset source (a button, the "locked" +signal of a PLL, a dedicated reset controller, etc.). +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Reset Cause</div> +The actual reset cause can be determined via the <a href="#_watchdog_timer_wdt">Watchdog Timer (WDT)</a>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>If any of these sources triggers a reset, the internal system-wide reset will be active for at least 4 clock cycles ensuring +a valid reset of the entire processor. This system reset is asserted <em>asynchronoulsy</em> if triggered by the external +<code>rstn_i</code> signal and is asserted <em>synchronously</em> if triggered by an internal reset source. However, the system reset is +always de-asserted <em>synchronously</em> at the next rising clock edge.</p> +</div> +<div class="paragraph"> +<p>Internally, <strong>all registers</strong> that are not meant for mapping to blockRAM (like the register file) do provide a dedicated and +<strong>low-active asynchronous</strong> hardware reset. This asynchronous reset ensures that the entire processor logic is reset to a +defined state even if the main clock is not operational yet.</p> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_processor_interrupts">2.5. Processor Interrupts</h3> +<div class="paragraph"> +<p>The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Trigger Type</div> +All interrupt request lines are <strong>level-triggered and high-active</strong>. Once set, the signal should remain high until +the interrupt request is explicitly acknowledged (e.g. writing to a memory-mapped register). +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_risc_v_standard_interrupts">2.5.1. RISC-V Standard Interrupts</h4> +<div class="paragraph"> +<p>The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine +software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture +specifications. However, bare-metal system can also repurpose these interrupts. See CPU section +<a href="#_traps_exceptions_and_interrupts">Traps, Exceptions and Interrupts</a> for more information.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<colgroup> +<col style="width: 28.5714%;"> +<col style="width: 71.4286%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Top signal</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mtime_irq_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine timer interrupt from <em>processor-external</em> MTIME unit (<code>MTI</code>). This IRQ is only available if the processor-internal <a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a> unit is not implemented.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>msw_irq_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine software interrupt (<code>MSI</code>). This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mext_irq_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine external interrupt (<code>MEI</code>). This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_neorv32_specific_fast_interrupt_requests">2.5.2. NEORV32-Specific Fast Interrupt Requests</h4> +<div class="paragraph"> +<p>As part of the NEORV32-specific CPU extensions, the processor core features 16 fast interrupt request signals +(<code>FIRQ0</code> to <code>FIRQ15</code>) providing dedicated bits in the <a href="#_mip"><strong><code>mip</code></strong></a> and <a href="#_mie"><strong><code>mie</code></strong></a> CSRs and custom <a href="#_mcause"><strong><code>mcause</code></strong></a> trap codes. +The FIRQ signals are reserved for <em>processor-internal</em> modules only (for example for the communication +interfaces to signal "available incoming data" or "ready to send new data").</p> +</div> +<div class="paragraph"> +<p>The mapping of the 16 FIRQ channels to the according processor-internal modules is shown in the following +table (the channel number also corresponds to the according FIRQ priority: 0 = highest, 15 = lowest):</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 6. NEORV32 Fast Interrupt Request (FIRQ) Mapping</caption> +<colgroup> +<col style="width: 20%;"> +<col style="width: 20%;"> +<col style="width: 60%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Channel</th> +<th class="tableblock halign-left valign-top">Source</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_true_random_number_generator_trng">TRNG</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TRNG data available interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_custom_functions_subsystem_cfs">CFS</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Custom functions subsystem (CFS) interrupt (user-defined)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">UART0</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART0 RX FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">UART0</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART0 TX FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_secondary_universal_asynchronous_receiver_and_transmitter_uart1">UART1</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART1 RX FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">5</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_secondary_universal_asynchronous_receiver_and_transmitter_uart1">UART1</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART1 TX FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">6</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_serial_peripheral_interface_controller_spi">SPI</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_two_wire_serial_interface_controller_twi">TWI</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TWI FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_external_interrupt_controller_xirq">XIRQ</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">External interrupt controller interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">9</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_smart_led_interface_neoled">NEOLED</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">NEOLED TX FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">10</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_direct_memory_access_controller_dma">DMA</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">DMA transfer done interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_serial_data_interface_controller_sdi">SDI</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SDI FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">12</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_general_purpose_timer_gptmr">GPTMR</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">General purpose timer interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">13</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_one_wire_serial_interface_controller_onewire">ONEWIRE</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-wire idle interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">14</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_stream_link_interface_slink">SLINK</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SLINK RX FIFO level interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_stream_link_interface_slink">SLINK</a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SLINK TX FIFO level interrupt</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_address_space">2.6. Address Space</h3> +<div class="paragraph"> +<p>As a 32-bit architecture the NEORV32 can access a 4GB physical address space. By default, this address space is +split into six main regions. Each region provides specific <em>physical memory attributes</em> ("PMAs") that define +the access capabilities (<code>rwxac</code>; <code>r</code> = read permission, <code>w</code> = write permission, <code>x</code> - execute permission, +<code>a</code> = atomic access support, <code>c</code> = cached CPU access, <code>p</code> = privileged access only).</p> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/address_space.png" alt="900"> +</div> +<div class="title">Figure 2. NEORV32 Processor Address Space (Default Configuration)</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">The "Void" (Unmapped Addresses)</div> +All accesses to "unmapped" addresses (= "void") are redirected to the <a href="#_processor_external_bus_interface_xbus">Processor-External Bus Interface (XBUS)</a>. +For example, if the internal IMEM is disabled, the accesses to the <em>entire</em> address space between <code>0x00000000</code> and +<code>0x7FFFFFFF</code> are converted into XBUS requests. If the XBUS interface is not enabled any access to the void will +raise a bus error exception. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 7. Main Address Regions</caption> +<colgroup> +<col style="width: 7.1428%;"> +<col style="width: 28.5714%;"> +<col style="width: 14.2857%;"> +<col style="width: 50.0001%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">#</th> +<th class="tableblock halign-center valign-top">Region</th> +<th class="tableblock halign-center valign-top">PMAs</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">Internal IMEM address space</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>rwxac-</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">For instructions (=code) and constants; mapped to the internal <a href="#_instruction_memory_imem">Instruction Memory (IMEM)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">Internal DMEM address space</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>rwxac-</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">For application runtime data (heap, stack, etc.); mapped to the internal <a href="#_data_memory_dmem">Data Memory (DMEM)</a>).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">Memory-mapped XIP flash</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>r-xac-</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Memory-mapped access to the <a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a> SPI flash.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">Bootloader address space</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>r-xa-p</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Read-only memory for the internal <a href="#_bootloader_rom_bootrom">Bootloader ROM (BOOTROM)</a> containing the default <a href="#_bootloader">Bootloader</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">IO/peripheral address space</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>rwxa-p</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Processor-internal peripherals / IO devices.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">The "<strong>void</strong>"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>rwxac-</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Unmapped address space. All accesses to this region(s) are redirected to the <a href="#_processor_external_bus_interface_xbus">Processor-External Bus Interface (XBUS)</a> (if implemented).</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Privileged IO and BOOTROM Access Only</div> +Only privileged accesses (M-mode) to the IO/peripheral and bootloader address spaces are allowed. +If an unprivileged application tries to access this address space a bus access error exception is raised. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Custom PMAs</div> +Custom physical memory attributes enforced by the CPU&#8217;s <em>physcial memory protection</em> (<a href="#_smpmp_isa_extension"><code>Smpmp</code> ISA Extension</a>) +can be used to further constrain the physical memory attributes. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_bus_system">2.6.1. Bus System</h4> +<div class="paragraph"> +<p>The CPU can access all of the 32-bit address space from the instruction fetch interface and also from the data access +interface. Both CPU interfaces can be equipped with optional caches (<a href="#_processor_internal_data_cache_dcache">Processor-Internal Data Cache (dCACHE)</a> and +<a href="#_processor_internal_instruction_cache_icache">Processor-Internal Instruction Cache (iCACHE)</a>). The two CPU interfaces are multiplexed by a simple bus switch into +a <em>single processor-internal bus</em>. Optionally, this bus is further switched by another instance of the bus switch so the +<a href="#_direct_memory_access_controller_dma">Direct Memory Access Controller (DMA)</a> controller can also access the entire address space. Accesses via the +resulting SoC bus are split by the <a href="#_bus_gateway">Bus Gateway</a> that redirects accesses to the according main address regions +(see table above). Accesses to the processor-internal IO/peripheral devices are further redirected via a +dedicated <a href="#_io_switch">IO Switch</a>.</p> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/neorv32_bus.png" alt="1300"> +</div> +<div class="title">Figure 3. Processor-Internal Bus Architecture</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Bus System Infrastructure</div> +The components of the processor&#8217;s bus system infrastructure are located in <code>rtl/core/neorv32_bus.vhd</code>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Bus Interface</div> +See sections CPU <a href="#_architecture">Architecture</a> and <a href="#_bus_interface">Bus Interface</a> for more information regarding the CPU bus accesses. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_bus_gateway">2.6.2. Bus Gateway</h4> +<div class="paragraph"> +<p>The central bus gateway serves two purposes: <strong>redirect</strong> core accesses to the according modules (e.g. memory accesses +vs. memory-mapped IO accesses) and <strong>monitor</strong> all bus transactions. The redirection of access request is based on a +customizable memory map implemented via VHDL constants in the main package file (<code>rtl/core/neorv323_package.vhd</code>):</p> +</div> +<div class="listingblock"> +<div class="title">Listing 3. Main Address Regions Configuration in the VHDL Package File</div> +<div class="content"> +<pre class="highlight"><code class="language-vhdl" data-lang="vhdl">-- Main Address Regions --- +constant mem_imem_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; +constant mem_dmem_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; +constant mem_xip_base_c : std_ulogic_vector(31 downto 0) := x"e0000000"; +constant mem_xip_size_c : natural := 256*1024*1024; +constant mem_boot_base_c : std_ulogic_vector(31 downto 0) := x"ffffc000"; +constant mem_boot_size_c : natural := 8*1024; +constant mem_io_base_c : std_ulogic_vector(31 downto 0) := x"ffffe000"; +constant mem_io_size_c : natural := 8*1024;</code></pre> +</div> +</div> +<div class="paragraph"> +<p>Besides the delegation of bus requests the gateway also implements a bus monitor (aka "the bus keeper") that tracks all +active bus transactions to ensure <em>safe</em> and <em>deterministic</em> operations.</p> +</div> +<div class="paragraph"> +<p>Whenever a memory-mapped device is accessed (a real memory, a memory-mapped IO or some processor-external module) the bus +monitor starts an internal timer. The accessed module has to respond ("ACK") to the bus request within a specific +<strong>time window</strong>. This time window is defined by a global constant in the processor&#8217;s VHDL package file +(<code>rtl/core/neorv323_package.vhd</code>).</p> +</div> +<div class="listingblock"> +<div class="title">Listing 4. Internal Bus Timeout Configuration</div> +<div class="content"> +<pre class="highlight"><code class="language-vhdl" data-lang="vhdl"> constant bus_timeout_c : natural := 15;</code></pre> +</div> +</div> +<div class="paragraph"> +<p>This constant defines the <em>maximum</em> number of cycles after which a non-responding bus request (i.e. no <code>ack</code> +and no <code>err</code> signal) will time out raising a bus access fault exception. For example this can happen when accessing +"address space holes" - addresses that are not mapped to any physical module. The resulting exception type corresponds +to the according access type, i.e. instruction fetch access exception, load access exception or store access exception.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">XIP Timeout</div> +Accesses to the memory-mapped XIP flash (via the <a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a>) will <em>never</em> time out. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">External Bus Interface Timeout</div> +Accesses that are delegated to the external bus interface have a different maximum timeout value that is defined by an +explicit specific processor generic. See section <a href="#_processor_external_bus_interface_xbus">Processor-External Bus Interface (XBUS)</a> for more information. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_reservation_set_controller">2.6.3. Reservation Set Controller</h4> +<div class="paragraph"> +<p>The reservation set controller is responsible for handling the load-reservate and store-conditional bus transaction that +are triggered by the <code>lr.w</code> (LR) and <code>sc.w</code> (SC) instructions from the CPU&#8217;s <a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a>.</p> +</div> +<div class="paragraph"> +<p>A "reservation" defines an address or address range that provides a guarding mechanism to support atomic accesses. A new +reservation is registered by the LR instruction. The address provided by this instruction defines the memory location +that is now monitored for atomic accesses. The according SC instruction evaluates the state of this reservation. If +the reservation is still valid the write access triggered by the SC instruction is finally executed and the instruction +return a "success" state (<code>rd</code> = 0). If the reservation has been invalidated the SC instruction will not write to memory +and will return a "failed" state (<code>rd</code> = 1).</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Reservation Set(s) and Granule</div> +The reservation set controller supports only <strong>a single</strong> global reservation set with a <strong>word-aligned 4-byte granule</strong>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The reservation is invalidated if&#8230;&#8203;</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>an SC instruction is executed that accesses an address <strong>outside</strong> of the reservation set of the previous LR instruction. +This SC instruction will <strong>fail</strong> (not writing to memory).</p> +</li> +<li> +<p>an SC instruction is executed that accesses an address <strong>inside</strong> of the reservation set of the previous LR instruction. +This SC instruction will <strong>succeed</strong> (finally writing to memory).</p> +</li> +<li> +<p>a normal store operation accesses an address <strong>inside</strong> of the current reservation set (by the CPU or by the DMA).</p> +</li> +<li> +<p>a hardware reset is triggered.</p> +</li> +</ul> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Consecutive LR Instructions</div> +If an LR instruction is followed by another LR instruction the reservation set of the former one is overridden +by the reservation set of the latter one. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Bus Access Errors</div> +If the LR operation causes a bus access error (raising a load access exception) the reservation <strong>is registered anyway</strong>. +If the SC operation causes a bus access error (raising a store access exception) an already registered reservation set +<strong>is invalidated anyway</strong>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Strong Semantic</div> +The LR/SC mechanism follows the <em>strong semantic</em> approach: the LR/SC instruction pair fails only if there is a write +access to the referenced memory location between the LR and SC instructions (by the CPU itself or by the DMA). +Context changes, interrupts, traps, etc. do not effect nor invalidate the reservation state at all. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Physical Memory Attributes</div> +The reservation set can be set for <em>any</em> address (only constrained by the configured granularity). This also +includes cached memory, memory-mapped IO devices and processor-external address spaces. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>Bus transactions triggered by the LR instruction register a new reservation set and are delegated to the adressed +memory/device. Bus transactions triggered by the SC remove a reservation set and are forwarded to the adressed +memory/device only if the SC operations succeeds. Otherwise, the access request is not forwarded and a local ACK is +generated to terminate the bus transaction.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">LR/SC Bus Protocol</div> +More information regarding the LR/SC bus transactions and the the according protocol can be found in section +<a href="#_bus_interface">Bus Interface</a> / <a href="#_atomic_accesses">Atomic Accesses</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Cache Coherency</div> +Atomic operations <strong>always bypass</strong> the cache using direct/uncached accesses. Care must be taken +to maintain data cache coherency (e.g. by using the <code>fence</code> instruction). +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_io_switch">2.6.4. IO Switch</h4> +<div class="paragraph"> +<p>The IO switch further decodes the address when accessing the processor-internal IO/peripheral devices and forwards +the access request to the according module. Note that a total address space size of 256 bytes is assigned to each +IO module in order to simplify address decoding. The IO-specific address map is also defined in the main VHDL +package file (<code>rtl/core/neorv323_package.vhd</code>).</p> +</div> +<div class="listingblock"> +<div class="title">Listing 5. Exemplary Cut-Out from the IO Address Map</div> +<div class="content"> +<pre class="highlight"><code class="language-vhdl" data-lang="vhdl"> -- IO Address Map -- + constant iodev_size_c : natural := 256; -- size of a single IO device (bytes) + constant base_io_cfs_c : std_ulogic_vector(31 downto 0) := x"ffffeb00"; + constant base_io_slink_c : std_ulogic_vector(31 downto 0) := x"ffffec00"; + constant base_io_dma_c : std_ulogic_vector(31 downto 0) := x"ffffed00";</code></pre> +</div> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">IO Access Latency</div> +In order to shorten the critical path of the IO system, the IO switch contain a partial register stage that +buffers the address bus. Hence, accesses to the processor-internal IO region requires an additional clock cycle +to complete. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_boot_configuration">2.6.5. Boot Configuration</h4> +<div class="paragraph"> +<p>Due to the flexible memory configuration, the NEORV32 Processor provides several different boot scenarios. +The following section illustrates the two most common boot scenarios.</p> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/neorv32_boot_configurations.png" alt="800"> +</div> +<div class="title">Figure 4. NEORV32 Boot Configurations</div> +</div> +<div class="paragraph"> +<p>There are two general boot scenarios: <em>Indirect Boot</em> (1a and 1b) and <em>Direct Boot</em> (2a and 2b) configured via the +<code>INT_BOOTLOADER_EN</code> generic. If this generic is <code>true</code> the <em>indirect boot scenario</em> is used. This is also the +default boot configuration of the processor. If <code>INT_BOOTLOADER_EN</code> is <code>*false</code> the <em>direct boot scenario</em> is used.</p> +</div> +<div class="sect4"> +<h5 id="_indirect_boot">Indirect Boot</h5> +<div class="paragraph"> +<p>The indirect_boot scenarios <strong>1a</strong> and <strong>1b</strong> are based on the processor-internal <a href="#_bootloader">Bootloader</a>. This boot setup is enabled +by setting the <code>INT_BOOTLOADER_EN</code> generic to <code>true</code>, which will implement the processor-internal <a href="#_bootloader_rom_bootrom">Bootloader ROM (BOOTROM)</a>. +This read-only memory is pre-initialized during synthesis with the default bootloader firmware. The bootloader provides several +options to upload an executable copying it to the beginning of the <em>instruction address space</em> so the CPU can execute it.</p> +</div> +<div class="paragraph"> +<p>Boot scenario <strong>1a</strong> uses the processor-internal IMEM. This scenario implements the internal <a href="#_instruction_memory_imem">Instruction Memory (IMEM)</a> +as non-initialized RAM so the bootloader can copy the actual executable to it.</p> +</div> +<div class="paragraph"> +<p>Boot scenario <strong>1b</strong> uses a processor-external IMEM that is connected via the processor&#8217;s bus interface. In this scenario +the internal <a href="#_instruction_memory_imem">Instruction Memory (IMEM)</a> is not implemented at all and the bootloader will copy the executable to the +processor-external memory. Hence, the external memory has to be implemented as RAM.</p> +</div> +</div> +<div class="sect4"> +<h5 id="_direct_boot">Direct Boot</h5> +<div class="paragraph"> +<p>The direct boot scenarios <strong>2a</strong> and <strong>2b</strong> do not use the processor-internal bootloader since the <code>INT_BOOTLOADER_EN</code> +generic is set <code>false</code>. In this configuration the <a href="#_bootloader_rom_bootrom">Bootloader ROM (BOOTROM)</a> is not implemented at all and the CPU will +directly begin executing code from the beginning of the instruction address space after reset. An application-specific +"pre-initialization" mechanism is required in order to provide an executable inside the memory.</p> +</div> +<div class="paragraph"> +<p>Boot scenario <strong>2a</strong> uses the processor-internal IMEM implemented as <em>read-only memory</em> in this scenario. +It is pre-initialized (by the bitstream) with the actual application executable during synthesis.</p> +</div> +<div class="paragraph"> +<p>In contrast, boot scenario <strong>2b</strong> uses a processor-external IMEM. In this scenario the system designer is responsible for +providing an initialized external memory that contains the actual application to be executed.</p> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_processor_internal_modules">2.7. Processor-Internal Modules</h3> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Privileged IO Access Only</div> +Only privileged accesses (M-mode) to the IO/peripheral modules are allowed. If an unprivileged application +tries to access this address space a bus access error exception is raised. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Full-Word Write Accesses Only</div> +All peripheral/IO devices should only be written in full-word mode (i.e. 32-bit). Byte or half-word (8/16-bit) write accesses +might cause undefined behavior. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Writing to Read-Only Registers</div> +Unless otherwise specified, writing to registers that are listed as read-only does not trigger an exception. +The write access is simply ignored by the corresponding hardware module. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">IO Module&#8217;s Address Space</div> +Each peripheral/IO module occupies an address space of 256 bytes (64 words). Most devices do not fully utilize this address +space and will simply <em>mirror</em> the available interface registers across the entire 256 bytes of address space. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Unimplemented Modules / Address Holes</div> +When accessing an IO device that hast not been implemented (disabled via the according generic) +or when accessing an address that is actually unused, a load/store access fault exception is raised. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Module Interrupts</div> +Several peripheral/IO devices provide some kind of interrupt. These interrupts are mapped to the CPU&#8217;s +<a href="#_custom_fast_interrupt_request_lines">Custom Fast Interrupt Request Lines</a>. See section <a href="#_processor_interrupts">Processor Interrupts</a> for more information. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">CMSIS System Description View (SVD)</div> +A CMSIS-compatible <strong>System View Description (SVD)</strong> file including all peripherals is available in <code>sw/svd</code>. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +<div class="sect3"> +<h4 id="_instruction_memory_imem">2.7.1. Instruction Memory (IMEM)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_imem.vhd</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">default platform-agnostic instruction memory</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>implicitly used</em></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM_INT_IMEM_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement processor-internal IMEM when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM_INT_IMEM_SIZE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">IMEM size in bytes (use a power of 2)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>INT_BOOTLOADER_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">use internal bootloader when <code>true</code> (implements IMEM as <em>uninitialized</em> RAM, otherwise the IMEM is implemented an <em>pre-intialized</em> ROM)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">none / read-only if <code>INT_BOOTLOADER_EN = true</code></p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>Implementation of the processor-internal instruction memory is enabled by the processor&#8217;s +<code>MEM_INT_IMEM_EN</code> generic. The total memory size in bytes is defined via the <code>MEM_INT_IMEM_SIZE</code> generic. +Note that this size should be a power of two to optimize physical implementation. If the IMEM is implemented, +it is mapped to base address <code>0x00000000</code> by default (see section <a href="#_address_space">Address Space</a>).</p> +</div> +<div class="paragraph"> +<p>By default the IMEM is implemented as true RAM so the content can be modified during run time. This is +required when using the bootloader (or the on-chip debugger) so it can update the content of the IMEM at +any time. If this feature is not required the IMEM can be implemented as <em>pre-intialized</em> ROM so that the +application code permanently resides in memory. This is automatically implemented when the +processor-internal bootloader is disabled (<code>INT_BOOTLOADER_EN</code> = <code>false</code>).</p> +</div> +<div class="paragraph"> +<p>When the IMEM is implemented as ROM, it will be initialized during synthesis with the actual application program +image. The compiler toolchain provides an option to generate and override the default VHDL initialization file +<code>rtl/core/neorv32_application_image.vhd</code>, which is automatically inserted into the IMEM. If the IMEM is implemented +as RAM (default), the memory block will <strong>not be initialized at all</strong>.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Platform-Specific Memory Primitives</div> +If required, the default IMEM can be replaced by a platform-/technology-specific primitive to +optimize area utilization, timing and power consumption. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Memory Size</div> +If the configured memory size (via the <code>MEM_INT_IMEM_SIZE</code> generic) is not a power of two the actual memory +size will be auto-adjusted to the next power of two (e.g. configuring a memory size of 60kB will result in a +physical memory size of 64kB). +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Legacy HDL Style</div> +If synthesis fails to infer block RAM for the IMEM, turn on the <code>alternaitve_style_en_c</code> option inside +the memory&#8217;s VHDL source file. When enabled, a different HDL style is used to describe the memory core. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Read-Only Access</div> +If the IMEM is implemented as true ROM any write attempt to it will raise a <em>store access fault</em> exception. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_data_memory_dmem">2.7.2. Data Memory (DMEM)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_dmem.vhd</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">default platform-agnostic data memory</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>implicitly used</em></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM_INT_DMEM_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement processor-internal DMEM when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM_INT_DMEM_SIZE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">DMEM size in bytes (use a power of 2)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">none</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>Implementation of the processor-internal data memory is enabled by the processor&#8217;s <code>MEM_INT_DMEM_EN</code> +generic. The total memory size in bytes is defined via the <code>MEM_INT_DMEM_SIZE</code> generic. Note that this +size should be a power of two to optimize physical implementation. If the DMEM is implemented, +it is mapped to base address <code>0x80000000</code> by default (see section <a href="#_address_space">Address Space</a>). +The DMEM is always implemented as true RAM.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Platform-Specific Memory Primitives</div> +If required, the default DMEM can be replaced by a platform-/technology-specific primitive to +optimize area utilization, timing and power consumption. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Memory Size</div> +If the configured memory size (via the <code>MEM_INT_DMEM_SIZE</code> generic) is not a power of two the actual memory +size will be auto-adjusted to the next power of two (e.g. configuring a memory size of 60kB will result in a +physical memory size of 64kB). +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Legacy HDL Style</div> +If synthesis fails to infer block RAM for the DMEM, turn on the <code>alternaitve_style_en_c</code> option inside +the memory&#8217;s VHDL source file. When enabled, a different HDL style is used to describe the memory core. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Execute from RAM</div> +The CPU is capable of executing code also from arbitrary data memory. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_bootloader_rom_bootrom">2.7.3. Bootloader ROM (BOOTROM)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_boot_rom.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>INT_BOOTLOADER_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement processor-internal bootloader when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, read-only</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>This boot ROM module provides a read-only memory that contain the executable image of the default NEORV32 +<a href="#_bootloader">Bootloader</a>. If the internal bootloader is enabled via the <code>INT_BOOTLOADER_EN</code> generic the CPU&#8217;s boot address +is automatically set to the beginning of the bootloader ROM. See sections <a href="#_address_space">Address Space</a> and +<a href="#_boot_configuration">Boot Configuration</a> for more information regarding the processor&#8217;s different boot scenarios.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Memory Size</div> +If the configured boot ROM size is <strong>not</strong> a power of two the actual memory size will be auto-adjusted to +the next power of two (e.g. configuring a memory size of 6kB will result in a physical memory size of 8kB). +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Bootloader Image</div> +The boot ROM is initialized during synthesis with the default bootloader image +(<code>rtl/core/neorv32_bootloader_image.vhd</code>). +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_processor_internal_instruction_cache_icache">2.7.4. Processor-Internal Instruction Cache (iCACHE)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_cache.vhd</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generic cache module</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>implicitly used</em></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ICACHE_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement processor-internal instruction cache when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ICACHE_NUM_BLOCKS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of cache blocks (pages/lines)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ICACHE_BLOCK_SIZE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">size of a cache block in bytes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">none</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The processor features an optional instruction cache to improve performance when using memories with high +access latencies. The cache is connected directly to the CPU&#8217;s instruction fetch interface and provides +full-transparent accesses. The cache is direct-mapped and read-only.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Cached/Uncached Accesses</div> +The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the +processor-internal IO/peripheral modules). All accesses that target the address range from <code>0xF0000000</code> to <code>0xFFFFFFFF</code> +will not be cached at all (see section <a href="#_address_space">Address Space</a>). Direct/uncached accesses have <strong>lower</strong> priority than +cache block operations to allow continuous burst transfer and also to maintain logical instruction forward +progress / data coherency. Furthermore, atomic load-reservate and store-conditional instructions (<a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a>) +will always <strong>bypass</strong> the cache. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Caching Internal Memories</div> +The data cache is intended to accelerate data access to <strong>processor-external</strong> memories. +The CPU cache(s) should not be implemented when using only processor-internal data and instruction memories. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Manual Cache Clear/Reload</div> +By executing the <code>fence(.i)</code> instruction the cache is cleared and a reload from main memory is triggered. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Retrieve Cache Configuration from Software</div> +Software can retrieve the cache configuration/layout from the <a href="#_sysinfo_cache_configuration">SYSINFO - Cache Configuration</a> register. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Bus Access Fault Handling</div> +The cache always loads a complete cache block (aligned to the block size) every time a +cache miss is detected. Each cached word from this block provides a single status bit that indicates if the +according bus access was successful or caused a bus error. Hence, the whole cache block remains valid even +if certain addresses inside caused a bus error. If the CPU accesses any of the faulty cache words, an +instruction bus error exception is raised. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_processor_internal_data_cache_dcache">2.7.5. Processor-Internal Data Cache (dCACHE)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_cache.vhd</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generic cache module</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>implicitly used</em></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DCACHE_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement processor-internal data cache when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DCACHE_NUM_BLOCKS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of cache blocks (pages/lines)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DCACHE_BLOCK_SIZE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">size of a cache block in bytes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">none</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The processor features an optional data cache to improve performance when using memories with high +access latencies. The cache is connected directly to the CPU&#8217;s data access interface and provides +full-transparent accesses. The cache is direct-mapped and uses "write-allocate" and "write-back" strategies.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Cached/Uncached Accesses</div> +The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the +processor-internal IO/peripheral modules). All accesses that target the address range from <code>0xF0000000</code> to <code>0xFFFFFFFF</code> +will not be cached at all (see section <a href="#_address_space">Address Space</a>). Direct/uncached accesses have <strong>lower</strong> priority than +cache block operations to allow continuous burst transfer and also to maintain logical instruction forward +progress / data coherency. Furthermore, atomic load-reservate and store-conditional instructions (<a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a>) +will always <strong>bypass</strong> the cache. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Caching Internal Memories</div> +The data cache is intended to accelerate data access to <strong>processor-external</strong> memories. +The CPU cache(s) should not be implemented when using only processor-internal data and instruction memories. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Manual Cache Flush/Clear/Reload</div> +By executing the <code>fence(.i)</code> instruction the cache is flushed, cleared and a reload from main memory is triggered. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Retrieve Cache Configuration from Software</div> +Software can retrieve the cache configuration/layout from the <a href="#_sysinfo_cache_configuration">SYSINFO - Cache Configuration</a> register. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Bus Access Fault Handling</div> +The cache always loads a complete cache block (aligned to the block size) every time a +cache miss is detected. Each cached word from this block provides a single status bit that indicates if the +according bus access was successful or caused a bus error. Hence, the whole cache block remains valid even +if certain addresses inside caused a bus error. If the CPU accesses any of the faulty cache words, a +data bus error exception is raised. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_direct_memory_access_controller_dma">2.7.6. Direct Memory Access Controller (DMA)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_dma.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_dma.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_dma.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_DMA_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement DMA when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 10</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">DMA transfer done (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The NEORV32 DMA provides a small-scale scatter/gather direct memory access controller that allows to transfer and +modify data independently of the CPU. A single read/write transfer channel is implemented that is configured via +memory-mapped registers. a configured transfer can either be triggered manually or by a programmable CPU FIRQ interrupt +(see <a href="#_neorv32_specific_fast_interrupt_requests">NEORV32-Specific Fast Interrupt Requests</a>).</p> +</div> +<div class="paragraph"> +<p>The DMA is connected to the central processor-internal bus system (see section <a href="#_address_space">Address Space</a>) and can access the same +address space as the CPU core. It uses <em>interleaving mode</em> accessing the central processor bus only if the CPU does not +currently request and bus access.</p> +</div> +<div class="paragraph"> +<p>The controller can handle different data quantities (e.g. read bytes and write them back as sign-extend words) and can +also change the Endianness of data while transferring.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">DMA Demo Program</div> +A DMA example program can be found in <code>sw/example/demo_dma</code>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The DMA provides four memory-mapped interface registers: A status and control register <code>CTRL</code> and three registers for +configuring the actual DMA transfer. The base address of the source data is programmed via the <code>SRC_BASE</code> register. +Vice versa, the base address of the destination data is programmed via the <code>DST_BASE</code>. The third configuration register +<code>TTYPE</code> is use to configure the actual transfer type and the number of elements to transfer.</p> +</div> +<div class="paragraph"> +<p>The DMA is enabled by setting the <code>DMA_CTRL_EN</code> bit of the control register. Manual trigger mode (i.e. the DMA transfer is +triggered by writing to the <code>TTYPE</code> register) is selected if <code>DMA_CTRL_AUTO</code> is cleared. Alternatively, the DMA transfer can +be triggered by a processor internal FIRQ signal if <code>DMA_CTRL_AUTO</code> is set (see section below).</p> +</div> +<div class="paragraph"> +<p>The DMA uses a load-modify-write data transfer process. Data is read from the bus system, internally modified and then written +back to the bus system. This combination is implemented as an atomic progress, so canceling the current transfer by clearing the +<code>DMA_CTRL_EN</code> bit will stop the DMA right after the current load-modify-write operation.</p> +</div> +<div class="paragraph"> +<p>If the DMA controller detects a bus error during operation, it will set either the <code>DMA_CTRL_ERROR_RD</code> (error during +last read access) or <code>DMA_CTRL_ERROR_WR</code> (error during last write access) and will terminate the current transfer. +Software can read the <code>SRC_BASE</code> or <code>DST_BASE</code> register to retrieve the address that caused the according error. +Alternatively, software can read back the <code>NUM</code> bits of the control register to determine the index of the element +that caused the error. The error bits are automatically cleared when starting a new transfer.</p> +</div> +<div class="paragraph"> +<p>When the <code>DMA_CTRL_DONE</code> flag is set the DMA has actually executed a transfer. However, the <code>DMA_CTRL_ERROR_*</code> flags +should also be checked to verify that the executed transfer completed without errors. The <code>DMA_CTRL_DONE</code> flag is +automatically cleared when writing the <code>CTRL</code> register.</p> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">DMA Access Privilege Level</div> +Transactions performed by the DMA are executed as bus transactions with elevated <strong>machine-mode</strong> privilege level. +Note that any physical memory protection rules (<a href="#_smpmp_isa_extension"><code>Smpmp</code> ISA Extension</a>) are not applied to DMA transfers. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Transfer Configuration</strong></p> +</div> +<div class="paragraph"> +<p>If the DMA is set to <strong>manual trigger mode</strong> (<code>DMA_CTRL_AUTO</code> = 0) writing the <code>TTRIG</code> register will start the +programmed DMA transfer. Once started, the DMA will read one data quantity from the source address, processes it internally +and then will write it back to the destination address. The <code>DMA_TTYPE_NUM</code> bits of the <code>TTYPE</code> register define how many +times this process is repeated by specifying the number of elements to transfer.</p> +</div> +<div class="paragraph"> +<p>Optionally, the source and/or destination addresses can be increments according to the data quantities +automatically by setting the according <code>DMA_TTYPE_SRC_INC</code> and/or <code>DMA_TTYPE_DST_INC</code> bit.</p> +</div> +<div class="paragraph"> +<p>Four different transfer quantities are available, which are configured via the <code>DMA_TTYPE_QSEL</code> bits:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>00</code>: Read source data as byte, write destination data as byte</p> +</li> +<li> +<p><code>01</code>: Read source data as byte, write destination data as zero-extended word</p> +</li> +<li> +<p><code>10</code>: Read source data as byte, write destination data as sign-extended word</p> +</li> +<li> +<p><code>11</code>: Read source data as word, write destination data as word</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>Optionally, the DMA controller can automatically convert Endianness of the transferred data if the <code>DMA_TTYPE_ENDIAN</code> +bit is set.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Address Alignment</div> +Make sure to align the source and destination base addresses to the according transfer data quantities. For instance, +word-to-word transfers require that the two LSB of <code>SRC_BASE</code> and <code>DST_BASE</code> are cleared. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Writing to IO Device</div> +When writing data to IO / peripheral devices (for example to the <a href="#_cyclic_redundancy_check_crc">Cyclic Redundancy Check (CRC)</a>) the destination +data quantity has to be set to <strong>word</strong> (32-bit) since all IO registers can only be written in full 32-bit word mode. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Automatic Trigger</strong></p> +</div> +<div class="paragraph"> +<p>As an alternative to the manual trigger mode, the DMA can be set to <strong>automatic trigger mode</strong> starting a pre-configured +transfer if a specific processor-internal peripheral issues a FIRQ interrupt request. The automatic trigger mode is enabled by +setting the <code>CTRL</code> register&#8217;s <code>DMA_CTRL_AUTO</code> bit. In this configuration <em>no</em> transfer is started when writing to the DMA&#8217;s +<code>TTYPE</code> register.</p> +</div> +<div class="paragraph"> +<p>The actually triggering FIRQ channel is configured via the control register&#8217;s <code>DMA_CTRL_FIRQ_SEL</code> bits. Writing a 0 will +select FIRQ channel 0, writing a 1 will select FIRQ channel 1, and so on. See section <a href="#_processor_interrupts">Processor Interrupts</a> +for a list of all FIRQ channels and their according sources.</p> +</div> +<div class="paragraph"> +<p>The FIRQ trigger can operate in two trigger mode configured via the <code>DMA_CTRL_FIRQ_TYPE</code> flag:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>DMA_CTRL_FIRQ_TYPE = 0</code>: trigger the automatic DMA transfer on a rising-edge of the selected FIRQ channel (e.g. trigger +DMA transfer only once)</p> +</li> +<li> +<p><code>DMA_CTRL_FIRQ_TYPE = 1</code>: trigger the automatic DMA transfer when the selected FIRQ channel is active (e.g. trigger +DMA transfer again and again)</p> +</li> +</ul> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">FIRQ Trigger</div> +The DMA transfer will start if a <strong>rising edge</strong> is detected on the configured FIRQ channel. Hence, the DMA is triggered only +once even if the selected FIRQ channel keeps pending. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Memory Barrier / Fence Operation</strong></p> +</div> +<div class="paragraph"> +<p>Optionally, the DMA can issue a FENCE request to the downstream memory system when a transfer has been completed +without errors. This can be used to re-sync caches (flush and reload) and buffers to maintain data coherency. +This automatic fencing is enabled by the setting the control register&#8217;s <code>DMA_CTRL_FENCE</code> bit.</p> +</div> +<div class="paragraph"> +<p><strong>DMA Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>The DMA features a single CPU interrupt that is triggered when the programmed transfer has completed. This +interrupt is also triggered if the DMA encounters a bus error during operation. The interrupt will remain pending +until the control register&#8217;s <code>DMA_CTRL_DONE</code> is cleared (this will happen upon any write access to the control +register).</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 8. DMA Register Map (<code>struct NEORV32_DMA</code>)</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 26.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 46.6669%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="12"><p class="tableblock"><code>0xffffed00</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="12"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>DMA_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">DMA module enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> <code>DMA_CTRL_AUTO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable automatic mode (FIRQ-triggered)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>2</code> <code>DMA_CTRL_FENCE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Issue a downstream FENCE operation when DMA transfer completes (without errors)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:3</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>8</code> <code>DMA_CTRL_ERROR_RD</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Error during read access, clears when starting a new transfer</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>9</code> <code>DMA_CTRL_ERROR_WR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Error during write access, clears when starting a new transfer</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>10</code> <code>DMA_CTRL_BUSY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">DMA transfer in progress</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>11</code> <code>DMA_CTRL_DONE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/c</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set if a transfer was executed; auto-clears on write-access</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>14:12</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>15</code> <code>DMA_CTRL_FIRQ_TYPE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger on rising-edge (<code>0</code>) or high-level (<code>1</code>) or selected FIRQ channel</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>19:16</code> <code>DMA_CTRL_FIRQ_SEL_MSB : DMA_CTRL_FIRQ_SEL_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FIRQ trigger select (FIRQ0=0 &#8230;&#8203; FIRQ15=15)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:20</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffed04</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SRC_BASE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Source base address (shows the last-accessed source address when read)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffed08</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DST_BASE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Destination base address (shows the last-accessed destination address when read)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="6"><p class="tableblock"><code>0xffffed0c</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="6"><p class="tableblock"><code>TTYPE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>23:0</code> <code>DMA_TTYPE_NUM_MSB : DMA_TTYPE_NUM_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of elements to transfer (shows the last-transferred element index when read)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>26:24</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>28:27</code> <code>DMA_TTYPE_QSEL_MSB : DMA_TTYPE_QSEL_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Quantity select (<code>00</code> = byte &#8594; byte, <code>01</code> = byte &#8594; zero-extended-word, <code>10</code> = byte &#8594; sign-extended-word, <code>11</code> = word &#8594; word)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>29</code> <code>DMA_TTYPE_SRC_INC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Constant (<code>0</code>) or incrementing (<code>1</code>) source address</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>DMA_TTYPE_DST_INC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Constant (<code>0</code>) or incrementing (<code>1</code>) destination address</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>DMA_TTYPE_ENDIAN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Swap Endianness when set</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_processor_external_bus_interface_xbus">2.7.7. Processor-External Bus Interface (XBUS)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_xbus.vhd</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">External bus gateway</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_cache.vhd</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generic cache module</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>implicitly used</em></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_adr_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">address output (32-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_dat_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">data output (32-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_tag_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">access tag (3-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_we_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">write enable (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_sel_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">byte enable (4-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_stb_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">bus strobe (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_cyc_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">valid cycle (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_dat_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">data input (32-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_ack_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">acknowledge (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xbus_err_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">bus error (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">enable external bus interface when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_TIMEOUT</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_REGSTAGE_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement XBUS register stages</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_CACHE_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement the external bus cache</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_CACHE_NUM_BLOCKS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of blocks ("lines"), has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XBUS_CACHE_BLOCK_SIZE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">size in bytes of each block, has to be a power of two.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">none</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The external bus interface provides a <strong>Wishbone b4</strong>-compatible on-chip bus interface that is +implemented if the <code>XBUS_EN</code> generic is <code>true</code>. This bus interface can be used to attach processor-external +modules like memories, custom hardware accelerators or additional peripheral devices. +An optional cache module ("XCACHE") can be enabled to improve memory access latency.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Address Mapping</div> +The external interface is <strong>not</strong> mapped to a specific address space. Instead, all CPU memory accesses that +do not target a specific (and actually implemented) processor-internal address region (hence, accessing the "void"; +see section <a href="#_address_space">Address Space</a>) are <strong>redirected</strong> to the external bus interface. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">AXI4-Lite Interface Bridge</div> +A processor top entity with an AXI4-Lite-compatible bus interface can be found in <code>rtl/system_inegration</code>. +More information regarding this alternate top entity can be found in in the user guide: +<a href="https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block" class="bare">https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block</a> +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">AHB3-Lite Interface Bridge</div> +A simple bridge that converts the processor&#8217;s XBUS into an AHB3-lite-compatible host interface can +be found in in <code>rtl/system_inegration</code> (<code>xbus2ahblite_bridge.vhd</code>). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Wishbone Bus Protocol</strong></p> +</div> +<div class="paragraph"> +<p>The external bus interface complies to the <strong>pipelined Wishbone b4</strong> protocol. Even though this protocol +was explicitly designed to support pipelined transfers, only a single transfer will be "in fly" at once. +Hence, just two types of bus transactions are generated by the XBUS controller (see images below).</p> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/xbus_write.png" alt="700"> +</div> +<div class="title">Figure 5. XBUS/Wishbone Write Transaction</div> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/xbus_read.png" alt="700"> +</div> +<div class="title">Figure 6. XBUS/Wishbone Read Transaction</div> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Wishbone "Classic" Protocol</div> +Native support for the "classic" Wishbone protocol has been deprecated. +However, classic mode can still be <em>emulated</em> by connecting the processor&#8217;s <code>xbus_cyc_o</code> directly to the +device&#8217;s / bus system&#8217;s <code>cyc</code> and <code>stb</code> signals (omitting the processor&#8217;s <code>xbus_stb_o</code> signal). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Endianness</div> +Just like the processor itself the XBUS interface uses <strong>little-endian</strong> byte order. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Wishbone Specs.</div> +A detailed description of the implemented Wishbone bus protocol and the according interface signals +can be found in the data sheet "Wishbone B4 - WISHBONE System-on-Chip (SoC) Interconnection +Architecture for Portable IP Cores". A copy of this document can be found in the <code>docs</code> folder of this +project. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>An accessed XBUS/Wishbone device does not have to respond immediately to a bus request by sending an <code>ACK</code>. +Instead, there is a <strong>time window</strong> where the device has to acknowledge the transfer. This time window +is configured by the <code>XBUS_TIMEOUT</code> generic and it defines the maximum time (in clock cycles) a bus access can +be pending before it is automatically terminated raising an bus fault exception. If <code>XBUS_TIMEOUT</code> is set to zero, +the timeout is disabled and a bus access can take an arbitrary number of cycles to complete. Note that this is not +recommended as a missing ACK will permanently stall the entire processor!</p> +</div> +<div class="paragraph"> +<p>Furthermore, an accesses XBUS/Wishbone device can signal an error condition at any time by setting the <code>ERR</code> signal +high for one cycle. This will also terminate the current bus transaction before raising a CPU bus fault exception.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Register Stage</div> +An optional register stage can be added to the XBUS gateway to break up the critical path easing timing closure. +When <code>XBUS_REGSTAGE_EN</code> is <em>true</em> all outgoing and incoming XBUS signals are registered increasing access latency +by two cycles. Furthermore, all outgoing signals (like the address) will be kept stable if there is no bus access +being initiated. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Access Tag</strong></p> +</div> +<div class="paragraph"> +<p>The XBUS tag signal <code>xbus_tag_o(0)</code> provides additional information about the current access cycle. +It compatible to the the AXI4 <code>ARPROT</code> and <code>AWPROT</code> signals.</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>xbus_tag_o(0)</code> <strong>P</strong>: access is performed from <strong>privileged</strong> mode (machine-mode) when set</p> +</li> +<li> +<p><code>xbus_tag_o(1)</code> <strong>NS</strong>: this bit is hardwired to <code>0</code> indicating a <strong>secure</strong> access</p> +</li> +<li> +<p><code>xbus_tag_o(2)</code> <strong>I</strong>: access is an <strong>instruction</strong> fetch when set; access is a data access when cleared</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>External Bus Cache (X-CACHE)</strong></p> +</div> +<div class="paragraph"> +<p>The XBUS interface provides an optional internal cache that can be used to buffer processor-external accesses. +The x-cache is enabled via the <code>XBUS_CACHE_EN</code> generic. The total size of the cache is split into the number of +cache lines or cache blocks (<code>XBUS_CACHE_NUM_BLOCKS</code> generic) and the line or block size in bytes +(<code>XBUS_CACHE_BLOCK_SIZE</code> generic).</p> +</div> +<div class="listingblock"> +<div class="title">Listing 6. Simplified X-Cache Architecture</div> +<div class="content"> +<pre class="highlight"><code class="language-asciiart" data-lang="asciiart"> Direct Access +----------+ + /|-------------------------&gt;| Register |------------------------&gt;|\ + | | +----------+ | | +Core ---&gt;| | | |---&gt; XBUS + | | +--------------+ +--------------+ +-------------+ | | + \|---&gt;| Host Arbiter |---&gt;| Cache Memory |&lt;---| Bus Arbiter |---&gt;|/ + +--------------+ +--------------+ +-------------+</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The cache uses a direct-mapped architecture that implements "write-allocate" and "write-back" strategies. +The <strong>write-allocate</strong> strategy will fetch the entire referenced block from main memory when encountering +a cache write-miss. The <strong>write-back</strong> strategy will gather all writes locally inside the cache until the according +cache block is about to be replaced. In this case, the entire modified cache block is written back to main memory.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Cached/Uncached Accesses</div> +The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO. +All accesses that target the address range from <code>0xF0000000</code> to <code>0xFFFFFFFF</code> +will not be cached at all (see section <a href="#_address_space">Address Space</a>). Direct/uncached accesses have <strong>lower</strong> priority than +cache block operations to allow continuous burst transfer and also to maintain logical instruction forward +progress / data coherency. Furthermore, atomic load-reservate and store-conditional instructions (<a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a>) +will always <strong>bypass</strong> the cache. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_stream_link_interface_slink">2.7.8. Stream Link Interface (SLINK)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_slink.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_slink.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_slink.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_dat_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX link data (32-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_src_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX routing information (4-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_val_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX link data valid (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_lst_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX link last element of stream (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_rx_rdy_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX link ready to receive (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_dat_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX link data (32-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_dst_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX routing information (4-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_val_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX link data valid (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_lst_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX link last element of stream (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>slink_tx_rdy_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX link allowed to send (1-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SLINK_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement SLINK when <em>true</em></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SLINK_RX_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO depth (1..32k), has to be a power of two, min 1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SLINK_TX_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO depth (1..32k), has to be a power of two, min 1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 14</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX SLINK IRQ (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 15</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX SLINK IRQ (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The stream link interface provides independent RX and TX channels for sending and receiving +stream data. Each channel features a configurable internal FIFO to buffer stream data +(<code>IO_SLINK_RX_FIFO</code> for the RX FIFO, <code>IO_SLINK_TX_FIFO</code> for the TX FIFO). The SLINK interface provides higher +bandwidth and less latency than the external bus interface making it ideally suited for coupling custom +stream processors or streaming peripherals.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Example Program</div> +An example program for the SLINK module is available in <code>sw/example/demo_slink</code>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Interface &amp; Protocol</strong></p> +</div> +<div class="paragraph"> +<p>The SLINK interface consists of four signals for each channel:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>dat</code> contains the actual data word</p> +</li> +<li> +<p><code>val</code> marks the current transmission cycle as valid</p> +</li> +<li> +<p><code>lst</code> marks the current transmission cycle as the last element of a stream</p> +</li> +<li> +<p><code>rdy</code> indicates that the receiver is ready to receive</p> +</li> +<li> +<p><code>src</code> and <code>dst</code> provide source/destination routing information (optional)</p> +</li> +</ul> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">AXI4-Stream Compatibility</div> +The interface names (except for <code>src</code> and <code>dst</code>) and the underlying protocol is compatible to the AXI4-Stream protocol standard. +A processor top entity with a AXI4-Stream-compatible interfaces can be found in <code>rtl/system_inegration</code>. +More information regarding this alternate top entity can be found in in the user guide: +<a href="https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block" class="bare">https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block</a> +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The SLINK provides four interface registers. The control register (<code>CTRL</code>) is used to configure +the module and to check its status. Two individual data registers (<code>DATA</code> and <code>DATA_LAST</code>) +are used to send and receive the link&#8217;s actual data stream.</p> +</div> +<div class="paragraph"> +<p>The <code>DATA</code> register provides direct access to the RX/TX FIFO buffers. Read accesses return data from the RX FIFO. +After reading data from this register the control register&#8217;s <code>SLINK_CTRL_RX_LAST</code> flag can be checked to determine +if the according data word has been marked as "end of stream" via the <code>slink_rx_lst_i</code> signal (this signal is also +buffered by the link&#8217;s FIFO). +Writing to the <code>DATA</code> register will immediately write to the TX link FIFO. +When writing to the <code>TX_DATA_LAST</code> the according data word will also be marked as "end of stream" via the +<code>slink_tx_lst_o</code> signal (this signal is also buffered by the link&#8217;s FIFO).</p> +</div> +<div class="paragraph"> +<p>The configured FIFO sizes can be retrieved by software via the control register&#8217;s <code>SLINK_CTRL_RX_FIFO_*</code> and +<code>SLINK_CTRL_TX_FIFO_*</code> bits.</p> +</div> +<div class="paragraph"> +<p>The SLINK is globally activated by setting the control register&#8217;s enable bit <code>SLINK_CTRL_EN</code>. Clearing this bit will +reset all internal logic and will also clear both FIFOs. The FIFOs can also be cleared manually at any time by +setting the <code>SLINK_CTRL_RX_CLR</code> and/or <code>SLINK_CTRL_TX_CLR</code> bits (these bits will auto-clear).</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">FIFO Overflow</div> +Writing to the TX channel&#8217;s FIFO while it is <em>full</em> will have no effect. Reading from the RX channel&#8217;s FIFO while it +is <em>empty</em> will also have no effect and will return the last received data word. There is no overflow indicator +implemented yet. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The current status of the RX and TX FIFOs can be determined via the control register&#8217;s <code>SLINK_CTRL_RX_*</code> and +<code>SLINK_CTRL_TX_*</code> flags.</p> +</div> +<div class="paragraph"> +<p><strong>Stream Routing Information</strong></p> +</div> +<div class="paragraph"> +<p>Both stream link interface provide an optional port for routing information: <code>slink_tx_dst_o</code> (AXI stream&#8217;s <code>TDEST</code>) +can be used to set a destination address when using a switch/interconnect to access several stream sinks. <code>slink_rx_src_i</code> +(AXI stream&#8217;s <code>TID</code>) can be used to determine the source when several sources can send data via a switch/interconnect. +The routing information can be set/read via the <code>ROUTE</code> interface registers. Note that all routing information is also +fully buffered by the internal RX/TX FIFOs. RX routing information has to be read <strong>after</strong> reading the according RX +data. Vice versa, TX routing information has to be set <strong>before</strong> writing the according TX data.</p> +</div> +<div class="paragraph"> +<p><strong>Interrupts</strong></p> +</div> +<div class="paragraph"> +<p>The SLINK module provides two independent interrupt channels: one for RX events and one for TX events. +The interrupt conditions are based on the according link&#8217;s FIFO status flags and are configured via the control +register&#8217;s <code>SLINK_CTRL_IRQ_*</code> flags. The according interrupt will fire when the module is enabled (<code>SLINK_CTRL_EN</code>) +and the selected interrupt conditions are met. Note that all enabled interrupt conditions are logically OR-ed per +channel. If any enable interrupt conditions becomes active the interrupt will become pending until the +interrupt-causing condition is resolved (e.g. by reading from the RX FIFO).</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 9. SLINK register map (<code>struct NEORV32_SLINK</code>)</caption> +<colgroup> +<col style="width: 15.3846%;"> +<col style="width: 15.3846%;"> +<col style="width: 30.7692%;"> +<col style="width: 7.6923%;"> +<col style="width: 30.7693%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s)</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="22"><p class="tableblock"><code>0xffffec00</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="22"><p class="tableblock"><code>NEORV32_SLINK.CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>SLINK_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SLINK global enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> <code>SLINK_CTRL_RX_CLR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Clear RX FIFO when set (bit auto-clears)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>2</code> <code>SLINK_CTRL_TX_CLR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Clear TX FIFO when set (bit auto-clears)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>3</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>4</code> <code>SLINK_CTRL_RX_LAST</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Last word read from <code>RX_DATA</code> is marked as "end of stream"</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:5</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>8</code> <code>SLINK_CTRL_RX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>9</code> <code>SLINK_CTRL_RX_HALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>10</code> <code>SLINK_CTRL_RX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>11</code> <code>SLINK_CTRL_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>12</code> <code>SLINK_CTRL_TX_HALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>13</code> <code>SLINK_CTRL_TX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>15:14</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>16</code> <code>SLINK_CTRL_IRQ_RX_NEMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX interrupt if RX FIFO not empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>17</code> <code>SLINK_CTRL_IRQ_RX_HALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX interrupt if RX FIFO at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>18</code> <code>SLINK_CTRL_IRQ_RX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX interrupt if RX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>19</code> <code>SLINK_CTRL_IRQ_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX interrupt if TX FIFO empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>20</code> <code>SLINK_CTRL_IRQ_TX_NHALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX interrupt if TX FIFO not at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>21</code> <code>SLINK_CTRL_IRQ_TX_NFULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX interrupt if TX FIFO not full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>23:22</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27:24</code> <code>SLINK_CTRL_RX_FIFO_MSB : SLINK_CTRL_RX_FIFO_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">log2(RX FIFO size)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:28</code> <code>SLINK_CTRL_TX_FIFO_MSB : SLINK_CTRL_TX_FIFO_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">log2(TX FIFO size)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="3"><p class="tableblock"><code>0xffffec04</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="3"><p class="tableblock"><code>NEORV32_SLINK.ROUTE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>3:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX destination routing information (<code>slink_tx_dst_o</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:4</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX source routing information (<code>slink_rx_src_i</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:8</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffec08</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>NEORV32_SLINK.DATA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Write data to TX FIFO; read data from RX FIFO</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffec0c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>NEORV32_SLINK.DATA_LAST</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Write data to TX FIFO (and also set "last" signal); read data from RX FIFO</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_general_purpose_input_and_output_port_gpio">2.7.9. General Purpose Input and Output Port (GPIO)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_gpio.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_gpio.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_gpio.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>gpio_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">64-bit parallel output port</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>gpio_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">64-bit parallel input port</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_GPIO_NUM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of input/output pairs to implement (0..64)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The general purpose parallel IO unit provides a simple parallel input and output port. These ports can be used +chip-externally (for example to drive status LEDs, connect buttons, etc.) or chip-internally to provide control +signals for other IP modules.</p> +</div> +<div class="paragraph"> +<p>The actual number of input/output pairs is defined by the <code>IO_GPIO_NUM</code> generic. When set to zero, the GPIO module +is excluded from synthesis and the output port <code>gpio_o</code> is tied to all-zero. If <code>IO_GPIO_NUM</code> is less than the +maximum value of 64, only the LSB-aligned bits in <code>gpio_o</code> and <code>gpio_i</code> are actually connected while the remaining +bits are tied to zero or are left unconnected, respectively.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Access Atomicity</div> +The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and +output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot +be performed within a single clock cycle. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 10. GPIO unit register map (<code>struct NEORV32_GPIO</code>)</caption> +<colgroup> +<col style="width: 16.6666%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 50.0002%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">Bit(s)</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffc00</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>INPUT[0]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">parallel input port pins 31:0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffc04</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>INPUT[1]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">parallel input port pins 63:32</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffc08</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>OUTPUT[0]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">parallel output port pins 31:0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffc0c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>OUTPUT[1]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">parallel output port pins 63:32</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_cyclic_redundancy_check_crc">2.7.10. Cyclic Redundancy Check (CRC)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_crc.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_crc.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_crc.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CRC_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement CRC module when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The cyclic redundancy check unit provides a programmable checksum computation module. The unit operates on +single bytes and can either compute CRC8, CRC16 or CRC32 checksums based on an arbitrary polynomial and +start value.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">CRC Demo Program</div> +A CRC example program (also using CPU-independent DMA transfers) can be found in <code>sw/example/crc_dma</code>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">CPU-Independent Operation</div> +The CRC unit can compute a checksum for an arbitrary memory array without any CPU overhead +by using the processor&#8217;s <a href="#_direct_memory_access_controller_dma">Direct Memory Access Controller (DMA)</a>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The module provides four interface registers:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>MODE</code>: selects either CRC8-, CRC16- or CRC32-mode</p> +</li> +<li> +<p><code>POLY</code>: programmable polynomial</p> +</li> +<li> +<p><code>DATA</code>: data input register (single bytes only)</p> +</li> +<li> +<p><code>SREG</code>: the CRC shift register; this register is used to define the start value and to obtain +the final processing result</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>The <code>MODE</code>, <code>POLY</code> and <code>SREG</code> registers need to be programmed before the actual processing can be started. +Writing a byte to <code>DATA</code> will update the current checksum in <code>SREG</code>.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Access Latency</div> +Write access to the CRC module have an increased latency of 8 clock cycles. This additional latency +ensures that the internal bit-serial processing of the current data byte has also been completed when the +transfer is completed. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Data Size</div> +For CRC8-mode only bits <code>7:0</code> of <code>POLY</code> and <code>SREG</code> are relevant; for CRC16-mode only bits <code>15:0</code> are used +and for CRC32-mode the entire 32-bit of <code>POLY</code> and <code>SREG</code> are used. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 11. CRC Register Map (<code>struct NEORV32_CRC</code>)</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 26.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 46.6669%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>0xffffee00</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">CRC mode select (<code>00</code> CRC8, <code>01</code>: CRC16, <code>10</code>: CRC32)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:2</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffee04</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>POLY</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">CRC polynomial</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>0xffffee08</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>DATA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">data input (single byte)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:8</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero, writes are ignored</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffee0c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SREG</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>32:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">current CRC shift register value (set start value on write)</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_watchdog_timer_wdt">2.7.11. Watchdog Timer (WDT)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_wdt.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_wdt.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_wdt.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_WDT_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement watchdog when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The watchdog (WDT) provides a last resort for safety-critical applications. When a pre-programmed timeout value is reached +a system-wide hardware reset is generated. The internal counter has to be reset explicitly by the application +program every now and then to prevent a timeout.</p> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The watchdog is enabled by setting the control register&#8217;s <code>WDT_CTRL_EN</code> bit. When this bit is cleared, the internal +timeout counter is reset to zero and no system reset can be triggered by this module.</p> +</div> +<div class="paragraph"> +<p>The internal 32-bit timeout counter is clocked at 1/4096th of the processor&#8217;s main clock (f<sub>WDT</sub>[Hz] = f<sub>main</sub>[Hz] / 4096). +Whenever this counter reaches the programmed timeout value (<code>WDT_CTRL_TIMEOUT</code> bits in the control register) a +hardware reset is triggered.</p> +</div> +<div class="paragraph"> +<p>The watchdog&#8217;s timeout counter is reset ("feeding the watchdog") by writing the reset <strong>PASSWORD</strong> to the <code>RESET</code> register. +The password is hardwired to hexadecimal <code>0x709D1AB3</code>.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Watchdog Operation during Debugging</div> +By default, the watchdog stops operation when the CPU enters debug mode and will resume normal operation after +the CPU has left debug mode again. This will prevent an unintended watchdog timeout during a debug session. However, +the watchdog can also be configured to keep operating even when the CPU is in debug mode by setting the control +register&#8217;s <code>WDT_CTRL_DBEN</code> bit. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Watchdog Operation during CPU Sleep</div> +By default, the watchdog stops operating when the CPU enters sleep mode. However, the watchdog can also be configured +to keep operating even when the CPU is in sleep mode by setting the control register&#8217;s <code>WDT_CTRL_SEN</code> bit. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Configuration Lock</strong></p> +</div> +<div class="paragraph"> +<p>The watchdog control register can be <em>locked</em> to protect the current configuration from being modified. The lock is +activated by setting the <code>WDT_CTRL_LOCK</code> bit. In the locked state any write access to the control register is entirely +ignored (see table below, "writable if locked"). However, read accesses to the control register as well as watchdog resets +are further possible.</p> +</div> +<div class="paragraph"> +<p>The lock bit can only be set if the WDT is already enabled (<code>WDT_CTRL_EN</code> is set). Furthermore, the lock bit can +only be cleared again by a system-wide hardware reset.</p> +</div> +<div class="paragraph"> +<p><strong>Strict Mode</strong></p> +</div> +<div class="paragraph"> +<p>The <em>strict operation mode</em> provides additional safety functions. If the strict mode is enabled by the <code>WDT_CTRL_STRICT</code> +control register bit an <strong>immediate hardware</strong> reset if enforced if</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>the <code>RESET</code> register is written with an incorrect password or</p> +</li> +<li> +<p>the <code>CTRL</code> register is written and the <code>WDT_CTRL_LOCK</code> bit is set.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>Cause of last Hardware Reset</strong></p> +</div> +<div class="paragraph"> +<p>The cause of the last system hardware reset can be determined via the <code>WDT_CTRL_RCAUSE_*</code> bits:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>WDT_RCAUSE_EXT</code> (0b00): Reset caused by external reset signal/pin</p> +</li> +<li> +<p><code>WDT_RCAUSE_OCD</code> (0b01): Reset caused by on-chip debugger</p> +</li> +<li> +<p><code>WDT_RCAUSE_TMO</code> (0b10): Reset caused by watchdog timeout</p> +</li> +<li> +<p><code>WDT_RCAUSE_ACC</code> (0b11): Reset caused by illegal watchdog access (strict mode)</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 12. WDT register map (<code>struct NEORV32_WDT</code>)</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 26.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 13.3333%;"> +<col style="width: 26.667%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-center valign-top">Reset value</th> +<th class="tableblock halign-center valign-top">Writable if locked</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="8"><p class="tableblock"><code>0xfffffb00</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="8"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>WDT_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">watchdog enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> <code>WDT_CTRL_LOCK</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">lock configuration when set, clears only on system reset, can only be set if enable bit is set already</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>2</code> <code>WDT_CTRL_DBEN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set to allow WDT to continue operation even when CPU is in debug mode</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>3</code> <code>WDT_CTRL_SEN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set to allow WDT to continue operation even when CPU is in sleep mode</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>4</code> <code>WDT_CTRL_STRICT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set to enable strict mode (force hardware reset if reset password is incorrect or if write access to locked CTRL register)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>6:5</code> <code>WDT_CTRL_RCAUSE_HI : WDT_CTRL_RCAUSE_LO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">cause of last system reset; 0=external reset, 1=ocd-reset, 2=watchdog reset</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, reads as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:8</code> <code>WDT_CTRL_TIMEOUT_MSB : WDT_CTRL_TIMEOUT_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">24-bit watchdog timeout value</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffb04</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RESET</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">yes</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Write <em>PASSWORD</em> to reset WDT timeout counter</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_machine_system_timer_mtime">2.7.12. Machine System Timer (MTIME)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_mtime.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_mtime.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_mtime.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mtime_irq_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RISC-V machine timer IRQ if internal one is <strong>not</strong> implemented</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mtime_time_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Current system time (<code>TIME</code> register)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_MTIME_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement machine timer when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MTI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine timer interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The MTIME module implements a memory-mapped machine system timer that is compatible to the RISC-V +privileged specifications. The 64-bit system time is accessed via individual <code>TIME_LO</code> and +<code>TIME_HI</code> registers. A 64-bit time compare register, which is accessible via individual <code>TIMECMP_LO</code> +and <code>TIMECMP_HI</code> registers, can be used to configure the CPU&#8217;s machine timer interrupt (<code>MTI</code>)).</p> +</div> +<div class="paragraph"> +<p>The interrupt is triggered whenever <code>TIME</code> (high &amp; low part) is greater than or equal to <code>TIMECMP</code> (high &amp; low part). +The interrupt remains active (=pending) until <code>TIME</code> becomes less than <code>TIMECMP</code> again (either by modifying +<code>TIME</code> or <code>TIMECMP</code>). The current system time is available for other SoC modules via the top&#8217;s <code>mtime_time_o</code> signal.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Hardware Reset</div> +After a hardware reset the <code>TIME</code> and <code>TIMECMP</code> register are reset to all-zero. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">External MTIME Interrupt</div> +If the internal MTIME module is disabled (<code>IO_MTIME_EN</code> = <code>false</code>) the machine timer interrupt becomes available +as external signal. The <code>mtime_irq_i</code> signal is level-triggered and high-active. Once set the signal has to stay +high until the interrupt request is explicitly acknowledged (e.g. writing to a user-defined memory-mapped register). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 13. MTIME register map (<code>struct NEORV32_MTIME</code>)</caption> +<colgroup> +<col style="width: 21.4285%;"> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 7.1428%;"> +<col style="width: 42.8574%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">Bits</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff400</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TIME_LO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">system time, low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff404</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TIME_HI</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">system time, high word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff408</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TIMECMP_LO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">time compare, low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff40c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TIMECMP_HI</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">time compare, high word</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_primary_universal_asynchronous_receiver_and_transmitter_uart0">2.7.13. Primary Universal Asynchronous Receiver and Transmitter (UART0)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_uart.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_uart.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_uart.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart0_txd_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial transmitter output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart0_rxd_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial receiver input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart0_rts_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">flow control: RX ready to receive, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart0_cts_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">flow control: RX ready to receive, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_UART0_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement UART0 when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>UART0_RX_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO depth (power of 2, min 1)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>UART0_TX_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO depth (power of 2, min 1)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 2</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 3</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The NEORV32 UART provides a standard serial interface with independent transmitter and receiver channels, each +equipped with a configurable FIFO. The transmission frame is fixed to <strong>8N1</strong>: 8 data bits, no parity bit, 1 stop +bit. The actual transmission rate (Baud rate) is programmable via software. The module features two memory-mapped +registers: <code>CTRL</code> and <code>DATA</code>. These are used for configuration, status check and data transfer.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Standard Console</div> +All default example programs and software libraries of the NEORV32 software framework (including the bootloader +and the runtime environment) use the primary UART (<em>UART0</em>) as default user console interface. Furthermore, UART0 +is used to implement the "standard consoles" (<code>STDIN</code>, <code>STDOUT</code> and <code>STDERR</code>). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>RX and TX FIFOs</strong></p> +</div> +<div class="paragraph"> +<p>The UART provides individual data FIFOs for RX and TX to allow data transmission without CPU intervention. +The sizes of these FIFOs can be configured via the according configuration generics (<code>UART0_RX_FIFO</code> and <code>UART0_TX_FIFO</code>). +Both FIFOs a re automatically cleared when disabling the module via the <code>UART_CTRL_EN</code> flag. However, the FIFOs can +also be cleared individually by setting the <code>UART_CTRL_RX_CLR</code> / <code>UART_CTRL_TX_CLR</code> flags.</p> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The module is enabled by setting the <code>UART_CTRL_EN</code> bit in the UART0 control register <code>CTRL</code>. The Baud rate +is configured via a 10-bit <code>UART_CTRL_BAUDx</code> baud divisor (<code>baud_div</code>) and a 3-bit <code>UART_CTRL_PRSCx</code> +clock prescaler (<code>clock_prescaler</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 14. UART0 Clock Configuration</caption> +<colgroup> +<col style="width: 33.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3336%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"><strong><code>UART_CTRL_PRSCx</code></strong></th> +<th class="tableblock halign-center valign-top"><code>0b000</code></th> +<th class="tableblock halign-center valign-top"><code>0b001</code></th> +<th class="tableblock halign-center valign-top"><code>0b010</code></th> +<th class="tableblock halign-center valign-top"><code>0b011</code></th> +<th class="tableblock halign-center valign-top"><code>0b100</code></th> +<th class="tableblock halign-center valign-top"><code>0b101</code></th> +<th class="tableblock halign-center valign-top"><code>0b110</code></th> +<th class="tableblock halign-center valign-top"><code>0b111</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting <code>clock_prescaler</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">128</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2048</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4096</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><em><strong>Baud rate</strong></em> = (<em>f<sub>main</sub>[Hz]</em> / <code>clock_prescaler</code>) / (<code>baud_div</code> + 1)</p> +</div> +<div class="paragraph"> +<p>The control register&#8217;s <code>UART_CTRL_RX_*</code> and <code>UART_CTRL_TX_*</code> flags provide information about the RX and TX FIFO fill level. +Disabling the module via the <code>UART_CTRL_EN</code> bit will also clear these FIFOs.</p> +</div> +<div class="paragraph"> +<p>A new TX transmission is started by writing to the <code>DATA</code> register. The +transfer is completed when the <code>UART_CTRL_TX_BUSY</code> control register flag returns to zero. RX data is available when +the <code>UART_CTRL_RX_NEMPTY</code> flag becomes set. The <code>UART_CTRL_RX_OVER</code> will be set if the RX FIFO overflows. This flag +is cleared only by disabling the module via <code>UART_CTRL_EN</code>.</p> +</div> +<div class="paragraph"> +<p><strong>UART Interrupts</strong></p> +</div> +<div class="paragraph"> +<p>The UART module provides independent interrupt channels for RX and TX. These interrupts are triggered by certain RX and TX +FIFO levels. The actual configuration is programmed independently for the RX and TX interrupt channel via the control register&#8217;s +<code>UART_CTRL_IRQ_RX_*</code> and <code>UART_CTRL_IRQ_TX_*</code> bits:</p> +</div> +<div class="olist arabic"> +<ol class="arabic"> +<li> +<p><strong>RX IRQ</strong> The RX interrupt can be triggered by three different RX FIFO level states: If <code>UART_CTRL_IRQ_RX_NEMPTY</code> is set the +interrupt fires if the RX FIFO is <em>not</em> empty (e.g. when incoming data is available). If <code>UART_CTRL_IRQ_RX_HALF</code> is set the RX IRQ +fires if the RX FIFO is at least half-full. If <code>UART_CTRL_IRQ_RX_FULL</code> the interrupt fires if the RX FIFO is full. Note that all +these programmable conditions are logically OR-ed (interrupt fires if any enabled conditions is true).</p> +</li> +<li> +<p><strong>TX IRQ</strong> The TX interrupt can be triggered by two different TX FIFO level states: If <code>UART_CTRL_IRQ_TX_EMPTY</code> is set the +interrupt fires if the TX FIFO is empty. If <code>UART_CTRL_IRQ_TX_NHALF</code> is set the interrupt fires if the TX FIFO is <em>not</em> at least +half full. Note that all these programmable conditions are logically OR-ed (interrupt fires if any enabled conditions is true).</p> +</li> +</ol> +</div> +<div class="paragraph"> +<p>Once an UART interrupt has fired it remains pending until the actual cause of the interrupt is resolved; for +example if just the <code>UART_CTRL_IRQ_RX_NEMPTY</code> bit is set, the RX interrupt will keep firing until the RX FIFO is empty again.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">RX/TX FIFO Size</div> +Software can retrieve the configured sizes of the RX and TX FIFO via the according <code>UART_DATA_RX_FIFO_SIZE</code> and +<code>UART_DATA_TX_FIFO_SIZE</code> bits from the <code>DATA</code> register. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>RTS/CTS Hardware Flow Control</strong></p> +</div> +<div class="paragraph"> +<p>The NEORV32 UART supports optional hardware flow control using the standard CTS <code>uart0_cts_i</code> ("clear to send") and RTS +<code>uart0_rts_o</code> ("ready to send" / "ready to receive (RTR)") signals. Both signals are low-active. +Hardware flow control is enabled by setting the <code>UART_CTRL_HWFC_EN</code> bit in the modules control register <code>CTRL</code>.</p> +</div> +<div class="paragraph"> +<p>When hardware flow control is enabled:</p> +</div> +<div class="olist arabic"> +<ol class="arabic"> +<li> +<p>The UART&#8217;s transmitter will not start a new transmission until the <code>uart0_cts_i</code> signal goes low. +During this time, the UART busy flag <code>UART_CTRL_TX_BUSY</code> remains set.</p> +</li> +<li> +<p>The UART will set <code>uart0_rts_o</code> signal low if the RX FIFO is <strong>less than half full</strong> (to have a wide safety margin). +As long as this signal is low, the connected device can send new data. <code>uart0_rts_o</code> is always low if the hardware flow-control +is disabled. Disabling the UART (setting <code>UART_CTRL_EN</code> low) while having hardware flow-control enabled, will set <code>uart0_rts_o</code> +high to signal that the UARt is not capable of receiving new data.</p> +</li> +</ol> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Note that RTS and CTS signaling can only be activated together. If the RTS handshake is not required the signal can be left +unconnected. If the CTS handshake is not required it has to be tied to zero. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Simulation Mode</strong></p> +</div> +<div class="paragraph"> +<p>The UART provides a <em>simulation-only</em> mode to dump console data as well as raw data directly to a file. When the simulation +mode is enabled (by setting the <code>UART_CTRL_SIM_MODE</code> bit) there will be <strong>no</strong> physical transaction on the <code>uart0_txd_o</code> signal. +Instead, all data written to the <code>DATA</code> register is immediately dumped to a file. Data written to <code>DATA[7:0]</code> will be dumped as +ASCII chars to a file named <code>neorv32.uart0.sim_mode.text.out</code>. Additionally, the ASCII data is printed to the simulator console.</p> +</div> +<div class="paragraph"> +<p>Both file are created in the simulation&#8217;s home folder.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 15. UART0 register map (<code>struct NEORV32_UART0</code>)</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 11.1111%;"> +<col style="width: 27.7777%;"> +<col style="width: 11.1111%;"> +<col style="width: 27.7779%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="20"><p class="tableblock"><code>0xfffff500</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="20"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>UART_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">UART enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> <code>UART_CTRL_SIM_MODE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">enable <strong>simulation mode</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>2</code> <code>UART_CTRL_HWFC_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">enable RTS/CTS hardware flow-control</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>5:3</code> <code>UART_CTRL_PRSC2 : UART_CTRL_PRSC0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Baud rate clock prescaler select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>15:6</code> <code>UART_CTRL_BAUD9 : UART_CTRL_BAUD0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">12-bit Baud value configuration value</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>16</code> <code>UART_CTRL_RX_NEMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO not empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>17</code> <code>UART_CTRL_RX_HALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO at least half-full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>18</code> <code>UART_CTRL_RX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>19</code> <code>UART_CTRL_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>20</code> <code>UART_CTRL_TX_NHALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO not at least half-full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>21</code> <code>UART_CTRL_TX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>22</code> <code>UART_CTRL_IRQ_RX_NEMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire IRQ if RX FIFO not empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>23</code> <code>UART_CTRL_IRQ_RX_HALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire IRQ if RX FIFO at least half-full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>24</code> <code>UART_CTRL_IRQ_RX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire IRQ if RX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>25</code> <code>UART_CTRL_IRQ_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire IRQ if TX FIFO empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>26</code> <code>UART_CTRL_IRQ_TX_NHALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire IRQ if TX not at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em> read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>28</code> <code>UART_CTRL_RX_CLR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Clear RX FIFO, flag auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>29</code> <code>UART_CTRL_TX_CLR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Clear TX FIFO, flag auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>UART_CTRL_RX_OVER</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO overflow; cleared by disabling the module</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>UART_CTRL_TX_BUSY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX busy or TX FIFO not empty</p></td> +<td class="tableblock halign-left valign-top" rowspan="4"><p class="tableblock"><code>0xfffff504</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="4"><p class="tableblock"><code>DATA</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code> <code>UART_DATA_RTX_MSB : UART_DATA_RTX_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">receive/transmit data</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>11:8</code> <code>UART_DATA_RX_FIFO_SIZE_MSB : UART_DATA_RX_FIFO_SIZE_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">log2(RX FIFO size)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>15:12</code> <code>UART_DATA_TX_FIFO_SIZE_MSB : UART_DATA_TX_FIFO_SIZE_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">log2(RX FIFO size)</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_secondary_universal_asynchronous_receiver_and_transmitter_uart1">2.7.14. Secondary Universal Asynchronous Receiver and Transmitter (UART1)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_uart.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_uart.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_uart.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart1_txd_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial transmitter output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart1_rxd_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial receiver input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart1_rts_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">flow control: RX ready to receive, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>uart1_cts_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">flow control: RX ready to receive, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_UART1_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement UART1 when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>UART1_RX_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO depth (power of 2, min 1)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>UART1_TX_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO depth (power of 2, min 1)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 5</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The secondary UART (UART1) is functionally identical to the primary UART +(<a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">Primary Universal Asynchronous Receiver and Transmitter (UART0)</a>). Obviously, UART1 uses different addresses for the +control register (<code>CTRL</code>) and the data register (<code>DATA</code>). The register&#8217;s bits/flags use the same bit positions and naming +as for the primary UART. The RX and TX interrupts of UART1 are mapped to different CPU fast interrupt (FIRQ) channels.</p> +</div> +<div class="paragraph"> +<p><strong>Simulation Mode</strong></p> +</div> +<div class="paragraph"> +<p>The secondary UART (UART1) provides the same simulation options as the primary UART (UART0). However, output data is +written to UART1-specific file <code>neorv32.uart1.sim_mode.text.out</code>. This data is also printed to the simulator console.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 16. UART1 register map (<code>struct NEORV32_UART1</code>)</caption> +<colgroup> +<col style="width: 28.5714%;"> +<col style="width: 14.2857%;"> +<col style="width: 14.2857%;"> +<col style="width: 14.2857%;"> +<col style="width: 28.5715%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff600</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">&#8230;&#8203;</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">&#8230;&#8203;</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Same as UART0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff604</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DATA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">&#8230;&#8203;</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">&#8230;&#8203;</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Same as UART0</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_serial_peripheral_interface_controller_spi">2.7.15. Serial Peripheral Interface Controller (SPI)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_spi.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_spi.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_spi.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>spi_clk_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial clock output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>spi_dat_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>spi_dat_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>spi_csn_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">8-bit dedicated chip select output (low-active)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SPI_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement SPI controller when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SPI_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FIFO depth, has to be a power of two, min 1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 6</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">configurable SPI interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The NEORV32 SPI module is a <strong>host</strong> transceiver. Hence, it is responsible for generating transmission. +The module operates on a byte.wide data granularity, supports all 4 standard clock modes, a fine-tunable +SPI clock generator and provides up to 8 dedicated chip select signals via the top entity&#8217;s <code>spi_csn_o</code> signal. +An optional receive/transmit ring-buffer/FIFO can be configured via the <code>IO_SPI_FIFO</code> generic to support block-based +transmissions without CPU interaction.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Host-Mode Only</div> +The NEORV32 SPI module only supports <em>host mode</em>. Transmission are initiated only by the processor&#8217;s SPI module +and not by an external SPI module. If you are looking for a <em>device-mode</em> serial peripheral interface (transactions +initiated by an external host) check out the <a href="#_serial_data_interface_controller_sdi">Serial Data Interface Controller (SDI)</a>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The SPI module provides a single control register <code>CTRL</code> to configure the module and to check it&#8217;s status +and a single data register <code>DATA</code> for receiving/transmitting data.</p> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The SPI module is enabled by setting the <code>SPI_CTRL_EN</code> bit in the <code>CTRL</code> control register. No transfer can be initiated +and no interrupt request will be triggered if this bit is cleared. Clearing this bit will reset the entire module, clear +the FIFO and terminate any transfer being in process.</p> +</div> +<div class="paragraph"> +<p>The actual SPI transfer (receiving one byte while sending one byte) as well as control of the chip-select lines is handled +via the module&#8217;s <code>DATA</code> register. Note that this register will access the TX FIFO of the ring-buffer when writing and will +access the RX FIFO of the ring-buffer when reading.</p> +</div> +<div class="paragraph"> +<p>The most significant bit of the <code>DATA</code> register (<code>SPI_DATA_CMD</code>) is used to select the purpose of the data being written. +When the <code>SPI_DATA_CMD</code> is cleared, the lowest 8-bit represent the actual SPI TX data. This data will be transmitted by the +SPI bus engine. After completion, the received data is stored to the RX FIFO.</p> +</div> +<div class="paragraph"> +<p>If <code>SPI_DATA_CMD</code> is cleared, the lowest 4-bit control the chip-select lines. In this case, bis <code>2:0</code> select one of the eight +chip-select lines. The selected line will become enabled when bit <code>3</code> is also set. If bit <code>3</code> is cleared, all chip-select +lines will be disabled.</p> +</div> +<div class="paragraph"> +<p>Examples:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Enable chip-select line 3: <code>NEORV32_SPI&#8594;DATA = (1 &lt;&lt; SPI_DATA_CMD) | (1 &lt;&lt; 3) | 3;</code></p> +</li> +<li> +<p>Enable chip-select line 7: <code>NEORV32_SPI&#8594;DATA = (1 &lt;&lt; SPI_DATA_CMD) | (1 &lt;&lt; 3) | 7;</code></p> +</li> +<li> +<p>Disable all chip-select lines: <code>NEORV32_SPI&#8594;DATA = (1 &lt;&lt; SPI_DATA_CMD) | (0 &lt;&lt; 3);</code></p> +</li> +<li> +<p>Send data byte <code>0xAB</code>: <code>NEORV32_SPI&#8594;DATA = (0 &lt;&lt; SPI_DATA_CMD) | 0xAB;</code></p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>Since all SPI operations are controlled via the FIFO, entire SPI sequences (chip-enable, data transmissions, chip-disable) +can be "programmed". Thus, SPI operations can be executed without any CPU interaction at all.</p> +</div> +<div class="paragraph"> +<p>Application software can check if any chip-select is enabled by reading the control register&#8217;s <code>SPI_CS_ACTIVE</code> flag.</p> +</div> +<div class="paragraph"> +<p><strong>SPI Clock Configuration</strong></p> +</div> +<div class="paragraph"> +<p>The SPI module supports all standard SPI clock modes (0, 1, 2, 3), which are configured via the two control register bits +<code>SPI_CTRL_CPHA</code> and <code>SPI_CTRL_CPOL</code>. The <code>SPI_CTRL_CPHA</code> bit defines the <em>clock phase</em> and the <code>SPI_CTRL_CPOL</code> +bit defines the <em>clock polarity</em>.</p> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/SPI_timing_diagram2.wikimedia.png" alt="SPI timing diagram2.wikimedia"> +</div> +<div class="title">Figure 7. SPI clock modes; image from <a href="https://en.wikipedia.org/wiki/File:SPI_timing_diagram2.svg" class="bare">https://en.wikipedia.org/wiki/File:SPI_timing_diagram2.svg</a> (license: (Wikimedia) <a href="https://en.wikipedia.org/wiki/Creative_Commons">Creative Commons</a> <a href="https://creativecommons.org/licenses/by-sa/3.0/deed.en">Attribution-Share Alike 3.0 Unported</a>)</div> +</div> +<div class="paragraph"> +<p>The SPI clock frequency (<code>spi_clk_o</code>) is programmed by the 3-bit <code>SPI_CTRL_PRSCx</code> clock prescaler for a coarse clock selection +and a 4-bit clock divider <code>SPI_CTRL_CDIVx</code> for a fine clock configuration. +The following clock prescalers (<code>SPI_CTRL_PRSCx</code>) are available:</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 17. SPI prescaler configuration</caption> +<colgroup> +<col style="width: 33.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3336%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"><strong><code>SPI_CTRL_PRSCx</code></strong></th> +<th class="tableblock halign-center valign-top"><code>0b000</code></th> +<th class="tableblock halign-center valign-top"><code>0b001</code></th> +<th class="tableblock halign-center valign-top"><code>0b010</code></th> +<th class="tableblock halign-center valign-top"><code>0b011</code></th> +<th class="tableblock halign-center valign-top"><code>0b100</code></th> +<th class="tableblock halign-center valign-top"><code>0b101</code></th> +<th class="tableblock halign-center valign-top"><code>0b110</code></th> +<th class="tableblock halign-center valign-top"><code>0b111</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting <code>clock_prescaler</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">128</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2048</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4096</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>Based on the programmed clock configuration, the actual SPI clock frequency f<sub>SPI</sub> is derived +from the processor&#8217;s main clock f<sub>main</sub> according to the following equation:</p> +</div> +<div class="paragraph"> +<p><em><strong>f<sub>SPI</sub></strong></em> = <em>f<sub>main</sub>[Hz]</em> / (2 * <code>clock_prescaler</code> * (1 + <code>SPI_CTRL_CDIVx</code>))</p> +</div> +<div class="paragraph"> +<p>Hence, the maximum SPI clock is f<sub>main</sub> / 4 and the lowest SPI clock is f<sub>main</sub> / 131072. The SPI clock is always +symmetric having a duty cycle of exactly 50%.</p> +</div> +<div class="paragraph"> +<p><strong>High-Speed Mode</strong></p> +</div> +<div class="paragraph"> +<p>The SPI provides a high-speed mode to further boost the maximum SPI clock frequency. When enabled via the control +register&#8217;s <code>SPI_CTRL_HIGHSPEED</code> bit the clock prescaler configuration (<code>SPI_CTRL_PRSCx</code> bits) is overridden setting it +to a minimal factor of 1. However, the clock speed can still be fine-tuned using the <code>SPI_CTRL_CDIVx</code> bits.</p> +</div> +<div class="paragraph"> +<p><em><strong>f<sub>SPI</sub></strong></em> = <em>f<sub>main</sub>[Hz]</em> / (2 * 1 * (1 + <code>SPI_CTRL_CDIVx</code>))</p> +</div> +<div class="paragraph"> +<p>Hence, the maximum SPI clock is f<sub>main</sub> / 2 when in high-speed mode.</p> +</div> +<div class="paragraph"> +<p><strong>SPI Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>The SPI module provides a set of programmable interrupt conditions based on the level of the RX/TX FIFO. The different +interrupt sources are enabled by setting the according control register&#8217;s <code>SPI_CTRL_IRQ_*</code> bits. All enabled interrupt +conditions are logically OR-ed, so any enabled interrupt source will trigger the module&#8217;s interrupt signal.</p> +</div> +<div class="paragraph"> +<p>Once the SPI interrupt has fired it remains pending until the actual cause of the interrupt is resolved; for +example if just the <code>SPI_CTRL_IRQ_RX_AVAIL</code> bit is set, the interrupt will keep firing until the RX FIFO is empty again.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 18. SPI register map (<code>struct NEORV32_SPI</code>)</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 26.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 46.6669%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="19"><p class="tableblock"><code>0xfffff800</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="19"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>SPI_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI module enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> <code>SPI_CTRL_CPHA</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">clock phase</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>2</code> <code>SPI_CTRL_CPOL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">clock polarity</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>5:3</code> <code>SPI_CTRL_PRSC2 : SPI_CTRL_PRSC0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3-bit clock prescaler select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>9:6</code> <code>SPI_CTRL_CDIV2 : SPI_CTRL_CDIV0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4-bit clock divider for fine-tuning</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>10</code> <code>SPI_CTRL_HIGHSPEED</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">high-speed mode enable (overriding <code>SPI_CTRL_PRSC*</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>15:11</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>16</code> <code>SPI_CTRL_RX_AVAIL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO data available (RX FIFO not empty)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>17</code> <code>SPI_CTRL_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>18</code> <code>SPI_CTRL_TX_NHALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO <em>not</em> at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>19</code> <code>SPI_CTRL_TX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>20</code> <code>SPI_CTRL_IRQ_RX_AVAIL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger IRQ if RX FIFO not empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>21</code> <code>SPI_CTRL_IRQ_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger IRQ if TX FIFO empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>22</code> <code>SPI_CTRL_IRQ_TX_NHALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger IRQ if TX FIFO <em>not</em> at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>23</code> <code>SPI_CTRL_IRQ_IDLE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger IRQ if TX FIFO is empty and SPI bus engine is idle</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27:24</code> <code>SPI_CTRL_FIFO_MSB : SPI_CTRL_FIFO_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FIFO depth; log2(<code>IO_SPI_FIFO</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30:28</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>SPI_CS_ACTIVE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set if any chip-select line is active</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>SPI_CTRL_BUSY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI module busy when set (serial engine operation in progress and TX FIFO not empty yet)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="3"><p class="tableblock"><code>0xfffff804</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="3"><p class="tableblock"><code>DATA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code> <code>SPI_DATA_MSB : SPI_DATA_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">receive/transmit data (FIFO)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30:8</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>SPI_DATA_CMD</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">data (<code>0</code>) / chip-select-command (<code>1</code>) select</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_serial_data_interface_controller_sdi">2.7.16. Serial Data Interface Controller (SDI)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_sdi.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_sdi.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_sdi.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sdi_clk_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial clock input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sdi_dat_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sdi_dat_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sdi_csn_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit chip-select input (low-active)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SDI_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement SDI controller when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_SDI_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">data FIFO size, has to a power of two, min 1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 11</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">configurable SDI interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The serial data interface module provides a <strong>device-class</strong> SPI interface and allows to connect the processor +to an <strong>external SPI host</strong>, which is responsible of performing the actual transmission - the SDI is entirely +passive. An optional receive/transmit ring buffer (FIFOs) can be configured via the <code>IO_SDI_FIFO</code> generic to +support block-based transmissions without CPU interaction.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Device-Mode Only</div> +The NEORV32 SDI module only supports <em>device mode</em>. Transmission are initiated by an external host and not by the +the processor itself. If you are looking for a <em>host-mode</em> serial peripheral interface (transactions +performed by the NEORV32) check out the <a href="#_serial_peripheral_interface_controller_spi">Serial Peripheral Interface Controller (SPI)</a>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The SDI module provides a single control register <code>CTRL</code> to configure the module and to check it&#8217;s status +and a single data register <code>DATA</code> for receiving/transmitting data. Any access to the <code>DATA</code> register +actually accesses the internal ring buffer.</p> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The SDI module is enabled by setting the <code>SDI_CTRL_EN</code> bit in the <code>CTRL</code> control register. Clearing this bit +resets the entire module and will also clear the entire RX/TX ring buffer.</p> +</div> +<div class="paragraph"> +<p>The SDI operates on byte-level only. Data written to the <code>DATA</code> register will be pushed to the TX FIFO. Received +data can be retrieved by reading the RX FIFO via the <code>DATA</code> register. The current state of these FIFOs is available +via the control register&#8217;s <code>SDI_CTRL_RX_*</code> and <code>SDI_CTRL_TX_*</code> flags. If no data is available in the TX FIFO while +an external device performs a transmission the external device will read all-zero from the SDI controller.</p> +</div> +<div class="paragraph"> +<p>Application software can check the current state of the SDI chip-select input via the control register&#8217;s +<code>SDI_CTRL_CS_ACTIVE</code> flag (the flag is set when the chip-select line is active (pulled low)).</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">MSB-first Only</div> +The NEORV32 SDI module only supports MSB-first mode. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">In-Transmission Abort</div> +If the external SPI controller aborts the transmission by setting the chip-select signal high again <em>before</em> +8 data bits have been transferred, no data is written to the RX FIFO. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>SDI Clocking</strong></p> +</div> +<div class="paragraph"> +<p>The SDI module supports both SPI clock polarity modes ("CPOL") but only "CPHA=0"-clock-phase is <em>officially</em> supported +yet. However, experiments have shown that the SDI module can also deal with both clock phase modes (for slow SDI clock speeds).</p> +</div> +<div class="paragraph"> +<p>All SDI operations are clocked by the external <code>sdi_clk_i</code> signal. This signal is synchronized to the processor&#8217;s +clock domain to simplify timing behavior. This clock synchronization requires the external SDI clock +(<code>sdi_clk_i</code>) does <strong>not exceed 1/4 of the processor&#8217;s main clock</strong>.</p> +</div> +<div class="paragraph"> +<p><strong>SDI Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>The SDI module provides a set of programmable interrupt conditions based on the level of the RX &amp; TX FIFOs. The different +interrupt sources are enabled by setting the according control register&#8217;s <code>SDI_CTRL_IRQ_*</code> bits. All enabled interrupt +conditions are logically OR-ed so any enabled interrupt source will trigger the module&#8217;s interrupt signal.</p> +</div> +<div class="paragraph"> +<p>Once the SDI interrupt has fired it will remain active until the actual cause of the interrupt is resolved; for +example if just the <code>SDI_CTRL_IRQ_RX_AVAIL</code> bit is set, the interrupt will keep firing until the RX FIFO is empty again.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 19. SDI register map (<code>struct NEORV32_SDI</code>)</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 26.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 46.6669%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="18"><p class="tableblock"><code>0xfffff700</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="18"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>SDI_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SDI module enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>3:1</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:4</code> <code>SDI_CTRL_FIFO_MSB : SDI_CTRL_FIFO_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FIFO depth; log2(<em>IO_SDI_FIFO</em>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>14:8</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>15</code> <code>SDI_CTRL_IRQ_RX_AVAIL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire interrupt if RX FIFO is not empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>16</code> <code>SDI_CTRL_IRQ_RX_HALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire interrupt if RX FIFO is at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>17</code> <code>SDI_CTRL_IRQ_RX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire interrupt if if RX FIFO is full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>18</code> <code>SDI_CTRL_IRQ_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire interrupt if TX FIFO is empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>19</code> <code>SDI_CTRL_IRQ_TX_NHALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fire interrupt if TX FIFO is not at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>22:20</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>23</code> <code>SDI_CTRL_RX_AVAIL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO data available (RX FIFO not empty)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>24</code> <code>SDI_CTRL_RX_HALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>25</code> <code>SDI_CTRL_RX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>26</code> <code>SDI_CTRL_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27</code> <code>SDI_CTRL_TX_NHALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO not at least half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>28</code> <code>SDI_CTRL_TX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30:29</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>SDI_CTRL_CS_ACTIVE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Chip-select is active when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>0xfffff704</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>DATA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">receive/transmit data (FIFO)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:8</code> <em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_two_wire_serial_interface_controller_twi">2.7.17. Two-Wire Serial Interface Controller (TWI)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_twi.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_twi.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_twi.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>twi_sda_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data line sense input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>twi_sda_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data line output (pull low only)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>twi_scl_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial clock line sense input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>twi_scl_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial clock line output (pull low only)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_TWI_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement TWI controller when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_TWI_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FIFO depth, has to be a power of two, min 1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 7</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FIFO empty and module idle interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The NEORV32 TWI implements an I2C-compatible host controller to communicate with arbitrary I2C-devices. +Note that peripheral-mode (controller acts as a device) and multi-controller mode are not supported yet.</p> +</div> +<div class="paragraph"> +<p>The TWI controller provides two memory-mapped registers that are used for configuring the module and +for triggering operation: <code>CTRL</code> is the control and status register, <code>DCMD</code> is the command and data register.</p> +</div> +<div class="paragraph"> +<p>Key features:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Programmable clock speed</p> +</li> +<li> +<p>Optional clock stretching</p> +</li> +<li> +<p>Generate START / repeated-START and STOP conditions</p> +</li> +<li> +<p>Sending &amp; receiving 8 data bits including ACK/NACK</p> +</li> +<li> +<p>Generating a host-ACK (ACK send by the TWI controller)</p> +</li> +<li> +<p>Configurable data/command FIFO to "program" large TWI sequences without further involvement of the CPU</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>Tristate Drivers</strong></p> +</div> +<div class="paragraph"> +<p>The TWI module requires two tristate drivers (actually: open-drain drivers; signals can only be actively driven low) for +the SDA and SCL lines, which have to be implemented by the user in the setup&#8217;s top module / IO ring. A generic VHDL example +is shown below (here, <code>sda_io</code> and <code>scl_io</code> are the actual TWI bus lines, which are of type <code>std_logic</code>).</p> +</div> +<div class="listingblock"> +<div class="title">Listing 7. TWI VHDL Tristate Driver Example</div> +<div class="content"> +<pre class="highlight"><code class="language-VHDL" data-lang="VHDL">sda_io &lt;= '0' when (twi_sda_o = '0') else 'Z'; -- drive +scl_io &lt;= '0' when (twi_scl_o = '0') else 'Z'; -- drive +twi_sda_i &lt;= std_ulogic(sda_io); -- sense +twi_scl_i &lt;= std_ulogic(scl_io); -- sense</code></pre> +</div> +</div> +<div class="paragraph"> +<p><strong>TWI Clock Speed</strong></p> +</div> +<div class="paragraph"> +<p>The TWI clock frequency is programmed by two bit-fields in the device&#8217;s control register <code>CTRL</code>: a 3-bit <code>TWI_CTRL_PRSCx</code> +clock prescaler is sued for a coarse clock configuration and a 4-bit clock divider <code>TWI_CTRL_CDIVx</code> is used for a fine +clock configuration.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 20. TWI prescaler configuration</caption> +<colgroup> +<col style="width: 33.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3336%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"><strong><code>TWI_CTRL_PRSCx</code></strong></th> +<th class="tableblock halign-center valign-top"><code>0b000</code></th> +<th class="tableblock halign-center valign-top"><code>0b001</code></th> +<th class="tableblock halign-center valign-top"><code>0b010</code></th> +<th class="tableblock halign-center valign-top"><code>0b011</code></th> +<th class="tableblock halign-center valign-top"><code>0b100</code></th> +<th class="tableblock halign-center valign-top"><code>0b101</code></th> +<th class="tableblock halign-center valign-top"><code>0b110</code></th> +<th class="tableblock halign-center valign-top"><code>0b111</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting <code>clock_prescaler</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">128</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2048</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4096</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>Based on the clock configuration, the actual TWI clock frequency f<sub>SCL</sub> is derived +from the processor&#8217;s main clock f<sub>main</sub> according to the following equation:</p> +</div> +<div class="paragraph"> +<p><em><strong>f<sub>SCL</sub></strong></em> = <em>f<sub>main</sub>[Hz]</em> / (4 * <code>clock_prescaler</code> * (1 + TWI_CTRL_CDIV))</p> +</div> +<div class="paragraph"> +<p>Hence, the maximum TWI clock is f<sub>main</sub> / 8 and the lowest TWI clock is f<sub>main</sub> / 262144. The generated TWI clock is +always symmetric having a duty cycle of exactly 50%.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Clock Stretching</div> +An accessed peripheral can slow down/halt the controller&#8217;s bus clock by using clock stretching (= actively keeping the +SCL line low). The controller will halt operation in this case. Clock stretching is enabled by setting the +<code>TWI_CTRL_CLKSTR</code> bit in the module&#8217;s control register <code>CTRL</code>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>TWI Transfers</strong></p> +</div> +<div class="paragraph"> +<p>The TWI is enabled via the <code>TWI_CTRL_EN</code> bit in the <code>CTRL</code> control register. All TWI operations are controlled by +the <code>DCMD</code> register. The actual operation is selected by a 2-bit value that is written to the register&#8217;s <code>TWI_DCMD_CMD_*</code> +bit-field:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>00</code>: NOP (no-operation); all further bit-fields in <code>DCMD</code> are ignored</p> +</li> +<li> +<p><code>01</code>: Generate a (repeated) START conditions; all further bit-fields in <code>DCMD</code> are ignored</p> +</li> +<li> +<p><code>10</code>: Generate a STOP conditions; all further bit-fields in <code>DCMD</code> are ignored</p> +</li> +<li> +<p><code>11</code>: Trigger a data transmission; the data to be send has to be written to the register&#8217;s <code>TWI_DCMD_MSB : TWI_DCMD_LSB</code> +bit-field; if <code>TWI_DCMD_ACK</code> is set the controller will send a host-ACK in the ACK/NACK time slot; after the transmission +is completed <code>TWI_DCMD_MSB : TWI_DCMD_LSB</code> contains the RX data and <code>TWI_DCMD_ACK</code> the device&#8217;s response if no host-ACK was +configured (<code>0</code> = ACK, <code>1</code> = ACK)</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>All operations/data written to the <code>DCMD</code> register are buffered by a configurable data/command FIFO. The depth of the FIFO is +configured by the <code>IO_TWI_FIFO</code> top generic. Software can retrieve this size by reading the control register&#8217;s <code>TWI_CTRL_FIFO</code> bits.</p> +</div> +<div class="paragraph"> +<p>The command/data FIFO is internally split into a TX FIFO and a RX FIFO. Writing to <code>DCMD</code> will write to the TX FIFO while reading from +<code>DCMD</code> will read from the RX FIFO. The TX FIFO is full when the <code>TWI_CTRL_TX_FULL</code> flag is set. Accordingly, the RX FIFO contains valid +data when the <code>TWI_CTRL_RX_AVAIL</code> flag is set.</p> +</div> +<div class="paragraph"> +<p>The control register&#8217;s busy flag <code>TWI_CTRL_BUSY</code> is set as long as the TX FIFO contains valid data (i.e. programmed TWI operations +that have not been executed yet) or of the TWI bus engine is still processing an operation.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +An active transmission can be terminated at any time by disabling the TWI module. This will also clear the data/command FIFO. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +When reading data from a device, an all-one byte (<code>0xFF</code>) has to be written to TWI data register <code>NEORV32_TWI.DATA</code> +so the accessed device can actively pull-down SDA when required. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>TWI Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>The TWI module provides a single interrupt to signal "idle condition" to the CPU. The interrupt becomes active when the +TWI module is enabled (<code>TWI_CTRL_EN</code> = <code>1</code>) and the TX FIFO is empty and the TWI bus engine is idle.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 21. TWI register map (<code>struct NEORV32_TWI</code>)</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 26.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 46.6669%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="10"><p class="tableblock"><code>0xfffff900</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="10"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>TWI_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TWI enable, reset if cleared</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>3:1</code> <code>TWI_CTRL_PRSC2 : TWI_CTRL_PRSC0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3-bit clock prescaler select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:4</code> <code>TWI_CTRL_CDIV3 : TWI_CTRL_CDIV0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4-bit clock divider</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>8</code> <code>TWI_CTRL_CLKSTR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable (allow) clock stretching</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>14:9</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>18:15</code> <code>TWI_CTRL_FIFO_MSB : TWI_CTRL_FIFO_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FIFO depth; log2(<code>IO_TWI_FIFO</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>28:12</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>29</code> <code>TWI_CTRL_TX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if the TWI bus is claimed by any controller</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>TWI_CTRL_RX_AVAIL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX FIFO data available</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>TWI_CTRL_BUSY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TWI bus engine busy or TX FIFO not empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="3"><p class="tableblock"><code>0xfffff904</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="3"><p class="tableblock"><code>DCMD</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code> <code>TWI_DCMD_MSB : TWI_DCMD_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RX/TX data byte</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>8</code> <code>TWI_DCMD_ACK</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">write: ACK bit sent by controller; read: <code>1</code> = device NACK, <code>0</code> = device ACK</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>10:9</code> <code>TWI_DCMD_CMD_HI : TWI_DCMD_CMD_LO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TWI operation (<code>00</code> = NOP, <code>01</code> = START conditions, <code>10</code> = STOP condition, <code>11</code> = data transmission)</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_one_wire_serial_interface_controller_onewire">2.7.18. One-Wire Serial Interface Controller (ONEWIRE)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_onewire.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_onewire.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_onewire.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>onewire_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit 1-wire bus sense input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>onewire_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit 1-wire bus output (pull low only)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_ONEWIRE_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement ONEWIRE interface controller when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 13</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">operation done interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The NEORV32 ONEWIRE module implements a single-wire interface controller that is compatible to the +<em>Dallas/Maxim 1-Wire</em> protocol, which is an asynchronous half-duplex bus requiring only a single signal wire +connected to <code>onewire_io</code> (plus ground).</p> +</div> +<div class="paragraph"> +<p>The bus is based on a single open-drain signal. The controller and all the devices can only pull-down the bus actively. +Hence, an external pull-up resistor is required. Recommended values are between 1kฮฉ and 4kฮฉ depending on the bus +characteristics (wire length, number of devices, etc.). Furthermore, a series resistor (~100ฮฉ) at the controller side +is recommended to control the slew rate and to reduce signal reflections. Also, additional external ESD protection clamp diodes +should be added to the bus line.</p> +</div> +<div class="paragraph"> +<p><strong>Tri-State Drivers</strong></p> +</div> +<div class="paragraph"> +<p>The ONEWIRE module requires a tri-state driver (actually, open-drain) for the 1-wire bus line, which has to be implemented +in the top module of the setup. A generic VHDL example is given below (<code>onewire</code> is the actual 1-wire +bus signal, which is of type <code>std_logic</code>).</p> +</div> +<div class="listingblock"> +<div class="title">Listing 8. ONEWIRE VHDL tri-state driver example</div> +<div class="content"> +<pre class="highlight"><code class="language-VHDL" data-lang="VHDL">onewire &lt;= '0' when (onewire_o = '0') else 'Z'; -- drive +onewire_i &lt;= std_ulogic(onewire); -- sense</code></pre> +</div> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The ONEWIRE controller provides two interface registers: <code>CTRL</code> and <code>DATA.</code> The control registers (<code>CTRL</code>) +is used to configure the module, to trigger bus transactions and to monitor the current state of the module. +The <code>DATA</code> register is used to read/write data from/to the bus.</p> +</div> +<div class="paragraph"> +<p>The module is enabled by setting the <code>ONEWIRE_CTRL_EN</code> bit in the control register. If this bit is cleared, the +module is automatically reset and the bus is brought to high-level (due to the external pull-up resistor). +The basic timing configuration is programmed via the clock prescaler bits <code>ONEWIRE_CTRL_PRSCx</code> and the +clock divider bits <code>ONEWIRE_CTRL_CLKDIVx</code> (see next section).</p> +</div> +<div class="paragraph"> +<p>The controller can execute three basic bus operations, which are triggered by setting one out of three specific +control register bits (the bits auto-clear):</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>generate reset pulse and check for device presence; triggered when setting <code>ONEWIRE_CTRL_TRIG_RST</code></p> +</li> +<li> +<p>transfer a single-bit (read-while-write); triggered when setting <code>ONEWIRE_CTRL_TRIG_BIT</code></p> +</li> +<li> +<p>transfer a full-byte (read-while-write); triggered when setting <code>ONEWIRE_CTRL_TRIG_BYTE</code></p> +</li> +</ol> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Only one trigger bit may be set at once, otherwise undefined behavior might occur. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>When a single-bit operation has been triggered, the data previously written to <code>DATA[0]</code> will be send to the bus +and <code>DATA[7]</code> will be sampled from the bus. Accordingly, a full-byte transmission will send the previously +byte written to <code>DATA[7:0]</code> to the bus and will update <code>DATA[7:0]</code> with the data read from the bus (LSB-first). +The triggered operation has completed when the module&#8217;s busy flag <code>ONEWIRE_CTRL_BUSY</code> has cleared again.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Read from Bus</div> +In order to read a single bit from the bus <code>DATA[0]</code> has to set to <code>1</code> before triggering the bit transmission +operation to allow the accessed device to pull-down the bus. Accordingly, <code>DATA</code> has to be set to <code>0xFF</code> before +triggering the byte transmission operation when the controller shall read a byte from the bus. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The <code>ONEWIRE_CTRL_PRESENCE</code> bit gets set if at least one device has send a "presence" signal right after the +reset pulse.</p> +</div> +<div class="paragraph"> +<p><strong>Bus Timing</strong></p> +</div> +<div class="paragraph"> +<p>The control register provides a 2-bit clock prescaler select (<code>ONEWIRE_CTRL_PRSCx</code>) and a 8-bit clock divider +(<code>ONEWIRE_CTRL_CLKDIVx</code>) for timing configuration. Both are used to define the elementary <strong>base time T<sub>base</sub></strong>. +All bus operations are timed using <em>multiples</em> of this elementary base time.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 22. ONEWIRE Clock Prescaler Configurations</caption> +<colgroup> +<col style="width: 50%;"> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"><strong><code>ONEWIRE_CTRL_PRSCx</code></strong></th> +<th class="tableblock halign-center valign-top"><code>0b00</code></th> +<th class="tableblock halign-center valign-top"><code>0b01</code></th> +<th class="tableblock halign-center valign-top"><code>0b10</code></th> +<th class="tableblock halign-center valign-top"><code>0b11</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting <code>clock_prescaler</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>Together with the clock divider value (<code>ONEWIRE_CTRL_PRSCx</code> bits = <code>clock_divider</code>) the base time is defined by the +following formula:</p> +</div> +<div class="paragraph"> +<p><em><strong>T<sub>base</sub></strong></em> = (1 / <em>f<sub>main</sub>[Hz]</em>) * <code>clock_prescaler</code> * (<code>clock_divider</code> + 1)</p> +</div> +<div class="paragraph"> +<p>Example:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><em>f<sub>main</sub></em> = 100MHz</p> +</li> +<li> +<p>clock prescaler select = <code>0b01</code> &#8594; <code>clock_prescaler</code> = 4</p> +</li> +<li> +<p>clock divider <code>clock_divider</code> = 249</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><em><strong>T<sub>base</sub></strong></em> = (1 / 100000000Hz) * 4 * (249 + 1) = 10000ns = <strong>10ยตs</strong></p> +</div> +<div class="paragraph"> +<p>The base time is used to coordinate all bus interactions. Hence, all delays, time slots and points in time are +quantized as multiples of the base time. The following images show the two basic operations of the ONEWIRE +controller: single-bit (0 or 1) transaction and reset with presence detect. The relevant points in time are +shown as <em>absolute</em> time (in multiples of the time base) with the bus' falling edge as reference point.</p> +</div> +<table class="tableblock frame-all grid-none stretch"> +<colgroup> +<col style="width: 50%;"> +<col style="width: 50%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><div class="content"><div class="imageblock text-center"> +<div class="content"> +<img src="img/onewire_data.png" alt="onewire data"> +</div> +</div></div></td> +<td class="tableblock halign-center valign-top"><div class="content"><div class="imageblock text-center"> +<div class="content"> +<img src="img/onewire_reset.png" alt="onewire reset"> +</div> +</div></div></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">Single-bit data transmission (not to scale)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">Reset pulse and presence detect (not to scale)</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 23. Data Transmission Timing</caption> +<colgroup> +<col style="width: 14.2857%;"> +<col style="width: 42.8571%;"> +<col style="width: 21.4285%;"> +<col style="width: 21.4287%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Symbol</th> +<th class="tableblock halign-left valign-top">Description</th> +<th class="tableblock halign-center valign-top">Multiples of T<sub>base</sub></th> +<th class="tableblock halign-center valign-top">Time when T<sub>base</sub> = 10ยตs</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Single-bit data transmission</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>t0</code> (a&#8594;b)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Time until end of active low-phase when writing a <code>'1'</code> or when reading</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">10ยตs</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>t1</code> (a&#8594;c)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Time until controller samples bus state (read operation)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">20ยตs</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>t2</code> (a&#8594;d)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Time until end of bit time slot (when writing a <code>'0'</code> or when reading)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">70ยตs</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>t3</code> (a&#8594;e)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Time until end of inter-slot pause (= total duration of one bit)</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">9</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">90ยตs</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Reset pulse and presence detect</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>t4</code> (f&#8594;g)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Time until end of active reset pulse</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">48</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">480ยตs</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>t5</code> (f&#8594;h)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Time until controller samples bus presence</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">55</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">550ยตs</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>t6</code> (f&#8594;i)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Time until end of presence phase</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">96</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">960ยตs</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The default values for base time multiples were chosen to for stable and reliable bus +operation (not for maximum throughput). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The absolute points in time are hardwired by the VHDL code and cannot be changed during runtime. +However, the timing parameter can be customized by editing the ONEWIRE&#8217;s VHDL source file:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 9. Hardwired time configuration in <code>neorv32_onewire.vhd</code></div> +<div class="content"> +<pre class="highlight"><code class="language-VHDL" data-lang="VHDL">-- timing configuration (absolute time in multiples of the base tick time t_base) -- +constant t_write_one_c : unsigned(6 downto 0) := to_unsigned( 1, 7); -- t0 +constant t_read_sample_c : unsigned(6 downto 0) := to_unsigned( 2, 7); -- t1 +constant t_slot_end_c : unsigned(6 downto 0) := to_unsigned( 7, 7); -- t2 +constant t_pause_end_c : unsigned(6 downto 0) := to_unsigned( 9, 7); -- t3 +constant t_reset_end_c : unsigned(6 downto 0) := to_unsigned(48, 7); -- t4 +constant t_presence_sample_c : unsigned(6 downto 0) := to_unsigned(55, 7); -- t5 +constant t_presence_end_c : unsigned(6 downto 0) := to_unsigned(96, 7); -- t6</code></pre> +</div> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Overdrive</div> +The ONEWIRE controller does not support the <em>overdrive</em> mode. However, it can be implemented by reducing the base +time <strong>T<sub>base</sub></strong> (and by eventually changing the hardwired timing configuration in the VHDL source file). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>A single interrupt is provided by the ONEWIRE module to signal "idle" condition to the CPU. Whenever the +controller is idle (again) the interrupt becomes active.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 24. ONEWIRE register map (<code>struct NEORV32_ONEWIRE</code>)</caption> +<colgroup> +<col style="width: 20%;"> +<col style="width: 10%;"> +<col style="width: 30%;"> +<col style="width: 10%;"> +<col style="width: 30%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="10"><p class="tableblock"><code>0xfffff200</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="10"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>ONEWIRE_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">ONEWIRE enable, reset if cleared</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>2:1</code> <code>ONEWIRE_CTRL_PRSC1 : ONEWIRE_CTRL_PRSC0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">2-bit clock prescaler select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>10:3</code> <code>ONEWIRE_CTRL_CLKDIV7 : ONEWIRE_CTRL_CLKDIV0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">8-bit clock divider value</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>11</code> <code>ONEWIRE_CTRL_TRIG_RST</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">trigger reset pulse, auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>12</code> <code>ONEWIRE_CTRL_TRIG_BIT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">trigger single bit transmission, auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>13</code> <code>ONEWIRE_CTRL_TRIG_BYTE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">trigger full-byte transmission, auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>28:14</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>29</code> <code>ONEWIRE_CTRL_SENSE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">current state of the bus line</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>ONEWIRE_CTRL_PRESENCE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">device presence detected after reset pulse</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>ONEWIRE_CTRL_BUSY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">operation in progress when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff204</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DATA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code> <code>ONEWIRE_DATA_MSB : ONEWIRE_DATA_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">receive/transmit data (8-bit)</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_pulse_width_modulation_controller_pwm">2.7.19. Pulse-Width Modulation Controller (PWM)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_pwm.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_pwm.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_pwm.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>pwm_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PWM output channels (16-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_PWM_NUM_CH</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of PWM channels to implement (0..16)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The PWM module implements a pulse-width modulation controller with up to 16 independent channels. Duty cycle and +carrier frequency can be programmed individually for each channel.The total number of implemented channels is +defined by the <code>IO_PWM_NUM_CH</code> generic. The PWM output signal <code>pwm_o</code> has a static size of 16-bit. Channel 0 +corresponds to bit 0, channel 1 to bit 1 and so on. If less than 16 channels are configured, only the LSB-aligned +channel bits are connected while the remaining ones are hardwired to zero.</p> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>Depending on the configured number channels, the PWM module provides 16 configuration registers <code>CHANNEL_CFG[0]</code> to +<code>CHANNEL_CFG[15]</code> - one for each channel. Regardless of the configuration of <code>IO_PWM_NUM_CH</code> all channel registers can +be accessed without raising an exception. However, registers above <code>IO_PWM_NUM_CH-1</code> are read-only and hardwired to +all-zero.</p> +</div> +<div class="paragraph"> +<p>Each configuration provides a 1-bit enable flag to enable/disable the according channel, an 8-bit register for setting +the duty cycle and a 3-bit clock prescaler select as well as a 10-bit clock diver for <em>coarse</em> and <em>fine</em> tuning of the +carrier frequency, respectively.</p> +</div> +<div class="paragraph"> +<p>A channel is enabled by setting the <code>PWM_CFG_EN</code> bit. If this bit is cleared the according PWM output is set to zero. +The duty cycle is programmed via the 8 <code>PWM_CFG_DUTY</code> bits. Based on the value programmed to this bits the duty cycle +the resulting duty cycle of the according channel can be computed by the following formula:</p> +</div> +<div class="paragraph"> +<p><em>Duty Cycle</em>[%] = <code>PWM_CFG_DUTY</code> / 2<sup>8</sup></p> +</div> +<div class="paragraph"> +<p>The PWM period (carrier frequency) is derived from the processor&#8217;s main clock (<em>f<sub>main</sub></em>). The <code>PWM_CFG_PRSC</code> register +bits allow to select one out of eight pre-defined clock prescalers for a coarse clock scaling. The 10 <code>PWM_CFG_CDIV</code> register +bits can be used to apply another fine clock scaling.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 25. PWM prescaler configuration</caption> +<colgroup> +<col style="width: 33.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3336%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"><strong><code>PWM_CFG_PRSC</code></strong></th> +<th class="tableblock halign-center valign-top"><code>0b000</code></th> +<th class="tableblock halign-center valign-top"><code>0b001</code></th> +<th class="tableblock halign-center valign-top"><code>0b010</code></th> +<th class="tableblock halign-center valign-top"><code>0b011</code></th> +<th class="tableblock halign-center valign-top"><code>0b100</code></th> +<th class="tableblock halign-center valign-top"><code>0b101</code></th> +<th class="tableblock halign-center valign-top"><code>0b110</code></th> +<th class="tableblock halign-center valign-top"><code>0b111</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting <code>clock_prescaler</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">128</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2048</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4096</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>The resulting PWM carrier frequency is defined by:</p> +</div> +<div class="paragraph"> +<p><em>f<sub>PWM</sub></em>[Hz] = <em>f<sub>main</sub></em>[Hz] / (2<sup>8</sup> * <code>clock_prescaler</code> * (1 + <code>PWM_CFG_CDIV</code>))</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 26. PWM register map (<code>struct neorv32_pwm_t</code>)</caption> +<colgroup> +<col style="width: 18.1818%;"> +<col style="width: 9.0909%;"> +<col style="width: 27.2727%;"> +<col style="width: 9.0909%;"> +<col style="width: 36.3637%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="5"><p class="tableblock"><code>0xfffff000</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="5"><p class="tableblock"><code>CHANNEL_CFG[0]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> - <code>PWM_CFG_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 0: channel enabled when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30:28</code> - <code>PWM_CFG_PRSC_MSB:PWM_CFG_PRSC_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 0: 3-bit clock prescaler select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27:18</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 0: <em>reserved</em>, hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>17:8</code> - <code>PWM_CFG_CDIV_MSB:PWM_CFG_CDIV_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 0: 10-bit clock divider</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code> - <code>PWM_CFG_DUTY_MSB:PWM_CFG_DUTY_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 0: 8-bit duty cycle</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff004</code> &#8230;&#8203; <code>0xfffff038</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CHANNEL_CFG[1]</code> &#8230;&#8203; <code>CHANNEL_CFG[14]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">&#8230;&#8203;</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channels 1 to 14</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="5"><p class="tableblock"><code>0xfffff03C</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="5"><p class="tableblock"><code>CHANNEL_CFG[15]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> - <code>PWM_CFG_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 15: channel enabled when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30:28</code> - <code>PWM_CFG_PRSC_MSB:PWM_CFG_PRSC_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 15: 3-bit clock prescaler select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27:18</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 15: <em>reserved</em>, hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>17:8</code> - <code>PWM_CFG_CDIV_MSB:PWM_CFG_CDIV_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 15: 10-bit clock divider</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code> - <code>PWM_CFG_DUTY_MSB:PWM_CFG_DUTY_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Channel 15: 8-bit duty cycle</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_true_random_number_generator_trng">2.7.20. True Random-Number Generator (TRNG)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_trng.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_trng.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_trng.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_TRNG_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement TRNG when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_TRNG_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">data FIFO depth, min 1, has to be a power of two</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TRNG data available interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The NEORV32 true random number generator provides <em>physically</em> true random numbers. It is based on free-running +ring-oscillators that generate <strong>phase noise</strong> when being sampled by a constant clock. This phase noise is +used as physical entropy source. The TRNG features a platform independent architecture without FPGA-specific +primitives, macros or attributes so it can be synthesized for <em>any</em> FPGA.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">In-Depth Documentation</div> +For more information about the neoTRNG architecture and an analysis of its random quality check out the +neoTRNG repository: <a href="https://github.com/stnolting/neoTRNG" class="bare">https://github.com/stnolting/neoTRNG</a> +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Inferring Latches</div> +The synthesis tool might emit warnings regarding <strong>inferred latches</strong> or <strong>combinatorial loops</strong>. However, this +is not design flaw as this is exactly what we want. ;) +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Simulation</div> +When simulating the processor the TRNG is automatically set to "simulation mode". In this mode the physical entropy +sources (the ring oscillators) are replaced by a simple <strong>pseudo RNG</strong> based on a LFSR providing only +<strong>deterministic pseudo-random</strong> data. The <code>TRNG_CTRL_SIM_MODE</code> flag of the control register is set if simulation +mode is active. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The TRNG features a single control register <code>CTRL</code> for control, status check and data access. When the <code>TRNG_CTRL_EN</code> +bit is set, the TRNG is enabled and starts operation. As soon as the <code>TRNG_CTRL_VALID</code> bit is set a new random data byte +is available and can be obtained from the lowest 8 bits of the <code>CTRL</code> register. If this bit is cleared, there is no +valid data available and the lowest 8 bit of the <code>CTRL</code> register are set to all-zero.</p> +</div> +<div class="paragraph"> +<p>An internal entropy FIFO can be configured using the <code>IO_TRNG_FIFO</code> generic. This FIFO automatically samples +new random data from the TRNG to provide some kind of <em>random data pool</em> for applications, which require a large number +of random data in a short time. The random data FIFO can be cleared at any time either by disabling the TRNG or by +setting the <code>TRNG_CTRL_FIFO_CLR</code> flag. The FIFO depth can be retrieved by software via the <code>TRNG_CTRL_FIFO_*</code> bits.</p> +</div> +<div class="paragraph"> +<p><strong>TRNG Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>As the neoTRNG is a rather slow entropy source, a "data available" interrupt is provided to inform the application +software that new random data is available. This interrupt can be trigger by either of two conditions: trigger the +interrupt if <em>any</em> random data is available (i.e. the data FIFO is not empty; <code>TRNG_CTRL_IRQ_SEL = 0</code>) or trigger +the interrupt if the random pool is full (i.e. the data FIFO is full; <code>TRNG_CTRL_IRQ_SEL = 1</code>). +Once the TRNG interrupt has fired it remains pending until the actual cause of the interrupt is resolved.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 27. TRNG register map (<code>struct NEORV32_TRNG</code>)</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 26.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 46.6669%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="9"><p class="tableblock"><code>0xfffffa00</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="9"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>7:0</code> <code>TRNG_CTRL_DATA_MSB : TRNG_CTRL_DATA_MSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">8-bit random data</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>15:8</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>19:16</code> <code>TRNG_CTRL_FIFO_MSB : TRNG_CTRL_FIFO_MSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FIFO depth, log2(<code>IO_TRNG_FIFO</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27:20</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27</code> <code>TRNG_CTRL_IRQ_SEL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">interrupt trigger select (0 = data available, 1 = FIFO full)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>28</code> <code>TRNG_CTRL_FIFO_CLR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">flush random data FIFO when set; flag auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>29</code> <code>TRNG_CTRL_SIM_MODE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">simulation mode (PRNG!)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>TRNG_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TRNG enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>TRNG_CTRL_VALID</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">random data is valid when set</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_custom_functions_subsystem_cfs">2.7.21. Custom Functions Subsystem (CFS)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_cfs.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_cfs.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_cfs.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>cfs_in_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom input conduit</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>cfs_out_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom output conduit</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CFS_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement CFS when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CFS_CONFIG</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom generic conduit</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CFS_IN_SIZE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">size of <code>cfs_in_i</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_CFS_OUT_SIZE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">size of <code>cfs_out_o</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">CFS interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The custom functions subsystem is meant for implementing custom tightly-coupled co-processors or interfaces. +IT provides up to 64 32-bit memory-mapped read/write registers (<code>REG</code>, see register map below) that can be +accessed by the CPU via normal load/store operations. The actual functionality of these register has to be +defined by the hardware designer. Furthermore, the CFS provides two IO conduits to implement custom on-chip +or off-chip interfaces.</p> +</div> +<div class="paragraph"> +<p>Just like any other externally-connected IP, logic implemented within the custom functions subsystem can operate +<em>independently</em> of the CPU providing true parallel processing capabilities. Potential use cases might include +dedicated hardware accelerators for en-/decryption (AES), signal processing (FFT) or AI applications +(CNNs) as well as custom IO systems like fast memory interfaces (DDR) and mass storage (SDIO), networking (CAN) +or real-time data transport (I2S).</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +If you like to implement <em>custom instructions</em> that are executed right within the CPU&#8217;s ALU +see the <a href="#_zxcfu_isa_extension"><code>Zxcfu</code> ISA Extension</a> and the according <a href="#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +Take a look at the template CFS VHDL source file (<code>rtl/core/neorv32_cfs.vhd</code>). The file is highly +commented to illustrate all aspects that are relevant for implementing custom CFS-based co-processor designs. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +The CFS can also be used to <em>replicate</em> existing NEORV32 modules - for example to implement several TWI controllers. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>CFS Software Access</strong></p> +</div> +<div class="paragraph"> +<p>The CFS memory-mapped registers can be accessed by software using the provided C-language aliases (see +register map table below). Note that all interface registers are defined as 32-bit words of type <code>uint32_t</code>.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 10. CFS Software Access Example</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">// C-code CFS usage example +NEORV32_CFS-&gt;REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0 +int temp = (int)NEORV32_CFS-&gt;REG[20]; // read from CFS register 20</code></pre> +</div> +</div> +<div class="paragraph"> +<p><strong>CFS Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>The CFS provides a single high-level-triggered interrupt request signal mapped to the CPU&#8217;s fast interrupt channel 1.</p> +</div> +<div class="paragraph"> +<p><strong>CFS Configuration Generic</strong></p> +</div> +<div class="paragraph"> +<p>By default, the CFS provides a single 32-bit <code>std_ulogic_vector</code> configuration generic <code>IO_CFS_CONFIG</code> +that is available in the processor&#8217;s top entity. This generic can be used to pass custom configuration options +from the top entity directly down to the CFS. The actual definition of the generic and it&#8217;s usage inside the +CFS is left to the hardware designer.</p> +</div> +<div class="paragraph"> +<p><strong>CFS Custom IOs</strong></p> +</div> +<div class="paragraph"> +<p>By default, the CFS also provides two unidirectional input and output conduits <code>cfs_in_i</code> and <code>cfs_out_o</code>. +These signals are directly propagated to the processor&#8217;s top entity. These conduits can be used to implement +application-specific interfaces like memory or peripheral connections. The actual use case of these signals +has to be defined by the hardware designer.</p> +</div> +<div class="paragraph"> +<p>The size of the input signal conduit <code>cfs_in_i</code> is defined via the top&#8217;s <code>IO_CFS_IN_SIZE</code> configuration +generic (default = 32-bit). The size of the output signal conduit <code>cfs_out_o</code> is defined via the top&#8217;s +<code>IO_CFS_OUT_SIZE</code> configuration generic (default = 32-bit). If the custom function subsystem is not implemented +(<code>IO_CFS_EN</code> = false) the <code>cfs_out_o</code> signal is tied to all-zero.</p> +</div> +<div class="paragraph"> +<p>If the CFU output signals are to be used outside the chip, it is recommended to register these signals.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 28. CFS register map (<code>struct NEORV32_CFS</code>)</caption> +<colgroup> +<col style="width: 25%;"> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +<col style="width: 37.5%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">Bit(s)</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xffffeb00</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>REG[0]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">(r)/(w)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom CFS register 0</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xffffeb04</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>REG[1]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">(r)/(w)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom CFS register 1</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">&#8230;&#8203;</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">&#8230;&#8203;</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">(r)/(w)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">&#8230;&#8203;</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xffffebf8</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>REG[62]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">(r)/(w)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom CFS register 62</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xffffebfc</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>REG[63]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">(r)/(w)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">custom CFS register 63</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_smart_led_interface_neoled">2.7.22. Smart LED Interface (NEOLED)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_neoled.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_neoled.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_neoled.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neoled_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_NEOLED_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement NEOLED controller when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_NEOLED_TX_FIFO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO depth, has to be a power of 2, min 1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 9</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">configurable NEOLED data FIFO interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The NEOLED module provides a dedicated interface for "smart RGB LEDs" like WS2812, WS2811 or any other compatible +LEDs. These LEDs provide a single-wire interface that uses an asynchronous serial protocol for transmitting color +data. Using the NEOLED module allows CPU-independent operation of an arbitrary number of smart LEDs. A configurable data +buffer (FIFO) allows to utilize block transfer operation without requiring the CPU.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The NEOLED interface is compatible to the "Adafruit Industries NeoPixel&#8482;" products, which feature +WS2812 (or older WS2811) smart LEDs. Other LEDs might be compatible as well when adjusting the controller&#8217;s programmable +timing configuration. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The interface provides a single 1-bit output <code>neoled_o</code> to drive an arbitrary number of cascaded LEDs. Since the +NEOLED module provides 24-bit and 32-bit operating modes, a mixed setup with RGB LEDs (24-bit color) +and RGBW LEDs (32-bit color including a dedicated white LED chip) is possible.</p> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The NEOLED modules provides two accessible interface registers: the control register <code>CTRL</code> and the write-only +TX data register <code>DATA</code>. The NEOLED module is globally enabled via the control register&#8217;s +<code>NEOLED_CTRL_EN</code> bit. Clearing this bit will terminate any current operation, clear the TX buffer, reset the module +and set the <code>neoled_o</code> output to zero. The precise timing (e.g. implementing the <strong>WS2812</strong> protocol) and transmission +mode are fully programmable via the <code>CTRL</code> register to provide maximum flexibility.</p> +</div> +<div class="paragraph"> +<p><strong>RGB / RGBW Configuration</strong></p> +</div> +<div class="paragraph"> +<p>NeoPixel&#8482; LEDs are available in two "color" version: LEDs with three chips providing RGB color and LEDs with +four chips providing RGB color plus a dedicated white LED chip (= RGBW). Since the intensity of every +LED chip is defined via an 8-bit value the RGB LEDs require a frame of 24-bit per module and the RGBW +LEDs require a frame of 32-bit per module.</p> +</div> +<div class="paragraph"> +<p>The data transfer quantity of the NEOLED module can be programmed via the <code>NEOLED_MODE_EN</code> control +register bit. If this bit is cleared, the NEOLED interface operates in 24-bit mode and will transmit bits <code>23:0</code> of +the data written to <code>DATA</code> to the LEDs. If <code>NEOLED_MODE_EN</code> is set, the NEOLED interface operates in 32-bit +mode and will transmit bits <code>31:0</code> of the data written to <code>DATA</code> to the LEDs.</p> +</div> +<div class="paragraph"> +<p>The mode bit can be reconfigured before writing a new data word to <code>DATA</code> in order to support an arbitrary setup/mixture +of RGB and RGBW LEDs.</p> +</div> +<div class="paragraph"> +<p><strong>Protocol</strong></p> +</div> +<div class="paragraph"> +<p>The interface of the WS2812 LEDs uses an 800kHz carrier signal. Data is transmitted in a serial manner +starting with LSB-first. The intensity for each R, G &amp; B (&amp; W) LED chip (= color code) is defined via an 8-bit +value. The actual data bits are transferred by modifying the duty cycle of the signal (the timings for the +WS2812 are shown below). A RESET command is "send" by pulling the data line LOW for at least 50ฮผs.</p> +</div> +<div class="imageblock text-left"> +<div class="content"> +<img src="img/neopixel_timing.png" alt="neopixel timing"> +</div> +<div class="title">Figure 8. WS2812 bit-level timing (timing does not scale)</div> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 29. WS2812 interface timing</caption> +<colgroup> +<col style="width: 20%;"> +<col style="width: 20%;"> +<col style="width: 60%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">T<sub>total</sub> (T<sub>carrier</sub>)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1.25ฮผs +/- 300ns</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">period for a single bit</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">T<sub>0H</sub></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0.4ฮผs +/- 150ns</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">high-time for sending a <code>1</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">T<sub>0L</sub></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0.8ฮผs +/- 150ns</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">low-time for sending a <code>1</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">T<sub>1H</sub></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0.85ฮผs +/- 150ns</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">high-time for sending a <code>0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">T<sub>1L</sub></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0.45ฮผs +/- 150 ns</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">low-time for sending a <code>0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">RESET</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Above 50ฮผs</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">low-time for sending a RESET command</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Timing Configuration</strong></p> +</div> +<div class="paragraph"> +<p>The basic carrier frequency (800kHz for the WS2812 LEDs) is configured via a 3-bit main clock prescaler +(<code>NEOLED_CTRL_PRSC*</code>, see table below) that scales the main processor clock f<sub>main</sub> and a 5-bit cycle +multiplier <code>NEOLED_CTRL_T_TOT_*</code>.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 30. NEOLED Prescaler Configuration</caption> +<colgroup> +<col style="width: 33.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3336%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"><strong><code>NEOLED_CTRL_PRSCx</code></strong></th> +<th class="tableblock halign-center valign-top"><code>0b000</code></th> +<th class="tableblock halign-center valign-top"><code>0b001</code></th> +<th class="tableblock halign-center valign-top"><code>0b010</code></th> +<th class="tableblock halign-center valign-top"><code>0b011</code></th> +<th class="tableblock halign-center valign-top"><code>0b100</code></th> +<th class="tableblock halign-center valign-top"><code>0b101</code></th> +<th class="tableblock halign-center valign-top"><code>0b110</code></th> +<th class="tableblock halign-center valign-top"><code>0b111</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting <code>clock_prescaler</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">128</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2048</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4096</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>The duty-cycles (or more precisely: the high- and low-times for sending either a '1' bit or a '0' bit) are +defined via the 5-bit <code>NEOLED_CTRL_T_ONE_H_*</code> and <code>NEOLED_CTRL_T_ZERO_H_*</code> values, respectively. These programmable +timing constants allow to adapt the interface for a wide variety of smart LED protocol (for example WS2812 vs. +WS2811).</p> +</div> +<div class="paragraph"> +<p><strong>Timing Configuration - Example (WS2812)</strong></p> +</div> +<div class="paragraph"> +<p>Generate the base clock f<sub>TX</sub> for the NEOLED TX engine:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>processor clock f<sub>main</sub> = 100 MHz</p> +</li> +<li> +<p><code>NEOLED_CTRL_PRSCx</code> = <code>0b001</code> = f<sub>main</sub> / 4</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><em><strong>f<sub>TX</sub></strong></em> = <em>f<sub>main</sub>[Hz]</em> / <code>clock_prescaler</code> = 100MHz / 4 = 25MHz</p> +</div> +<div class="paragraph"> +<p><em><strong>T<sub>TX</sub></strong></em> = 1 / <em><strong>f<sub>TX</sub></strong></em> = 40ns</p> +</div> +<div class="paragraph"> +<p>Generate carrier period (T<sub>carrier</sub>) and <strong>high-times</strong> (duty cycle) for sending <code>0</code> (T<sub>0H</sub>) and <code>1</code> (T<sub>1H</sub>) bits:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>NEOLED_CTRL_T_TOT</code> = <code>0b11110</code> (= decimal 30)</p> +</li> +<li> +<p><code>NEOLED_CTRL_T_ZERO_H</code> = <code>0b01010</code> (= decimal 10)</p> +</li> +<li> +<p><code>NEOLED_CTRL_T_ONE_H</code> = <code>0b10100</code> (= decimal 20)</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><em><strong>T<sub>carrier</sub></strong></em> = <em><strong>T<sub>TX</sub></strong></em> * <code>NEOLED_CTRL_T_TOT</code> = 40ns * 30 = 1.4ยตs</p> +</div> +<div class="paragraph"> +<p><em><strong>T<sub>0H</sub></strong></em> = <em><strong>T<sub>TX</sub></strong></em> * <code>NEOLED_CTRL_T_ZERO_H</code> = 40ns * 10 = 0.4ยตs</p> +</div> +<div class="paragraph"> +<p><em><strong>T<sub>1H</sub></strong></em> = <em><strong>T<sub>TX</sub></strong></em> * <code>NEOLED_CTRL_T_ONE_H</code> = 40ns * 20 = 0.8ยตs</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +The NEOLED SW driver library (<code>neorv32_neoled.h</code>) provides a simplified configuration +function that configures all timing parameters for driving WS2812 LEDs based on the processor +clock frequency. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>TX Data FIFO</strong></p> +</div> +<div class="paragraph"> +<p>The interface features a configurable TX data buffer (a FIFO) to allow more CPU-independent operation. The buffer +depth is configured via the <code>IO_NEOLED_TX_FIFO</code> top generic (default = 1 entry). The FIFO size configuration can be +read via the <code>NEOLED_CTRL_BUFS_x</code> control register bits, which result log2(<em>IO_NEOLED_TX_FIFO</em>).</p> +</div> +<div class="paragraph"> +<p>When writing data to the <code>DATA</code> register the data is automatically written to the TX buffer. Whenever +data is available in the buffer the serial transmission engine will take and transmit it to the LEDs. +The data transfer size (<code>NEOLED_MODE_EN</code>) can be modified at any time since this control register bit is also buffered +in the FIFO. This allows an arbitrary mix of RGB and RGBW LEDs in the chain.</p> +</div> +<div class="paragraph"> +<p>Software can check the FIFO fill level via the control register&#8217;s <code>NEOLED_CTRL_TX_EMPTY</code>, <code>NEOLED_CTRL_TX_HALF</code> +and <code>NEOLED_CTRL_TX_FULL</code> flags. The <code>NEOLED_CTRL_TX_BUSY</code> flags provides additional information if the the serial +transmit engine is still busy sending data.</p> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +Please note that the timing configurations (<code>NEOLED_CTRL_PRSCx</code>, <code>NEOLED_CTRL_T_TOT_x</code>, +<code>NEOLED_CTRL_T_ONE_H_x</code> and <code>NEOLED_CTRL_T_ZERO_H_x</code>) are <strong>NOT</strong> stored to the buffer. Changing +these value while the buffer is not empty or the TX engine is still busy will cause data corruption. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Strobe Command ("RESET")</strong></p> +</div> +<div class="paragraph"> +<p>According to the WS2812 specs the data written to the LED&#8217;s shift registers is strobed to the actual PWM driver +registers when the data line is low for 50ฮผs ("RESET" command, see table above). This can be implemented +using busy-wait for at least 50ฮผs. Obviously, this concept wastes a lot of processing power.</p> +</div> +<div class="paragraph"> +<p>To circumvent this, the NEOLED module provides an option to automatically issue an idle time for creating the RESET +command. If the <code>NEOLED_CTRL_STROBE</code> control register bit is set, <em>all</em> data written to the data FIFO (via <code>DATA</code>, +the actually written data is irrelevant) will trigger an idle phase (<code>neoled_o</code> = zero) of 127 periods (= <em><strong>T<sub>carrier</sub></strong></em>). +This idle time will cause the LEDs to strobe the color data into the PWM driver registers.</p> +</div> +<div class="paragraph"> +<p>Since the <code>NEOLED_CTRL_STROBE</code> flag is also buffered in the TX buffer, the RESET command is treated just as another +data word being written to the TX buffer making busy wait concepts obsolete and allowing maximum refresh rates.</p> +</div> +<div class="paragraph"> +<p><strong>NEOLED Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>The NEOLED modules features a single interrupt that triggers based on the current TX buffer fill level. +The interrupt can only become pending if the NEOLED module is enabled. The specific interrupt condition +is configured via the <code>NEOLED_CTRL_IRQ_CONF</code> bit in the unit&#8217;s control register.</p> +</div> +<div class="paragraph"> +<p>If <code>NEOLED_CTRL_IRQ_CONF</code> is set, the module&#8217;s interrupt is generated whenever the TX FIFO is less than half-full. +In this case software can write up to <code>IO_NEOLED_TX_FIFO</code>/2 new data words to <code>DATA</code> without checking the FIFO +status flags. If <code>NEOLED_CTRL_IRQ_CONF</code> is cleared, an interrupt is generated when the TX FIFO is empty.</p> +</div> +<div class="paragraph"> +<p>Once the NEOLED interrupt has fired it remains pending until the actual cause of the interrupt is resolved.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 31. NEOLED register map (<code>struct NEORV32_NEOLED</code>)</caption> +<colgroup> +<col style="width: 14.2857%;"> +<col style="width: 7.1428%;"> +<col style="width: 35.7142%;"> +<col style="width: 7.1428%;"> +<col style="width: 35.7145%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="13"><p class="tableblock"><code>0xfffffd00</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="13"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>NEOLED_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">NEOLED enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> <code>NEOLED_CTRL_MODE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">data transfer size; <code>0</code>=24-bit; <code>1</code>=32-bit</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>2</code> <code>NEOLED_CTRL_STROBE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code>=send normal color data; <code>1</code>=send RESET command on data write access</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>5:3</code> <code>NEOLED_CTRL_PRSC2 : NEOLED_CTRL_PRSC0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3-bit clock prescaler, bit 0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>9:6</code> <code>NEOLED_CTRL_BUFS3 : NEOLED_CTRL_BUFS0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4-bit log2(<em>IO_NEOLED_TX_FIFO</em>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>14:10</code> <code>NEOLED_CTRL_T_TOT_4 : NEOLED_CTRL_T_TOT_0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5-bit pulse clock ticks per total single-bit period (T<sub>total</sub>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>19:15</code> <code>NEOLED_CTRL_T_ZERO_H_4 : NEOLED_CTRL_T_ZERO_H_0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5-bit pulse clock ticks per high-time for sending a zero-bit (T<sub>0H</sub>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>24:20</code> <code>NEOLED_CTRL_T_ONE_H_4 : NEOLED_CTRL_T_ONE_H_0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5-bit pulse clock ticks per high-time for sending a one-bit (T<sub>1H</sub>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>27</code> <code>NEOLED_CTRL_IRQ_CONF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO interrupt configuration: <code>0</code>=IRQ if FIFO is empty, <code>1</code>=IRQ if FIFO is less than half-full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>28</code> <code>NEOLED_CTRL_TX_EMPTY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO is empty</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>29</code> <code>NEOLED_CTRL_TX_HALF</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO is <em>at least</em> half full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>NEOLED_CTRL_TX_FULL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX FIFO is full</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>NEOLED_CTRL_TX_BUSY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX serial engine is busy when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffd04</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DATA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code> / <code>23:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">TX data (32- or 24-bit, depending on <em>NEOLED_CTRL_MODE</em> bit)</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_external_interrupt_controller_xirq">2.7.23. External Interrupt Controller (XIRQ)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_xirq.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_xirq.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_xirq.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xirq_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">External interrupts input (32-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIRQ_NUM_CH</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of external IRQ channels to implement (0..32)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 8</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">XIRQ (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The external interrupt controller provides a simple mechanism to implement up to 32 platform-level / processor-external +interrupt request signals. The external IRQ requests are prioritized, queued and signaled to the CPU via a +<em>single</em> CPU fast interrupt request channel.</p> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>The XIRQ provides up to 32 external interrupt channels configured via the <code>XIRQ_NUM_CH</code> generic. Each bit in the +<code>xirq_i</code> input signal vector represents one interrupt channel. If less than 32 channels are configured, only the +LSB-aligned channels are used while the remaining ones are left unconnected internally.</p> +</div> +<div class="paragraph"> +<p>The external interrupt controller features five interface registers:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>external interrupt channel enable (<code>EIE</code>)</p> +</li> +<li> +<p>external interrupt channel pending (<code>EIP</code>)</p> +</li> +<li> +<p>external interrupt source (<code>ESC</code>)</p> +</li> +<li> +<p>trigger type configuration (<code>TTYP</code>)</p> +</li> +<li> +<p>trigger polarity configuration (<code>TPOL</code>)</p> +</li> +</ol> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +From a functional point of view, the <code>EIE</code>, <code>EIP</code> and <code>ESC</code> registers follow the behavior +of the RISC-V <a href="#_mie"><strong><code>mie</code></strong></a>, <a href="#_mip"><strong><code>mip</code></strong></a> and <a href="#_mcause"><strong><code>mcause</code></strong></a> CSRs. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The actual interrupt trigger type can be configured individually for each channel using the <code>TTYP</code> and <code>TPOL</code> +registers. <code>TTYP</code> defines the actual trigger type (level-triggered or edge-triggered), while <code>TPOL</code> defines +the trigger&#8217;s polarity (low-level/falling-edge or high-level_/rising-edge). The position of each bit in these +registers corresponds the according XIRQ channel.</p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 32. XIRQ Trigger Configuration</caption> +<colgroup> +<col style="width: 28.5714%;"> +<col style="width: 28.5714%;"> +<col style="width: 42.8572%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top"><code>TTYP(i)</code></th> +<th class="tableblock halign-center valign-top"><code>TPOL(i)</code></th> +<th class="tableblock halign-left valign-top">Resulting trigger of <code>xirq_i(i)</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">low-level</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">high-level</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">falling-edge</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">rising-edge</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>When the configured trigger of an interrupt channel fires the according interrupt channel becomes <em>pending</em> +which is indicated by the according channel bit being set in the <code>EIP</code> register. This pending interrupt can +be manually cleared at any time by writing zero to the according <code>EIP</code> bit.</p> +</div> +<div class="paragraph"> +<p>A pending interrupt can only generate a CPU interrupt if the according channel is enabled by the <code>EIE</code> +register. Once triggered, disabled channels that <strong>were already triggered</strong> remain pending until explicitly +(= manually) cleared. The channels are prioritized in a static order, i.e. channel 0 (<code>xirq_i(0)</code>) has the +highest priority and channel 31 (<code>xirq_i(31)</code>) has the lowest priority. If <strong>any</strong> pending interrupt channel is +also enabled, an interrupt request is sent to the CPU.</p> +</div> +<div class="paragraph"> +<p>The CPU can determine the most prioritized external interrupt request either by checking the bits in the <code>EIP</code> +register or by reading the interrupt source register <code>ESC</code>. This register provides a 5-bit wide ID (0..31) +identifying the currently firing external interrupt source channel. Writing <em>any</em> value to this register will +acknowledge and clear the <em>current</em> CPU interrupt (so the XIRQ controller can issue a new CPU interrupt).</p> +</div> +<div class="paragraph"> +<p>In order to acknowledge an XIRQ interrupt, the interrupt handler has to&#8230;&#8203; +* clear the pending XIRQ channel by clearing the according <code>EIP</code> bit +* writing <em>any</em> value to <code>ESC</code> to acknowledge the XIRQ CPU interrupt</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 33. XIRQ register map (<code>struct NEORV32_XIRQ</code>)</caption> +<colgroup> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 58.3335%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">Bit(s)</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xfffff300</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>EIE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">External interrupt enable register (one bit per channel, LSB-aligned)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xfffff304</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>EIP</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">External interrupt pending register (one bit per channel, LSB-aligned); writing 0 to a bit clears the according pending interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xfffff308</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ESC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>4:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Interrupt source ID (0..31) of firing IRQ (prioritized!); writing <em>any</em> value will acknowledge the current XIRQ CPU interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xfffff30c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TTYP</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger type select (<code>0</code> = level trigger, <code>1</code> = edge trigger); each bit corresponds to the according channel number</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xfffff310</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TPOL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger polarity select (<code>0</code> = low-level/falling-edge, <code>1</code> = high-level/rising-edge); each bit corresponds to the according channel number</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xfffff314</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xfffff318</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xfffff31c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_general_purpose_timer_gptmr">2.7.24. General Purpose Timer (GPTMR)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_gptmr.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_gptmr.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_gptmr.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IO_GPTMR_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement general purpose timer when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast IRQ channel 12</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">timer interrupt (see <a href="#_processor_interrupts">Processor Interrupts</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The general purpose timer module implements a simple yet universal 32-bit timer. It is implemented if the processor&#8217;s +<code>IO_GPTMR_EN</code> top generic is set <code>true</code>. The timer provides a pre-scaled counter register that can trigger an interrupt +when reaching a programmable threshold value.</p> +</div> +<div class="paragraph"> +<p>The GPTMR provides three interface registers : a control register (<code>CTRL</code>), a 32-bit counter register (<code>COUNT</code>) and a +32-bit threshold register (<code>THRES</code>). The timer is globally enabled by setting the <code>GPTMR_CTRL_EN</code> bit in the module&#8217;s +control register. When the timer is enable the <code>COUNT</code> register will start incrementing from zero at a programmable +rate that scales the main processor clock. this pre-scaler is configured via the three <code>GPTMR_CTRL_PRSCx</code> +control register bits:</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 34. GPTMR prescaler configuration</caption> +<colgroup> +<col style="width: 33.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3336%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"><strong><code>GPTMR_CTRL_PRSCx</code></strong></th> +<th class="tableblock halign-center valign-top"><code>0b000</code></th> +<th class="tableblock halign-center valign-top"><code>0b001</code></th> +<th class="tableblock halign-center valign-top"><code>0b010</code></th> +<th class="tableblock halign-center valign-top"><code>0b011</code></th> +<th class="tableblock halign-center valign-top"><code>0b100</code></th> +<th class="tableblock halign-center valign-top"><code>0b101</code></th> +<th class="tableblock halign-center valign-top"><code>0b110</code></th> +<th class="tableblock halign-center valign-top"><code>0b111</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting <code>clock_prescaler</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">128</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2048</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4096</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>Whenever the counter register <code>COUNT</code> equals the programmable threshold value <code>THRES</code> the module&#8217;s interrupt +signal becomes pending (indicated by <code>GPTMR_CTRL_IRQ_PND</code> being set). Note that a pending interrupt has to be +cleared manually by writing a <code>1</code> to <code>GPTMR_CTRL_IRQ_CLR</code>.</p> +</div> +<div class="paragraph"> +<p>The control register&#8217;s <code>GPTMR_CTRL_MODE</code> bit defines what will happen when <code>COUNT == THRES</code>.</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>GPTMR_CTRL_MODE = 0</code>: <strong>single-shot mode</strong> - the <code>COUNT</code> register will stop incrementing</p> +</li> +<li> +<p><code>GPTMR_CTRL_MODE = 1</code>: <strong>continuous mode</strong> - the <code>COUNT</code> register is automatically reset and restarts incrementing from zero</p> +</li> +</ul> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Resetting the Counter</div> +Disabling the GPTMR will also clear the <code>COUNT</code> register. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Interrupt</strong></p> +</div> +<div class="paragraph"> +<p>The GPTRM provides a single interrupt line is triggered whenever <code>COUNT</code> equals <code>THRES</code>. Once triggered, the interrupt will +stay pending until explicitly cleared by writing a 1 to <code>GPTMR_CTRL_IRQ_CLR</code>.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 35. GPTMR register map (<code>struct NEORV32_GPTMR</code>)</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 11.1111%;"> +<col style="width: 22.2222%;"> +<col style="width: 5.5555%;"> +<col style="width: 38.889%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="6"><p class="tableblock"><code>0xfffff100</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="6"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>GPTMR_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Timer enable flag</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>3:1</code> <code>GPTMR_CTRL_PRSC2 : GPTMR_CTRL_PRSC0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3-bit clock prescaler select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>4</code> <code>GPTMR_CTRL_MODE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Operation mode (0=single-shot, 1=continuous)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>29:5</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>GPTMR_CTRL_IRQ_CLR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Write <code>1</code> to clear timer-match interrupt; auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>GPTMR_CTRL_IRQ_PND</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Timer-match interrupt pending</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff104</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>THRES</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Threshold value register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffff108</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>COUNT</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Counter register</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_execute_in_place_module_xip">2.7.25. Execute In Place Module (XIP)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_xip.vhd</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">XIP module</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_cache.vhd</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generic cache module</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_xip.c</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_xip.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip_csn_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit chip select, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip_clk_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial clock output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip_dat_i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data input</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip_dat_o</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1-bit serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement XIP module when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_CACHE_EN</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">implement XIP cache when <code>true</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_CACHE_NUM_BLOCKS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of blocks in XIP cache; has to be a power of two</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_CACHE_BLOCK_SIZE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of bytes per XIP cache block; has to be a power of two, min 4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">control registers: privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">XIP data access: read-only</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The execute in-place (XIP) module allows to execute code (and read constant data) directly from an external SPI flash memory. +The standard serial peripheral interface (SPI) is used as transfer protocol. All bus requests issued by the CPU +are converted transparently into SPI flash access commands. Hence, the external XIP flash behaves like a simple on-chip ROM.</p> +</div> +<div class="paragraph"> +<p>From the CPU side, the modules provides two independent interfaces: one for transparently accessing the XIP flash and another +one for accessing the module&#8217;s control and status registers. The first interface provides the <em>transparent</em> +gateway to the SPI flash, so the CPU can directly fetch and execute instructions and/or read constant data. +Note that this interface is read-only. Any write access will raise a bus error exception. The second interface is +mapped to the processor&#8217;s IO space and allows accesses to the XIP module&#8217;s configuration registers as well as +conducting individual SPI transfers.</p> +</div> +<div class="paragraph"> +<p>The XIP module provides an optional configurable cache to accelerate SPI flash accesses.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">XIP Address Mapping</div> +When XIP mode is enabled the flash is mapped to fixed address space region starting at address +<code>0xE0000000</code> (see section <a href="#_address_space">Address Space</a>) supporting a maximum flash size of 256MB. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">XIP Example Program</div> +An example program is provided in <code>sw/example/demo_xip</code> that illustrate how to program and configure +an external SPI flash to run a program from it. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>SPI Configuration</strong></p> +</div> +<div class="paragraph"> +<p>The XIP module accesses external flash using the standard SPI protocol. The module always sends data MSB-first and +provides all of the standard four clock modes (0..3), which are configured via the <code>XIP_CTRL_CPOL</code> (clock polarity) +and <code>XIP_CTRL_CPHA</code> (clock phase) control register bits, respectively. The flash&#8217;s "read command", which initiates +a read access, is defined by the <code>XIP_CTRL_RD_CMD</code> control register bits. For most SPI flash memories this is <code>0x03</code> +for <em>normal</em> SPI mode.</p> +</div> +<div class="paragraph"> +<p>The SPI clock (<code>xip_clk_o</code>) frequency is programmed by the 3-bit <code>XIP_CTRL_PRSCx</code> clock prescaler for a coarse clock +selection and a 4-bit clock divider <code>XPI_CTRL_CDIVx</code> for a fine clock selection. +The following clock prescalers (<code>XIP_CTRL_PRSCx</code>) are available:</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 36. XIP clock prescaler configuration</caption> +<colgroup> +<col style="width: 33.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 8.3336%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"><strong><code>XIP_CTRL_PRSCx</code></strong></th> +<th class="tableblock halign-center valign-top"><code>0b000</code></th> +<th class="tableblock halign-center valign-top"><code>0b001</code></th> +<th class="tableblock halign-center valign-top"><code>0b010</code></th> +<th class="tableblock halign-center valign-top"><code>0b011</code></th> +<th class="tableblock halign-center valign-top"><code>0b100</code></th> +<th class="tableblock halign-center valign-top"><code>0b101</code></th> +<th class="tableblock halign-center valign-top"><code>0b110</code></th> +<th class="tableblock halign-center valign-top"><code>0b111</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Resulting <code>clock_prescaler</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">128</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1024</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">2048</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4096</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>Based on the programmed clock configuration, the actual SPI clock frequency f<sub>SPI</sub> is derived +from the processor&#8217;s main clock f<sub>main</sub> according to the following equation:</p> +</div> +<div class="paragraph"> +<p><em><strong>f<sub>SPI</sub></strong></em> = <em>f<sub>main</sub>[Hz]</em> / (2 * <code>clock_prescaler</code> * (1 + <code>XPI_CTRL_CDIVx</code>))</p> +</div> +<div class="paragraph"> +<p>Hence, the maximum SPI clock is f<sub>main</sub> / 4 and the lowest SPI clock is f<sub>main</sub> / 131072. The SPI clock is always +symmetric having a duty cycle of 50%.</p> +</div> +<div class="paragraph"> +<p><strong>High-Speed Mode</strong></p> +</div> +<div class="paragraph"> +<p>The XIP module provides a high-speed mode to further boost the maximum SPI clock frequency. When enabled via the control +register&#8217;s <code>XIP_CTRL_HIGHSPEED</code> bit the clock prescaler configuration (<code>XIP_CTRL_PRSCx</code> bits) is overridden setting it +to a minimal factor of 1. However, the clock speed can still be fine-tuned using the <code>XPI_CTRL_CDIVx</code> bits.</p> +</div> +<div class="paragraph"> +<p><em><strong>f<sub>SPI</sub></strong></em> = <em>f<sub>main</sub>[Hz]</em> / (2 * 1 * (1 + <code>XPI_CTRL_CDIVx</code>))</p> +</div> +<div class="paragraph"> +<p>Hence, the maximum SPI clock when in high-speed mode is f<sub>main</sub> / 2.</p> +</div> +<div class="paragraph"> +<p><strong>Direct SPI Access</strong></p> +</div> +<div class="paragraph"> +<p>The XIP module allows to initiate <em>direct</em> SPI transactions. This feature can be used to configure the attached SPI +flash or to perform direct read and write accesses to the flash memory. Two data registers <code>DATA_LO</code> and +<code>DATA_HI</code> are provided to send up to 64-bit of SPI data. The <code>DATA_HI</code> register is write-only, +so a total of just 32-bits of receive data is provided. Note that the module handles the chip-select +line (<code>xip_csn_o</code>) by itself so it is not possible to construct larger consecutive transfers.</p> +</div> +<div class="paragraph"> +<p>The actual data transmission size in bytes is defined by the control register&#8217;s <code>XIP_CTRL_SPI_NBYTES</code> bits. +Any configuration from 1 byte to 8 bytes is valid. Other value will result in unpredictable behavior.</p> +</div> +<div class="paragraph"> +<p>Since data is always transferred MSB-first, the data in <code>DATA_HI:DATA_LO</code> also has to be MSB-aligned. Receive data is +available in <code>DATA_LO</code> only since <code>DATA_HI</code> is write-only. Writing to <code>DATA_HI</code> triggers the actual SPI transmission. +The <code>XIP_CTRL_PHY_BUSY</code> control register flag indicates a transmission being in progress.</p> +</div> +<div class="paragraph"> +<p>The chip-select line of the XIP module (<code>xip_csn_o</code>) will only become asserted (enabled, pulled low) if the +<code>XIP_CTRL_SPI_CSEN</code> control register bit is set. If this bit is cleared, <code>xip_csn_o</code> is always disabled +(pulled high).</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Direct SPI mode is only possible when the module is enabled (setting <code>XIP_CTRL_EN</code>) but <strong>before</strong> the actual +XIP mode is enabled via <code>XIP_CTRL_XIP_EN</code>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +When the XIP mode is not enabled, the XIP module can also be used as additional general purpose SPI controller +with a transfer size of up to 64 bits per transmission. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Using the XIP Mode</strong></p> +</div> +<div class="paragraph"> +<p>The XIP module is globally enabled by setting the <code>XIP_CTRL_EN</code> bit in the device&#8217;s <code>CTRL</code> control register. +Clearing this bit will reset the whole module and will also terminate any pending SPI transfer.</p> +</div> +<div class="paragraph"> +<p>Since there is a wide variety of SPI flash components with different sizes, the XIP module allows to specify +the address width of the flash: the number of address bytes used for addressing flash memory content has to be +configured using the control register&#8217;s <em>XIP_CTRL_XIP_ABYTES</em> bits. These two bits contain the number of SPI +address bytes (<strong>minus one</strong>). For example for a SPI flash with 24-bit addresses these bits have to be set to +<code>0b10</code>.</p> +</div> +<div class="paragraph"> +<p>The transparent XIP accesses are transformed into SPI transmissions with the following format (starting with the MSB):</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>8-bit command: configured by the <code>XIP_CTRL_RD_CMD</code> control register bits ("SPI read command")</p> +</li> +<li> +<p>8 to 32 bits address: defined by the <code>XIP_CTRL_XIP_ABYTES</code> control register bits ("number of address bytes")</p> +</li> +<li> +<p>32-bit data: sending zeros and receiving the according flash word (32-bit)</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>Hence, the maximum XIP transmission size is 72-bit, which has to be configured via the <code>XIP_CTRL_SPI_NBYTES</code> +control register bits. Note that the 72-bit transmission size is only available in XIP mode. The transmission +size of the direct SPI accesses is limited to 64-bit.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +When using four SPI flash address bytes, the most significant 4 bits of the address are always hardwired +to zero allowing a maximum <strong>accessible</strong> flash size of 256MB. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The XIP module always fetches a full naturally aligned 32-bit word from the SPI flash. Any sub-word data masking +or alignment will be performed by the CPU core logic. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +The XIP mode requires the 4-byte data words in the flash to be ordered in <strong>little-endian</strong> byte order. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>After the SPI properties (including the amount of address bytes <strong>and</strong> the total amount of SPI transfer bytes) +and XIP address mapping are configured, the actual XIP mode can be enabled by setting +the control register&#8217;s <code>XIP_CTRL_XIP_EN</code> bit. This will enable the "transparent SPI access port" of the module and thus, +the <em>transparent</em> conversion of access requests into proper SPI flash transmissions. Hence, any access to the processor&#8217;s +memory-mapped XIP region (<code>0xE0000000</code> to <code>0xEFFFFFFF</code>) will be converted into SPI flash accesses. +Make sure <code>XIP_CTRL_SPI_CSEN</code> is also set so the module can actually select/enable the attached SPI flash. +No more direct SPI accesses via <code>DATA_HI:DATA_LO</code> are possible when the XIP mode is enabled. However, the +XIP mode can be disabled at any time.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +If the XIP module is disabled (<em>XIP_CTRL_EN</em> = <code>0</code>) any accesses to the memory-mapped XIP flash address region +will raise a bus access exception. If the XIP module is enabled (<em>XIP_CTRL_EN</em> = <code>1</code>) but XIP mode is not enabled +yet (<em>XIP_CTRL_XIP_EN</em> = '0') any access to the programmed XIP memory segment will also raise a bus access exception. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +It is highly recommended to enable the <a href="#_processor_internal_instruction_cache_icache">Processor-Internal Instruction Cache (iCACHE)</a> to cover some +of the SPI access latency. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>XIP Cache</strong></p> +</div> +<div class="paragraph"> +<p>Since every single instruction fetch request from the CPU is translated into serial SPI transmissions the access latency is +very high resulting in a low throughput. In order to improve performance, the XIP module provides an optional cache that +allows to buffer recently-accessed data. The cache is implemented as a simple direct-mapped read-only cache with a configurable +cache layout:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>XIP_CACHE_EN</code>: when set to <code>true</code> the CIP cache is implemented</p> +</li> +<li> +<p><code>XIP_CACHE_NUM_BLOCKS</code> defines the number of cache blocks (or lines)</p> +</li> +<li> +<p><code>XIP_CACHE_BLOCK_SIZE</code> defines the size in bytes of each cache block</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>When the cache is implemented, the XIP module operates in <strong>burst mode</strong> utilizing the flash&#8217;s <em>incremental read</em> capabilities. +Thus, several bytes (= <code>XIP_CACHE_BLOCK_SIZE</code>) are read consecutively from the flash using a single read command.</p> +</div> +<div class="paragraph"> +<p>The XIP cache is cleared when the XIP module is disabled (<code>XIP_CTRL_EN = 0</code>), when XIP mode is disabled +(<code>XIP_CTRL_XIP_EN = 0</code>) or when the CPU issues a <code>fence(.i)</code> instruction.</p> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 37. XIP Register Map (<code>struct NEORV32_XIP</code>)</caption> +<colgroup> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 26.6666%;"> +<col style="width: 6.6666%;"> +<col style="width: 46.6669%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Bit(s), Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="14"><p class="tableblock"><code>0xffffff40</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="14"><p class="tableblock"><code>CTRL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> <code>XIP_CTRL_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">XIP module enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>3:1</code> <code>XIP_CTRL_PRSC2 : XIP_CTRL_PRSC0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3-bit SPI clock prescaler select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>4</code> <code>XIP_CTRL_CPOL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI clock polarity</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>5</code> <code>XIP_CTRL_CPHA</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI clock phase</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>9:6</code> <code>XIP_CTRL_SPI_NBYTES_MSB : XIP_CTRL_SPI_NBYTES_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of bytes in SPI transaction (1..9)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>10</code> <code>XIP_CTRL_XIP_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">XIP mode enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>12:11</code> <code>XIP_CTRL_XIP_ABYTES_MSB : XIP_CTRL_XIP_ABYTES_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Number of address bytes for XIP flash (minus 1)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>20:13</code> <code>XIP_CTRL_RD_CMD_MSB : XIP_CTRL_RD_CMD_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Flash read command</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>21</code> <code>XIP_CTRL_SPI_CSEN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Allow SPI chip-select to be actually asserted when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>22</code> <code>XIP_CTRL_HIGHSPEED</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">enable SPI high-speed mode (ignoring <code>XIP_CTRL_PRSCx</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>26:23</code> <code>XIP_CTRL_CDIV3 : XIP_CTRL_CDIV0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4-bit clock divider for fine-tuning</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>29:27</code> -</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>30</code> <code>XIP_CTRL_PHY_BUSY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI PHY busy when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31</code> <code>XIP_CTRL_XIP_BUSY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">XIP access in progress when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffff44</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffff48</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DATA_LO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Direct SPI access - data register low</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xffffff4C</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DATA_HI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>31:0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Direct SPI access - data register high; write access triggers SPI transfer</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_system_configuration_information_memory_sysinfo">2.7.26. System Configuration Information Memory (SYSINFO)</h4> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 30%;"> +<col style="width: 30%;"> +<col style="width: 40%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware source files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_sysinfo.vhd</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Software driver files:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">neorv32_sysinfo.h</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Top entity ports:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration generics:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">*</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">most of the top&#8217;s configuration generics</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU interrupts:</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">none</p></td> +<td class="tableblock halign-left valign-top"></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access restrictions:</p></td> +<td class="tableblock halign-left valign-top" colspan="2"><p class="tableblock">privileged access only, non-32-bit write accesses are ignored</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>Overview</strong></p> +</div> +<div class="paragraph"> +<p>The SYSINFO module allows the application software to determine the setting of most of the <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a> +that are related to CPU and processor/SoC configuration. This device is always implemented - regardless of the actual hardware +configuration since the NEORV32 software framework requires information from this device for correct operation. +However, advanced users that do not want to use the default NEORV32 software framework can choose to disable the +entire SYSINFO module. This might also be suitable for setups that use the processor just as wrapper for a CPU-only +configuration.</p> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Disabling the SYSINFO Module</div> +Setting the <code>IO_DISABLE_SYSINFO</code> top entity generic to <code>true</code> will remove the SYSINFO module from the design. +This option is suitable for advanced uses that wish to use a CPU-only setup that still contains the bus infrastructure. +As a result, large parts of the NEORV32 software framework no longer work (e.g. most IO drivers, the RTE and the bootloader). +<strong>Hence, this option is not recommended.</strong> +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Register Map</strong></p> +</div> +<div class="paragraph"> +<p>All registers of this module are read-only except for the <code>CLK</code> register. Upon reset, the <code>CLK</code> registers is initialized +from the <code>CLOCK_FREQUENCY</code> top entity generic. Application software can override this default value in order, for example, +to take into account a dynamic frequency scaling of the processor.</p> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 38. SYSINFO register map (<code>struct NEORV32_SYSINFO</code>)</caption> +<colgroup> +<col style="width: 18.1818%;"> +<col style="width: 9.0909%;"> +<col style="width: 9.0909%;"> +<col style="width: 63.6364%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffe00</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CLK</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">clock frequency in Hz (initialized from top&#8217;s <code>CLOCK_FREQUENCY</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffe04</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MEM[4]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">internal memory configuration (see <a href="#_sysinfo_memory_configuration">SYSINFO - Memory Configuration</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffe08</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SOC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">specific SoC configuration (see <a href="#_sysinfo_soc_configuration">SYSINFO - SoC Configuration</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfffffe0c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CACHE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">cache configuration information (see <a href="#_sysinfo_cache_configuration">SYSINFO - Cache Configuration</a>)</p></td> +</tr> +</tbody> +</table> +<div class="sect4"> +<h5 id="_sysinfo_memory_configuration">SYSINFO - Memory Configuration</h5> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Bit fields in this register are set to all-zero if the according memory system is not implemented. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 39. SYSINFO <code>MEM</code> Bytes</caption> +<colgroup> +<col style="width: 10%;"> +<col style="width: 20%;"> +<col style="width: 70%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Byte</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_MEM_IMEM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(internal IMEM size in bytes), via top&#8217;s <code>MEM_INT_IMEM_SIZE</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_MEM_DMEM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(internal DMEM size in bytes), via top&#8217;s <code>MEM_INT_DMEM_SIZE</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>2</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>3</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_sysinfo_soc_configuration">SYSINFO - SoC Configuration</h5> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 40. SYSINFO <code>SOC</code> Bits</caption> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 33.3333%;"> +<col style="width: 55.5556%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_BOOTLOADER</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if processor-internal bootloader is implemented (via top&#8217;s <code>INT_BOOTLOADER_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_XBUS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if external Wishbone bus interface is implemented (via top&#8217;s <code>XBUS_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>2</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_MEM_INT_IMEM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if processor-internal DMEM implemented (via top&#8217;s <code>MEM_INT_DMEM_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>3</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_MEM_INT_DMEM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if processor-internal IMEM is implemented (via top&#8217;s <code>MEM_INT_IMEM_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>4</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_OCD</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if on-chip debugger is implemented (via top&#8217;s <code>ON_CHIP_DEBUGGER_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>5</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_ICACHE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if processor-internal instruction cache is implemented (via top&#8217;s <code>ICACHE_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>6</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_DCACHE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if processor-internal data cache is implemented (via top&#8217;s <code>DCACHE_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>7</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_CLOCK_GATING</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if CPU clock gating is implemented (via top&#8217;s <code>CLOCK_GATING_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>8</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_XBUS_CACHE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if external bus interface cache is implemented (via top&#8217;s <code>XBUS_CACHE_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>9</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_XIP</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if XIP module is implemented (via top&#8217;s <code>XIP_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>10</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_XIP_CACHE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if XIP cache is implemented (via top&#8217;s <code>XIP_CACHE_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>13:11</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, read as zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>14</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_DMA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if direct memory access controller is implemented (via top&#8217;s <code>IO_DMA_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>15</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_GPIO</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if GPIO is implemented (via top&#8217;s <code>IO_GPIO_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>16</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_MTIME</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if MTIME is implemented (via top&#8217;s <code>IO_MTIME_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>17</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_UART0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if primary UART0 is implemented (via top&#8217;s <code>IO_UART0_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>18</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_SPI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if SPI is implemented (via top&#8217;s <code>IO_SPI_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>19</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_TWI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if TWI is implemented (via top&#8217;s <code>IO_TWI_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>20</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_PWM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if PWM is implemented (via top&#8217;s <code>IO_PWM_NUM_CH</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>21</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_WDT</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if WDT is implemented (via top&#8217;s <code>IO_WDT_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>22</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_CFS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if custom functions subsystem is implemented (via top&#8217;s <code>IO_CFS_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>23</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_TRNG</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if TRNG is implemented (via top&#8217;s <code>IO_TRNG_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>24</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_SDI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if SDI is implemented (via top&#8217;s <code>IO_SDI_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>25</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_UART1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if secondary UART1 is implemented (via top&#8217;s <code>IO_UART1_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>26</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_NEOLED</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if NEOLED is implemented (via top&#8217;s <code>IO_NEOLED_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>27</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_XIRQ</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if XIRQ is implemented (via top&#8217;s <code>XIRQ_NUM_CH</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>28</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_GPTMR</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if GPTMR is implemented (via top&#8217;s <code>IO_GPTMR_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>29</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_SLINK</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if stream link interface is implemented (via top&#8217;s <code>IO_SLINK_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>30</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_ONEWIRE</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if ONEWIRE interface is implemented (via top&#8217;s <code>IO_ONEWIRE_EN</code> generic)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_SOC_IO_CRC</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if cyclic redundancy check unit is implemented (via top&#8217;s <code>IO_CRC_EN</code> generic)</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_sysinfo_cache_configuration">SYSINFO - Cache Configuration</h5> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Bit fields in this register are set to all-zero if the according cache is not implemented. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 41. SYSINFO <code>CACHE</code> Bits</caption> +<colgroup> +<col style="width: 4.7619%;"> +<col style="width: 47.619%;"> +<col style="width: 47.6191%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>3:0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_CACHE_INST_BLOCK_SIZE_3 : SYSINFO_CACHE_INST_BLOCK_SIZE_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(i-cache block size in bytes), via top&#8217;s <code>ICACHE_BLOCK_SIZE</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>7:4</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_CACHE_INST_NUM_BLOCKS_3 : SYSINFO_CACHE_INST_NUM_BLOCKS_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(i-cache number of cache blocks), via top&#8217;s <code>ICACHE_NUM_BLOCKS</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>11:8</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_CACHE_DATA_BLOCK_SIZE_3 : SYSINFO_CACHE_DATA_BLOCK_SIZE_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(d-cache block size in bytes), via top&#8217;s <code>DCACHE_BLOCK_SIZE</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>15:12</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_CACHE_DATA_NUM_BLOCKS_3 : SYSINFO_CACHE_DATA_NUM_BLOCKS_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(d-cache number of cache blocks), via top&#8217;s <code>DCACHE_NUM_BLOCKS</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>19:16</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_CACHE_XIP_BLOCK_SIZE_3 : SYSINFO_CACHE_XIP_BLOCK_SIZE_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(xip-cache block size in bytes), via top&#8217;s <code>XIP_CACHE_BLOCK_SIZE</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>23:20</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_CACHE_XIP_NUM_BLOCKS_3 : SYSINFO_CACHE_XIP_NUM_BLOCKS_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(xip-cache number of cache blocks), via top&#8217;s <code>XIP_CACHE_NUM_BLOCKS</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>27:24</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_CACHE_XBUS_BLOCK_SIZE_3 : SYSINFO_CACHE_XBUS_BLOCK_SIZE_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(xbus-cache block size in bytes), via top&#8217;s <code>XBUS_CACHE_BLOCK_SIZE</code> generic</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>31:28</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SYSINFO_CACHE_XBUS_NUM_BLOCKS_3 : SYSINFO_CACHE_XBUS_NUM_BLOCKS_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>log2</em>(xbus-cache number of cache blocks), via top&#8217;s <code>XBUS_CACHE_NUM_BLOCKS</code> generic</p></td> +</tr> +</tbody> +</table> +</div> +</div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_neorv32_central_processing_unit_cpu">3. NEORV32 Central Processing Unit (CPU)</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 CPU is an area-optimized RISC-V core implementing the <code>rv32i_zicsr_zifencei</code> base (privileged) ISA and +supporting several additional/optional ISA extensions. The CPU&#8217;s micro architecture is based on a von-Neumann +machine build upon a mixture of multi-cycle and pipelined execution schemes.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +This chapter assumes that the reader is familiar with the official +RISC-V <em>User</em> and <em>Privileged Architecture</em> specifications. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Section Structure</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_risc_v_compatibility">RISC-V Compatibility</a></p> +</li> +<li> +<p><a href="#_cpu_top_entity_signals">CPU Top Entity - Signals</a> and <a href="#_cpu_top_entity_generics">CPU Top Entity - Generics</a></p> +</li> +<li> +<p><a href="#_architecture">Architecture</a> and <a href="#_full_virtualization">Full Virtualization</a></p> +</li> +<li> +<p><a href="#_instruction_sets_and_extensions">Instruction Sets and Extensions</a> and <a href="#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a></p> +</li> +<li> +<p><a href="#_control_and_status_registers_csrs">Control and Status Registers (CSRs)</a></p> +</li> +<li> +<p><a href="#_traps_exceptions_and_interrupts">Traps, Exceptions and Interrupts</a></p> +</li> +<li> +<p><a href="#_bus_interface">Bus Interface</a></p> +</li> +</ul> +</div> +<div class="sect2"> +<h3 id="_risc_v_compatibility">3.1. RISC-V Compatibility</h3> +<div class="paragraph"> +<p>The NEORV32 CPU passes the tests of the <strong>official RISCOF RISC-V Architecture Test Framework</strong>. This framework is used to check +RISC-V implementations for compatibility to the official RISC-V user/privileged ISA specifications. The NEORV32 port of this +test framework is available in a separate repository at GitHub: <a href="https://github.com/stnolting/neorv32-riscof" class="bare">https://github.com/stnolting/neorv32-riscof</a></p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Unsupported ISA Extensions</div> +Executing instructions or accessing CSRs from yet unsupported ISA extensions will raise an illegal +instruction exception (see section <a href="#_full_virtualization">Full Virtualization</a>). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Incompatibility Issues and Limitations</strong></p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title"><code>time[h]</code> CSRs (Wall Clock Time)</div> +The NEORV32 does not implement the <code>time[h]</code> registers. Any access to these registers will trap. It is +recommended that the trap handler software provides a means of accessing the platform-defined <a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">No Hardware Support of Misaligned Memory Accesses</div> +The CPU does not support resolving unaligned memory access by the hardware (this is not a +RISC-V-incompatibility issue but an important thing to know!). Any kind of unaligned memory access +will raise an exception to allow a <em>software-based</em> emulation provided by the application. However, unaligned memory +access can be <strong>emulated</strong> using the NEORV32 runtime environment. See section <a href="#_application_context_handling">Application Context Handling</a> +for more information. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_cpu_top_entity_signals">3.2. CPU Top Entity - Signals</h3> +<div class="paragraph"> +<p>The following table shows all interface signals of the CPU top entity <code>rtl/core/neorv32_cpu.vhd</code>. The +type of all signals is <em>std_ulogic</em> or <em>std_ulogic_vector</em>, respectively. The "Dir." column shows the signal +direction as seen from the CPU.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 42. NEORV32 CPU Signal List</caption> +<colgroup> +<col style="width: 25%;"> +<col style="width: 25%;"> +<col style="width: 8.3333%;"> +<col style="width: 41.6667%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Signal</th> +<th class="tableblock halign-center valign-top">Width/Type</th> +<th class="tableblock halign-center valign-top">Dir</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Global Signals</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>clk_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Global clock line, all registers triggering on rising edge, this clock can be switched off during <a href="#_sleep_mode">Sleep Mode</a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>clk_aux_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Always-on clock, used to keep the the sleep control active when <code>clk_i</code> is switched off</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rstn_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Global reset, low-active</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sleep_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU is in <a href="#_sleep_mode">Sleep Mode</a> when set</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>debug_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU is in <a href="#_cpu_debug_mode">debug mode</a> when set</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Interrupts (<a href="#_traps_exceptions_and_interrupts">Traps, Exceptions and Interrupts</a>)</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>msi_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RISC-V machine software interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mei_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RISC-V machine external interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mti_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RISC-V machine timer interrupt</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>firq_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Custom fast interrupt request signals</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>dbi_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Request CPU to halt and enter debug mode (RISC-V <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Instruction <a href="#_bus_interface">Bus Interface</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ibus_req_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>bus_req_t</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction fetch bus request</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ibus_rsp_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>bus_rsp_t</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction fetch bus response</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>Data <a href="#_bus_interface">Bus Interface</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>dbus_req_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>bus_req_t</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Data access (load/store) bus request</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>dbus_rsp_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>bus_rsp_t</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Data access (load/store) bus response</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Bus Interface Protocol</div> +See section <a href="#_bus_interface">Bus Interface</a> for the instruction fetch and data access interface protocol and the +according interface types (<code>bus_req_t</code> and <code>bus_rsp_t</code>). +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_cpu_top_entity_generics">3.3. CPU Top Entity - Generics</h3> +<div class="paragraph"> +<p>Most of the CPU configuration generics are a subset of the actual Processor configuration generics +(see section <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a>). and are not listed here. However, the CPU provides +some <em>specific</em> generics that are used to configure the CPU for the NEORV32 processor setup. These generics +are assigned by the processor setup only and are not available for user defined configuration. +The specific generics are listed below.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Table Abbreviations</div> +The generic type "suv(x:y)" represents a <code>std_ulogic_vector(x downto y)</code>. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 43. NEORV32 CPU-Exclusive Generic List</caption> +<colgroup> +<col style="width: 28.5714%;"> +<col style="width: 14.2857%;"> +<col style="width: 57.1429%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Name</th> +<th class="tableblock halign-center valign-top">Type</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>VENDOR_ID</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">suv(31:0)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Value for the <a href="#_mvendorid"><strong><code>mvendorid</code></strong></a> CSR.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>BOOT_ADDR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">suv(31:0)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU reset address. See section <a href="#_address_space">Address Space</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DEBUG_PARK_ADDR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">suv(31:0)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Park loop" entry address for the <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a>, has to be 4-byte aligned.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DEBUG_EXC_ADDR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">suv(31:0)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Exception" entry address for the <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a>, has to be 4-byte aligned.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Sdext</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement RISC-V-compatible "debug" CPU operation mode required for the <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Sdtrig</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement RISC-V-compatible trigger module. See section <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_ISA_Smpmp</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">boolean</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Implement RISC-V-compatible physical memory protection (PMP). See section <a href="#_smpmp_isa_extension"><code>Smpmp</code> ISA Extension</a>.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_architecture">3.4. Architecture</h3> +<div class="imageblock text-center"> +<div class="content"> +<img src="img/neorv32_cpu.png" alt="neorv32 cpu"> +</div> +</div> +<div class="paragraph"> +<p>The CPU implements a pipelined multi-cycle architecture: each instruction is executed as a series of consecutive +micro-operations. In order to increase performance, the CPU&#8217;s front-end (instruction fetch) and back-end +(instruction execution) are de-couples via a FIFO (the instruction prefetch buffer. Thus, the front-end can already +fetch new instructions while the back-end is still processing the previously-fetched instructions.</p> +</div> +<div class="paragraph"> +<p>Basically, the CPU&#8217;s micro architecture is somewhere between a classical pipelined architecture, where each stage +requires exactly one processing cycle (if not stalled) and a classical multi-cycle architecture, which executes +every single instruction (<em>including</em> fetch) in a series of consecutive micro-operations. The combination of these +two design paradigms allows an increased instruction execution in contrast to a pure multi-cycle approach (due to +overlapping operation of fetch and execute) at a reduced hardware footprint (due to the multi-cycle concept).</p> +</div> +<div class="paragraph"> +<p>As a Von-Neumann machine, the CPU provides independent interfaces for instruction fetch and data access. However, +these two bus interfaces are merged into a single processor-internal bus via a prioritizing bus switch (data accesses +have higher priority). Hence, <em>all</em> memory addresses including peripheral devices are mapped to a single unified 32-bit +<a href="#_address_space">Address Space</a>.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Linear/In-Order Execution Only</div> +The CPU does not perform any speculative/out-of-order operations at all. Hence, it is not vulnerable to security issues +caused by speculative execution (like Spectre or Meltdown). +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_cpu_register_file">3.4.1. CPU Register File</h4> +<div class="paragraph"> +<p>The data register file contains the general purpose architecture registers <code>x0</code> to <code>x31</code>. For the <code>rv32e</code> ISA only the lower +16 registers are implemented. Register zero (<code>x0</code>/<code>zero</code>) always read as zero and any write access to it has no effect. +Up to four individual synchronous read ports allow to fetch up to 4 register operands at once. The write and read accesses +are mutually exclusive as they happen in separate cycles. Hence, there is no need to consider things like "read-during-write" +behavior.</p> +</div> +<div class="paragraph"> +<p>The register file provides two different implementation options configured via the top&#8217;s <code>REGFILE_HW_RST</code> generic.</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>REGFILE_HW_RST = false</code> (default): In this configuration the register file is implemented as plain memory array without a +dictated hardware reset. This architecture allows to infer FPGA block RAM for the entire register file resulting in minimal +general logic utilization.</p> +</li> +<li> +<p><code>REGFILE_HW_RST = true</code>: This configuration is based on individual FFs that do provide a dedicated hardware reset. +Hence, the register cannot be mapped to FPGA block RAM. This optional can be selected if the application requires a +reset of the register file (e.g. for security reasons) or if the design shall be synthesized for an <strong>ASIC</strong> implementation. +Using individual FFs for th register file might also improve timing as no long routing lines are required to connect to +block RAM primitives.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>The state of this configuration generic can be checked by software via the <a href="#_mxisa"><strong><code>mxisa</code></strong></a> CSR.</p> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">FPGA Implementation</div> +Enabling the <code>REGFILE_HW_RST</code> option for FPGA implementation is not recommended as this will massively increase the amount +of required logic resources. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Implementation of the <code>zero</code> Register within FPGA Block RAM</div> +Register <code>zero</code> is also mapped to a <em>physical memory location</em> within the register file&#8217;s block RAM. By this, there is no need +to add a further multiplexer to "insert" zero if reading from register <code>zero</code> reducing logic requirements and shortening the +critical path. However, this also requires that the physical storage bits of register <code>zero</code> are explicitly initialized (set +to zero) by the hardware. This is done transparently by the CPU control requiring no additional processing overhead. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Block RAM Ports</div> +The default register file configuration uses two access ports: a read-only port for reading register <code>rs2</code> (second source operand) +and a read/write port for reading register <code>rs1</code> (first source operand) and for writing processing results to register <code>rd</code> +(destination register). Hence, a simple dual-port RAM can be used to implement the entire register file. From a functional point +of view, read and write accesses to the register file do never occur in the same clock cycle, so no bypass logic is required at all. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_cpu_arithmetic_logic_unit">3.4.2. CPU Arithmetic Logic Unit</h4> +<div class="paragraph"> +<p>The arithmetic/logic unit (ALU) is used for actual data processing as well as generating memory and branch addresses. +All "simple" <a href="#_i_isa_extension"><code>I</code> ISA Extension</a> computational instructions (like <code>add</code> and <code>or</code>) are implemented as plain combinatorial logic +requiring only a single cycle to complete. More sophisticated instructions like shift operations or multiplications are processed +by so-called "ALU co-processors".</p> +</div> +<div class="paragraph"> +<p>The co-processors are implemented as iterative units that require several cycles to complete processing. Besides the base ISA&#8217;s +shift instructions, the co-processors are used to implement all further processing-based ISA extensions (e.g. <a href="#_m_isa_extension"><code>M</code> ISA Extension</a> +and <a href="#_b_isa_extension"><code>B</code> ISA Extension</a>).</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Multi-Cycle Execution Monitor</div> +The CPU control will raise an illegal instruction exception if a multi-cycle functional unit (like the <a href="#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a>) +does not complete processing in a bound amount of time (configured via the package&#8217;s <code>monitor_mc_tmo_c</code> constant; default = 512 clock cycles). +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Tuning Options</div> +The ALU architecture can be tuned for an application-specific area-vs-performance trade-off. The <code>FAST_MUL_EN</code> and <code>FAST_SHIFT_EN</code> +generics can be used to implement performance-optimized barrel shifters and DSP blocks, respectively. See sections <a href="#_i_isa_extension"><code>I</code> ISA Extension</a>, +<a href="#_b_isa_extension"><code>B</code> ISA Extension</a> and <a href="#_m_isa_extension"><code>M</code> ISA Extension</a> for specific examples. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_cpu_bus_unit">3.4.3. CPU Bus Unit</h4> +<div class="paragraph"> +<p>The bus unit takes care of handling data memory accesses via load and store instructions. It handles data adjustment when accessing +sub-word data quantities (16-bit or 8-bit) and performs sign-extension for singed load operations. The bus unit also includes the optional +<a href="#_smpmp_isa_extension"><code>Smpmp</code> ISA Extension</a> that performs permission checks for all data and instruction accesses.</p> +</div> +<div class="paragraph"> +<p>A list of the bus interface signals and a detailed description of the protocol can be found in section <a href="#_bus_interface">Bus Interface</a>. +All bus interface signals are driven/buffered by registers; so even a complex SoC interconnection bus network will not +effect maximal operation frequency.</p> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Unaligned Accesses</div> +The CPU does not support a hardware-based handling of unaligned memory accesses! Any unaligned access will raise a bus load/store unaligned +address exception. The exception handler can be used to <em>emulate</em> unaligned memory accesses in software. +See the NEORV32 Runtime Environment&#8217;s <a href="#_application_context_handling">Application Context Handling</a> section for more information. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_cpu_control_unit">3.4.4. CPU Control Unit</h4> +<div class="paragraph"> +<p>The CPU control unit is responsible for generating all the control signals for the different CPU modules. +The control unit is split into a "front-end" and a "back-end".</p> +</div> +<div class="paragraph"> +<p><strong>Front-End</strong></p> +</div> +<div class="paragraph"> +<p>The front-end is responsible for fetching instructions in chunks of 32-bits. This can be a single aligned 32-bit instruction, +two aligned 16-bit instructions or a mixture of those. The instructions including control and exception information are stored +to a FIFO queue - the instruction prefetch buffer (IPB). This FIFO has a depth of two entries by default but can be customized +via the <code>ipb_depth_c</code> VHDL package constant.</p> +</div> +<div class="paragraph"> +<p>The FIFO allows the front-end to do "speculative" instruction fetches, as it keeps fetching the next consecutive instruction +all the time. This also allows to decouple front-end (instruction fetch) and back-end (instruction execution) so both modules +can operate in parallel to increase performance. However, all potential side effects that are caused by this "speculative" +instruction fetch are already handled by the CPU front-end ensuring a defined execution stage while preventing security +side attacks.</p> +</div> +<div class="paragraph"> +<p><strong>Back-End</strong></p> +</div> +<div class="paragraph"> +<p>Instruction data from the instruction prefetch buffer is decompressed (if the <code>C</code> ISA extension is enabled) and sent to the +CPU back-end for actual execution. Execution is conducted by a state-machine that controls all of the CPU modules. The back-end also +includes the <a href="#_control_and_status_registers_csrs">Control and Status Registers (CSRs)</a> as well as the trap controller.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_sleep_mode">3.4.5. Sleep Mode</h4> +<div class="paragraph"> +<p>The NEORV32 CPU provides a single sleep mode that can be entered to power-down the core reducing +dynamic power consumption. Sleep mode is entered by executing the <code>wfi</code> ("wait for interrupt") instruction.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Execution Details</div> +The <code>wfi</code> instruction will raise an illegal instruction exception when executed in user-mode +if <code>TW</code> in <a href="#_mstatus"><strong><code>mstatus</code></strong></a> is set. When executed in debug-mode or during single-stepping <code>wfi</code> will behave as +simple <code>nop</code> without entering sleep mode. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>After executing the <code>wfi</code> instruction the CPU&#8217;s <code>sleep_o</code> signal (<a href="#_cpu_top_entity_signals">CPU Top Entity - Signals</a>) will become set +as soon as the CPU has fully halted ("CPU is sleeping"):</p> +</div> +<div class="paragraph"> +<div class="title">There is no enabled interrupt being pending.</div> +<p>CPU-external modules like memories, timers and peripheral interfaces are not affected by this. Furthermore, the CPU will +continue to buffer/enqueue incoming interrupt. The CPU will leave sleep mode as soon as any <em>enabled</em> interrupt (via <a href="#_mie"><strong><code>mie</code></strong></a>) +source becomes <em>pending</em> or if a debug session is started.</p> +</div> +<div class="sect4"> +<h5 id="_power_down_mode">Power-Down Mode</h5> +<div class="paragraph"> +<p>Optionally, the sleep mode can also be used to shut down the CPU&#8217;s main clock to further reduce power consumption +by halting the core&#8217;s clock tree. This clock gating mode is enabled by the <code>CLOCK_GATING_EN</code> generic +(<a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a>). See section <a href="#_processor_clocking">Processor Clocking</a> for more information.</p> +</div> +</div> +</div> +<div class="sect3"> +<h4 id="_full_virtualization">3.4.6. Full Virtualization</h4> +<div class="paragraph"> +<p>Just like the RISC-V ISA, the NEORV32 aims to provide <em>maximum virtualization</em> capabilities on CPU and SoC level to +allow a high standard of <strong>execution safety</strong>. The CPU supports <strong>all</strong> traps specified by the official RISC-V +specifications. Thus, the CPU provides defined hardware fall-backs via traps for any expected and unexpected situations +(e.g. executing a malformed or not supported instruction or accessing a non-allocated memory address). For any kind +of trap the core is always in a defined and fully synchronized state throughout the whole system (i.e. there are no +out-of-order operations that might have to be reverted). This allows a defined and predictable execution behavior +at any time improving overall execution safety.</p> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_bus_interface">3.5. Bus Interface</h3> +<div class="paragraph"> +<p>The NEORV32 CPU provides separated instruction fetch and data access interfaces making it a <strong>Harvard Architecture</strong>: +the instruction fetch interface (<code>i_bus_*</code> signals) is used for fetching instructions and the data access interface +(<code>d_bus_*</code> signals) is used to access data via load and store operations. Each of these interfaces can access an address +space of up to 2<sup>32</sup> bytes (4GB).</p> +</div> +<div class="paragraph"> +<p>The bus interface uses two custom interface types: <code>bus_req_t</code> is used to propagate the bus access <strong>requests</strong>. These +signals are driven by the <em>accessing</em> device (i.e. the CPU core). <code>bus_rsp_t</code> is used to return the bus <strong>response</strong> and +is driven by the <em>accessed</em> device or bus system (i.e. a processor-internal memory or IO device).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 44. Bus Interface - Request Bus (<code>bus_req_t</code>)</caption> +<colgroup> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +<col style="width: 75%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Signal</th> +<th class="tableblock halign-center valign-top">Width</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>addr</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access address (byte addressing)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>data</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Write data</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>ben</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Byte-enable for each byte in <code>data</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>stb</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Request trigger ("strobe", single-shot)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>rw</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access direction (<code>0</code> = read, <code>1</code> = write)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>src</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Access source (<code>0</code> = instruction fetch, <code>1</code> = load/store)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>priv</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set if privileged (M-mode) access</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>rvso</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set if current access is a reservation-set operation (<code>lr</code> or <code>sc</code> instruction, <a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>fence</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Data/instruction fence operation; valid without <code>stb</code> being set</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 45. Bus Interface - Response Bus (<code>bus_rsp_t</code>)</caption> +<colgroup> +<col style="width: 12.5%;"> +<col style="width: 12.5%;"> +<col style="width: 75%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Signal</th> +<th class="tableblock halign-center valign-top">Width</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>data</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Read data (single-shot)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>ack</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Transfer acknowledge / success (single-shot)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>err</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Transfer error / fail (single-shot)</p></td> +</tr> +</tbody> +</table> +<div class="sect3"> +<h4 id="_bus_interface_protocol">3.5.1. Bus Interface Protocol</h4> +<div class="paragraph"> +<p>Transactions are triggered entirely by the request bus. A new bus request is initiated by setting the <em>strobe</em> +signal <code>stb</code> high for exactly one cycle. All remaining signals of the bus are set together with <code>stb</code> and will +remain unchanged until the transaction is completed.</p> +</div> +<div class="paragraph"> +<p>The transaction is completed when the accessed device returns a response via the response interface: +<code>ack</code> is high for exactly one cycle if the transaction was completed successfully. <code>err</code> is high for exactly +one cycle if the transaction failed to complete. These two signals are mutually exclusive. In case of a read +access the read data is returned together with the <code>ack</code> signal. Otherwise, the return data signal is +kept at all-zero allowing wired-or interconnection of all response buses.</p> +</div> +<div class="paragraph"> +<p>The figure below shows three exemplary bus accesses:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>A read access to address <code>A_addr</code> returning <code>rdata</code> after several cycles (slow response; <code>ACK</code> arrives after several cycles).</p> +</li> +<li> +<p>A write access to address <code>B_addr</code> writing <code>wdata</code> (fastest response; <code>ACK</code> arrives right in the next cycle).</p> +</li> +<li> +<p>A failing read access to address <code>C_addr</code> (slow response; <code>ERR</code> arrives after several cycles).</p> +</li> +</ol> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/bus_interface.png" alt="700"> +</div> +<div class="title">Figure 9. Three Exemplary Bus Transactions</div> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Adding Register Stages</div> +Arbitrary pipeline stages can be added to the request and response buses at any point to relax timing (at the cost of +additional latency). However, <em>all</em> bus signals (request and response) need to be registered. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_atomic_accesses">3.5.2. Atomic Accesses</h4> +<div class="paragraph"> +<p>The load-reservate (<code>lr.w</code>) and store-conditional (<code>sc.w</code>) instructions from the <a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a> execute as standard +load/store bus transactions but with the <code>rvso</code> ("reservation set operation") signal being set. It is the task of the +<a href="#_reservation_set_controller">Reservation Set Controller</a> to handle these LR/SC bus transactions accordingly. Note that these reservation set operations +are intended for processor-internal usage only (i.e. the reservation state is not available for processor-external modules yet).</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Reservation Set Controller</div> +See section <a href="#_address_space">Address Space</a> / <a href="#_reservation_set_controller">Reservation Set Controller</a> for more information. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The figure below shows three exemplary bus accesses (1 to 3 from left to right). The <code>req</code> signal record represents +the CPU-side of the bus interface. For easier understanding the current state of the reservation set is added as <code>rvs_valid</code> signal.</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>A load-reservate (LR) instruction using <code>addr</code> as address. This instruction returns the loaded data <code>rdata</code> via <code>rsp.data</code> +and also registers a reservation for the address <code>addr</code> (<code>rvs_valid</code> becomes set).</p> +</li> +<li> +<p>A store-conditional (SC) instruction attempts to write <code>wdata1</code> to address <code>addr</code>. This SC operation <strong>succeeds</strong>, so +<code>wdata1</code> is actually written to address <code>addr</code>. The successful operation is indicated by a <strong>0</strong> being returned via +<code>rsp.data</code> together with <code>ack</code>. As the LR/SC is completed the registered reservation is invalidated (<code>rvs_valid</code> becomes cleared).</p> +</li> +<li> +<p>Another store-conditional (SC) instruction attempts to write <code>wdata2</code> to address <code>addr</code>. As the reservation set is already +invalidated (<code>rvs_valid</code> is <code>0</code>) the store access fails, so <code>wdata2</code> is <strong>not</strong> written to address <code>addr</code> at all. The failed +operation is indicated by a <strong>1</strong> being returned via <code>rsp.data</code> together with <code>ack</code>.</p> +</li> +</ol> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/bus_interface_atomic.png" alt="700"> +</div> +<div class="title">Figure 10. Three Exemplary LR/SC Bus Transactions</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Store-Conditional Status</div> +The "normal" load data mechanism is used to return success/failure of the <code>sc.w</code> instruction to the CPU (via the LSB of <code>rsp.data</code>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Cache Coherency</div> +Atomic operations <strong>always bypass</strong> the CPU caches using direct/uncached accesses. Care must be taken +to maintain data cache coherency (e.g. by using the <code>fence</code> instruction). +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_instruction_sets_and_extensions">3.6. Instruction Sets and Extensions</h3> +<div class="paragraph"> +<p>The NEORV32 CPU provides several optional RISC-V-compliant and custom/user-defined ISA extensions. +The extensions can be enabled/configured via the according <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a>. +This chapter gives a brief overview of all available ISA extensions.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 46. NEORV32 Instruction Set Extensions</caption> +<colgroup> +<col style="width: 20%;"> +<col style="width: 50%;"> +<col style="width: 30%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Name</th> +<th class="tableblock halign-left valign-top">Description</th> +<th class="tableblock halign-left valign-top"><a href="#_processor_top_entity_generics">Enabled by Generic</a></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_b_isa_extension"><code>B</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Bit manipulation instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>Implicitly</em> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_c_isa_extension"><code>C</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Compressed (16-bit) instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_C</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_e_isa_extension"><code>E</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Embedded CPU extension (reduced register file size)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_E</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_i_isa_extension"><code>I</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Integer base ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enabled if <code>RISCV_ISA_E</code> is <strong>not</strong> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_m_isa_extension"><code>M</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Integer multiplication and division instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_M</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_u_isa_extension"><code>U</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Less-privileged <em>user</em> mode extension</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_U</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_x_isa_extension"><code>X</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Platform-specific / NEORV32-specific extension</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Always enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zalrsc_isa_extension"><code>Zalrsc</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Atomic reservation-set instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zalrsc</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zba_isa_extension"><code>Zba</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Shifted-add bit manipulation instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zba</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbb_isa_extension"><code>Zbb</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Basic bit manipulation instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbb</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbkb_isa_extension"><code>Zbkb</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic bit manipulation instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbkb</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbkc_isa_extension"><code>Zbkc</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic carry-less multiplication instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbkc</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbkx_isa_extension"><code>Zbkx</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic crossbar permutation instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbkx</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbs_isa_extension"><code>Zbs</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Single-bit bit manipulation instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbs</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zfinx_isa_extension"><code>Zfinx</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Floating-point instructions using integer registers</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zfinx</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zifencei_isa_extension"><code>Zifencei</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction stream synchronization instruction</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Always enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zicntr_isa_extension"><code>Zicntr</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Base counters extension</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zicntr</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zicond_isa_extension"><code>Zicond</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Integer conditional operations</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zicond</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zicsr_isa_extension"><code>Zicsr</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Control and status register access instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Always enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zihpm_isa_extension"><code>Zihpm</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hardware performance monitors extension</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zihpm</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zkn_isa_extension"><code>Zkn</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic NIST algorithm suite</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>Implicitly</em> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zknd_isa_extension"><code>Zknd</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic NIST AES decryption instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zknd</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zkne_isa_extension"><code>Zkne</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic NIST AES encryption instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zkne</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zknh_isa_extension"><code>Zknh</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic NIST hash function instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zknh</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zkt_isa_extension"><code>Zkt</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Data independent execution time (of cryptographic operations)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>Implicitly</em> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zks_isa_extension"><code>Zks</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic ShangMi algorithm suite</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>Implicitly</em> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zksed_isa_extension"><code>Zksed</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic ShangMi block cypher instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zksed</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zksh_isa_extension"><code>Zksh</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scalar cryptographic ShangMi hash instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zksh</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zmmul_isa_extension"><code>Zmmul</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Integer multiplication-only instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zmmul</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zxcfu_isa_extension"><code>Zcfu</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Custom / user-defined instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zxcfu</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_smpmp_isa_extension"><code>Smpmp</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Physical memory protection (PMP) extension</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>RISCV_ISA_Smpmp</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_sdext_isa_extension"><code>Sdext</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">External debug support extension</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>ON_CHIP_DEBUGGER_EN</code></a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_sdtrig_isa_extension"><code>Sdtrig</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger module extension</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_processor_top_entity_generics"><code>ON_CHIP_DEBUGGER_EN</code></a></p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">RISC-V ISA Specification</div> +For more information regarding the RISC-V ISA extensions please refer to the "RISC-V Instruction Set Manual - Volume +I: Unprivileged ISA" and "The RISC-V Instruction Set Manual Volume II: Privileged Architecture". A copy of these +documents can be found in the projects <code>docs/references</code> folder. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Discovering ISA Extensions</div> +Software can discover available ISA extensions via the <a href="#_misa"><strong><code>misa</code></strong></a> and <a href="#_mxisa"><strong><code>mxisa</code></strong></a> CSRs or by executing an instruction +and checking for an illegal instruction exception (i.e. <a href="#_full_virtualization">Full Virtualization</a>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Instruction Cycles</div> +This chapter shows the CPI values (cycles per instruction) for each individual instruction/type. Note that +values reflect <em>optimal conditions</em> (i.e. no additional memory delay, no cache misses, no pipeline waits, etc.). +To benchmark a certain processor configuration for its setup-specific CPI value please refer to the +<code>sw/example/performance_tests</code> test programs. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_b_isa_extension">3.6.1. <code>B</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>B</code> ISA extension adds instructions for bit-manipulation operations. +This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of +bit-manipulation sub-extensions are enabled.</p> +</div> +<div class="paragraph"> +<p>The <code>B</code> extension is shorthand for the following set of other extensions:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_zba_isa_extension"><code>Zba</code> ISA Extension</a> - Address-generation / shifted-add instructions.</p> +</li> +<li> +<p><a href="#_zbb_isa_extension"><code>Zbb</code> ISA Extension</a> - Basic bit manipulation instructions.</p> +</li> +<li> +<p><a href="#_zbs_isa_extension"><code>Zbs</code> ISA Extension</a> - Single-bit operations.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>A processor configuration which implements <code>B</code> must implement all of the above extensions.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_c_isa_extension">3.6.2. <code>C</code> ISA Extension</h4> +<div class="paragraph"> +<p>The "compressed" ISA extension provides 16-bit encodings of commonly used instructions to reduce code space size.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 47. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ALU</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>c.addi4spn</code> <code>c.nop</code> <code>c.add[i]</code> <code>c.li</code> <code>c.addi16sp</code> <code>c.lui</code> <code>c.and[i]</code> <code>c.sub</code> <code>c.xor</code> <code>c.or</code> <code>c.mv</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">2</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ALU</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>c.srli</code> <code>c.srai</code> <code>c.slli</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3 + 1..32; FAST_SHIFT: 4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Branches</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>c.beqz</code> <code>c.bnez</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">taken: 6; not taken: 3</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Jumps / calls</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>c.jal[r]</code> <code>c.j</code> <code>c.jr</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Memory access</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>c.lw</code> <code>c.sw</code> <code>c.lwsp</code> <code>c.swsp</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">System</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>c.break</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_e_isa_extension">3.6.3. <code>E</code> ISA Extension</h4> +<div class="paragraph"> +<p>The "embedded" ISA extensions reduces the size of the general purpose register file from 32 entries to 16 entries to +shrink hardware size. It provides the same instructions as the the base <code>I</code> ISA extensions.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Alternative MABI</div> +Due to the reduced register file size an alternate toolchain ABI (<code>ilp32e*</code>) is required. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_i_isa_extension">3.6.4. <code>I</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>I</code> ISA extensions is the base RISC-V integer ISA that is always enabled.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 48. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ALU</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>add[i]</code> <code>slt[i]</code> <code>slt[i]u</code> <code>xor[i]</code> <code>or[i]</code> <code>and[i]</code> <code>sub</code> <code>lui</code> <code>auipc</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">2</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ALU shifts</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sll[i]</code> <code>srl[i]</code> <code>sra[i]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3 + 1..32; FAST_SHIFT: 4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Branches</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>beq</code> <code>bne</code> <code>blt</code> <code>bge</code> <code>bltu</code> <code>bgeu</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">taken: 6; not taken: 3</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Jump/call</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>jal[r]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Load/store</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>lb</code> <code>lh</code> <code>lw</code> <code>lbu</code> <code>lhu</code> <code>sb</code> <code>sh</code> <code>sw</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">System</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ecall</code> <code>ebreak</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Data fence</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>fence</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">System</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>wfi</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">System</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mret</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Illegal inst.</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title"><code>fence</code> Instruction</div> +The <code>fence</code> instruction word&#8217;s <em>predecessor</em> and <em>successor</em> bits (used for memory ordering) are not evaluated +by the hardware at all. For the NEORV32 the <code>fence</code> instruction behaves exactly like the <code>fence.i</code> instruction +(see <a href="#_zifencei_isa_extension"><code>Zifencei</code> ISA Extension</a>). However, software should still use distinct <code>fence</code> and <code>fence.i</code> to provide +platform-compatibility and to indicate the actual intention of the according fence instruction(s). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title"><code>wfi</code> Instruction</div> +The <code>wfi</code> instruction is used to enter <a href="#_sleep_mode">Sleep Mode</a>. Executing the <code>wfi</code> instruction in user-mode +will raise an illegal instruction exception if the <code>TW</code> bit of <a href="#_mstatus"><strong><code>mstatus</code></strong></a> is set. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Barrel Shifter</div> +The shift operations are implemented as multi-cycle ALU co-process (<code>rtl/core/neorv32_cpu_cp_shifter.vhd</code>). +These operations can be accelerated (at the cost of additional logic resources) by enabling the <code>FAST_SHIFT_EN</code> +configuration option that will replace the (time-variant) bit-serial shifter by a (time-constant) barrel shifter. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_m_isa_extension">3.6.5. <code>M</code> ISA Extension</h4> +<div class="paragraph"> +<p>Hardware-accelerated integer multiplication and division operations are available via the RISC-V <code>M</code> ISA extension. +This ISA extension is implemented as multi-cycle ALU co-process (<code>rtl/core/neorv32_cpu_cp_muldiv.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 49. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Multiplication</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mul</code> <code>mulh</code> <code>mulhsu</code> <code>mulhu</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">36; FAST_MUL: 4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Division</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>div</code> <code>divu</code> <code>rem</code> <code>remu</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">36</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">DSP Blocks</div> +Multiplication operations can be accelerated (at the cost of additional logic resources) by enabling the <code>FAST_MUL_EN</code> +configuration option that will replace the (time-variant) bit-serial multiplier by (time-constant) FPGA DSP blocks. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_u_isa_extension">3.6.6. <code>U</code> ISA Extension</h4> +<div class="paragraph"> +<p>In addition to the highest-privileged machine-mode, the user-mode ISA extensions adds a second <strong>less-privileged</strong> +operation mode. Code executed in user-mode has reduced CSR access rights. Furthermore, user-mode accesses to the address space +(like peripheral/IO devices) can be constrained via the physical memory protection. +Any kind of privilege rights violation will raise an exception to allow <a href="#_full_virtualization">Full Virtualization</a>.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_x_isa_extension">3.6.7. <code>X</code> ISA Extension</h4> +<div class="paragraph"> +<p>The NEORV32-specific ISA extensions <code>X</code> is always enabled. The most important points of the NEORV32-specific extensions are: +* The CPU provides 16 <em>fast interrupt</em> interrupts (<code>FIRQ</code>), which are controlled via custom bits in the <a href="#_mie"><strong><code>mie</code></strong></a> +and <a href="#_mip"><strong><code>mip</code></strong></a> CSRs. These extensions are mapped to CSR bits, that are available for custom use according to the +RISC-V specs. Also, custom trap codes for <a href="#_mcause"><strong><code>mcause</code></strong></a> are implemented. +* All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception (see <a href="#_full_virtualization">Full Virtualization</a>). +* There are <a href="#_neorv32_specific_csrs">NEORV32-Specific CSRs</a>.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_zalrsc_isa_extension">3.6.8. <code>Zalrsc</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zalrsc</code> ISA extension is a sub-extension of the RISC-V <em>atomic memory access</em> (<code>A</code>) ISA extension and includes +instructions for reservation-set operations (load-reservate <code>lr</code> and store-conditional <code>sc</code>) only. +It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zalrsc</code></a> generic.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">AMO / <code>A</code> Emulation</div> +The atomic memory access / read-modify-write operations of the <code>A</code> ISA extension can be emulated using the +LR and SC operations (quote from the RISC-V spec.: "<em>Any AMO can be emulated by an LR/SC pair.</em>"). +The NEORV32 <a href="#_core_libraries">Core Libraries</a> provide an emulation wrapper for emulating AMO/read-modify-write instructions that is +based on LR/SC pairs. A demo/program can be found in <code>sw/example/atomic_test</code>. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 50. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Load-reservate word</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>lr.w</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Store-conditional word</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sc.w</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title"><code>aq</code> and <code>rl</code> Bits</div> +The instruction word&#8217;s <code>aq</code> and <code>lr</code> memory ordering bits are not evaluated by the hardware at all. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Atomic Memory Access on Hardware Level</div> +More information regarding the atomic memory accesses and the according reservation +sets can be found in section <a href="#_reservation_set_controller">Reservation Set Controller</a>. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_zifencei_isa_extension">3.6.9. <code>Zifencei</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zifencei</code> CPU extension allows manual synchronization of the instruction stream. This extension is always enabled.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">NEORV32 Fence Instructions</div> +The NEORV32 treats both fence instructions (<code>fence</code> = data fence, <code>fence.i</code> = instruction fence) in exactly the same way. +Both instructions cause a flush of the CPU&#8217;s instruction prefetch buffer and also send a fence request via the system +bus (see <a href="#_bus_interface">Bus Interface</a>). This system bus fence operation will, for example, clear/flush all downstream caches. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 51. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction fence</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>fence.i</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zfinx_isa_extension">3.6.10. <code>Zfinx</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zfinx</code> floating-point extension is an <em>alternative</em> of the standard <code>F</code> floating-point ISA extension. +It also uses the integer register file <code>x</code> to store and operate on floating-point data +instead of a dedicated floating-point register file. Thus, the <code>Zfinx</code> extension requires +less hardware resources and features faster context changes. This also implies that there are NO dedicated <code>f</code> +register file-related load/store or move instructions. The <code>Zfinx</code> extension&#8217;S floating-point unit is controlled +via dedicated <a href="#_floating_point_csrs">Floating-Point CSRs</a>. +This ISA extension is implemented as multi-cycle ALU co-process (<code>rtl/core/neorv32_cpu_cp_fpu.vhd</code>).</p> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Fused / Multiply-Add Instructions</div> +Fused multiply-add instructions <code>f[n]m[add/sub].s</code> are not supported. A special GCC switch is used to prevent the +compiler from emitting contracted/fused floating-point operations (see <a href="#_default_compiler_flags">Default Compiler Flags</a>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Division and Squarer Root Instructions</div> +Division <code>fdiv.s</code> and square root <code>fsqrt.s</code> instructions are not supported yet. +</td> +</tr> +</table> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Subnormal Number</div> +Subnormal numbers ("de-normalized" numbers, i.e. exponent = 0) are not supported by the NEORV32 FPU. +Subnormal numbers are <em>flushed to zero</em> setting them to +/- 0 before being processed by <strong>any</strong> FPU operation. +If a computational instruction generates a subnormal result it is also flushed to zero during normalization. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 52. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Artihmetic</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>fadd.s</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">110</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Artihmetic</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>fsub.s</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">112</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Artihmetic</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>fmul.s</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">22</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Compare</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>fmin.s</code> <code>fmax.s</code> <code>feq.s</code> <code>flt.s</code> <code>fle.s</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">13</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Conversion</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>fcvt.w.s</code> <code>fcvt.wu.s</code> <code>fcvt.s.w</code> <code>fcvt.s.wu</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">48</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Misc</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>fsgnj.s</code> <code>fsgnjn.s</code> <code>fsgnjx.s</code> <code>fclass.s</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">12</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zicntr_isa_extension">3.6.11. <code>Zicntr</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zicntr</code> ISA extension adds the basic <a href="#_cycleh"><strong><code>cycle[h]</code></strong></a>, <a href="#_mcycleh"><strong><code>mcycle[h]</code></strong></a>, <a href="#_instreth"><strong><code>instret[h]</code></strong></a> and <a href="#_minstreth"><strong><code>minstret[h]</code></strong></a> +counter CSRs. Section <a href="#_machine_counter_and_timer_csrs">(Machine) Counter and Timer CSRs</a> shows a list of all <code>Zicntr</code>-related CSRs.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Time CSRs</div> +The user-mode <code>time[h]</code> CSRs are <strong>not implemented</strong>. Any access will trap allowing the trap handler to +retrieve system time from the <a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Mandatory Extension</div> +This extensions is stated as <em>mandatory</em> by the RISC-V spec. However, area-constrained setups may remove +support for these counters. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Constrained Access</div> +User-level access to the counter CSRs can be constrained by the <a href="#_mcounteren"><strong><code>mcounteren</code></strong></a> CSR. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_zicond_isa_extension">3.6.12. <code>Zicond</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zicond</code> ISA extension adds integer conditional move primitives that allow to implement branch-less +control flows. It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zicond</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_cond.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 53. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Conditional</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>czero.eqz</code> <code>czero.nez</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zicsr_isa_extension">3.6.13. <code>Zicsr</code> ISA Extension</h4> +<div class="paragraph"> +<p>This ISA extensions provides instructions for accessing the <a href="#_control_and_status_registers_csrs">Control and Status Registers (CSRs)</a> as well as further +privileged-architecture extensions. This extension is mandatory and cannot be disabled. Hence, there is no generic +for enabling/disabling this ISA extension.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Side-Effects if Destination is Zero-Register</div> +If <code>rd=x0</code> for the <code>csrrw[i]</code> instructions there will be no actual read access to the according CSR. +However, access privileges are still enforced so these instruction variants <em>do</em> cause side-effects +(the RISC-V spec. state that these combinations "shall" not cause any side-effects). +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 54. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">System</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>csrrw[i]</code> <code>csrrs[i]</code> <code>csrrc[i]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zihpm_isa_extension">3.6.14. <code>Zihpm</code> ISA Extension</h4> +<div class="paragraph"> +<p>In additions to the base counters the NEORV32 CPU provides up to 13 hardware performance monitors (HPM 3..15), +which can be used to benchmark applications. Each HPM consists of an N-bit wide counter (split in a high-word 32-bit +CSR and a low-word 32-bit CSR), where N is defined via the top&#8217;s <code>HPM_CNT_WIDTH</code> generic and a corresponding event +configuration CSR.</p> +</div> +<div class="paragraph"> +<p>The event configuration CSR defines the architectural events that lead to an increment of the associated HPM counter. +See section <a href="#_hardware_performance_monitors_hpm_csrs">Hardware Performance Monitors (HPM) CSRs</a> for a list of all HPM-related CSRs and event configurations.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Machine-Mode HPMs Only</div> +Note that only the machine-mode hardware performance counter CSR are available (<code>mhpmcounter*[h]</code>). +Accessing any user-mode HPM CSR (<code>hpmcounter*[h]</code>) will raise an illegal instruction exception. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Increment Inhibit</div> +The event-driven increment of the HPMs can be deactivated individually via the <a href="#_mcountinhibit"><strong><code>mcountinhibit</code></strong></a> CSR. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_zba_isa_extension">3.6.15. <code>Zba</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zba</code> sub-extension is part of the <em>RISC-V bit manipulation</em> ISA specification (<a href="#_b_isa_extension"><code>B</code> ISA Extension</a>) +and adds shifted-add / address-generation instructions. It is enabled by the top&#8217;s +<a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zba</code></a> generic. This ISA extension is implemented as multi-cycle +ALU co-processor (<code>rtl/core/neorv32_cpu_cp_bitmanip.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 55. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Shifted-add</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sh1add</code> <code>sh2add</code> <code>sh3add</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zbb_isa_extension">3.6.16. <code>Zbb</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zbb</code> sub-extension is part of the <em>RISC-V bit manipulation</em> ISA specification (<a href="#_b_isa_extension"><code>B</code> ISA Extension</a>) +and adds the basic bit manipulation instructions. It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbb</code></a> +generic. This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_bitmanip.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 56. Instructions and Timing</caption> +<colgroup> +<col style="width: 35.7142%;"> +<col style="width: 28.5714%;"> +<col style="width: 35.7144%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Logic with negate</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>andn</code> <code>orn</code> <code>xnor</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Count leading/trailing zeros</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>clz</code> <code>ctz</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6 + 1..32; FAST_SHIFT: 4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Count population</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>cpop</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6 + 32; FAST_SHIFT: 4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Integer maximum/minimum</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>min[u]</code> <code>max[u]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Sign/zero extension</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sext.b</code> <code>sext.h</code> <code>zext</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Bitwise rotation</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rol</code> <code>ror[i]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6 + <em>shift_amount</em>; FAST_SHIFT: 4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">OR-combine</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>orc.b</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Byte-reverse</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rev8</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Shift Operations</div> +Shift operations can be accelerated (at the cost of additional logic resources) by enabling the <code>FAST_SHIFT_EN</code> +configuration option that will replace the (time-variant) bit-serial shifter by a (time-constant) barrel shifter. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_zbs_isa_extension">3.6.17. <code>Zbs</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zbs</code> sub-extension is part of the <em>RISC-V bit manipulation</em> ISA specification (<a href="#_b_isa_extension"><code>B</code> ISA Extension</a>) +and adds single-bit operations. It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbs</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_bitmanip.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 57. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Single-bit</th> +<th class="tableblock halign-left valign-top"><code>sbset[i]</code> <code>sbclr[i]</code> <code>sbinv[i]</code> <code>sbext[i]</code></th> +<th class="tableblock halign-left valign-top">4</th> +</tr> +</thead> +</table> +</div> +<div class="sect3"> +<h4 id="_zbkb_isa_extension">3.6.18. <code>Zbkb</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zbkb</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and extends the <em>RISC-V bit manipulation</em> +ISA extension with additional instructions. It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbkb</code></a> generic. +Note that enabling this extension will also enable the <code>Zbb</code> basic bit-manipulation ISA extension (which is extended by <code>Zknb</code>). +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_bitmanip.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 58. Instructions and Timing (in addition to <code>Zbb</code>)</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Packing</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>pack</code> <code>packh</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Interleaving</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>zip</code> <code>unzip</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Byte-wise bit reversal</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>brev8</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zbkc_isa_extension">3.6.19. <code>Zbkc</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zbkc</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA extension and adds carry-less multiplication instruction. +ISA extension with additional instructions. It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbkc</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_bitmanip.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 59. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Carry-less multiply</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>clmul</code> <code>clmulh</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6 + 32</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zbkx_isa_extension">3.6.20. <code>Zbkx</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zbkx</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and adds crossbar permutation instructions. +It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zbkx</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_crypto.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 60. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Crossbar permutation</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xperm8</code> <code>xperm4</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zkn_isa_extension">3.6.21. <code>Zkn</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zkn</code> ISA extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and defines the "NIST algorithm suite". +This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of cryptography-related +sub-extensions is enabled.</p> +</div> +<div class="paragraph"> +<p>The <code>Zkn</code> extension is shorthand for the following set of other extensions:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_zbkb_isa_extension"><code>Zbkb</code> ISA Extension</a> - Bit manipulation instructions for cryptography.</p> +</li> +<li> +<p><a href="#_zbkc_isa_extension"><code>Zbkc</code> ISA Extension</a> - Carry-less multiply instructions.</p> +</li> +<li> +<p><a href="#_zbkx_isa_extension"><code>Zbkx</code> ISA Extension</a> - Cross-bar permutation instructions.</p> +</li> +<li> +<p><a href="#_zkne_isa_extension"><code>Zkne</code> ISA Extension</a> - AES encryption instructions.</p> +</li> +<li> +<p><a href="#_zknd_isa_extension"><code>Zknd</code> ISA Extension</a> - AES decryption instructions.</p> +</li> +<li> +<p><a href="#_zknh_isa_extension"><code>Zknh</code> ISA Extension</a> - SHA2 hash function instructions.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>A processor configuration which implements <code>Zkn</code> must implement all of the above extensions.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_zknd_isa_extension">3.6.22. <code>Zknd</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zknd</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and adds NIST AES decryption instructions. +It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zknd</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_crypto.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 61. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">AES decryption</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>aes32dsi</code> <code>aes32dsmi</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zkne_isa_extension">3.6.23. <code>Zkne</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zkne</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and adds NIST AES encryption instructions. +It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zkne</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_crypto.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 62. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">AES decryption</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>aes32esi</code> <code>aes32esmi</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zknh_isa_extension">3.6.24. <code>Zknh</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zknh</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and adds NIST hash function instructions. +It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zknh</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_crypto.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 63. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">sha256</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sha256sig0</code> <code>sha256sig1</code> <code>sha256sum0</code> <code>sha256sum1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">sha512</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sha512sig0h</code> <code>sha512sig0l</code> <code>sha512sig1h</code> <code>sha512sig1l</code> <code>sha512sum0r</code> <code>sha512sum1r</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zks_isa_extension">3.6.25. <code>Zks</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zks</code> ISA extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and defines the "ShangMi algorithm suite". +This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of cryptography-related +sub-extensions is enabled.</p> +</div> +<div class="paragraph"> +<p>The <code>Zks</code> extension is shorthand for the following set of other extensions:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_zbkb_isa_extension"><code>Zbkb</code> ISA Extension</a> - Bit manipulation instructions for cryptography.</p> +</li> +<li> +<p><a href="#_zbkc_isa_extension"><code>Zbkc</code> ISA Extension</a> - Carry-less multiply instructions.</p> +</li> +<li> +<p><a href="#_zbkx_isa_extension"><code>Zbkx</code> ISA Extension</a> - Cross-bar permutation instructions.</p> +</li> +<li> +<p><a href="#_zksed_isa_extension"><code>Zksed</code> ISA Extension</a> - SM4 block cipher instructions.</p> +</li> +<li> +<p><a href="#_zksh_isa_extension"><code>Zksh</code> ISA Extension</a> - SM3 hash function instructions.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>A processor configuration which implements <code>Zks</code> must implement all of the above extensions.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_zksed_isa_extension">3.6.26. <code>Zksed</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zksed</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and adds ShangMi block cypher +and key schedule instructions. It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zksed</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_crypto.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 64. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Block cyphers</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sm4ed</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Key schedule</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sm4ks</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zksh_isa_extension">3.6.27. <code>Zksh</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zksh</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and adds ShangMi hash function instructions. +It is enabled by the top&#8217;s <a href="#_processor_top_entity_generics"><code>RISCV_ISA_Zksh</code></a> generic. +This ISA extension is implemented as multi-cycle ALU co-processor (<code>rtl/core/neorv32_cpu_cp_crypto.vhd</code>).</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 65. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hash</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sm3p0</code> <code>sm3p1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zkt_isa_extension">3.6.28. <code>Zkt</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zkt</code> sub-extension is part of the <em>RISC-V scalar cryptography</em> ISA specification and guarantees data independent execution +times of cryptographic and cryptography-related instructions. The ISA extension cannot be enabled by a specific generic. +Instead, it is enabled implicitly by certain CPU configurations.</p> +</div> +<div class="paragraph"> +<p>The RISC-V <code>Zkt</code> specifications provides a list of instructions that are included within this specification. +However, not all instructions are required to be implemented. Rather, every one of these instructions that the +core does implement must adhere to the requirements of <code>Zkt</code>.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 66. <code>Zkt</code> instruction listing</caption> +<colgroup> +<col style="width: 10%;"> +<col style="width: 60%;"> +<col style="width: 30%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Parent extension</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Data independent execution time?</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>RVI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>lui</code> <code>auipc</code> <code>add[i]</code> <code>slt[i][u]</code> <code>xor[i]</code> <code>or[i]</code> <code>and[i]</code> <code>sub</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">yes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sll[i]</code> <code>srl[i]</code> <code>sra[i]</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">yes if <code>FAST_SHIFT_EN</code> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RVM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>mul[h]</code> <code>mulh[s]u</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">yes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>RVC</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>c.nop</code> <code>c.addi</code> <code>c.lui</code> <code>c.andi</code> <code>c.sub</code> <code>c.xor</code> <code>c.and</code> <code>c.mv</code> <code>c.add</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">yes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>c.srli</code> <code>c.srai</code> <code>c.slli</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">yes if <code>FAST_SHIFT_EN</code> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RVK</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>aes32ds[m]i</code> <code>aes32es[m]i</code> <code>sha256sig*</code> <code>sha512sig*</code> <code>sha512sum*</code> <code>sm3p0</code> <code>sm3p1</code> <code>sm4ed</code> <code>sm4ks</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">yes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>RVB</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xperm4</code> <code>xperm8</code> <code>andn</code> <code>orn</code> <code>xnor</code> <code>pack[h]</code> <code>brev8</code> <code>rev8</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">yes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ror[i]</code> <code>rol</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">yes if <code>FAST_SHIFT_EN</code> enabled</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_zmmul_isa_extension">3.6.29. <code>Zmmul</code> - ISA Extension</h4> +<div class="paragraph"> +<p>This is a sub-extension of the <a href="#_m_isa_extension"><code>M</code> ISA Extension</a> ISA extension. It implements only the multiplication operations +of the <code>M</code> extensions and is intended for size-constrained setups that require hardware-based +integer multiplications but not hardware-based divisions, which will be computed entirely in software. +Note that the <a href="#_zmmul_isa_extension"><code>Zmmul</code> - ISA Extension</a> and <a href="#_m_isa_extension"><code>M</code> ISA Extension</a> are mutually exclusive.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_zxcfu_isa_extension">3.6.30. <code>Zxcfu</code> ISA Extension</h4> +<div class="paragraph"> +<p>The <code>Zxcfu</code> presents a NEORV32-specific ISA extension. It adds the <a href="#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a> to +the CPU core, which allows to add custom RISC-V instructions to the processor core. +For detailed information regarding the CFU, its hardware and the according software interface +see section <a href="#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a>.</p> +</div> +<div class="paragraph"> +<p>Software can utilize the custom instructions by using <em>intrinsics</em>, which are basically inline assembly functions that +behave like regular C functions but that evaluate to a single custom instruction word (no calling overhead at all).</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">CFU Execution Time</div> +The actual CFU execution time depends on the logic being implemented. The CPU architecture requires a minimal execution +time of 3 cycles (purely combinatorial CFU operation) and automatically terminates execution after 512 cycles if the CFU +does not complete operation within this time window. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 67. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 55.5555%;"> +<col style="width: 22.2223%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Custom instructions</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction words with <code>custom-0</code> or <code>custom-1</code> opcode</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">3 &#8230;&#8203; 3+512</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_smpmp_isa_extension">3.6.31. <code>Smpmp</code> ISA Extension</h4> +<div class="paragraph"> +<p>The NEORV32 physical memory protection (PMP) provides an elementary memory +protection mechanism that can be used to constrain read, write and execute rights of arbitrary memory regions. +The NEORV32 PMP is fully compatible to the RISC-V Privileged Architecture Specifications. In general, the PMP can +<strong>grant permissions to user mode</strong>, which by default has none, and can <strong>revoke permissions from M-mode</strong>, which +by default has full permissions. The PMP is configured via the <a href="#_machine_physical_memory_protection_csrs">Machine Physical Memory Protection CSRs</a>.</p> +</div> +<div class="paragraph"> +<p>Several <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a> are provided to fine-tune the CPU&#8217;s PMP capabilities: +* <code>PMP_NUM_REGIONS</code> defines the number of implemented PMP region +* <code>PMP_MIN_GRANULARITY</code> defines the minimal granularity of each region +* <code>PMP_TOR_MODE_EN</code> controls the implementation of the top-of-region (TOR) mode +* <code>PMP_NAP_MODE_EN</code> controls the implementation of the naturally-aligned-power-of-two (NA4 and NAPOT) modes</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">PMP Rules when in Debug Mode</div> +When in debug-mode all PMP rules are ignored making the debugger have maximum access rights. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Protected Instruction Fetches</div> +New instruction fetches are <strong>always triggered even when denied</strong> by a certain PMP rule. However, the fetched instruction(s) +will not be executed and will not change CPU core state. Instead, they will raise a bus exception when reaching the CPU&#8217;s +executions stage. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_sdext_isa_extension">3.6.32. <code>Sdext</code> ISA Extension</h4> +<div class="paragraph"> +<p>This ISA extension enables the RISC-V-compatible "external debug support" by implementing +the CPU "debug mode", which is required for the on-chip debugger. +See section <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a> / <a href="#_cpu_debug_mode">CPU Debug Mode</a> for more information.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 68. Instructions and Timing</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 44.4444%;"> +<col style="width: 33.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Class</th> +<th class="tableblock halign-left valign-top">Instructions</th> +<th class="tableblock halign-left valign-top">Execution cycles</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">System</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>dret</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_sdtrig_isa_extension">3.6.33. <code>Sdtrig</code> ISA Extension</h4> +<div class="paragraph"> +<p>This ISA extension implements the RISC-V-compatible "trigger module". +See section <a href="#_on_chip_debugger_ocd">On-Chip Debugger (OCD)</a> / <a href="#_trigger_module">Trigger Module</a> for more information.</p> +</div> +<div style="page-break-after: always;"></div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_custom_functions_unit_cfu">3.7. Custom Functions Unit (CFU)</h3> +<div class="paragraph"> +<p>The Custom Functions Unit (CFU) is the central part of the NEORV32-specific <a href="#_zxcfu_isa_extension"><code>Zxcfu</code> ISA Extension</a> and +represents the actual hardware module that can be used to implement <strong>custom RISC-V instructions</strong>.</p> +</div> +<div class="paragraph"> +<p>The CFU is intended for operations that are inefficient in terms of performance, latency, energy consumption or +program memory requirements when implemented entirely in software. Some potential application fields and exemplary +use-cases might include:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><strong>AI:</strong> sub-word / vertical vector/SIMD operations like processing all four sub-bytes of a 32-bit data word individually</p> +</li> +<li> +<p><strong>Cryptographic:</strong> bit substitution and permutation</p> +</li> +<li> +<p><strong>Communication:</strong> data conversions like binary to gray-code</p> +</li> +<li> +<p><strong>Arithmetic:</strong> BCD (binary-coded decimal) operations; multiply-add operations; shift-and-add algorithms like CORDIC or BKM</p> +</li> +<li> +<p><strong>Image processing:</strong> look-up-tables for color space transformations</p> +</li> +<li> +<p>implementing instructions from <strong>other RISC-V ISA extensions</strong> that are not yet supported by NEORV32</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>The NEORV32 CFU supports two different instruction formats (R3-type and R4-type; see <a href="#_cfu_instruction_formats">CFU Instruction Formats</a>) and also +allows to implement up to 4 CFU-internal custom control and status registers (see <a href="#_cfu_control_and_status_registers_cfu_csrs">CFU Control and Status Registers (CFU-CSRs)</a>).</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">CFU Complexity</div> +The CFU is not intended for complex and <strong>CPU-independent</strong> functional units that implement complete accelerators +(like block-based AES encryption). These kind of accelerators should be implemented as memory-mapped co-processor via the +<a href="#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a> to allow CPU-independent operation. A comparative survey of all NEORV32-specific +hardware extension/customization options is provided in the user guide section +<a href="https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules">Adding Custom Hardware Modules</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Default CFU Hardware Example</div> +The default CFU module (<code>rtl/core/neorv32_cpu_cp_cfu.vhd</code>) implements the <em>Extended Tiny Encryption Algorithm (XTEA)</em> +as "real world" application example. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_cfu_instruction_formats">3.7.1. CFU Instruction Formats</h4> +<div class="paragraph"> +<p>The custom instructions executed by the CFU utilize a specific opcode space in the <code>rv32</code> 32-bit instruction +encoding space that has been explicitly reserved for user-defined extensions by the RISC-V specifications ("Guaranteed +Non-Standard Encoding Space"). The NEORV32 CFU uses the <code>custom-0</code> and <code>custom-1</code> opcodes to identify the instruction +implemented by the CFU and to differentiate between the predefined instruction formats.</p> +</div> +<div class="paragraph"> +<p>The NEORV32 CFU utilizes these two opcodes to support user-defined <strong>R3-type</strong> instructions (2 source registers, +1 destination register) and <strong>R4-type</strong> instructions (3 source registers, 1 destination register). Both instruction +formats are compliant to the RISC-V specification.</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>custom-0</code>: <code>0001011</code> RISC-V standard, used for NEORV32 <a href="#_cfu_r3_type_instructions">CFU R3-Type Instructions</a> (3x register addresses)</p> +</li> +<li> +<p><code>custom-1</code>: <code>0101011</code> RISC-V standard, used for NEORV32 <a href="#_cfu_r4_type_instructions">CFU R4-Type Instructions</a> (4x register addresses)</p> +</li> +</ul> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +The provided instructions formats are <em>predefined</em> to allow an easy integration framework. +However, system designers are free to ignore these and use their own instruction types and formats. +</td> +</tr> +</table> +</div> +<div class="sect4"> +<h5 id="_cfu_r3_type_instructions">CFU R3-Type Instructions</h5> +<div class="paragraph"> +<p>The R3-type CFU instructions operate on two source registers <code>rs1</code> and <code>rs2</code> and return the processing result to +the destination register <code>rd</code>. The actual operation can be defined by using the <code>funct7</code> and <code>funct3</code> bit fields. +These immediates can also be used to pass additional data to the CFU like offsets, look-up-tables addresses or +shift-amounts. However, the actual functionality is entirely user-defined. Note that all immediate values are +always compile-time-static.</p> +</div> +<div class="paragraph"> +<p>Example operation: <code>rd &#8656; rs1 xnor rs2</code> (bit-wise logical XNOR)</p> +</div> +<div class="imageblock text-left"> +<div class="content"> +<img src="img/cfu_r3type_instruction.png" alt="cfu r3type instruction"> +</div> +<div class="title">Figure 11. CFU R3-type instruction format</div> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>funct7</code>: 7-bit immediate (immediate data or function select)</p> +</li> +<li> +<p><code>rs2</code>: address of second source register (providing 32-bit source data)</p> +</li> +<li> +<p><code>rs1</code>: address of first source register (providing 32-bit source data)</p> +</li> +<li> +<p><code>funct3</code>: 3-bit immediate (immediate data or function select)</p> +</li> +<li> +<p><code>rd</code>: address of destination register (32-bit processing result)</p> +</li> +<li> +<p><code>opcode</code>: <code>0001011</code> (RISC-V <code>custom-0</code> opcode)</p> +</li> +</ul> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Instruction encoding space</div> +By using the <code>funct7</code> and <code>funct3</code> bit fields entirely for selecting the actual operation a total of 1024 custom +R3-type instructions can be implemented (7-bit + 3-bit = 10 bit &#8594; 1024 different values). +</td> +</tr> +</table> +</div> +</div> +<div class="sect4"> +<h5 id="_cfu_r4_type_instructions">CFU R4-Type Instructions</h5> +<div class="paragraph"> +<p>The R4-type CFU instructions operate on three source registers <code>rs1</code>, <code>rs2</code> and <code>rs2</code> and return the processing +result to the destination register <code>rd</code>. The actual operation can be defined by using the <code>funct3</code> bit field. +Alternatively, this immediate can also be used to pass additional data to the CFU like offsets, look-up-tables +addresses or shift-amounts. However, the actual functionality is entirely user-defined. Note that all immediate +values are always compile-time-static.</p> +</div> +<div class="paragraph"> +<p>Example operation: <code>rd &#8656; (rs1 * rs2 + rs3)[31:0]</code> (multiply-and-accumulate; "MAC")</p> +</div> +<div class="imageblock text-left"> +<div class="content"> +<img src="img/cfu_r4type_instruction.png" alt="cfu r4type instruction"> +</div> +<div class="title">Figure 12. CFU R4-type instruction format</div> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>rs3</code>: address of third source register (providing 32-bit source data)</p> +</li> +<li> +<p><code>rs2</code>: address of second source register (providing 32-bit source data)</p> +</li> +<li> +<p><code>rs1</code>: address of first source register (providing 32-bit source data)</p> +</li> +<li> +<p><code>funct3</code>: 3-bit immediate (immediate data or function select)</p> +</li> +<li> +<p><code>rd</code>: address of destination register (32-bit processing result)</p> +</li> +<li> +<p><code>opcode</code>: <code>0101011</code> (RISC-V <code>custom-1</code> opcode)</p> +</li> +<li> +<p>โš ๏ธ bits [26:25] of the R4-type instruction word are unused. However, these bits are ignored +by CPU&#8217;s instruction decoder and can be retrieved via the CFU&#8217;s <code>funct7_i(6 downto 5)</code> signal.</p> +</li> +</ul> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Instruction encoding space</div> +By using the <code>funct3</code> bit field entirely for selecting the actual operation a total of 8 custom R4-type +instructions can be implemented (3-bit &#8594; 8 different values). +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Re-purposing R4-type instructions as additional R3-type instructions</div> +Advanced user can use the custom-1 opcode to implement additional R3-type instructions instead of the +predefined r4-type instructions. +</td> +</tr> +</table> +</div> +</div> +</div> +<div class="sect3"> +<h4 id="_using_custom_instructions_in_software">3.7.2. Using Custom Instructions in Software</h4> +<div class="paragraph"> +<p>The custom instructions provided by the CFU can be used in plain C code by using <strong>intrinsics</strong>. Intrinsics +behave like "normal" C functions but under the hood they are a set of macros that hide the complexity of inline +assembly, which is used to construct the custom 32-bit instruction words. Using intrinsics removes the need to +modify the compiler, built-in libraries or the assembler when using custom instructions. Each intrinsic will be +compiled into a single 32-bit instruction word without any overhead providing maximum code efficiency.</p> +</div> +<div class="paragraph"> +<p>The NEORV32 software framework provides two pre-defined prototypes for custom instructions, which are defined in +<code>sw/lib/include/neorv32_cpu_cfu.h</code>:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 11. CFU instruction prototypes</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">uint32_t neorv32_cfu_r3_instr(funct7, funct3, rs1, rs2); // R3-type instructions +uint32_t neorv32_cfu_r4_instr(funct3, rs1, rs2, rs3); // R4-type instructions</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The intrinsic functions always return a 32-bit value of type <code>uint32_t</code> (the processing result), which can be +discarded if not needed. Each intrinsic function requires several arguments depending on the instruction type/format:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>funct7</code> - 7-bit immediate (R3-type)</p> +</li> +<li> +<p><code>funct3</code> - 3-bit immediate (R3-type, R4-type)</p> +</li> +<li> +<p><code>rs1</code> - source operand 1, 32-bit (R3-type, R4-type)</p> +</li> +<li> +<p><code>rs2</code> - source operand 2, 32-bit (R3-type, R4-type)</p> +</li> +<li> +<p><code>rs3</code> - source operand 3, 32-bit (R4-type)</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>The <code>funct3</code> and <code>funct7</code> bit-fields are used to pass 3-bit or 7-bit literals to the CFU. The <code>rs1</code>, <code>rs2</code> and +<code>rs3</code> arguments pass the actual data to the CFU via register addresses. These register arguments can be populated +with variables or literals; the compiler will add the required code to move the data into a register before +passing it to the CFU. The following examples shows how to pass arguments:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 12. CFU instruction usage example</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">uint32_t tmp = some_function(); +... +uint32_t res = neorv32_cfu_r3_instr(0b0000000, 0b101, tmp, 123); +uint32_t foo = neorv32_cfu_r4_instr(0b011, tmp, res, (uint32_t)some_array[i]); +neorv32_cfu_r3_instr(0b0100100, 0b001, tmp, foo); // discard result</code></pre> +</div> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">CFU Example Program</div> +There is an example program for the CFU, which shows how to use the <em>default</em> CFU hardware module. +This example program is located in <code>sw/example/demo_cfu</code>. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_cfu_control_and_status_registers_cfu_csrs">3.7.3. CFU Control and Status Registers (CFU-CSRs)</h4> +<div class="paragraph"> +<p>The CPU provides up to four control and status registers (<a href="#_cfureg"><code>cfureg*</code></a>) to be used within the CFU. +These CSRs are mapped to the "custom user-mode read/write" CSR address space, which is explicitly reserved for +platform-specific application by the RISC-V spec. For example, these CSRs can be used to pass additional operands +to the CFU, to obtain additional results, to check processing status or to configure operation modes.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 13. CFU CSR Access Example</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">neorv32_cpu_csr_write(CSR_CFUREG0, 0xabcdabcd); // write data to CFU CSR 0 +uint32_t tmp = neorv32_cpu_csr_read(CSR_CFUREG3); // read data from CFU CSR 3</code></pre> +</div> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Additional CFU-internal CSRs</div> +If more than four CFU-internal CSRs are required the designer can implement an "indirect access mechanism" based +on just two of the default CSRs: one CSR is used to configure the index while the other is used as alias to exchange +data with the indexed CFU-internal CSR - this concept is similar to the RISC-V Indirect CSR Access Extension +Specification (<code>Smcsrind</code>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Security Considerations</div> +The CFU CSRs are mapped to the user-mode CSR space so software running at <em>any privilege level</em> can access these +CSRs. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_custom_instructions_hardware">3.7.4. Custom Instructions Hardware</h4> +<div class="paragraph"> +<p>The actual functionality of the CFU&#8217;s custom instructions is defined by the user-defined logic inside the CFU +hardware module (<code>rtl/core/neorv32_cpu_cp_cfu.vhd</code>). This file is highly commented to explain the interface and +to illustrate hardware design considerations.</p> +</div> +<div class="paragraph"> +<p>CFU operations can be entirely combinatorial (like bit-reversal) so the result is available at the end of the +current clock cycle. However, operations can also take several clock cycles to complete (like multiplications) +and may also include internal states and memories.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">CFU Hardware Resource Requirements</div> +Enabling the CFU and actually implementing R4-type instructions (or more precisely, using the third register +source <code>rs3</code>) will add an additional read port to the core&#8217;s register file increasing resource requirements +of the register file by 50%. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">CFU Execution Time</div> +The CFU has to complete computation within a <strong>bound time window</strong> (default = 512 clock cycles). Otherwise, +the CFU operation is terminated by the CPU execution logic and an illegal instruction exception is raised. See section +<a href="#_cpu_arithmetic_logic_unit">CPU Arithmetic Logic Unit</a> for more information. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">CFU Exception</div> +The CFU can intentionally raise an illegal instruction exception by not asserting the <code>done</code> at all causing an +execution timeout. For example this can be used to signal invalid configurations/operations to the runtime +environment. See the documentation in the CFU&#8217;s VHDL source file for more information. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_control_and_status_registers_csrs">3.8. Control and Status Registers (CSRs)</h3> +<div class="paragraph"> +<p>The following table shows a summary of all available NEORV32 CSRs. The address field defines the CSR address for +the CSR access instructions. The "Name [ASM]" column provides the CSR name aliases that can be used in (inline) assembly. +The "Name [C]" column lists the name aliases that are defined by the NEORV32 core library. These can be used in plain C code. +The "Access" column shows the minimal required privilege mode required for accessing the according CSR (<code>M</code> = machine-mode, +<code>U</code> = user-mode, <code>D</code> = debug-mode) and the read/write capabilities (<code>RW</code> = read-write, <code>RO</code> = read-only)</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Unused, Reserved, Unimplemented and Disabled CSRs</div> +All CSRs and CSR bits that are not listed in the table below are <em>unimplemented</em> and are <em>hardwired to zero</em>. Additionally, +CSRs that are unavailable ("disabled") because the according ISA extension is not enabled are also considered <em>unimplemented</em> +and are also hardwired to zero. Any access to such a CSR will raise an illegal instruction exception. All writable CSRs provide +<strong>WARL</strong> behavior (write all values; read only legal values). Application software should always read back a CSR after writing +to check if the targeted bits can actually be modified. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-all stretch"> +<caption class="title">Table 69. NEORV32 Control and Status Registers (CSRs)</caption> +<colgroup> +<col style="width: 8.6956%;"> +<col style="width: 17.3913%;"> +<col style="width: 21.7391%;"> +<col style="width: 4.3478%;"> +<col style="width: 47.8262%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Address</th> +<th class="tableblock halign-left valign-top">Name [ASM]</th> +<th class="tableblock halign-left valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">Access</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_floating_point_csrs">Floating-Point CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x001</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_fflags"><strong><code>fflags</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_FFLAGS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">URW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Floating-point accrued exceptions</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x002</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_frm"><strong><code>frm</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_FRM</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">URW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Floating-point dynamic rounding mode</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x003</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_fcsr"><strong><code>fcsr</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_FCSR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">URW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Floating-point control and status</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_machine_trap_setup_csrs">Machine Trap Setup CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x300</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mstatus"><strong><code>mstatus</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MSTATUS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine status register - low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x301</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_misa"><strong><code>misa</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MISA</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine CPU ISA and extensions</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x304</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mie"><strong><code>mie</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MIE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine interrupt enable register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x305</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mtvec"><strong><code>mtvec</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MTVEC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine trap-handler base address for ALL traps</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x306</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mcounteren"><strong><code>mcounteren</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MCOUNTEREN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine counter-enable register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x310</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mstatush"><strong><code>mstatush</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MSTATUSH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine status register - high word</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_machine_configuration_csrs">Machine Configuration CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x30a</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_menvcfg"><strong><code>menvcfg</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MENVCFG</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine environment configuration register - low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x31a</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_menvcfgh"><strong><code>menvcfgh</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MENVCFGH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine environment configuration register - high word</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_machine_counter_setup_csrs">Machine Counter Setup CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x320</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mcountinhibit"><strong><code>mcountinhibit</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MCOUNTINHIBIT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine counter-inhibit register</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_machine_trap_handling_csrs">Machine Trap Handling CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x340</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mscratch"><strong><code>mscratch</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MSCRATCH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine scratch register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x341</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mepc"><strong><code>mepc</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MEPC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine exception program counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x342</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mcause"><strong><code>mcause</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MCAUSE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine trap cause</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x343</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mtval"><strong><code>mtval</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MTVAL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine trap value</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x344</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mip"><strong><code>mip</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MIP</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine interrupt pending register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x34a</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mtinst"><strong><code>mtinst</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MTINST</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine trap instruction</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_machine_physical_memory_protection_csrs">Machine Physical Memory Protection CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x3a0 .. 0x303</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_pmpcfg"><code>pmpcfg0</code></a> .. <a href="#_pmpcfg"><code>pmpcfg3</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_PMPCFG0</code> .. <code>CSR_PMPCFG3</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Physical memory protection configuration registers</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x3b0 .. 0x3bf</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_pmpaddr"><code>pmpaddr0</code></a> .. <a href="#_pmpaddr"><code>pmpaddr15</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_PMPADDR0</code> .. <code>CSR_PMPADDR15</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Physical memory protection address registers</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_trigger_module_csrs">Trigger Module CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x7a0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_tselect"><strong><code>tselect</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_TSELECT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger select register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x7a1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_tdata1"><strong><code>tdata1</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_TDATA1</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger data register 1</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x7a2</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_tdata2"><strong><code>tdata2</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_TDATA2</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger data register 2</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x7a4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_tinfo"><strong><code>tinfo</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_TINFO</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger information register</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_cpu_debug_mode_csrs">CPU Debug Mode CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x7b0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_dcsr"><strong><code>dcsr</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">DRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug control and status register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x7b1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_dpc"><strong><code>dpc</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">DRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug program counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x7b2</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_dscratch0"><strong><code>dscratch0</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">DRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug scratch register 0</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_custom_functions_unit_cfu_csrs">Custom Functions Unit (CFU) CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x800 .. 0x803</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_cfureg"><code>cfureg0</code></a> .. <a href="#_cfureg"><code>cfureg3</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_CFUCREG0</code> .. <code>CSR_CFUCREG3</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">URW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Custom CFU registers 0 to 3</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_machine_counter_and_timer_csrs">(Machine) Counter and Timer CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xb00</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mcycleh"><code>mcycle</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MCYCLE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine cycle counter low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xb02</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_minstreth"><code>minstret</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MINSTRET</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine instruction-retired counter low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xb80</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mcycleh"><code>mcycleh</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MCYCLEH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine cycle counter high word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xb82</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_minstreth"><code>minstreth</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MINSTRETH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine instruction-retired counter high word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xc00</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_cycleh"><code>cycle</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_CYCLE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">URO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Cycle counter low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xc02</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_instreth"><code>instret</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_INSTRET</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">URO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction-retired counter low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xc80</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_cycleh"><code>cycleh</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_CYCLEH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">URO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Cycle counter high word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xc82</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_instreth"><code>instreth</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_INSTRETH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">URO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction-retired counter high word</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_hardware_performance_monitors_hpm_csrs">Hardware Performance Monitors (HPM) CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x323 .. 0x32f</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mhpmevent"><code>mhpmevent3</code></a> .. <a href="#_mhpmevent"><code>mhpmevent15</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MHPMEVENT3</code> .. <code>CSR_MHPMEVENT15</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine performance-monitoring event select for counter 3..15</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xb03 .. 0xb0f</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mhpmcounterh"><code>mhpmcounter3</code></a> .. <a href="#_mhpmcounterh"><code>mhpmcounter15</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MHPMCOUNTER3</code> .. <code>CSR_MHPMCOUNTER15</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine performance-monitoring counter 3..15 low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xb83 .. 0xb8f</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mhpmcounterh"><code>mhpmcounter3h</code></a> .. <a href="#_mhpmcounterh"><code>mhpmcounter15h</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MHPMCOUNTER3H</code> .. <code>CSR_MHPMCOUNTER15H</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRW</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine performance-monitoring counter 3..15 high word</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_machine_information_csrs">Machine Information CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xf11</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mvendorid"><strong><code>mvendorid</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MVENDORID</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine vendor ID</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xf12</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_marchid"><strong><code>marchid</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MARCHID</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine architecture ID</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xf13</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mimpid"><strong><code>mimpid</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MIMPID</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine implementation ID / version</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xf14</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mhartid"><strong><code>mhartid</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MHARTID</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine hardware thread ID</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xf15</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mconfigptr"><strong><code>mconfigptr</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MCONFIGPTR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine configuration pointer register</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="5"><p class="tableblock"><strong><a href="#_neorv32_specific_csrs">NEORV32-Specific CSRs</a></strong></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0xfc0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_mxisa"><strong><code>mxisa</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MXISA</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">MRO</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">NEORV32-specific "eXtended" machine CPU ISA and extensions</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +<div class="sect3"> +<h4 id="_floating_point_csrs">3.8.1. Floating-Point CSRs</h4> +<h5 id="_fflags" class="discrete"><strong><code>fflags</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Floating-point accrued exceptions</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x001</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zfinx</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">FPU status flags.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 70. <code>fflags</code> CSR bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 83.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>NX</strong>: inexact</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>UF</strong>: underflow</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>OF</strong>: overflow</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>DZ</strong>: division by zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>NV</strong>: invalid operation</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_frm" class="discrete"><strong><code>frm</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Floating-point dynamic rounding mode</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x002</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zfinx</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>frm</code> CSR is used to configure the rounding mode of the FPU.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 71. <code>frm</code> CSR bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 83.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Rounding mode</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_fcsr" class="discrete"><strong><code>fcsr</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Floating-point control and status register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x003</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zfinx</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>fcsr</code> provides combined access to the <a href="#_fflags"><strong><code>fflags</code></strong></a> and <a href="#_frm"><strong><code>frm</code></strong></a> flags.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 72. <code>fcsr</code> CSR bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 83.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Accrued exception flags (<a href="#_fflags"><strong><code>fflags</code></strong></a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7:5</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Rounding mode (<a href="#_frm"><strong><code>frm</code></strong></a>)</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_machine_trap_setup_csrs">3.8.2. Machine Trap Setup CSRs</h4> +<h5 id="_mstatus" class="discrete"><strong><code>mstatus</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine status register - low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x300</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00001800</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mstatus</code> CSR is used to configure general machine environment parameters.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 73. <code>mstatus</code> CSR bits</caption> +<colgroup> +<col style="width: 7.1428%;"> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 64.2859%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MSTATUS_MIE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MIE</strong>: Machine-mode interrupt enable flag</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MSTATUS_MPIE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MPIE</strong>: Previous machine-mode interrupt enable flag state</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">12:11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MSTATUS_MPP_H</code> : <code>CSR_MSTATUS_MPP_L</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MPP</strong>: Previous machine privilege mode, <code>11</code> = machine-mode "M", <code>00</code> = user-mode "U"; other values will fall-back to machine-mode</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">17</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MSTATUS_MPRV</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MPRV</strong>: Effective privilege mode for load/stores; use <code>MPP</code> as effective privilege mode when set; hardwired to zero if user-mode not implemented</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">21</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MSTATUS_TW</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>TW</strong>: Trap on execution of <code>wfi</code> instruction in user mode when set; hardwired to zero if user-mode not implemented</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +If the core is in user-mode, machine-mode interrupts are globally <strong>enabled</strong> even if <code>mstatus.mie</code> is cleared: +"Interrupts for higher-privilege modes, y&gt;x, are always globally enabled regardless of the setting of the global yIE +bit for the higher-privilege mode." - RISC-V ISA Spec. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_misa" class="discrete"><strong><code>misa</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA and extensions</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x301</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DEFINED</code>, according to enabled ISA extensions</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>misa</code> CSR provides information regarding the availability of basic RISC-V ISa extensions.</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The NEORV32 <code>misa</code> CSR is read-only. Hence, active CPU extensions are entirely defined by pre-synthesis configurations +and cannot be switched on/off during runtime. For compatibility reasons any write access to this CSR is simply ignored and +will <em>not</em> cause an illegal instruction exception. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 74. <code>misa</code> CSR bits</caption> +<colgroup> +<col style="width: 7.1428%;"> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 64.2859%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MISA_B_EXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>B</strong>: CPU extension (bit-manipulation) available, set when <a href="#_b_isa_extension"><code>B</code> ISA Extension</a> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MISA_C_EXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>C</strong>: CPU extension (compressed instruction) available, set when <a href="#_c_isa_extension"><code>C</code> ISA Extension</a> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MISA_E_EXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>E</strong>: CPU extension (embedded) available, set when <a href="#_e_isa_extension"><code>E</code> ISA Extension</a> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MISA_I_EXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>I</strong>: CPU base ISA, cleared when <a href="#_e_isa_extension"><code>E</code> ISA Extension</a> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">12</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MISA_M_EXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>M</strong>: CPU extension (mul/div) available, set when <a href="#_m_isa_extension"><code>M</code> ISA Extension</a> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">20</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MISA_U_EXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>U</strong>: CPU extension (user mode) available, set when <a href="#_u_isa_extension"><code>U</code> ISA Extension</a> enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">23</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MISA_X_EXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>X</strong>: bit is always set to indicate non-standard / NEORV32-specific extensions</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:30</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MISA_MXL_HI_EXT</code> : <code>CSR_MISA_MXL_LO_EXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MXL</strong>: 32-bit architecture indicator (always <code>01</code>)</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +Machine-mode software can discover available <code>Z*</code> <em>sub-extensions</em> (like <code>Zicsr</code> or <code>Zfinx</code>) by checking the NEORV32-specific +<a href="#_mxisa"><strong><code>mxisa</code></strong></a> CSR. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mie" class="discrete"><strong><code>mie</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine interrupt-enable register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x304</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mie</code> CSR is used to enable/disable individual interrupt sources.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 75. <code>mie</code> CSR bits</caption> +<colgroup> +<col style="width: 7.1428%;"> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 64.2859%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MIE_MSIE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MSIE</strong>: Machine <em>software</em> interrupt enable</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MIE_MTIE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MTIE</strong>: Machine <em>timer</em> interrupt enable (from <a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MIE_MEIE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MEIE</strong>: Machine <em>external</em> interrupt enable</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MIE_FIRQ15E</code> : <code>CSR_MIE_FIRQ0E</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Fast interrupt channel 15..0 enable</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mtvec" class="discrete"><strong><code>mtvec</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine trap-handler base address</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x305</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mtvec</code> CSR holds the trap vector configuration.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 76. <code>mtvec</code> CSR bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 83.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MODE</strong>: mode configuration, <code>00</code> = DIRECT, <code>01</code> = VECTORED; other encodings are <em>reserved</em>.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>BASE</strong>: in DIRECT mode = 4-byte-aligned base address of trap base handler, <em>all</em> traps jump to <code>pc = BASE</code>; +in VECTORED mode = 128-byte-aligned base address of trap vector table, interrupts cause a jump to <code>pc = BASE + 4 * mcause</code> +and exceptions a jump to <code>pc = BASE</code>.</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Interrupt Latency</div> +The vectored <code>mtvec</code> mode is useful for reducing the time between interrupt request (IRQ) and servicing it (ISR). +As software does not need to determine the interrupt cause the reduction in latency can be 5 to 10 times and as low as <em>26</em> cycles. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mcounteren" class="discrete"><strong><code>mcounteren</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine counter enable</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x306</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zicntr</code> &amp; <code>U</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mcounteren</code> CSR is used to constrain user-mode access to the CPU&#8217;s counter CSRs.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 77. <code>mcounteren</code> CSR bits</caption> +<colgroup> +<col style="width: 10%;"> +<col style="width: 10%;"> +<col style="width: 80%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-left valign-top">R/W</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">Function</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CSR_MCOUNTEREN_CY</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>CY</strong>: User-mode is allowed to read <a href="#_cycleh"><strong><code>cycle[h]</code></strong></a> CSRs when set</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">1</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>TM</strong>: not implemented, hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MCOUNTEREN_IR</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">r/w</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>IR</strong>: User-mode is allowed to read <a href="#_instreth"><strong><code>instret[h]</code></strong></a> CSRs when set</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:3</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mstatush" class="discrete"><strong><code>mstatush</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine status register - high word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x310</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The features of this CSR are not implemented yet. The register is read-only and always returns zero.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_machine_trap_handling_csrs">3.8.3. Machine Trap Handling CSRs</h4> +<h5 id="_mscratch" class="discrete"><strong><code>mscratch</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Scratch register for machine trap handlers</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x340</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mscratch</code> is a general-purpose machine-mode scratch register.</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mepc" class="discrete"><strong><code>mepc</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine exception program counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x341</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mepc</code> CSR provides the instruction address where execution has stopped/failed when +an interrupt is triggered / an exception is raised. See section <a href="#_traps_exceptions_and_interrupts">Traps, Exceptions and Interrupts</a> for a list of all legal values. +The <code>mret</code> instruction will return to the address stored in <code>mepc</code> by automatically moving <code>mepc</code> to the program counter.</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<code>mepc[0]</code> is hardwired to zero. If IALIGN = 32 (i.e. <a href="#_c_isa_extension"><code>C</code> ISA Extension</a> is disabled) then <code>mepc[1]</code> is also hardwired to zero. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mcause" class="discrete"><strong><code>mcause</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine trap cause</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x342</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mcause</code> CSRs shows the exact cause of a trap. See section <a href="#_traps_exceptions_and_interrupts">Traps, Exceptions and Interrupts</a> for a list of all legal values.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 78. <code>mcause</code> CSR bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 8.3333%;"> +<col style="width: 83.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Exception code</strong>: see <a href="#_neorv32_trap_listing">NEORV32 Trap Listing</a></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Interrupt</strong>: <code>1</code> if the trap is caused by an interrupt (<code>0</code> if the trap is caused by an exception)</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mtval" class="discrete"><strong><code>mtval</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine trap value</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x343</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mtval</code> CSR provides additional information why a trap was entered. See section <a href="#_traps_exceptions_and_interrupts">Traps, Exceptions and Interrupts</a> for more information.</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Read-Only</div> +Note that the NEORV32 <code>mtval</code> CSR is updated by the hardware only and cannot be written from software. +However, any write-access will be ignored and will not cause an exception to maintain RISC-V compatibility. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mip" class="discrete"><strong><code>mip</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine interrupt pending</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x344</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mip</code> CSR shows currently <em>pending</em> machine-mode interrupt requests. Any write access to this register is ignored.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 79. <code>mip</code> CSR bits</caption> +<colgroup> +<col style="width: 7.1428%;"> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 64.2859%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MIP_MSIP</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MSIP</strong>: Machine <em>software</em> interrupt pending; <em>cleared by platform-defined mechanism</em></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MIP_MTIP</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MTIP</strong>: Machine <em>timer</em> interrupt pending; <em>cleared by platform-defined mechanism</em></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MIP_MEIP</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>MEIP</strong>: Machine <em>external</em> interrupt pending; <em>cleared by platform-defined mechanism</em></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MIP_FIRQ15P</code> : <code>CSR_MIP_FIRQ0P</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>FIRQxP</strong>: Fast interrupt channel 15..0 pending; <em>cleared by platform-defined mechanism</em></p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">FIRQ Channel Mapping</div> +See section <a href="#_neorv32_specific_fast_interrupt_requests">NEORV32-Specific Fast Interrupt Requests</a> for the mapping of the FIRQ channels and the according +interrupt-triggering processor module. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mtinst" class="discrete"><strong><code>mtinst</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine trap instruction</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x34a</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mtinst</code> CSR provides additional information why a trap was entered. See section <a href="#_traps_exceptions_and_interrupts">Traps, Exceptions and Interrupts</a> for more information.</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Read-Only</div> +Note that the NEORV32 <code>mtinst</code> CSR is updated by the hardware only and cannot be written from software. +However, any write-access will be ignored and will not cause an exception to maintain RISC-V compatibility. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Instruction Transformation</div> +The RISC-V priv. spec. suggests that the instruction word written to <code>mtinst</code> by the hardware should be "transformed". +However, the NEORV32 <code>mtinst</code> CSR uses a simplified transformation scheme: if the trap-causing instruction is a +standard 32-bit instruction, <code>mtinst</code> contains the exact instruction word that caused the trap. If the trap-causing +instruction is a compressed instruction, <code>mtinst</code> contains the de-compressed 32-bit equivalent with bit 1 being cleared +while all remaining bits represent the pre-decoded 32-bit instruction equivalent. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_machine_configuration_csrs">3.8.4. Machine Configuration CSRs</h4> +<h5 id="_menvcfg" class="discrete"><strong><code>menvcfg</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine environment configuration register - low word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x30a</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>U</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Currently, the features of this CSR are not supported. Hence, the entire register is hardwired to all-zero.</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_menvcfgh" class="discrete"><strong><code>menvcfgh</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine environment configuration register - high word</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x31a</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>U</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Currently, the features of this CSR are not supported. Hence, the entire register is hardwired to all-zero.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_machine_physical_memory_protection_csrs">3.8.5. Machine Physical Memory Protection CSRs</h4> +<div class="paragraph"> +<p>The physical memory protection system is configured via the <code>PMP_NUM_REGIONS</code> and <code>PMP_MIN_GRANULARITY</code> top entity +generics. <code>PMP_NUM_REGIONS</code> defines the total number of implemented regions. Note that the maximum number of regions +is constrained to 16. If trying to access a PMP-related CSR beyond <code>PMP_NUM_REGIONS</code> <strong>no illegal instruction exception</strong> +is triggered. The according CSRs are read-only (writes are ignored) and always return zero. +See section <a href="#_smpmp_isa_extension"><code>Smpmp</code> ISA Extension</a> for more information.</p> +</div> +<h5 id="_pmpcfg" class="discrete"><strong><code>pmpcfg</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PMP region configuration registers</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3a0</code> (<code>pmpcfg0</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3a1</code> (<code>pmpcfg1</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3a2</code> (<code>pmpcfg2</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3a3</code> (<code>pmpcfg3</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Smpmp</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Configuration of physical memory protection regions. Each region provides an individual 8-bit array in these CSRs.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 80. <code>pmpcfg0</code> CSR Bits</caption> +<colgroup> +<col style="width: 6.6666%;"> +<col style="width: 13.3333%;"> +<col style="width: 6.6666%;"> +<col style="width: 73.3335%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Function</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>PMPCFG_R</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>R</strong>: Read permission</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>PMPCFG_W</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>W</strong>: Write permission</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>PMPCFG_X</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>X</strong>: Execute permission</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4:3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>PMPCFG_A_MSB</code> : <code>PMPCFG_A_LSB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>A</strong>: Mode configuration (<code>00</code> = OFF, <code>01</code> = TOR, <code>10</code> = NA4, <code>11</code> = NAPOT)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>PMPCFG_L</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>L</strong>: Lock bit, prevents further write accesses, also enforces access rights in machine-mode, can only be cleared by CPU reset</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Implemented Modes</div> +In order to reduce the CPU size certain PMP modes (<code>A</code> bits) can be excluded from synthesis. +Use the <code>PMP_TOR_MODE_EN</code> and <code>PMP_NAP_MODE_EN</code> <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a> to control +implementation of the according modes. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_pmpaddr" class="discrete"><strong><code>pmpaddr</code></strong></h5> +<div class="paragraph"> +<p>The <code>pmpaddr*</code> CSRs are used to configure the region&#8217;s address boundaries.</p> +</div> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Physical memory protection address registers</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b0</code> (<code>pmpaddr1</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b1</code> (<code>pmpaddr2</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b2</code> (<code>pmpaddr3</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b3</code> (<code>pmpaddr4</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b4</code> (<code>pmpaddr5</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b5</code> (<code>pmpaddr6</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b6</code> (<code>pmpaddr6</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b7</code> (<code>pmpaddr7</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b8</code> (<code>pmpaddr8</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3b9</code> (<code>pmpaddr9</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3ba</code> (<code>pmpaddr10</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3bb</code> (<code>pmpaddr11</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3bc</code> (<code>pmpaddr12</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3bd</code> (<code>pmpaddr13</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3be</code> (<code>pmpaddr14</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x3bf</code> (<code>pmpaddr15</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Smpmp</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Region address configuration. The two MSBs of each CSR are hardwired to zero (= bits 33:32 of the physical address).</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_custom_functions_unit_cfu_csrs">3.8.6. Custom Functions Unit (CFU) CSRs</h4> +<h5 id="_cfureg" class="discrete"><strong><code>cfureg</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Custom (user-defined) CFU CSRs</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x800</code> (<code>cfureg0</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x801</code> (<code>cfureg1</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x802</code> (<code>cfureg2</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x803</code> (<code>cfureg3</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zxcfu</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">User-defined CSRs to be used within the <a href="#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a>.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_machine_counter_and_timer_csrs">3.8.7. (Machine) Counter and Timer CSRs</h4> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title"><code>time[h]</code> CSRs (Wall Clock Time)</div> +The NEORV32 does not implement the user-mode <code>time[h]</code> registers. Any access to these registers will trap. +It is recommended that the trap handler software provides a means of accessing the platform-defined <a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Instruction Retired Counter Increment</div> +The <code>[m]instret[h]</code> counter always increments when a instruction enters the pipeline&#8217;s execute stage no matter +if this instruction is actually going to retire or if it causes an exception. +</td> +</tr> +</table> +</div> +<h5 id="_cycleh" class="discrete"><strong><code>cycle[h]</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Cycle counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xc00</code> (<code>cycle</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xc80</code> (<code>cycleh</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zicntr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>cycle[h]</code> CSRs are user-mode shadow copies of the according <a href="#_mcycleh"><strong><code>mcycle[h]</code></strong></a> CSRs. The user-mode +counter are read-only. Any write access will raise an illegal instruction exception.</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_instreth" class="discrete"><strong><code>instret[h]</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instructions-retired counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xc02</code> (<code>instret</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xc82</code> (<code>instreth</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zicntr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>instret[h]</code> CSRs are user-mode shadow copies of the according <a href="#_minstreth"><strong><code>minstret[h]</code></strong></a> CSRs. The user-mode +counter are read-only. Any write access will raise an illegal instruction exception.</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mcycleh" class="discrete"><strong><code>mcycle[h]</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine cycle counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb00</code> (<code>mcycle</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb80</code> (<code>mcycleh</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zicntr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">If not halted via the <a href="#_mcountinhibit"><strong><code>mcountinhibit</code></strong></a> CSR the <code>cycle[h]</code> CSRs will increment with every active CPU clock +cycle (CPU not in sleep mode). These registers are read/write only for machine-mode software.</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_minstreth" class="discrete"><strong><code>minstret[h]</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine instructions-retired counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb02</code> (<code>minstret</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb82</code> (<code>minstreth</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zicntr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">If not halted via the <a href="#_mcountinhibit"><strong><code>mcountinhibit</code></strong></a> CSR the <code>minstret[h]</code> CSRs will increment with every retired instruction. +These registers are read/write only for machine-mode software</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Instruction Retiring</div> +Note that <strong>all</strong> executed instruction do increment the <code>[m]instret</code>[h] counters even if they do not retire +(e.g. if the instruction causes an exception). +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_hardware_performance_monitors_hpm_csrs">3.8.8. Hardware Performance Monitors (HPM) CSRs</h4> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Machine-Mode HPMs Only</div> +Note that only the machine-mode hardware performance counter CSR are available (<code>mhpmcounter*[h]</code>). +Accessing any user-mode HPM CSR (<code>hpmcounter*[h]</code>) will raise an illegal instruction exception. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The actual number of implemented hardware performance monitors is configured via the <code>HPM_NUM_CNTS</code> top entity generic, +Note that always all 13 HPM counter and configuration registers (<code>mhpmcounter*[h]</code>) are implemented, but +only the actually configured ones are implemented as "real" physical registers - the remaining ones will be hardwired to zero. +If trying to access an HPM-related CSR beyond <code>HPM_NUM_CNTS</code> <strong>no illegal instruction exception is +triggered</strong>. These CSRs are read-only, writes are ignored and reads always return zero.</p> +</div> +<div class="paragraph"> +<p>The total counter width of the HPMs can be configured before synthesis via the <code>HPM_CNT_WIDTH</code> generic (0..64-bit). +If <code>HPM_NUM_CNTS</code> is less than 64, all remaining MSB-aligned bits are hardwired to zero.</p> +</div> +<h5 id="_mhpmevent" class="discrete"><strong><code>mhpmevent</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine hardware performance monitor event select</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x233</code> (<code>mhpmevent3</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x234</code> (<code>mhpmevent4</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x235</code> (<code>mhpmevent5</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x236</code> (<code>mhpmevent6</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x237</code> (<code>mhpmevent7</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x238</code> (<code>mhpmevent8</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x239</code> (<code>mhpmevent9</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x23a</code> (<code>mhpmevent10</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x23b</code> (<code>mhpmevent11</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x23c</code> (<code>mhpmevent12</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x23d</code> (<code>mhpmevent13</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x23e</code> (<code>mhpmevent14</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x23f</code> (<code>mhpmevent15</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zihpm</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The value in these CSRs define the architectural events that cause an increment of the according <code>mhpmcounter*[h]</code> counter(s). +All available events are listed in the table below. If more than one event is selected, the according counter will increment if <em>any</em> of +the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock +cycle even if more than one trigger event is observed.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 81. <code>mhpmevent*</code> CSR Bits</caption> +<colgroup> +<col style="width: 7.1428%;"> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 64.2859%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Event Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>RISC-V-compatible</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_CY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">active clock cycle (CPU not in <a href="#_sleep_mode">Sleep Mode</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_TM</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>not implemented</em>, hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_IR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">any executed instruction (16-bit/compressed or 32-bit/uncompressed)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock"><strong>NEORV32-specific</strong></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_COMPR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">any executed 16-bit/compressed (<a href="#_c_isa_extension"><code>C</code> ISA Extension</a>) instruction</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_WAIT_DIS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">instruction dispatch wait cycle (wait for instruction prefetch-buffer refill (<a href="#_cpu_control_unit">CPU Control Unit</a> IPB); +caused by a fence instruction, a control flow transfer or a instruction fetch bus wait cycle)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">5</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_WAIT_ALU</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">any delay/wait cycle caused by a <em>multi-cycle</em> <a href="#_cpu_arithmetic_logic_unit">CPU Arithmetic Logic Unit</a> operation</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">6</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_BRANCH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">any executed branch instruction (unconditional, conditional-taken or conditional-not-taken)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_BRANCHED</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">any control transfer operation (unconditional jump, taken conditional branch or trap entry/exit)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_LOAD</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">any executed load operation (including atomic memory operations, <a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">9</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_STORE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">any executed store operation (including atomic memory operations, <a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">10</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_WAIT_LSU</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">any memory/bus/cache/etc. delay/wait cycle while executing any load or store operation (caused by a data bus wait cycle))</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>HPMCNT_EVENT_TRAP</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">starting processing of any trap (<a href="#_traps_exceptions_and_interrupts">Traps, Exceptions and Interrupts</a>)</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Instruction Retiring ("Retired == Executed")</div> +The CPU HPM/counter logic treats all executed instruction as "retired" even if they raise an exception, +cause an interrupt, trigger a privilege mode change or were not meant to retire (i.e. claimed by the RISC-V spec.). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mhpmcounterh" class="discrete"><strong><code>mhpmcounter[h]</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine hardware performance monitor (HPM) counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb03</code>, <code>0xb83</code> (<code>mhpmcounter3</code>, <code>mhpmcounter3h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb04</code>, <code>0xb84</code> (<code>mhpmcounter4</code>, <code>mhpmcounter4h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb05</code>, <code>0xb85</code> (<code>mhpmcounter5</code>, <code>mhpmcounter5h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb06</code>, <code>0xb86</code> (<code>mhpmcounter6</code>, <code>mhpmcounter6h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb07</code>, <code>0xb87</code> (<code>mhpmcounter7</code>, <code>mhpmcounter7h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb08</code>, <code>0xb88</code> (<code>mhpmcounter8</code>, <code>mhpmcounter8h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb09</code>, <code>0xb89</code> (<code>mhpmcounter9</code>, <code>mhpmcounter9h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb0a</code>, <code>0xb8a</code> (<code>mhpmcounter10</code>, <code>mhpmcounter10h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb0b</code>, <code>0xb8b</code> (<code>mhpmcounter11</code>, <code>mhpmcounter11h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb0c</code>, <code>0xb8c</code> (<code>mhpmcounter12</code>, <code>mhpmcounter12h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb0d</code>, <code>0xb8d</code> (<code>mhpmcounter13</code>, <code>mhpmcounter13h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb0e</code>, <code>0xb8e</code> (<code>mhpmcounter14</code>, <code>mhpmcounter14h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xb0f</code>, <code>0xb8f</code> (<code>mhpmcounter15</code>, <code>mhpmcounter15h</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Zihpm</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">If not halted via the <a href="#_mcountinhibit"><strong><code>mcountinhibit</code></strong></a> CSR the HPM counter CSR(s) increment whenever the +configured event from the according <a href="#_mhpmevent"><strong><code>mhpmevent</code></strong></a> CSR occurs. The counter registers are read/write for machine mode +and are not accessible for lower-privileged software.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_machine_counter_setup_csrs">3.8.9. Machine Counter Setup CSRs</h4> +<h5 id="_mcountinhibit" class="discrete"><strong><code>mcountinhibit</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine counter-inhibit register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x320</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set bit to halt the according counter CSR.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 82. <code>mcountinhibit</code> CSR Bits</caption> +<colgroup> +<col style="width: 7.1428%;"> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 64.2859%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MCOUNTINHIBIT_IR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>IR</strong>: Set to <code>1</code> to halt <code>[m]instret[h]</code>; hardwired to zero if <code>Zicntr</code> ISA extension is disabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>TM</strong>: Hardwired to zero as <code>time[h]</code> CSRs are not implemented</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MCOUNTINHIBIT_CY</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>CY</strong>: Set to <code>1</code> to halt <code>[m]cycle[h]</code>; hardwired to zero if <code>Zicntr</code> ISA extension is disabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15:3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MCOUNTINHIBIT_HPM3</code> : <code>CSR_MCOUNTINHIBIT_HPM15</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>HPMx</strong>: Set to <code>1</code> to halt <code>[m]hpmcount*[h]</code>; hardwired to zero if <code>Zihpm</code> ISA extension is disabled</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_machine_information_csrs">3.8.10. Machine Information CSRs</h4> +<h5 id="_mvendorid" class="discrete"><strong><code>mvendorid</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine vendor ID</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xf11</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DEFINED</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Vendor ID (JEDEC identifier, lowest 11 bits), assigned via the <code>JEDEC_ID</code> top generic (<a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a>).</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_marchid" class="discrete"><strong><code>marchid</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine architecture ID</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xf12</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000013</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>marchid</code> CSR is read-only and provides the NEORV32 official RISC-V open-source architecture ID +(decimal: 19, 32-bit hexadecimal: 0x00000013).</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mimpid" class="discrete"><strong><code>mimpid</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine implementation ID</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xf13</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DEFINED</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mimpid</code> CSR is read-only and provides the version of the +NEORV32 as BCD-coded number (example: <code>mimpid = 0x01020312</code> โ†’ 01.02.03.12 โ†’ version 1.2.3.12).</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mhartid" class="discrete"><strong><code>mhartid</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine hardware thread ID</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xf14</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DEFINED</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mhartid</code> CSR is read-only and provides the core&#8217;s hart ID, +which is assigned via the <code>HW_THREAD_ID</code> top generic (<a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a>).</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><br></p> +</div> +<h5 id="_mconfigptr" class="discrete"><strong><code>mconfigptr</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine configuration pointer register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xf15</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The features of this CSR are not implemented yet. The register is read-only and always returns zero.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect3"> +<h4 id="_neorv32_specific_csrs">3.8.11. NEORV32-Specific CSRs</h4> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +All NEORV32-specific CSRs are mapped to addresses that are explicitly reserved for custom <strong>Machine-Mode, read-only</strong> CSRs +(assured by the RISC-V privileged specifications). Hence, these CSRs can only be accessed when in machine-mode. Any access +outside of machine-mode will raise an illegal instruction exception. +</td> +</tr> +</table> +</div> +<h5 id="_mxisa" class="discrete"><strong><code>mxisa</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Machine extended ISA and extensions register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0xfc0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DEFINED</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>X</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <code>mxisa</code> CSRs is a NEORV32-specific read-only CSR that helps machine-mode software to +discover ISA sub-extensions and CPU configuration options</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 83. <code>mxisa</code> CSR Bits</caption> +<colgroup> +<col style="width: 10%;"> +<col style="width: 30%;"> +<col style="width: 10%;"> +<col style="width: 50%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [C]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZICSR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zicsr_isa_extension"><code>Zicsr</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZIFENCEI</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zifencei_isa_extension"><code>Zifencei</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZMMUL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zmmul_isa_extension"><code>Zmmul</code> - ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZXCFU</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zxcfu_isa_extension"><code>Zxcfu</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZKT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zkt_isa_extension"><code>Zkt</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">5</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZFINX</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zfinx_isa_extension"><code>Zfinx</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">6</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZICOND</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zicond_isa_extension"><code>Zicond</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZICNTR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zicntr_isa_extension"><code>Zicntr</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_SMPMP</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_smpmp_isa_extension"><code>Smpmp</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">9</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZIHPM</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zihpm_isa_extension"><code>Zihpm</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">10</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_SDEXT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_sdext_isa_extension"><code>Sdext</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_SDTRIG</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_sdtrig_isa_extension"><code>Sdtrig</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">12</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZBKX</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbkx_isa_extension"><code>Zbkx</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">13</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZKND</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zknd_isa_extension"><code>Zknd</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">14</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZKNE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zkne_isa_extension"><code>Zkne</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZKNH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zknh_isa_extension"><code>Zknh</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZBKB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbkb_isa_extension"><code>Zbkb</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">17</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZBKC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbkc_isa_extension"><code>Zbkc</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">18</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZKN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zkn_isa_extension"><code>Zkn</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">19</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZKSH</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zksh_isa_extension"><code>Zksh</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">20</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZKSED</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zksed_isa_extension"><code>Zksed</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">21</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZKS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zks_isa_extension"><code>Zks</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">22</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZBA</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zba_isa_extension"><code>Zba</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">23</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZBB</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbb_isa_extension"><code>Zbb</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">24</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZBS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zbs_isa_extension"><code>Zbs</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">25</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_ZALRSC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a> available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">27:26</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">28</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_RFHWRST</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">full hardware reset of register file available when set (<code>REGFILE_HW_RST</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">29</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_FASTMUL</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast multiplication available when set (<code>FAST_MUL_EN</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">30</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_FASTSHIFT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast shifts available when set (<code>FAST_SHIFT_EN</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CSR_MXISA_IS_SIM</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set if CPU is being <strong>simulated</strong> (โš ๏ธ not guaranteed)</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_traps_exceptions_and_interrupts">3.9. Traps, Exceptions and Interrupts</h3> +<div class="paragraph"> +<p>In this document the following terminology is used (derived from the RISC-V trace specification +available at <a href="https://github.com/riscv-non-isa/riscv-trace-spec" class="bare">https://github.com/riscv-non-isa/riscv-trace-spec</a>):</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><strong>exception</strong>: an unusual condition occurring at run time associated (i.e. <em>synchronous</em>) with an instruction in a RISC-V hart</p> +</li> +<li> +<p><strong>interrupt</strong>: an external <em>asynchronous</em> event that may cause a RISC-V hart to experience an unexpected transfer of control</p> +</li> +<li> +<p><strong>trap</strong>: the transfer of control to a trap handler caused by either an <em>exception</em> or an <em>interrupt</em></p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>Whenever an exception or interrupt is triggered, the CPU switches to machine-mode (if not already in machine-mode) +and continues operation at the address being stored in the <a href="#_mtvec"><strong><code>mtvec</code></strong></a> CSR. The cause of the the trap can be determined via the +<a href="#_mcause"><strong><code>mcause</code></strong></a> CSR. A list of all implemented <code>mcause</code> values and the according description can be found below in section +<a href="#_neorv32_trap_listing">NEORV32 Trap Listing</a>. The address that reflects the current program counter when a trap was taken is stored to +<a href="#_mepc"><strong><code>mepc</code></strong></a> CSR. Additional information regarding the cause of the trap can be retrieved from the <a href="#_mtval"><strong><code>mtval</code></strong></a> and <a href="#_mtinst"><strong><code>mtinst</code></strong></a> CSRs.</p> +</div> +<div class="paragraph"> +<p>The traps are prioritized. If several <em>exceptions</em> occur at once only the one with highest priority is triggered +while all remaining exceptions are ignored and discarded. If several <em>interrupts</em> trigger at once, the one with highest priority +is serviced first while the remaining ones stay <em>pending</em>. After completing the interrupt handler the interrupt with +the second highest priority will get serviced and so on until no further interrupts are pending.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Interrupts when in User-Mode</div> +If the core is currently operating in less privileged user-mode, interrupts are globally enabled +even if <a href="#_mstatus"><strong><code>mstatus</code></strong></a>.mie is cleared. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Interrupt Signal Requirements - Standard RISC-V Interrupts</div> +All interrupt request signals are <strong>high-active</strong>. Once triggered, a interrupt request line should stay high +until it is explicitly acknowledged by a source-specific mechanism (for example by writing to a specific memory-mapped register). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Instruction Atomicity and Forward-Progress</div> +All instructions execute as atomic operations - interrupts can only trigger <em>between</em> consecutive instructions. +Additionally, if there is a permanent interrupt request, exactly one instruction from the interrupted program will be executed before +another interrupt handler can start. This allows program progress even if there are permanent interrupt requests. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_memory_access_exceptions">3.9.1. Memory Access Exceptions</h4> +<div class="paragraph"> +<p>If a load operation causes any exception, the instruction&#8217;s destination register is <strong>not written</strong> at all. Furthermore, +exceptions caused by a misaligned memory address a physical memory protection fault do not trigger a memory access request at all.</p> +</div> +<div class="paragraph"> +<p>For 32-bit-only instructions (= no <code>C</code> extension) the misaligned instruction exception is raised if bit 1 of the fetch +address is set (i.e. not on a 32-bit boundary). If the <code>C</code> extension is implemented there will <strong>never</strong> be a misaligned +instruction exception at all.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_custom_fast_interrupt_request_lines">3.9.2. Custom Fast Interrupt Request Lines</h4> +<div class="paragraph"> +<p>As a custom extension, the NEORV32 CPU features 16 fast interrupt request (FIRQ) lines via the <code>firq_i</code> CPU top +entity signals. These interrupts have custom configuration and status flags in the <a href="#_mie"><strong><code>mie</code></strong></a> and <a href="#_mip"><strong><code>mip</code></strong></a> CSRs and also +provide custom trap codes in <a href="#_mcause"><strong><code>mcause</code></strong></a>. These FIRQs are reserved for NEORV32 processor-internal usage only.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_neorv32_trap_listing">3.9.3. NEORV32 Trap Listing</h4> +<div class="paragraph"> +<p>The following tables show all traps that are currently supported by the NEORV32 CPU. It also shows the prioritization +and the CSR side-effects.</p> +</div> +<div class="paragraph"> +<p><strong>Table Annotations</strong></p> +</div> +<div class="paragraph"> +<p>The "Prio." column shows the priority of each trap with the highest priority being 1. The "RTE Trap ID" aliases are +defined by the NEORV32 core library (the runtime environment <em>RTE</em>) and can be used in plain C code when interacting +with the pre-defined RTE function. The <a href="#_mcause"><strong><code>mcause</code></strong></a>, <a href="#_mepc"><strong><code>mepc</code></strong></a>, <a href="#_mtval"><strong><code>mtval</code></strong></a> and <a href="#_mtinst"><strong><code>mtinst</code></strong></a> columns show the value being +written to the according CSRs when a trap is triggered:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><strong>I-PC</strong> - address of intercepted instruction (instruction has <em>not</em> been executed yet)</p> +</li> +<li> +<p><strong>PC</strong> - address of instruction that caused the trap (instruction has been executed)</p> +</li> +<li> +<p><strong>ADR</strong> - bad data memory access address that caused the trap</p> +</li> +<li> +<p><strong>INS</strong> - the transformed/decompressed instruction word that caused the trap</p> +</li> +<li> +<p><strong>0</strong> - zero</p> +</li> +</ul> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 84. NEORV32 Trap Listing</caption> +<colgroup> +<col style="width: 3.4482%;"> +<col style="width: 13.7931%;"> +<col style="width: 27.5862%;"> +<col style="width: 34.4827%;"> +<col style="width: 6.8965%;"> +<col style="width: 6.8965%;"> +<col style="width: 6.8968%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Prio.</th> +<th class="tableblock halign-left valign-top"><code>mcause</code></th> +<th class="tableblock halign-left valign-top">RTE Trap ID</th> +<th class="tableblock halign-left valign-top">Cause</th> +<th class="tableblock halign-left valign-top"><code>mepc</code></th> +<th class="tableblock halign-left valign-top"><code>mtval</code></th> +<th class="tableblock halign-left valign-top"><code>mtinst</code></th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" colspan="7"><p class="tableblock"><strong>Exceptions</strong> (<em>synchronous</em> to instruction execution)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000001</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_I_ACCESS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">instruction access fault</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000002</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_I_ILLEGAL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">illegal instruction</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_I_MISALIGNED</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">instruction address misaligned</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x0000000b</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_MENV_CALL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">environment call from M-mode</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">5</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000008</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_UENV_CALL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">environment call from U-mode</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">6</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000003</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_BREAKPOINT</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">software breakpoint / trigger firing</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000006</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_S_MISALIGNED</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">store address misaligned</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">ADR</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000004</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_L_MISALIGNED</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">load address misaligned</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">ADR</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">9</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000007</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_S_ACCESS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">store access fault</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">ADR</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">10</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000005</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_L_ACCESS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">load access fault</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">ADR</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">INS</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="7"><p class="tableblock"><strong>Interrupts</strong> (<em>asynchronous</em> to instruction execution)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000010</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_0</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">12</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000011</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">13</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000012</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_2</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 2</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">14</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000013</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_3</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 3</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">15</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000014</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_4</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 4</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000015</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_5</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 5</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">17</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000016</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_6</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 6</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">18</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000017</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_7</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 7</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">19</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000018</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_8</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 8</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">20</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000019</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_9</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 9</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">21</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x8000001a</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_10</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 10</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">22</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x8000001b</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_11</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 11</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">23</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x8000001c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_12</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 12</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">24</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x8000001d</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_13</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 13</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">25</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x8000001e</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_14</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 14</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">26</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x8000001f</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_15</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fast interrupt request channel 15</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">27</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x8000000b</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_MEI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine external interrupt (MEI)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">28</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000003</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_MSI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine software interrupt (MSI)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">29</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x80000007</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_MTI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine timer interrupt (MTI)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">I-PC</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">0</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 85. NEORV32 Trap Description</caption> +<colgroup> +<col style="width: 30%;"> +<col style="width: 70%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Trap ID [C]</th> +<th class="tableblock halign-left valign-top">Triggered when &#8230;&#8203;</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_I_ACCESS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">bus timeout, bus access error or <a href="#_smpmp_isa_extension">PMP</a> rule violation during instruction fetch</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_I_ILLEGAL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">trying to execute an invalid instruction word (malformed or not supported) or on a privilege violation</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_I_MISALIGNED</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">fetching a 32-bit instruction word that is not 32-bit-aligned (see note below)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_MENV_CALL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">executing <code>ecall</code> instruction in machine-mode</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_UENV_CALL</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">executing <code>ecall</code> instruction in user-mode</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_BREAKPOINT</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">executing <code>ebreak</code> instruction or if <a href="#_trigger_module">Trigger Module</a> fires</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_S_MISALIGNED</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">storing data to an address that is not naturally aligned to the data size (half/word)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_L_MISALIGNED</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">loading data from an address that is not naturally aligned to the data size (half/word)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_L_ACCESS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">bus timeout, bus access error or <a href="#_smpmp_isa_extension">PMP</a> rule violation during load data operation</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_S_ACCESS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">bus timeout, bus access error or <a href="#_smpmp_isa_extension">PMP</a> rule violation during store data operation</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_FIRQ_*</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">caused by interrupt-condition of <strong>processor-internal modules</strong>, see <a href="#_neorv32_specific_fast_interrupt_requests">NEORV32-Specific Fast Interrupt Requests</a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_MEI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine external interrupt (via dedicated <a href="#_processor_top_entity_signals">Processor Top Entity - Signals</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_MSI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine software interrupt (via dedicated <a href="#_processor_top_entity_signals">Processor Top Entity - Signals</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>TRAP_CODE_MTI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">machine timer interrupt (internal <a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a> or via dedicated <a href="#_processor_top_entity_signals">Processor Top Entity - Signals</a>)</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Resumable Exceptions</div> +Note that not all exceptions are resumable. For example, the "instruction access fault" exception or the "instruction +address misaligned" exception are not resumable in most cases. These exception might indicate a fatal memory hardware failure. +</td> +</tr> +</table> +</div> +</div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_software_framework">4. Software Framework</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 project comes with a complete software ecosystem called the "software framework", which +is based on the C-language RISC-V GCC port and consists of the following parts:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_compiler_toolchain">Compiler Toolchain</a></p> +</li> +<li> +<p><a href="#_core_libraries">Core Libraries</a></p> +</li> +<li> +<p><a href="#_application_makefile">Application Makefile</a></p> +</li> +<li> +<p><a href="#_executable_image_format">Executable Image Format</a></p> +<div class="ulist"> +<ul> +<li> +<p><a href="#_linker_script">Linker Script</a></p> +</li> +<li> +<p><a href="#_ram_layout">RAM Layout</a></p> +</li> +<li> +<p><a href="#_c_standard_library">C Standard Library</a></p> +</li> +<li> +<p><a href="#_start_up_code_crt0">Start-Up Code (crt0)</a></p> +</li> +</ul> +</div> +</li> +<li> +<p><a href="#_bootloader">Bootloader</a></p> +</li> +<li> +<p><a href="#_neorv32_runtime_environment">NEORV32 Runtime Environment</a></p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>A summarizing list of the most important elements of the software framework and their according +files and folders is shown below:</p> +</div> +<table class="tableblock frame-all grid-none stretch"> +<colgroup> +<col style="width: 50%;"> +<col style="width: 50%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Application start-up code</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sw/common/crt0.S</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Application linker script</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sw/common/neorv32.ld</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Core hardware driver libraries ("HAL")</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sw/lib/include/</code> &amp; <code>sw/lib/source/</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Central application makefile</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sw/common/common.mk</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Tool for generating NEORV32 executables</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sw/image_gen/</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Default bootloader</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sw/bootloader</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Example programs</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>sw/example</code></p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Software Documentation</div> +All core libraries and example programs are documented "in-code" using <strong>Doxygen</strong>. +The documentation is automatically built and deployed to GitHub pages and is available online +at <a href="https://stnolting.github.io/neorv32/sw/files.html" class="bare">https://stnolting.github.io/neorv32/sw/files.html</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Example Programs</div> +A collection of annotated example programs, which show how to use certain CPU functions +and peripheral/IO modules, can be found in <code>sw/example</code>. +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_compiler_toolchain">4.1. Compiler Toolchain</h3> +<div class="paragraph"> +<p>The toolchain for this project is based on the free and open RISC-V GCC-port. You can find the compiler sources and +build instructions on the official RISC-V GNU toolchain GitHub page: <a href="https://github.com/riscv/riscv-gnutoolchain" class="bare">https://github.com/riscv/riscv-gnutoolchain</a>.</p> +</div> +<div class="paragraph"> +<p>The NEORV32 implements a 32-bit RISC-V architecture and uses a 32-bit integer and soft-float ABI by default. +Make sure the toolchain / toolchain build is configured accordingly.</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>MARCH=rv32i</code></p> +</li> +<li> +<p><code>MABI=ilp32</code></p> +</li> +<li> +<p><code>RISCV_PREFIX=riscv32-unknown-elf-</code></p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>These default configurations can be overridden at any times using <a href="#_application_makefile">Application Makefile</a> variables.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +More information regarding the toolchain (building from scratch or downloading prebuilt ones) can be found in the +user guide section <a href="https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup">Software Toolchain Setup</a>. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_core_libraries">4.2. Core Libraries</h3> +<div class="paragraph"> +<p>The NEORV32 project provides a set of pre-defined C libraries that allow an easy integration of the processor/CPU features +(also called "HAL" - <em>hardware abstraction layer</em>). All driver and runtime-related files are located in +<code>sw/lib</code>. These library files are automatically included and linked by adding the following include statement:</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">#include &lt;neorv32.h&gt; // NEORV32 HAL, core and runtime libraries</code></pre> +</div> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 86. NEORV32 Hardware Abstraction Layer File List</caption> +<colgroup> +<col style="width: 25%;"> +<col style="width: 25%;"> +<col style="width: 50%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">C source file</th> +<th class="tableblock halign-left valign-top">C header file</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Main NEORV32 library file</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_aux.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_aux.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">General auxiliary/helper function</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cfs.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cfs.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_crc.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_crc.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_cyclic_redundancy_check_crc">Cyclic Redundancy Check (CRC)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cpu.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cpu.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_neorv32_central_processing_unit_cpu">NEORV32 Central Processing Unit (CPU)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cpu_amo.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cpu_amo.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Emulation functions for the read-modify-write <a href="#_zalrsc_isa_extension"><code>Zalrsc</code> ISA Extension</a> / <code>A</code> instructions</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cpu_csr.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_control_and_status_registers_csrs">Control and Status Registers (CSRs)</a> definitions</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cpu_cfu.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_cpu_cfu.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_dma.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_dma.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_direct_memory_access_controller_dma">Direct Memory Access Controller (DMA)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_gpio.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_gpio.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_general_purpose_input_and_output_port_gpio">General Purpose Input and Output Port (GPIO)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_gptmr.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_gptmr.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_general_purpose_timer_gptmr">General Purpose Timer (GPTMR)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_intrinsics.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Macros for intrinsics and custom instructions</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_legacy.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Legacy compatibility layer / wrappers (<strong>do not use for new designs</strong>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_mtime.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_mtime.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_neoled.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_neoled.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_smart_led_interface_neoled">Smart LED Interface (NEOLED)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_onewire.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_onewire.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_one_wire_serial_interface_controller_onewire">One-Wire Serial Interface Controller (ONEWIRE)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_pwm.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_pwm.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_pulse_width_modulation_controller_pwm">Pulse-Width Modulation Controller (PWM)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_rte.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_rte.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_neorv32_runtime_environment">NEORV32 Runtime Environment</a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_sdi.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_sdi.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_serial_data_interface_controller_sdi">Serial Data Interface Controller (SDI)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_slink.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_slink.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_stream_link_interface_slink">Stream Link Interface (SLINK)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_spi.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_spi.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_serial_peripheral_interface_controller_spi">Serial Peripheral Interface Controller (SPI)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_sysinfo.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_sysinfo.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_system_configuration_information_memory_sysinfo">System Configuration Information Memory (SYSINFO)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_trng.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_trng.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_true_random_number_generator_trng">True Random-Number Generator (TRNG)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_twi.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_twi.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_two_wire_serial_interface_controller_twi">Two-Wire Serial Interface Controller (TWI)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_uart.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_uart.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">Primary Universal Asynchronous Receiver and Transmitter (UART0)</a> and UART1 HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_wdt.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_wdt.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_watchdog_timer_wdt">Watchdog Timer (WDT)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_xip.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_xip.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_xirq.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_xirq.h</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><a href="#_external_interrupt_controller_xirq">External Interrupt Controller (XIRQ)</a> HAL</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>neorv32_newlib.c</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Platform-specific system calls for <em>newlib</em></p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Core Library Documentation</div> +The <em>doxygen</em>-based documentation of the software framework including all core libraries is available online at +<a href="https://stnolting.github.io/neorv32/sw/files.html" class="bare">https://stnolting.github.io/neorv32/sw/files.html</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">CMSIS System View Description File (SVD)</div> +A CMSIS-SVD-compatible <strong>System View Description (SVD)</strong> file including all peripherals is available in <code>sw/svd</code>. +Together with a third-party plugin the processor&#8217;s SVD file can be imported right into GDB to allow comfortable +debugging of peripheral/IO devices (see <a href="https://github.com/stnolting/neorv32/discussions/656" class="bare">https://github.com/stnolting/neorv32/discussions/656</a>). +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_application_makefile">4.3. Application Makefile</h3> +<div class="paragraph"> +<p>Application compilation is based on a single, centralized GNU makefile (<code>sw/common/common.mk</code>). Each project in the +<code>sw/example</code> folder provides a makefile that just <em>includes</em> this central makefile.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +When creating a new project, copy an existing project folder or at least the makefile to the new project folder. +It is recommended to create new projects also in <code>sw/example</code> to keep the file dependencies. However, these +dependencies can be manually configured via makefile variables if the new project is located somewhere else. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Before the makefile can be used to compile applications, the RISC-V GCC toolchain needs to be installed and +the compiler&#8217;s <code>bin</code> folder has to be added to the system&#8217;s <code>PATH</code> environment variable. More information can be +found in <a href="https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup">User Guide: Software Toolchain Setup</a>. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_makefile_targets">4.3.1. Makefile Targets</h4> +<div class="paragraph"> +<p>Just executing <code>make</code> (or executing <code>make help</code>) will show the help menu listing all available targets.</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-makefile" data-lang="makefile">$ make +NEORV32 Software Application Makefile +Find more information at https://github.com/stnolting/neorv32 + +Targets: + + help - show this text + check - check toolchain + info - show makefile/toolchain configuration + gdb - run GNU debugging session + asm - compile and generate &lt;main.asm&gt; assembly listing file for manual debugging + elf - compile and generate &lt;main.elf&gt; ELF file + exe - compile and generate &lt;neorv32_exe.bin&gt; executable image file for upload via default bootloader (binary file) + bin - compile and generate &lt;neorv32_raw_exe.bin&gt; RAW executable memory image (binary file) + hex - compile and generate &lt;neorv32_raw_exe.hex&gt; RAW executable memory image (hex char file) + coe - compile and generate &lt;neorv32_raw_exe.coe&gt; RAW executable memory image (COE file) + mem - compile and generate &lt;neorv32_raw_exe.mem&gt; RAW executable memory image (MEM file) + mif - compile and generate &lt;neorv32_raw_exe.mif&gt; RAW executable memory image (MIF file) + image - compile and generate VHDL IMEM boot image (for application, no header) in local folder + install - compile, generate and install VHDL IMEM boot image (for application, no header) + sim - in-console simulation using default/simple testbench and GHDL + hdl_lists - regenerate HDL file-lists in NEORV32_HOME/rtl + all - exe + install + hex + bin + asm + elf_info - show ELF layout info + elf_sections - show ELF sections + clean - clean up project home folder + clean_all - clean up whole project, core libraries and image generator + bl_image - compile and generate VHDL BOOTROM boot image (for bootloader only, no header) in local folder + bootloader - compile, generate and install VHDL BOOTROM boot image (for bootloader only, no header) + +Variables: + + USER_FLAGS - Custom toolchain flags [append only]: "" + USER_LIBS - Custom libraries [append only]: "" + EFFORT - Optimization level: "-Os" + MARCH - Machine architecture: "rv32i_zicsr_zifencei" + MABI - Machine binary interface: "ilp32" + APP_INC - C include folder(s) [append only]: "-I ." + ASM_INC - ASM include folder(s) [append only]: "-I ." + RISCV_PREFIX - Toolchain prefix: "riscv32-unknown-elf-" + NEORV32_HOME - NEORV32 home folder: "../../.." + GDB_ARGS - GDB (connection) arguments: "-ex target extended-remote localhost:3333" + GHDL_RUN_FLAGS - GHDL simulation run arguments: ""</code></pre> +</div> +</div> +</div> +<div class="sect3"> +<h4 id="_makefile_configuration">4.3.2. Makefile Configuration</h4> +<div class="paragraph"> +<p>The compilation flow is configured via variables right at the beginning of the central +makefile (<code>sw/common/common.mk</code>):</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Customizing Makefile Variables</div> +The makefile configuration variables can be overridden or extended directly when invoking the makefile. For +example <code>$ make MARCH=rv32ic_zicsr_zifencei clean_all exe</code> overrides the default <code>MARCH</code> variable definitions. +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="title">Listing 14. Default Makefile Configuration</div> +<div class="content"> +<pre class="highlight"><code class="language-makefile" data-lang="makefile"># ***************************************************************************** +# USER CONFIGURATION +# ***************************************************************************** +# User's application sources (*.c, *.cpp, *.s, *.S); add additional files here +APP_SRC ?= $(wildcard ./*.c) $(wildcard ./*.s) $(wildcard ./*.cpp) $(wildcard ./*.S) +# User's application include folders (don't forget the '-I' before each entry) +APP_INC ?= -I . +# User's application include folders - for assembly files only (don't forget the '-I' before each +entry) +ASM_INC ?= -I . +# Optimization +EFFORT ?= -Os +# Compiler toolchain +RISCV_PREFIX ?= riscv32-unknown-elf- +# CPU architecture and ABI +MARCH ?= rv32i_zicsr_zifencei +MABI ?= ilp32 +# User flags for additional configuration (will be added to compiler flags) +USER_FLAGS ?= +# User libraries (will be included by linker) +USER_LIBS ?= +# Language specific compiler flags: C +CFLAGS ?= +# C++ +CXXFLAGS ?= +# Assembly +ASFLAGS ?= +# Flags passed only to the linker +LDFLAGS ?= +# Relative or absolute path to the NEORV32 home folder +NEORV32_HOME ?= ../../.. +# GDB arguments +GDB_ARGS ?= -ex "target extended-remote localhost:3333" +# *****************************************************************************</code></pre> +</div> +</div> +<table class="tableblock frame-all grid-none stretch"> +<caption class="title">Table 87. Variables Description</caption> +<colgroup> +<col style="width: 20%;"> +<col style="width: 80%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>APP_SRC</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The source files of the application (<code><strong>.c</code>, <code></strong>.cpp</code>, <code><strong>.S</code> and <code></strong>.s</code> files are allowed; files of these types in the project folder are automatically added via wild cards). Additional files can be added separated by white spaces</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>APP_INC</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Include file folders; separated by white spaces; must be defined with <code>-I</code> prefix</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ASM_INC</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Include file folders that are used only for the assembly source files (<code><strong>.S</code>/<code></strong>.s</code>).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>EFFORT</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Optimization level, optimize for size (<code>-Os</code>) is default; legal values: <code>-O0</code>, <code>-O1</code>, <code>-O2</code>, <code>-O3</code>, <code>-Os</code>, <code>-Ofast</code>, &#8230;&#8203;</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>RISCV_PREFIX</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The toolchain prefix to be used; follows the triplet naming convention <code>[architecture]-[host_system]-[output]-&#8230;&#8203;</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MARCH</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The targeted RISC-V architecture/ISA</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MABI</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Application binary interface (default: 32-bit integer ABI <code>ilp32</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>USER_FLAGS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Additional flags that will be forwarded to the compiler tools</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>USER_LIBS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Additional libraries to include during linking (<code>*.a</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CFLAGS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Additional flags that will be forwarded to the C compiler</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CXXFLAGS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Additional flags that will be forwarded to the C++ compiler</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ASFLAGS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Additional flags that will be forwarded to the assembler</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>LDFLAGS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Additional flags that will be forwarded to the linker</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>NEORV32_HOME</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Relative or absolute path to the NEORV32 project home folder; adapt this if the makefile/project is not in the project&#8217;s default <code>sw/example</code> folder</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>GDB_ARGS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Default GDB arguments when running the <code>gdb</code> target</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>GHDL_RUN_FLAGS</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">GHDL run arguments (e.g. <code>--stop-time=1ms</code>)</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_default_compiler_flags">4.3.3. Default Compiler Flags</h4> +<div class="paragraph"> +<p>The following default compiler flags are used for compiling an application. These flags are defined via the +<code>CC_OPTS</code> variable.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +The makefile&#8217;s <code>CC_OPTS</code> is exported as <strong>define</strong> to be available within a C program; for example +<code>neorv32_uart0_printf("%s\n", CC_OPTS);</code>. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-none stretch"> +<colgroup> +<col style="width: 25%;"> +<col style="width: 75%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-Wall</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable all compiler warnings.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-ffunction-sections</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Put functions and data segment in independent sections. This allows a code optimization as dead code and unused data can be easily removed.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-nostartfiles</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Do not use the default start code. Instead, the NEORV32-specific start-up code (<code>sw/common/crt0.S</code>) is used (pulled-in by the linker script).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-Wl,--gc-sections</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Make the linker perform dead code elimination.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-lm</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Include/link with <code>math.h</code>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-lc</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Search for the standard C library when linking.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-lgcc</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Make sure we have no unresolved references to internal GCC library subroutines.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-mno-fdiv</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Use built-in software functions for floating-point divisions and square roots (since the according instructions are not supported yet).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-mstrict-align</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Unaligned memory accesses cannot be resolved by the hardware and require emulation.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-mbranch-cost=10</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Branching costs a lot of cycles.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-ffp-contract=off</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Do not allow contraction of floating-point operations (no fused operations as they are not supported).</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Debug Symbols</div> +By default, no debug symbols are added to the ELF. +You can add them manually (to your local project&#8217;s makefile) via <code>USER_FLAGS+=-g</code>. +Note that other debug flags may be required depending of the GCC/GDB version +(e.g. <code>USER_FLAGS += -ggdb -gdwarf-3</code>). +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_custom_compiler_flags">4.3.4. Custom (Compiler) Flags</h4> +<div class="paragraph"> +<p>Custom flags can be <em>appended</em> to the <code>USER_FLAGS</code> variable. This allows to customize the entire software framework while +calling <code>make</code> without the need to change the makefile(s) or the linker script. The following example will add debug symbols +to the executable (<code>-g</code>) and will also re-define the linker script&#8217;s <code>__neorv32_heap_size</code> variable setting the maximal heap +size to 4096 bytes (see sections <a href="#_linker_script">Linker Script</a> and <a href="#_ram_layout">RAM Layout</a>):</p> +</div> +<div class="listingblock"> +<div class="title">Listing 15. Using the <code>USER_FLAGS</code> Variable for Customization</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">$ make USER_FLAGS+="-g -Wl,--__neorv32_heap_size,__heap_size=4096" clean_all exe</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The configuration can also be made "permanent" by adapting the application&#8217;s makefile (make sure to use the +<code>override</code> command here):</p> +</div> +<div class="listingblock"> +<div class="title">Listing 16. Using the <code>USER_FLAGS</code> Variable for Permanent Customization</div> +<div class="content"> +<pre class="highlight"><code class="language-makefile" data-lang="makefile">override USER_FLAGS += "-g -Wl,--__neorv32_heap_size,__heap_size=4096"</code></pre> +</div> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_executable_image_format">4.4. Executable Image Format</h3> +<div class="paragraph"> +<p>In order to generate an executable for the processors all source files have to be compiled, linked +and packed into a final executable. This executable can be further converted into several image formats.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Memory Image Formats</div> +The NEORV32 software framework includes an <a href="#_executable_image_generator">Executable Image Generator</a> than can convert an application +into several different file formats. These include raw hex files, a proprietary format for uploading via the +default <a href="#_bootloader">Bootloader</a> as well as several standard FPGA memory initialization file types (e.g. <code><strong>.coe</code>, +<code></strong>.mem</code> and <code>*.mif</code>). These image file formats are generated by the according <a href="#_makefile_targets">Makefile Targets</a>. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_linker_script">4.4.1. Linker Script</h4> +<div class="paragraph"> +<p>After all the application sources have been compiled, they need to be <em>linked</em>. +For this purpose the makefile uses the NEORV32-specific linker script. This linker script defines several sections +for the final executable (compare with <a href="#_address_space">Address Space</a>). However, only the <code>ram</code> and <code>rom</code> sections are +relevant for the executable itself; the remaining sections are just listed for completeness.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 88. Linker script - memory sections</caption> +<colgroup> +<col style="width: 20%;"> +<col style="width: 80%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Memory section</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ram</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Data memory address space (processor-internal <a href="#_data_memory_dmem">Data Memory (DMEM)</a> and/or external memory)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>rom</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Instruction memory address space (processor-internal <a href="#_instruction_memory_imem">Instruction Memory (IMEM)</a> and/or external memory)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>xip</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address space for the <a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a> (accessing an external SPI memory)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>boot</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address space for the processor-internal <a href="#_bootloader_rom_bootrom">Bootloader ROM (BOOTROM)</a></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>io</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address space for the processor-internal IO/peripheral devices</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The <code>rom</code> section is automatically re-mapped to the processor-internal <a href="#_bootloader_rom_bootrom">Bootloader ROM (BOOTROM)</a> when compiling the +bootloader sources. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>Each section has two main attributes: <code>ORIGIN</code> and <code>LENGTH</code>. <code>ORIGIN</code> defines the base address of the according section +while <code>LENGTH</code> defines its size in bytes. For the <code>ram</code> and <code>rom</code> sections these attributes are configured indirectly +via variables that provide default values.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 17. Linker script - section configuration</div> +<div class="content"> +<pre class="highlight"><code>/* Default rom/ram (IMEM/DMEM) sizes */ +__neorv32_rom_size = DEFINED(__neorv32_rom_size) ? __neorv32_rom_size : 2048M; +__neorv32_ram_size = DEFINED(__neorv32_ram_size) ? __neorv32_ram_size : 8K; + +/* Default section base addresses */ +__neorv32_rom_base = DEFINED(__neorv32_rom_base) ? __neorv32_rom_base : 0x00000000; +__neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x80000000;</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The region size and base address configuration can be edited by the user - either by explicitly +changing the default values in the linker script or by overriding them when invoking <code>make</code>:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 18. Overriding default <code>rom</code> size configuration (configuring 4096 bytes)</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">$ make USER_FLAGS+="-Wl,--defsym,__neorv32_rom_size=4096" clean_all exe</code></pre> +</div> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<code><em>neorv32_rom_base</code> (= <code>ORIGIN</code> of the <code>rom</code> section) and <code></em>neorv32_ram_base</code> (= <code>ORIGIN</code> of the <code>ram</code> section) have to +be sync to the actual memory layout configuration of the processor (see section <a href="#_address_space">Address Space</a>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The default configuration for the <code>rom</code> section assumes a maximum of 2GB <em>logical</em> memory address space. This size does not +have to reflect the <em>actual</em> physical size of the entire instruction memory. It just provides a maximum limit. When uploading +a new executable via the bootloader, the bootloader itself checks if sufficient <em>physical</em> instruction memory is available. +If a new executable is embedded right into the internal-IMEM the synthesis tool will check, if the configured instruction memory +size is sufficient. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The linker maps all the regions from the compiled object files into five final sections: <code>.text</code>, +<code>.rodata</code>, <code>.data</code>, <code>.bss</code> and <code>.heap</code>:</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 89. Linker script - memory regions</caption> +<colgroup> +<col style="width: 10%;"> +<col style="width: 90%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Region</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>.text</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Executable instructions generated from the start-up code and all application sources.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>.rodata</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Constants (like strings) from the application; also the initial data for initialized variables.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>.data</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">This section is required for the address generation of fixed (= global) variables only.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>.bss</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">This section is required for the address generation of dynamic memory constructs only.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>.heap</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">This section is required for the address generation of dynamic memory constructs only.</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>The <code>.text</code> and <code>.rodata</code> sections are mapped to processor&#8217;s instruction memory space and the <code>.data</code>, +<code>.bss</code> and <code>heap</code> sections are mapped to the processor&#8217;s data memory space. Finally, the <code>.text</code>, <code>.rodata</code> and <code>.data</code> +sections are extracted and concatenated into a single file <code>main.bin</code>.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Section Alignment</div> +The default NEORV32 linker script aligns <em>all</em> regions so they start and end on a 32-bit (word) boundaries. The default +NEORV32 start-up code (crt0) makes use of this alignment by using word-level memory instructions to initialize the <code>.data</code> +section and to clear the <code>.bss</code> section (faster!). +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_ram_layout">4.4.2. RAM Layout</h4> +<div class="paragraph"> +<p>The default NEORV32 linker script uses all of the defined RAM (linker script memory section <code>ram</code>) to several sections. +Note that depending on the application some sections might have zero size.</p> +</div> +<div class="imageblock"> +<div class="content"> +<img src="img/ram_layout.png" alt="400"> +</div> +<div class="title">Figure 13. Default RAM Layout</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p><strong>Constant data (<code>.data</code>)</strong>: The constant data section is placed right at the beginning of the RAM. For example, this section +contains <em>explicitly initialized</em> global variables. This section is initialized by the executable.</p> +</li> +<li> +<p><strong>Dynamic data (<code>.bss</code>)</strong>: The constant data section is followed by the dynamic data section, which contains <em>uninitialized</em> data +like global variables without explicit initialization. This section is cleared by the start-up code <code>crt0.S</code>.</p> +</li> +<li> +<p><strong>Heap (<code>.heap</code>)</strong>: The heap is used for dynamic memory that is managed by functions like <code>malloc()</code> and <code>free()</code>. The heap +grows upwards. This section is not initialized at all.</p> +</li> +<li> +<p><strong>Stack</strong>: The stack starts at the very end of the RAM at address <code>ORIGIN(ram) + LENGTH(ram) - 1</code>. According to the RISC-V ABI / calling +convention the stack is 128-bit-aligned before procedure entry. The stack grows downwards.</p> +</li> +</ol> +</div> +<div class="paragraph"> +<p>There is <em>no explicit limit</em> for the maximum stack size as this is hard to check. However, a physical memory protection rule could +be used to configure a maximum size by adding a "protection area" between stack and heap (a PMP region without any access rights).</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Heap Size</div> +The maximum size of the heap is defined by the linker script&#8217;s <code><em>neorv32_heap_size</code> variable. This variable has to be +<strong>explicitly defined</strong> in order to define a heap size (and to use dynamic memory allocation at all) other than zero. The user +can define the heap size while invoking the application makefile: <code>$ USER_FLAGS+="-Wl,--defsym,</em>neorv32_heap_size=4k" make clean_all exe</code> +(defines a heap size of 4*1024 bytes). +</td> +</tr> +</table> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Heap-Stack Collisions</div> +Take care when using dynamic memory to avoid collision of the heap and stack memory areas. There is no compile-time protection +mechanism available as the actual heap and stack size are defined by <em>runtime</em> data. Also beware of fragmentation when +using dynamic memory allocation. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_c_standard_library">4.4.3. C Standard Library</h4> +<div class="paragraph"> +<p>The default software framework relies on <strong>newlib</strong> as default C standard library.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">RTOS Support</div> +The NEORV32 CPU and processor <strong>do support</strong> embedded RTOS like FreeRTOS and Zephyr. See the User guide section +<a href="https://stnolting.github.io/neorv32/ug/#_zephyr_rtos_support">Zephyr RTOS Support</a> and +<a href="https://stnolting.github.io/neorv32/ug/#_freertos_support">FreeRTOS Support</a> +for more information.<br> +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>+ +The FreeRTOS port and demo is available in a separate repository: <a href="https://github.com/stnolting/neorv32-freertos" class="bare">https://github.com/stnolting/neorv32-freertos</a></p> +</div> +<div class="paragraph"> +<p>Newlib provides stubs for common "system calls" (like file handling and standard input/output) that are used by other +C libraries like <code>stdio</code>. These stubs are available in <code>sw/source/source/syscalls.c</code> and were adapted for the NEORV32 processor.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Standard Consoles</div> +The <a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">UART0</a> +is used to implement all the standard input, output and error consoles (<code>STDIN</code>, <code>STDOUT</code> and <code>STDERR</code>). +Note that <code>\n</code> (newline) is automatically converted to <code>\r\n</code> (carriage-return and newline). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Constructors and Destructors</div> +Constructors and destructors for plain C code or for C++ applications are supported by the software framework. +See <code>sw/example/hello_cpp</code> for a minimal example. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Newlib Test/Demo Program</div> +A simple test and demo program, which uses some of newlib&#8217;s core functions (like <code>malloc</code>/<code>free</code> and <code>read</code>/<code>write</code>) +is available in <code>sw/example/demo_newlib</code> +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_executable_image_generator">4.4.4. Executable Image Generator</h4> +<div class="paragraph"> +<p>The <code>main.bin</code> file is packed by the NEORV32 image generator (<code>sw/image_gen</code>) to generate the final executable file. +The image generator can generate several types of executable file formats selected by a flag when calling the generator:</p> +</div> +<table class="tableblock frame-all grid-none stretch"> +<colgroup> +<col style="width: 20%;"> +<col style="width: 80%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-app_bin</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generates an executable binary file <code>neorv32_exe.bin</code> (including bootloader header) for uploading via the bootloader.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-app_img</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generates an executable VHDL memory initialization image for the processor-internal IMEM. This option regenerates the <code>rtl/core/neorv32_application_image.vhd</code> file.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-bld_img</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generates an executable VHDL memory initialization image for the processor-internal BOOT ROM. This option regenerates the <code>rtl/core/neorv32_bootloader_image.vhd</code> file.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-raw_hex</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generates a raw 8x ASCII hex-char file <code>neorv32_raw_exe.hex</code> for custom purpose.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-raw_bin</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generates a raw binary file <code>neorv32_raw_exe.bin</code> for custom purpose.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-raw_coe</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generates a raw COE file <code>neorv32_raw_exe.coe</code> for FPGA memory initialization.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-raw_mem</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generates a raw MEM file <code>neorv32_raw_exe.mem</code> for FPGA memory initialization.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>-raw_mif</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Generates a raw MIF file <code>neorv32_raw_exe.mif</code> for FPGA memory initialization.</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p><strong>All these options are managed by the makefile (see <a href="#_makefile_targets">Makefile Targets</a>).</strong></p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Image Generator Compilation</div> +The sources of the image generator are automatically compiled when invoking the makefile (requiring a <em>native</em> GCC installation). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Executable Header</div> +The image generator add a small header to the <code>neorv32_exe.bin</code> executable, which consists of three 32-bit words located right +at the beginning of the file. The first word of the executable is the signature word and is always <code>0x4788cafe</code>. Based on this +word the bootloader can identify a valid image file. The next word represents the size in bytes of the actual program image in +bytes. A simple "complement" checksum of the actual program image is given by the third word. This provides a simple protection +against data transmission or storage errors. <strong>Note that this executable format cannot be used for <em>direct</em> execution (e.g. via +XIP or direct memory access).</strong> +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_start_up_code_crt0">4.4.5. Start-Up Code (crt0)</h4> +<div class="paragraph"> +<p>The CPU and also the processor require a minimal start-up and initialization code to bring the CPU (and the SoC) +into a stable and initialized state and to initialize the C runtime environment before the actual application can be executed. +This start-up code is located in <code>sw/common/crt0.S</code> and is automatically linked <em>every</em> application program +and placed right before the actual application code so it gets executed right after reset.</p> +</div> +<div class="paragraph"> +<p>The <code>crt0.S</code> start-up performs the following operations:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Clear <a href="#_mstatus"><strong><code>mstatus</code></strong></a>.</p> +</li> +<li> +<p>Clear <a href="#_mie"><strong><code>mie</code></strong></a> disabling all interrupt sources.</p> +</li> +<li> +<p>Install an <a href="#_early_trap_handler">Early Trap Handler</a> to <a href="#_mtvec"><strong><code>mtvec</code></strong></a>.</p> +</li> +<li> +<p>Initialize the global pointer <code>gp</code> and the stack pointer <code>sp</code> according to the <a href="#_ram_layout">RAM Layout</a> provided by the linker script. According to the RISC-V ABI the stack pointer gets 128-bit-aligned.</p> +</li> +<li> +<p>Initialize all integer register <code>x1</code> - <code>x31</code> (only <code>x1</code> - <code>x15</code> if the <code>E</code> CPU extension is enabled).</p> +</li> +<li> +<p>Setup <code>.data</code> section to configure initialized variables.</p> +</li> +<li> +<p>Clear the <code>.bss</code> section.</p> +</li> +<li> +<p>Call all <em>constructors</em> (if there are any).</p> +</li> +<li> +<p>Call the application&#8217;s <code>main</code> function (with no arguments: <code>argc</code> = <code>argv</code> = 0).</p> +</li> +<li> +<p>If <code>main</code> returns:</p> +<div class="ulist"> +<ul> +<li> +<p>All interrupt sources are disabled by clearing <a href="#_mie"><strong><code>mie</code></strong></a>.</p> +</li> +<li> +<p>The return value of <code>main</code> is copied to the <a href="#_mscratch"><strong><code>mscratch</code></strong></a> CSR to allow inspection by the debugger.</p> +</li> +<li> +<p>Call all <em>destructors</em> (if there are any). If any destructor causes an exception the crt0&#8217;s trap handler is used for handling (= skipping) this.</p> +</li> +<li> +<p>The CPU enters sleep mode executing the <code>wfi</code> instruction in an endless loop.</p> +</li> +</ul> +</div> +</li> +</ol> +</div> +<div class="sect4"> +<h5 id="_early_trap_handler">Early Trap Handler</h5> +<div class="paragraph"> +<p>The start-up code provides a very basic trap handler for the early boot stage. This handler does nothing but trying to move +on to the next linear instruction whenever an interrupt or synchronous exception is encountered.</p> +</div> +<div class="paragraph"> +<p>This simple trap handler does not interact with the stack at all as it just uses a single register that is backup-ed +using the <a href="#_mscratch"><strong><code>mscratch</code></strong></a> CSR. Furthermore, the information if the trap-causing instruction is compressed or uncompressed +is <strong>not</strong> determined by loading the instruction from memory. Instead, the transformed instruction word is read from the +<a href="#_mtinst"><strong><code>mtinst</code></strong></a> CSRs. These two features allow the trap handler to execute with minimal latency and high robustness.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The early-trap handler should be replaced by a more capable / informative one as soon as the application software is started +(for example by using the <a href="#_neorv32_runtime_environment">NEORV32 Runtime Environment</a>). +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_bootloader">4.5. Bootloader</h3> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Pre-Built Bootloader Image</div> +This section refers to the <strong>default</strong> NEORV32 bootloader. A pre-compiled memory image for the processor-internal +<a href="#_bootloader_rom_bootrom">Bootloader ROM (BOOTROM)</a> is available in the project&#8217;s rtl folder: <code>rtl/core/neorv32_bootloader_image.vhd</code>. +This image is automatically inserted into the boot ROM when synthesizing the processor with the bootloader being +enabled. <strong>Note that the default bootloader image was compiled for a minimal <code>rv32i</code> + priv. ISA!</strong> +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The NEORV32 bootloader (<code>sw/bootloader/bootloader.c</code>) provides an optional built-in firmware that +allows to upload new application executables at <em>any time</em> without the need to re-synthesize the FPGA&#8217;s bitstream. +A UART connection is used to provide a simple text-based user interface that allows to upload executables.</p> +</div> +<div class="paragraph"> +<p>Furthermore, the bootloader provides options to store an executable to a processor-external SPI flash. +An "auto boot" feature can optionally fetch this executable right after reset if there is no user interaction +via UART. This allows to build processor setups with <em>non-volatile application storage</em> while maintaining the option +to update the application software at any timer.</p> +</div> +<div class="sect3"> +<h4 id="_bootloader_soccpu_requirements">4.5.1. Bootloader SoC/CPU Requirements</h4> +<div class="paragraph"> +<p>The bootloader requires certain CPU and SoC extensions and modules to be enabled in order to operate correctly.</p> +</div> +<table class="tableblock frame-all grid-none stretch"> +<colgroup> +<col style="width: 20%;"> +<col style="width: 80%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>REQUIRED</strong></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The bootloader is implemented only if the <code>INT_BOOTLOADER_EN</code> top generic is <code>true</code>. This will automatically select the CPU&#8217;s <a href="#_indirect_boot">Indirect Boot</a> boot configuration.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>REQUIRED</strong></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The bootloader requires the privileged architecture CPU extension (<a href="#_zicsr_isa_extension"><code>Zicsr</code> ISA Extension</a>) to be enabled.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>REQUIRED</strong></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">At least 512 bytes of data memory (processor-internal DMEM or processor-external DMEM) are required for the bootloader&#8217;s stack and global variables.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>RECOMMENDED</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">For user interaction via the <a href="#_bootloader_console">Bootloader Console</a> (like uploading executables) the primary UART (<a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">Primary Universal Asynchronous Receiver and Transmitter (UART0)</a>) is required.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>RECOMMENDED</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The default bootloader uses bit 0 of the <a href="#_general_purpose_input_and_output_port_gpio">General Purpose Input and Output Port (GPIO)</a> output port to drive a high-active "heart beat" status LED.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>RECOMMENDED</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The <a href="#_machine_system_timer_mtime">Machine System Timer (MTIME)</a> is used to control blinking of the status LED and also to automatically trigger the <a href="#_auto_boot_sequence">Auto Boot Sequence</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">OPTIONAL</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The SPI controller (<a href="#_serial_peripheral_interface_controller_spi">Serial Peripheral Interface Controller (SPI)</a>) is needed to store/load executable from external flash using the <a href="#_auto_boot_sequence">Auto Boot Sequence</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">OPTIONAL</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The XIP controller (<a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a>) is needed to boot/execute code directly from a pre-programmed SPI flash.</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_bootloader_flash_requirements">4.5.2. Bootloader Flash Requirements</h4> +<div class="paragraph"> +<p>The bootloader can access an SPI-compatible flash via the processor&#8217;s top entity SPI port. By default, the flash +chip-select line is driven by <code>spi_csn_o(0)</code> and the SPI clock uses 1/8 of the processor&#8217;s main clock as clock frequency. +The SPI flash has to support single-byte read and write operations, 24-bit addresses and at least the following standard commands:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>0x02</code>: Program page (write byte)</p> +</li> +<li> +<p><code>0x03</code>: Read data (byte)</p> +</li> +<li> +<p><code>0x04</code>: Write disable (for volatile status register)</p> +</li> +<li> +<p><code>0x05</code>: Read (first) status register</p> +</li> +<li> +<p><code>0x06</code>: Write enable (for volatile status register)</p> +</li> +<li> +<p><code>0xAB</code>: Wake-up from sleep mode (optional)</p> +</li> +<li> +<p><code>0xD8</code>: Block erase (64kB)</p> +</li> +</ul> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Custom Configuration</div> +Most properties (like chip select line, flash address width, SPI clock frequency, &#8230;&#8203;) of the default bootloader can be reconfigured +without the need to change the source code. Custom configuration can be made using command line switches (defines) when recompiling +the bootloader. See the User Guide <a href="https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader" class="bare">https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader</a> for more information. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_bootloader_console">4.5.3. Bootloader Console</h4> +<div class="paragraph"> +<p>To interact with the bootloader, connect the primary UART (UART0) signals (<code>uart0_txd_o</code> and <code>uart0_rxd_o</code>) of the processor&#8217;s top +entity via a serial port (-adapter) to your computer (hardware flow control is not used so the according interface signals can be +ignored), configure your terminal program using the following settings and perform a reset of the processor.</p> +</div> +<div class="paragraph"> +<p>Terminal console settings (<code>19200-8-N-1</code>):</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>19200 Baud</p> +</li> +<li> +<p>8 data bits</p> +</li> +<li> +<p>no parity bit</p> +</li> +<li> +<p>1 stop bit</p> +</li> +<li> +<p>newline on <code>\r\n</code> (carriage return, newline)</p> +</li> +<li> +<p>no transfer protocol / control flow protocol - just raw bytes</p> +</li> +</ul> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Terminal Program</div> +Any terminal program that can connect to a serial port should work. However, make sure the program +can transfer data in <em>raw</em> byte mode without any protocol overhead (e.g. XMODEM). Some terminal programs struggle with +transmitting files larger than 4kB (see <a href="https://github.com/stnolting/neorv32/pull/215" class="bare">https://github.com/stnolting/neorv32/pull/215</a>). Try a different terminal program +if uploading of a binary does not work. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The bootloader uses the LSB of the top entity&#8217;s <code>gpio_o</code> output port as high-active status LED. All other +output pins are set to low level and won&#8217;t be altered. After reset, the status LED will start blinking at 2Hz and the +following intro screen shows up:</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code>&lt;&lt; NEORV32 Bootloader &gt;&gt; + +BLDV: Mar 7 2023 +HWV: 0x01080107 +CLK: 0x05f5e100 +MISA: 0x40901106 +XISA: 0xc0000fab +SOC: 0xffff402f +IMEM: 0x00008000 +DMEM: 0x00002000 + +Autoboot in 10s. Press any key to abort.</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The start-up screen gives some brief information about the bootloader and several system configuration parameters:</p> +</div> +<table class="tableblock frame-all grid-none stretch"> +<colgroup> +<col style="width: 11.7647%;"> +<col style="width: 88.2353%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>BLDV</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Bootloader version (built date).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>HWV</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Processor hardware version (the <a href="#_mimpid"><strong><code>mimpid</code></strong></a> CSR); in BCD format; example: <code>0x01040606</code> = v1.4.6.6).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>CLK</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Processor clock speed in Hz (via the <code>CLK</code> register from the <a href="#_system_configuration_information_memory_sysinfo">System Configuration Information Memory (SYSINFO)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>MISA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">RISC-V CPU extensions (<a href="#_misa"><strong><code>misa</code></strong></a> CSR).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XISA</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">NEORV32-specific CPU extensions (<a href="#_mxisa"><strong><code>mxisa</code></strong></a> CSR).</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SOC</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Processor configuration (via the <code>SOC</code> register from the <a href="#_system_configuration_information_memory_sysinfo">System Configuration Information Memory (SYSINFO)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>IMEM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Internal IMEM size in byte (via the <code>MEM</code> register from the <a href="#_system_configuration_information_memory_sysinfo">System Configuration Information Memory (SYSINFO)</a>.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>DMEM</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Internal DMEM size in byte (via the <code>MEM</code> register from the <a href="#_system_configuration_information_memory_sysinfo">System Configuration Information Memory (SYSINFO)</a>.</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>Now you have 10 seconds to press <em>any</em> key. Otherwise, the bootloader starts the <a href="#_auto_boot_sequence">Auto Boot Sequence</a>. When +you press any key within the 10 seconds, the actual bootloader user console starts:</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code>&lt;&lt; NEORV32 Bootloader &gt;&gt; + +BLDV: Mar 7 2023 +HWV: 0x01080107 +CLK: 0x05f5e100 +MISA: 0x40901106 +XISA: 0xc0000fab +SOC: 0xffff402f +IMEM: 0x00008000 +DMEM: 0x00002000 + +Autoboot in 10s. Press any key to abort. <i class="conum" data-value="1"></i><b>(1)</b> +Aborted. + +Available CMDs: + h: Help + r: Restart + u: Upload + s: Store to flash + l: Load from flash + x: Boot from flash (XIP) + e: Execute +CMD:&gt;</code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td>Auto boot sequence aborted due to user console input.</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The auto boot countdown is stopped and the bootloader&#8217;s user console is ready to receive one of the following commands:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>h</code>: Show the help text (again)</p> +</li> +<li> +<p><code>r</code>: Restart the bootloader and the auto-boot sequence</p> +</li> +<li> +<p><code>u</code>: Upload new program executable (<code>neorv32_exe.bin</code>) via UART into the instruction memory</p> +</li> +<li> +<p><code>s</code>: Store executable to SPI flash at <code>spi_csn_o(0)</code> (little-endian byte order)</p> +</li> +<li> +<p><code>l</code>: Load executable from SPI flash at <code>spi_csn_o(0)</code> (little-endian byte order)</p> +</li> +<li> +<p><code>x</code>: Boot program directly from flash via XIP (requires a pre-programmed image)</p> +</li> +<li> +<p><code>e</code>: Start the application, which is currently stored in the instruction memory (IMEM)</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>A new executable can be uploaded via UART by executing the <code>u</code> command. After that, the executable can be directly +executed via the <code>e</code> command. To store the recently uploaded executable to an attached SPI flash press <code>s</code>. To +directly load an executable from the SPI flash press <code>l</code>. The bootloader and the auto-boot sequence can be +manually restarted via the <code>r</code> command.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Executable Upload</div> +Make sure to upload the NEORV32 executable <code>neorv32_exe.bin</code>. Uploading any other file (like <code>main.bin</code>) +will cause an <code>ERR_EXE</code> bootloader error (see <a href="#_bootloader_error_codes">Bootloader Error Codes</a>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Booting via XIP</div> +The bootloader allows to execute an application right from flash using the <a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a> module. +This requires a pre-programmed flash. The bootloader&#8217;s "store" option can <strong>not</strong> be used to program an XIP image. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">SPI Flash Power Down Mode</div> +The bootloader will issue a "wake-up" command prior to using the SPI flash to ensure it is not +in sleep mode / power-down mode (see <a href="https://github.com/stnolting/neorv32/pull/552" class="bare">https://github.com/stnolting/neorv32/pull/552</a>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Default Configuration</div> +More information regarding the default SPI, GPIO, XIP, etc. configuration can be found in the User Guide +section <a href="https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader" class="bare">https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader</a>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">SPI Flash Programming</div> +For detailed information on using an SPI flash for application storage see User Guide section +<a href="https://stnolting.github.io/neorv32/ug/#_programming_an_external_spi_flash_via_the_bootloader">Programming an External SPI Flash via the Bootloader</a>. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_auto_boot_sequence">4.5.4. Auto Boot Sequence</h4> +<div class="paragraph"> +<p>When you reset the NEORV32 processor, the bootloader waits 8 seconds for a UART console input before it +starts the automatic boot sequence. This sequence tries to fetch a valid boot image from the external SPI +flash, connected to SPI chip select <code>spi_csn_o(0)</code>. If a valid boot image is found that can be successfully +transferred into the instruction memory, it is automatically started. If no SPI flash is detected or if there +is no valid boot image found, and error code will be shown.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_bootloader_error_codes">4.5.5. Bootloader Error Codes</h4> +<div class="paragraph"> +<p>If something goes wrong during bootloader operation an error code and a short message is shown. In this case the processor +is halted (entering <a href="#_sleep_mode">Sleep Mode</a>), the bootloader status LED is permanently activated and the processor has to be reset manually.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +In many cases the error source is just <em>temporary</em> (like some HF spike during an UART upload). Just try again. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<colgroup> +<col style="width: 20%;"> +<col style="width: 80%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong><code>ERR_EXE</code></strong></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">If you try to transfer an invalid executable (via UART or from the external SPI flash), this error message shows up. There might be a transfer protocol configuration error in the terminal program or maybe just the wrong file was selected. Also, if no SPI flash was found during an auto-boot attempt, this message will be displayed.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong><code>ERR_SIZE</code></strong></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Your program is way too big for the internal processorโ€™s instructions memory. Increase the memory size or reduce your application code.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong><code>ERR_CHKS</code></strong></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">This indicates a checksum error. Something went wrong during the transfer of the program image (upload via UART or loading from the external SPI flash). If the error was caused by a UART upload, just try it again. When the error was generated during a flash access, the stored image might be corrupted.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong><code>ERR_FLSH</code></strong></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">This error occurs if the attached SPI flash cannot be accessed. Make sure you have the right type of flash and that it is properly connected to the NEORV32 SPI port using chip select #0.</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong><code>ERR_EXC</code></strong></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The bootloader encountered an unexpected exception during operation. This might be caused when it tries to access peripherals that were not implemented during synthesis. Example: executing commands <code>l</code> or <code>s</code> (SPI flash operations) without the SPI module being implemented.</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +If an unexpected exception has been raised, the bootloader prints hexadecimal debug information showing +the <a href="#_mcause"><strong><code>mcause</code></strong></a>, <a href="#_mepc"><strong><code>mepc</code></strong></a> and <a href="#_mtval"><strong><code>mtval</code></strong></a> CSR values. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect2"> +<h3 id="_neorv32_runtime_environment">4.6. NEORV32 Runtime Environment</h3> +<div class="paragraph"> +<p>The NEORV32 software framework provides a minimal <strong>runtime environment</strong> (abbreviated "RTE") that takes care of a stable +and <em>safe</em> execution environment by handling <em>all</em> traps (exceptions &amp; interrupts). The RTE simplifies trap handling +by wrapping the CPU&#8217;s privileged architecture (i.e. trap-related CSRs) into a unified software API.</p> +</div> +<div class="paragraph"> +<p>Once initialized, the RTE provides <a href="#_default_rte_trap_handlers">Default RTE Trap Handlers</a> that catch all possible traps. These +default handlers just output a message via UART to inform the user when a certain trap has been triggered. The +default handlers can be overridden by the application code to install application-specific handler functions for each trap.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Using the RTE is <strong>optional but highly recommended</strong>. The RTE provides a simple and comfortable way of delegating +traps to application-specific handlers while making sure that all traps (even though they are not explicitly used +by the application) are handled correctly. Performance-optimized applications or embedded operating systems may +not use the RTE at all in order to increase response time. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_rte_operation">4.6.1. RTE Operation</h4> +<div class="paragraph"> +<p>The RTE manages the trap-related CSRs of the CPU&#8217;s privileged architecture (<a href="#_machine_trap_handling_csrs">Machine Trap Handling CSRs</a>). +It initializes the <a href="#_mtvec"><strong><code>mtvec</code></strong></a> CSR in DIRECT mode, which then provides the base entry point for <em>all</em> traps. The address +stored to this register defines the address of the <strong>first-level trap handler</strong>, which is provided by the +NEORV32 RTE. Whenever an exception or interrupt is triggered this first-level trap handler is executed.</p> +</div> +<div class="paragraph"> +<p>The first-level handler performs a complete context save, analyzes the source of the trap and +calls the according <strong>second-level trap handler</strong>, which takes care of the actual exception/interrupt +handling. The RTE manages a private look-up table to store the addresses of the according second-level trap handlers.</p> +</div> +<div class="paragraph"> +<p>After the initial RTE setup, each entry in the RTE&#8217;s trap handler look-up table is initialized with a +<a href="#_default_rte_trap_handlers">Default RTE Trap Handlers</a>. These default handler do not execute any trap-related operations - they +just output a message via the <strong>primary UART (UART0)</strong> to inform the user that a trap has occurred, which is not (yet) +handled by the actual application. After sending this message, the RTE tries to continue executing the actual program +by resolving the trap cause.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_using_the_rte">4.6.2. Using the RTE</h4> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +All provided RTE functions can be called only from machine-mode code. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The NEORV32 is part of the default NEORV32 software framework. However, it has to explicitly enabled by calling +the RTE&#8217;s setup function:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 19. RTE Setup (Function Prototype)</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">void neorv32_rte_setup(void);</code></pre> +</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The RTE should be enabled right at the beginning of the application&#8217;s <code>main</code> function. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +It is recommended to not use the <a href="#_mscratch"><strong><code>mscratch</code></strong></a> CSR when using the RTE as this register is used to provide services +for <a href="#_application_context_handling">Application Context Handling</a> (i.e. modifying the registers of application code that caused a trap). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>As mentioned above, all traps will just trigger execution of the RTE&#8217;s <a href="#_default_rte_trap_handlers">Default RTE Trap Handlers</a> at first. +To use application-specific handlers, which actually "handle" a trap, the default handlers can be overridden +by installing user-defined ones:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 20. Installing an Application-Specific Trap Handler (Function Prototype)</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">int neorv32_rte_handler_install(uint8_t id, void (*handler)(void));</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The first argument <code>id</code> defines the "trap ID" (for example a certain interrupt request) that shall be handled +by the user-defined handler. These IDs are defined in <code>sw/lib/include/neorv32_rte.h</code>:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 21. RTE Trap Identifiers (cut-out)</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">enum NEORV32_RTE_TRAP_enum { + RTE_TRAP_I_MISALIGNED = 0, /**&lt; Instruction address misaligned */ + RTE_TRAP_I_ACCESS = 1, /**&lt; Instruction (bus) access fault */ + RTE_TRAP_I_ILLEGAL = 2, /**&lt; Illegal instruction */ + RTE_TRAP_BREAKPOINT = 3, /**&lt; Breakpoint (EBREAK instruction) */ + RTE_TRAP_L_MISALIGNED = 4, /**&lt; Load address misaligned */ + RTE_TRAP_L_ACCESS = 5, /**&lt; Load (bus) access fault */ + RTE_TRAP_S_MISALIGNED = 6, /**&lt; Store address misaligned */ + RTE_TRAP_S_ACCESS = 7, /**&lt; Store (bus) access fault */ + RTE_TRAP_UENV_CALL = 8, /**&lt; Environment call from user mode (ECALL instruction) */ + RTE_TRAP_MENV_CALL = 9, /**&lt; Environment call from machine mode (ECALL instruction) */ + RTE_TRAP_MSI = 10, /**&lt; Machine software interrupt */ + RTE_TRAP_MTI = 11, /**&lt; Machine timer interrupt */ + RTE_TRAP_MEI = 12, /**&lt; Machine external interrupt */ + RTE_TRAP_FIRQ_0 = 13, /**&lt; Fast interrupt channel 0 */ + RTE_TRAP_FIRQ_1 = 14, /**&lt; Fast interrupt channel 1 */ + RTE_TRAP_FIRQ_2 = 15, /**&lt; Fast interrupt channel 2 */ + RTE_TRAP_FIRQ_3 = 16, /**&lt; Fast interrupt channel 3 */ + RTE_TRAP_FIRQ_4 = 17, /**&lt; Fast interrupt channel 4 */ + RTE_TRAP_FIRQ_5 = 18, /**&lt; Fast interrupt channel 5 */ + RTE_TRAP_FIRQ_6 = 19, /**&lt; Fast interrupt channel 6 */ + RTE_TRAP_FIRQ_7 = 20, /**&lt; Fast interrupt channel 7 */ + RTE_TRAP_FIRQ_8 = 21, /**&lt; Fast interrupt channel 8 */ + RTE_TRAP_FIRQ_9 = 22, /**&lt; Fast interrupt channel 9 */ + RTE_TRAP_FIRQ_10 = 23, /**&lt; Fast interrupt channel 10 */ + RTE_TRAP_FIRQ_11 = 24, /**&lt; Fast interrupt channel 11 */ + RTE_TRAP_FIRQ_12 = 25, /**&lt; Fast interrupt channel 12 */ + RTE_TRAP_FIRQ_13 = 26, /**&lt; Fast interrupt channel 13 */ + RTE_TRAP_FIRQ_14 = 27, /**&lt; Fast interrupt channel 14 */ + RTE_TRAP_FIRQ_15 = 28 /**&lt; Fast interrupt channel 15 */</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The second argument <code>*handler</code> is the actual function that implements the user-defined trap handler. +The custom handler functions need to have a specific format without any arguments and with no return value:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 22. Custom Trap Handler (Function Prototype)</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">void custom_trap_handler_xyz(void) { + + // handle trap... +}</code></pre> +</div> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Custom Trap Handler Attributes</div> +Do <strong>NOT</strong> use the <code>interrupt</code> attribute for the application trap handler functions! This +will place a <code>mret</code> instruction to the end of it making it impossible to return to the first-level +trap handler of the RTE core, which will cause stack corruption. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The following example shows how to install a custom handler (<code>custom_mtime_irq_handler</code>) for handling +the RISC-V machine timer (MTIME) interrupt:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 23. Installing a MTIME IRQ Handler</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">neorv32_rte_handler_install(RTE_TRAP_MTI, custom_mtime_irq_handler);</code></pre> +</div> +</div> +<div class="paragraph"> +<p>User-defined trap handlers can also be un-installed. This will remove the users trap handler from the RTE core +and will re-install the <a href="#_default_rte_trap_handlers">Default RTE Trap Handlers</a> for the specific trap.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 24. Function Prototype: Installing an Application-Specific Trap Handler</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">int neorv32_rte_handler_uninstall(uint8_t id);</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The argument <code>id</code> defines the identifier of the according trap that shall be un-installed. +The following example shows how to un-install the custom handler <code>custom_mtime_irq_handler</code> from the +RISC-V machine timer (MTIME) interrupt:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 25. Example: Removing the Custom MTIME IRQ Handler</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">neorv32_rte_handler_uninstall(RTE_TRAP_MTI);</code></pre> +</div> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +The current RTE configuration can be printed via UART0 via the <code>neorv32_rte_info</code> function. +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_default_rte_trap_handlers">4.6.3. Default RTE Trap Handlers</h4> +<div class="paragraph"> +<p>The default RTE trap handlers are executed when a certain trap is triggered that is not (yet) handled by an +application-defined trap handler. The default handler will output a message giving additional debug information +via the <a href="#_primary_universal_asynchronous_receiver_and_transmitter_uart0">Primary Universal Asynchronous Receiver and Transmitter (UART0)</a> to inform the user and it will also +try to resume normal program execution. Some exemplary RTE outputs are shown below.</p> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Continuing Execution</div> +In most cases the RTE can successfully continue operation - for example if it catches an <strong>interrupt</strong> request +that is not handled by the actual application program. However, if the RTE catches an un-handled <strong>trap</strong> like +a bus access fault exception continuing execution will most likely fail making the CPU crash. Some exceptions +cannot be resolved by the default debug trap handlers and will halt the CPU (see example below). +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="title">Listing 26. RTE Default Trap Handler Output Examples</div> +<div class="content"> +<pre class="highlight"><code>&lt;NEORV32-RTE&gt; [M] Illegal instruction @ PC=0x000002d6, MTINST=0x000000FF, MTVAL=0x00000000 &lt;/NEORV32-RTE&gt; <i class="conum" data-value="1"></i><b>(1)</b> +&lt;NEORV32-RTE&gt; [U] Illegal instruction @ PC=0x00000302, MTINST=0x00000000, MTVAL=0x00000000 &lt;/NEORV32-RTE&gt; <i class="conum" data-value="2"></i><b>(2)</b> +&lt;NEORV32-RTE&gt; [U] Load address misaligned @ PC=0x00000440, MTINST=0x01052603, MTVAL=0x80000101 &lt;/NEORV32-RTE&gt; <i class="conum" data-value="3"></i><b>(3)</b> +&lt;NEORV32-RTE&gt; [M] Fast IRQ 0x00000003 @ PC=0x00000820, MTINST=0x00000000, MTVAL=0x00000000 &lt;/NEORV32-RTE&gt; <i class="conum" data-value="4"></i><b>(4)</b> +&lt;NEORV32-RTE&gt; [M] Instruction access fault @ PC=0x90000000, MTINST=0x42078b63, MTVAL=0x00000000 !!FATAL EXCEPTION!! Halting CPU. &lt;/NEORV32-RTE&gt;\n <i class="conum" data-value="5"></i><b>(5)</b></code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td>Illegal 32-bit instruction <code>MTINST=0x000000FF</code> at address <code>PC=0x000002d6</code> while the CPU was in machine-mode (<code>[M]</code>).</td> +</tr> +<tr> +<td><i class="conum" data-value="2"></i><b>2</b></td> +<td>Illegal 16-bit instruction <code>MTINST=0x00000000</code> at address <code>PC=0x00000302</code> while the CPU was in user-mode (<code>[U]</code>).</td> +</tr> +<tr> +<td><i class="conum" data-value="3"></i><b>3</b></td> +<td>Misaligned load access at address <code>PC=0x00000440</code> caused by instruction <code>MTINST=0x01052603</code> (trying to load a full 32-bit word from address <code>MTVAL=0x80000101</code>) while the CPU was in machine-mode (<code>[U]</code>).</td> +</tr> +<tr> +<td><i class="conum" data-value="4"></i><b>4</b></td> +<td>Fast interrupt request from channel 3 before executing instruction at address <code>PC=0x00000820</code> while the CPU was in machine-mode (<code>[M]</code>).</td> +</tr> +<tr> +<td><i class="conum" data-value="5"></i><b>5</b></td> +<td>Instruction bus access fault at address <code>PC=0x90000000</code> while executing instruction <code>MTINST=0x42078b63</code> - this is fatal for the default debug trap handler while the CPU was in machine-mode (<code>[M]</code>).</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The specific message right at the beginning of the debug trap handler message corresponds to the trap code +obtained from the <a href="#_mcause"><strong><code>mcause</code></strong></a> CSR (see <a href="#_neorv32_trap_listing">NEORV32 Trap Listing</a>). A full list of all messages and the according +<code>mcause</code> trap codes is shown below.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 90. RTE Default Trap Handler Messages and According <code>mcause</code> Values</caption> +<colgroup> +<col style="width: 50%;"> +<col style="width: 50%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Trap identifier</th> +<th class="tableblock halign-center valign-top">According <code>mcause</code> CSR value</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Instruction address misaligned"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Instruction access fault"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000001</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Illegal instruction"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000002</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Breakpoint"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000003</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Load address misaligned"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000004</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Load access fault"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000005</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Store address misaligned"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000006</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Store access fault"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000007</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Environment call from U-mode"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000008</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Environment call from M-mode"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x0000000b</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Machine software IRQ"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000003</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Machine timer IRQ"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000007</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Machine external IRQ"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x8000000b</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000000"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000010</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000001"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000011</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000002"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000012</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000003"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000013</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000004"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000014</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000005"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000015</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000006"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000016</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000007"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000017</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000008"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000018</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x00000009"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000019</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x0000000a"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x8000001a</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x0000000b"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x8000001b</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x0000000c"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x8000001c</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x0000000d"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x8000001d</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x0000000e"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x8000001e</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Fast IRQ 0x0000000f"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x8000001f</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">"Unknown trap cause"</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">undefined</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect3"> +<h4 id="_application_context_handling">4.6.4. Application Context Handling</h4> +<div class="paragraph"> +<p>Upon trap entry the RTE backups the <em>entire</em> application context (i.e. all <code>x</code> general purpose registers) +to the stack. The context is restored automatically after trap completion. The base address of the according +stack frame is copied to the <a href="#_mscratch"><strong><code>mscratch</code></strong></a> CSR. By having this information available, the RTE provides dedicated +functions for accessing and <em>altering</em> the application context:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 27. Context Access Functions</div> +<div class="content"> +<pre class="highlight"><code class="language-c" data-lang="c">// Prototypes +uint32_t neorv32_rte_context_get(int x); // read register x +void neorv32_rte_context_put(int x, uint32_t data); write data to register x + +// Examples +uint32_t tmp = neorv32_rte_context_get(9); // read register 'x9' +neorv32_rte_context_put(28, tmp); // write 'tmp' to register 'x28'</code></pre> +</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">RISC-V <code>E</code> Extension</div> +Registers <code>x16..x31</code> are not available if the RISC-V <a href="#_e_isa_extension"><code>E</code> ISA Extension</a> is enabled. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The context access functions can be used by application-specific trap handlers to emulate unsupported +CPU / SoC features like unimplemented IO modules, unsupported instructions and even unaligned memory accesses.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Demo Program: Emulate Unaligned Memory Access</div> +A demo program, which showcases how to emulate unaligned memory accesses using the NEORV32 runtime environment +can be found in <code>sw/example/demo_emulate_unaligned</code>. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_on_chip_debugger_ocd">5. On-Chip Debugger (OCD)</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 Processor features an <em>on-chip debugger</em> (OCD) implementing the <strong>execution-based debugging</strong> scheme +compatible to the <strong>Minimal RISC-V Debug Specification</strong>. A copy of the specification is +available in <code>docs/references</code>.</p> +</div> +<div class="paragraph"> +<p><strong>Key Features</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>standard JTAG access port</p> +</li> +<li> +<p>full control of the CPU: halting, single-stepping and resuming</p> +</li> +<li> +<p>indirect access to all core registers (via program buffer)</p> +</li> +<li> +<p>indirect access to the whole processor address space (via program buffer)</p> +</li> +<li> +<p>trigger module for hardware breakpoints</p> +</li> +<li> +<p>compatible with upstream OpenOCD and GDB</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>Section Structure</strong></p> +</div> +<div class="paragraph"> +<p>This chapter is separated into four sections:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_debug_transport_module_dtm">Debug Transport Module (DTM)</a></p> +</li> +<li> +<p><a href="#_debug_module_dm">Debug Module (DM)</a></p> +</li> +<li> +<p><a href="#_cpu_debug_mode">CPU Debug Mode</a></p> +</li> +<li> +<p><a href="#_trigger_module">Trigger Module</a></p> +</li> +</ul> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">GDB + SVD</div> +Together with a third-party plugin the processor&#8217;s SVD file can be imported right into GDB to allow comfortable +debugging of peripheral/IO devices (see <a href="https://github.com/stnolting/neorv32/discussions/656" class="bare">https://github.com/stnolting/neorv32/discussions/656</a>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Hands-On Tutorial</div> +A simple example on how to use NEORV32 on-chip debugger in combination with OpenOCD and the GNU debugger is shown in +section <a href="https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger">Debugging using the On-Chip Debugger</a> +of the User Guide. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The NEORV32 on-chip debugger is based on four hardware modules:</p> +</div> +<div class="imageblock text-center"> +<div class="content"> +<img src="img/neorv32_ocd_complex.png" alt="neorv32 ocd complex"> +</div> +<div class="title">Figure 14. NEORV32 on-chip debugger complex</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p><a href="#_debug_transport_module_dtm">Debug Transport Module (DTM)</a> (<code>rtl/core/neorv32_debug_dtm.vhd</code>): JTAG access tap to allow an external +adapter to interface with the <em>debug module (DM)</em> using the <em>debug module interface (dmi)</em>.</p> +</li> +<li> +<p><a href="#_debug_module_dm">Debug Module (DM)</a> (<code>rtl/core/neorv32_debug_tm.vhd</code>): RISC-V debug module that is configured by the DTM via the dmi. +From the CPU&#8217;s "point of view" this module behaves as another memory-mapped peripheral that can be accessed via the +processor-internal bus. The memory-mapped registers provide an internal <em>data buffer</em> for data transfer from/to the DM, a +<em>code ROM</em> containing the "park loop" code, a <em>program buffer</em> to allow the debugger to execute small programs defined by the +DM and a <em>status register</em> that is used to communicate <em>exception</em>, <em>halt</em>, <em>resume</em> and <em>execute</em> requests/acknowledges from/to the DM.</p> +</li> +<li> +<p><a href="#_cpu_debug_mode">CPU Debug Mode</a> extension (part of <code>rtl/core/neorv32_cpu_control.vhd</code>): This extension provides the "debug execution mode" +as another operation mode, which is used to execute the park loop code from the DM. This mode also provides additional CSRs and instructions.</p> +</li> +<li> +<p>CPU <a href="#_trigger_module">Trigger Module</a> (also part of <code>rtl/core/neorv32_cpu_control.vhd</code>): This module provides a single <em>hardware</em> breakpoint.</p> +</li> +</ol> +</div> +<div class="paragraph"> +<p><strong>Theory of Operation</strong></p> +</div> +<div class="paragraph"> +<p>When debugging the system using the OCD, the debugger issues a halt request to the CPU (via the CPU&#8217;s +<code>db_halt_req_i</code> signal) to make the CPU enter <em>debug mode</em>. In this mode, the application-defined architectural +state of the system/CPU is "frozen" so the debugger can monitor if without interfering with the actual application. +However, the OCD can also modify the entire architectural state at any time. While in debug mode, the debugger has +full control over the entire CPU and processor operating at highest-privileged mode.</p> +</div> +<div class="paragraph"> +<p>While in debug mode, the CPU executes the "park loop" code from the code ROM of the debug module (DM). +This park loop implements an endless loop, where the CPU polls a memory-mapped <a href="#_status_register">Status Register</a> that is +controlled by the DM. The flags in this register are used to communicate requests from +the DM and to acknowledge them by the CPU: trigger execution of the program buffer or resume the halted +application. Furthermore, the CPU uses this register to signal that the CPU has halted after a halt request +and to signal that an exception has been triggered while being in debug mode.</p> +</div> +<div style="page-break-after: always;"></div> +<div class="sect2"> +<h3 id="_debug_transport_module_dtm">5.1. Debug Transport Module (DTM)</h3> +<div class="paragraph"> +<p>The debug transport module "DTM" (VHDL module: <code>rtl/core/neorv32_debug_dtm.vhd</code>) provides a JTAG test access port ("tap"). +External JTAG access is provided by the following top-level ports:</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 91. JTAG top level signals</caption> +<colgroup> +<col style="width: 14.2857%;"> +<col style="width: 14.2857%;"> +<col style="width: 14.2857%;"> +<col style="width: 57.1429%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Name</th> +<th class="tableblock halign-center valign-top">Width</th> +<th class="tableblock halign-center valign-top">Direction</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>jtag_tck_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial clock</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>jtag_tdi_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data input</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>jtag_tdo_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">out</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">serial data output</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>jtag_tms_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">in</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">mode select</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Maximum JTAG Clock</div> +All JTAG signals are synchronized to the processor&#8217;s clock domain. Hence, no additional clock domain is required for the DTM. +However, this constraints the maximal JTAG clock frequency (<code>jtag_tck_i</code>) to be less than or equal to <strong>1/5</strong> of the processor +clock frequency (<code>clk_i</code>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">JTAG TAP Reset</div> +The NEORV32 JTAG TAP does not provide a dedicated reset signal ("TRST"). However, the missing TRST is not a problem, +since JTAG-level resets can be triggered using with TMS signaling. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Maintaining JTAG Chain</div> +If the on-chip debugger is disabled the JTAG serial input <code>jtag_tdi_i</code> is directly +connected to the JTAG serial output <code>jtag_tdo_o</code> to maintain the JTAG chain. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>JTAG accesses are based on a single <em>instruction register</em> <code>IR</code>, which is 5 bit wide, and several <em>data registers</em> <code>DR</code> +with different sizes. The individual data registers are accessed by writing the according address to the instruction +register. The following table shows the available data registers and their addresses:</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 92. JTAG TAP registers</caption> +<colgroup> +<col style="width: 14.2857%;"> +<col style="width: 14.2857%;"> +<col style="width: 14.2857%;"> +<col style="width: 57.1429%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Address (via <code>IR</code>)</th> +<th class="tableblock halign-center valign-top">Name</th> +<th class="tableblock halign-center valign-top">Size (bits)</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>00001</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>IDCODE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">identifier, version and part ID fields are hardwired to zero, manufacturer ID is assigned via the <code>JEDEC_ID</code> top generic (<a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>10000</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>DTMCS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">32</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">debug transport module control and status register</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>10001</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>DMI</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">41</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">debug module interface (<em>dmi</em>); 7-bit address, 32-bit read/write data, 2-bit operation (<code>00</code> = NOP; <code>10</code> = write; <code>01</code> = read)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">others</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>BYPASS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">default JTAG bypass register</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 93. <code>DTMCS</code> - DTM Control and Status Register</caption> +<colgroup> +<col style="width: 14.2857%;"> +<col style="width: 21.4285%;"> +<col style="width: 7.1428%;"> +<col style="width: 57.143%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit(s)</th> +<th class="tableblock halign-center valign-top">Name</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:18</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">17</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dmihardreset</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">setting this bit will reset the debug module interface; this bit auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dmireset</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">setting this bit will clear the sticky error state; this bit auto-clears</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><em>reserved</em>, hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">14:12</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>idle</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">recommended idle states (= 0, no idle states required)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11:10</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dmistat</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">DMI status: <code>00</code> = no error, <code>01</code> = reserved, <code>10</code> = operation failed, <code>11</code> = failed operation during pending DMI operation</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">9:4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>abits</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">number of address bits in <code>DMI</code> register (= 6)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>version</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0001</code> = DTM is compatible to spec. versions v0.13 and v1.0</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_debug_module_dm">5.2. Debug Module (DM)</h3> +<div class="paragraph"> +<p>The debug module "DM" (VHDL module: <code>rtl/core/neorv32_debug_dm.vhd</code>) acts as a translation interface between abstract +operations issued by the debugger application (like GDB) and the platform-specific debugger hardware. +It supports the following features:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Gives the debugger necessary information about the implementation.</p> +</li> +<li> +<p>Allows the hart to be halted/resumed/reset and provides the current status.</p> +</li> +<li> +<p>Provides abstract read and write access to the halted hart&#8217;s generap purpose registers.</p> +</li> +<li> +<p>Provides access to a reset signal that allows debugging from the very first instruction after reset.</p> +</li> +<li> +<p>Provides a <em>Program Buffer</em> to force the hart to execute arbitrary instructions.</p> +</li> +<li> +<p>Allows memory access from a hart&#8217;s point of view.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>The NEORV32 DM follows the "Minimal RISC-V External Debug Specification" to provide full debugging capabilities while +keeping resource/area requirements at a minimum. It implements the <strong>execution based debugging scheme</strong> for a +single hart and provides the following core features:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>program buffer with 2 entries and an implicit <code>ebreak</code> instruction</p> +</li> +<li> +<p>indirect bus access via the CPU using the program buffer</p> +</li> +<li> +<p>abstract commands: "access register" plus auto-execution</p> +</li> +<li> +<p>halt-on-reset capability</p> +</li> +</ul> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">DM Spec. Version</div> +By default, the OCD&#8217;s debug module supports version 1.0 of the RISC-V debug spec. For backwards compatibility, the DM +can be "downgraded" back to version 0.13 via the <code>DM_LEGACY_MODE</code> generic (see <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a>). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The DM provides two access "point of views": accesses from the DTM via the <em>debug module interface (dmi)</em> and +accesses from the CPU via the processor-internal bus system. From the DTM&#8217;s point of view, the DM implements a set of +<a href="#_dm_registers">DM Registers</a> that are used to control and monitor the debugging session. From the CPU&#8217;s point of view, the +DM implements several memory-mapped registers (within the <em>normal</em> address space) that are used for communicating +debugging control and status (<a href="#_dm_cpu_access">DM CPU Access</a>).</p> +</div> +<div class="sect3"> +<h4 id="_dm_registers">5.2.1. DM Registers</h4> +<div class="paragraph"> +<p>The DM is controlled via a set of registers that are accessed via the DTM&#8217;s <em>debug module interface</em> (dmi). +The following registers are implemented:</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Write accesses to registers that are not implemented are simply ignored and read accesses +to these registers will always return zero. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 94. Available DM registers</caption> +<colgroup> +<col style="width: 16.6666%;"> +<col style="width: 25%;"> +<col style="width: 58.3334%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Address</th> +<th class="tableblock halign-center valign-top">Name</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x04</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_data0"><strong><code>data0</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Abstract data 0, used for data transfer between debugger and processor</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x10</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_dmcontrol"><strong><code>dmcontrol</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug module control</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x11</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_dmstatus"><strong><code>dmstatus</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug module status</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x12</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_hartinfo"><strong><code>hartinfo</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hart information</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x16</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_abstracts"><strong><code>abstracts</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Abstract control and status</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x17</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_command"><strong><code>command</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Abstract command</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x18</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_abstractauto"><strong><code>abstractauto</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Abstract command auto-execution</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x1d</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>nextdm</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Base address of next DM; reads as zero to indicate there is only one DM</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x20</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_progbuf"><code>progbuf0</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Program buffer 0</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x21</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_progbuf"><code>progbuf1</code></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Program buffer 1</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x38</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>sbcs</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">System bus access control and status; reads as zero to indicate there is <strong>no</strong> direct system bus access</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x40</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><a href="#_haltsum0"><strong><code>haltsum0</code></strong></a></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Halted harts</p></td> +</tr> +</tbody> +</table> +<div class="sect4"> +<h5 id="_data0"><strong><code>data0</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x04</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Abstract data 0</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>data0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Basic read/write data exchange register to be used with abstract commands (for example to read/write data from/to CPU GPRs).</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_dmcontrol"><strong><code>dmcontrol</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x10</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Debug module control register</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>dmcontrol</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Control of the overall debug module and the hart. The following table shows all implemented bits. All remaining bits/bit-fields +are configured as "zero" and are read-only. Writing '1' to these bits/fields will be ignored.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 95. <code>dmcontrol</code> Register Bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 66.6668%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>haltreq</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set/clear hart halt request</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">30</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>resumereq</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">request hart to resume</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">28</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>ackhavereset</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">write <code>1</code> to clear <code>*havereset</code> flags</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>ndmreset</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">put whole system (except OCD) into reset state when <code>1</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dmactive</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">DM enable; writing <code>0</code>-<code>1</code> will reset the DM</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_dmstatus"><strong><code>dmstatus</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x11</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Debug module status register</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>dmstatus</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <code>0x00400083</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Current status of the overall debug module and the hart. The entire register is read-only.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 96. <code>dmstatus</code> Register Bits</caption> +<colgroup> +<col style="width: 7.6923%;"> +<col style="width: 15.3846%;"> +<col style="width: 76.9231%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:23</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved; always zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">22</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>impebreak</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">always <code>1</code>; indicates an implicit <code>ebreak</code> instruction after the last program buffer entry</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">21:20</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved; always zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">19</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>allhavereset</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>1</code> when the hart is in reset</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">18</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>anyhavereset</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">17</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>allresumeack</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>1</code> when the hart has acknowledged a resume request</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>anyresumeack</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>allnonexistent</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock">always zero to indicate the hart is always existent</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">14</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>anynonexistent</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">13</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>allunavail</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>1</code> when the DM is disabled to indicate the hart is unavailable</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">12</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>anyunavail</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>allrunning</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>1</code> when the hart is running</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">10</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>anyrunning</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">9</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>allhalted</code></p></td> +<td class="tableblock halign-left valign-top" rowspan="2"><p class="tableblock"><code>1</code> when the hart is halted</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>anyhalted</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>authenticated</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">always <code>1</code>; there is no authentication</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">6</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>authbusy</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">always <code>0</code>; there is no authentication</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">5</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>hasresethaltreq</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">always <code>0</code>; halt-on-reset is not supported (directly)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>confstrptrvalid</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">always <code>0</code>; no configuration string available</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>version</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">debug spec. version; <code>0011</code> (v1.0) or <code>0010</code> (v0.13); configured via the <code>DM_LEGACY_MODE</code> <a href="#_processor_top_entity_generics">Processor Top Entity - Generics</a></p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">OCD Security</div> +JTAG access via the OCD is <strong>always authenticated</strong> (<code>dmstatus.authenticated = 1</code>). Hence, the entire system can always +be accessed via the on-chip debugger. +</td> +</tr> +</table> +</div> +</div> +<div class="sect4"> +<h5 id="_hartinfo"><strong><code>hartinfo</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x12</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Hart information</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>hartinfo</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <em>see below</em></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">This register gives information about the hart. The entire register is read-only.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 97. <code>hartinfo</code> Register Bits</caption> +<colgroup> +<col style="width: 9.0909%;"> +<col style="width: 18.1818%;"> +<col style="width: 72.7273%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:24</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved; always zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">23:20</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>nscratch</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0001</code>, number of <code>dscratch*</code> CPU registers = 1</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">19:17</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved; always zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dataccess</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code>, the <code>data</code> registers are shadowed in the hart&#8217;s address space</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15:12</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>datasize</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0001</code>, number of 32-bit words in the address space dedicated to shadowing the <code>data</code> registers (1 register)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dataaddr</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">= <code>dm_data_base_c(11:0)</code>, signed base address of <code>data</code> words (see address map in <a href="#_dm_cpu_access">DM CPU Access</a>)</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_abstracts"><strong><code>abstracts</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x16</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Abstract control and status</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>abstracts</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <code>0x02000801</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Command execution info and status.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 98. <code>abstracts</code> Register Bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 66.6668%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:29</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved; always zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">28:24</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>progbufsize</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">always <code>0010</code>: size of the program buffer (<code>progbuf</code>) = 2 entries</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">23:11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved; always zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">12</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>busy</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> when a command is being executed</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>relaxedpriv</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">always <code>1</code>: PMP rules are ignored when in debug mode</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">10:8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>cmderr</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">error during command execution (see below); has to be cleared by writing <code>111</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">7:4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved; always zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>datacount</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">always <code>0001</code>: number of implemented <code>data</code> registers for abstract commands = 1</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>Error codes in <code>cmderr</code> (highest priority first):</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>000</code> - no error</p> +</li> +<li> +<p><code>100</code> - command cannot be executed since hart is not in expected state</p> +</li> +<li> +<p><code>011</code> - exception during command execution</p> +</li> +<li> +<p><code>010</code> - unsupported command</p> +</li> +<li> +<p><code>001</code> - invalid DM register read/write while command is/was executing</p> +</li> +</ul> +</div> +</div> +<div class="sect4"> +<h5 id="_command"><strong><code>command</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x17</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Abstract command</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>command</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Writing this register will trigger the execution of an abstract command. New command can only be executed if +<code>cmderr</code> is zero. The entire register in write-only (reads will return zero).</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The NEORV32 DM only supports <strong>Access Register</strong> abstract commands. These commands can only access the +hart&#8217;s GPRs x0 - x15/31 (abstract command register index <code>0x1000</code> - <code>0x101f</code>). +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 99. <code>command</code> Register Bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 66.6668%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description / required value</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:24</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>cmdtype</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>00000000</code> to indicate "access register" command</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">23</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>reserved</em></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">reserved, has to be <code>0</code> when writing</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">22:20</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>aarsize</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>010</code> to indicate 32-bit accesses</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">21</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>aarpostincrement</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code>, post-increment is not supported</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">18</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>postexec</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">if set the program buffer is executed <em>after</em> the command</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">17</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>transfer</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">if set the operation in <code>write</code> is conducted</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>write</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code>: copy <code>data0</code> to <code>[regno]</code>, <code>0</code>: copy <code>[regno]</code> to <code>data0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>regno</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">GPR-access only; has to be <code>0x1000</code> - <code>0x101f</code></p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_abstractauto"><strong><code>abstractauto</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x18</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Abstract command auto-execution</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>abstractauto</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Register to configure if a read/write access to a DM register re-triggers execution of the last abstract command.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 100. <code>abstractauto</code> Register Bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 66.6668%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">17</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>autoexecprogbuf[1]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">when set reading/writing from/to <code>progbuf1</code> will execute <code>command</code> again</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>autoexecprogbuf[0]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">when set reading/writing from/to <code>progbuf0</code> will execute <code>command</code> again</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>autoexecdata[0]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">when set reading/writing from/to <code>data0</code> will execute <code>command</code> again</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_progbuf"><strong><code>progbuf</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x20</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Program buffer 0</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>progbuf0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x21</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Program buffer 1</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>progbuf1</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <code>0x00000013</code> ("NOP")</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Program buffer (two entries) for the DM.</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_haltsum0"><strong><code>haltsum0</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 10.5263%;"> +<col style="width: 71.0526%;"> +<col style="width: 18.4211%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">0x408</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Halted harts status</strong></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>haltsum0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Reset value: <code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top" colspan="3"><p class="tableblock">Hart has halted when according bit is set.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 101. <code>haltsum0</code> Register Bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 66.6668%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>haltsum0[0]</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Hart is halted when set.</p></td> +</tr> +</tbody> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_dm_cpu_access">5.2.2. DM CPU Access</h4> +<div class="paragraph"> +<p>From the CPU&#8217;s perspective, the DM acts like another memory-mapped peripheral. It occupies 256 bytes of the CPU&#8217;s address +space starting at address <code>base_io_dm_c</code> (see table below). This address space is divided into four sections of 64 bytes +each to provide access to the <em>park loop code ROM</em>, the <em>program buffer</em>, the <em>data buffer</em> and the <em>status register</em>. +The program buffer, the data buffer and the status register do not fully occupy the 64-byte-wide sections and are +mirrored several times to fill the entire section.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 102. DM CPU Access - Address Map</caption> +<colgroup> +<col style="width: 22.2222%;"> +<col style="width: 22.2222%;"> +<col style="width: 55.5556%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Base address</th> +<th class="tableblock halign-center valign-top">Actual size</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xffffff00</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">64 bytes</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">ROM for the "park loop" code</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xffffff40</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">16 bytes</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Program buffer (<a href="#_progbuf"><strong><code>progbuf</code></strong></a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xffffff80</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4 bytes</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Data buffer (<a href="#_data0"><strong><code>data0</code></strong></a>)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xffffffc0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">4 bytes</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Control and <a href="#_status_register">Status Register</a></p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">DM Register Access</div> +All memory-mapped registers of the DM can only be accessed by the CPU if it is actually in debug mode. +Hence, the DM registers are not "visible" for normal CPU operations. +Any CPU access outside of debug mode will raise a bus access fault exception. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Park Loop Code Sources ("OCD Firmware")</div> +The assembly sources of the <strong>park loop code</strong> are available in <code>sw/ocd-firmware/park_loop.S</code>. +</td> +</tr> +</table> +</div> +<div class="sect4"> +<h5 id="_code_rom_entry_points">Code ROM Entry Points</h5> +<div class="paragraph"> +<p>The park loop code provides two entry points where the actual code execution can start. These are used to enter +the park loop either when an explicit debug-entry request has been issued (for example a halt request) or when an exception +has occurred while executing code <em>inside</em> debug mode.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 103. Park Loop Entry Points</caption> +<colgroup> +<col style="width: 60%;"> +<col style="width: 40%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Address</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dm_exc_entry_c</code> (<code>base_io_dm_c</code> + 0)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Exception entry address</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dm_park_entry_c</code> (<code>base_io_dm_c</code> + 8)</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Normal entry address</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>When the CPU enters or re-enters debug mode (for example via an <code>ebreak</code> in the DM&#8217;s program buffer), it jumps to +the <em>normal entry point</em> that is configured via the <code>CPU_DEBUG_PARK_ADDR</code> generic +(<a href="#_cpu_top_entity_generics">CPU Top Entity - Generics</a>). By default, this generic is set to <code>dm_park_entry_c</code>, which is defined in main +package file. If an exception is encountered during debug mode, the CPU jumps to the address of the <em>exception +entry point</em> configured via the <code>CPU_DEBUG_EXC_ADDR</code> generic (<a href="#_cpu_top_entity_generics">CPU Top Entity - Generics</a>). By default, this generic +is set to <code>dm_exc_entry_c</code>, which is also defined in main package file.</p> +</div> +</div> +<div class="sect4"> +<h5 id="_status_register">Status Register</h5> +<div class="paragraph"> +<p>The status register provides a direct communication channel between the CPU&#8217;s debug mode executing the park loop +and the debugger-controlled debug module. This register is used to communicate <em>requests</em>, which are issued by the +DM and the according <em>acknowledges</em>, which are generated by the CPU.</p> +</div> +<div class="paragraph"> +<p>There are only 4 bits in this register that are used to implement the requests/acknowledges. Each bit is left-aligned +in one sub-byte of the entire 32-bit register. Thus, the CPU can access each bit individually using <em>store-byte</em> and +<em>load-byte</em> instructions. This eliminates the need to perform bit-masking in the park loop code leading to less code size +and faster execution.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 104. DM Status Register - CPU Access</caption> +<colgroup> +<col style="width: 7.1428%;"> +<col style="width: 21.4285%;"> +<col style="width: 14.2857%;"> +<col style="width: 57.143%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name</th> +<th class="tableblock halign-center valign-top">CPU access</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" rowspan="2"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>sreg_halt_ack</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">read</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">write</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set by the CPU while it is halted (and executing the park loop).</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" rowspan="2"><p class="tableblock">8</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>sreg_resume_req</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">read</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set by the DM to request the CPU to resume normal operation.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>sreg_resume_ack</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">write</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set by the CPU before it starts resuming.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" rowspan="2"><p class="tableblock">16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>sreg_execute_req</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">read</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set by the DM to request execution of the program buffer.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>sreg_execute_ack</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">write</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set by the CPU before it starts executing the program buffer.</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" rowspan="2"><p class="tableblock">24</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">read</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">-</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>sreg_execute_ack</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">write</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set by the CPU if an exception occurs while being in debug mode.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_cpu_debug_mode">5.3. CPU Debug Mode</h3> +<div class="paragraph"> +<p>The NEORV32 CPU Debug Mode is compatible to the <strong>Minimal RISC-V Debug Specification 1.0</strong> +<code>Sdext</code> (external debug) ISA extension. When enabled via the CPU&#8217;s <a href="#_sdext_isa_extension"><code>Sdext</code> ISA Extension</a> generic and/or +the processor&#8217;s <code>ON_CHIP_DEBUGGER_EN</code> it adds a new CPU operation mode ("debug mode"), three additional +<a href="#_cpu_debug_mode_csrs">CPU Debug Mode CSRs</a> and one additional instruction (<code>dret</code>) to the core.</p> +</div> +<div class="paragraph"> +<p>Debug-mode is entered on any of the following events:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>The CPU executes an <code>ebreak</code> instruction (when in machine-mode and <code>ebreakm</code> in <a href="#_dcsr"><strong><code>dcsr</code></strong></a> is set OR when in user-mode and <code>ebreaku</code> in <a href="#_dcsr"><strong><code>dcsr</code></strong></a> is set).</p> +</li> +<li> +<p>A debug halt request is issued by the DM (via CPU signal <code>db_halt_req_i</code>, high-active).</p> +</li> +<li> +<p>The CPU completes executing of a single instruction while being in single-step debugging mode (<code>step</code> in <a href="#_dcsr"><strong><code>dcsr</code></strong></a> is set).</p> +</li> +<li> +<p>A hardware trigger from the <a href="#_trigger_module">Trigger Module</a> fires (<code>exe</code> and <code>action</code> in <a href="#_tdata1"><strong><code>tdata1</code></strong></a> / <code>mcontrol</code> are set).</p> +</li> +</ol> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +From a hardware point of view these debug-mode-entry conditions are special traps (synchronous exceptions or +asynchronous interrupts) that are handled transparently by the control logic. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Whenever the CPU enters debug-mode it performs the following operations:</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>wake-up CPU if it was send to sleep mode by the <code>wfi</code> instruction</p> +</li> +<li> +<p>switch to debug-mode privilege level</p> +</li> +<li> +<p>move the current program counter to <a href="#_dpc"><strong><code>dpc</code></strong></a></p> +</li> +<li> +<p>copy the hart&#8217;s current privilege level to the <code>prv</code> flags in <a href="#_dcsr"><strong><code>dcsr</code></strong></a></p> +</li> +<li> +<p>set <code>cause</code> in <a href="#_dcsr"><strong><code>dcsr</code></strong></a> according to the cause why debug mode is entered</p> +</li> +<li> +<p><strong>no update</strong> of <code>mtval</code>, <code>mcause</code>, <code>mtval</code> and <code>mstatus</code> CSRs</p> +</li> +<li> +<p>load the address configured via the CPU&#8217;s <code>CPU_DEBUG_PARK_ADDR</code> (<a href="#_cpu_top_entity_generics">CPU Top Entity - Generics</a>) generic to the program counter jumping to the +"debugger park loop" code stored in the debug module (DM)</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>When the CPU is in debug-mode the following things are important:</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>while in debug mode, the CPU executes the parking loop and - if requested by the DM - the program buffer</p> +</li> +<li> +<p>effective CPU privilege level is <code>machine</code> mode; any active physical memory protection (PMP) configuration is bypassed</p> +</li> +<li> +<p>the <code>wfi</code> instruction acts as a <code>nop</code> (also during single-stepping)</p> +</li> +<li> +<p>if an exception occurs while being in debug mode:</p> +<div class="ulist"> +<ul> +<li> +<p>if the exception was caused by any debug-mode entry action the CPU jumps to the normal entry point (defined by <code>CPU_DEBUG_PARK_ADDR</code> generic of the <a href="#_cpu_top_entity_generics">CPU Top Entity - Generics</a>) of the park loop again (for example when executing <code>ebreak</code> while in debug-mode)</p> +</li> +<li> +<p>for all other exception sources the CPU jumps to the exception entry point (defined by <code>CPU_DEBUG_EXC_ADDR</code> generic of the <a href="#_cpu_top_entity_generics">CPU Top Entity - Generics</a>) to signal an exception to the DM; the CPU restarts the park loop again afterwards</p> +</li> +</ul> +</div> +</li> +<li> +<p>interrupts are disabled; however, they will remain pending and will get executed after the CPU has left debug mode and is not being single-stepped</p> +</li> +<li> +<p>if the DM makes a resume request, the park loop exits and the CPU leaves debug mode (executing <code>dret</code>)</p> +</li> +<li> +<p>the standard counters <a href="#_machine_counter_and_timer_csrs">(Machine) Counter and Timer CSRs</a> <code>[m]cycle[h]</code> and <code>[m]instret[h]</code> are stopped</p> +</li> +<li> +<p>all <a href="#_hardware_performance_monitors_hpm_csrs">Hardware Performance Monitors (HPM) CSRs</a> are stopped</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>Debug mode is left either by executing the <code>dret</code> instruction or by performing a hardware reset of the CPU. +Executing <code>dret</code> outside of debug mode will raise an illegal instruction exception.</p> +</div> +<div class="paragraph"> +<p><strong>Whenever the CPU leaves debug mode it performs the following operations:</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>set the hart&#8217;s current privilege level according to the <code>prv</code> flags of <a href="#_dcsr"><strong><code>dcsr</code></strong></a></p> +</li> +<li> +<p>restore the original program counter from <a href="#_dpc"><strong><code>dpc</code></strong></a> resuming normal operation</p> +</li> +</ul> +</div> +<div class="sect3"> +<h4 id="_cpu_debug_mode_csrs">5.3.1. CPU Debug Mode CSRs</h4> +<div class="paragraph"> +<p>Two additional CSRs are required by the <em>Minimal RISC-V Debug Specification</em>: the debug mode control and status register +<code>dcsr</code> and the debug program counter <code>dpc</code>. An additional general purpose scratch register for debug-mode-only +(<code>dscratch0</code>) allows faster execution by having a fast-accessible backup register. +These CSRs are only accessible when the CPU is <em>in</em> debug mode. If these CSRs are accessed outside of debug mode +an illegal instruction exception is raised.</p> +</div> +<div class="sect4"> +<h5 id="_dcsr"><strong><code>dcsr</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug control and status register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x7b0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x40000410</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Sdext</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">This register is used to configure the debug mode environment and provides additional status information.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 105. Debug control and status register <code>dcsr</code> bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 66.6668%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:28</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>xdebugver</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0100</code> - CPU debug mode is compatible to spec. version 1.0</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">27:16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>000000000000</code> - <em>reserved</em></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>ebereakm</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ebreak</code> instructions in <code>machine</code> mode will <em>enter</em> debug mode when set</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">14</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>ebereakh</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - hypervisor mode not supported</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">13</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>ebereaks</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - supervisor mode not supported</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">12</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>ebereaku</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>ebreak</code> instructions in <code>user</code> mode will <em>enter</em> debug mode when set</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>stepie</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - IRQs are disabled during single-stepping</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">10</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>stopcount</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> - standard counters and HPMs are stopped when in debug mode</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">9</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>stoptime</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - timers increment as usual</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">8:6</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>cause</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">cause identifier - why debug mode was entered (see below)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">5</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - <em>reserved</em></p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>mprven</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> - <code>mprv</code> in <a href="#_mstatus"><strong><code>mstatus</code></strong></a> is also evaluated when in debug mode</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>nmip</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - non-maskable interrupt is pending</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>step</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">enable single-stepping when set</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>prv</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">CPU privilege level before/after debug mode</p></td> +</tr> +</tbody> +</table> +<div class="paragraph"> +<p>Cause codes in <code>dcsr.cause</code> (highest priority first):</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>010</code> - triggered by hardware <a href="#_trigger_module">Trigger Module</a></p> +</li> +<li> +<p><code>001</code> - executed <code>EBREAK</code> instruction</p> +</li> +<li> +<p><code>011</code> - external halt request (from DM)</p> +</li> +<li> +<p><code>100</code> - return from single-stepping</p> +</li> +</ul> +</div> +</div> +<div class="sect4"> +<h5 id="_dpc"><strong><code>dpc</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug program counter</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x7b1</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Sdext</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The register is used to store the current program counter when debug mode is entered. The <code>dret</code> instruction will +return to the address stored in <code>dpc</code> by automatically moving <code>dpc</code> to the program counter.</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<code>dpc[0]</code> is hardwired to zero. If <code>IALIGN</code> = 32 (i.e. <a href="#_c_isa_extension"><code>C</code> ISA Extension</a> is disabled) then <code>dpc[1]</code> is also hardwired to zero. +</td> +</tr> +</table> +</div> +</div> +<div class="sect4"> +<h5 id="_dscratch0"><strong><code>dscratch0</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Debug scratch register 0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x7b2</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Sdext</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The register provides a general purpose debug mode-only scratch register.</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_trigger_module">5.4. Trigger Module</h3> +<div class="paragraph"> +<p>"Normal" <em>software</em> breakpoints (using GDB&#8217;s <code>b</code>/<code>break</code> command) are implemented by temporarily replacing the according +instruction word by an <code>[c.]ebreak</code> instruction. However, this is not possible when debugging code that is executed from +read-only memory (for example when debugging programs that are executed via the <a href="#_execute_in_place_module_xip">Execute In Place Module (XIP)</a>). +To circumvent this limitation a hardware trigger logic allows to (re-)enter debug-mode when instruction execution +reaches a programmable address. These "hardware-assisted breakpoints" are used by GDB&#8217;s <code>hb</code>/<code>hbreak</code> commands.</p> +</div> +<div class="paragraph"> +<p>The RISC-V <code>Sdtrig</code> ISA extension adds a programmable <em>trigger module</em> to the CPU core that is enabled via the +<a href="#_sdtrig_isa_extension"><code>Sdtrig</code> ISA Extension</a> generic. The trigger module implements a subset of the features described in the +"RISC-V Debug Specification / Trigger Module" and complies to version v1.0 of the <code>Sdtrig</code> spec.</p> +</div> +<div class="paragraph"> +<p>The NEORV32 trigger module features only a <em>single</em> trigger implementing a "type 6 - instruction address match" trigger. +This limitation is granted by the RISC-V debug spec and is sufficient to <strong>debug code executed from read-only memory (ROM)</strong>. +The trigger module can also be used independently of the CPU debug-mode / <code>Sdext</code> ISA extension. +Machine-mode software can use the trigger module to raise a breakpoint exception when instruction execution +reaches a programmed address.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Trigger Timing</div> +When enabled the address match trigger will fire <strong>BEFORE</strong> the instruction at the programmed address gets executed. +</td> +</tr> +</table> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">MEPC &amp; DPC CSRs</div> +The breakpoint exception when raised by the trigger module behaves different then the "normal" trapping (see +<a href="#_neorv32_trap_listing">NEORV32 Trap Listing</a>): <a href="#_mepc"><strong><code>mepc</code></strong></a> / <a href="#_dpc"><strong><code>dpc</code></strong></a> is set to the address of the next instruction that needs to be +executed to preserve the program flow. A "normal" breakpoint exception would set <a href="#_mepc"><strong><code>mepc</code></strong></a> / <a href="#_dpc"><strong><code>dpc</code></strong></a> to the address +of the actual <code>ebreak</code> instruction itself. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_trigger_module_csrs">5.4.1. Trigger Module CSRs</h4> +<div class="paragraph"> +<p>The <code>Sdtrig</code> ISA extension adds 4 additional CSRs that are accessible from debug-mode and also from machine-mode. +Machine-mode write accesses can be ignored by setting ยดdmodeยด in <a href="#_tdata1"><strong><code>tdata1</code></strong></a>. This is automatically done by the debugger +if it uses the trigger module for implementing a "hardware breakpoint"</p> +</div> +<div class="sect4"> +<h5 id="_tselect"><strong><code>tselect</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger select register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x7a0</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Sdtrig</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">This CSR is hardwired to zero indicating there is only one trigger available. Any write access is ignored.</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_tdata1"><strong><code>tdata1</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger data register 1, visible as trigger "type 6 match control" (<code>mcontrol6</code>)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x7a1</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x60000048</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Sdtrig</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">This CSR is used to configure the address match trigger using the "type 6" format.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 106. Match Control CSR (<code>tdata1</code>) Bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 66.6668%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:28</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>type</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0100</code> - address match trigger type 6</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">27</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>dmode</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set to ignore write accesses to <a href="#_tdata1"><strong><code>tdata1</code></strong></a> and <a href="#_tdata2"><strong><code>tdata2</code></strong></a> from machine-mode; writable from debug-mode only</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">26</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>uncertain</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - trigger satisfies the configured conditions</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">25</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>hit1</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - hardwired to zero, only <code>hit0</code> is used</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">24</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>vs</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - VS-mode not supported</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">23</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>vu</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - VU-mode not supported</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">22</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>hit0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/c</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set when trigger has fired (<strong>BEFORE</strong> executing the triggering address); must be explicitly cleared by writing zero; writing 1 has no effect</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">21</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>select</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - only address matching is supported</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">20:19</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">reserved</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>00</code> - hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">18:16</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>size</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>000</code> - match accesses of any size</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15:12</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>action</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0000</code> = breakpoint exception on trigger match, <code>0001</code> = enter debug-mode on trigger match</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">11</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>chain</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - chaining is not supported as there is only one trigger</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">10:6</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>match</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0000</code> - equal-match only</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">6</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>m</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>1</code> - trigger enabled when in machine-mode</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">5</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>uncertainen</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - feature not supported, hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">4</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>s</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - supervisor-mode not supported</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">3</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>u</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code>/<code>1</code> - trigger enabled when in user-mode, set if <code>U</code> ISA extension is enabled</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">2</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>execute</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/w</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">set to enable trigger matching on instruction address</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">1</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>store</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - store address/data matching not supported</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>load</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0</code> - load address/data matching not supported</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_tdata2"><strong><code>tdata2</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger data register 2</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x7a2</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Sdtrig</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Since only the "address match trigger" type is supported, this r/w CSR is used to configure the address of the triggering instruction. +Note that the trigger module will fire <strong>before</strong> the instruction at the programmed address gets executed.</p></td> +</tr> +</tbody> +</table> +</div> +<div class="sect4"> +<h5 id="_tinfo"><strong><code>tinfo</code></strong></h5> +<table class="tableblock frame-ends grid-none stretch"> +<colgroup> +<col style="width: 11.1111%;"> +<col style="width: 88.8889%;"> +</colgroup> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Name</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Trigger information register</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Address</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x7a4</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Reset value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x01000006</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">ISA</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>Zicsr</code> &amp; <code>Sdtrig</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock">Description</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">The CSR shows global trigger information (see below). Any write access is ignored.</p></td> +</tr> +</tbody> +</table> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 107. Trigger Info CSR (<code>tinfo</code>) Bits</caption> +<colgroup> +<col style="width: 8.3333%;"> +<col style="width: 16.6666%;"> +<col style="width: 8.3333%;"> +<col style="width: 66.6668%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Bit</th> +<th class="tableblock halign-center valign-top">Name [RISC-V]</th> +<th class="tableblock halign-center valign-top">R/W</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">31:24</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>version</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x01</code> - compatible to spec. version v1.0</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">23:15</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">reserved</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x00</code> - hardwired to zero</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock">15:0</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>info</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">r/-</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>0x0006</code> - only the "type 6 trigger" is supported</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_legal">6. Legal</h2> +<div class="sectionbody"> +<div class="sect2"> +<h3 id="_about">About</h3> +<div class="exampleblock"> +<div class="content"> +<div class="paragraph"> +<p><strong>The NEORV32 RISC-V Processor</strong><br> +<a href="https://github.com/stnolting/neorv32" class="bare">https://github.com/stnolting/neorv32</a><br> +Stephan Nolting, M.Sc.<br> +๐Ÿ‡ช๐Ÿ‡บ European Union<br> +<code>stnolting[รคt]gmail[d0t]com</code></p> +</div> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_license">License</h3> +<div class="paragraph"> +<p><strong>BSD 3-Clause License</strong></p> +</div> +<div class="paragraph"> +<p>Copyright (c) NEORV32 contributors. +Copyright (c) 2020 - 2024, Stephan Nolting. All rights reserved.</p> +</div> +<div class="paragraph"> +<p>Redistribution and use in source and binary forms, with or without modification, are permitted provided that +the following conditions are met:</p> +</div> +<div class="olist arabic"> +<ol class="arabic"> +<li> +<p>Redistributions of source code must retain the above copyright notice, this list of conditions and the +following disclaimer.</p> +</li> +<li> +<p>Redistributions in binary form must reproduce the above copyright notice, this list of conditions and +the following disclaimer in the documentation and/or other materials provided with the distribution.</p> +</li> +<li> +<p>Neither the name of the copyright holder nor the names of its contributors may be used to endorse or +promote products derived from this software without specific prior written permission.</p> +</li> +</ol> +</div> +<div class="paragraph"> +<p>THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. 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Teranishi.</p> +</li> +<li> +<p>"NeoPixel" is a trademark of Adafruit Industries.</p> +</li> +<li> +<p>"Segger Embedded Studio" and "J-Link" are trademarks of Segger Microcontroller Systems GmbH.</p> +</li> +<li> +<p>Images/figures made with <em>Microsoft Power Point</em>.</p> +</li> +<li> +<p>Timing diagrams made with <em>WaveDrom Editor</em>.</p> +</li> +<li> +<p>Documentation made with <code>asciidoctor</code>.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>All further/unreferenced projects/products/brands belong to their according copyright holders. +No copyright infringement intended.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_disclaimer">Disclaimer</h3> +<div class="paragraph"> +<p>This project is released under the BSD 3-Clause license. NO COPYRIGHT INFRINGEMENT INTENDED. +Other implied or used projects/sources might have different licensing โ€“ see their according +documentation for more information.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_limitation_of_liability_for_external_links">Limitation of Liability for External Links</h3> +<div class="paragraph"> +<p>This document contains links to the websites of third parties ("external links"). As the content of these websites +is not under our control, we cannot assume any liability for such external content. In all cases, the provider of +information of the linked websites is liable for the content and accuracy of the information provided. At the +point in time when the links were placed, no infringements of the law were recognizable to us. As soon as an +infringement of the law becomes known to us, we will immediately remove the link in question.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_citing">Citing</h3> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +This is an open-source project that is free of charge. Use this project in any way you like +(as long as it complies to the permissive license). Please cite it appropriately. ๐Ÿ‘ +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Contributors &amp; Community ๐Ÿค</div> +Please add as many <a href="https://github.com/stnolting/neorv32/graphs/contributors">contributors</a> as possible to the <code>author</code> field.<br> +This project would not be where it is without them. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">DOI</div> +This project provides a <em>digital object identifier</em> provided by <a href="https://zenodo.org">zenodo</a>: +<a href="https://doi.org/10.5281/zenodo.5018888"><span class="image"><img src="https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg" alt="zenodo.5018888" title="zenodo"></span></a> +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_acknowledgments">Acknowledgments</h3> +<div class="paragraph"> +<p><strong>A big shout-out to the community and all the <a href="https://github.com/stnolting/neorv32/graphs/contributors">contributors</a>, +who helped improving this project! This project would not be where it is without them. โค๏ธ</strong></p> +</div> +<div class="paragraph"> +<p><a href="https://riscv.org">RISC-V</a> - instruction sets want to be free!</p> +</div> +<div class="paragraph"> +<p>Continuous integration provided by <a href="https://github.com/features/actions">GitHub Actions</a> +and powered by <a href="https://github.com/ghdl/ghdl">GHDL</a>.</p> +</div> +</div> +</div> +</div> +</div> +<div id="footer"> +<div id="footer-text"> +Version v1.10.5-r58-gf1069d11<br> +</div> +</div> +<script type="text/x-mathjax-config"> +MathJax.Hub.Config({ + messageStyle: "none", + tex2jax: { + inlineMath: [["\\(", "\\)"]], + displayMath: [["\\[", "\\]"]], + ignoreClass: "nostem|nolatexmath" + }, + asciimath2jax: { + delimiters: [["\\$", "\\$"]], + ignoreClass: "nostem|noasciimath" + }, + TeX: { equationNumbers: { autoNumber: "none" } } +}) +MathJax.Hub.Register.StartupHook("AsciiMath Jax Ready", function () { + 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b/sw/atomic__test_2main_8c.html new file mode 100644 index 000000000..248280cf7 --- /dev/null +++ b/sw/atomic__test_2main_8c.html @@ -0,0 +1,308 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/atomic_test/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script 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+<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_449d8ba5f8b78dc90092f20d15a2386a.html">atomic_test</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Test program for the NEORV32 'A' ISA extension - check the emulation of the AMO (read-modify-write) operations. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">User configuration</h2></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;(19200)</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a83792c34853f1d2801b59ad46adc7e1e" id="r_a83792c34853f1d2801b59ad46adc7e1e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a83792c34853f1d2801b59ad46adc7e1e">NUM_TEST_CASES</a>&#160;&#160;&#160;(1000)</td></tr> +<tr class="separator:a83792c34853f1d2801b59ad46adc7e1e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a87f296d7594bb8178cf76f0c045b7013" id="r_a87f296d7594bb8178cf76f0c045b7013"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a87f296d7594bb8178cf76f0c045b7013">SILENT_MODE</a>&#160;&#160;&#160;(1)</td></tr> +<tr class="separator:a87f296d7594bb8178cf76f0c045b7013"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9141e95a5f98420ddf8a43e6d20ff6dc" id="r_a9141e95a5f98420ddf8a43e6d20ff6dc"><td class="memItemLeft" align="right" valign="top">volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9141e95a5f98420ddf8a43e6d20ff6dc">amo_var</a></td></tr> +<tr class="separator:a9141e95a5f98420ddf8a43e6d20ff6dc"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4f4c6d8481b4100f90955ba5a70428a4" id="r_a4f4c6d8481b4100f90955ba5a70428a4"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4f4c6d8481b4100f90955ba5a70428a4">check_result</a> (uint32_t num, uint32_t amo_var_old, uint32_t amo_var_pre, uint32_t amo_var_new, uint32_t <a class="el" href="#a9141e95a5f98420ddf8a43e6d20ff6dc">amo_var</a>)</td></tr> +<tr class="separator:a4f4c6d8481b4100f90955ba5a70428a4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a99377a057d14aaa9b45f8cab890e8cf7" id="r_a99377a057d14aaa9b45f8cab890e8cf7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a99377a057d14aaa9b45f8cab890e8cf7">print_report</a> (int num_err, int num_tests)</td></tr> +<tr class="separator:a99377a057d14aaa9b45f8cab890e8cf7"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aafcbf639ae4f66e5dfe9dea511a59f9d" id="r_aafcbf639ae4f66e5dfe9dea511a59f9d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aafcbf639ae4f66e5dfe9dea511a59f9d">trap_handler_emulate_amo</a> (void)</td></tr> +<tr class="separator:aafcbf639ae4f66e5dfe9dea511a59f9d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Test program for the NEORV32 'A' ISA extension - check the emulation of the AMO (read-modify-write) operations. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;(19200)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a83792c34853f1d2801b59ad46adc7e1e" name="a83792c34853f1d2801b59ad46adc7e1e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a83792c34853f1d2801b59ad46adc7e1e">&#9670;&#160;</a></span>NUM_TEST_CASES</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NUM_TEST_CASES&#160;&#160;&#160;(1000)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a87f296d7594bb8178cf76f0c045b7013" name="a87f296d7594bb8178cf76f0c045b7013"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a87f296d7594bb8178cf76f0c045b7013">&#9670;&#160;</a></span>SILENT_MODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SILENT_MODE&#160;&#160;&#160;(1)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a4f4c6d8481b4100f90955ba5a70428a4" name="a4f4c6d8481b4100f90955ba5a70428a4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4f4c6d8481b4100f90955ba5a70428a4">&#9670;&#160;</a></span>check_result()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t check_result </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>amo_var_old</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>amo_var_pre</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>amo_var_new</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>amo_var</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check results (reference (SW) vs actual hardware).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Test case number </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">amo_var_old</td><td>Initial value of atomic variable. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">amo_var_pre</td><td>Value of atomic variable read from memory (before operation). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">amo_var_new</td><td>Expected new value of atomic variable. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">amo_var</td><td>Actual new value of atomic variable. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>zero if results are correct. </dd></dl> + +</div> +</div> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function; test all provided AMO emulation functions.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the RISC-V A CPU extension.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Irrelevant. </dd></dl> + +</div> +</div> +<a id="a99377a057d14aaa9b45f8cab890e8cf7" name="a99377a057d14aaa9b45f8cab890e8cf7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a99377a057d14aaa9b45f8cab890e8cf7">&#9670;&#160;</a></span>print_report()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void print_report </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>num_err</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>num_tests</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print test report.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">num_err</td><td>Number or errors in this test. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">num_tests</td><td>Total number of conducted tests. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aafcbf639ae4f66e5dfe9dea511a59f9d" name="aafcbf639ae4f66e5dfe9dea511a59f9d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aafcbf639ae4f66e5dfe9dea511a59f9d">&#9670;&#160;</a></span>trap_handler_emulate_amo()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void trap_handler_emulate_amo </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Emulate atomic memory operation.</p> +<dl class="section note"><dt>Note</dt><dd>This is a RTE "second-level" trap handler. </dd></dl> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a id="a9141e95a5f98420ddf8a43e6d20ff6dc" name="a9141e95a5f98420ddf8a43e6d20ff6dc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9141e95a5f98420ddf8a43e6d20ff6dc">&#9670;&#160;</a></span>amo_var</h2> + +<div class="memitem"> +<div class="memproto"> + <table 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class="headertitle"><div class="title">bootloader.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Default NEORV32 bootloader. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +<code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:a0035ad41f622dbfc2412318a8ed39257" id="r_a0035ad41f622dbfc2412318a8ed39257"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0035ad41f622dbfc2412318a8ed39257">EXE_SIGNATURE</a>&#160;&#160;&#160;0x4788CAFE</td></tr> +<tr class="separator:a0035ad41f622dbfc2412318a8ed39257"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">Bootloader configuration (override via console to customize);</div></td></tr> +<tr><td colspan="2"><div class="groupText"><p>default values are used if not explicitly customized </p> +</div></td></tr> +<tr class="memitem:a18936dc79b9e5aa84df016b046a6b977" id="r_a18936dc79b9e5aa84df016b046a6b977"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a18936dc79b9e5aa84df016b046a6b977">EXE_BASE_ADDR</a>&#160;&#160;&#160;0x00000000UL</td></tr> +<tr class="separator:a18936dc79b9e5aa84df016b046a6b977"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af1c2f103ac6e3183f08b39099fab2be9" id="r_af1c2f103ac6e3183f08b39099fab2be9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af1c2f103ac6e3183f08b39099fab2be9">UART_EN</a>&#160;&#160;&#160;1</td></tr> +<tr class="separator:af1c2f103ac6e3183f08b39099fab2be9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1fac9153314479ad0ad495d752f0224a" id="r_a1fac9153314479ad0ad495d752f0224a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1fac9153314479ad0ad495d752f0224a">UART_BAUD</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:a1fac9153314479ad0ad495d752f0224a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a20e93d623ce07939c3fdd53898f9d583" id="r_a20e93d623ce07939c3fdd53898f9d583"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a20e93d623ce07939c3fdd53898f9d583">UART_HW_HANDSHAKE_EN</a>&#160;&#160;&#160;0</td></tr> +<tr class="separator:a20e93d623ce07939c3fdd53898f9d583"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa9696325b450773c7a87c991abca3a54" id="r_aa9696325b450773c7a87c991abca3a54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa9696325b450773c7a87c991abca3a54">STATUS_LED_EN</a>&#160;&#160;&#160;1</td></tr> +<tr class="separator:aa9696325b450773c7a87c991abca3a54"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a089a71f836911c71b3f73fdd3b4b890b" id="r_a089a71f836911c71b3f73fdd3b4b890b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a089a71f836911c71b3f73fdd3b4b890b">STATUS_LED_PIN</a>&#160;&#160;&#160;0</td></tr> +<tr class="separator:a089a71f836911c71b3f73fdd3b4b890b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af6fcb607a9c320da869b72aa30893a69" id="r_af6fcb607a9c320da869b72aa30893a69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af6fcb607a9c320da869b72aa30893a69">AUTO_BOOT_TIMEOUT</a>&#160;&#160;&#160;10</td></tr> +<tr class="separator:af6fcb607a9c320da869b72aa30893a69"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aea75cf0485ce0a4ea320eba994859686" id="r_aea75cf0485ce0a4ea320eba994859686"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aea75cf0485ce0a4ea320eba994859686">SPI_EN</a>&#160;&#160;&#160;1</td></tr> +<tr class="separator:aea75cf0485ce0a4ea320eba994859686"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa2132454aada86216009f3af206899b1" id="r_aa2132454aada86216009f3af206899b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa2132454aada86216009f3af206899b1">SPI_FLASH_CS</a>&#160;&#160;&#160;0</td></tr> +<tr class="separator:aa2132454aada86216009f3af206899b1"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afe60a31c8561952f2f734fd67e6f7406" id="r_afe60a31c8561952f2f734fd67e6f7406"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afe60a31c8561952f2f734fd67e6f7406">SPI_FLASH_ADDR_BYTES</a>&#160;&#160;&#160;3</td></tr> +<tr class="separator:afe60a31c8561952f2f734fd67e6f7406"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a00924a8ba223b2ca0e7031259b292c84" id="r_a00924a8ba223b2ca0e7031259b292c84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a00924a8ba223b2ca0e7031259b292c84">SPI_FLASH_SECTOR_SIZE</a>&#160;&#160;&#160;65536</td></tr> +<tr class="separator:a00924a8ba223b2ca0e7031259b292c84"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a709071a651213770b4efe6e6e055ec3d" id="r_a709071a651213770b4efe6e6e055ec3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a709071a651213770b4efe6e6e055ec3d">SPI_FLASH_CLK_PRSC</a>&#160;&#160;&#160;<a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73aa4e3a6a5b3cd895f63b4544f63ce22c9">CLK_PRSC_8</a></td></tr> +<tr class="separator:a709071a651213770b4efe6e6e055ec3d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a418adcf57119600c3580fd2297d28de0" id="r_a418adcf57119600c3580fd2297d28de0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a418adcf57119600c3580fd2297d28de0">SPI_BOOT_BASE_ADDR</a>&#160;&#160;&#160;0x00400000UL</td></tr> +<tr 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+</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a> +Enumerations</h2></td></tr> +<tr class="memitem:abcbf77626fdd0b475d245f836eab7a83" id="r_abcbf77626fdd0b475d245f836eab7a83"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abcbf77626fdd0b475d245f836eab7a83">EXE_STREAM_SOURCE_enum</a> { <a class="el" href="#abcbf77626fdd0b475d245f836eab7a83ab149261ddf3f08e44e9d2538e384f58f">EXE_STREAM_UART</a> = 0 +, <a class="el" href="#abcbf77626fdd0b475d245f836eab7a83a98526cd8f81d570c57d98193b32cf114">EXE_STREAM_FLASH</a> = 1 + }</td></tr> +<tr class="separator:abcbf77626fdd0b475d245f836eab7a83"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa0c639898508ff8e4fab6290101f3088" id="r_aa0c639898508ff8e4fab6290101f3088"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td 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id="r_a6a8caddda6e729d747726471b0b0f742"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6a8caddda6e729d747726471b0b0f742">spi_flash_write_addr</a> (uint32_t addr)</td></tr> +<tr class="separator:a6a8caddda6e729d747726471b0b0f742"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a840291bc02cba5474a4cb46a9b9566fe" id="r_a840291bc02cba5474a4cb46a9b9566fe"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a840291bc02cba5474a4cb46a9b9566fe">main</a> (void)</td></tr> +<tr class="separator:a840291bc02cba5474a4cb46a9b9566fe"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a6fea855ffe2fa0cd5ea9f98c0d5adc4d" id="r_a6fea855ffe2fa0cd5ea9f98c0d5adc4d"><td class="memItemLeft" align="right" valign="top">const char&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6fea855ffe2fa0cd5ea9f98c0d5adc4d">error_message</a> [4][5]</td></tr> +<tr class="separator:a6fea855ffe2fa0cd5ea9f98c0d5adc4d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0f9fcfdf758260b9b79b6eda063dd87a" id="r_a0f9fcfdf758260b9b79b6eda063dd87a"><td class="memItemLeft" align="right" valign="top">volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0f9fcfdf758260b9b79b6eda063dd87a">exe_available</a></td></tr> +<tr class="separator:a0f9fcfdf758260b9b79b6eda063dd87a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5fa6b109bf211d1768f84c9d38eef240" id="r_a5fa6b109bf211d1768f84c9d38eef240"><td class="memItemLeft" align="right" valign="top">volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5fa6b109bf211d1768f84c9d38eef240">getting_exe</a></td></tr> +<tr class="separator:a5fa6b109bf211d1768f84c9d38eef240"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Default NEORV32 bootloader. </p> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="af6fcb607a9c320da869b72aa30893a69" name="af6fcb607a9c320da869b72aa30893a69"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af6fcb607a9c320da869b72aa30893a69">&#9670;&#160;</a></span>AUTO_BOOT_TIMEOUT</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define AUTO_BOOT_TIMEOUT&#160;&#160;&#160;10</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Time until the auto-boot sequence starts (in seconds); 0 = disabled </p> + +</div> +</div> +<a id="a18936dc79b9e5aa84df016b046a6b977" name="a18936dc79b9e5aa84df016b046a6b977"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a18936dc79b9e5aa84df016b046a6b977">&#9670;&#160;</a></span>EXE_BASE_ADDR</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define EXE_BASE_ADDR&#160;&#160;&#160;0x00000000UL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Memory base address for the executable </p> + +</div> +</div> +<a id="a0035ad41f622dbfc2412318a8ed39257" name="a0035ad41f622dbfc2412318a8ed39257"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0035ad41f622dbfc2412318a8ed39257">&#9670;&#160;</a></span>EXE_SIGNATURE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define EXE_SIGNATURE&#160;&#160;&#160;0x4788CAFE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Valid executable identification signature </p> + +</div> +</div> +<a id="a999b04603115ce08b0cb33e333312480" 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+ <tr> + <td class="memname">#define SPI_FLASH_CS&#160;&#160;&#160;0</td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI flash chip select (low-active) at SPI.spi_csn_o(SPI_FLASH_CS) </p> + +</div> +</div> +<a id="a00924a8ba223b2ca0e7031259b292c84" name="a00924a8ba223b2ca0e7031259b292c84"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a00924a8ba223b2ca0e7031259b292c84">&#9670;&#160;</a></span>SPI_FLASH_SECTOR_SIZE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SPI_FLASH_SECTOR_SIZE&#160;&#160;&#160;65536</td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI flash sector size in bytes </p> + +</div> +</div> +<a id="aa9696325b450773c7a87c991abca3a54" name="aa9696325b450773c7a87c991abca3a54"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa9696325b450773c7a87c991abca3a54">&#9670;&#160;</a></span>STATUS_LED_EN</h2> + +<div class="memitem"> +<div class="memproto"> + <table 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name="af1c2f103ac6e3183f08b39099fab2be9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af1c2f103ac6e3183f08b39099fab2be9">&#9670;&#160;</a></span>UART_EN</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART_EN&#160;&#160;&#160;1</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set to 0 to disable UART interface </p> + +</div> +</div> +<a id="a20e93d623ce07939c3fdd53898f9d583" name="a20e93d623ce07939c3fdd53898f9d583"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a20e93d623ce07939c3fdd53898f9d583">&#9670;&#160;</a></span>UART_HW_HANDSHAKE_EN</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART_HW_HANDSHAKE_EN&#160;&#160;&#160;0</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set to 1 to enable UART HW handshaking </p> + +</div> +</div> +<a id="a2cf31934b909299fb93bb5eebdbc7c9e" name="a2cf31934b909299fb93bb5eebdbc7c9e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2cf31934b909299fb93bb5eebdbc7c9e">&#9670;&#160;</a></span>XIP_EN</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIP_EN&#160;&#160;&#160;1</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable XIP boot options </p> + +</div> +</div> +<a id="aff6b53dd58cea43d24393a9a2f79e772" name="aff6b53dd58cea43d24393a9a2f79e772"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aff6b53dd58cea43d24393a9a2f79e772">&#9670;&#160;</a></span>xstr</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define xstr</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>a</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_define" href="#af6cf19e40e97afb5a7c29f7b439d091d">str</a>(a)</div> +<div class="ttc" id="abootloader_8c_html_af6cf19e40e97afb5a7c29f7b439d091d"><div class="ttname"><a href="#af6cf19e40e97afb5a7c29f7b439d091d">str</a></div><div class="ttdeci">#define str(a)</div><div class="ttdef"><b>Definition</b> bootloader.c:187</div></div> +</div><!-- fragment --><p>Helper macros Actual define-to-string helper </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="aa0c639898508ff8e4fab6290101f3088" name="aa0c639898508ff8e4fab6290101f3088"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa0c639898508ff8e4fab6290101f3088">&#9670;&#160;</a></span>ERROR_CODES_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#aa0c639898508ff8e4fab6290101f3088">ERROR_CODES_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Error codes </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="aa0c639898508ff8e4fab6290101f3088ad41014563cb3ca69ab69b94d43e97caa" name="aa0c639898508ff8e4fab6290101f3088ad41014563cb3ca69ab69b94d43e97caa"></a>ERROR_SIGNATURE&#160;</td><td class="fielddoc"><p>0: Wrong signature in executable </p> +</td></tr> +<tr><td class="fieldname"><a id="aa0c639898508ff8e4fab6290101f3088a2d77ed1c715fb969a1faa01c71625f2d" name="aa0c639898508ff8e4fab6290101f3088a2d77ed1c715fb969a1faa01c71625f2d"></a>ERROR_SIZE&#160;</td><td class="fielddoc"><p>1: Insufficient instruction memory capacity </p> +</td></tr> +<tr><td class="fieldname"><a id="aa0c639898508ff8e4fab6290101f3088a471ebe6c0766abc6fa4e82a09bfdb985" name="aa0c639898508ff8e4fab6290101f3088a471ebe6c0766abc6fa4e82a09bfdb985"></a>ERROR_CHECKSUM&#160;</td><td class="fielddoc"><p>2: Checksum error in executable </p> +</td></tr> +<tr><td class="fieldname"><a id="aa0c639898508ff8e4fab6290101f3088a684d6723fa25e7651e13d99fb249363c" name="aa0c639898508ff8e4fab6290101f3088a684d6723fa25e7651e13d99fb249363c"></a>ERROR_FLASH&#160;</td><td class="fielddoc"><p>3: SPI flash access error </p> +</td></tr> +</table> + +</div> +</div> +<a id="abcbf77626fdd0b475d245f836eab7a83" name="abcbf77626fdd0b475d245f836eab7a83"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abcbf77626fdd0b475d245f836eab7a83">&#9670;&#160;</a></span>EXE_STREAM_SOURCE_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#abcbf77626fdd0b475d245f836eab7a83">EXE_STREAM_SOURCE_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executable stream source select (for copying into IMEM) </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="abcbf77626fdd0b475d245f836eab7a83ab149261ddf3f08e44e9d2538e384f58f" name="abcbf77626fdd0b475d245f836eab7a83ab149261ddf3f08e44e9d2538e384f58f"></a>EXE_STREAM_UART&#160;</td><td class="fielddoc"><p>Get executable via UART </p> +</td></tr> +<tr><td class="fieldname"><a id="abcbf77626fdd0b475d245f836eab7a83a98526cd8f81d570c57d98193b32cf114" name="abcbf77626fdd0b475d245f836eab7a83a98526cd8f81d570c57d98193b32cf114"></a>EXE_STREAM_FLASH&#160;</td><td class="fielddoc"><p>Get executable via SPI flash </p> +</td></tr> +</table> + +</div> +</div> +<a id="a165a347c51d8aae06a564a2f297f2feb" name="a165a347c51d8aae06a564a2f297f2feb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a165a347c51d8aae06a564a2f297f2feb">&#9670;&#160;</a></span>NEORV32_EXECUTABLE_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a165a347c51d8aae06a564a2f297f2feb">NEORV32_EXECUTABLE_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 executable </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a165a347c51d8aae06a564a2f297f2feba61100996f309c45b8b628ade2e3acc7f" name="a165a347c51d8aae06a564a2f297f2feba61100996f309c45b8b628ade2e3acc7f"></a>EXE_OFFSET_SIGNATURE&#160;</td><td class="fielddoc"><p>Offset in bytes from start to signature (32-bit) </p> +</td></tr> +<tr><td class="fieldname"><a id="a165a347c51d8aae06a564a2f297f2febacc430caa4bff2fef4568c757893fe2fe" name="a165a347c51d8aae06a564a2f297f2febacc430caa4bff2fef4568c757893fe2fe"></a>EXE_OFFSET_SIZE&#160;</td><td class="fielddoc"><p>Offset in bytes from start to size (32-bit) </p> +</td></tr> +<tr><td class="fieldname"><a id="a165a347c51d8aae06a564a2f297f2febabc27a855096a70dca0f8bc148a123be4" name="a165a347c51d8aae06a564a2f297f2febabc27a855096a70dca0f8bc148a123be4"></a>EXE_OFFSET_CHECKSUM&#160;</td><td class="fielddoc"><p>Offset in bytes from start to checksum (32-bit) </p> +</td></tr> +<tr><td class="fieldname"><a id="a165a347c51d8aae06a564a2f297f2febaea032c54a21057710ef2021638972ce6" name="a165a347c51d8aae06a564a2f297f2febaea032c54a21057710ef2021638972ce6"></a>EXE_OFFSET_DATA&#160;</td><td class="fielddoc"><p>Offset in bytes from start to data (32-bit) </p> +</td></tr> +</table> + +</div> +</div> +<a id="aa5e5723e4cbf83805c3b1197cd401fed" name="aa5e5723e4cbf83805c3b1197cd401fed"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa5e5723e4cbf83805c3b1197cd401fed">&#9670;&#160;</a></span>SPI_FLASH_CMD_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#aa5e5723e4cbf83805c3b1197cd401fed">SPI_FLASH_CMD_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI flash commands </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="aa5e5723e4cbf83805c3b1197cd401feda31c8d698c551d081a0adeafb988ed49e" name="aa5e5723e4cbf83805c3b1197cd401feda31c8d698c551d081a0adeafb988ed49e"></a>SPI_FLASH_CMD_PAGE_PROGRAM&#160;</td><td class="fielddoc"><p>Program page </p> +</td></tr> +<tr><td class="fieldname"><a id="aa5e5723e4cbf83805c3b1197cd401feda6c1994ba2cfd97e0c77dcdf8bbdfdfa6" name="aa5e5723e4cbf83805c3b1197cd401feda6c1994ba2cfd97e0c77dcdf8bbdfdfa6"></a>SPI_FLASH_CMD_READ&#160;</td><td class="fielddoc"><p>Read data </p> +</td></tr> +<tr><td class="fieldname"><a id="aa5e5723e4cbf83805c3b1197cd401fedaa91d3c1d788b21fc798a5976c9f0da77" name="aa5e5723e4cbf83805c3b1197cd401fedaa91d3c1d788b21fc798a5976c9f0da77"></a>SPI_FLASH_CMD_WRITE_DISABLE&#160;</td><td class="fielddoc"><p>Disallow write access </p> +</td></tr> +<tr><td class="fieldname"><a id="aa5e5723e4cbf83805c3b1197cd401feda5fbc6551a10549b38e5ab4a76c38f214" name="aa5e5723e4cbf83805c3b1197cd401feda5fbc6551a10549b38e5ab4a76c38f214"></a>SPI_FLASH_CMD_READ_STATUS&#160;</td><td class="fielddoc"><p>Get status register </p> +</td></tr> +<tr><td class="fieldname"><a id="aa5e5723e4cbf83805c3b1197cd401feda152e091e93778f217f8b766298351513" name="aa5e5723e4cbf83805c3b1197cd401feda152e091e93778f217f8b766298351513"></a>SPI_FLASH_CMD_WRITE_ENABLE&#160;</td><td class="fielddoc"><p>Allow write access </p> +</td></tr> +<tr><td class="fieldname"><a id="aa5e5723e4cbf83805c3b1197cd401feda25bf16cd42b1fd1d95e0957b5be137d2" name="aa5e5723e4cbf83805c3b1197cd401feda25bf16cd42b1fd1d95e0957b5be137d2"></a>SPI_FLASH_CMD_WAKE&#160;</td><td class="fielddoc"><p>Wake up from sleep mode </p> +</td></tr> +<tr><td class="fieldname"><a id="aa5e5723e4cbf83805c3b1197cd401fedacd62141d6331f66e31bd252e2a92b836" name="aa5e5723e4cbf83805c3b1197cd401fedacd62141d6331f66e31bd252e2a92b836"></a>SPI_FLASH_CMD_SECTOR_ERASE&#160;</td><td class="fielddoc"><p>Erase complete sector </p> +</td></tr> +</table> + +</div> +</div> +<a id="a97299f563ebc1fca4c663b025a15136f" name="a97299f563ebc1fca4c663b025a15136f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a97299f563ebc1fca4c663b025a15136f">&#9670;&#160;</a></span>SPI_FLASH_SREG_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a97299f563ebc1fca4c663b025a15136f">SPI_FLASH_SREG_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI flash status register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a97299f563ebc1fca4c663b025a15136fa133cd87673ce9a612da494583e03dae9" name="a97299f563ebc1fca4c663b025a15136fa133cd87673ce9a612da494583e03dae9"></a>FLASH_SREG_BUSY&#160;</td><td class="fielddoc"><p>Busy, write/erase in progress when set, read-only </p> +</td></tr> +<tr><td class="fieldname"><a id="a97299f563ebc1fca4c663b025a15136fa22e8c983d74430ea0930e37781e88bf9" name="a97299f563ebc1fca4c663b025a15136fa22e8c983d74430ea0930e37781e88bf9"></a>FLASH_SREG_WEL&#160;</td><td class="fielddoc"><p>Write access enabled when set, read-only </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="af13b4b3d5e6597feacf331e6d16b08e9" name="af13b4b3d5e6597feacf331e6d16b08e9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af13b4b3d5e6597feacf331e6d16b08e9">&#9670;&#160;</a></span>bootloader_trap_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void bootloader_trap_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Function prototypes</p> +<p>Bootloader trap handler. Used for the MTIME tick and to capture any other traps.</p> +<dl class="section note"><dt>Note</dt><dd>Since we have no runtime environment we have to use the interrupt attribute here. </dd></dl> + +</div> +</div> +<a id="ac18819795adb6dbdd52b0587e7fbb569" name="ac18819795adb6dbdd52b0587e7fbb569"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac18819795adb6dbdd52b0587e7fbb569">&#9670;&#160;</a></span>get_exe()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void get_exe </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>src</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get executable stream.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">src</td><td>Source of executable stream data. See <a class="el" href="#abcbf77626fdd0b475d245f836eab7a83">EXE_STREAM_SOURCE_enum</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac58d9f7dc79a549bde1cb50f619c19af" name="ac58d9f7dc79a549bde1cb50f619c19af"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac58d9f7dc79a549bde1cb50f619c19af">&#9670;&#160;</a></span>get_exe_word()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t get_exe_word </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>src</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get word from executable stream</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">src</td><td>Source of executable stream data. See <a class="el" href="#abcbf77626fdd0b475d245f836eab7a83">EXE_STREAM_SOURCE_enum</a>. </td></tr> + <tr><td class="paramname">addr</td><td>Address when accessing SPI flash. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>32-bit data word from stream. </dd></dl> + +</div> +</div> +<a id="a840291bc02cba5474a4cb46a9b9566fe" name="a840291bc02cba5474a4cb46a9b9566fe"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a840291bc02cba5474a4cb46a9b9566fe">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Sanity check: Base RV32I ISA only! Bootloader main. </p> + +</div> +</div> +<a id="a402ea961bfc2ffeee61e3a7c330b1559" name="a402ea961bfc2ffeee61e3a7c330b1559"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a402ea961bfc2ffeee61e3a7c330b1559">&#9670;&#160;</a></span>print_help()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void print_help </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print help menu. </p> + +</div> +</div> +<a id="a70b7d5c3b3ae97e4e72e84c4bc28fb8a" name="a70b7d5c3b3ae97e4e72e84c4bc28fb8a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a70b7d5c3b3ae97e4e72e84c4bc28fb8a">&#9670;&#160;</a></span>print_hex_word()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void print_hex_word </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print 32-bit number as 8-digit hexadecimal value (with "0x" suffix).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Number to print as hexadecimal. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ababfffe8e7036179e150ad3b9bda3a74" name="ababfffe8e7036179e150ad3b9bda3a74"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ababfffe8e7036179e150ad3b9bda3a74">&#9670;&#160;</a></span>save_exe()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void save_exe </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Store content of instruction memory to SPI flash. </p> + +</div> +</div> +<a id="a1919595ed2232aebb3e774b916ab1662" name="a1919595ed2232aebb3e774b916ab1662"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1919595ed2232aebb3e774b916ab1662">&#9670;&#160;</a></span>spi_flash_check()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int spi_flash_check </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if SPI and flash are available/working by making sure the WEL flag of the flash status register can be set and cleared again.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if success, -1 if error </dd></dl> + +</div> +</div> +<a id="a0d877f0611dfcee32a483c8a3660eb1b" name="a0d877f0611dfcee32a483c8a3660eb1b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0d877f0611dfcee32a483c8a3660eb1b">&#9670;&#160;</a></span>spi_flash_erase_sector()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_flash_erase_sector </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Erase sector (64kB) at base address.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Base address of sector to erase. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a09e72e2debdd94929b2be4c7713d5e17" name="a09e72e2debdd94929b2be4c7713d5e17"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a09e72e2debdd94929b2be4c7713d5e17">&#9670;&#160;</a></span>spi_flash_read_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t spi_flash_read_byte </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read byte from SPI flash.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Flash read address. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Read byte from SPI flash. </dd></dl> + +</div> +</div> +<a id="a005966cd0b32f3d5c041028c4b1c99f5" name="a005966cd0b32f3d5c041028c4b1c99f5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a005966cd0b32f3d5c041028c4b1c99f5">&#9670;&#160;</a></span>spi_flash_read_status()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t spi_flash_read_status </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read flash status register.</p> +<dl class="section return"><dt>Returns</dt><dd>SPI flash status register (32-bit zero-extended). </dd></dl> + +</div> +</div> +<a id="a1fbdccc60f05756213c9f3d64bac6d47" name="a1fbdccc60f05756213c9f3d64bac6d47"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1fbdccc60f05756213c9f3d64bac6d47">&#9670;&#160;</a></span>spi_flash_wakeup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_flash_wakeup </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Wake up flash from deep sleep state </p> + +</div> +</div> +<a id="a6a8caddda6e729d747726471b0b0f742" name="a6a8caddda6e729d747726471b0b0f742"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6a8caddda6e729d747726471b0b0f742">&#9670;&#160;</a></span>spi_flash_write_addr()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_flash_write_addr </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send address word to flash (MSB-first, 16-bit, 24-bit or 32-bit address size).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address word. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a006c27b7d80897b78ab8cd83a391331f" name="a006c27b7d80897b78ab8cd83a391331f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a006c27b7d80897b78ab8cd83a391331f">&#9670;&#160;</a></span>spi_flash_write_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_flash_write_byte </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write byte to SPI flash.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>SPI flash read address. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>SPI flash read data. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a82d26a2d6293ed7fd44a5c622adfbd45" name="a82d26a2d6293ed7fd44a5c622adfbd45"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a82d26a2d6293ed7fd44a5c622adfbd45">&#9670;&#160;</a></span>spi_flash_write_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_flash_write_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable flash write access. </p> + +</div> +</div> +<a id="a9642e28ef2baec5b356ad9a70970d0e6" name="a9642e28ef2baec5b356ad9a70970d0e6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9642e28ef2baec5b356ad9a70970d0e6">&#9670;&#160;</a></span>spi_flash_write_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_flash_write_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable flash write access. </p> + +</div> +</div> +<a id="a717c72166af7c2ff7e73bd0b47128338" name="a717c72166af7c2ff7e73bd0b47128338"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a717c72166af7c2ff7e73bd0b47128338">&#9670;&#160;</a></span>spi_flash_write_word()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_flash_write_word </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write word to SPI flash.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">addr</td><td>SPI flash write address. </td></tr> + <tr><td class="paramname">wdata</td><td>SPI flash write data. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ae8de91537ac2782f0f0ebc3b2d4fb1df" name="ae8de91537ac2782f0f0ebc3b2d4fb1df"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae8de91537ac2782f0f0ebc3b2d4fb1df">&#9670;&#160;</a></span>start_app()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void start_app </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>boot_xip</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Start application program.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">boot_xip</td><td>Set to boot via XIP. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a3bdfe2f25b1bfb42f80624ffff22ab01" name="a3bdfe2f25b1bfb42f80624ffff22ab01"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3bdfe2f25b1bfb42f80624ffff22ab01">&#9670;&#160;</a></span>system_error()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void system_error </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>err_code</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Output system error ID and halt.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">err_code</td><td>Error code. See #ERROR_CODES and <a class="el" href="#a6fea855ffe2fa0cd5ea9f98c0d5adc4d">error_message</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a id="a6fea855ffe2fa0cd5ea9f98c0d5adc4d" name="a6fea855ffe2fa0cd5ea9f98c0d5adc4d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6fea855ffe2fa0cd5ea9f98c0d5adc4d">&#9670;&#160;</a></span>error_message</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const char error_message[4][5]</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Initial value:</b><div class="fragment"><div class="line">= {</div> +<div class="line"> <span class="stringliteral">&quot;EXE&quot;</span>,</div> +<div class="line"> <span class="stringliteral">&quot;SIZE&quot;</span>,</div> +<div class="line"> <span class="stringliteral">&quot;CHKS&quot;</span>,</div> +<div class="line"> <span class="stringliteral">&quot;FLSH&quot;</span></div> +<div class="line">}</div> +</div><!-- fragment --><p>Error messages </p> + +</div> +</div> +<a id="a0f9fcfdf758260b9b79b6eda063dd87a" name="a0f9fcfdf758260b9b79b6eda063dd87a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0f9fcfdf758260b9b79b6eda063dd87a">&#9670;&#160;</a></span>exe_available</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">volatile uint32_t exe_available</td> + </tr> + </table> +</div><div class="memdoc"> +<p>This global variable keeps the size of the available executable in bytes. If =0 no executable is available (yet). </p> + +</div> +</div> +<a id="a5fa6b109bf211d1768f84c9d38eef240" name="a5fa6b109bf211d1768f84c9d38eef240"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5fa6b109bf211d1768f84c9d38eef240">&#9670;&#160;</a></span>getting_exe</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">volatile uint32_t getting_exe</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Only set during executable fetch (required for capturing STORE BUS-TIMOUT exception). </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/bus__explorer_2main_8c.html b/sw/bus__explorer_2main_8c.html new file mode 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class="summary"> +<a href="#func-members">Functions</a> &#124; +<a href="#var-members">Variables</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Interactive memory inspector. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:afc9b1ab3db46eccf51d55c715fa2fbd4" id="r_afc9b1ab3db46eccf51d55c715fa2fbd4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afc9b1ab3db46eccf51d55c715fa2fbd4">read_memory</a> (uint32_t address)</td></tr> +<tr class="separator:afc9b1ab3db46eccf51d55c715fa2fbd4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2b6196c2e97a7f7702c0068780304ec1" id="r_a2b6196c2e97a7f7702c0068780304ec1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2b6196c2e97a7f7702c0068780304ec1">setup_access</a> (void)</td></tr> +<tr class="separator:a2b6196c2e97a7f7702c0068780304ec1"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a96729fb5279642ac56c8e6a513789b45" id="r_a96729fb5279642ac56c8e6a513789b45"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a96729fb5279642ac56c8e6a513789b45">write_memory</a> (uint32_t address, uint32_t data)</td></tr> +<tr class="separator:a96729fb5279642ac56c8e6a513789b45"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6405739c6012158151eb082c31c312da" id="r_a6405739c6012158151eb082c31c312da"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6405739c6012158151eb082c31c312da">dump_memory</a> (uint32_t address)</td></tr> +<tr class="separator:a6405739c6012158151eb082c31c312da"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a02640a99db37b8d92b9edffc9720a210" id="r_a02640a99db37b8d92b9edffc9720a210"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a02640a99db37b8d92b9edffc9720a210">hexdump</a> (uint32_t address)</td></tr> +<tr class="separator:a02640a99db37b8d92b9edffc9720a210"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac582208281cd6fce4eb61c234f312ef6" id="r_ac582208281cd6fce4eb61c234f312ef6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac582208281cd6fce4eb61c234f312ef6">aux_print_hex_byte</a> (uint8_t byte)</td></tr> +<tr class="separator:ac582208281cd6fce4eb61c234f312ef6"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a12606de4f336516339c495642a436032" id="r_a12606de4f336516339c495642a436032"><td class="memItemLeft" align="right" valign="top"><a id="a12606de4f336516339c495642a436032" name="a12606de4f336516339c495642a436032"></a> +char&#160;</td><td class="memItemRight" valign="bottom"><b>access_size</b></td></tr> +<tr class="separator:a12606de4f336516339c495642a436032"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Interactive memory inspector. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ac582208281cd6fce4eb61c234f312ef6" name="ac582208281cd6fce4eb61c234f312ef6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac582208281cd6fce4eb61c234f312ef6">&#9670;&#160;</a></span>aux_print_hex_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void aux_print_hex_byte </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>byte</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print HEX byte.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Byte to be printed as 2-cahr hex value. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a6405739c6012158151eb082c31c312da" name="a6405739c6012158151eb082c31c312da"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6405739c6012158151eb082c31c312da">&#9670;&#160;</a></span>dump_memory()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void dump_memory </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>address</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read several bytes/halfs/word from memory base address </p> + +</div> +</div> +<a id="a02640a99db37b8d92b9edffc9720a210" name="a02640a99db37b8d92b9edffc9720a210"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a02640a99db37b8d92b9edffc9720a210">&#9670;&#160;</a></span>hexdump()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void hexdump </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>address</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Make pretty hexadecimal + ASCII dump (byte-wise) </p> + +</div> +</div> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This program provides an interactive console to read/write memory.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the UART to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +<a id="afc9b1ab3db46eccf51d55c715fa2fbd4" name="afc9b1ab3db46eccf51d55c715fa2fbd4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afc9b1ab3db46eccf51d55c715fa2fbd4">&#9670;&#160;</a></span>read_memory()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void read_memory </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>address</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read from memory address </p> + +</div> +</div> +<a id="a2b6196c2e97a7f7702c0068780304ec1" name="a2b6196c2e97a7f7702c0068780304ec1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2b6196c2e97a7f7702c0068780304ec1">&#9670;&#160;</a></span>setup_access()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void setup_access </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure memory access size </p> + +</div> +</div> +<a id="a96729fb5279642ac56c8e6a513789b45" name="a96729fb5279642ac56c8e6a513789b45"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a96729fb5279642ac56c8e6a513789b45">&#9670;&#160;</a></span>write_memory()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void write_memory </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>address</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>data</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write to memory address </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/classes.html b/sw/classes.html new file mode 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remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script 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class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_9a1c128d67c35790e92af404beb936aa.html">demo_blink_led</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Minimal blinking LED demo program using the lowest 8 bits of the GPIO.output port. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Minimal blinking LED demo program using the lowest 8 bits of the GPIO.output port. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function; shows an incrementing 8-bit counter on GPIO.output(7:0).</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the GPIO controller to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Will never return. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__cfs_2main_8c.html b/sw/demo__cfs_2main_8c.html new file mode 100644 index 000000000..384c3f830 --- /dev/null +++ b/sw/demo__cfs_2main_8c.html @@ -0,0 +1,178 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_cfs/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" 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+<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license 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href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_01cde3d98944a579dc3b5e43a5311a79.html">demo_cfs</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Simple demo program for the <em>default</em> custom functions subsystem (CFS) module. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a906949f076e3e0d0082af3c3b1acb518" id="r_a906949f076e3e0d0082af3c3b1acb518"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a906949f076e3e0d0082af3c3b1acb518">TESTCASES</a>&#160;&#160;&#160;4</td></tr> +<tr class="separator:a906949f076e3e0d0082af3c3b1acb518"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Simple demo program for the <em>default</em> custom functions subsystem (CFS) module. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a906949f076e3e0d0082af3c3b1acb518" name="a906949f076e3e0d0082af3c3b1acb518"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a906949f076e3e0d0082af3c3b1acb518">&#9670;&#160;</a></span>TESTCASES</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TESTCASES&#160;&#160;&#160;4</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Number of test cases per CFS function </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the CFS and UART0.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__cfu_2main_8c.html b/sw/demo__cfu_2main_8c.html new file mode 100644 index 000000000..d16fea2ee --- /dev/null +++ b/sw/demo__cfu_2main_8c.html @@ -0,0 +1,600 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onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_09a89dfa1596b6613cf2c29528a32844.html">demo_cfu</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Example program showing how to use the CFU's custom instructions (XTEA example). +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr 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id="r_a0ff5df4be3476f4e7756c472f2644726"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0ff5df4be3476f4e7756c472f2644726">xtea_hw_init</a>(sum)</td></tr> +<tr class="separator:a0ff5df4be3476f4e7756c472f2644726"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8fddbd0364944fa3dca477599079c78e" id="r_a8fddbd0364944fa3dca477599079c78e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8fddbd0364944fa3dca477599079c78e">xtea_hw_enc_v0_step</a>(v0, v1)</td></tr> +<tr class="separator:a8fddbd0364944fa3dca477599079c78e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af6c6097c851dc97679d939d0d506342c" id="r_af6c6097c851dc97679d939d0d506342c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a094212e3731a9aecbd278fac243de6ec">time_enc_hw</a></td></tr> +<tr class="separator:a094212e3731a9aecbd278fac243de6ec"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2d3853c367c3bce99e787c0df445030a" id="r_a2d3853c367c3bce99e787c0df445030a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2d3853c367c3bce99e787c0df445030a">time_dec_sw</a></td></tr> +<tr class="separator:a2d3853c367c3bce99e787c0df445030a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acb6dd9d6ab74ac94f174a11ff3ad76af" id="r_acb6dd9d6ab74ac94f174a11ff3ad76af"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acb6dd9d6ab74ac94f174a11ff3ad76af">time_dec_hw</a></td></tr> +<tr class="separator:acb6dd9d6ab74ac94f174a11ff3ad76af"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Example program showing how to use the CFU's custom instructions (XTEA example). </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Take a look at the highly-commented "hardware-counterpart" of this CFU example in 'rtl/core/neorv32_cpu_cp_cfu.vhd'. </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + 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class="permalink"><a href="#af139f37dd13866ecb4aa9002ac8f798e">&#9670;&#160;</a></span>xtea_hw_dec_v1_step</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define xtea_hw_dec_v1_step</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>v0</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>v1</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_define" href="neorv32__cpu__cfu_8h.html#a69d60ccd0cee950b08ce585c3f13b85c">neorv32_cfu_r3_instr</a>(0b0000000, 0b011, v0, v1)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a8fddbd0364944fa3dca477599079c78e" name="a8fddbd0364944fa3dca477599079c78e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8fddbd0364944fa3dca477599079c78e">&#9670;&#160;</a></span>xtea_hw_enc_v0_step</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define xtea_hw_enc_v0_step</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>v0</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>v1</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_define" href="neorv32__cpu__cfu_8h.html#a69d60ccd0cee950b08ce585c3f13b85c">neorv32_cfu_r3_instr</a>(0b0000000, 0b000, v0, v1)</div> +</div><!-- fragment --> +</div> +</div> +<a id="af6c6097c851dc97679d939d0d506342c" name="af6c6097c851dc97679d939d0d506342c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af6c6097c851dc97679d939d0d506342c">&#9670;&#160;</a></span>xtea_hw_enc_v1_step</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define xtea_hw_enc_v1_step</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>v0</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>v1</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_define" href="neorv32__cpu__cfu_8h.html#a69d60ccd0cee950b08ce585c3f13b85c">neorv32_cfu_r3_instr</a>(0b0000000, 0b001, v0, v1)</div> +</div><!-- fragment --> +</div> +</div> +<a id="aaa2516cd7853e9c7c274cb3de35cb2d5" name="aaa2516cd7853e9c7c274cb3de35cb2d5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaa2516cd7853e9c7c274cb3de35cb2d5">&#9670;&#160;</a></span>xtea_hw_illegal_inst</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define xtea_hw_illegal_inst</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_define" href="neorv32__cpu__cfu_8h.html#a69d60ccd0cee950b08ce585c3f13b85c">neorv32_cfu_r3_instr</a>(0b0000000, 0b111, 0, 0 )</div> +</div><!-- fragment --> +</div> +</div> +<a id="a0ff5df4be3476f4e7756c472f2644726" name="a0ff5df4be3476f4e7756c472f2644726"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0ff5df4be3476f4e7756c472f2644726">&#9670;&#160;</a></span>xtea_hw_init</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define xtea_hw_init</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>sum</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_define" href="neorv32__cpu__cfu_8h.html#a69d60ccd0cee950b08ce585c3f13b85c">neorv32_cfu_r3_instr</a>(0b0000000, 0b100, sum, 0 )</div> +</div><!-- fragment --> +</div> +</div> +<a id="a36801eebef583b6c3438709144834e3e" name="a36801eebef583b6c3438709144834e3e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a36801eebef583b6c3438709144834e3e">&#9670;&#160;</a></span>XTEA_ROUNDS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XTEA_ROUNDS&#160;&#160;&#160;20</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Number XTEA rounds </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function: run pure-SW XTEA and compare with HW-accelerated XTEA</p> +<dl class="section note"><dt>Note</dt><dd>This program requires UART0 and the Zxcfu and Zicntr ISA extension.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +<a id="a0e980c5d81b1eca90b8073e54099bdb0" name="a0e980c5d81b1eca90b8073e54099bdb0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0e980c5d81b1eca90b8073e54099bdb0">&#9670;&#160;</a></span>xtea_sw_decipher()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void xtea_sw_decipher </td> + <td>(</td> + <td class="paramtype">unsigned int</td> <td class="paramname"><span class="paramname"><em>num_cycles</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t *</td> <td class="paramname"><span class="paramname"><em>v</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const uint32_t</td> <td class="paramname"><span class="paramname"><em>k</em></span>[4]&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XTEA decryption - software reference Source: <a href="https://de.wikipedia.org/wiki/Extended_Tiny_Encryption_Algorithm">https://de.wikipedia.org/wiki/Extended_Tiny_Encryption_Algorithm</a></p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">num_cycles</td><td>Number of encryption cycles. </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">v</td><td>Decryption data/result array (2x32-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">k</td><td>Decryption key array (4x32-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a8dc502bf508491eed1f39c4acf040efb" name="a8dc502bf508491eed1f39c4acf040efb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8dc502bf508491eed1f39c4acf040efb">&#9670;&#160;</a></span>xtea_sw_encipher()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void xtea_sw_encipher </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num_cycles</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t *</td> <td class="paramname"><span class="paramname"><em>v</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const uint32_t</td> <td class="paramname"><span class="paramname"><em>k</em></span>[4]&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XTEA encryption - software reference Source: <a href="https://de.wikipedia.org/wiki/Extended_Tiny_Encryption_Algorithm">https://de.wikipedia.org/wiki/Extended_Tiny_Encryption_Algorithm</a></p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">num_cycles</td><td>Number of encryption cycles. </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">v</td><td>Encryption data/result array (2x32-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">k</td><td>Encryption key array (4x32-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a id="a9ad2780a4cfe0d9cb4f1a846a92063ae" name="a9ad2780a4cfe0d9cb4f1a846a92063ae"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9ad2780a4cfe0d9cb4f1a846a92063ae">&#9670;&#160;</a></span>cypher_data_hw</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t cypher_data_hw[<a class="el" href="#ac637695e266f3af7799e352b374412ad">DATA_NUM</a>]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XTEA delta (round-key update); do not change </p> + +</div> +</div> +<a id="a33b2d9298edf94c5961e67a59c371d00" name="a33b2d9298edf94c5961e67a59c371d00"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a33b2d9298edf94c5961e67a59c371d00">&#9670;&#160;</a></span>cypher_data_sw</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t cypher_data_sw[<a class="el" href="#ac637695e266f3af7799e352b374412ad">DATA_NUM</a>]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Encryption result buffer </p> + +</div> +</div> +<a id="a2e2ccb9136736a673dbef71f207e97a0" name="a2e2ccb9136736a673dbef71f207e97a0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2e2ccb9136736a673dbef71f207e97a0">&#9670;&#160;</a></span>input_data</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t input_data[<a class="el" href="#ac637695e266f3af7799e352b374412ad">DATA_NUM</a>]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Encryption input data </p> + +</div> +</div> +<a id="ab5c498f9da12ab2d6ddc89bf4a46dec6" name="ab5c498f9da12ab2d6ddc89bf4a46dec6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab5c498f9da12ab2d6ddc89bf4a46dec6">&#9670;&#160;</a></span>key</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const uint32_t key[4] = {0x207230ba, 0x1ffba710, 0xc45271ef, 0xdd01768a}</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Secret encryption/decryption key (128-bit) </p> + +</div> +</div> +<a id="aee8dde13fe2f5ac52dd6075e2fe1eab5" name="aee8dde13fe2f5ac52dd6075e2fe1eab5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aee8dde13fe2f5ac52dd6075e2fe1eab5">&#9670;&#160;</a></span>plain_data_hw</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t plain_data_hw[<a class="el" href="#ac637695e266f3af7799e352b374412ad">DATA_NUM</a>]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XTEA delta (round-key update); do not change </p> + +</div> +</div> +<a id="a72ba1460776ad684028448ca51810bbe" name="a72ba1460776ad684028448ca51810bbe"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a72ba1460776ad684028448ca51810bbe">&#9670;&#160;</a></span>plain_data_sw</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t plain_data_sw[<a class="el" href="#ac637695e266f3af7799e352b374412ad">DATA_NUM</a>]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Decryption result buffer </p> + +</div> +</div> +<a id="acb6dd9d6ab74ac94f174a11ff3ad76af" name="acb6dd9d6ab74ac94f174a11ff3ad76af"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acb6dd9d6ab74ac94f174a11ff3ad76af">&#9670;&#160;</a></span>time_dec_hw</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t time_dec_hw</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XTEA delta (round-key update); do not change </p> + +</div> +</div> +<a id="a2d3853c367c3bce99e787c0df445030a" name="a2d3853c367c3bce99e787c0df445030a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2d3853c367c3bce99e787c0df445030a">&#9670;&#160;</a></span>time_dec_sw</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t time_dec_sw</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XTEA delta (round-key update); do not change </p> + +</div> +</div> +<a id="a094212e3731a9aecbd278fac243de6ec" name="a094212e3731a9aecbd278fac243de6ec"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a094212e3731a9aecbd278fac243de6ec">&#9670;&#160;</a></span>time_enc_hw</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t time_enc_hw</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XTEA delta (round-key update); do not change </p> + +</div> +</div> +<a id="ad424a26173bd8d84b8d1cae94a55f248" name="ad424a26173bd8d84b8d1cae94a55f248"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad424a26173bd8d84b8d1cae94a55f248">&#9670;&#160;</a></span>time_enc_sw</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t time_enc_sw</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Timing data </p> + +</div> +</div> +<a id="a26da64691624f3c899f2394a427d6593" name="a26da64691624f3c899f2394a427d6593"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a26da64691624f3c899f2394a427d6593">&#9670;&#160;</a></span>xtea_delta</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const uint32_t xtea_delta = 0x9e3779b9</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XTEA delta (round-key update); do not change </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__crc_2main_8c.html b/sw/demo__crc_2main_8c.html new file mode 100644 index 000000000..b70c99008 --- /dev/null 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+ onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_bf935196a1ea0ca9cb42aae56d70946a.html">demo_crc</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> &#124; +<a href="#var-members">Variables</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>CRC demo program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a61cf3bdb35d76183cca44c4496ed39a1" id="r_a61cf3bdb35d76183cca44c4496ed39a1"><td class="memItemLeft" align="right" valign="top"><a id="a61cf3bdb35d76183cca44c4496ed39a1" name="a61cf3bdb35d76183cca44c4496ed39a1"></a> +const uint8_t&#160;</td><td class="memItemRight" valign="bottom"><b>test_string</b> [] = {0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x00}</td></tr> +<tr class="separator:a61cf3bdb35d76183cca44c4496ed39a1"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>CRC demo program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Simple demo program to showcase the NEORV32 CRC unit.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires UART0 and the CRC unit to be synthesized. The DMA controller is optional.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Irrelevant. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__dma_2main_8c.html b/sw/demo__dma_2main_8c.html new file mode 100644 index 000000000..83b38a0bb --- /dev/null +++ b/sw/demo__dma_2main_8c.html @@ -0,0 +1,212 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 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cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_8c514361e1f16692c783b23503f30f16.html">demo_dma</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> &#124; +<a href="#var-members">Variables</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>DMA demo program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a8ad0c7bfd07edb6d42d86b166347206b" id="r_a8ad0c7bfd07edb6d42d86b166347206b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8ad0c7bfd07edb6d42d86b166347206b">show_arrays</a> (void)</td></tr> +<tr class="separator:a8ad0c7bfd07edb6d42d86b166347206b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aefcc5abb86a652587ff69be120a66487" id="r_aefcc5abb86a652587ff69be120a66487"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aefcc5abb86a652587ff69be120a66487">dma_firq_handler</a> (void)</td></tr> +<tr class="separator:aefcc5abb86a652587ff69be120a66487"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a5d49f871680881f4a84770fc76e40b77" id="r_a5d49f871680881f4a84770fc76e40b77"><td class="memItemLeft" align="right" valign="top"><a id="a5d49f871680881f4a84770fc76e40b77" name="a5d49f871680881f4a84770fc76e40b77"></a> +volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>dma_src</b> [4]</td></tr> +<tr class="separator:a5d49f871680881f4a84770fc76e40b77"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a71821daf63f808350ae702ca7edb38e2" id="r_a71821daf63f808350ae702ca7edb38e2"><td class="memItemLeft" align="right" valign="top"><a id="a71821daf63f808350ae702ca7edb38e2" name="a71821daf63f808350ae702ca7edb38e2"></a> +volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>dma_dst</b> [4]</td></tr> +<tr class="separator:a71821daf63f808350ae702ca7edb38e2"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>DMA demo program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="aefcc5abb86a652587ff69be120a66487" name="aefcc5abb86a652587ff69be120a66487"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aefcc5abb86a652587ff69be120a66487">&#9670;&#160;</a></span>dma_firq_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void dma_firq_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA FIRQ handler.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function has to be of type "void xyz(void)" and must not use any interrupt attributes! </dd></dl> + +</div> +</div> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Simple demo program to showcase the NEORV32 DMA controller.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires UART0 and the DMA controller to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Irrelevant. </dd></dl> + +</div> +</div> +<a id="a8ad0c7bfd07edb6d42d86b166347206b" name="a8ad0c7bfd07edb6d42d86b166347206b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8ad0c7bfd07edb6d42d86b166347206b">&#9670;&#160;</a></span>show_arrays()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void show_arrays </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print test data arrays </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__emulate__unaligned_2main_8c.html b/sw/demo__emulate__unaligned_2main_8c.html new file mode 100644 index 000000000..f3c9f0993 --- /dev/null +++ b/sw/demo__emulate__unaligned_2main_8c.html @@ -0,0 +1,216 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_emulate_unaligned/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_2ba96d3140b089dada6fb9f817b7975f.html">demo_emulate_unaligned</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Demo program for emulating unaligned memory accesses using the NEORV32 run-time environment (RTE). +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4407b4d6eae3ba7fe9538b1242a7e165" id="r_a4407b4d6eae3ba7fe9538b1242a7e165"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4407b4d6eae3ba7fe9538b1242a7e165">DEBUG_INFO</a>&#160;&#160;&#160;0</td></tr> +<tr class="separator:a4407b4d6eae3ba7fe9538b1242a7e165"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">Global variables</h2></td></tr> +<tr class="memitem:a556f675911f865ead06c36072b1b9c3b" id="r_a556f675911f865ead06c36072b1b9c3b"><td class="memItemLeft" align="right" valign="top">volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a556f675911f865ead06c36072b1b9c3b">data_block</a> [2]</td></tr> +<tr class="separator:a556f675911f865ead06c36072b1b9c3b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a07da42351229525998965b219e827460" id="r_a07da42351229525998965b219e827460"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a07da42351229525998965b219e827460">trap_handler_emulate_unaligned_lw</a> (void)</td></tr> +<tr class="separator:a07da42351229525998965b219e827460"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Demo program for emulating unaligned memory accesses using the NEORV32 run-time environment (RTE). </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a4407b4d6eae3ba7fe9538b1242a7e165" name="a4407b4d6eae3ba7fe9538b1242a7e165"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4407b4d6eae3ba7fe9538b1242a7e165">&#9670;&#160;</a></span>DEBUG_INFO</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DEBUG_INFO&#160;&#160;&#160;0</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Show debug info when 1 </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Demo program to showcase RTE-based emulation of unaligned memory accesses.</p> +<dl class="section return"><dt>Returns</dt><dd>Irrelevant. </dd></dl> + +</div> +</div> +<a id="a07da42351229525998965b219e827460" name="a07da42351229525998965b219e827460"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a07da42351229525998965b219e827460">&#9670;&#160;</a></span>trap_handler_emulate_unaligned_lw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void trap_handler_emulate_unaligned_lw </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Emulate unaligned load-word operation</p> +<dl class="section note"><dt>Note</dt><dd>This is a RTE "second-level" trap handler.</dd></dl> +<dl class="section warning"><dt>Warning</dt><dd>Compressed load instructions are not supported here! </dd></dl> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a id="a556f675911f865ead06c36072b1b9c3b" name="a556f675911f865ead06c36072b1b9c3b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a556f675911f865ead06c36072b1b9c3b">&#9670;&#160;</a></span>data_block</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">volatile uint32_t data_block[2]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Emulate unaligned load-word operation</p> +<dl class="section note"><dt>Note</dt><dd>This is a RTE "second-level" trap handler.</dd></dl> +<dl class="section warning"><dt>Warning</dt><dd>Compressed load instructions are not supported here! </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__gptmr_2main_8c.html b/sw/demo__gptmr_2main_8c.html new file mode 100644 index 000000000..e38b6f42d --- /dev/null +++ b/sw/demo__gptmr_2main_8c.html @@ -0,0 +1,182 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_gptmr/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_b68ac2efc0c6ed3018151f7bb6c45670.html">demo_gptmr</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Simple GPTMR timer-match interrupt example. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a2bd89412466a65329711bfd5c29199c9" id="r_a2bd89412466a65329711bfd5c29199c9"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2bd89412466a65329711bfd5c29199c9">gptmr_firq_handler</a> (void)</td></tr> +<tr class="separator:a2bd89412466a65329711bfd5c29199c9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Simple GPTMR timer-match interrupt example. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a2bd89412466a65329711bfd5c29199c9" name="a2bd89412466a65329711bfd5c29199c9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2bd89412466a65329711bfd5c29199c9">&#9670;&#160;</a></span>gptmr_firq_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void gptmr_firq_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>GPTMR FIRQ handler.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function has to be of type "void xyz(void)" and must not use any interrupt attributes! </dd></dl> + +</div> +</div> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This program blinks an LED at GPIO.output(0) at 1Hz using the general purpose timer interrupt.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the GPTMR unit to be synthesized (and UART0 and GPIO).</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Should not return. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__hpm_2main_8c.html b/sw/demo__hpm_2main_8c.html new file mode 100644 index 000000000..1c4b6ef53 --- /dev/null +++ b/sw/demo__hpm_2main_8c.html @@ -0,0 +1,161 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_93967190e0d2e549ceca77007097849b.html">demo_hpm</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Hardware performance monitor (HPM) example program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Hardware performance monitor (HPM) example program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the CPU Zihpm extension (with at least 2 regions) and UART0.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__mtime_2main_8c.html b/sw/demo__mtime_2main_8c.html new file mode 100644 index 000000000..b00598e21 --- /dev/null +++ b/sw/demo__mtime_2main_8c.html @@ -0,0 +1,174 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_mtime/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script 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by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_8d341cbe0581f44e1ae95d82d74e8bc8.html">demo_mtime</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#define-members">Macros</a> &#124; +<a href="#func-members">Functions</a> &#124; +<a href="#var-members">Variables</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Simple machine timer (MTIME) usage example. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top"><a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>BAUD_RATE</b>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a329137855a7c2e098715a0771c5585d7" id="r_a329137855a7c2e098715a0771c5585d7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a329137855a7c2e098715a0771c5585d7">mtime_irq_handler</a> (void)</td></tr> +<tr class="separator:a329137855a7c2e098715a0771c5585d7"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a8cc234243e9622043b343cde3d4dccac" id="r_a8cc234243e9622043b343cde3d4dccac"><td class="memItemLeft" align="right" valign="top"><a id="a8cc234243e9622043b343cde3d4dccac" name="a8cc234243e9622043b343cde3d4dccac"></a> +const char&#160;</td><td class="memItemRight" valign="bottom"><b>weekdays</b> [7][4] = {&quot;Mon&quot;, &quot;Tue&quot;, &quot;Wed&quot;, &quot;Thu&quot;, &quot;Fri&quot;, &quot;Sat&quot;, &quot;Sun&quot;}</td></tr> +<tr class="separator:a8cc234243e9622043b343cde3d4dccac"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Simple machine timer (MTIME) usage example. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This program toggles an LED at GPIO.output(0) at 1Hz and also prints and updates the Unix time in human-readable format using the machine timer interrupt.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the MTIME unit to be synthesized (and UART0 and GPIO).</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Should not return. </dd></dl> + +</div> +</div> +<a id="a329137855a7c2e098715a0771c5585d7" name="a329137855a7c2e098715a0771c5585d7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a329137855a7c2e098715a0771c5585d7">&#9670;&#160;</a></span>mtime_irq_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void mtime_irq_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MTIME IRQ handler.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function has to be of type "void xyz(void)" and must not use any interrupt attributes! </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__neopixel_2main_8c.html b/sw/demo__neopixel_2main_8c.html new file mode 100644 index 000000000..ff0d1e47d --- /dev/null +++ b/sw/demo__neopixel_2main_8c.html @@ -0,0 +1,228 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_neopixel/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div 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class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_d68bb921df3f2482fe9ace49b286ab86.html">demo_neopixel</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>NeoPixel (WS2812) interface demo using the processor's smart LED interface (NEOLED). +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa1dddb8d6b3b4d2f19afc3c09e2ff572" id="r_aa1dddb8d6b3b4d2f19afc3c09e2ff572"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa1dddb8d6b3b4d2f19afc3c09e2ff572">NUM_LEDS_24BIT</a>&#160;&#160;&#160;(12)</td></tr> +<tr class="separator:aa1dddb8d6b3b4d2f19afc3c09e2ff572"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1d1d5e7ff16f25b68fdf779befd298f7" id="r_a1d1d5e7ff16f25b68fdf779befd298f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1d1d5e7ff16f25b68fdf779befd298f7">MAX_INTENSITY</a>&#160;&#160;&#160;(16)</td></tr> +<tr class="separator:a1d1d5e7ff16f25b68fdf779befd298f7"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a2736ec755f9e10c80bf66f727f870ffc" id="r_a2736ec755f9e10c80bf66f727f870ffc"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2736ec755f9e10c80bf66f727f870ffc">hsv2rgb</a> (int h, int v)</td></tr> +<tr class="separator:a2736ec755f9e10c80bf66f727f870ffc"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>NeoPixel (WS2812) interface demo using the processor's smart LED interface (NEOLED). </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a1d1d5e7ff16f25b68fdf779befd298f7" name="a1d1d5e7ff16f25b68fdf779befd298f7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1d1d5e7ff16f25b68fdf779befd298f7">&#9670;&#160;</a></span>MAX_INTENSITY</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define MAX_INTENSITY&#160;&#160;&#160;(16)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Max intensity (0..255) </p> + +</div> +</div> +<a id="aa1dddb8d6b3b4d2f19afc3c09e2ff572" name="aa1dddb8d6b3b4d2f19afc3c09e2ff572"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa1dddb8d6b3b4d2f19afc3c09e2ff572">&#9670;&#160;</a></span>NUM_LEDS_24BIT</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NUM_LEDS_24BIT&#160;&#160;&#160;(12)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Number of RGB LEDs in stripe (24-bit data) </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a2736ec755f9e10c80bf66f727f870ffc" name="a2736ec755f9e10c80bf66f727f870ffc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2736ec755f9e10c80bf66f727f870ffc">&#9670;&#160;</a></span>hsv2rgb()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t hsv2rgb </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>h</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>v</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Convert HSV color to RGB.</p> +<dl class="section note"><dt>Note</dt><dd>Very simple version: using integer arithmetic and ignoring saturation (saturation is always MAX).</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">h</td><td>Hue (color angle), 0..359 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">v</td><td>Value (intensity), 0..255 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>LSB-aligned 24-bit RGB data [G,R,B] </dd></dl> + +</div> +</div> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function This demo uses a 12-LED RGB ring</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the NEOLED controller to be synthesized (UART0 is optional).</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__newlib_2main_8c.html b/sw/demo__newlib_2main_8c.html new file mode 100644 index 000000000..2934127ab --- /dev/null +++ b/sw/demo__newlib_2main_8c.html @@ -0,0 +1,185 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" 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class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;unistd.h&gt;</code><br /> +<code>#include &lt;time.h&gt;</code><br /> +<code>#include &lt;stdlib.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Print main's return code using a destructor</div></td></tr> +<tr class="memitem:a7076a1dfd3c18c91fcf665ce54b087b3" id="r_a7076a1dfd3c18c91fcf665ce54b087b3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7076a1dfd3c18c91fcf665ce54b087b3">main_destructor_test</a> (void)</td></tr> +<tr class="separator:a7076a1dfd3c18c91fcf665ce54b087b3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Demo/test program for NEORV32's newlib C standard library support. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function: Check some of newlib's core functions.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires UART0.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +<a id="a7076a1dfd3c18c91fcf665ce54b087b3" name="a7076a1dfd3c18c91fcf665ce54b087b3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7076a1dfd3c18c91fcf665ce54b087b3">&#9670;&#160;</a></span>main_destructor_test()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void main_destructor_test </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function: Check some of newlib's core functions.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires UART0.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__onewire_2main_8c.html b/sw/demo__onewire_2main_8c.html new file mode 100644 index 000000000..24199dda6 --- /dev/null +++ b/sw/demo__onewire_2main_8c.html @@ -0,0 +1,270 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 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class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Demo program for the NEORV32 1-Wire interface controller (ONEWIRE). +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +<code>#include &quot;onewire_aux.h&quot;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:af25820ed386a66a0d6bb4dcdd2204704" id="r_af25820ed386a66a0d6bb4dcdd2204704"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af25820ed386a66a0d6bb4dcdd2204704">show_help</a> (void)</td></tr> +<tr class="separator:af25820ed386a66a0d6bb4dcdd2204704"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a29d5831498c2eaf0415d6f01efb9e7ce" id="r_a29d5831498c2eaf0415d6f01efb9e7ce"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a29d5831498c2eaf0415d6f01efb9e7ce">show_1wire_commands</a> (void)</td></tr> +<tr class="separator:a29d5831498c2eaf0415d6f01efb9e7ce"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a951a31029af34715f20856eb82432637" id="r_a951a31029af34715f20856eb82432637"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a951a31029af34715f20856eb82432637">read_byte</a> (void)</td></tr> +<tr class="separator:a951a31029af34715f20856eb82432637"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a28283848f09bf8feebc860a51545f487" id="r_a28283848f09bf8feebc860a51545f487"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a28283848f09bf8feebc860a51545f487">write_byte</a> (void)</td></tr> +<tr class="separator:a28283848f09bf8feebc860a51545f487"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac07c9cfd80ac2e24be9dac6cf943b7de" id="r_ac07c9cfd80ac2e24be9dac6cf943b7de"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac07c9cfd80ac2e24be9dac6cf943b7de">scan_bus</a> (void)</td></tr> +<tr class="separator:ac07c9cfd80ac2e24be9dac6cf943b7de"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a8c86c6436e898f550d96b4ae9aa8c2cd" id="r_a8c86c6436e898f550d96b4ae9aa8c2cd"><td class="memItemLeft" align="right" valign="top"><a id="a8c86c6436e898f550d96b4ae9aa8c2cd" name="a8c86c6436e898f550d96b4ae9aa8c2cd"></a> +const char&#160;</td><td class="memItemRight" valign="bottom"><b>hex_c</b> [16] = {'0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'}</td></tr> +<tr class="separator:a8c86c6436e898f550d96b4ae9aa8c2cd"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Demo program for the NEORV32 1-Wire interface controller (ONEWIRE). </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the ONEWIRE and UART0 modules. Only non-blocking ONEWIRE functions are used.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>!=0 if setup error </dd></dl> + +</div> +</div> +<a id="a951a31029af34715f20856eb82432637" name="a951a31029af34715f20856eb82432637"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a951a31029af34715f20856eb82432637">&#9670;&#160;</a></span>read_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void read_byte </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read full byte from bus. </p> + +</div> +</div> +<a id="ac07c9cfd80ac2e24be9dac6cf943b7de" name="ac07c9cfd80ac2e24be9dac6cf943b7de"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac07c9cfd80ac2e24be9dac6cf943b7de">&#9670;&#160;</a></span>scan_bus()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void scan_bus </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Scan bus for devices and print IDs. </p> + +</div> +</div> +<a id="a29d5831498c2eaf0415d6f01efb9e7ce" name="a29d5831498c2eaf0415d6f01efb9e7ce"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a29d5831498c2eaf0415d6f01efb9e7ce">&#9670;&#160;</a></span>show_1wire_commands()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void show_1wire_commands </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Show standard 1-wire commands. </p> + +</div> +</div> +<a id="af25820ed386a66a0d6bb4dcdd2204704" name="af25820ed386a66a0d6bb4dcdd2204704"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af25820ed386a66a0d6bb4dcdd2204704">&#9670;&#160;</a></span>show_help()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void show_help </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Show help menu. </p> + +</div> +</div> +<a id="a28283848f09bf8feebc860a51545f487" name="a28283848f09bf8feebc860a51545f487"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a28283848f09bf8feebc860a51545f487">&#9670;&#160;</a></span>write_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void write_byte </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write full byte to bus. </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__pwm_2main_8c.html b/sw/demo__pwm_2main_8c.html new file mode 100644 index 000000000..81089392a --- /dev/null +++ b/sw/demo__pwm_2main_8c.html @@ -0,0 +1,178 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta 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id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script 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class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_b683da3a5fc966bff32ebf7cda721811.html">demo_pwm</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Simple PWM demo program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2351f30f0895b552e5fe9944d69e645d" id="r_a2351f30f0895b552e5fe9944d69e645d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2351f30f0895b552e5fe9944d69e645d">MAX_DUTY</a>&#160;&#160;&#160;200</td></tr> +<tr class="separator:a2351f30f0895b552e5fe9944d69e645d"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Simple PWM demo program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a2351f30f0895b552e5fe9944d69e645d" name="a2351f30f0895b552e5fe9944d69e645d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2351f30f0895b552e5fe9944d69e645d">&#9670;&#160;</a></span>MAX_DUTY</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define MAX_DUTY&#160;&#160;&#160;200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Maximum PWM output intensity (8-bit duty cycle) </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This program generates a simple dimming sequence for PWM channels 0 to 3.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the PWM controller to be synthesized (the UART is optional).</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>!=0 if error. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__sdi_2main_8c.html b/sw/demo__sdi_2main_8c.html new file mode 100644 index 000000000..e75b5ac0e --- /dev/null +++ b/sw/demo__sdi_2main_8c.html @@ -0,0 +1,202 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_sdi/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" 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+<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_c413aba6cb5da07a571465ba333950af.html">demo_sdi</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>SDI test program (direct access to the SDI module). +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae3dc843520a800d7ba2b5d6be03d9c3d" id="r_ae3dc843520a800d7ba2b5d6be03d9c3d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae3dc843520a800d7ba2b5d6be03d9c3d">sdi_put</a> (void)</td></tr> +<tr class="separator:ae3dc843520a800d7ba2b5d6be03d9c3d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa25f620a5631e862252be1d5429e8585" id="r_aa25f620a5631e862252be1d5429e8585"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa25f620a5631e862252be1d5429e8585">sdi_get</a> (void)</td></tr> +<tr class="separator:aa25f620a5631e862252be1d5429e8585"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>SDI test program (direct access to the SDI module). </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This program provides an interactive console for the SDI module.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires UART0 and the SDI to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Irrelevant. </dd></dl> + +</div> +</div> +<a id="aa25f620a5631e862252be1d5429e8585" name="aa25f620a5631e862252be1d5429e8585"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa25f620a5631e862252be1d5429e8585">&#9670;&#160;</a></span>sdi_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void sdi_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read data from SDI RX buffer. </p> + +</div> +</div> +<a id="ae3dc843520a800d7ba2b5d6be03d9c3d" name="ae3dc843520a800d7ba2b5d6be03d9c3d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae3dc843520a800d7ba2b5d6be03d9c3d">&#9670;&#160;</a></span>sdi_put()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void sdi_put </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write data to SDI TX buffer. </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__slink_2main_8c.html b/sw/demo__slink_2main_8c.html new file mode 100644 index 000000000..6f5e5de3d --- /dev/null +++ b/sw/demo__slink_2main_8c.html @@ -0,0 +1,182 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_slink/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" 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onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_c2d46947bdd73c33f53326fc5ee3a272.html">demo_slink</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>SLINK demo program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a48c79e20ed1d4138d61b5593bdbe537a" id="r_a48c79e20ed1d4138d61b5593bdbe537a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a48c79e20ed1d4138d61b5593bdbe537a">slink_firq_handler</a> (void)</td></tr> +<tr class="separator:a48c79e20ed1d4138d61b5593bdbe537a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>SLINK demo program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Simple SLINK demo program.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the UART0 and the SLINK to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>=! 0 if execution failed. </dd></dl> + +</div> +</div> +<a id="a48c79e20ed1d4138d61b5593bdbe537a" name="a48c79e20ed1d4138d61b5593bdbe537a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a48c79e20ed1d4138d61b5593bdbe537a">&#9670;&#160;</a></span>slink_firq_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void slink_firq_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SLINK interrupt handler. </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__spi_2main_8c.html b/sw/demo__spi_2main_8c.html new file mode 100644 index 000000000..90b38ba23 --- /dev/null +++ b/sw/demo__spi_2main_8c.html @@ -0,0 +1,261 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta 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id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script 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class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_4c113257314015688a865e1bb8429184.html">demo_spi</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> &#124; +<a href="#var-members">Variables</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>SPI bus explorer (execute SPI transactions by hand). +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a6f94991b8943a141ed4124585222470d" id="r_a6f94991b8943a141ed4124585222470d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6f94991b8943a141ed4124585222470d">spi_cs</a> (uint32_t type)</td></tr> +<tr class="separator:a6f94991b8943a141ed4124585222470d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a13e10b34fbbffca6c31f0ce25b3f8432" id="r_a13e10b34fbbffca6c31f0ce25b3f8432"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a13e10b34fbbffca6c31f0ce25b3f8432">spi_trans</a> (void)</td></tr> +<tr class="separator:a13e10b34fbbffca6c31f0ce25b3f8432"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a755192be6c3cf9904564b0eee99de445" id="r_a755192be6c3cf9904564b0eee99de445"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a755192be6c3cf9904564b0eee99de445">spi_setup</a> (void)</td></tr> +<tr class="separator:a755192be6c3cf9904564b0eee99de445"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac582208281cd6fce4eb61c234f312ef6" id="r_ac582208281cd6fce4eb61c234f312ef6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac582208281cd6fce4eb61c234f312ef6">aux_print_hex_byte</a> (uint8_t byte)</td></tr> +<tr class="separator:ac582208281cd6fce4eb61c234f312ef6"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a4ebbc33db8ee81cb971eba8365696709" id="r_a4ebbc33db8ee81cb971eba8365696709"><td class="memItemLeft" align="right" valign="top"><a id="a4ebbc33db8ee81cb971eba8365696709" name="a4ebbc33db8ee81cb971eba8365696709"></a> +uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>spi_configured</b></td></tr> +<tr class="separator:a4ebbc33db8ee81cb971eba8365696709"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>SPI bus explorer (execute SPI transactions by hand). </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ac582208281cd6fce4eb61c234f312ef6" name="ac582208281cd6fce4eb61c234f312ef6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac582208281cd6fce4eb61c234f312ef6">&#9670;&#160;</a></span>aux_print_hex_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void aux_print_hex_byte </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>byte</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print HEX byte.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Byte to be printed as 2-cahr hex value. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This program provides an interactive console to communicate with SPI devices.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the UART and the SPI to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Irrelevant. </dd></dl> + +</div> +</div> +<a id="a6f94991b8943a141ed4124585222470d" name="a6f94991b8943a141ed4124585222470d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6f94991b8943a141ed4124585222470d">&#9670;&#160;</a></span>spi_cs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_cs </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>type</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable or disable chip-select line</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">type</td><td>0=disable, 1=enable </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a755192be6c3cf9904564b0eee99de445" name="a755192be6c3cf9904564b0eee99de445"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a755192be6c3cf9904564b0eee99de445">&#9670;&#160;</a></span>spi_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_setup </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure SPI module </p> + +</div> +</div> +<a id="a13e10b34fbbffca6c31f0ce25b3f8432" name="a13e10b34fbbffca6c31f0ce25b3f8432"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a13e10b34fbbffca6c31f0ce25b3f8432">&#9670;&#160;</a></span>spi_trans()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_trans </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI data transfer </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__spi__irq_2main_8c.html b/sw/demo__spi__irq_2main_8c.html new file mode 100644 index 000000000..e62b2b5b0 --- /dev/null +++ b/sw/demo__spi__irq_2main_8c.html @@ -0,0 +1,192 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, 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id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license 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id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_8f848e36ac87ced1c361afcc0549ca32.html">demo_spi_irq</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> &#124; +<a href="#var-members">Variables</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Example of an ISR driven SPI transfer. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__spi__irq_8h_source.html">neorv32_spi_irq.h</a>&quot;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a7e266cc5247c999948dacc2102bd184a" id="r_a7e266cc5247c999948dacc2102bd184a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7e266cc5247c999948dacc2102bd184a">spi_irq_handler</a> (void)</td></tr> +<tr class="separator:a7e266cc5247c999948dacc2102bd184a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a9f865a7dd1c92230d701ba10cd81ad78" id="r_a9f865a7dd1c92230d701ba10cd81ad78"><td class="memItemLeft" align="right" valign="top"><a id="a9f865a7dd1c92230d701ba10cd81ad78" name="a9f865a7dd1c92230d701ba10cd81ad78"></a> +<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>&#160;</td><td class="memItemRight" valign="bottom"><b>g_neorv32_spi</b></td></tr> +<tr class="separator:a9f865a7dd1c92230d701ba10cd81ad78"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Example of an ISR driven SPI transfer. </p> +<dl class="section author"><dt>Author</dt><dd>Andreas Kaeberlein </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This program demonstrates the usage of an ISR driven SPI transfer</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the UART and the SPI to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Irrelevant. </dd></dl> + +</div> +</div> +<a id="a7e266cc5247c999948dacc2102bd184a" name="a7e266cc5247c999948dacc2102bd184a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7e266cc5247c999948dacc2102bd184a">&#9670;&#160;</a></span>spi_irq_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void spi_irq_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI Interrupt Handler</p> +<dl class="section note"><dt>Note</dt><dd>Captures/Transmits the data to the SPI core</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>void. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__trng_2main_8c.html b/sw/demo__trng_2main_8c.html new file mode 100644 index 000000000..c640a4248 --- /dev/null +++ b/sw/demo__trng_2main_8c.html @@ -0,0 +1,261 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_trng/main.c File Reference</title> +<link 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href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_237db5b95db643499d4c20f0bc5f6a7d.html">demo_trng</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>True random number generator demo program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a64205d97b57c99dc5e95b8621827f4a4" id="r_a64205d97b57c99dc5e95b8621827f4a4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a64205d97b57c99dc5e95b8621827f4a4">print_random_data</a> (void)</td></tr> +<tr class="separator:a64205d97b57c99dc5e95b8621827f4a4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr 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class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>True random number generator demo program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a23a91e6fe2cc44f3c29baf0d331e05db" name="a23a91e6fe2cc44f3c29baf0d331e05db"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a23a91e6fe2cc44f3c29baf0d331e05db">&#9670;&#160;</a></span>adaptive_proportion_test()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void adaptive_proportion_test </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Run adaptive proportion test (NIST SP 800-90B) </p> + +</div> +</div> +<a id="abbde1237eed617466fb971a78c3acd1e" name="abbde1237eed617466fb971a78c3acd1e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abbde1237eed617466fb971a78c3acd1e">&#9670;&#160;</a></span>compute_rate()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void compute_rate </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Compute average random generation rate </p> + +</div> +</div> +<a id="a4e49f5e3feb4bd5755f919cd3310b506" name="a4e49f5e3feb4bd5755f919cd3310b506"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4e49f5e3feb4bd5755f919cd3310b506">&#9670;&#160;</a></span>generate_histogram()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void generate_histogram </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate and print histogram. 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href="#a64205d97b57c99dc5e95b8621827f4a4">&#9670;&#160;</a></span>print_random_data()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void print_random_data </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print random numbers until a key is pressed. </p> + +</div> +</div> +<a id="af37eae672fee5e81f00a1dbf51b7e417" name="af37eae672fee5e81f00a1dbf51b7e417"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af37eae672fee5e81f00a1dbf51b7e417">&#9670;&#160;</a></span>repetition_count_test()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void repetition_count_test </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Run repetition count test (NIST SP 800-90B) </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__twi_2main_8c.html b/sw/demo__twi_2main_8c.html new file mode 100644 index 000000000..0ccb40433 --- /dev/null +++ b/sw/demo__twi_2main_8c.html @@ -0,0 +1,248 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta 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<tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license 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id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_ebeff77b922fbb914a1494857a82a38e.html">demo_twi</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>TWI bus explorer. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:aace46ee34e954f9ebee5873beb0785f1" id="r_aace46ee34e954f9ebee5873beb0785f1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aace46ee34e954f9ebee5873beb0785f1">scan_twi</a> (void)</td></tr> +<tr class="separator:aace46ee34e954f9ebee5873beb0785f1"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acee0c1770467f85a150d072ac7e1252f" id="r_acee0c1770467f85a150d072ac7e1252f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acee0c1770467f85a150d072ac7e1252f">set_clock</a> (void)</td></tr> +<tr class="separator:acee0c1770467f85a150d072ac7e1252f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa94edd4f55a3ac18913f661f4bc16fb1" id="r_aa94edd4f55a3ac18913f661f4bc16fb1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa94edd4f55a3ac18913f661f4bc16fb1">send_twi</a> (void)</td></tr> +<tr class="separator:aa94edd4f55a3ac18913f661f4bc16fb1"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2ebc688bc1dad328693fc0974b378fa0" id="r_a2ebc688bc1dad328693fc0974b378fa0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2ebc688bc1dad328693fc0974b378fa0">print_hex_byte</a> (uint8_t data)</td></tr> +<tr class="separator:a2ebc688bc1dad328693fc0974b378fa0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>TWI bus explorer. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This program provides an interactive console to communicate with TWI devices.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the UART to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +<a id="a2ebc688bc1dad328693fc0974b378fa0" name="a2ebc688bc1dad328693fc0974b378fa0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2ebc688bc1dad328693fc0974b378fa0">&#9670;&#160;</a></span>print_hex_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void print_hex_byte </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print byte as hex chars via UART0.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">data</td><td>8-bit data to be printed as two hex chars. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aace46ee34e954f9ebee5873beb0785f1" name="aace46ee34e954f9ebee5873beb0785f1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aace46ee34e954f9ebee5873beb0785f1">&#9670;&#160;</a></span>scan_twi()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void scan_twi </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Scan 7-bit TWI address space and print results </p> + +</div> +</div> +<a id="aa94edd4f55a3ac18913f661f4bc16fb1" name="aa94edd4f55a3ac18913f661f4bc16fb1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa94edd4f55a3ac18913f661f4bc16fb1">&#9670;&#160;</a></span>send_twi()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void send_twi </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read/write menu to transfer 1 byte from/to bus </p> + +</div> +</div> +<a id="acee0c1770467f85a150d072ac7e1252f" name="acee0c1770467f85a150d072ac7e1252f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acee0c1770467f85a150d072ac7e1252f">&#9670;&#160;</a></span>set_clock()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void set_clock </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>TWI clock setup </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__wdt_2main_8c.html b/sw/demo__wdt_2main_8c.html new file mode 100644 index 000000000..ef4a1b725 --- /dev/null +++ b/sw/demo__wdt_2main_8c.html @@ -0,0 +1,178 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, 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id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license 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id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_78d7bfa405ff3a31fa7539cfd8bc8262.html">demo_wdt</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Watchdog demo program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a01af3905e60b1869f669315f4a1297f5" id="r_a01af3905e60b1869f669315f4a1297f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a01af3905e60b1869f669315f4a1297f5">WDT_TIMEOUT_S</a>&#160;&#160;&#160;8</td></tr> +<tr class="separator:a01af3905e60b1869f669315f4a1297f5"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Watchdog demo program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a01af3905e60b1869f669315f4a1297f5" name="a01af3905e60b1869f669315f4a1297f5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a01af3905e60b1869f669315f4a1297f5">&#9670;&#160;</a></span>WDT_TIMEOUT_S</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define WDT_TIMEOUT_S&#160;&#160;&#160;8</td> + </tr> + </table> +</div><div class="memdoc"> +<p>WDT timeout (until system reset) in seconds </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the WDT and UART0 to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/demo__xip_2main_8c.html b/sw/demo__xip_2main_8c.html new file mode 100644 index 000000000..d48b7176d --- /dev/null +++ b/sw/demo__xip_2main_8c.html @@ -0,0 +1,479 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_xip/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" 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+</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#define-members">Macros</a> &#124; +<a href="#enum-members">Enumerations</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Interactive console program to upload and execute a XIP program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:a0035ad41f622dbfc2412318a8ed39257" id="r_a0035ad41f622dbfc2412318a8ed39257"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0035ad41f622dbfc2412318a8ed39257">EXE_SIGNATURE</a>&#160;&#160;&#160;0x4788CAFE</td></tr> +<tr class="separator:a0035ad41f622dbfc2412318a8ed39257"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a23a9099a5f8fc9c6e253c0eecb2be8db" id="r_a23a9099a5f8fc9c6e253c0eecb2be8db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a933045a5405de55781d687315f42054e">CLK_PRSC_128</a></td></tr> +<tr class="separator:aec72efe062dbdb149ae6d4f8b1be6793"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6b20d41d6252e9871430c242cb1a56e7" id="r_a6b20d41d6252e9871430c242cb1a56e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6b20d41d6252e9871430c242cb1a56e7">BUFFER_SIZE</a>&#160;&#160;&#160;(7*1024)</td></tr> +<tr class="separator:a6b20d41d6252e9871430c242cb1a56e7"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a> +Enumerations</h2></td></tr> +<tr class="memitem:af30de1c8d8502ad374612d308cfbd12e" id="r_af30de1c8d8502ad374612d308cfbd12e"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af30de1c8d8502ad374612d308cfbd12e">SPI_FLASH_CMD</a> { <br /> +&#160;&#160;<a class="el" href="#af30de1c8d8502ad374612d308cfbd12ea528cebc54176f6f4c0a8f7f16fb28ca1">SPI_FLASH_CMD_WRITE</a> = 0x02 +, <a class="el" href="#af30de1c8d8502ad374612d308cfbd12ea6c1994ba2cfd97e0c77dcdf8bbdfdfa6">SPI_FLASH_CMD_READ</a> = 0x03 +, <a class="el" href="#af30de1c8d8502ad374612d308cfbd12eaa91d3c1d788b21fc798a5976c9f0da77">SPI_FLASH_CMD_WRITE_DISABLE</a> = 0x04 +, <a class="el" href="#af30de1c8d8502ad374612d308cfbd12ea5fbc6551a10549b38e5ab4a76c38f214">SPI_FLASH_CMD_READ_STATUS</a> = 0x05 +, <br /> +&#160;&#160;<a class="el" href="#af30de1c8d8502ad374612d308cfbd12ea152e091e93778f217f8b766298351513">SPI_FLASH_CMD_WRITE_ENABLE</a> = 0x06 +, <a class="el" href="#af30de1c8d8502ad374612d308cfbd12eacd62141d6331f66e31bd252e2a92b836">SPI_FLASH_CMD_SECTOR_ERASE</a> = 0xD8 +<br /> + }</td></tr> +<tr class="separator:af30de1c8d8502ad374612d308cfbd12e"><td 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class="separator:a3043d09bdc155f57f45cd91e0cd4d15b"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">RAM storage for executable</h2></td></tr> +<tr class="memitem:acc95e55a622d79c2a398397d1f9b8033" id="r_acc95e55a622d79c2a398397d1f9b8033"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acc95e55a622d79c2a398397d1f9b8033">ram_buffer</a> [<a class="el" href="#a6b20d41d6252e9871430c242cb1a56e7">BUFFER_SIZE</a>/4]</td></tr> +<tr class="separator:acc95e55a622d79c2a398397d1f9b8033"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Interactive console program to upload and execute a XIP program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a6b20d41d6252e9871430c242cb1a56e7" name="a6b20d41d6252e9871430c242cb1a56e7"></a> +<h2 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</p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="af30de1c8d8502ad374612d308cfbd12ea528cebc54176f6f4c0a8f7f16fb28ca1" name="af30de1c8d8502ad374612d308cfbd12ea528cebc54176f6f4c0a8f7f16fb28ca1"></a>SPI_FLASH_CMD_WRITE&#160;</td><td class="fielddoc"><p>Write data </p> +</td></tr> +<tr><td class="fieldname"><a id="af30de1c8d8502ad374612d308cfbd12ea6c1994ba2cfd97e0c77dcdf8bbdfdfa6" name="af30de1c8d8502ad374612d308cfbd12ea6c1994ba2cfd97e0c77dcdf8bbdfdfa6"></a>SPI_FLASH_CMD_READ&#160;</td><td class="fielddoc"><p>Read data </p> +</td></tr> +<tr><td class="fieldname"><a id="af30de1c8d8502ad374612d308cfbd12eaa91d3c1d788b21fc798a5976c9f0da77" name="af30de1c8d8502ad374612d308cfbd12eaa91d3c1d788b21fc798a5976c9f0da77"></a>SPI_FLASH_CMD_WRITE_DISABLE&#160;</td><td class="fielddoc"><p>Disable write access </p> +</td></tr> +<tr><td class="fieldname"><a id="af30de1c8d8502ad374612d308cfbd12ea5fbc6551a10549b38e5ab4a76c38f214" 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class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#adccf1bb8f1f203cb1350f7f2eb15a08e">SPI_FLASH_SREG</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI flash status register </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="adccf1bb8f1f203cb1350f7f2eb15a08eac84de63bbea3989c71bcc92d1d01cfa4" name="adccf1bb8f1f203cb1350f7f2eb15a08eac84de63bbea3989c71bcc92d1d01cfa4"></a>SPI_FLASH_SREG_WIP&#160;</td><td class="fielddoc"><p>Write-in-progress data </p> +</td></tr> +<tr><td class="fieldname"><a id="adccf1bb8f1f203cb1350f7f2eb15a08ea90f3b76faed13819ee13e574d1bff0c1" name="adccf1bb8f1f203cb1350f7f2eb15a08ea90f3b76faed13819ee13e574d1bff0c1"></a>SPI_FLASH_SREG_WEL&#160;</td><td class="fielddoc"><p>Write-enable latch </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the XIP module and UART0.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +<a id="a0458656f8a108ff31f4bbbd005f029a0" name="a0458656f8a108ff31f4bbbd005f029a0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0458656f8a108ff31f4bbbd005f029a0">&#9670;&#160;</a></span>uart_get_executable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int uart_get_executable </td> + <td>(</td> + <td class="paramtype">uint32_t *</td> <td class="paramname"><span class="paramname"><em>dst</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t *</td> <td class="paramname"><span class="paramname"><em>length</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get NEORV32 executable via UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">dst</td><td>Pointer to uin32_t data array where the executable will be stored. </td></tr> + <tr><td class="paramdir">[out]</td><td class="paramname">length</td><td>Pointer to a uin32_t to store the executable size in bytes. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success. </dd></dl> + +</div> +</div> +<a id="a3043d09bdc155f57f45cd91e0cd4d15b" name="a3043d09bdc155f57f45cd91e0cd4d15b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3043d09bdc155f57f45cd91e0cd4d15b">&#9670;&#160;</a></span>uart_get_word()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t uart_get_word </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get 32-bit word from UART.</p> +<dl class="section return"><dt>Returns</dt><dd>32-bit data word. </dd></dl> + +</div> +</div> +<a id="a23bd7bd7b0808d919fd09ac0a8258498" name="a23bd7bd7b0808d919fd09ac0a8258498"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a23bd7bd7b0808d919fd09ac0a8258498">&#9670;&#160;</a></span>xip_flash_access_check()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int xip_flash_access_check </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check SPI flash connection by toggling the status register's write enable latch.</p> +<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success. </dd></dl> + +</div> +</div> +<a id="a9e0b2714126b6699ddb65485c93293e4" name="a9e0b2714126b6699ddb65485c93293e4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9e0b2714126b6699ddb65485c93293e4">&#9670;&#160;</a></span>xip_flash_erase_sector()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void xip_flash_erase_sector </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>base_addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Erase sector starting at base address.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">base_addr</td><td>Base address of sector to erase. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a4ddfa8fdc072cadeef18a4a10bc8b174" name="a4ddfa8fdc072cadeef18a4a10bc8b174"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4ddfa8fdc072cadeef18a4a10bc8b174">&#9670;&#160;</a></span>xip_flash_program()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void xip_flash_program </td> + <td>(</td> + <td class="paramtype">uint32_t *</td> <td class="paramname"><span class="paramname"><em>src</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>base_addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>size</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Helper function to program the XIP flash via the direct SPI access feature of the XIP module.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function can only be used BEFORE the XIP-mode is activated! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function is blocking and performs individual writes for each byte (little-endian byte order!).</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">src</td><td>Pointer to data that will be copied to flash (32-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">base_addr</td><td>Image base address (in flash). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">size</td><td>Image size in bytes. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Returns 0 if write was successful. </dd></dl> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a id="acc95e55a622d79c2a398397d1f9b8033" name="acc95e55a622d79c2a398397d1f9b8033"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acc95e55a622d79c2a398397d1f9b8033">&#9670;&#160;</a></span>ram_buffer</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t ram_buffer[<a class="el" href="#a6b20d41d6252e9871430c242cb1a56e7">BUFFER_SIZE</a>/4]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the XIP module and UART0.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a 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href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_5534fa9035f54ab438a41c43d6f7fc7a.html">demo_xirq</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>External interrupt controller (XIRQ) demo program (using hardware-assisted prioritization). +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a8874ccfc0b56171c359b5c2ceaf2bd80" id="r_a8874ccfc0b56171c359b5c2ceaf2bd80"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8874ccfc0b56171c359b5c2ceaf2bd80">xirq_handler_ch0</a> (void)</td></tr> +<tr class="separator:a8874ccfc0b56171c359b5c2ceaf2bd80"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abfe0c0bc47a683ba55df2aed63a12d4b" id="r_abfe0c0bc47a683ba55df2aed63a12d4b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abfe0c0bc47a683ba55df2aed63a12d4b">xirq_handler_ch1</a> (void)</td></tr> +<tr class="separator:abfe0c0bc47a683ba55df2aed63a12d4b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae8e3b3236aa2303c2b5e6e421b72cf73" id="r_ae8e3b3236aa2303c2b5e6e421b72cf73"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae8e3b3236aa2303c2b5e6e421b72cf73">xirq_handler_ch2</a> (void)</td></tr> +<tr class="separator:ae8e3b3236aa2303c2b5e6e421b72cf73"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a99e9ae3088f39995c852b2c53ec21266" id="r_a99e9ae3088f39995c852b2c53ec21266"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a99e9ae3088f39995c852b2c53ec21266">xirq_handler_ch3</a> (void)</td></tr> +<tr class="separator:a99e9ae3088f39995c852b2c53ec21266"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>External interrupt controller (XIRQ) demo program (using hardware-assisted prioritization). </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the XIRQ and the UART to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +<a id="a8874ccfc0b56171c359b5c2ceaf2bd80" name="a8874ccfc0b56171c359b5c2ceaf2bd80"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8874ccfc0b56171c359b5c2ceaf2bd80">&#9670;&#160;</a></span>xirq_handler_ch0()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void xirq_handler_ch0 </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ handler channel 0. </p><dl class="section warning"><dt>Warning</dt><dd>This function has to be of type "void xyz(void)" and must not use any interrupt attributes! </dd></dl> + +</div> +</div> +<a id="abfe0c0bc47a683ba55df2aed63a12d4b" name="abfe0c0bc47a683ba55df2aed63a12d4b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abfe0c0bc47a683ba55df2aed63a12d4b">&#9670;&#160;</a></span>xirq_handler_ch1()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void xirq_handler_ch1 </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ handler channel 1. </p><dl class="section warning"><dt>Warning</dt><dd>This function has to be of type "void xyz(void)" and must not use any interrupt attributes! </dd></dl> + +</div> +</div> +<a id="ae8e3b3236aa2303c2b5e6e421b72cf73" name="ae8e3b3236aa2303c2b5e6e421b72cf73"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae8e3b3236aa2303c2b5e6e421b72cf73">&#9670;&#160;</a></span>xirq_handler_ch2()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void xirq_handler_ch2 </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ handler channel 2. </p><dl class="section warning"><dt>Warning</dt><dd>This function has to be of type "void xyz(void)" and must not use any interrupt attributes! </dd></dl> + +</div> +</div> +<a id="a99e9ae3088f39995c852b2c53ec21266" name="a99e9ae3088f39995c852b2c53ec21266"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a99e9ae3088f39995c852b2c53ec21266">&#9670;&#160;</a></span>xirq_handler_ch3()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void xirq_handler_ch3 </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ handler channel 3. </p><dl class="section warning"><dt>Warning</dt><dd>This function has to be of type "void xyz(void)" and must not use any interrupt attributes! </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/dhry_8h_source.html b/sw/dhry_8h_source.html new file mode 100644 index 000000000..2dfb3f647 --- /dev/null +++ b/sw/dhry_8h_source.html @@ -0,0 +1,557 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">/*</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment"> ****************************************************************************</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment"> *</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment"> * &quot;DHRYSTONE&quot; Benchmark Program</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment"> * -----------------------------</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment"> *</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment"> * Version: C, Version 2.1</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="comment"> *</span></div> +<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="comment"> * File: dhry.h (part 1 of 3)</span></div> +<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span><span class="comment"> *</span></div> +<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="comment"> * Date: May 25, 1988</span></div> +<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="comment"> *</span></div> +<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span><span class="comment"> * Author: Reinhold P. Weicker</span></div> +<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span><span class="comment"> * Siemens AG, E STE 35</span></div> +<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="comment"> * Postfach 3240</span></div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="comment"> * 8520 Erlangen</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="comment"> * Germany (West)</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="comment"> * Phone: [xxx-49]-9131-7-20330</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="comment"> * (8-17 Central European Time)</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="comment"> * Usenet: ..!mcvax!unido!estevax!weicker</span></div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="comment"> *</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment"> * Original Version (in Ada) published in</span></div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span><span class="comment"> * &quot;Communications of the ACM&quot; vol. 27., no. 10 (Oct. 1984),</span></div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment"> * pp. 1013 - 1030, together with the statistics</span></div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span><span class="comment"> * on which the distribution of statements etc. is based.</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span><span class="comment"> *</span></div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span><span class="comment"> * In this C version, the following C library functions are used:</span></div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span><span class="comment"> * - strcpy, strcmp (inside the measurement loop)</span></div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span><span class="comment"> * - printf, scanf (outside the measurement loop)</span></div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span><span class="comment"> * In addition, Berkeley UNIX system calls &quot;times ()&quot; or &quot;time ()&quot;</span></div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span><span class="comment"> * are used for execution time measurement. For measurements</span></div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span><span class="comment"> * on other systems, these calls have to be changed.</span></div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span><span class="comment"> *</span></div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span><span class="comment"> * Collection of Results:</span></div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span><span class="comment"> * Reinhold Weicker (address see above) and</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span><span class="comment"> *</span></div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span><span class="comment"> * Rick Richardson</span></div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span><span class="comment"> * PC Research. Inc.</span></div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span><span class="comment"> * 94 Apple Orchard Drive</span></div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span><span class="comment"> * Tinton Falls, NJ 07724</span></div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span><span class="comment"> * Phone: (201) 389-8963 (9-17 EST)</span></div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span><span class="comment"> * Usenet: ...!uunet!pcrat!rick</span></div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span><span class="comment"> *</span></div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="comment"> * Please send results to Rick Richardson and/or Reinhold Weicker.</span></div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span><span class="comment"> * Complete information should be given on hardware and software used.</span></div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span><span class="comment"> * Hardware information includes: Machine type, CPU, type and size</span></div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span><span class="comment"> * of caches; for microprocessors: clock frequency, memory speed</span></div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="comment"> * (number of wait states).</span></div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span><span class="comment"> * Software information includes: Compiler (and runtime library)</span></div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span><span class="comment"> * manufacturer and version, compilation switches, OS version.</span></div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span><span class="comment"> * The Operating System version may give an indication about the</span></div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="comment"> * compiler; Dhrystone itself performs no OS calls in the measurement loop.</span></div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="comment"> *</span></div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span><span class="comment"> * The complete output generated by the program should be mailed</span></div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span><span class="comment"> * such that at least some checks for correctness can be made.</span></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span><span class="comment"> *</span></div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="comment"> ***************************************************************************</span></div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="comment"> *</span></div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="comment"> * History: This version C/2.1 has been made for two reasons:</span></div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="comment"> *</span></div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span><span class="comment"> * 1) There is an obvious need for a common C version of</span></div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span><span class="comment"> * Dhrystone, since C is at present the most popular system</span></div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span><span class="comment"> * programming language for the class of processors</span></div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span><span class="comment"> * (microcomputers, minicomputers) where Dhrystone is used most.</span></div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span><span class="comment"> * There should be, as far as possible, only one C version of</span></div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span><span class="comment"> * Dhrystone such that results can be compared without</span></div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="comment"> * restrictions. In the past, the C versions distributed</span></div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="comment"> * by Rick Richardson (Version 1.1) and by Reinhold Weicker</span></div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="comment"> * had small (though not significant) differences.</span></div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span><span class="comment"> *</span></div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="comment"> * 2) As far as it is possible without changes to the Dhrystone</span></div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="comment"> * statistics, optimizing compilers should be prevented from</span></div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="comment"> * removing significant statements.</span></div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="comment"> *</span></div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="comment"> * This C version has been developed in cooperation with</span></div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span><span class="comment"> * Rick Richardson (Tinton Falls, NJ), it incorporates many</span></div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="comment"> * ideas from the &quot;Version 1.1&quot; distributed previously by</span></div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="comment"> * him over the UNIX network Usenet.</span></div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span><span class="comment"> * I also thank Chaim Benedelac (National Semiconductor),</span></div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span><span class="comment"> * David Ditzel (SUN), Earl Killian and John Mashey (MIPS),</span></div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span><span class="comment"> * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)</span></div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="comment"> * for their help with comments on earlier versions of the</span></div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="comment"> * benchmark.</span></div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span><span class="comment"> *</span></div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span><span class="comment"> * Changes: In the initialization part, this version follows mostly</span></div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span><span class="comment"> * Rick Richardson&#39;s version distributed via Usenet, not the</span></div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span><span class="comment"> * version distributed earlier via floppy disk by Reinhold Weicker.</span></div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span><span class="comment"> * As a concession to older compilers, names have been made</span></div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span><span class="comment"> * unique within the first 8 characters.</span></div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span><span class="comment"> * Inside the measurement loop, this version follows the</span></div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span><span class="comment"> * version previously distributed by Reinhold Weicker.</span></div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span><span class="comment"> *</span></div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span><span class="comment"> * At several places in the benchmark, code has been added,</span></div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span><span class="comment"> * but within the measurement loop only in branches that</span></div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span><span class="comment"> * are not executed. The intention is that optimizing compilers</span></div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span><span class="comment"> * should be prevented from moving code out of the measurement</span></div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span><span class="comment"> * loop, or from removing code altogether. Since the statements</span></div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span><span class="comment"> * that are executed within the measurement loop have NOT been</span></div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span><span class="comment"> * changed, the numbers defining the &quot;Dhrystone distribution&quot;</span></div> +<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span><span class="comment"> * (distribution of statements, operand types and locality)</span></div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span><span class="comment"> * still hold. Except for sophisticated optimizing compilers,</span></div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span><span class="comment"> * execution times for this version should be the same as</span></div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span><span class="comment"> * for previous versions.</span></div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span><span class="comment"> *</span></div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span><span class="comment"> * Since it has proven difficult to subtract the time for the</span></div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span><span class="comment"> * measurement loop overhead in a correct way, the loop check</span></div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span><span class="comment"> * has been made a part of the benchmark. This does have</span></div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span><span class="comment"> * an impact - though a very minor one - on the distribution</span></div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span><span class="comment"> * statistics which have been updated for this version.</span></div> +<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span><span class="comment"> *</span></div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span><span class="comment"> * All changes within the measurement loop are described</span></div> +<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span><span class="comment"> * and discussed in the companion paper &quot;Rationale for</span></div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span><span class="comment"> * Dhrystone version 2&quot;.</span></div> +<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span><span class="comment"> *</span></div> +<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span><span class="comment"> * Because of the self-imposed limitation that the order and</span></div> +<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span><span class="comment"> * distribution of the executed statements should not be</span></div> +<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span><span class="comment"> * changed, there are still cases where optimizing compilers</span></div> +<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span><span class="comment"> * may not generate code for some statements. To a certain</span></div> +<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"> 119</span><span class="comment"> * degree, this is unavoidable for small synthetic benchmarks.</span></div> +<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"> 120</span><span class="comment"> * Users of the benchmark are advised to check code listings</span></div> +<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span><span class="comment"> * whether code is generated for all statements of Dhrystone.</span></div> +<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span><span class="comment"> *</span></div> +<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span><span class="comment"> * Version 2.1 is identical to version 2.0 distributed via</span></div> +<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span><span class="comment"> * the UNIX network Usenet in March 1988 except that it corrects</span></div> +<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span><span class="comment"> * some minor deficiencies that were found by users of version 2.0.</span></div> +<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span><span class="comment"> * The only change within the measurement loop is that a</span></div> +<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"> 127</span><span class="comment"> * non-executed &quot;else&quot; part was added to the &quot;if&quot; statement in</span></div> +<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"> 128</span><span class="comment"> * Func_3, and a non-executed &quot;else&quot; part removed from Proc_3.</span></div> +<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span><span class="comment"> *</span></div> +<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span><span class="comment"> ***************************************************************************</span></div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span><span class="comment"> *</span></div> +<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span><span class="comment"> * Defines: The following &quot;Defines&quot; are possible:</span></div> +<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span><span class="comment"> * -DREG=register (default: Not defined)</span></div> +<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"> 134</span><span class="comment"> * As an approximation to what an average C programmer</span></div> +<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"> 135</span><span class="comment"> * might do, the &quot;register&quot; storage class is applied</span></div> +<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"> 136</span><span class="comment"> * (if enabled by -DREG=register)</span></div> +<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"> 137</span><span class="comment"> * - for local variables, if they are used (dynamically)</span></div> +<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"> 138</span><span class="comment"> * five or more times</span></div> +<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"> 139</span><span class="comment"> * - for parameters if they are used (dynamically)</span></div> +<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span><span class="comment"> * six or more times</span></div> +<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span><span class="comment"> * Note that an optimal &quot;register&quot; strategy is</span></div> +<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span><span class="comment"> * compiler-dependent, and that &quot;register&quot; declarations</span></div> +<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"> 143</span><span class="comment"> * do not necessarily lead to faster execution.</span></div> +<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span><span class="comment"> * -DNOSTRUCTASSIGN (default: Not defined)</span></div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span><span class="comment"> * Define if the C compiler does not support</span></div> +<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span><span class="comment"> * assignment of structures.</span></div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span><span class="comment"> * -DNOENUMS (default: Not defined)</span></div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span><span class="comment"> * Define if the C compiler does not support</span></div> +<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span><span class="comment"> * enumeration types.</span></div> +<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span><span class="comment"> * -DTIMES (default)</span></div> +<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span><span class="comment"> * -DTIME</span></div> +<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span><span class="comment"> * The &quot;times&quot; function of UNIX (returning process times)</span></div> +<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span><span class="comment"> * or the &quot;time&quot; function (returning wallclock time)</span></div> +<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"> 154</span><span class="comment"> * is used for measurement.</span></div> +<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span><span class="comment"> * For single user machines, &quot;time ()&quot; is adequate. For</span></div> +<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span><span class="comment"> * multi-user machines where you cannot get single-user</span></div> +<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span><span class="comment"> * access, use the &quot;times ()&quot; function. If you have</span></div> +<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"> 158</span><span class="comment"> * neither, use a stopwatch in the dead of night.</span></div> +<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"> 159</span><span class="comment"> * &quot;printf&quot;s are provided marking the points &quot;Start Timer&quot;</span></div> +<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span><span class="comment"> * and &quot;Stop Timer&quot;. DO NOT use the UNIX &quot;time(1)&quot;</span></div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span><span class="comment"> * command, as this will measure the total time to</span></div> +<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span><span class="comment"> * run this program, which will (erroneously) include</span></div> +<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"> 163</span><span class="comment"> * the time to allocate storage (malloc) and to perform</span></div> +<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span><span class="comment"> * the initialization.</span></div> +<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span><span class="comment"> * -DHZ=nnn</span></div> +<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"> 166</span><span class="comment"> * In Berkeley UNIX, the function &quot;times&quot; returns process</span></div> +<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span><span class="comment"> * time in 1/HZ seconds, with HZ = 60 for most systems.</span></div> +<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span><span class="comment"> * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY</span></div> +<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"> 169</span><span class="comment"> * A VALUE.</span></div> +<div class="line"><a id="l00170" name="l00170"></a><span class="lineno"> 170</span><span class="comment"> *</span></div> +<div class="line"><a id="l00171" name="l00171"></a><span class="lineno"> 171</span><span class="comment"> ***************************************************************************</span></div> +<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"> 172</span><span class="comment"> *</span></div> +<div class="line"><a id="l00173" name="l00173"></a><span class="lineno"> 173</span><span class="comment"> * Compilation model and measurement (IMPORTANT):</span></div> +<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"> 174</span><span class="comment"> *</span></div> +<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span><span class="comment"> * This C version of Dhrystone consists of three files:</span></div> +<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span><span class="comment"> * - dhry.h (this file, containing global definitions and comments)</span></div> +<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span><span class="comment"> * - dhry_1.c (containing the code corresponding to Ada package Pack_1)</span></div> +<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span><span class="comment"> * - dhry_2.c (containing the code corresponding to Ada package Pack_2)</span></div> +<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span><span class="comment"> *</span></div> +<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span><span class="comment"> * The following &quot;ground rules&quot; apply for measurements:</span></div> +<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span><span class="comment"> * - Separate compilation</span></div> +<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"> 182</span><span class="comment"> * - No procedure merging</span></div> +<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"> 183</span><span class="comment"> * - Otherwise, compiler optimizations are allowed but should be indicated</span></div> +<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"> 184</span><span class="comment"> * - Default results are those without register declarations</span></div> +<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"> 185</span><span class="comment"> * See the companion paper &quot;Rationale for Dhrystone Version 2&quot; for a more</span></div> +<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"> 186</span><span class="comment"> * detailed discussion of these ground rules.</span></div> +<div class="line"><a id="l00187" name="l00187"></a><span class="lineno"> 187</span><span class="comment"> *</span></div> +<div class="line"><a id="l00188" name="l00188"></a><span class="lineno"> 188</span><span class="comment"> * For 16-Bit processors (e.g. 80186, 80286), times for all compilation</span></div> +<div class="line"><a id="l00189" name="l00189"></a><span class="lineno"> 189</span><span class="comment"> * models (&quot;small&quot;, &quot;medium&quot;, &quot;large&quot; etc.) should be given if possible,</span></div> +<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"> 190</span><span class="comment"> * together with a definition of these models for the compiler system used.</span></div> +<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span><span class="comment"> *</span></div> +<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"> 192</span><span class="comment"> **************************************************************************</span></div> +<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span><span class="comment"> *</span></div> +<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span><span class="comment"> * Dhrystone (C version) statistics:</span></div> +<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span><span class="comment"> *</span></div> +<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span><span class="comment"> * [Comment from the first distribution, updated for version 2.</span></div> +<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span><span class="comment"> * Note that because of language differences, the numbers are slightly</span></div> +<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span><span class="comment"> * different from the Ada version.]</span></div> +<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span><span class="comment"> *</span></div> +<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"> 200</span><span class="comment"> * The following program contains statements of a high level programming</span></div> +<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"> 201</span><span class="comment"> * language (here: C) in a distribution considered representative:</span></div> +<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span><span class="comment"> *</span></div> +<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span><span class="comment"> * assignments 52 (51.0 %)</span></div> +<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"> 204</span><span class="comment"> * control statements 33 (32.4 %)</span></div> +<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"> 205</span><span class="comment"> * procedure, function calls 17 (16.7 %)</span></div> +<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"> 206</span><span class="comment"> *</span></div> +<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"> 207</span><span class="comment"> * 103 statements are dynamically executed. The program is balanced with</span></div> +<div class="line"><a id="l00208" name="l00208"></a><span class="lineno"> 208</span><span class="comment"> * respect to the three aspects:</span></div> +<div class="line"><a id="l00209" name="l00209"></a><span class="lineno"> 209</span><span class="comment"> *</span></div> +<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"> 210</span><span class="comment"> * - statement type</span></div> +<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"> 211</span><span class="comment"> * - operand type</span></div> +<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"> 212</span><span class="comment"> * - operand locality</span></div> +<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"> 213</span><span class="comment"> * operand global, local, parameter, or constant.</span></div> +<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"> 214</span><span class="comment"> *</span></div> +<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"> 215</span><span class="comment"> * The combination of these three aspects is balanced only approximately.</span></div> +<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"> 216</span><span class="comment"> *</span></div> +<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"> 217</span><span class="comment"> * 1. Statement Type:</span></div> +<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span><span class="comment"> * ----------------- number</span></div> +<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"> 219</span><span class="comment"> *</span></div> +<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"> 220</span><span class="comment"> * V1 = V2 9</span></div> +<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"> 221</span><span class="comment"> * (incl. V1 = F(..)</span></div> +<div class="line"><a id="l00222" name="l00222"></a><span class="lineno"> 222</span><span class="comment"> * V = Constant 12</span></div> +<div class="line"><a id="l00223" name="l00223"></a><span class="lineno"> 223</span><span class="comment"> * Assignment, 7</span></div> +<div class="line"><a id="l00224" name="l00224"></a><span class="lineno"> 224</span><span class="comment"> * with array element</span></div> +<div class="line"><a id="l00225" name="l00225"></a><span class="lineno"> 225</span><span class="comment"> * Assignment, 6</span></div> +<div class="line"><a id="l00226" name="l00226"></a><span class="lineno"> 226</span><span class="comment"> * with record component</span></div> +<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"> 227</span><span class="comment"> * --</span></div> +<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span><span class="comment"> * 34 34</span></div> +<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span><span class="comment"> *</span></div> +<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span><span class="comment"> * X = Y +|-|&quot;&amp;&amp;&quot;|&quot;|&quot; Z 5</span></div> +<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span><span class="comment"> * X = Y +|-|&quot;==&quot; Constant 6</span></div> +<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span><span class="comment"> * X = X +|- 1 3</span></div> +<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span><span class="comment"> * X = Y *|/ Z 2</span></div> +<div class="line"><a id="l00234" name="l00234"></a><span class="lineno"> 234</span><span class="comment"> * X = Expression, 1</span></div> +<div class="line"><a id="l00235" name="l00235"></a><span class="lineno"> 235</span><span class="comment"> * two operators</span></div> +<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"> 236</span><span class="comment"> * X = Expression, 1</span></div> +<div class="line"><a id="l00237" name="l00237"></a><span class="lineno"> 237</span><span class="comment"> * three operators</span></div> +<div class="line"><a id="l00238" name="l00238"></a><span class="lineno"> 238</span><span class="comment"> * --</span></div> +<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"> 239</span><span class="comment"> * 18 18</span></div> +<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"> 240</span><span class="comment"> *</span></div> +<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"> 241</span><span class="comment"> * if .... 14</span></div> +<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"> 242</span><span class="comment"> * with &quot;else&quot; 7</span></div> +<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"> 243</span><span class="comment"> * without &quot;else&quot; 7</span></div> +<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"> 244</span><span class="comment"> * executed 3</span></div> +<div class="line"><a id="l00245" name="l00245"></a><span class="lineno"> 245</span><span class="comment"> * not executed 4</span></div> +<div class="line"><a id="l00246" name="l00246"></a><span class="lineno"> 246</span><span class="comment"> * for ... 7 | counted every time</span></div> +<div class="line"><a id="l00247" name="l00247"></a><span class="lineno"> 247</span><span class="comment"> * while ... 4 | the loop condition</span></div> +<div class="line"><a id="l00248" name="l00248"></a><span class="lineno"> 248</span><span class="comment"> * do ... while 1 | is evaluated</span></div> +<div class="line"><a id="l00249" name="l00249"></a><span class="lineno"> 249</span><span class="comment"> * switch ... 1</span></div> +<div class="line"><a id="l00250" name="l00250"></a><span class="lineno"> 250</span><span class="comment"> * break 1</span></div> +<div class="line"><a id="l00251" name="l00251"></a><span class="lineno"> 251</span><span class="comment"> * declaration with 1</span></div> +<div class="line"><a id="l00252" name="l00252"></a><span class="lineno"> 252</span><span class="comment"> * initialization</span></div> +<div class="line"><a id="l00253" name="l00253"></a><span class="lineno"> 253</span><span class="comment"> * --</span></div> +<div class="line"><a id="l00254" name="l00254"></a><span class="lineno"> 254</span><span class="comment"> * 34 34</span></div> +<div class="line"><a id="l00255" name="l00255"></a><span class="lineno"> 255</span><span class="comment"> *</span></div> +<div class="line"><a id="l00256" name="l00256"></a><span class="lineno"> 256</span><span class="comment"> * P (...) procedure call 11</span></div> +<div class="line"><a id="l00257" name="l00257"></a><span class="lineno"> 257</span><span class="comment"> * user procedure 10</span></div> +<div class="line"><a id="l00258" name="l00258"></a><span class="lineno"> 258</span><span class="comment"> * library procedure 1</span></div> +<div class="line"><a id="l00259" name="l00259"></a><span class="lineno"> 259</span><span class="comment"> * X = F (...)</span></div> +<div class="line"><a id="l00260" name="l00260"></a><span class="lineno"> 260</span><span class="comment"> * function call 6</span></div> +<div class="line"><a id="l00261" name="l00261"></a><span class="lineno"> 261</span><span class="comment"> * user function 5</span></div> +<div class="line"><a id="l00262" name="l00262"></a><span class="lineno"> 262</span><span class="comment"> * library function 1</span></div> +<div class="line"><a id="l00263" name="l00263"></a><span class="lineno"> 263</span><span class="comment"> * --</span></div> +<div class="line"><a id="l00264" name="l00264"></a><span class="lineno"> 264</span><span class="comment"> * 17 17</span></div> +<div class="line"><a id="l00265" name="l00265"></a><span class="lineno"> 265</span><span class="comment"> * ---</span></div> +<div class="line"><a id="l00266" name="l00266"></a><span class="lineno"> 266</span><span class="comment"> * 103</span></div> +<div class="line"><a id="l00267" name="l00267"></a><span class="lineno"> 267</span><span class="comment"> *</span></div> +<div class="line"><a id="l00268" name="l00268"></a><span class="lineno"> 268</span><span class="comment"> * The average number of parameters in procedure or function calls</span></div> +<div class="line"><a id="l00269" name="l00269"></a><span class="lineno"> 269</span><span class="comment"> * is 1.82 (not counting the function values aX *</span></div> +<div class="line"><a id="l00270" name="l00270"></a><span class="lineno"> 270</span><span class="comment"> *</span></div> +<div class="line"><a id="l00271" name="l00271"></a><span class="lineno"> 271</span><span class="comment"> * 2. Operators</span></div> +<div class="line"><a id="l00272" name="l00272"></a><span class="lineno"> 272</span><span class="comment"> * ------------</span></div> +<div class="line"><a id="l00273" name="l00273"></a><span class="lineno"> 273</span><span class="comment"> * number approximate</span></div> +<div class="line"><a id="l00274" name="l00274"></a><span class="lineno"> 274</span><span class="comment"> * percentage</span></div> +<div class="line"><a id="l00275" name="l00275"></a><span class="lineno"> 275</span><span class="comment"> *</span></div> +<div class="line"><a id="l00276" name="l00276"></a><span class="lineno"> 276</span><span class="comment"> * Arithmetic 32 50.8</span></div> +<div class="line"><a id="l00277" name="l00277"></a><span class="lineno"> 277</span><span class="comment"> *</span></div> +<div class="line"><a id="l00278" name="l00278"></a><span class="lineno"> 278</span><span class="comment"> * + 21 33.3</span></div> +<div class="line"><a id="l00279" name="l00279"></a><span class="lineno"> 279</span><span class="comment"> * - 7 11.1</span></div> +<div class="line"><a id="l00280" name="l00280"></a><span class="lineno"> 280</span><span class="comment"> * * 3 4.8</span></div> +<div class="line"><a id="l00281" name="l00281"></a><span class="lineno"> 281</span><span class="comment"> * / (int div) 1 1.6</span></div> +<div class="line"><a id="l00282" name="l00282"></a><span class="lineno"> 282</span><span class="comment"> *</span></div> +<div class="line"><a id="l00283" name="l00283"></a><span class="lineno"> 283</span><span class="comment"> * Comparison 27 42.8</span></div> +<div class="line"><a id="l00284" name="l00284"></a><span class="lineno"> 284</span><span class="comment"> *</span></div> +<div class="line"><a id="l00285" name="l00285"></a><span class="lineno"> 285</span><span class="comment"> * == 9 14.3</span></div> +<div class="line"><a id="l00286" name="l00286"></a><span class="lineno"> 286</span><span class="comment"> * /= 4 6.3</span></div> +<div class="line"><a id="l00287" name="l00287"></a><span class="lineno"> 287</span><span class="comment"> * &gt; 1 1.6</span></div> +<div class="line"><a id="l00288" name="l00288"></a><span class="lineno"> 288</span><span class="comment"> * &lt; 3 4.8</span></div> +<div class="line"><a id="l00289" name="l00289"></a><span class="lineno"> 289</span><span class="comment"> * &gt;= 1 1.6</span></div> +<div class="line"><a id="l00290" name="l00290"></a><span class="lineno"> 290</span><span class="comment"> * &lt;= 9 14.3</span></div> +<div class="line"><a id="l00291" name="l00291"></a><span class="lineno"> 291</span><span class="comment"> *</span></div> +<div class="line"><a id="l00292" name="l00292"></a><span class="lineno"> 292</span><span class="comment"> * Logic 4 6.3</span></div> +<div class="line"><a id="l00293" name="l00293"></a><span class="lineno"> 293</span><span class="comment"> *</span></div> +<div class="line"><a id="l00294" name="l00294"></a><span class="lineno"> 294</span><span class="comment"> * &amp;&amp; (AND-THEN) 1 1.6</span></div> +<div class="line"><a id="l00295" name="l00295"></a><span class="lineno"> 295</span><span class="comment"> * | (OR) 1 1.6</span></div> +<div class="line"><a id="l00296" name="l00296"></a><span class="lineno"> 296</span><span class="comment"> * ! (NOT) 2 3.2</span></div> +<div class="line"><a id="l00297" name="l00297"></a><span class="lineno"> 297</span><span class="comment"> *</span></div> +<div class="line"><a id="l00298" name="l00298"></a><span class="lineno"> 298</span><span class="comment"> * -- -----</span></div> +<div class="line"><a id="l00299" name="l00299"></a><span class="lineno"> 299</span><span class="comment"> * 63 100.1</span></div> +<div class="line"><a id="l00300" name="l00300"></a><span class="lineno"> 300</span><span class="comment"> *</span></div> +<div class="line"><a id="l00301" name="l00301"></a><span class="lineno"> 301</span><span class="comment"> *</span></div> +<div class="line"><a id="l00302" name="l00302"></a><span class="lineno"> 302</span><span class="comment"> * 3. Operand Type (counted once per operand reference):</span></div> +<div class="line"><a id="l00303" name="l00303"></a><span class="lineno"> 303</span><span class="comment"> * ---------------</span></div> +<div class="line"><a id="l00304" name="l00304"></a><span class="lineno"> 304</span><span class="comment"> * number approximate</span></div> +<div class="line"><a id="l00305" name="l00305"></a><span class="lineno"> 305</span><span class="comment"> * percentage</span></div> +<div class="line"><a id="l00306" name="l00306"></a><span class="lineno"> 306</span><span class="comment"> *</span></div> +<div class="line"><a id="l00307" name="l00307"></a><span class="lineno"> 307</span><span class="comment"> * Integer 175 72.3 %</span></div> +<div class="line"><a id="l00308" name="l00308"></a><span class="lineno"> 308</span><span class="comment"> * Character 45 18.6 %</span></div> +<div class="line"><a id="l00309" name="l00309"></a><span class="lineno"> 309</span><span class="comment"> * Pointer 12 5.0 %</span></div> +<div class="line"><a id="l00310" name="l00310"></a><span class="lineno"> 310</span><span class="comment"> * String30 6 2.5 %</span></div> +<div class="line"><a id="l00311" name="l00311"></a><span class="lineno"> 311</span><span class="comment"> * Array 2 0.8 %</span></div> +<div class="line"><a id="l00312" name="l00312"></a><span class="lineno"> 312</span><span class="comment"> * Record 2 0.8 %</span></div> +<div class="line"><a id="l00313" name="l00313"></a><span class="lineno"> 313</span><span class="comment"> * --- -------</span></div> +<div class="line"><a id="l00314" name="l00314"></a><span class="lineno"> 314</span><span class="comment"> * 242 100.0 %</span></div> +<div class="line"><a id="l00315" name="l00315"></a><span class="lineno"> 315</span><span class="comment"> *</span></div> +<div class="line"><a id="l00316" name="l00316"></a><span class="lineno"> 316</span><span class="comment"> * When there is an access path leading to the final operand (e.g. a record</span></div> +<div class="line"><a id="l00317" name="l00317"></a><span class="lineno"> 317</span><span class="comment"> * component), only the final data type on the access path is counted.</span></div> +<div class="line"><a id="l00318" name="l00318"></a><span class="lineno"> 318</span><span class="comment"> *</span></div> +<div class="line"><a id="l00319" name="l00319"></a><span class="lineno"> 319</span><span class="comment"> *</span></div> +<div class="line"><a id="l00320" name="l00320"></a><span class="lineno"> 320</span><span class="comment"> * 4. Operand Locality:</span></div> +<div class="line"><a id="l00321" name="l00321"></a><span class="lineno"> 321</span><span class="comment"> * -------------------</span></div> +<div class="line"><a id="l00322" name="l00322"></a><span class="lineno"> 322</span><span class="comment"> * number approximate</span></div> +<div class="line"><a id="l00323" name="l00323"></a><span class="lineno"> 323</span><span class="comment"> * percentage</span></div> +<div class="line"><a id="l00324" name="l00324"></a><span class="lineno"> 324</span><span class="comment"> *</span></div> +<div class="line"><a id="l00325" name="l00325"></a><span class="lineno"> 325</span><span class="comment"> * local variable 114 47.1 %</span></div> +<div class="line"><a id="l00326" name="l00326"></a><span class="lineno"> 326</span><span class="comment"> * global variable 22 9.1 %</span></div> +<div class="line"><a id="l00327" name="l00327"></a><span class="lineno"> 327</span><span class="comment"> * parameter 45 18.6 %</span></div> +<div class="line"><a id="l00328" name="l00328"></a><span class="lineno"> 328</span><span class="comment"> * value 23 9.5 %</span></div> +<div class="line"><a id="l00329" name="l00329"></a><span class="lineno"> 329</span><span class="comment"> * reference 22 9.1 %</span></div> +<div class="line"><a id="l00330" name="l00330"></a><span class="lineno"> 330</span><span class="comment"> * function result 6 2.5 %</span></div> +<div class="line"><a id="l00331" name="l00331"></a><span class="lineno"> 331</span><span class="comment"> * constant 55 22.7 %</span></div> +<div class="line"><a id="l00332" name="l00332"></a><span class="lineno"> 332</span><span class="comment"> * --- -------</span></div> +<div class="line"><a id="l00333" name="l00333"></a><span class="lineno"> 333</span><span class="comment"> * 242 100.0 %</span></div> +<div class="line"><a id="l00334" name="l00334"></a><span class="lineno"> 334</span><span class="comment"> *</span></div> +<div class="line"><a id="l00335" name="l00335"></a><span class="lineno"> 335</span><span class="comment"> *</span></div> +<div class="line"><a id="l00336" name="l00336"></a><span class="lineno"> 336</span><span class="comment"> * The program does not compute anything meaningful, but it is syntactically</span></div> +<div class="line"><a id="l00337" name="l00337"></a><span class="lineno"> 337</span><span class="comment"> * and semantically correct. All variables have a value assigned to them</span></div> +<div class="line"><a id="l00338" name="l00338"></a><span class="lineno"> 338</span><span class="comment"> * before they are used as a source operand.</span></div> +<div class="line"><a id="l00339" name="l00339"></a><span class="lineno"> 339</span><span class="comment"> *</span></div> +<div class="line"><a id="l00340" name="l00340"></a><span class="lineno"> 340</span><span class="comment"> * There has been no explicit effort to account for the effects of a</span></div> +<div class="line"><a id="l00341" name="l00341"></a><span class="lineno"> 341</span><span class="comment"> * cache, or to balance the use of long or short displacements for code or</span></div> +<div class="line"><a id="l00342" name="l00342"></a><span class="lineno"> 342</span><span class="comment"> * data.</span></div> +<div class="line"><a id="l00343" name="l00343"></a><span class="lineno"> 343</span><span class="comment"> *</span></div> +<div class="line"><a id="l00344" name="l00344"></a><span class="lineno"> 344</span><span class="comment"> ***************************************************************************</span></div> +<div class="line"><a id="l00345" name="l00345"></a><span class="lineno"> 345</span><span class="comment"> */</span></div> +<div class="line"><a id="l00346" name="l00346"></a><span class="lineno"> 346</span> </div> +<div class="line"><a id="l00347" name="l00347"></a><span class="lineno"> 347</span><span class="preprocessor">#ifndef dhrystone_h</span></div> +<div class="line"><a id="l00348" name="l00348"></a><span class="lineno"> 348</span><span class="preprocessor">#define dhrystone_h</span></div> +<div class="line"><a id="l00349" name="l00349"></a><span class="lineno"> 349</span> </div> +<div class="line"><a id="l00350" name="l00350"></a><span class="lineno"> 350</span><span class="comment">/* Compiler and system dependent definitions: */</span></div> +<div class="line"><a id="l00351" name="l00351"></a><span class="lineno"> 351</span> </div> +<div class="line"><a id="l00352" name="l00352"></a><span class="lineno"> 352</span><span class="preprocessor">#ifndef TIME</span></div> +<div class="line"><a id="l00353" name="l00353"></a><span class="lineno"> 353</span><span class="preprocessor">#undef TIMES</span></div> +<div class="line"><a id="l00354" name="l00354"></a><span class="lineno"> 354</span><span class="preprocessor">#define TIMES</span></div> +<div class="line"><a id="l00355" name="l00355"></a><span class="lineno"> 355</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00356" name="l00356"></a><span class="lineno"> 356</span> <span class="comment">/* Use times(2) time function unless */</span></div> +<div class="line"><a id="l00357" name="l00357"></a><span class="lineno"> 357</span> <span class="comment">/* explicitly defined otherwise */</span></div> +<div class="line"><a id="l00358" name="l00358"></a><span class="lineno"> 358</span> </div> +<div class="line"><a id="l00359" name="l00359"></a><span class="lineno"> 359</span><span class="comment">//#ifdef MSC_CLOCK</span></div> +<div class="line"><a id="l00360" name="l00360"></a><span class="lineno"> 360</span><span class="comment">//#undef HZ</span></div> +<div class="line"><a id="l00361" name="l00361"></a><span class="lineno"> 361</span><span class="comment">//#undef TIMES</span></div> +<div class="line"><a id="l00362" name="l00362"></a><span class="lineno"> 362</span><span class="comment">//#include &lt;time.h&gt;</span></div> +<div class="line"><a id="l00363" name="l00363"></a><span class="lineno"> 363</span><span class="comment">//#define HZ CLK_TCK</span></div> +<div class="line"><a id="l00364" name="l00364"></a><span class="lineno"> 364</span><span class="comment">//#endif</span></div> +<div class="line"><a id="l00365" name="l00365"></a><span class="lineno"> 365</span><span class="comment">// /* Use Microsoft C hi-res clock */</span></div> +<div class="line"><a id="l00366" name="l00366"></a><span class="lineno"> 366</span> </div> +<div class="line"><a id="l00367" name="l00367"></a><span class="lineno"> 367</span><span class="preprocessor">#define HZ SYSINFO_CLK</span></div> +<div class="line"><a id="l00368" name="l00368"></a><span class="lineno"> 368</span> </div> +<div class="line"><a id="l00369" name="l00369"></a><span class="lineno"> 369</span><span class="preprocessor">#ifdef TIMES</span></div> +<div class="line"><a id="l00370" name="l00370"></a><span class="lineno"> 370</span><span class="preprocessor">#include &lt;sys/types.h&gt;</span></div> +<div class="line"><a id="l00371" name="l00371"></a><span class="lineno"> 371</span><span class="preprocessor">#include &lt;sys/times.h&gt;</span></div> +<div class="line"><a id="l00372" name="l00372"></a><span class="lineno"> 372</span> <span class="comment">/* for &quot;times&quot; */</span></div> +<div class="line"><a id="l00373" name="l00373"></a><span class="lineno"> 373</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00374" name="l00374"></a><span class="lineno"> 374</span> </div> +<div class="line"><a id="l00375" name="l00375"></a><span class="lineno"> 375</span><span class="preprocessor">#define Mic_secs_Per_Second 1000000</span></div> +<div class="line"><a id="l00376" name="l00376"></a><span class="lineno"> 376</span> <span class="comment">/* Berkeley UNIX C returns process times in seconds/HZ */</span></div> +<div class="line"><a id="l00377" name="l00377"></a><span class="lineno"> 377</span> </div> +<div class="line"><a id="l00378" name="l00378"></a><span class="lineno"> 378</span><span class="preprocessor">#ifdef NOSTRUCTASSIGN</span></div> +<div class="line"><a id="l00379" name="l00379"></a><span class="lineno"> 379</span><span class="preprocessor">#define structassign(d, s) memcpy(&amp;(d), &amp;(s), sizeof(d))</span></div> +<div class="line"><a id="l00380" name="l00380"></a><span class="lineno"> 380</span><span class="preprocessor">#else</span></div> +<div class="line"><a id="l00381" name="l00381"></a><span class="lineno"> 381</span><span class="preprocessor">#define structassign(d, s) d = s</span></div> +<div class="line"><a id="l00382" name="l00382"></a><span class="lineno"> 382</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00383" name="l00383"></a><span class="lineno"> 383</span> </div> +<div class="line"><a id="l00384" name="l00384"></a><span class="lineno"> 384</span><span class="preprocessor">#ifdef NOENUM</span></div> +<div class="line"><a id="l00385" name="l00385"></a><span class="lineno"> 385</span><span class="preprocessor">#define Ident_1 0</span></div> +<div class="line"><a id="l00386" name="l00386"></a><span class="lineno"> 386</span><span class="preprocessor">#define Ident_2 1</span></div> +<div class="line"><a id="l00387" name="l00387"></a><span class="lineno"> 387</span><span class="preprocessor">#define Ident_3 2</span></div> +<div class="line"><a id="l00388" name="l00388"></a><span class="lineno"> 388</span><span class="preprocessor">#define Ident_4 3</span></div> +<div class="line"><a id="l00389" name="l00389"></a><span class="lineno"> 389</span><span class="preprocessor">#define Ident_5 4</span></div> +<div class="line"><a id="l00390" name="l00390"></a><span class="lineno"> 390</span> <span class="keyword">typedef</span> <span class="keywordtype">int</span> Enumeration;</div> +<div class="line"><a id="l00391" name="l00391"></a><span class="lineno"> 391</span><span class="preprocessor">#else</span></div> +<div class="line"><a id="l00392" name="l00392"></a><span class="lineno"> 392</span> <span class="keyword">typedef</span> <span class="keyword">enum</span> {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}</div> +<div class="line"><a id="l00393" name="l00393"></a><span class="lineno"> 393</span> Enumeration;</div> +<div class="line"><a id="l00394" name="l00394"></a><span class="lineno"> 394</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00395" name="l00395"></a><span class="lineno"> 395</span> <span class="comment">/* for boolean and enumeration types in Ada, Pascal */</span></div> +<div class="line"><a id="l00396" name="l00396"></a><span class="lineno"> 396</span> </div> +<div class="line"><a id="l00397" name="l00397"></a><span class="lineno"> 397</span><span class="comment">/* General definitions: */</span></div> +<div class="line"><a id="l00398" name="l00398"></a><span class="lineno"> 398</span> </div> +<div class="line"><a id="l00399" name="l00399"></a><span class="lineno"> 399</span><span class="preprocessor">#include &lt;stdio.h&gt;</span></div> +<div class="line"><a id="l00400" name="l00400"></a><span class="lineno"> 400</span> <span class="comment">/* for strcpy, strcmp */</span></div> +<div class="line"><a id="l00401" name="l00401"></a><span class="lineno"> 401</span> </div> +<div class="line"><a id="l00402" name="l00402"></a><span class="lineno"> 402</span><span class="preprocessor">#define Null 0</span></div> +<div class="line"><a id="l00403" name="l00403"></a><span class="lineno"> 403</span> <span class="comment">/* Value of a Null pointer */</span></div> +<div class="line"><a id="l00404" name="l00404"></a><span class="lineno"> 404</span><span class="preprocessor">#define true 1</span></div> +<div class="line"><a id="l00405" name="l00405"></a><span class="lineno"> 405</span><span class="preprocessor">#define false 0</span></div> +<div class="line"><a id="l00406" name="l00406"></a><span class="lineno"> 406</span> </div> +<div class="line"><a id="l00407" name="l00407"></a><span class="lineno"> 407</span><span class="keyword">typedef</span> <span class="keywordtype">int</span> One_Thirty;</div> +<div class="line"><a id="l00408" name="l00408"></a><span class="lineno"> 408</span><span class="keyword">typedef</span> <span class="keywordtype">int</span> One_Fifty;</div> +<div class="line"><a id="l00409" name="l00409"></a><span class="lineno"> 409</span><span class="keyword">typedef</span> <span class="keywordtype">char</span> Capital_Letter;</div> +<div class="line"><a id="l00410" name="l00410"></a><span class="lineno"> 410</span><span class="keyword">typedef</span> <span class="keywordtype">int</span> Boolean;</div> +<div class="line"><a id="l00411" name="l00411"></a><span class="lineno"> 411</span><span class="keyword">typedef</span> <span class="keywordtype">char</span> Str_30 [31];</div> +<div class="line"><a id="l00412" name="l00412"></a><span class="lineno"> 412</span><span class="keyword">typedef</span> <span class="keywordtype">int</span> Arr_1_Dim [50];</div> +<div class="line"><a id="l00413" name="l00413"></a><span class="lineno"> 413</span><span class="keyword">typedef</span> <span class="keywordtype">int</span> Arr_2_Dim [50] [50];</div> +<div class="line"><a id="l00414" name="l00414"></a><span class="lineno"> 414</span> </div> +<div class="foldopen" id="foldopen00415" data-start="{" data-end="};"> +<div class="line"><a id="l00415" name="l00415"></a><span class="lineno"><a class="line" href="structrecord.html"> 415</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structrecord.html">record</a></div> +<div class="line"><a id="l00416" name="l00416"></a><span class="lineno"> 416</span> {</div> +<div class="line"><a id="l00417" name="l00417"></a><span class="lineno"> 417</span> <span class="keyword">struct </span><a class="code hl_struct" href="structrecord.html">record</a> *Ptr_Comp;</div> +<div class="line"><a id="l00418" name="l00418"></a><span class="lineno"> 418</span> Enumeration Discr;</div> +<div class="line"><a id="l00419" name="l00419"></a><span class="lineno"> 419</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00420" name="l00420"></a><span class="lineno"> 420</span> <span class="keyword">struct </span>{</div> +<div class="line"><a id="l00421" name="l00421"></a><span class="lineno"> 421</span> Enumeration Enum_Comp;</div> +<div class="line"><a id="l00422" name="l00422"></a><span class="lineno"> 422</span> <span class="keywordtype">int</span> Int_Comp;</div> +<div class="line"><a id="l00423" name="l00423"></a><span class="lineno"> 423</span> <span class="keywordtype">char</span> Str_Comp [31];</div> +<div class="line"><a id="l00424" name="l00424"></a><span class="lineno"> 424</span> } var_1;</div> +<div class="line"><a id="l00425" name="l00425"></a><span class="lineno"> 425</span> <span class="keyword">struct </span>{</div> +<div class="line"><a id="l00426" name="l00426"></a><span class="lineno"> 426</span> Enumeration E_Comp_2;</div> +<div class="line"><a id="l00427" name="l00427"></a><span class="lineno"> 427</span> <span class="keywordtype">char</span> Str_2_Comp [31];</div> +<div class="line"><a id="l00428" name="l00428"></a><span class="lineno"> 428</span> } var_2;</div> +<div class="line"><a id="l00429" name="l00429"></a><span class="lineno"> 429</span> <span class="keyword">struct </span>{</div> +<div class="line"><a id="l00430" name="l00430"></a><span class="lineno"> 430</span> <span class="keywordtype">char</span> Ch_1_Comp;</div> +<div class="line"><a id="l00431" name="l00431"></a><span class="lineno"> 431</span> <span class="keywordtype">char</span> Ch_2_Comp;</div> +<div class="line"><a id="l00432" name="l00432"></a><span class="lineno"> 432</span> } var_3;</div> +<div class="line"><a id="l00433" name="l00433"></a><span class="lineno"> 433</span> } variant;</div> +<div class="line"><a id="l00434" name="l00434"></a><span class="lineno"> 434</span> } <a class="code hl_struct" href="structrecord.html">Rec_Type</a>, *<a class="code hl_struct" href="structrecord.html">Rec_Pointer</a>;</div> +</div> +<div class="line"><a id="l00435" name="l00435"></a><span class="lineno"> 435</span> </div> +<div class="line"><a id="l00436" name="l00436"></a><span class="lineno"> 436</span> </div> +<div class="line"><a id="l00437" name="l00437"></a><span class="lineno"> 437</span><span class="comment">// function prototypes</span></div> +<div class="line"><a id="l00438" name="l00438"></a><span class="lineno"> 438</span>Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val);</div> +<div class="line"><a id="l00439" name="l00439"></a><span class="lineno"> 439</span>Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref);</div> +<div class="line"><a id="l00440" name="l00440"></a><span class="lineno"> 440</span>Boolean Func_3 (Enum_Par_Val);</div> +<div class="line"><a id="l00441" name="l00441"></a><span class="lineno"> 441</span><span class="keywordtype">void</span> Proc_1 (Ptr_Val_Par);</div> +<div class="line"><a id="l00442" name="l00442"></a><span class="lineno"> 442</span><span class="keywordtype">void</span> Proc_2 (Int_Par_Ref);</div> +<div class="line"><a id="l00443" name="l00443"></a><span class="lineno"> 443</span><span class="keywordtype">void</span> Proc_3 (Ptr_Ref_Par);</div> +<div class="line"><a id="l00444" name="l00444"></a><span class="lineno"> 444</span><span class="keywordtype">void</span> Proc_4 (<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00445" name="l00445"></a><span class="lineno"> 445</span><span class="keywordtype">void</span> Proc_5 (<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00446" name="l00446"></a><span class="lineno"> 446</span><span class="keywordtype">void</span> Proc_6 (Enum_Val_Par, Enum_Ref_Par);</div> +<div class="line"><a id="l00447" name="l00447"></a><span class="lineno"> 447</span><span class="keywordtype">void</span> Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref);</div> +<div class="line"><a id="l00448" name="l00448"></a><span class="lineno"> 448</span><span class="keywordtype">void</span> Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val);</div> +<div class="line"><a id="l00449" name="l00449"></a><span class="lineno"> 449</span><span class="keywordtype">int</span> strcmp(<span class="keyword">const</span> <span class="keywordtype">char</span> *p1, <span class="keyword">const</span> <span class="keywordtype">char</span> *p2);</div> +<div class="line"><a id="l00450" name="l00450"></a><span class="lineno"> 450</span> </div> +<div class="line"><a id="l00451" name="l00451"></a><span class="lineno"> 451</span><span class="preprocessor">#endif </span><span class="comment">// dhrystone_h</span></div> +<div class="ttc" id="astructrecord_html"><div class="ttname"><a href="structrecord.html">record</a></div><div class="ttdef"><b>Definition</b> dhry.h:416</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git 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+--group-header-color: #90A5CE; +--inherit-header-color: #A0A0A0; + +--footer-foreground-color: #5B7AB7; +--footer-logo-width: 60px; +--citation-label-color: #90A5CE; +--glow-color: cyan; + +--title-background-color: #090D16; +--title-separator-color: #354C79; +--directory-separator-color: #283A5D; +--separator-color: #283A5D; + +--blockquote-background-color: #101826; +--blockquote-border-color: #283A5D; + +--scrollbar-thumb-color: #283A5D; +--scrollbar-background-color: #070B11; + +--icon-background-color: #334975; +--icon-foreground-color: #C4CFE5; +--icon-doc-image: url('docd.svg'); +--icon-folder-open-image: url('folderopend.svg'); +--icon-folder-closed-image: url('folderclosedd.svg'); + +/* brief member declaration list */ +--memdecl-background-color: #0B101A; +--memdecl-separator-color: #2C3F65; +--memdecl-foreground-color: #BBB; +--memdecl-template-color: #7C95C6; + +/* detailed member list */ +--memdef-border-color: #233250; +--memdef-title-background-color: #1B2840; +--memdef-title-gradient-image: url('nav_fd.png'); +--memdef-proto-background-color: #19243A; +--memdef-proto-text-color: #9DB0D4; +--memdef-proto-text-shadow: 0px 1px 1px rgba(0, 0, 0, 0.9); +--memdef-doc-background-color: black; +--memdef-param-name-color: #D28757; +--memdef-template-color: #7C95C6; + +/* tables */ +--table-cell-border-color: #283A5D; +--table-header-background-color: #283A5D; +--table-header-foreground-color: #C4CFE5; + +/* labels */ +--label-background-color: #354C7B; +--label-left-top-border-color: #4665A2; +--label-right-bottom-border-color: #283A5D; +--label-foreground-color: #CCCCCC; + +/** navigation bar/tree/menu */ +--nav-background-color: #101826; +--nav-foreground-color: #364D7C; +--nav-gradient-image: url('tab_bd.png'); +--nav-gradient-hover-image: url('tab_hd.png'); +--nav-gradient-active-image: url('tab_ad.png'); +--nav-gradient-active-image-parent: url("../tab_ad.png"); +--nav-separator-image: url('tab_sd.png'); +--nav-breadcrumb-image: url('bc_sd.png'); +--nav-breadcrumb-border-color: #2A3D61; +--nav-splitbar-image: url('splitbard.png'); +--nav-font-size-level1: 13px; +--nav-font-size-level2: 10px; +--nav-font-size-level3: 9px; +--nav-text-normal-color: #B6C4DF; +--nav-text-hover-color: #DCE2EF; +--nav-text-active-color: #DCE2EF; +--nav-text-normal-shadow: 0px 1px 1px black; +--nav-text-hover-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +--nav-text-active-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +--nav-menu-button-color: #B6C4DF; +--nav-menu-background-color: #05070C; +--nav-menu-foreground-color: #BBBBBB; +--nav-menu-toggle-color: rgba(255, 255, 255, 0.2); +--nav-arrow-color: #334975; +--nav-arrow-selected-color: #90A5CE; + +/* table of contents */ +--toc-background-color: #151E30; +--toc-border-color: #202E4A; +--toc-header-color: #A3B4D7; +--toc-down-arrow-image: url("data:image/svg+xml;utf8,<svg xmlns='http://www.w3.org/2000/svg' version='1.1' height='10px' width='5px'><text x='0' y='5' font-size='10' fill='grey'>&%238595;</text></svg>"); + +/** search field */ +--search-background-color: black; +--search-foreground-color: #C5C5C5; +--search-magnification-image: url('mag_d.svg'); +--search-magnification-select-image: url('mag_seld.svg'); +--search-active-color: #C5C5C5; +--search-filter-background-color: #101826; +--search-filter-foreground-color: #90A5CE; +--search-filter-border-color: #7C95C6; +--search-filter-highlight-text-color: #BCC9E2; +--search-filter-highlight-bg-color: #283A5D; +--search-results-background-color: #101826; +--search-results-foreground-color: #90A5CE; +--search-results-border-color: #7C95C6; +--search-box-shadow: inset 0.5px 0.5px 3px 0px #2F436C; + +/** code fragments */ +--code-keyword-color: #CC99CD; +--code-type-keyword-color: #AB99CD; +--code-flow-keyword-color: #E08000; +--code-comment-color: #717790; +--code-preprocessor-color: #65CABE; +--code-string-literal-color: #7EC699; +--code-char-literal-color: #00E0F0; +--code-xml-cdata-color: #C9D1D9; +--code-vhdl-digit-color: #FF00FF; +--code-vhdl-char-color: #C0C0C0; +--code-vhdl-keyword-color: #CF53C9; +--code-vhdl-logic-color: #FF0000; +--code-link-color: #79C0FF; +--code-external-link-color: #79C0FF; +--fragment-foreground-color: #C9D1D9; +--fragment-background-color: #090D16; +--fragment-border-color: #30363D; +--fragment-lineno-border-color: #30363D; +--fragment-lineno-background-color: black; +--fragment-lineno-foreground-color: #6E7681; +--fragment-lineno-link-fg-color: #6E7681; +--fragment-lineno-link-bg-color: #303030; +--fragment-lineno-link-hover-fg-color: #8E96A1; +--fragment-lineno-link-hover-bg-color: #505050; +--fragment-copy-ok-color: #0EA80E; +--tooltip-foreground-color: #C9D1D9; +--tooltip-background-color: #202020; +--tooltip-border-color: #C9D1D9; +--tooltip-doc-color: #D9E1E9; +--tooltip-declaration-color: #20C348; +--tooltip-link-color: #79C0FF; +--tooltip-shadow: none; +--fold-line-color: #808080; +--fold-minus-image: url('minusd.svg'); +--fold-plus-image: url('plusd.svg'); +--fold-minus-image-relpath: url('../../minusd.svg'); +--fold-plus-image-relpath: url('../../plusd.svg'); + +/** font-family */ +--font-family-normal: Roboto,sans-serif; +--font-family-monospace: 'JetBrains Mono',Consolas,Monaco,'Andale Mono','Ubuntu Mono',monospace,fixed; +--font-family-nav: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; +--font-family-title: Tahoma,Arial,sans-serif; +--font-family-toc: Verdana,'DejaVu Sans',Geneva,sans-serif; +--font-family-search: Arial,Verdana,sans-serif; +--font-family-icon: Arial,Helvetica; +--font-family-tooltip: Roboto,sans-serif; + +/** special sections */ +--warning-color-bg: #2e1917; +--warning-color-hl: #ad2617; +--warning-color-text: #f5b1aa; +--note-color-bg: #3b2e04; +--note-color-hl: #f1b602; +--note-color-text: #ceb670; +--todo-color-bg: #163750; +--todo-color-hl: #1982D2; +--todo-color-text: #dcf0fa; +--test-color-bg: #121258; +--test-color-hl: #4242cf; +--test-color-text: #c0c0da; +--deprecated-color-bg: #2e323b; +--deprecated-color-hl: #738396; +--deprecated-color-text: #abb0bd; +--bug-color-bg: #2a2536; +--bug-color-hl: #7661b3; +--bug-color-text: #ae9ed6; +--invariant-color-bg: #303a35; +--invariant-color-hl: #76ce96; +--invariant-color-text: #cceed5; +}} +body { + background-color: var(--page-background-color); + color: var(--page-foreground-color); +} + +body, table, div, p, dl { + font-weight: 400; + font-size: 14px; + font-family: var(--font-family-normal); + line-height: 22px; +} + +/* @group Heading Levels */ + +.title { + font-family: var(--font-family-normal); + line-height: 28px; + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h1.groupheader { + font-size: 150%; +} + +h2.groupheader { + border-bottom: 1px solid var(--group-header-separator-color); + color: var(--group-header-color); + font-size: 150%; + font-weight: normal; + margin-top: 1.75em; + padding-top: 8px; + padding-bottom: 4px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px var(--glow-color); +} + +dt { + font-weight: bold; +} + +p.startli, p.startdd { + margin-top: 2px; +} + +th p.starttd, th p.intertd, th p.endtd { + font-size: 100%; + font-weight: 700; +} + +p.starttd { + margin-top: 0px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +p.interli { +} + +p.interdd { +} + +p.intertd { +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.navtab { + padding-right: 15px; + text-align: right; + line-height: 110%; +} + +div.navtab table { + border-spacing: 0; +} + +td.navtab { + padding-right: 6px; + padding-left: 6px; +} + +td.navtabHL { + background-image: var(--nav-gradient-active-image); + background-repeat:repeat-x; + padding-right: 6px; + padding-left: 6px; +} + +td.navtabHL a, td.navtabHL a:visited { + color: var(--nav-text-hover-color); + text-shadow: var(--nav-text-hover-shadow); +} + +a.navtab { + font-weight: bold; +} + +div.qindex{ + text-align: center; + width: 100%; + line-height: 140%; + font-size: 130%; + color: var(--index-separator-color); +} + +#main-menu a:focus { + outline: auto; + z-index: 10; + position: relative; +} + +dt.alphachar{ + font-size: 180%; + font-weight: bold; +} + +.alphachar a{ + color: var(--index-header-color); +} + +.alphachar a:hover, .alphachar a:visited{ + text-decoration: none; +} + +.classindex dl { + padding: 25px; + column-count:1 +} + +.classindex dd { + display:inline-block; + margin-left: 50px; + width: 90%; + line-height: 1.15em; +} + +.classindex dl.even { + background-color: var(--index-even-item-bg-color); +} + +.classindex dl.odd { + background-color: var(--index-odd-item-bg-color); +} + +@media(min-width: 1120px) { + .classindex dl { + column-count:2 + } +} + +@media(min-width: 1320px) { + .classindex dl { + column-count:3 + } +} + + +/* @group Link Styling */ + +a { + color: var(--page-link-color); + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: var(--page-visited-link-color); +} + +a:hover { + text-decoration: none; + background: linear-gradient(to bottom, transparent 0,transparent calc(100% - 1px), currentColor 100%); +} + +a:hover > span.arrow { + text-decoration: none; + background : var(--nav-background-color); +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited, a.line, a.line:visited { + color: var(--code-link-color); +} + +a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited { + color: var(--code-external-link-color); +} + +a.code.hl_class { /* style for links to class names in code snippets */ } +a.code.hl_struct { /* style for links to struct names in code snippets */ } +a.code.hl_union { /* style for links to union names in code snippets */ } +a.code.hl_interface { /* style for links to interface names in code snippets */ } +a.code.hl_protocol { /* style for links to protocol names in code snippets */ } +a.code.hl_category { /* style for links to category names in code snippets */ } +a.code.hl_exception { /* style for links to exception names in code snippets */ } +a.code.hl_service { /* style for links to service names in code snippets */ } +a.code.hl_singleton { /* style for links to singleton names in code snippets */ } +a.code.hl_concept { /* style for links to concept names in code snippets */ } +a.code.hl_namespace { /* style for links to namespace names in code snippets */ } +a.code.hl_package { /* style for links to package names in code snippets */ } +a.code.hl_define { /* style for links to macro names in code snippets */ } +a.code.hl_function { /* style for links to function names in code snippets */ } +a.code.hl_variable { /* style for links to variable names in code snippets */ } +a.code.hl_typedef { /* style for links to typedef names in code snippets */ } +a.code.hl_enumvalue { /* style for links to enum value names in code snippets */ } +a.code.hl_enumeration { /* style for links to enumeration names in code snippets */ } +a.code.hl_signal { /* style for links to Qt signal names in code snippets */ } +a.code.hl_slot { /* style for links to Qt slot names in code snippets */ } +a.code.hl_friend { /* style for links to friend names in code snippets */ } +a.code.hl_dcop { /* style for links to KDE3 DCOP names in code snippets */ } +a.code.hl_property { /* style for links to property names in code snippets */ } +a.code.hl_event { /* style for links to event names in code snippets */ } +a.code.hl_sequence { /* style for links to sequence names in code snippets */ } +a.code.hl_dictionary { /* style for links to dictionary names in code snippets */ } + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +ul.check { + list-style:none; + text-indent: -16px; + padding-left: 38px; +} +li.unchecked:before { + content: "\2610\A0"; +} +li.checked:before { + content: "\2611\A0"; +} + +ol { + text-indent: 0px; +} + +ul { + text-indent: 0px; + overflow: visible; +} + +ul.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; + column-count: 3; + list-style-type: none; +} + +#side-nav ul { + overflow: visible; /* reset ul rule for scroll bar in GENERATE_TREEVIEW window */ +} + +#main-nav ul { + overflow: visible; /* reset ul rule for the navigation bar drop down lists */ +} + +.fragment { + text-align: left; + direction: ltr; + overflow-x: auto; + overflow-y: hidden; + position: relative; + min-height: 12px; + margin: 10px 0px; + padding: 10px 10px; + border: 1px solid var(--fragment-border-color); + border-radius: 4px; + background-color: var(--fragment-background-color); + color: var(--fragment-foreground-color); +} + +pre.fragment { + word-wrap: break-word; + font-size: 10pt; + line-height: 125%; + font-family: var(--font-family-monospace); +} + +.clipboard { + width: 24px; + height: 24px; + right: 5px; + top: 5px; + opacity: 0; + position: absolute; + display: inline; + overflow: auto; + fill: var(--fragment-foreground-color); + justify-content: center; + align-items: center; + cursor: pointer; +} + +.clipboard.success { + border: 1px solid var(--fragment-foreground-color); + border-radius: 4px; +} + +.fragment:hover .clipboard, .clipboard.success { + opacity: .28; +} + +.clipboard:hover, .clipboard.success { + opacity: 1 !important; +} + +.clipboard:active:not([class~=success]) svg { + transform: scale(.91); +} + +.clipboard.success svg { + fill: var(--fragment-copy-ok-color); +} + +.clipboard.success { + border-color: var(--fragment-copy-ok-color); +} + +div.line { + font-family: var(--font-family-monospace); + font-size: 13px; + min-height: 13px; + line-height: 1.2; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +div.line:after { + content:"\000A"; + white-space: pre; +} + +div.line.glow { + background-color: var(--glow-color); + box-shadow: 0 0 10px var(--glow-color); +} + +span.fold { + margin-left: 5px; + margin-right: 1px; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; + display: inline-block; + width: 12px; + height: 12px; + background-repeat:no-repeat; + background-position:center; +} + +span.lineno { + padding-right: 4px; + margin-right: 9px; + text-align: right; + border-right: 2px solid var(--fragment-lineno-border-color); + color: var(--fragment-lineno-foreground-color); + background-color: var(--fragment-lineno-background-color); + white-space: pre; +} +span.lineno a, span.lineno a:visited { + color: var(--fragment-lineno-link-fg-color); + background-color: var(--fragment-lineno-link-bg-color); +} + +span.lineno a:hover { + color: var(--fragment-lineno-link-hover-fg-color); + background-color: var(--fragment-lineno-link-hover-bg-color); +} + +.lineno { + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +div.classindex ul { + list-style: none; + padding-left: 0; +} + +div.classindex span.ai { + display: inline-block; +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + color: var(--page-foreground-color); + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +p.formulaDsp { + text-align: center; +} + +img.dark-mode-visible { + display: none; +} +img.light-mode-visible { + display: none; +} + +img.formulaInl, img.inline { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; + width: var(--footer-logo-width); +} + +.compoundTemplParams { + color: var(--memdecl-template-color); + font-size: 80%; + line-height: 120%; +} + +/* @group Code Colorization */ + +span.keyword { + color: var(--code-keyword-color); +} + +span.keywordtype { + color: var(--code-type-keyword-color); +} + +span.keywordflow { + color: var(--code-flow-keyword-color); +} + +span.comment { + color: var(--code-comment-color); +} + +span.preprocessor { + color: var(--code-preprocessor-color); +} + +span.stringliteral { + color: var(--code-string-literal-color); +} + +span.charliteral { + color: var(--code-char-literal-color); +} + +span.xmlcdata { + color: var(--code-xml-cdata-color); +} + +span.vhdldigit { + color: var(--code-vhdl-digit-color); +} + +span.vhdlchar { + color: var(--code-vhdl-char-color); +} + +span.vhdlkeyword { + color: var(--code-vhdl-keyword-color); +} + +span.vhdllogic { + color: var(--code-vhdl-logic-color); +} + +blockquote { + background-color: var(--blockquote-background-color); + border-left: 2px solid var(--blockquote-border-color); + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid var(--table-cell-border-color); +} + +th.dirtab { + background-color: var(--table-header-background-color); + color: var(--table-header-foreground-color); + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid var(--separator-color); +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: var(--glow-color); + box-shadow: 0 0 15px var(--glow-color); +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: var(--memdecl-background-color); + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: var(--memdecl-foreground-color); +} + +.memSeparator { + border-bottom: 1px solid var(--memdecl-separator-color); + line-height: 1px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight, .memTemplItemRight { + width: 100%; +} + +.memTemplParams { + color: var(--memdecl-template-color); + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtitle { + padding: 8px; + border-top: 1px solid var(--memdef-border-color); + border-left: 1px solid var(--memdef-border-color); + border-right: 1px solid var(--memdef-border-color); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + margin-bottom: -1px; + background-image: var(--memdef-title-gradient-image); + background-repeat: repeat-x; + background-color: var(--memdef-title-background-color); + line-height: 1.25; + font-weight: 300; + float:left; +} + +.permalink +{ + font-size: 65%; + display: inline-block; + vertical-align: middle; +} + +.memtemplate { + font-size: 80%; + color: var(--memdef-template-color); + font-weight: normal; + margin-left: 9px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px var(--glow-color); +} + +.memname { + font-weight: 400; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid var(--memdef-border-color); + border-left: 1px solid var(--memdef-border-color); + border-right: 1px solid var(--memdef-border-color); + padding: 6px 0px 6px 0px; + color: var(--memdef-proto-text-color); + font-weight: bold; + text-shadow: var(--memdef-proto-text-shadow); + background-color: var(--memdef-proto-background-color); + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; +} + +.overload { + font-family: var(--font-family-monospace); + font-size: 65%; +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid var(--memdef-border-color); + border-left: 1px solid var(--memdef-border-color); + border-right: 1px solid var(--memdef-border-color); + padding: 6px 10px 2px 10px; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: var(--memdef-doc-background-color); + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; + padding: 0px; + padding-bottom: 1px; +} + +.paramname { + white-space: nowrap; + padding: 0px; + padding-bottom: 1px; + margin-left: 2px; +} + +.paramname em { + color: var(--memdef-param-name-color); + font-style: normal; + margin-right: 1px; +} + +.paramname .paramdefval { + font-family: var(--font-family-monospace); +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname, .tparams .paramname, .exception .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype, .tparams .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir, .tparams .paramdir { + font-family: var(--font-family-monospace); + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: var(--label-background-color); + border-top:1px solid var(--label-left-top-border-color); + border-left:1px solid var(--label-left-top-border-color); + border-right:1px solid var(--label-right-bottom-border-color); + border-bottom:1px solid var(--label-right-bottom-border-color); + text-shadow: none; + color: var(--label-foreground-color); + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view inside a (index) page */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid var(--directory-separator-color); + border-bottom: 1px solid var(--directory-separator-color); + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.odd { + padding-left: 6px; + background-color: var(--index-odd-item-bg-color); +} + +.directory tr.even { + padding-left: 6px; + background-color: var(--index-even-item-bg-color); +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: var(--page-link-color); +} + +.arrow { + color: var(--nav-arrow-color); + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; + cursor: pointer; + font-size: 80%; + display: inline-block; + width: 16px; + height: 22px; +} + +.icon { + font-family: var(--font-family-icon); + line-height: normal; + font-weight: bold; + font-size: 12px; + height: 14px; + width: 16px; + display: inline-block; + background-color: var(--icon-background-color); + color: var(--icon-foreground-color); + text-align: center; + border-radius: 4px; + margin-left: 2px; + margin-right: 2px; +} + +.icona { + width: 24px; + height: 22px; + display: inline-block; +} + +.iconfopen { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:var(--icon-folder-open-image); + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.iconfclosed { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:var(--icon-folder-closed-image); + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.icondoc { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:var(--icon-doc-image); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: var(--footer-foreground-color); +} + +table.doxtable caption { + caption-side: top; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid var(--table-cell-border-color); + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: var(--table-header-background-color); + color: var(--table-header-foreground-color); + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + margin-bottom: 10px; + border: 1px solid var(--memdef-border-color); + border-spacing: 0px; + border-radius: 4px; + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname, .fieldtable td.fieldinit { + white-space: nowrap; + border-right: 1px solid var(--memdef-border-color); + border-bottom: 1px solid var(--memdef-border-color); + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fieldinit { + padding-top: 3px; + text-align: right; +} + + +.fieldtable td.fielddoc { + border-bottom: 1px solid var(--memdef-border-color); +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image: var(--memdef-title-gradient-image); + background-repeat:repeat-x; + background-color: var(--memdef-title-background-color); + font-size: 90%; + color: var(--memdef-proto-text-color); + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + font-weight: 400; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid var(--memdef-border-color); +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: var(--nav-gradient-image); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image: var(--nav-gradient-image); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:var(--nav-text-normal-color); + border:solid 1px var(--nav-breadcrumb-border-color); + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:var(--nav-breadcrumb-image); + background-repeat:no-repeat; + background-position:right; + color: var(--nav-foreground-color); +} + +.navpath li.navelem a +{ + height:32px; + display:block; + outline: none; + color: var(--nav-text-normal-color); + font-family: var(--font-family-nav); + text-shadow: var(--nav-text-normal-shadow); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color: var(--nav-text-hover-color); + text-shadow: var(--nav-text-hover-shadow); +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color: var(--footer-foreground-color); + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +table.classindex +{ + margin: 10px; + white-space: nowrap; + margin-left: 3%; + margin-right: 3%; + width: 94%; + border: 0; + border-spacing: 0; + padding: 0; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image: var(--header-gradient-image); + background-repeat:repeat-x; + background-color: var(--header-background-color); + margin: 0px; + border-bottom: 1px solid var(--header-separator-color); +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +.PageDocRTL-title div.headertitle { + text-align: right; + direction: rtl; +} + +dl { + padding: 0 0 0 0; +} + +/* + +dl.section { + margin-left: 0px; + padding-left: 0px; +} + +dl.note { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention, dl.important { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #00D000; +} + +dl.deprecated { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #505050; +} + +dl.todo { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #00C0E0; +} + +dl.test { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #3030E0; +} + +dl.bug { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #C08050; +} + +*/ + +dl.bug dt a, dl.deprecated dt a, dl.todo dt a, dl.test a { + font-weight: bold !important; +} + +dl.warning, dl.attention, dl.important, dl.note, dl.deprecated, dl.bug, +dl.invariant, dl.pre, dl.post, dl.todo, dl.test, dl.remark { + padding: 10px; + margin: 10px 0px; + overflow: hidden; + margin-left: 0; + border-radius: 4px; +} + +dl.section dd { + margin-bottom: 2px; +} + +dl.warning, dl.attention, dl.important { + background: var(--warning-color-bg); + border-left: 8px solid var(--warning-color-hl); + color: var(--warning-color-text); +} + +dl.warning dt, dl.attention dt, dl.important dt { + color: var(--warning-color-hl); +} + +dl.note, dl.remark { + background: var(--note-color-bg); + border-left: 8px solid var(--note-color-hl); + color: var(--note-color-text); +} + +dl.note dt, dl.remark dt { + color: var(--note-color-hl); +} + +dl.todo { + background: var(--todo-color-bg); + border-left: 8px solid var(--todo-color-hl); + color: var(--todo-color-text); +} + +dl.todo dt { + color: var(--todo-color-hl); +} + +dl.test { + background: var(--test-color-bg); + border-left: 8px solid var(--test-color-hl); + color: var(--test-color-text); +} + +dl.test dt { + color: var(--test-color-hl); +} + +dl.bug dt a { + color: var(--bug-color-hl) !important; +} + +dl.bug { + background: var(--bug-color-bg); + border-left: 8px solid var(--bug-color-hl); + color: var(--bug-color-text); +} + +dl.bug dt a { + color: var(--bug-color-hl) !important; +} + +dl.deprecated { + background: var(--deprecated-color-bg); + border-left: 8px solid var(--deprecated-color-hl); + color: var(--deprecated-color-text); +} + +dl.deprecated dt a { + color: var(--deprecated-color-hl) !important; +} + +dl.note dd, dl.warning dd, dl.pre dd, dl.post dd, +dl.remark dd, dl.attention dd, dl.important dd, dl.invariant dd, +dl.bug dd, dl.deprecated dd, dl.todo dd, dl.test dd { + margin-inline-start: 0px; +} + +dl.invariant, dl.pre, dl.post { + background: var(--invariant-color-bg); + border-left: 8px solid var(--invariant-color-hl); + color: var(--invariant-color-text); +} + +dl.invariant dt, dl.pre dt, dl.post dt { + color: var(--invariant-color-hl); +} + + +#projectrow +{ + height: 56px; +} + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectalign +{ + vertical-align: middle; + padding-left: 0.5em; +} + +#projectname +{ + font-size: 200%; + font-family: var(--font-family-title); + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font-size: 90%; + font-family: var(--font-family-title); + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font-size: 50%; + font-family: 50% var(--font-family-title); + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid var(--title-separator-color); + background-color: var(--title-background-color); +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.plantumlgraph +{ + text-align: center; +} + +.diagraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:var(--citation-label-color); + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; + text-align:right; + width:52px; +} + +dl.citelist dd { + margin:2px 0 2px 72px; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: var(--toc-background-color); + border: 1px solid var(--toc-border-color); + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 8px 10px 10px; + width: 200px; +} + +div.toc li { + background: var(--toc-down-arrow-image) no-repeat scroll 0 5px transparent; + font: 10px/1.2 var(--font-family-toc); + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 var(--font-family-toc); + color: var(--toc-header-color); + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li[class^='level'] { + margin-left: 15px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.empty { + background-image: none; + margin-top: 0px; +} + +span.emoji { + /* font family used at the site: https://unicode.org/emoji/charts/full-emoji-list.html + * font-family: "Noto Color Emoji", "Apple Color Emoji", "Segoe UI Emoji", Times, Symbola, Aegyptus, Code2000, Code2001, Code2002, Musica, serif, LastResort; + */ +} + +span.obfuscator { + display: none; +} + +.inherit_header { + font-weight: bold; + color: var(--inherit-header-color); + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +/* tooltip related style info */ + +.ttc { + position: absolute; + display: none; +} + +#powerTip { + cursor: default; + /*white-space: nowrap;*/ + color: var(--tooltip-foreground-color); + background-color: var(--tooltip-background-color); + border: 1px solid var(--tooltip-border-color); + border-radius: 4px 4px 4px 4px; + box-shadow: var(--tooltip-shadow); + display: none; + font-size: smaller; + max-width: 80%; + opacity: 0.9; + padding: 1ex 1em 1em; + position: absolute; + z-index: 2147483647; +} + +#powerTip div.ttdoc { + color: var(--tooltip-doc-color); + font-style: italic; +} + +#powerTip div.ttname a { + font-weight: bold; +} + +#powerTip a { + color: var(--tooltip-link-color); +} + +#powerTip div.ttname { + font-weight: bold; +} + +#powerTip div.ttdeci { + color: var(--tooltip-declaration-color); +} + +#powerTip div { + margin: 0px; + padding: 0px; + font-size: 12px; + font-family: var(--font-family-tooltip); + line-height: 16px; +} + +#powerTip:before, #powerTip:after { + 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sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file + */ + +function toggleVisibility(linkObj) { + return dynsection.toggleVisibility(linkObj); +} + +let dynsection = { + + // helper function + updateStripes : function() { + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); + $('table.directory tr'). + removeClass('odd').filter(':visible:odd').addClass('odd'); + }, + + toggleVisibility : function(linkObj) { + const base = $(linkObj).attr('id'); + const summary = $('#'+base+'-summary'); + const content = $('#'+base+'-content'); + const trigger = $('#'+base+'-trigger'); + const src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; + }, + + toggleLevel : function(level) { + $('table.directory tr').each(function() { + const l = this.id.split('_').length-1; + const i = $('#img'+this.id.substring(3)); + const a = $('#arr'+this.id.substring(3)); + if (l<level+1) { + i.removeClass('iconfopen iconfclosed').addClass('iconfopen'); + a.html('&#9660;'); + $(this).show(); + } else if (l==level+1) { + i.removeClass('iconfclosed iconfopen').addClass('iconfclosed'); + a.html('&#9658;'); + $(this).show(); + } else { + $(this).hide(); + } + }); + this.updateStripes(); + }, + + toggleFolder : function(id) { + // the clicked row + const currentRow = $('#row_'+id); + + // all rows after the clicked row + const rows = currentRow.nextAll("tr"); + + const re = new RegExp('^row_'+id+'\\d+_$', "i"); //only one sub + + // only match elements AFTER this one (can't hide elements before) + const childRows = rows.filter(function() { return this.id.match(re); }); + + // first row is visible we are HIDING + if (childRows.filter(':first').is(':visible')===true) { + // replace down arrow by right arrow for current row + const currentRowSpans = currentRow.find("span"); + currentRowSpans.filter(".iconfopen").removeClass("iconfopen").addClass("iconfclosed"); + currentRowSpans.filter(".arrow").html('&#9658;'); + rows.filter("[id^=row_"+id+"]").hide(); // hide all children + } else { // we are SHOWING + // replace right arrow by down arrow for current row + const currentRowSpans = currentRow.find("span"); + currentRowSpans.filter(".iconfclosed").removeClass("iconfclosed").addClass("iconfopen"); + currentRowSpans.filter(".arrow").html('&#9660;'); + // replace down arrows by right arrows for child rows + const childRowsSpans = childRows.find("span"); + childRowsSpans.filter(".iconfopen").removeClass("iconfopen").addClass("iconfclosed"); + childRowsSpans.filter(".arrow").html('&#9658;'); + childRows.show(); //show all children + } + this.updateStripes(); + }, + + toggleInherit : function(id) { + const rows = $('tr.inherit.'+id); + const img = $('tr.inherit_header.'+id+' img'); + const src = $(img).attr('src'); + if (rows.filter(':first').is(':visible')===true) { + rows.css('display','none'); + $(img).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + rows.css('display','table-row'); // using show() causes jump in firefox + $(img).attr('src',src.substring(0,src.length-10)+'open.png'); + } + }, +}; + +let codefold = { + opened : true, + + // in case HTML_COLORSTYLE is LIGHT or DARK the vars will be replaced, so we write them out explicitly and use double quotes + plusImg: [ "var(--fold-plus-image)", "var(--fold-plus-image-relpath)" ], + minusImg: [ "var(--fold-minus-image)", "var(--fold-minus-image-relpath)" ], + + // toggle all folding blocks + toggle_all : function(relPath) { + if (this.opened) { + $('#fold_all').css('background-image',this.plusImg[relPath]); + $('div[id^=foldopen]').hide(); + $('div[id^=foldclosed]').show(); + } else { + $('#fold_all').css('background-image',this.minusImg[relPath]); + $('div[id^=foldopen]').show(); + $('div[id^=foldclosed]').hide(); + } + this.opened=!this.opened; + }, + + // toggle single folding block + toggle : function(id) { + $('#foldopen'+id).toggle(); + $('#foldclosed'+id).toggle(); + }, + + init : function(relPath) { + $('span[class=lineno]').css({ + 'padding-right':'4px', + 'margin-right':'2px', + 'display':'inline-block', + 'width':'54px', + 'background':'linear-gradient(var(--fold-line-color),var(--fold-line-color)) no-repeat 46px/2px 100%' + }); + // add global toggle to first line + $('span[class=lineno]:first').append('<span class="fold" id="fold_all" '+ + 'onclick="javascript:codefold.toggle_all('+relPath+');" '+ + 'style="background-image:'+this.minusImg[relPath]+';"></span>'); + // add vertical lines to other rows + $('span[class=lineno]').not(':eq(0)').append('<span class="fold"></span>'); + // add toggle controls to lines with fold divs + $('div[class=foldopen]').each(function() { + // extract specific id to use + const id = $(this).attr('id').replace('foldopen',''); + // extract start and end foldable fragment attributes + const start = $(this).attr('data-start'); + const end = $(this).attr('data-end'); + // replace normal fold span with controls for the first line of a foldable fragment + $(this).find('span[class=fold]:first').replaceWith('<span class="fold" '+ + 'onclick="javascript:codefold.toggle(\''+id+'\');" '+ + 'style="background-image:'+codefold.minusImg[relPath]+';"></span>'); + // append div for folded (closed) representation + $(this).after('<div id="foldclosed'+id+'" class="foldclosed" style="display:none;"></div>'); + // extract the first line from the "open" section to represent closed content + const line = $(this).children().first().clone(); + // remove any glow that might still be active on the original line + $(line).removeClass('glow'); + if (start) { + // if line already ends with a start marker (e.g. trailing {), remove it + $(line).html($(line).html().replace(new RegExp('\\s*'+start+'\\s*$','g'),'')); + } + // replace minus with plus symbol + $(line).find('span[class=fold]').css('background-image',codefold.plusImg[relPath]); + // append ellipsis + $(line).append(' '+start+'<a href="javascript:codefold.toggle(\''+id+'\')">&#8230;</a>'+end); + // insert constructed line into closed div + $('#foldclosed'+id).html(line); + }); + }, +}; +/* @license-end */ diff --git a/sw/files.html b/sw/files.html new file mode 100644 index 000000000..91ae085fa --- /dev/null +++ b/sw/files.html @@ -0,0 +1,228 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: File List</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="header"> + <div class="headertitle"><div class="title">File List</div></div> +</div><!--header--> +<div class="contents"> +<div class="textblock">Here is a list of all documented files with brief descriptions:</div><div class="directory"> +<div class="levels">[detail level <span onclick="javascript:dynsection.toggleLevel(1);">1</span><span onclick="javascript:dynsection.toggleLevel(2);">2</span><span onclick="javascript:dynsection.toggleLevel(3);">3</span><span onclick="javascript:dynsection.toggleLevel(4);">4</span><span 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a/sw/float__corner__test_2main_8c.html b/sw/float__corner__test_2main_8c.html new file mode 100644 index 000000000..9cdd9af4b --- /dev/null +++ b/sw/float__corner__test_2main_8c.html @@ -0,0 +1,448 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/float_corner_test/main.c File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link 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</ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Verification program for the NEORV32 'Zfinx' extension (floating-point in x registers) using pseudo-random data as input; compares results from hardware against pure-sw reference functions. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;float.h&gt;</code><br /> +<code>#include &lt;math.h&gt;</code><br /> +<code>#include &quot;neorv32_zfinx_extension_intrinsics.h&quot;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div 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href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Verification program for the NEORV32 'Zfinx' extension (floating-point in x registers) using pseudo-random data as input; compares results from hardware against pure-sw reference functions. </p> +<dl class="section author"><dt>Author</dt><dd>Mikael Mortensen </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;(19200)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a83792c34853f1d2801b59ad46adc7e1e" name="a83792c34853f1d2801b59ad46adc7e1e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a83792c34853f1d2801b59ad46adc7e1e">&#9670;&#160;</a></span>NUM_TEST_CASES</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NUM_TEST_CASES&#160;&#160;&#160;(1000000)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a2d16b9e484b7af7897c7ae83f945ceca" name="a2d16b9e484b7af7897c7ae83f945ceca"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2d16b9e484b7af7897c7ae83f945ceca">&#9670;&#160;</a></span>RUN_ADDSUB_TESTS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define RUN_ADDSUB_TESTS&#160;&#160;&#160;(1)</td> + </tr> + </table> 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alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ 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+</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_23212395b5ee0866d2fdd629e0ddeae8.html">float_corner_test</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_zfinx_extension_intrinsics.h</div></div> +</div><!--header--> +<div class="contents"> +<div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// #################################################################################################</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// # &lt;&lt; NEORV32 - Intrinsics + Emulation Functions for the RISC-V &quot;Zfinx&quot; CPU extension &gt;&gt; #</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// # ********************************************************************************************* #</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// # The intrinsics provided by this library allow to use the hardware floating-point unit of the #</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// # RISC-V Zfinx CPU extension without the need for Zfinx support by the compiler / toolchain. #</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// # ********************************************************************************************* #</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// # BSD 3-Clause License #</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="comment">// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #</span></div> +<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="comment">// # Redistribution and use in source and binary forms, with or without modification, are #</span></div> +<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="comment">// # permitted provided that the following conditions are met: #</span></div> +<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span><span class="comment">// # 1. Redistributions of source code must retain the above copyright notice, this list of #</span></div> +<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="comment">// # conditions and the following disclaimer. #</span></div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="comment">// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="comment">// # conditions and the following disclaimer in the documentation and/or other materials #</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="comment">// # provided with the distribution. #</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="comment">// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">// # endorse or promote products derived from this software without specific prior written #</span></div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span><span class="comment">// # permission. #</span></div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span><span class="comment">// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS &quot;AS IS&quot; AND ANY EXPRESS #</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span><span class="comment">// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #</span></div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span><span class="comment">// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #</span></div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span><span class="comment">// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #</span></div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span><span class="comment">// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #</span></div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span><span class="comment">// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #</span></div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span><span class="comment">// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #</span></div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span><span class="comment">// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #</span></div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span><span class="comment">// # OF THE POSSIBILITY OF SUCH DAMAGE. #</span></div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span><span class="comment">// # ********************************************************************************************* #</span></div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span><span class="comment">// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span><span class="comment">// #################################################################################################</span></div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> </div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> </div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="preprocessor">#ifndef neorv32_zfinx_extension_intrinsics_h</span></div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="preprocessor">#define neorv32_zfinx_extension_intrinsics_h</span></div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span><span class="preprocessor">#define __USE_GNU</span></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="preprocessor">#include &lt;fenv.h&gt;</span></div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="comment">//#pragma STDC FENV_ACCESS ON</span></div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="preprocessor">#define _GNU_SOURCE</span></div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span> </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span><span class="preprocessor">#include &lt;float.h&gt;</span></div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span><span class="preprocessor">#include &lt;math.h&gt;</span></div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span> </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span> </div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="preprocessor">#if defined __riscv_f || (__riscv_flen == 32)</span></div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span><span class="preprocessor"> #error Application programs using the Zfinx intrinsic library have to be compiled WITHOUT the &lt;F&gt; MARCH ISA attribute!</span></div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span> </div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span> </div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00077" data-start="{" data-end="};"> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"><a class="line" href="unionfloat__conv__t.html"> 77</a></span><span class="keyword">typedef</span> <span class="keyword">union</span></div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span>{</div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"><a class="line" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606"> 79</a></span> uint32_t <a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>; </div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"><a class="line" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788"> 80</a></span> <span class="keywordtype">float</span> <a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>; </div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span>} <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a>;</div> +</div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span> </div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span> </div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span><span class="comment">// Helper functions</span></div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span> </div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span><span class="keywordtype">float</span> subnormal_flush(<span class="keywordtype">float</span> tmp) {</div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> </div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> <span class="keywordtype">float</span> res = tmp;</div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span> </div> +<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span> <span class="comment">// flush to zero if subnormal</span></div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span> <span class="keywordflow">if</span> (fpclassify(tmp) == FP_SUBNORMAL) {</div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span> <span class="keywordflow">if</span> (signbit(tmp) != 0) {</div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span> res = -0.0f;</div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span> }</div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span> res = +0.0f;</div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span> }</div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span> }</div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span> </div> +<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span>}</div> +<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span> </div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span> </div> +<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span><span class="comment">// Exception access</span></div> +<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span> </div> +<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span>uint32_t get_hw_exceptions(<span class="keywordtype">void</span>) {</div> +<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span> </div> +<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span> uint32_t res = <a class="code hl_function" href="neorv32__cpu_8h.html#aab7a9f9cf608599f2b124dd499cb8418">neorv32_cpu_csr_read</a>(<a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a">CSR_FFLAGS</a>);</div> +<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span> </div> +<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"> 127</span> <a class="code hl_function" href="neorv32__cpu_8h.html#afb5ef6e0b1a3e26570edfd8379490455">neorv32_cpu_csr_write</a>(<a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a">CSR_FFLAGS</a>, 0); <span class="comment">// clear status word</span></div> +<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"> 128</span> </div> +<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span>}</div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span> </div> +<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span> </div> +<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span>uint32_t get_sw_exceptions(<span class="keywordtype">void</span>) {</div> +<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span> </div> +<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span> <span class="keyword">const</span> uint32_t FP_EXC_NV_C = 1 &lt;&lt; 0; <span class="comment">// invalid operation</span></div> +<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"> 143</span> <span class="keyword">const</span> uint32_t FP_EXC_DZ_C = 1 &lt;&lt; 1; <span class="comment">// divide by zero</span></div> +<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span> <span class="keyword">const</span> uint32_t FP_EXC_OF_C = 1 &lt;&lt; 2; <span class="comment">// overflow</span></div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span> <span class="keyword">const</span> uint32_t FP_EXC_UF_C = 1 &lt;&lt; 3; <span class="comment">// underflow</span></div> +<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span> <span class="keyword">const</span> uint32_t FP_EXC_NX_C = 1 &lt;&lt; 4; <span class="comment">// inexact</span></div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span> </div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span> <span class="keywordtype">int</span> fpeRaised = fetestexcept(FE_ALL_EXCEPT);</div> +<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span> </div> +<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span> uint32_t res = 0;</div> +<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span> </div> +<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span> <span class="keywordflow">if</span> (fpeRaised &amp; FE_INVALID) { res |= FP_EXC_NV_C; }</div> +<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span> <span class="keywordflow">if</span> (fpeRaised &amp; FE_DIVBYZERO) { res |= FP_EXC_DZ_C; }</div> +<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"> 154</span> <span class="keywordflow">if</span> (fpeRaised &amp; FE_OVERFLOW) { res |= FP_EXC_OF_C; }</div> +<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span> <span class="keywordflow">if</span> (fpeRaised &amp; FE_UNDERFLOW) { res |= FP_EXC_UF_C; }</div> +<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span> <span class="keywordflow">if</span> (fpeRaised &amp; FE_INEXACT) { res |= FP_EXC_NX_C; }</div> +<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span> </div> +<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"> 158</span> feclearexcept(FE_ALL_EXCEPT);</div> +<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"> 159</span> </div> +<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span>}</div> +<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span> </div> +<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"> 163</span> </div> +<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span><span class="comment">// &quot;Intrinsics&quot;</span></div> +<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"> 166</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span> </div> +<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span> </div> +<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span> </div> +<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0000000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"> 182</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"> 183</span>}</div> +<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"> 184</span> </div> +<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"> 185</span> </div> +<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"> 186</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span> </div> +<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span> </div> +<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0000100, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"> 200</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"> 201</span>}</div> +<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span> </div> +<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span> </div> +<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"> 204</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"> 211</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmuls(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"> 212</span> </div> +<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"> 213</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"> 214</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"> 215</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"> 216</span> </div> +<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"> 217</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0001000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"> 219</span>}</div> +<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"> 220</span> </div> +<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"> 221</span> </div> +<div class="line"><a id="l00222" name="l00222"></a><span class="lineno"> 222</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmins(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span> </div> +<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00234" name="l00234"></a><span class="lineno"> 234</span> </div> +<div class="line"><a id="l00235" name="l00235"></a><span class="lineno"> 235</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010100, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"> 236</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00237" name="l00237"></a><span class="lineno"> 237</span>}</div> +<div class="line"><a id="l00238" name="l00238"></a><span class="lineno"> 238</span> </div> +<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"> 239</span> </div> +<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"> 240</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00247" name="l00247"></a><span class="lineno"> 247</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmaxs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00248" name="l00248"></a><span class="lineno"> 248</span> </div> +<div class="line"><a id="l00249" name="l00249"></a><span class="lineno"> 249</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00250" name="l00250"></a><span class="lineno"> 250</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00251" name="l00251"></a><span class="lineno"> 251</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00252" name="l00252"></a><span class="lineno"> 252</span> </div> +<div class="line"><a id="l00253" name="l00253"></a><span class="lineno"> 253</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010100, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b001, 0b1010011);</div> +<div class="line"><a id="l00254" name="l00254"></a><span class="lineno"> 254</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00255" name="l00255"></a><span class="lineno"> 255</span>}</div> +<div class="line"><a id="l00256" name="l00256"></a><span class="lineno"> 256</span> </div> +<div class="line"><a id="l00257" name="l00257"></a><span class="lineno"> 257</span> </div> +<div class="line"><a id="l00258" name="l00258"></a><span class="lineno"> 258</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00264" name="l00264"></a><span class="lineno"> 264</span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_wus(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00265" name="l00265"></a><span class="lineno"> 265</span> </div> +<div class="line"><a id="l00266" name="l00266"></a><span class="lineno"> 266</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa;</div> +<div class="line"><a id="l00267" name="l00267"></a><span class="lineno"> 267</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00268" name="l00268"></a><span class="lineno"> 268</span> </div> +<div class="line"><a id="l00269" name="l00269"></a><span class="lineno"> 269</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R2_TYPE(0b1100000, 0b00001, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00270" name="l00270"></a><span class="lineno"> 270</span>}</div> +<div class="line"><a id="l00271" name="l00271"></a><span class="lineno"> 271</span> </div> +<div class="line"><a id="l00272" name="l00272"></a><span class="lineno"> 272</span> </div> +<div class="line"><a id="l00273" name="l00273"></a><span class="lineno"> 273</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00279" name="l00279"></a><span class="lineno"> 279</span><span class="keyword">inline</span> int32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_ws(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00280" name="l00280"></a><span class="lineno"> 280</span> </div> +<div class="line"><a id="l00281" name="l00281"></a><span class="lineno"> 281</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa;</div> +<div class="line"><a id="l00282" name="l00282"></a><span class="lineno"> 282</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00283" name="l00283"></a><span class="lineno"> 283</span> </div> +<div class="line"><a id="l00284" name="l00284"></a><span class="lineno"> 284</span> <span class="keywordflow">return</span> (int32_t)CUSTOM_INSTR_R2_TYPE(0b1100000, 0b00000, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00285" name="l00285"></a><span class="lineno"> 285</span>}</div> +<div class="line"><a id="l00286" name="l00286"></a><span class="lineno"> 286</span> </div> +<div class="line"><a id="l00287" name="l00287"></a><span class="lineno"> 287</span> </div> +<div class="line"><a id="l00288" name="l00288"></a><span class="lineno"> 288</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00294" name="l00294"></a><span class="lineno"> 294</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fcvt_swu(uint32_t rs1) {</div> +<div class="line"><a id="l00295" name="l00295"></a><span class="lineno"> 295</span> </div> +<div class="line"><a id="l00296" name="l00296"></a><span class="lineno"> 296</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> res;</div> +<div class="line"><a id="l00297" name="l00297"></a><span class="lineno"> 297</span> </div> +<div class="line"><a id="l00298" name="l00298"></a><span class="lineno"> 298</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R2_TYPE(0b1101000, 0b00001, rs1, 0b000, 0b1010011);</div> +<div class="line"><a id="l00299" name="l00299"></a><span class="lineno"> 299</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00300" name="l00300"></a><span class="lineno"> 300</span>}</div> +<div class="line"><a id="l00301" name="l00301"></a><span class="lineno"> 301</span> </div> +<div class="line"><a id="l00302" name="l00302"></a><span class="lineno"> 302</span> </div> +<div class="line"><a id="l00303" name="l00303"></a><span class="lineno"> 303</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00309" name="l00309"></a><span class="lineno"> 309</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fcvt_sw(int32_t rs1) {</div> +<div class="line"><a id="l00310" name="l00310"></a><span class="lineno"> 310</span> </div> +<div class="line"><a id="l00311" name="l00311"></a><span class="lineno"> 311</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> res;</div> +<div class="line"><a id="l00312" name="l00312"></a><span class="lineno"> 312</span> </div> +<div class="line"><a id="l00313" name="l00313"></a><span class="lineno"> 313</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R2_TYPE(0b1101000, 0b00000, rs1, 0b000, 0b1010011);</div> +<div class="line"><a id="l00314" name="l00314"></a><span class="lineno"> 314</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00315" name="l00315"></a><span class="lineno"> 315</span>}</div> +<div class="line"><a id="l00316" name="l00316"></a><span class="lineno"> 316</span> </div> +<div class="line"><a id="l00317" name="l00317"></a><span class="lineno"> 317</span> </div> +<div class="line"><a id="l00318" name="l00318"></a><span class="lineno"> 318</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00325" name="l00325"></a><span class="lineno"> 325</span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_feqs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00326" name="l00326"></a><span class="lineno"> 326</span> </div> +<div class="line"><a id="l00327" name="l00327"></a><span class="lineno"> 327</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb;</div> +<div class="line"><a id="l00328" name="l00328"></a><span class="lineno"> 328</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00329" name="l00329"></a><span class="lineno"> 329</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00330" name="l00330"></a><span class="lineno"> 330</span> </div> +<div class="line"><a id="l00331" name="l00331"></a><span class="lineno"> 331</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R3_TYPE(0b1010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b010, 0b1010011);</div> +<div class="line"><a id="l00332" name="l00332"></a><span class="lineno"> 332</span>}</div> +<div class="line"><a id="l00333" name="l00333"></a><span class="lineno"> 333</span> </div> +<div class="line"><a id="l00334" name="l00334"></a><span class="lineno"> 334</span> </div> +<div class="line"><a id="l00335" name="l00335"></a><span class="lineno"> 335</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00342" name="l00342"></a><span class="lineno"> 342</span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_flts(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00343" name="l00343"></a><span class="lineno"> 343</span> </div> +<div class="line"><a id="l00344" name="l00344"></a><span class="lineno"> 344</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb;</div> +<div class="line"><a id="l00345" name="l00345"></a><span class="lineno"> 345</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00346" name="l00346"></a><span class="lineno"> 346</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00347" name="l00347"></a><span class="lineno"> 347</span> </div> +<div class="line"><a id="l00348" name="l00348"></a><span class="lineno"> 348</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R3_TYPE(0b1010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b001, 0b1010011);</div> +<div class="line"><a id="l00349" name="l00349"></a><span class="lineno"> 349</span>}</div> +<div class="line"><a id="l00350" name="l00350"></a><span class="lineno"> 350</span> </div> +<div class="line"><a id="l00351" name="l00351"></a><span class="lineno"> 351</span> </div> +<div class="line"><a id="l00352" name="l00352"></a><span class="lineno"> 352</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00359" name="l00359"></a><span class="lineno"> 359</span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fles(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00360" name="l00360"></a><span class="lineno"> 360</span> </div> +<div class="line"><a id="l00361" name="l00361"></a><span class="lineno"> 361</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb;</div> +<div class="line"><a id="l00362" name="l00362"></a><span class="lineno"> 362</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00363" name="l00363"></a><span class="lineno"> 363</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00364" name="l00364"></a><span class="lineno"> 364</span> </div> +<div class="line"><a id="l00365" name="l00365"></a><span class="lineno"> 365</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R3_TYPE(0b1010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00366" name="l00366"></a><span class="lineno"> 366</span>}</div> +<div class="line"><a id="l00367" name="l00367"></a><span class="lineno"> 367</span> </div> +<div class="line"><a id="l00368" name="l00368"></a><span class="lineno"> 368</span> </div> +<div class="line"><a id="l00369" name="l00369"></a><span class="lineno"> 369</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00376" name="l00376"></a><span class="lineno"> 376</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsgnjs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00377" name="l00377"></a><span class="lineno"> 377</span> </div> +<div class="line"><a id="l00378" name="l00378"></a><span class="lineno"> 378</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00379" name="l00379"></a><span class="lineno"> 379</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00380" name="l00380"></a><span class="lineno"> 380</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00381" name="l00381"></a><span class="lineno"> 381</span> </div> +<div class="line"><a id="l00382" name="l00382"></a><span class="lineno"> 382</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00383" name="l00383"></a><span class="lineno"> 383</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00384" name="l00384"></a><span class="lineno"> 384</span>}</div> +<div class="line"><a id="l00385" name="l00385"></a><span class="lineno"> 385</span> </div> +<div class="line"><a id="l00386" name="l00386"></a><span class="lineno"> 386</span> </div> +<div class="line"><a id="l00387" name="l00387"></a><span class="lineno"> 387</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00394" name="l00394"></a><span class="lineno"> 394</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsgnjns(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00395" name="l00395"></a><span class="lineno"> 395</span> </div> +<div class="line"><a id="l00396" name="l00396"></a><span class="lineno"> 396</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00397" name="l00397"></a><span class="lineno"> 397</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00398" name="l00398"></a><span class="lineno"> 398</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00399" name="l00399"></a><span class="lineno"> 399</span> </div> +<div class="line"><a id="l00400" name="l00400"></a><span class="lineno"> 400</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b001, 0b1010011);</div> +<div class="line"><a id="l00401" name="l00401"></a><span class="lineno"> 401</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00402" name="l00402"></a><span class="lineno"> 402</span>}</div> +<div class="line"><a id="l00403" name="l00403"></a><span class="lineno"> 403</span> </div> +<div class="line"><a id="l00404" name="l00404"></a><span class="lineno"> 404</span> </div> +<div class="line"><a id="l00405" name="l00405"></a><span class="lineno"> 405</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00412" name="l00412"></a><span class="lineno"> 412</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsgnjxs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00413" name="l00413"></a><span class="lineno"> 413</span> </div> +<div class="line"><a id="l00414" name="l00414"></a><span class="lineno"> 414</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00415" name="l00415"></a><span class="lineno"> 415</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00416" name="l00416"></a><span class="lineno"> 416</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00417" name="l00417"></a><span class="lineno"> 417</span> </div> +<div class="line"><a id="l00418" name="l00418"></a><span class="lineno"> 418</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b010, 0b1010011);</div> +<div class="line"><a id="l00419" name="l00419"></a><span class="lineno"> 419</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00420" name="l00420"></a><span class="lineno"> 420</span>}</div> +<div class="line"><a id="l00421" name="l00421"></a><span class="lineno"> 421</span> </div> +<div class="line"><a id="l00422" name="l00422"></a><span class="lineno"> 422</span> </div> +<div class="line"><a id="l00423" name="l00423"></a><span class="lineno"> 423</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00429" name="l00429"></a><span class="lineno"> 429</span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fclasss(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00430" name="l00430"></a><span class="lineno"> 430</span> </div> +<div class="line"><a id="l00431" name="l00431"></a><span class="lineno"> 431</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa;</div> +<div class="line"><a id="l00432" name="l00432"></a><span class="lineno"> 432</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00433" name="l00433"></a><span class="lineno"> 433</span> </div> +<div class="line"><a id="l00434" name="l00434"></a><span class="lineno"> 434</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R2_TYPE(0b1110000, 0b00000, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b001, 0b1010011);</div> +<div class="line"><a id="l00435" name="l00435"></a><span class="lineno"> 435</span>}</div> +<div class="line"><a id="l00436" name="l00436"></a><span class="lineno"> 436</span> </div> +<div class="line"><a id="l00437" name="l00437"></a><span class="lineno"> 437</span> </div> +<div class="line"><a id="l00438" name="l00438"></a><span class="lineno"> 438</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00439" name="l00439"></a><span class="lineno"> 439</span><span class="comment">// !!! UNSUPPORTED instructions !!!</span></div> +<div class="line"><a id="l00440" name="l00440"></a><span class="lineno"> 440</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00441" name="l00441"></a><span class="lineno"> 441</span> </div> +<div class="line"><a id="l00442" name="l00442"></a><span class="lineno"> 442</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00451" name="l00451"></a><span class="lineno"> 451</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fdivs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00452" name="l00452"></a><span class="lineno"> 452</span> </div> +<div class="line"><a id="l00453" name="l00453"></a><span class="lineno"> 453</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00454" name="l00454"></a><span class="lineno"> 454</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00455" name="l00455"></a><span class="lineno"> 455</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00456" name="l00456"></a><span class="lineno"> 456</span> </div> +<div class="line"><a id="l00457" name="l00457"></a><span class="lineno"> 457</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0001100, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00458" name="l00458"></a><span class="lineno"> 458</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00459" name="l00459"></a><span class="lineno"> 459</span>}</div> +<div class="line"><a id="l00460" name="l00460"></a><span class="lineno"> 460</span> </div> +<div class="line"><a id="l00461" name="l00461"></a><span class="lineno"> 461</span> </div> +<div class="line"><a id="l00462" name="l00462"></a><span class="lineno"> 462</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00470" name="l00470"></a><span class="lineno"> 470</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsqrts(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00471" name="l00471"></a><span class="lineno"> 471</span> </div> +<div class="line"><a id="l00472" name="l00472"></a><span class="lineno"> 472</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, res;</div> +<div class="line"><a id="l00473" name="l00473"></a><span class="lineno"> 473</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00474" name="l00474"></a><span class="lineno"> 474</span> </div> +<div class="line"><a id="l00475" name="l00475"></a><span class="lineno"> 475</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R2_TYPE(0b0101100, 0b00000, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00476" name="l00476"></a><span class="lineno"> 476</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00477" name="l00477"></a><span class="lineno"> 477</span>}</div> +<div class="line"><a id="l00478" name="l00478"></a><span class="lineno"> 478</span> </div> +<div class="line"><a id="l00479" name="l00479"></a><span class="lineno"> 479</span> </div> +<div class="line"><a id="l00480" name="l00480"></a><span class="lineno"> 480</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00490" name="l00490"></a><span class="lineno"> 490</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l00491" name="l00491"></a><span class="lineno"> 491</span> </div> +<div class="line"><a id="l00492" name="l00492"></a><span class="lineno"> 492</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, opc, res;</div> +<div class="line"><a id="l00493" name="l00493"></a><span class="lineno"> 493</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00494" name="l00494"></a><span class="lineno"> 494</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00495" name="l00495"></a><span class="lineno"> 495</span> opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs3;</div> +<div class="line"><a id="l00496" name="l00496"></a><span class="lineno"> 496</span> </div> +<div class="line"><a id="l00497" name="l00497"></a><span class="lineno"> 497</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R4_TYPE(opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1000011);</div> +<div class="line"><a id="l00498" name="l00498"></a><span class="lineno"> 498</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00499" name="l00499"></a><span class="lineno"> 499</span>}</div> +<div class="line"><a id="l00500" name="l00500"></a><span class="lineno"> 500</span> </div> +<div class="line"><a id="l00501" name="l00501"></a><span class="lineno"> 501</span> </div> +<div class="line"><a id="l00502" name="l00502"></a><span class="lineno"> 502</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00512" name="l00512"></a><span class="lineno"> 512</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l00513" name="l00513"></a><span class="lineno"> 513</span> </div> +<div class="line"><a id="l00514" name="l00514"></a><span class="lineno"> 514</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, opc, res;</div> +<div class="line"><a id="l00515" name="l00515"></a><span class="lineno"> 515</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00516" name="l00516"></a><span class="lineno"> 516</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00517" name="l00517"></a><span class="lineno"> 517</span> opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs3;</div> +<div class="line"><a id="l00518" name="l00518"></a><span class="lineno"> 518</span> </div> +<div class="line"><a id="l00519" name="l00519"></a><span class="lineno"> 519</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R4_TYPE(opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1000111);</div> +<div class="line"><a id="l00520" name="l00520"></a><span class="lineno"> 520</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00521" name="l00521"></a><span class="lineno"> 521</span>}</div> +<div class="line"><a id="l00522" name="l00522"></a><span class="lineno"> 522</span> </div> +<div class="line"><a id="l00523" name="l00523"></a><span class="lineno"> 523</span> </div> +<div class="line"><a id="l00524" name="l00524"></a><span class="lineno"> 524</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00534" name="l00534"></a><span class="lineno"> 534</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fnmsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l00535" name="l00535"></a><span class="lineno"> 535</span> </div> +<div class="line"><a id="l00536" name="l00536"></a><span class="lineno"> 536</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, opc, res;</div> +<div class="line"><a id="l00537" name="l00537"></a><span class="lineno"> 537</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00538" name="l00538"></a><span class="lineno"> 538</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00539" name="l00539"></a><span class="lineno"> 539</span> opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs3;</div> +<div class="line"><a id="l00540" name="l00540"></a><span class="lineno"> 540</span> </div> +<div class="line"><a id="l00541" name="l00541"></a><span class="lineno"> 541</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R4_TYPE(opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1001011);</div> +<div class="line"><a id="l00542" name="l00542"></a><span class="lineno"> 542</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00543" name="l00543"></a><span class="lineno"> 543</span>}</div> +<div class="line"><a id="l00544" name="l00544"></a><span class="lineno"> 544</span> </div> +<div class="line"><a id="l00545" name="l00545"></a><span class="lineno"> 545</span> </div> +<div class="line"><a id="l00546" name="l00546"></a><span class="lineno"> 546</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00556" name="l00556"></a><span class="lineno"> 556</span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fnmadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l00557" name="l00557"></a><span class="lineno"> 557</span> </div> +<div class="line"><a id="l00558" name="l00558"></a><span class="lineno"> 558</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, opc, res;</div> +<div class="line"><a id="l00559" name="l00559"></a><span class="lineno"> 559</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00560" name="l00560"></a><span class="lineno"> 560</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00561" name="l00561"></a><span class="lineno"> 561</span> opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs3;</div> +<div class="line"><a id="l00562" name="l00562"></a><span class="lineno"> 562</span> </div> +<div class="line"><a id="l00563" name="l00563"></a><span class="lineno"> 563</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R4_TYPE(opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1001111);</div> +<div class="line"><a id="l00564" name="l00564"></a><span class="lineno"> 564</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00565" name="l00565"></a><span class="lineno"> 565</span>}</div> +<div class="line"><a id="l00566" name="l00566"></a><span class="lineno"> 566</span> </div> +<div class="line"><a id="l00567" name="l00567"></a><span class="lineno"> 567</span> </div> +<div class="line"><a id="l00568" name="l00568"></a><span class="lineno"> 568</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00569" name="l00569"></a><span class="lineno"> 569</span><span class="comment">// Emulation functions</span></div> +<div class="line"><a id="l00570" name="l00570"></a><span class="lineno"> 570</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00571" name="l00571"></a><span class="lineno"> 571</span> </div> +<div class="line"><a id="l00572" name="l00572"></a><span class="lineno"> 572</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00579" name="l00579"></a><span class="lineno"> 579</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00580" name="l00580"></a><span class="lineno"> 580</span> </div> +<div class="line"><a id="l00581" name="l00581"></a><span class="lineno"> 581</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00582" name="l00582"></a><span class="lineno"> 582</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00583" name="l00583"></a><span class="lineno"> 583</span> </div> +<div class="line"><a id="l00584" name="l00584"></a><span class="lineno"> 584</span> <span class="keywordtype">float</span> res = opa + opb;</div> +<div class="line"><a id="l00585" name="l00585"></a><span class="lineno"> 585</span> </div> +<div class="line"><a id="l00586" name="l00586"></a><span class="lineno"> 586</span> <span class="comment">// make NAN canonical</span></div> +<div class="line"><a id="l00587" name="l00587"></a><span class="lineno"> 587</span> <span class="keywordflow">if</span> (fpclassify(res) == FP_NAN) {</div> +<div class="line"><a id="l00588" name="l00588"></a><span class="lineno"> 588</span> res = NAN;</div> +<div class="line"><a id="l00589" name="l00589"></a><span class="lineno"> 589</span> }</div> +<div class="line"><a id="l00590" name="l00590"></a><span class="lineno"> 590</span> </div> +<div class="line"><a id="l00591" name="l00591"></a><span class="lineno"> 591</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l00592" name="l00592"></a><span class="lineno"> 592</span>}</div> +<div class="line"><a id="l00593" name="l00593"></a><span class="lineno"> 593</span> </div> +<div class="line"><a id="l00594" name="l00594"></a><span class="lineno"> 594</span> </div> +<div class="line"><a id="l00595" name="l00595"></a><span class="lineno"> 595</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00602" name="l00602"></a><span class="lineno"> 602</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00603" name="l00603"></a><span class="lineno"> 603</span> </div> +<div class="line"><a id="l00604" name="l00604"></a><span class="lineno"> 604</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00605" name="l00605"></a><span class="lineno"> 605</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00606" name="l00606"></a><span class="lineno"> 606</span> </div> +<div class="line"><a id="l00607" name="l00607"></a><span class="lineno"> 607</span> <span class="keywordtype">float</span> res = opa - opb;</div> +<div class="line"><a id="l00608" name="l00608"></a><span class="lineno"> 608</span> </div> +<div class="line"><a id="l00609" name="l00609"></a><span class="lineno"> 609</span> <span class="comment">// make NAN canonical</span></div> +<div class="line"><a id="l00610" name="l00610"></a><span class="lineno"> 610</span> <span class="keywordflow">if</span> (fpclassify(res) == FP_NAN) {</div> +<div class="line"><a id="l00611" name="l00611"></a><span class="lineno"> 611</span> res = NAN;</div> +<div class="line"><a id="l00612" name="l00612"></a><span class="lineno"> 612</span> }</div> +<div class="line"><a id="l00613" name="l00613"></a><span class="lineno"> 613</span> </div> +<div class="line"><a id="l00614" name="l00614"></a><span class="lineno"> 614</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l00615" name="l00615"></a><span class="lineno"> 615</span>}</div> +<div class="line"><a id="l00616" name="l00616"></a><span class="lineno"> 616</span> </div> +<div class="line"><a id="l00617" name="l00617"></a><span class="lineno"> 617</span> </div> +<div class="line"><a id="l00618" name="l00618"></a><span class="lineno"> 618</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00625" name="l00625"></a><span class="lineno"> 625</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmuls(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00626" name="l00626"></a><span class="lineno"> 626</span> </div> +<div class="line"><a id="l00627" name="l00627"></a><span class="lineno"> 627</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00628" name="l00628"></a><span class="lineno"> 628</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00629" name="l00629"></a><span class="lineno"> 629</span> </div> +<div class="line"><a id="l00630" name="l00630"></a><span class="lineno"> 630</span> <span class="keywordtype">float</span> res = opa * opb;</div> +<div class="line"><a id="l00631" name="l00631"></a><span class="lineno"> 631</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l00632" name="l00632"></a><span class="lineno"> 632</span>}</div> +<div class="line"><a id="l00633" name="l00633"></a><span class="lineno"> 633</span> </div> +<div class="line"><a id="l00634" name="l00634"></a><span class="lineno"> 634</span> </div> +<div class="line"><a id="l00635" name="l00635"></a><span class="lineno"> 635</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00642" name="l00642"></a><span class="lineno"> 642</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmins(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00643" name="l00643"></a><span class="lineno"> 643</span> </div> +<div class="line"><a id="l00644" name="l00644"></a><span class="lineno"> 644</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00645" name="l00645"></a><span class="lineno"> 645</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00646" name="l00646"></a><span class="lineno"> 646</span> </div> +<div class="line"><a id="l00647" name="l00647"></a><span class="lineno"> 647</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00648" name="l00648"></a><span class="lineno"> 648</span> uint32_t binary_value; </div> +<div class="line"><a id="l00649" name="l00649"></a><span class="lineno"> 649</span> <span class="keywordtype">float</span> float_value; </div> +<div class="line"><a id="l00650" name="l00650"></a><span class="lineno"> 650</span> } tmp_a, tmp_b;</div> +<div class="line"><a id="l00651" name="l00651"></a><span class="lineno"> 651</span> </div> +<div class="line"><a id="l00652" name="l00652"></a><span class="lineno"> 652</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) &amp;&amp; (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00653" name="l00653"></a><span class="lineno"> 653</span> <span class="keywordflow">return</span> nanf(<span class="stringliteral">&quot;&quot;</span>);</div> +<div class="line"><a id="l00654" name="l00654"></a><span class="lineno"> 654</span> }</div> +<div class="line"><a id="l00655" name="l00655"></a><span class="lineno"> 655</span> </div> +<div class="line"><a id="l00656" name="l00656"></a><span class="lineno"> 656</span> <span class="keywordflow">if</span> (fpclassify(opa) == FP_NAN) {</div> +<div class="line"><a id="l00657" name="l00657"></a><span class="lineno"> 657</span> <span class="keywordflow">return</span> opb;</div> +<div class="line"><a id="l00658" name="l00658"></a><span class="lineno"> 658</span> }</div> +<div class="line"><a id="l00659" name="l00659"></a><span class="lineno"> 659</span> </div> +<div class="line"><a id="l00660" name="l00660"></a><span class="lineno"> 660</span> <span class="keywordflow">if</span> (fpclassify(opb) == FP_NAN) {</div> +<div class="line"><a id="l00661" name="l00661"></a><span class="lineno"> 661</span> <span class="keywordflow">return</span> opa;</div> +<div class="line"><a id="l00662" name="l00662"></a><span class="lineno"> 662</span> }</div> +<div class="line"><a id="l00663" name="l00663"></a><span class="lineno"> 663</span> </div> +<div class="line"><a id="l00664" name="l00664"></a><span class="lineno"> 664</span> <span class="comment">// RISC-V spec: -0 &lt; +0</span></div> +<div class="line"><a id="l00665" name="l00665"></a><span class="lineno"> 665</span> tmp_a.float_value = opa;</div> +<div class="line"><a id="l00666" name="l00666"></a><span class="lineno"> 666</span> tmp_b.float_value = opb;</div> +<div class="line"><a id="l00667" name="l00667"></a><span class="lineno"> 667</span> <span class="keywordflow">if</span> (((tmp_a.binary_value == 0x80000000) &amp;&amp; (tmp_b.binary_value == 0x00000000)) ||</div> +<div class="line"><a id="l00668" name="l00668"></a><span class="lineno"> 668</span> ((tmp_a.binary_value == 0x00000000) &amp;&amp; (tmp_b.binary_value == 0x80000000))) {</div> +<div class="line"><a id="l00669" name="l00669"></a><span class="lineno"> 669</span> <span class="keywordflow">return</span> -0.0f;</div> +<div class="line"><a id="l00670" name="l00670"></a><span class="lineno"> 670</span> }</div> +<div class="line"><a id="l00671" name="l00671"></a><span class="lineno"> 671</span> </div> +<div class="line"><a id="l00672" name="l00672"></a><span class="lineno"> 672</span> <span class="keywordflow">return</span> fmin(opa, opb);</div> +<div class="line"><a id="l00673" name="l00673"></a><span class="lineno"> 673</span>}</div> +<div class="line"><a id="l00674" name="l00674"></a><span class="lineno"> 674</span> </div> +<div class="line"><a id="l00675" name="l00675"></a><span class="lineno"> 675</span> </div> +<div class="line"><a id="l00676" name="l00676"></a><span class="lineno"> 676</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00683" name="l00683"></a><span class="lineno"> 683</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmaxs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00684" name="l00684"></a><span class="lineno"> 684</span> </div> +<div class="line"><a id="l00685" name="l00685"></a><span class="lineno"> 685</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00686" name="l00686"></a><span class="lineno"> 686</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00687" name="l00687"></a><span class="lineno"> 687</span> </div> +<div class="line"><a id="l00688" name="l00688"></a><span class="lineno"> 688</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00689" name="l00689"></a><span class="lineno"> 689</span> uint32_t binary_value; </div> +<div class="line"><a id="l00690" name="l00690"></a><span class="lineno"> 690</span> <span class="keywordtype">float</span> float_value; </div> +<div class="line"><a id="l00691" name="l00691"></a><span class="lineno"> 691</span> } tmp_a, tmp_b;</div> +<div class="line"><a id="l00692" name="l00692"></a><span class="lineno"> 692</span> </div> +<div class="line"><a id="l00693" name="l00693"></a><span class="lineno"> 693</span> </div> +<div class="line"><a id="l00694" name="l00694"></a><span class="lineno"> 694</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) &amp;&amp; (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00695" name="l00695"></a><span class="lineno"> 695</span> <span class="keywordflow">return</span> nanf(<span class="stringliteral">&quot;&quot;</span>);</div> +<div class="line"><a id="l00696" name="l00696"></a><span class="lineno"> 696</span> }</div> +<div class="line"><a id="l00697" name="l00697"></a><span class="lineno"> 697</span> </div> +<div class="line"><a id="l00698" name="l00698"></a><span class="lineno"> 698</span> <span class="keywordflow">if</span> (fpclassify(opa) == FP_NAN) {</div> +<div class="line"><a id="l00699" name="l00699"></a><span class="lineno"> 699</span> <span class="keywordflow">return</span> opb;</div> +<div class="line"><a id="l00700" name="l00700"></a><span class="lineno"> 700</span> }</div> +<div class="line"><a id="l00701" name="l00701"></a><span class="lineno"> 701</span> </div> +<div class="line"><a id="l00702" name="l00702"></a><span class="lineno"> 702</span> <span class="keywordflow">if</span> (fpclassify(opb) == FP_NAN) {</div> +<div class="line"><a id="l00703" name="l00703"></a><span class="lineno"> 703</span> <span class="keywordflow">return</span> opa;</div> +<div class="line"><a id="l00704" name="l00704"></a><span class="lineno"> 704</span> }</div> +<div class="line"><a id="l00705" name="l00705"></a><span class="lineno"> 705</span> </div> +<div class="line"><a id="l00706" name="l00706"></a><span class="lineno"> 706</span> <span class="comment">// RISC-V spec: -0 &lt; +0</span></div> +<div class="line"><a id="l00707" name="l00707"></a><span class="lineno"> 707</span> tmp_a.float_value = opa;</div> +<div class="line"><a id="l00708" name="l00708"></a><span class="lineno"> 708</span> tmp_b.float_value = opb;</div> +<div class="line"><a id="l00709" name="l00709"></a><span class="lineno"> 709</span> <span class="keywordflow">if</span> (((tmp_a.binary_value == 0x80000000) &amp;&amp; (tmp_b.binary_value == 0x00000000)) ||</div> +<div class="line"><a id="l00710" name="l00710"></a><span class="lineno"> 710</span> ((tmp_a.binary_value == 0x00000000) &amp;&amp; (tmp_b.binary_value == 0x80000000))) {</div> +<div class="line"><a id="l00711" name="l00711"></a><span class="lineno"> 711</span> <span class="keywordflow">return</span> +0.0f;</div> +<div class="line"><a id="l00712" name="l00712"></a><span class="lineno"> 712</span> }</div> +<div class="line"><a id="l00713" name="l00713"></a><span class="lineno"> 713</span> </div> +<div class="line"><a id="l00714" name="l00714"></a><span class="lineno"> 714</span> <span class="keywordflow">return</span> fmax(opa, opb);</div> +<div class="line"><a id="l00715" name="l00715"></a><span class="lineno"> 715</span>}</div> +<div class="line"><a id="l00716" name="l00716"></a><span class="lineno"> 716</span> </div> +<div class="line"><a id="l00717" name="l00717"></a><span class="lineno"> 717</span> </div> +<div class="line"><a id="l00718" name="l00718"></a><span class="lineno"> 718</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00724" name="l00724"></a><span class="lineno"> 724</span>uint32_t __attribute__ ((noinline)) riscv_emulate_fcvt_wus(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00725" name="l00725"></a><span class="lineno"> 725</span> </div> +<div class="line"><a id="l00726" name="l00726"></a><span class="lineno"> 726</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00727" name="l00727"></a><span class="lineno"> 727</span> </div> +<div class="line"><a id="l00728" name="l00728"></a><span class="lineno"> 728</span> <span class="keywordflow">return</span> (uint32_t)roundf(opa);</div> +<div class="line"><a id="l00729" name="l00729"></a><span class="lineno"> 729</span>}</div> +<div class="line"><a id="l00730" name="l00730"></a><span class="lineno"> 730</span> </div> +<div class="line"><a id="l00731" name="l00731"></a><span class="lineno"> 731</span> </div> +<div class="line"><a id="l00732" name="l00732"></a><span class="lineno"> 732</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00738" name="l00738"></a><span class="lineno"> 738</span>int32_t __attribute__ ((noinline)) riscv_emulate_fcvt_ws(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00739" name="l00739"></a><span class="lineno"> 739</span> </div> +<div class="line"><a id="l00740" name="l00740"></a><span class="lineno"> 740</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00741" name="l00741"></a><span class="lineno"> 741</span> </div> +<div class="line"><a id="l00742" name="l00742"></a><span class="lineno"> 742</span> <span class="keywordflow">return</span> (int32_t)roundf(opa);</div> +<div class="line"><a id="l00743" name="l00743"></a><span class="lineno"> 743</span>}</div> +<div class="line"><a id="l00744" name="l00744"></a><span class="lineno"> 744</span> </div> +<div class="line"><a id="l00745" name="l00745"></a><span class="lineno"> 745</span> </div> +<div class="line"><a id="l00746" name="l00746"></a><span class="lineno"> 746</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00752" name="l00752"></a><span class="lineno"> 752</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fcvt_swu(uint32_t rs1) {</div> +<div class="line"><a id="l00753" name="l00753"></a><span class="lineno"> 753</span> </div> +<div class="line"><a id="l00754" name="l00754"></a><span class="lineno"> 754</span> <span class="keywordflow">return</span> (<span class="keywordtype">float</span>)rs1;</div> +<div class="line"><a id="l00755" name="l00755"></a><span class="lineno"> 755</span>}</div> +<div class="line"><a id="l00756" name="l00756"></a><span class="lineno"> 756</span> </div> +<div class="line"><a id="l00757" name="l00757"></a><span class="lineno"> 757</span> </div> +<div class="line"><a id="l00758" name="l00758"></a><span class="lineno"> 758</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00764" name="l00764"></a><span class="lineno"> 764</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fcvt_sw(int32_t rs1) {</div> +<div class="line"><a id="l00765" name="l00765"></a><span class="lineno"> 765</span> </div> +<div class="line"><a id="l00766" name="l00766"></a><span class="lineno"> 766</span> <span class="keywordflow">return</span> (<span class="keywordtype">float</span>)rs1;</div> +<div class="line"><a id="l00767" name="l00767"></a><span class="lineno"> 767</span>}</div> +<div class="line"><a id="l00768" name="l00768"></a><span class="lineno"> 768</span> </div> +<div class="line"><a id="l00769" name="l00769"></a><span class="lineno"> 769</span> </div> +<div class="line"><a id="l00770" name="l00770"></a><span class="lineno"> 770</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00777" name="l00777"></a><span class="lineno"> 777</span>uint32_t __attribute__ ((noinline)) riscv_emulate_feqs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00778" name="l00778"></a><span class="lineno"> 778</span> </div> +<div class="line"><a id="l00779" name="l00779"></a><span class="lineno"> 779</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00780" name="l00780"></a><span class="lineno"> 780</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00781" name="l00781"></a><span class="lineno"> 781</span> </div> +<div class="line"><a id="l00782" name="l00782"></a><span class="lineno"> 782</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00783" name="l00783"></a><span class="lineno"> 783</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00784" name="l00784"></a><span class="lineno"> 784</span> }</div> +<div class="line"><a id="l00785" name="l00785"></a><span class="lineno"> 785</span> </div> +<div class="line"><a id="l00786" name="l00786"></a><span class="lineno"> 786</span> <span class="keywordflow">if</span> isless(opa, opb) {</div> +<div class="line"><a id="l00787" name="l00787"></a><span class="lineno"> 787</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00788" name="l00788"></a><span class="lineno"> 788</span> }</div> +<div class="line"><a id="l00789" name="l00789"></a><span class="lineno"> 789</span> <span class="keywordflow">else</span> <span class="keywordflow">if</span> isgreater(opa, opb) {</div> +<div class="line"><a id="l00790" name="l00790"></a><span class="lineno"> 790</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00791" name="l00791"></a><span class="lineno"> 791</span> }</div> +<div class="line"><a id="l00792" name="l00792"></a><span class="lineno"> 792</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00793" name="l00793"></a><span class="lineno"> 793</span> <span class="keywordflow">return</span> 1;</div> +<div class="line"><a id="l00794" name="l00794"></a><span class="lineno"> 794</span> }</div> +<div class="line"><a id="l00795" name="l00795"></a><span class="lineno"> 795</span>}</div> +<div class="line"><a id="l00796" name="l00796"></a><span class="lineno"> 796</span> </div> +<div class="line"><a id="l00797" name="l00797"></a><span class="lineno"> 797</span> </div> +<div class="line"><a id="l00798" name="l00798"></a><span class="lineno"> 798</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00805" name="l00805"></a><span class="lineno"> 805</span>uint32_t __attribute__ ((noinline)) riscv_emulate_flts(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00806" name="l00806"></a><span class="lineno"> 806</span> </div> +<div class="line"><a id="l00807" name="l00807"></a><span class="lineno"> 807</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00808" name="l00808"></a><span class="lineno"> 808</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00809" name="l00809"></a><span class="lineno"> 809</span> </div> +<div class="line"><a id="l00810" name="l00810"></a><span class="lineno"> 810</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00811" name="l00811"></a><span class="lineno"> 811</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00812" name="l00812"></a><span class="lineno"> 812</span> }</div> +<div class="line"><a id="l00813" name="l00813"></a><span class="lineno"> 813</span> </div> +<div class="line"><a id="l00814" name="l00814"></a><span class="lineno"> 814</span> <span class="keywordflow">if</span> isless(opa, opb) {</div> +<div class="line"><a id="l00815" name="l00815"></a><span class="lineno"> 815</span> <span class="keywordflow">return</span> 1;</div> +<div class="line"><a id="l00816" name="l00816"></a><span class="lineno"> 816</span> }</div> +<div class="line"><a id="l00817" name="l00817"></a><span class="lineno"> 817</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00818" name="l00818"></a><span class="lineno"> 818</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00819" name="l00819"></a><span class="lineno"> 819</span> }</div> +<div class="line"><a id="l00820" name="l00820"></a><span class="lineno"> 820</span>}</div> +<div class="line"><a id="l00821" name="l00821"></a><span class="lineno"> 821</span> </div> +<div class="line"><a id="l00822" name="l00822"></a><span class="lineno"> 822</span> </div> +<div class="line"><a id="l00823" name="l00823"></a><span class="lineno"> 823</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00830" name="l00830"></a><span class="lineno"> 830</span>uint32_t __attribute__ ((noinline)) riscv_emulate_fles(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00831" name="l00831"></a><span class="lineno"> 831</span> </div> +<div class="line"><a id="l00832" name="l00832"></a><span class="lineno"> 832</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00833" name="l00833"></a><span class="lineno"> 833</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00834" name="l00834"></a><span class="lineno"> 834</span> </div> +<div class="line"><a id="l00835" name="l00835"></a><span class="lineno"> 835</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00836" name="l00836"></a><span class="lineno"> 836</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00837" name="l00837"></a><span class="lineno"> 837</span> }</div> +<div class="line"><a id="l00838" name="l00838"></a><span class="lineno"> 838</span> </div> +<div class="line"><a id="l00839" name="l00839"></a><span class="lineno"> 839</span> <span class="keywordflow">if</span> islessequal(opa, opb) {</div> +<div class="line"><a id="l00840" name="l00840"></a><span class="lineno"> 840</span> <span class="keywordflow">return</span> 1;</div> +<div class="line"><a id="l00841" name="l00841"></a><span class="lineno"> 841</span> }</div> +<div class="line"><a id="l00842" name="l00842"></a><span class="lineno"> 842</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00843" name="l00843"></a><span class="lineno"> 843</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00844" name="l00844"></a><span class="lineno"> 844</span> }</div> +<div class="line"><a id="l00845" name="l00845"></a><span class="lineno"> 845</span>}</div> +<div class="line"><a id="l00846" name="l00846"></a><span class="lineno"> 846</span> </div> +<div class="line"><a id="l00847" name="l00847"></a><span class="lineno"> 847</span> </div> +<div class="line"><a id="l00848" name="l00848"></a><span class="lineno"> 848</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00855" name="l00855"></a><span class="lineno"> 855</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsgnjs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00856" name="l00856"></a><span class="lineno"> 856</span> </div> +<div class="line"><a id="l00857" name="l00857"></a><span class="lineno"> 857</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00858" name="l00858"></a><span class="lineno"> 858</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00859" name="l00859"></a><span class="lineno"> 859</span> </div> +<div class="line"><a id="l00860" name="l00860"></a><span class="lineno"> 860</span> <span class="keywordtype">int</span> sign_1 = (int)signbit(opa);</div> +<div class="line"><a id="l00861" name="l00861"></a><span class="lineno"> 861</span> <span class="keywordtype">int</span> sign_2 = (int)signbit(opb);</div> +<div class="line"><a id="l00862" name="l00862"></a><span class="lineno"> 862</span> <span class="keywordtype">float</span> res = 0;</div> +<div class="line"><a id="l00863" name="l00863"></a><span class="lineno"> 863</span> </div> +<div class="line"><a id="l00864" name="l00864"></a><span class="lineno"> 864</span> <span class="keywordflow">if</span> (sign_2 != 0) { <span class="comment">// opb is negative</span></div> +<div class="line"><a id="l00865" name="l00865"></a><span class="lineno"> 865</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00866" name="l00866"></a><span class="lineno"> 866</span> res = -opa;</div> +<div class="line"><a id="l00867" name="l00867"></a><span class="lineno"> 867</span> }</div> +<div class="line"><a id="l00868" name="l00868"></a><span class="lineno"> 868</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00869" name="l00869"></a><span class="lineno"> 869</span> res = opa;</div> +<div class="line"><a id="l00870" name="l00870"></a><span class="lineno"> 870</span> }</div> +<div class="line"><a id="l00871" name="l00871"></a><span class="lineno"> 871</span> }</div> +<div class="line"><a id="l00872" name="l00872"></a><span class="lineno"> 872</span> <span class="keywordflow">else</span> { <span class="comment">// opb is positive</span></div> +<div class="line"><a id="l00873" name="l00873"></a><span class="lineno"> 873</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00874" name="l00874"></a><span class="lineno"> 874</span> res = opa;</div> +<div class="line"><a id="l00875" name="l00875"></a><span class="lineno"> 875</span> }</div> +<div class="line"><a id="l00876" name="l00876"></a><span class="lineno"> 876</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00877" name="l00877"></a><span class="lineno"> 877</span> res = -opa;</div> +<div class="line"><a id="l00878" name="l00878"></a><span class="lineno"> 878</span> }</div> +<div class="line"><a id="l00879" name="l00879"></a><span class="lineno"> 879</span> }</div> +<div class="line"><a id="l00880" name="l00880"></a><span class="lineno"> 880</span> </div> +<div class="line"><a id="l00881" name="l00881"></a><span class="lineno"> 881</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00882" name="l00882"></a><span class="lineno"> 882</span>}</div> +<div class="line"><a id="l00883" name="l00883"></a><span class="lineno"> 883</span> </div> +<div class="line"><a id="l00884" name="l00884"></a><span class="lineno"> 884</span> </div> +<div class="line"><a id="l00885" name="l00885"></a><span class="lineno"> 885</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00892" name="l00892"></a><span class="lineno"> 892</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsgnjns(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00893" name="l00893"></a><span class="lineno"> 893</span> </div> +<div class="line"><a id="l00894" name="l00894"></a><span class="lineno"> 894</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00895" name="l00895"></a><span class="lineno"> 895</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00896" name="l00896"></a><span class="lineno"> 896</span> </div> +<div class="line"><a id="l00897" name="l00897"></a><span class="lineno"> 897</span> <span class="keywordtype">int</span> sign_1 = (int)signbit(opa);</div> +<div class="line"><a id="l00898" name="l00898"></a><span class="lineno"> 898</span> <span class="keywordtype">int</span> sign_2 = (int)signbit(opb);</div> +<div class="line"><a id="l00899" name="l00899"></a><span class="lineno"> 899</span> <span class="keywordtype">float</span> res = 0;</div> +<div class="line"><a id="l00900" name="l00900"></a><span class="lineno"> 900</span> </div> +<div class="line"><a id="l00901" name="l00901"></a><span class="lineno"> 901</span> <span class="keywordflow">if</span> (sign_2 != 0) { <span class="comment">// opb is negative</span></div> +<div class="line"><a id="l00902" name="l00902"></a><span class="lineno"> 902</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00903" name="l00903"></a><span class="lineno"> 903</span> res = opa;</div> +<div class="line"><a id="l00904" name="l00904"></a><span class="lineno"> 904</span> }</div> +<div class="line"><a id="l00905" name="l00905"></a><span class="lineno"> 905</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00906" name="l00906"></a><span class="lineno"> 906</span> res = -opa;</div> +<div class="line"><a id="l00907" name="l00907"></a><span class="lineno"> 907</span> }</div> +<div class="line"><a id="l00908" name="l00908"></a><span class="lineno"> 908</span> }</div> +<div class="line"><a id="l00909" name="l00909"></a><span class="lineno"> 909</span> <span class="keywordflow">else</span> { <span class="comment">// opb is positive</span></div> +<div class="line"><a id="l00910" name="l00910"></a><span class="lineno"> 910</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00911" name="l00911"></a><span class="lineno"> 911</span> res = -opa;</div> +<div class="line"><a id="l00912" name="l00912"></a><span class="lineno"> 912</span> }</div> +<div class="line"><a id="l00913" name="l00913"></a><span class="lineno"> 913</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00914" name="l00914"></a><span class="lineno"> 914</span> res = opa;</div> +<div class="line"><a id="l00915" name="l00915"></a><span class="lineno"> 915</span> }</div> +<div class="line"><a id="l00916" name="l00916"></a><span class="lineno"> 916</span> }</div> +<div class="line"><a id="l00917" name="l00917"></a><span class="lineno"> 917</span> </div> +<div class="line"><a id="l00918" name="l00918"></a><span class="lineno"> 918</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00919" name="l00919"></a><span class="lineno"> 919</span>}</div> +<div class="line"><a id="l00920" name="l00920"></a><span class="lineno"> 920</span> </div> +<div class="line"><a id="l00921" name="l00921"></a><span class="lineno"> 921</span> </div> +<div class="line"><a id="l00922" name="l00922"></a><span class="lineno"> 922</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00929" name="l00929"></a><span class="lineno"> 929</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsgnjxs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00930" name="l00930"></a><span class="lineno"> 930</span> </div> +<div class="line"><a id="l00931" name="l00931"></a><span class="lineno"> 931</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00932" name="l00932"></a><span class="lineno"> 932</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00933" name="l00933"></a><span class="lineno"> 933</span> </div> +<div class="line"><a id="l00934" name="l00934"></a><span class="lineno"> 934</span> <span class="keywordtype">int</span> sign_1 = (int)signbit(opa);</div> +<div class="line"><a id="l00935" name="l00935"></a><span class="lineno"> 935</span> <span class="keywordtype">int</span> sign_2 = (int)signbit(opb);</div> +<div class="line"><a id="l00936" name="l00936"></a><span class="lineno"> 936</span> <span class="keywordtype">float</span> res = 0;</div> +<div class="line"><a id="l00937" name="l00937"></a><span class="lineno"> 937</span> </div> +<div class="line"><a id="l00938" name="l00938"></a><span class="lineno"> 938</span> <span class="keywordflow">if</span> (((sign_1 == 0) &amp;&amp; (sign_2 != 0)) || ((sign_1 != 0) &amp;&amp; (sign_2 == 0))) {</div> +<div class="line"><a id="l00939" name="l00939"></a><span class="lineno"> 939</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00940" name="l00940"></a><span class="lineno"> 940</span> res = -opa;</div> +<div class="line"><a id="l00941" name="l00941"></a><span class="lineno"> 941</span> }</div> +<div class="line"><a id="l00942" name="l00942"></a><span class="lineno"> 942</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00943" name="l00943"></a><span class="lineno"> 943</span> res = opa;</div> +<div class="line"><a id="l00944" name="l00944"></a><span class="lineno"> 944</span> }</div> +<div class="line"><a id="l00945" name="l00945"></a><span class="lineno"> 945</span> }</div> +<div class="line"><a id="l00946" name="l00946"></a><span class="lineno"> 946</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00947" name="l00947"></a><span class="lineno"> 947</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00948" name="l00948"></a><span class="lineno"> 948</span> res = opa;</div> +<div class="line"><a id="l00949" name="l00949"></a><span class="lineno"> 949</span> }</div> +<div class="line"><a id="l00950" name="l00950"></a><span class="lineno"> 950</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00951" name="l00951"></a><span class="lineno"> 951</span> res = -opa;</div> +<div class="line"><a id="l00952" name="l00952"></a><span class="lineno"> 952</span> }</div> +<div class="line"><a id="l00953" name="l00953"></a><span class="lineno"> 953</span> }</div> +<div class="line"><a id="l00954" name="l00954"></a><span class="lineno"> 954</span> </div> +<div class="line"><a id="l00955" name="l00955"></a><span class="lineno"> 955</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00956" name="l00956"></a><span class="lineno"> 956</span>}</div> +<div class="line"><a id="l00957" name="l00957"></a><span class="lineno"> 957</span> </div> +<div class="line"><a id="l00958" name="l00958"></a><span class="lineno"> 958</span> </div> +<div class="line"><a id="l00959" name="l00959"></a><span class="lineno"> 959</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00965" name="l00965"></a><span class="lineno"> 965</span>uint32_t __attribute__ ((noinline)) riscv_emulate_fclasss(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00966" name="l00966"></a><span class="lineno"> 966</span> </div> +<div class="line"><a id="l00967" name="l00967"></a><span class="lineno"> 967</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00968" name="l00968"></a><span class="lineno"> 968</span> </div> +<div class="line"><a id="l00969" name="l00969"></a><span class="lineno"> 969</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00970" name="l00970"></a><span class="lineno"> 970</span> uint32_t binary_value; </div> +<div class="line"><a id="l00971" name="l00971"></a><span class="lineno"> 971</span> <span class="keywordtype">float</span> float_value; </div> +<div class="line"><a id="l00972" name="l00972"></a><span class="lineno"> 972</span> } aux;</div> +<div class="line"><a id="l00973" name="l00973"></a><span class="lineno"> 973</span> </div> +<div class="line"><a id="l00974" name="l00974"></a><span class="lineno"> 974</span> <span class="comment">// RISC-V classify result layout</span></div> +<div class="line"><a id="l00975" name="l00975"></a><span class="lineno"> 975</span> <span class="keyword">const</span> uint32_t CLASS_NEG_INF = 1 &lt;&lt; 0; <span class="comment">// negative infinity</span></div> +<div class="line"><a id="l00976" name="l00976"></a><span class="lineno"> 976</span> <span class="keyword">const</span> uint32_t CLASS_NEG_NORM = 1 &lt;&lt; 1; <span class="comment">// negative normal number</span></div> +<div class="line"><a id="l00977" name="l00977"></a><span class="lineno"> 977</span> <span class="keyword">const</span> uint32_t CLASS_NEG_DENORM = 1 &lt;&lt; 2; <span class="comment">// negative subnormal number</span></div> +<div class="line"><a id="l00978" name="l00978"></a><span class="lineno"> 978</span> <span class="keyword">const</span> uint32_t CLASS_NEG_ZERO = 1 &lt;&lt; 3; <span class="comment">// negative zero</span></div> +<div class="line"><a id="l00979" name="l00979"></a><span class="lineno"> 979</span> <span class="keyword">const</span> uint32_t CLASS_POS_ZERO = 1 &lt;&lt; 4; <span class="comment">// positive zero</span></div> +<div class="line"><a id="l00980" name="l00980"></a><span class="lineno"> 980</span> <span class="keyword">const</span> uint32_t CLASS_POS_DENORM = 1 &lt;&lt; 5; <span class="comment">// positive subnormal number</span></div> +<div class="line"><a id="l00981" name="l00981"></a><span class="lineno"> 981</span> <span class="keyword">const</span> uint32_t CLASS_POS_NORM = 1 &lt;&lt; 6; <span class="comment">// positive normal number</span></div> +<div class="line"><a id="l00982" name="l00982"></a><span class="lineno"> 982</span> <span class="keyword">const</span> uint32_t CLASS_POS_INF = 1 &lt;&lt; 7; <span class="comment">// positive infinity</span></div> +<div class="line"><a id="l00983" name="l00983"></a><span class="lineno"> 983</span> <span class="keyword">const</span> uint32_t CLASS_SNAN = 1 &lt;&lt; 8; <span class="comment">// signaling NaN (sNaN)</span></div> +<div class="line"><a id="l00984" name="l00984"></a><span class="lineno"> 984</span> <span class="keyword">const</span> uint32_t CLASS_QNAN = 1 &lt;&lt; 9; <span class="comment">// quiet NaN (qNaN)</span></div> +<div class="line"><a id="l00985" name="l00985"></a><span class="lineno"> 985</span> </div> +<div class="line"><a id="l00986" name="l00986"></a><span class="lineno"> 986</span> <span class="keywordtype">int</span> tmp = fpclassify(opa);</div> +<div class="line"><a id="l00987" name="l00987"></a><span class="lineno"> 987</span> <span class="keywordtype">int</span> sgn = (int)signbit(opa);</div> +<div class="line"><a id="l00988" name="l00988"></a><span class="lineno"> 988</span> </div> +<div class="line"><a id="l00989" name="l00989"></a><span class="lineno"> 989</span> uint32_t res = 0;</div> +<div class="line"><a id="l00990" name="l00990"></a><span class="lineno"> 990</span> </div> +<div class="line"><a id="l00991" name="l00991"></a><span class="lineno"> 991</span> <span class="comment">// infinity</span></div> +<div class="line"><a id="l00992" name="l00992"></a><span class="lineno"> 992</span> <span class="keywordflow">if</span> (tmp == FP_INFINITE) {</div> +<div class="line"><a id="l00993" name="l00993"></a><span class="lineno"> 993</span> <span class="keywordflow">if</span> (sgn) { res |= CLASS_NEG_INF; }</div> +<div class="line"><a id="l00994" name="l00994"></a><span class="lineno"> 994</span> <span class="keywordflow">else</span> { res |= CLASS_POS_INF; }</div> +<div class="line"><a id="l00995" name="l00995"></a><span class="lineno"> 995</span> }</div> +<div class="line"><a id="l00996" name="l00996"></a><span class="lineno"> 996</span> </div> +<div class="line"><a id="l00997" name="l00997"></a><span class="lineno"> 997</span> <span class="comment">// zero</span></div> +<div class="line"><a id="l00998" name="l00998"></a><span class="lineno"> 998</span> <span class="keywordflow">if</span> (tmp == FP_ZERO) {</div> +<div class="line"><a id="l00999" name="l00999"></a><span class="lineno"> 999</span> <span class="keywordflow">if</span> (sgn) { res |= CLASS_NEG_ZERO; }</div> +<div class="line"><a id="l01000" name="l01000"></a><span class="lineno"> 1000</span> <span class="keywordflow">else</span> { res |= CLASS_POS_ZERO; }</div> +<div class="line"><a id="l01001" name="l01001"></a><span class="lineno"> 1001</span> }</div> +<div class="line"><a id="l01002" name="l01002"></a><span class="lineno"> 1002</span> </div> +<div class="line"><a id="l01003" name="l01003"></a><span class="lineno"> 1003</span> <span class="comment">// normal</span></div> +<div class="line"><a id="l01004" name="l01004"></a><span class="lineno"> 1004</span> <span class="keywordflow">if</span> (tmp == FP_NORMAL) {</div> +<div class="line"><a id="l01005" name="l01005"></a><span class="lineno"> 1005</span> <span class="keywordflow">if</span> (sgn) { res |= CLASS_NEG_NORM; }</div> +<div class="line"><a id="l01006" name="l01006"></a><span class="lineno"> 1006</span> <span class="keywordflow">else</span> { res |= CLASS_POS_NORM; }</div> +<div class="line"><a id="l01007" name="l01007"></a><span class="lineno"> 1007</span> }</div> +<div class="line"><a id="l01008" name="l01008"></a><span class="lineno"> 1008</span> </div> +<div class="line"><a id="l01009" name="l01009"></a><span class="lineno"> 1009</span> <span class="comment">// subnormal</span></div> +<div class="line"><a id="l01010" name="l01010"></a><span class="lineno"> 1010</span> <span class="keywordflow">if</span> (tmp == FP_SUBNORMAL) {</div> +<div class="line"><a id="l01011" name="l01011"></a><span class="lineno"> 1011</span> <span class="keywordflow">if</span> (sgn) { res |= CLASS_NEG_DENORM; }</div> +<div class="line"><a id="l01012" name="l01012"></a><span class="lineno"> 1012</span> <span class="keywordflow">else</span> { res |= CLASS_POS_DENORM; }</div> +<div class="line"><a id="l01013" name="l01013"></a><span class="lineno"> 1013</span> }</div> +<div class="line"><a id="l01014" name="l01014"></a><span class="lineno"> 1014</span> </div> +<div class="line"><a id="l01015" name="l01015"></a><span class="lineno"> 1015</span> <span class="comment">// NaN</span></div> +<div class="line"><a id="l01016" name="l01016"></a><span class="lineno"> 1016</span> <span class="keywordflow">if</span> (tmp == FP_NAN) {</div> +<div class="line"><a id="l01017" name="l01017"></a><span class="lineno"> 1017</span> aux.float_value = opa;</div> +<div class="line"><a id="l01018" name="l01018"></a><span class="lineno"> 1018</span> <span class="keywordflow">if</span> ((aux.binary_value &gt;&gt; 22) &amp; 0b1) { <span class="comment">// bit 22 (mantissa&#39;s MSB) is set -&gt; canonical (quiet) NAN</span></div> +<div class="line"><a id="l01019" name="l01019"></a><span class="lineno"> 1019</span> res |= CLASS_QNAN;</div> +<div class="line"><a id="l01020" name="l01020"></a><span class="lineno"> 1020</span> }</div> +<div class="line"><a id="l01021" name="l01021"></a><span class="lineno"> 1021</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l01022" name="l01022"></a><span class="lineno"> 1022</span> res |= CLASS_SNAN;</div> +<div class="line"><a id="l01023" name="l01023"></a><span class="lineno"> 1023</span> }</div> +<div class="line"><a id="l01024" name="l01024"></a><span class="lineno"> 1024</span> }</div> +<div class="line"><a id="l01025" name="l01025"></a><span class="lineno"> 1025</span> </div> +<div class="line"><a id="l01026" name="l01026"></a><span class="lineno"> 1026</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l01027" name="l01027"></a><span class="lineno"> 1027</span>}</div> +<div class="line"><a id="l01028" name="l01028"></a><span class="lineno"> 1028</span> </div> +<div class="line"><a id="l01029" name="l01029"></a><span class="lineno"> 1029</span> </div> +<div class="line"><a id="l01030" name="l01030"></a><span class="lineno"> 1030</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l01037" name="l01037"></a><span class="lineno"> 1037</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fdivs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l01038" name="l01038"></a><span class="lineno"> 1038</span> </div> +<div class="line"><a id="l01039" name="l01039"></a><span class="lineno"> 1039</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01040" name="l01040"></a><span class="lineno"> 1040</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01041" name="l01041"></a><span class="lineno"> 1041</span> </div> +<div class="line"><a id="l01042" name="l01042"></a><span class="lineno"> 1042</span> <span class="keywordtype">float</span> res = opa / opb;</div> +<div class="line"><a id="l01043" name="l01043"></a><span class="lineno"> 1043</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01044" name="l01044"></a><span class="lineno"> 1044</span>}</div> +<div class="line"><a id="l01045" name="l01045"></a><span class="lineno"> 1045</span> </div> +<div class="line"><a id="l01046" name="l01046"></a><span class="lineno"> 1046</span> </div> +<div class="line"><a id="l01047" name="l01047"></a><span class="lineno"> 1047</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l01053" name="l01053"></a><span class="lineno"> 1053</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsqrts(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l01054" name="l01054"></a><span class="lineno"> 1054</span> </div> +<div class="line"><a id="l01055" name="l01055"></a><span class="lineno"> 1055</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01056" name="l01056"></a><span class="lineno"> 1056</span> </div> +<div class="line"><a id="l01057" name="l01057"></a><span class="lineno"> 1057</span> <span class="keywordtype">float</span> res = sqrtf(opa);</div> +<div class="line"><a id="l01058" name="l01058"></a><span class="lineno"> 1058</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01059" name="l01059"></a><span class="lineno"> 1059</span>}</div> +<div class="line"><a id="l01060" name="l01060"></a><span class="lineno"> 1060</span> </div> +<div class="line"><a id="l01061" name="l01061"></a><span class="lineno"> 1061</span> </div> +<div class="line"><a id="l01062" name="l01062"></a><span class="lineno"> 1062</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l01072" name="l01072"></a><span class="lineno"> 1072</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l01073" name="l01073"></a><span class="lineno"> 1073</span> </div> +<div class="line"><a id="l01074" name="l01074"></a><span class="lineno"> 1074</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01075" name="l01075"></a><span class="lineno"> 1075</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01076" name="l01076"></a><span class="lineno"> 1076</span> <span class="keywordtype">float</span> opc = subnormal_flush(rs3);</div> +<div class="line"><a id="l01077" name="l01077"></a><span class="lineno"> 1077</span> </div> +<div class="line"><a id="l01078" name="l01078"></a><span class="lineno"> 1078</span> <span class="keywordtype">float</span> res = (opa * opb) + opc;</div> +<div class="line"><a id="l01079" name="l01079"></a><span class="lineno"> 1079</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01080" name="l01080"></a><span class="lineno"> 1080</span>}</div> +<div class="line"><a id="l01081" name="l01081"></a><span class="lineno"> 1081</span> </div> +<div class="line"><a id="l01082" name="l01082"></a><span class="lineno"> 1082</span> </div> +<div class="line"><a id="l01083" name="l01083"></a><span class="lineno"> 1083</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l01091" name="l01091"></a><span class="lineno"> 1091</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l01092" name="l01092"></a><span class="lineno"> 1092</span> </div> +<div class="line"><a id="l01093" name="l01093"></a><span class="lineno"> 1093</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01094" name="l01094"></a><span class="lineno"> 1094</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01095" name="l01095"></a><span class="lineno"> 1095</span> <span class="keywordtype">float</span> opc = subnormal_flush(rs3);</div> +<div class="line"><a id="l01096" name="l01096"></a><span class="lineno"> 1096</span> </div> +<div class="line"><a id="l01097" name="l01097"></a><span class="lineno"> 1097</span> <span class="keywordtype">float</span> res = (opa * opb) - opc;</div> +<div class="line"><a id="l01098" name="l01098"></a><span class="lineno"> 1098</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01099" name="l01099"></a><span class="lineno"> 1099</span>}</div> +<div class="line"><a id="l01100" name="l01100"></a><span class="lineno"> 1100</span> </div> +<div class="line"><a id="l01101" name="l01101"></a><span class="lineno"> 1101</span> </div> +<div class="line"><a id="l01102" name="l01102"></a><span class="lineno"> 1102</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l01110" name="l01110"></a><span class="lineno"> 1110</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fnmsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l01111" name="l01111"></a><span class="lineno"> 1111</span> </div> +<div class="line"><a id="l01112" name="l01112"></a><span class="lineno"> 1112</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01113" name="l01113"></a><span class="lineno"> 1113</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01114" name="l01114"></a><span class="lineno"> 1114</span> <span class="keywordtype">float</span> opc = subnormal_flush(rs3);</div> +<div class="line"><a id="l01115" name="l01115"></a><span class="lineno"> 1115</span> </div> +<div class="line"><a id="l01116" name="l01116"></a><span class="lineno"> 1116</span> <span class="keywordtype">float</span> res = -(opa * opb) + opc;</div> +<div class="line"><a id="l01117" name="l01117"></a><span class="lineno"> 1117</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01118" name="l01118"></a><span class="lineno"> 1118</span>}</div> +<div class="line"><a id="l01119" name="l01119"></a><span class="lineno"> 1119</span> </div> +<div class="line"><a id="l01120" name="l01120"></a><span class="lineno"> 1120</span> </div> +<div class="line"><a id="l01121" name="l01121"></a><span class="lineno"> 1121</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l01129" name="l01129"></a><span class="lineno"> 1129</span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fnmadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l01130" name="l01130"></a><span class="lineno"> 1130</span> </div> +<div class="line"><a id="l01131" name="l01131"></a><span class="lineno"> 1131</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01132" name="l01132"></a><span class="lineno"> 1132</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01133" name="l01133"></a><span class="lineno"> 1133</span> <span class="keywordtype">float</span> opc = subnormal_flush(rs3);</div> +<div class="line"><a id="l01134" name="l01134"></a><span class="lineno"> 1134</span> </div> +<div class="line"><a id="l01135" name="l01135"></a><span class="lineno"> 1135</span> <span class="keywordtype">float</span> res = -(opa * opb) - opc;</div> +<div class="line"><a id="l01136" name="l01136"></a><span class="lineno"> 1136</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01137" name="l01137"></a><span class="lineno"> 1137</span>}</div> +<div class="line"><a id="l01138" name="l01138"></a><span class="lineno"> 1138</span> </div> +<div class="line"><a id="l01139" name="l01139"></a><span class="lineno"> 1139</span> </div> +<div class="line"><a id="l01140" name="l01140"></a><span class="lineno"> 1140</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_zfinx_extension_intrinsics_h</span></div> +<div class="line"><a id="l01141" name="l01141"></a><span class="lineno"> 1141</span> </div> +<div class="ttc" id="aneorv32__cpu_8h_html_aab7a9f9cf608599f2b124dd499cb8418"><div class="ttname"><a href="neorv32__cpu_8h.html#aab7a9f9cf608599f2b124dd499cb8418">neorv32_cpu_csr_read</a></div><div class="ttdeci">uint32_t neorv32_cpu_csr_read(const int csr_id)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:174</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_afb5ef6e0b1a3e26570edfd8379490455"><div class="ttname"><a href="neorv32__cpu_8h.html#afb5ef6e0b1a3e26570edfd8379490455">neorv32_cpu_csr_write</a></div><div class="ttdeci">void neorv32_cpu_csr_write(const int csr_id, uint32_t data)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:188</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a">CSR_FFLAGS</a></div><div class="ttdeci">@ CSR_FFLAGS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:27</div></div> +<div class="ttc" id="aunionfloat__conv__t_html"><div class="ttname"><a href="unionfloat__conv__t.html">float_conv_t</a></div><div class="ttdef"><b>Definition</b> neorv32_zfinx_extension_intrinsics.h:78</div></div> +<div class="ttc" id="aunionfloat__conv__t_html_a59ad19d41b1d973a6bda9032e1937606"><div class="ttname"><a href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">float_conv_t::binary_value</a></div><div class="ttdeci">uint32_t binary_value</div><div class="ttdef"><b>Definition</b> neorv32_zfinx_extension_intrinsics.h:79</div></div> +<div class="ttc" id="aunionfloat__conv__t_html_a95f2e38b437bd8d4e8de7f61d7474788"><div class="ttname"><a href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_conv_t::float_value</a></div><div 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id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_e9ffd83269fb7f0c372f5ffbe8545008.html">floating_point_test</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Verification program for the NEORV32 'Zfinx' extension (floating-point in x registers) using pseudo-random data as input; compares results from hardware against pure-sw reference functions. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;float.h&gt;</code><br /> +<code>#include &lt;math.h&gt;</code><br /> +<code>#include &quot;<a class="el" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h_source.html">neorv32_zfinx_extension_intrinsics.h</a>&quot;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;(19200)</td></tr> +<tr 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id="r_a1d43b83ff6bc32390f33da19567e5e43"><td class="memItemLeft" align="right" valign="top"><a id="a1d43b83ff6bc32390f33da19567e5e43" name="a1d43b83ff6bc32390f33da19567e5e43"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>FLOAT32_SNAN</b>&#160;&#160;&#160;( (uint32_t)(0x7fa00000U) )</td></tr> +<tr class="separator:a1d43b83ff6bc32390f33da19567e5e43"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a45c163e2a1825fbcbf094edd8e6612cd" id="r_a45c163e2a1825fbcbf094edd8e6612cd"><td class="memItemLeft" align="right" valign="top"><a id="a45c163e2a1825fbcbf094edd8e6612cd" name="a45c163e2a1825fbcbf094edd8e6612cd"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>FLOAT32_PMIN</b>&#160;&#160;&#160;( (uint32_t)(0x00800000U) )</td></tr> +<tr class="separator:a45c163e2a1825fbcbf094edd8e6612cd"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a70a69778e78bc867439bc030e665d3c1" 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id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Verification program for the NEORV32 'Zfinx' extension (floating-point in x registers) using pseudo-random data as input; compares results from hardware against pure-sw reference functions. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a 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href="#a2d16b9e484b7af7897c7ae83f945ceca">&#9670;&#160;</a></span>RUN_ADDSUB_TESTS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define RUN_ADDSUB_TESTS&#160;&#160;&#160;(1)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a7e134923925fa24fd1090281c3a416c3" name="a7e134923925fa24fd1090281c3a416c3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7e134923925fa24fd1090281c3a416c3">&#9670;&#160;</a></span>RUN_CLASSIFY_TESTS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define RUN_CLASSIFY_TESTS&#160;&#160;&#160;(1)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a4ee0f6d28896a97d2c0cad866e77b874" name="a4ee0f6d28896a97d2c0cad866e77b874"></a> +<h2 class="memtitle"><span class="permalink"><a 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href="#a923de9c3e55322d85522740c0d0ff867">&#9670;&#160;</a></span>RUN_UNAVAIL_TESTS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define RUN_UNAVAIL_TESTS&#160;&#160;&#160;(1)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="a87f296d7594bb8178cf76f0c045b7013" name="a87f296d7594bb8178cf76f0c045b7013"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a87f296d7594bb8178cf76f0c045b7013">&#9670;&#160;</a></span>SILENT_MODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SILENT_MODE&#160;&#160;&#160;(1)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a73c70bd0fb6d695cb113eaeb50923e3e" name="a73c70bd0fb6d695cb113eaeb50923e3e"></a> +<h2 class="memtitle"><span class="permalink"><a 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class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function; test all available operations of the NEORV32 'Zfinx' extensions using floating-point * hardware intrinsics and software-only reference functions (emulation).</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the Zfinx CPU extension.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +<a id="a1740720aa8ce1a30fcf642be9140d203" name="a1740720aa8ce1a30fcf642be9140d203"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1740720aa8ce1a30fcf642be9140d203">&#9670;&#160;</a></span>print_report()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void print_report </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num_err</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print test report.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">num_err</td><td>Number or errors in this test. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a941ef8d24fd8e8fe4536626b2ce72410" name="a941ef8d24fd8e8fe4536626b2ce72410"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a941ef8d24fd8e8fe4536626b2ce72410">&#9670;&#160;</a></span>verify_result()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t verify_result </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>opa</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>opb</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>ref</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>res</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Verify results (software reference vs. actual hardware).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Test case number </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">opa</td><td>Operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">opb</td><td>Operand 2 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+<a href="#define-members">Macros</a> &#124; +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_zfinx_extension_intrinsics.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>"Intrinsic" library for the NEORV32 single-precision floating-point in x registers (Zfinx) extension +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;float.h&gt;</code><br /> +<code>#include &lt;math.h&gt;</code><br /> +</div> +<p><a href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union &#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point addition</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="ae41a0bf9d28c35f4d6db7177ccf8ee06" name="ae41a0bf9d28c35f4d6db7177ccf8ee06"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae41a0bf9d28c35f4d6db7177ccf8ee06">&#9670;&#160;</a></span>riscv_emulate_fclasss()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_emulate_fclasss </td> + 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class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point unsigned integer to float</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a292365fe41a7a661e61ae746306ba5e9" name="a292365fe41a7a661e61ae746306ba5e9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a292365fe41a7a661e61ae746306ba5e9">&#9670;&#160;</a></span>riscv_emulate_fcvt_ws()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t riscv_emulate_fcvt_ws </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point float to signed integer</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="aad9fc7337e09081cf8c5bff8c28776c8" name="aad9fc7337e09081cf8c5bff8c28776c8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aad9fc7337e09081cf8c5bff8c28776c8">&#9670;&#160;</a></span>riscv_emulate_fcvt_wus()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_emulate_fcvt_wus </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point float to unsigned integer</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="aeaf46a17b671278be2bf804159827a40" name="aeaf46a17b671278be2bf804159827a40"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aeaf46a17b671278be2bf804159827a40">&#9670;&#160;</a></span>riscv_emulate_fdivs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fdivs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point division</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a7cb3c6570b911cd1dfb7b6e798cc1d21" name="a7cb3c6570b911cd1dfb7b6e798cc1d21"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7cb3c6570b911cd1dfb7b6e798cc1d21">&#9670;&#160;</a></span>riscv_emulate_feqs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_emulate_feqs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point equal comparison</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="ac5fdef0607602fa0bdb93b3535fd709e" name="ac5fdef0607602fa0bdb93b3535fd709e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac5fdef0607602fa0bdb93b3535fd709e">&#9670;&#160;</a></span>riscv_emulate_fles()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_emulate_fles </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point less-than-or-equal comparison</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a2b802122d53a2ce517b3d39fec34d7e0" name="a2b802122d53a2ce517b3d39fec34d7e0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2b802122d53a2ce517b3d39fec34d7e0">&#9670;&#160;</a></span>riscv_emulate_flts()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_emulate_flts </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point less-than comparison</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a39212f2e2bb0f1752092a1732f93edf3" name="a39212f2e2bb0f1752092a1732f93edf3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a39212f2e2bb0f1752092a1732f93edf3">&#9670;&#160;</a></span>riscv_emulate_fmadds()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fmadds </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point fused multiply-add</p> +<dl class="section warning"><dt>Warning</dt><dd>This instruction is not supported!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs3</td><td>Source operand 3 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="af9b16a32d2bb13c8af5a678271d74889" name="af9b16a32d2bb13c8af5a678271d74889"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af9b16a32d2bb13c8af5a678271d74889">&#9670;&#160;</a></span>riscv_emulate_fmaxs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fmaxs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point maximum</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> +<p>&lt; Access as native float</p> +<p>&lt; Access in binary representation</p> + +</div> +</div> +<a id="a872cd30fb61190bd1ac719d25b01f5a3" name="a872cd30fb61190bd1ac719d25b01f5a3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a872cd30fb61190bd1ac719d25b01f5a3">&#9670;&#160;</a></span>riscv_emulate_fmins()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fmins </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point minimum</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> +<p>&lt; Access as native float</p> +<p>&lt; Access in binary representation</p> + +</div> +</div> +<a id="a05d0d5a8eb9422e93448efdeb679cabf" name="a05d0d5a8eb9422e93448efdeb679cabf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a05d0d5a8eb9422e93448efdeb679cabf">&#9670;&#160;</a></span>riscv_emulate_fmsubs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fmsubs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point fused multiply-sub</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs3</td><td>Source operand 3 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="ad43e8bdf4a6fbe229d22d24680f2be80" name="ad43e8bdf4a6fbe229d22d24680f2be80"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad43e8bdf4a6fbe229d22d24680f2be80">&#9670;&#160;</a></span>riscv_emulate_fmuls()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fmuls </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point multiplication</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="ac8bb4450b39854ab07839e8f3505361c" name="ac8bb4450b39854ab07839e8f3505361c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac8bb4450b39854ab07839e8f3505361c">&#9670;&#160;</a></span>riscv_emulate_fnmadds()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fnmadds </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point fused negated multiply-add</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs3</td><td>Source operand 3 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a833638b346722dfa9d7d5c8d60998ec8" name="a833638b346722dfa9d7d5c8d60998ec8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a833638b346722dfa9d7d5c8d60998ec8">&#9670;&#160;</a></span>riscv_emulate_fnmsubs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fnmsubs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point fused negated multiply-sub</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs3</td><td>Source operand 3 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a0c985e626ed1d69314f4e3a0f1f58624" name="a0c985e626ed1d69314f4e3a0f1f58624"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0c985e626ed1d69314f4e3a0f1f58624">&#9670;&#160;</a></span>riscv_emulate_fsgnjns()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fsgnjns </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point sign-injection NOT</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a12498d635f422f607b9b83facf3050dd" name="a12498d635f422f607b9b83facf3050dd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a12498d635f422f607b9b83facf3050dd">&#9670;&#160;</a></span>riscv_emulate_fsgnjs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fsgnjs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point sign-injection</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a98caf7f310820052ae96ce0f45e6cd26" name="a98caf7f310820052ae96ce0f45e6cd26"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a98caf7f310820052ae96ce0f45e6cd26">&#9670;&#160;</a></span>riscv_emulate_fsgnjxs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fsgnjxs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point sign-injection XOR</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a1ceb3450f1e5c62d3079cd0e93c03501" name="a1ceb3450f1e5c62d3079cd0e93c03501"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1ceb3450f1e5c62d3079cd0e93c03501">&#9670;&#160;</a></span>riscv_emulate_fsqrts()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fsqrts </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point square root</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="ace5d95b855ec1aa8eacdb5bbeea58197" name="ace5d95b855ec1aa8eacdb5bbeea58197"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ace5d95b855ec1aa8eacdb5bbeea58197">&#9670;&#160;</a></span>riscv_emulate_fsubs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float riscv_emulate_fsubs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Single-precision floating-point subtraction</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a4b151fcb252fc7b894f247f5af6a1809" name="a4b151fcb252fc7b894f247f5af6a1809"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4b151fcb252fc7b894f247f5af6a1809">&#9670;&#160;</a></span>riscv_intrinsic_fadds()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fadds </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point addition</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a3064a5c57b5f45d57c4d19eb798724f6" name="a3064a5c57b5f45d57c4d19eb798724f6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3064a5c57b5f45d57c4d19eb798724f6">&#9670;&#160;</a></span>riscv_intrinsic_fclasss()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_intrinsic_fclasss </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point number classification</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a2103eb86052f6f8e24a8a848ffc6528a" name="a2103eb86052f6f8e24a8a848ffc6528a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2103eb86052f6f8e24a8a848ffc6528a">&#9670;&#160;</a></span>riscv_intrinsic_fcvt_sw()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fcvt_sw </td> + <td>(</td> + <td class="paramtype">int32_t</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point convert signed integer to float</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a837b7330f9d568791687ae1384b8ef28" name="a837b7330f9d568791687ae1384b8ef28"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a837b7330f9d568791687ae1384b8ef28">&#9670;&#160;</a></span>riscv_intrinsic_fcvt_swu()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fcvt_swu </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point convert unsigned integer to float</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a523fa0fb6f521311c7f44692c586b3ee" name="a523fa0fb6f521311c7f44692c586b3ee"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a523fa0fb6f521311c7f44692c586b3ee">&#9670;&#160;</a></span>riscv_intrinsic_fcvt_ws()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">int32_t riscv_intrinsic_fcvt_ws </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point convert float to signed integer</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a3bc6ee3059a7e99b187c4ea5e217715b" name="a3bc6ee3059a7e99b187c4ea5e217715b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3bc6ee3059a7e99b187c4ea5e217715b">&#9670;&#160;</a></span>riscv_intrinsic_fcvt_wus()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_intrinsic_fcvt_wus </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point convert float to unsigned integer</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="ab6a9d15643e3085ff80c7883f183a42b" name="ab6a9d15643e3085ff80c7883f183a42b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab6a9d15643e3085ff80c7883f183a42b">&#9670;&#160;</a></span>riscv_intrinsic_fdivs()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fdivs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point division</p> +<dl class="section warning"><dt>Warning</dt><dd>This instruction is not supported and should raise an illegal instruction exception when executed.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="af4ddfae45807d4e41f758672ee14cf7b" name="af4ddfae45807d4e41f758672ee14cf7b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af4ddfae45807d4e41f758672ee14cf7b">&#9670;&#160;</a></span>riscv_intrinsic_feqs()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_intrinsic_feqs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point equal comparison</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="adb83fab39d91e9291da2b7b07830cf82" name="adb83fab39d91e9291da2b7b07830cf82"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adb83fab39d91e9291da2b7b07830cf82">&#9670;&#160;</a></span>riscv_intrinsic_fles()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_intrinsic_fles </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point less-than-or-equal comparison</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a85aa18294a58997db2c324184196669c" name="a85aa18294a58997db2c324184196669c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a85aa18294a58997db2c324184196669c">&#9670;&#160;</a></span>riscv_intrinsic_flts()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t riscv_intrinsic_flts </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point less-than comparison</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="abbdb403cdeef414fa2f867b702d5f6eb" name="abbdb403cdeef414fa2f867b702d5f6eb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abbdb403cdeef414fa2f867b702d5f6eb">&#9670;&#160;</a></span>riscv_intrinsic_fmadds()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fmadds </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point fused multiply-add</p> +<dl class="section warning"><dt>Warning</dt><dd>This instruction is not supported and should raise an illegal instruction exception when executed.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs3</td><td>Source operand 3 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a87c1ce499e5e43554cb0f407cf0d3f7f" name="a87c1ce499e5e43554cb0f407cf0d3f7f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a87c1ce499e5e43554cb0f407cf0d3f7f">&#9670;&#160;</a></span>riscv_intrinsic_fmaxs()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fmaxs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point maximum</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="abf7f9e466906306d9755fd5bc7946e3c" name="abf7f9e466906306d9755fd5bc7946e3c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abf7f9e466906306d9755fd5bc7946e3c">&#9670;&#160;</a></span>riscv_intrinsic_fmins()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fmins </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point minimum</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a03aba9c70c5286dacebaeb0ef5219cc9" name="a03aba9c70c5286dacebaeb0ef5219cc9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a03aba9c70c5286dacebaeb0ef5219cc9">&#9670;&#160;</a></span>riscv_intrinsic_fmsubs()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fmsubs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point fused multiply-sub</p> +<dl class="section warning"><dt>Warning</dt><dd>This instruction is not supported and should raise an illegal instruction exception when executed.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs3</td><td>Source operand 3 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a87a106e0d24a3183712e438d2bcbfa2d" name="a87a106e0d24a3183712e438d2bcbfa2d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a87a106e0d24a3183712e438d2bcbfa2d">&#9670;&#160;</a></span>riscv_intrinsic_fmuls()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fmuls </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point multiplication</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="aa6473bc2d2721b57277b83a3ae0cfdb6" name="aa6473bc2d2721b57277b83a3ae0cfdb6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa6473bc2d2721b57277b83a3ae0cfdb6">&#9670;&#160;</a></span>riscv_intrinsic_fnmadds()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fnmadds </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point fused negated multiply-add</p> +<dl class="section warning"><dt>Warning</dt><dd>This instruction is not supported and should raise an illegal instruction exception when executed.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs3</td><td>Source operand 3 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a639fc7bd75933888540e9cceb67221a0" name="a639fc7bd75933888540e9cceb67221a0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a639fc7bd75933888540e9cceb67221a0">&#9670;&#160;</a></span>riscv_intrinsic_fnmsubs()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fnmsubs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point fused negated multiply-sub</p> +<dl class="section warning"><dt>Warning</dt><dd>This instruction is not supported and should raise an illegal instruction exception when executed.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2 </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs3</td><td>Source operand 3 </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="aa4010772a986d03929ba7a43dfdcddd9" name="aa4010772a986d03929ba7a43dfdcddd9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa4010772a986d03929ba7a43dfdcddd9">&#9670;&#160;</a></span>riscv_intrinsic_fsgnjns()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fsgnjns </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point sign-injection NOT</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="aff3acd90bcfbda96945f95a0e0bae12b" name="aff3acd90bcfbda96945f95a0e0bae12b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aff3acd90bcfbda96945f95a0e0bae12b">&#9670;&#160;</a></span>riscv_intrinsic_fsgnjs()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fsgnjs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point sign-injection</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a2235d91cdac03bf8071003a5c59b9dd0" name="a2235d91cdac03bf8071003a5c59b9dd0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2235d91cdac03bf8071003a5c59b9dd0">&#9670;&#160;</a></span>riscv_intrinsic_fsgnjxs()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fsgnjxs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point sign-injection XOR</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a17e2b7a399c956d548a609185084ea3c" name="a17e2b7a399c956d548a609185084ea3c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a17e2b7a399c956d548a609185084ea3c">&#9670;&#160;</a></span>riscv_intrinsic_fsqrts()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fsqrts </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point square root</p> +<dl class="section warning"><dt>Warning</dt><dd>This instruction is not supported and should raise an illegal instruction exception when executed.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="af8473ba61abab8ae2e3ecbaf22d70e89" name="af8473ba61abab8ae2e3ecbaf22d70e89"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af8473ba61abab8ae2e3ecbaf22d70e89">&#9670;&#160;</a></span>riscv_intrinsic_fsubs()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">float riscv_intrinsic_fsubs </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Single-precision floating-point subtraction</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rs1</td><td>Source operand 1. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rs2</td><td>Source operand 2. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +<a id="a791f880781a1bcea1861471be7d1a851" name="a791f880781a1bcea1861471be7d1a851"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a791f880781a1bcea1861471be7d1a851">&#9670;&#160;</a></span>subnormal_flush()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">float subnormal_flush </td> + <td>(</td> + <td class="paramtype">float</td> <td class="paramname"><span class="paramname"><em>tmp</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Flush to zero if de-normal number.</p> +<dl class="section warning"><dt>Warning</dt><dd>Subnormal numbers are not supported yet! Flush them to zero.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">tmp</td><td>Source operand. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Result. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/floating__point__test_2neorv32__zfinx__extension__intrinsics_8h_source.html b/sw/floating__point__test_2neorv32__zfinx__extension__intrinsics_8h_source.html new file mode 100644 index 000000000..0b5df25d3 --- /dev/null +++ b/sw/floating__point__test_2neorv32__zfinx__extension__intrinsics_8h_source.html @@ -0,0 +1,985 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/floating_point_test/neorv32_zfinx_extension_intrinsics.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_e9ffd83269fb7f0c372f5ffbe8545008.html">floating_point_test</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_zfinx_extension_intrinsics.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// #################################################################################################</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// # &lt;&lt; NEORV32 - Intrinsics + Emulation Functions for the RISC-V &quot;Zfinx&quot; CPU extension &gt;&gt; #</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// # ********************************************************************************************* #</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// # The intrinsics provided by this library allow to use the hardware floating-point unit of the #</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// # RISC-V Zfinx CPU extension without the need for Zfinx support by the compiler / toolchain. #</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// # ********************************************************************************************* #</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// # BSD 3-Clause License #</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="comment">// # Copyright (c) 2024, Stephan Nolting. All rights reserved. #</span></div> +<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="comment">// # Redistribution and use in source and binary forms, with or without modification, are #</span></div> +<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="comment">// # permitted provided that the following conditions are met: #</span></div> +<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span><span class="comment">// # 1. Redistributions of source code must retain the above copyright notice, this list of #</span></div> +<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="comment">// # conditions and the following disclaimer. #</span></div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="comment">// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="comment">// # conditions and the following disclaimer in the documentation and/or other materials #</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="comment">// # provided with the distribution. #</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="comment">// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">// # endorse or promote products derived from this software without specific prior written #</span></div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span><span class="comment">// # permission. #</span></div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span><span class="comment">// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS &quot;AS IS&quot; AND ANY EXPRESS #</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span><span class="comment">// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #</span></div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span><span class="comment">// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #</span></div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span><span class="comment">// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #</span></div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span><span class="comment">// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #</span></div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span><span class="comment">// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #</span></div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span><span class="comment">// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #</span></div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span><span class="comment">// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #</span></div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span><span class="comment">// # OF THE POSSIBILITY OF SUCH DAMAGE. #</span></div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span><span class="comment">// # ********************************************************************************************* #</span></div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span><span class="comment">// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span><span class="comment">// #################################################################################################</span></div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> </div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> </div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="preprocessor">#ifndef neorv32_zfinx_extension_intrinsics_h</span></div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="preprocessor">#define neorv32_zfinx_extension_intrinsics_h</span></div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span><span class="preprocessor">#define __USE_GNU</span></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span><span class="preprocessor">#define _GNU_SOURCE</span></div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="preprocessor">#include &lt;float.h&gt;</span></div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="preprocessor">#include &lt;math.h&gt;</span></div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span> </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span><span class="preprocessor">#if defined __riscv_f || (__riscv_flen == 32)</span></div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span><span class="preprocessor"> #error Application programs using the Zfinx intrinsic library have to be compiled WITHOUT the &lt;F&gt; MARCH ISA attribute!</span></div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span> </div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span> </div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="keyword">typedef</span> <span class="keyword">union</span></div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span>{</div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span> uint32_t binary_value; </div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span> <span class="keywordtype">float</span> float_value; </div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span>} <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a>;</div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span> </div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span> </div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span><span class="comment">// Helper functions</span></div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span> </div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00091" data-start="{" data-end="}"> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a791f880781a1bcea1861471be7d1a851"> 91</a></span><span class="keywordtype">float</span> subnormal_flush(<span class="keywordtype">float</span> tmp) {</div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span> </div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span> <span class="keywordtype">float</span> res = tmp;</div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span> </div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span> <span class="comment">// flush to zero if subnormal</span></div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span> <span class="keywordflow">if</span> (fpclassify(tmp) == FP_SUBNORMAL) {</div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> <span class="keywordflow">if</span> (signbit(tmp) != 0) {</div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> res = -0.0f;</div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span> }</div> +<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span> res = +0.0f;</div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span> }</div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span> }</div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span> </div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span>}</div> +</div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span> </div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span> </div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span><span class="comment">// &quot;Intrinsics&quot;</span></div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span> </div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00120" data-start="{" data-end="}"> +<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a4b151fcb252fc7b894f247f5af6a1809"> 120</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span> </div> +<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span> </div> +<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0000000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"> 127</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"> 128</span>}</div> +</div> +<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span> </div> +<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span> </div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00138" data-start="{" data-end="}"> +<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#af8473ba61abab8ae2e3ecbaf22d70e89"> 138</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"> 139</span> </div> +<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"> 143</span> </div> +<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0000100, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span>}</div> +</div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span> </div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span> </div> +<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00156" data-start="{" data-end="}"> +<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a87a106e0d24a3183712e438d2bcbfa2d"> 156</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmuls(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span> </div> +<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"> 158</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"> 159</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span> </div> +<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0001000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"> 163</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span>}</div> +</div> +<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span> </div> +<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"> 166</span> </div> +<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00174" data-start="{" data-end="}"> +<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#abf7f9e466906306d9755fd5bc7946e3c"> 174</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmins(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span> </div> +<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span> </div> +<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010100, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"> 182</span>}</div> +</div> +<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"> 183</span> </div> +<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"> 184</span> </div> +<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"> 185</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00192" data-start="{" data-end="}"> +<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a87c1ce499e5e43554cb0f407cf0d3f7f"> 192</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmaxs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span> </div> +<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span> </div> +<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010100, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b001, 0b1010011);</div> +<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"> 200</span>}</div> +</div> +<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"> 201</span> </div> +<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span> </div> +<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00209" data-start="{" data-end="}"> +<div class="line"><a id="l00209" name="l00209"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a3bc6ee3059a7e99b187c4ea5e217715b"> 209</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_wus(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"> 210</span> </div> +<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"> 211</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa;</div> +<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"> 212</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"> 213</span> </div> +<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"> 214</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R2_TYPE(0b1100000, 0b00001, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"> 215</span>}</div> +</div> +<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"> 216</span> </div> +<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"> 217</span> </div> +<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00224" data-start="{" data-end="}"> +<div class="line"><a id="l00224" name="l00224"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a523fa0fb6f521311c7f44692c586b3ee"> 224</a></span><span class="keyword">inline</span> int32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_ws(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00225" name="l00225"></a><span class="lineno"> 225</span> </div> +<div class="line"><a id="l00226" name="l00226"></a><span class="lineno"> 226</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa;</div> +<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"> 227</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span> </div> +<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span> <span class="keywordflow">return</span> (int32_t)CUSTOM_INSTR_R2_TYPE(0b1100000, 0b00000, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span>}</div> +</div> +<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span> </div> +<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span> </div> +<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00239" data-start="{" data-end="}"> +<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a837b7330f9d568791687ae1384b8ef28"> 239</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fcvt_swu(uint32_t rs1) {</div> +<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"> 240</span> </div> +<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"> 241</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> res;</div> +<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"> 242</span> </div> +<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"> 243</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R2_TYPE(0b1101000, 0b00001, rs1, 0b000, 0b1010011);</div> +<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"> 244</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00245" name="l00245"></a><span class="lineno"> 245</span>}</div> +</div> +<div class="line"><a id="l00246" name="l00246"></a><span class="lineno"> 246</span> </div> +<div class="line"><a id="l00247" name="l00247"></a><span class="lineno"> 247</span> </div> +<div class="line"><a id="l00248" name="l00248"></a><span class="lineno"> 248</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00254" data-start="{" data-end="}"> +<div class="line"><a id="l00254" name="l00254"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a2103eb86052f6f8e24a8a848ffc6528a"> 254</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fcvt_sw(int32_t rs1) {</div> +<div class="line"><a id="l00255" name="l00255"></a><span class="lineno"> 255</span> </div> +<div class="line"><a id="l00256" name="l00256"></a><span class="lineno"> 256</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> res;</div> +<div class="line"><a id="l00257" name="l00257"></a><span class="lineno"> 257</span> </div> +<div class="line"><a id="l00258" name="l00258"></a><span class="lineno"> 258</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R2_TYPE(0b1101000, 0b00000, rs1, 0b000, 0b1010011);</div> +<div class="line"><a id="l00259" name="l00259"></a><span class="lineno"> 259</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00260" name="l00260"></a><span class="lineno"> 260</span>}</div> +</div> +<div class="line"><a id="l00261" name="l00261"></a><span class="lineno"> 261</span> </div> +<div class="line"><a id="l00262" name="l00262"></a><span class="lineno"> 262</span> </div> +<div class="line"><a id="l00263" name="l00263"></a><span class="lineno"> 263</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00270" data-start="{" data-end="}"> +<div class="line"><a id="l00270" name="l00270"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#af4ddfae45807d4e41f758672ee14cf7b"> 270</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_feqs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00271" name="l00271"></a><span class="lineno"> 271</span> </div> +<div class="line"><a id="l00272" name="l00272"></a><span class="lineno"> 272</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb;</div> +<div class="line"><a id="l00273" name="l00273"></a><span class="lineno"> 273</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00274" name="l00274"></a><span class="lineno"> 274</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00275" name="l00275"></a><span class="lineno"> 275</span> </div> +<div class="line"><a id="l00276" name="l00276"></a><span class="lineno"> 276</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R3_TYPE(0b1010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b010, 0b1010011);</div> +<div class="line"><a id="l00277" name="l00277"></a><span class="lineno"> 277</span>}</div> +</div> +<div class="line"><a id="l00278" name="l00278"></a><span class="lineno"> 278</span> </div> +<div class="line"><a id="l00279" name="l00279"></a><span class="lineno"> 279</span> </div> +<div class="line"><a id="l00280" name="l00280"></a><span class="lineno"> 280</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00287" data-start="{" data-end="}"> +<div class="line"><a id="l00287" name="l00287"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a85aa18294a58997db2c324184196669c"> 287</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_flts(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00288" name="l00288"></a><span class="lineno"> 288</span> </div> +<div class="line"><a id="l00289" name="l00289"></a><span class="lineno"> 289</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb;</div> +<div class="line"><a id="l00290" name="l00290"></a><span class="lineno"> 290</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00291" name="l00291"></a><span class="lineno"> 291</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00292" name="l00292"></a><span class="lineno"> 292</span> </div> +<div class="line"><a id="l00293" name="l00293"></a><span class="lineno"> 293</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R3_TYPE(0b1010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b001, 0b1010011);</div> +<div class="line"><a id="l00294" name="l00294"></a><span class="lineno"> 294</span>}</div> +</div> +<div class="line"><a id="l00295" name="l00295"></a><span class="lineno"> 295</span> </div> +<div class="line"><a id="l00296" name="l00296"></a><span class="lineno"> 296</span> </div> +<div class="line"><a id="l00297" name="l00297"></a><span class="lineno"> 297</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00304" data-start="{" data-end="}"> +<div class="line"><a id="l00304" name="l00304"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#adb83fab39d91e9291da2b7b07830cf82"> 304</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fles(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00305" name="l00305"></a><span class="lineno"> 305</span> </div> +<div class="line"><a id="l00306" name="l00306"></a><span class="lineno"> 306</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb;</div> +<div class="line"><a id="l00307" name="l00307"></a><span class="lineno"> 307</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00308" name="l00308"></a><span class="lineno"> 308</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00309" name="l00309"></a><span class="lineno"> 309</span> </div> +<div class="line"><a id="l00310" name="l00310"></a><span class="lineno"> 310</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R3_TYPE(0b1010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00311" name="l00311"></a><span class="lineno"> 311</span>}</div> +</div> +<div class="line"><a id="l00312" name="l00312"></a><span class="lineno"> 312</span> </div> +<div class="line"><a id="l00313" name="l00313"></a><span class="lineno"> 313</span> </div> +<div class="line"><a id="l00314" name="l00314"></a><span class="lineno"> 314</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00321" data-start="{" data-end="}"> +<div class="line"><a id="l00321" name="l00321"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#aff3acd90bcfbda96945f95a0e0bae12b"> 321</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsgnjs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00322" name="l00322"></a><span class="lineno"> 322</span> </div> +<div class="line"><a id="l00323" name="l00323"></a><span class="lineno"> 323</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00324" name="l00324"></a><span class="lineno"> 324</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00325" name="l00325"></a><span class="lineno"> 325</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00326" name="l00326"></a><span class="lineno"> 326</span> </div> +<div class="line"><a id="l00327" name="l00327"></a><span class="lineno"> 327</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00328" name="l00328"></a><span class="lineno"> 328</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00329" name="l00329"></a><span class="lineno"> 329</span>}</div> +</div> +<div class="line"><a id="l00330" name="l00330"></a><span class="lineno"> 330</span> </div> +<div class="line"><a id="l00331" name="l00331"></a><span class="lineno"> 331</span> </div> +<div class="line"><a id="l00332" name="l00332"></a><span class="lineno"> 332</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00339" data-start="{" data-end="}"> +<div class="line"><a id="l00339" name="l00339"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#aa4010772a986d03929ba7a43dfdcddd9"> 339</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsgnjns(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00340" name="l00340"></a><span class="lineno"> 340</span> </div> +<div class="line"><a id="l00341" name="l00341"></a><span class="lineno"> 341</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00342" name="l00342"></a><span class="lineno"> 342</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00343" name="l00343"></a><span class="lineno"> 343</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00344" name="l00344"></a><span class="lineno"> 344</span> </div> +<div class="line"><a id="l00345" name="l00345"></a><span class="lineno"> 345</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b001, 0b1010011);</div> +<div class="line"><a id="l00346" name="l00346"></a><span class="lineno"> 346</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00347" name="l00347"></a><span class="lineno"> 347</span>}</div> +</div> +<div class="line"><a id="l00348" name="l00348"></a><span class="lineno"> 348</span> </div> +<div class="line"><a id="l00349" name="l00349"></a><span class="lineno"> 349</span> </div> +<div class="line"><a id="l00350" name="l00350"></a><span class="lineno"> 350</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00357" data-start="{" data-end="}"> +<div class="line"><a id="l00357" name="l00357"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a2235d91cdac03bf8071003a5c59b9dd0"> 357</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsgnjxs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00358" name="l00358"></a><span class="lineno"> 358</span> </div> +<div class="line"><a id="l00359" name="l00359"></a><span class="lineno"> 359</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00360" name="l00360"></a><span class="lineno"> 360</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00361" name="l00361"></a><span class="lineno"> 361</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00362" name="l00362"></a><span class="lineno"> 362</span> </div> +<div class="line"><a id="l00363" name="l00363"></a><span class="lineno"> 363</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0010000, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b010, 0b1010011);</div> +<div class="line"><a id="l00364" name="l00364"></a><span class="lineno"> 364</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00365" name="l00365"></a><span class="lineno"> 365</span>}</div> +</div> +<div class="line"><a id="l00366" name="l00366"></a><span class="lineno"> 366</span> </div> +<div class="line"><a id="l00367" name="l00367"></a><span class="lineno"> 367</span> </div> +<div class="line"><a id="l00368" name="l00368"></a><span class="lineno"> 368</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00374" data-start="{" data-end="}"> +<div class="line"><a id="l00374" name="l00374"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a3064a5c57b5f45d57c4d19eb798724f6"> 374</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fclasss(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00375" name="l00375"></a><span class="lineno"> 375</span> </div> +<div class="line"><a id="l00376" name="l00376"></a><span class="lineno"> 376</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa;</div> +<div class="line"><a id="l00377" name="l00377"></a><span class="lineno"> 377</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00378" name="l00378"></a><span class="lineno"> 378</span> </div> +<div class="line"><a id="l00379" name="l00379"></a><span class="lineno"> 379</span> <span class="keywordflow">return</span> CUSTOM_INSTR_R2_TYPE(0b1110000, 0b00000, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b001, 0b1010011);</div> +<div class="line"><a id="l00380" name="l00380"></a><span class="lineno"> 380</span>}</div> +</div> +<div class="line"><a id="l00381" name="l00381"></a><span class="lineno"> 381</span> </div> +<div class="line"><a id="l00382" name="l00382"></a><span class="lineno"> 382</span> </div> +<div class="line"><a id="l00383" name="l00383"></a><span class="lineno"> 383</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00384" name="l00384"></a><span class="lineno"> 384</span><span class="comment">// !!! UNSUPPORTED instructions !!!</span></div> +<div class="line"><a id="l00385" name="l00385"></a><span class="lineno"> 385</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00386" name="l00386"></a><span class="lineno"> 386</span> </div> +<div class="line"><a id="l00387" name="l00387"></a><span class="lineno"> 387</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00396" data-start="{" data-end="}"> +<div class="line"><a id="l00396" name="l00396"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#ab6a9d15643e3085ff80c7883f183a42b"> 396</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fdivs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00397" name="l00397"></a><span class="lineno"> 397</span> </div> +<div class="line"><a id="l00398" name="l00398"></a><span class="lineno"> 398</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, res;</div> +<div class="line"><a id="l00399" name="l00399"></a><span class="lineno"> 399</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00400" name="l00400"></a><span class="lineno"> 400</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00401" name="l00401"></a><span class="lineno"> 401</span> </div> +<div class="line"><a id="l00402" name="l00402"></a><span class="lineno"> 402</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R3_TYPE(0b0001100, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00403" name="l00403"></a><span class="lineno"> 403</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00404" name="l00404"></a><span class="lineno"> 404</span>}</div> +</div> +<div class="line"><a id="l00405" name="l00405"></a><span class="lineno"> 405</span> </div> +<div class="line"><a id="l00406" name="l00406"></a><span class="lineno"> 406</span> </div> +<div class="line"><a id="l00407" name="l00407"></a><span class="lineno"> 407</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00415" data-start="{" data-end="}"> +<div class="line"><a id="l00415" name="l00415"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a17e2b7a399c956d548a609185084ea3c"> 415</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fsqrts(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00416" name="l00416"></a><span class="lineno"> 416</span> </div> +<div class="line"><a id="l00417" name="l00417"></a><span class="lineno"> 417</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, res;</div> +<div class="line"><a id="l00418" name="l00418"></a><span class="lineno"> 418</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00419" name="l00419"></a><span class="lineno"> 419</span> </div> +<div class="line"><a id="l00420" name="l00420"></a><span class="lineno"> 420</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R2_TYPE(0b0101100, 0b00000, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1010011);</div> +<div class="line"><a id="l00421" name="l00421"></a><span class="lineno"> 421</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00422" name="l00422"></a><span class="lineno"> 422</span>}</div> +</div> +<div class="line"><a id="l00423" name="l00423"></a><span class="lineno"> 423</span> </div> +<div class="line"><a id="l00424" name="l00424"></a><span class="lineno"> 424</span> </div> +<div class="line"><a id="l00425" name="l00425"></a><span class="lineno"> 425</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00435" data-start="{" data-end="}"> +<div class="line"><a id="l00435" name="l00435"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#abbdb403cdeef414fa2f867b702d5f6eb"> 435</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l00436" name="l00436"></a><span class="lineno"> 436</span> </div> +<div class="line"><a id="l00437" name="l00437"></a><span class="lineno"> 437</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, opc, res;</div> +<div class="line"><a id="l00438" name="l00438"></a><span class="lineno"> 438</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00439" name="l00439"></a><span class="lineno"> 439</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00440" name="l00440"></a><span class="lineno"> 440</span> opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs3;</div> +<div class="line"><a id="l00441" name="l00441"></a><span class="lineno"> 441</span> </div> +<div class="line"><a id="l00442" name="l00442"></a><span class="lineno"> 442</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R4_TYPE(opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1000011);</div> +<div class="line"><a id="l00443" name="l00443"></a><span class="lineno"> 443</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00444" name="l00444"></a><span class="lineno"> 444</span>}</div> +</div> +<div class="line"><a id="l00445" name="l00445"></a><span class="lineno"> 445</span> </div> +<div class="line"><a id="l00446" name="l00446"></a><span class="lineno"> 446</span> </div> +<div class="line"><a id="l00447" name="l00447"></a><span class="lineno"> 447</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00457" data-start="{" data-end="}"> +<div class="line"><a id="l00457" name="l00457"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a03aba9c70c5286dacebaeb0ef5219cc9"> 457</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fmsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l00458" name="l00458"></a><span class="lineno"> 458</span> </div> +<div class="line"><a id="l00459" name="l00459"></a><span class="lineno"> 459</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, opc, res;</div> +<div class="line"><a id="l00460" name="l00460"></a><span class="lineno"> 460</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00461" name="l00461"></a><span class="lineno"> 461</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00462" name="l00462"></a><span class="lineno"> 462</span> opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs3;</div> +<div class="line"><a id="l00463" name="l00463"></a><span class="lineno"> 463</span> </div> +<div class="line"><a id="l00464" name="l00464"></a><span class="lineno"> 464</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R4_TYPE(opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1000111);</div> +<div class="line"><a id="l00465" name="l00465"></a><span class="lineno"> 465</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00466" name="l00466"></a><span class="lineno"> 466</span>}</div> +</div> +<div class="line"><a id="l00467" name="l00467"></a><span class="lineno"> 467</span> </div> +<div class="line"><a id="l00468" name="l00468"></a><span class="lineno"> 468</span> </div> +<div class="line"><a id="l00469" name="l00469"></a><span class="lineno"> 469</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00479" data-start="{" data-end="}"> +<div class="line"><a id="l00479" name="l00479"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a639fc7bd75933888540e9cceb67221a0"> 479</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fnmsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l00480" name="l00480"></a><span class="lineno"> 480</span> </div> +<div class="line"><a id="l00481" name="l00481"></a><span class="lineno"> 481</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, opc, res;</div> +<div class="line"><a id="l00482" name="l00482"></a><span class="lineno"> 482</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00483" name="l00483"></a><span class="lineno"> 483</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00484" name="l00484"></a><span class="lineno"> 484</span> opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs3;</div> +<div class="line"><a id="l00485" name="l00485"></a><span class="lineno"> 485</span> </div> +<div class="line"><a id="l00486" name="l00486"></a><span class="lineno"> 486</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R4_TYPE(opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1001011);</div> +<div class="line"><a id="l00487" name="l00487"></a><span class="lineno"> 487</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00488" name="l00488"></a><span class="lineno"> 488</span>}</div> +</div> +<div class="line"><a id="l00489" name="l00489"></a><span class="lineno"> 489</span> </div> +<div class="line"><a id="l00490" name="l00490"></a><span class="lineno"> 490</span> </div> +<div class="line"><a id="l00491" name="l00491"></a><span class="lineno"> 491</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00501" data-start="{" data-end="}"> +<div class="line"><a id="l00501" name="l00501"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#aa6473bc2d2721b57277b83a3ae0cfdb6"> 501</a></span><span class="keyword">inline</span> <span class="keywordtype">float</span> __attribute__ ((always_inline)) riscv_intrinsic_fnmadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l00502" name="l00502"></a><span class="lineno"> 502</span> </div> +<div class="line"><a id="l00503" name="l00503"></a><span class="lineno"> 503</span> <a class="code hl_union" href="unionfloat__conv__t.html">float_conv_t</a> opa, opb, opc, res;</div> +<div class="line"><a id="l00504" name="l00504"></a><span class="lineno"> 504</span> opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs1;</div> +<div class="line"><a id="l00505" name="l00505"></a><span class="lineno"> 505</span> opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs2;</div> +<div class="line"><a id="l00506" name="l00506"></a><span class="lineno"> 506</span> opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a> = rs3;</div> +<div class="line"><a id="l00507" name="l00507"></a><span class="lineno"> 507</span> </div> +<div class="line"><a id="l00508" name="l00508"></a><span class="lineno"> 508</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a> = CUSTOM_INSTR_R4_TYPE(opc.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opb.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, opa.<a class="code hl_variable" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">binary_value</a>, 0b000, 0b1001111);</div> +<div class="line"><a id="l00509" name="l00509"></a><span class="lineno"> 509</span> <span class="keywordflow">return</span> res.<a class="code hl_variable" href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a>;</div> +<div class="line"><a id="l00510" name="l00510"></a><span class="lineno"> 510</span>}</div> +</div> +<div class="line"><a id="l00511" name="l00511"></a><span class="lineno"> 511</span> </div> +<div class="line"><a id="l00512" name="l00512"></a><span class="lineno"> 512</span> </div> +<div class="line"><a id="l00513" name="l00513"></a><span class="lineno"> 513</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00514" name="l00514"></a><span class="lineno"> 514</span><span class="comment">// Emulation functions</span></div> +<div class="line"><a id="l00515" name="l00515"></a><span class="lineno"> 515</span><span class="comment">// ################################################################################################</span></div> +<div class="line"><a id="l00516" name="l00516"></a><span class="lineno"> 516</span> </div> +<div class="line"><a id="l00517" name="l00517"></a><span class="lineno"> 517</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00524" data-start="{" data-end="}"> +<div class="line"><a id="l00524" name="l00524"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a9d676567276439875c9b1a15b892b555"> 524</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00525" name="l00525"></a><span class="lineno"> 525</span> </div> +<div class="line"><a id="l00526" name="l00526"></a><span class="lineno"> 526</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00527" name="l00527"></a><span class="lineno"> 527</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00528" name="l00528"></a><span class="lineno"> 528</span> </div> +<div class="line"><a id="l00529" name="l00529"></a><span class="lineno"> 529</span> <span class="keywordtype">float</span> res = opa + opb;</div> +<div class="line"><a id="l00530" name="l00530"></a><span class="lineno"> 530</span> </div> +<div class="line"><a id="l00531" name="l00531"></a><span class="lineno"> 531</span> <span class="comment">// make NAN canonical</span></div> +<div class="line"><a id="l00532" name="l00532"></a><span class="lineno"> 532</span> <span class="keywordflow">if</span> (fpclassify(res) == FP_NAN) {</div> +<div class="line"><a id="l00533" name="l00533"></a><span class="lineno"> 533</span> res = NAN;</div> +<div class="line"><a id="l00534" name="l00534"></a><span class="lineno"> 534</span> }</div> +<div class="line"><a id="l00535" name="l00535"></a><span class="lineno"> 535</span> </div> +<div class="line"><a id="l00536" name="l00536"></a><span class="lineno"> 536</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l00537" name="l00537"></a><span class="lineno"> 537</span>}</div> +</div> +<div class="line"><a id="l00538" name="l00538"></a><span class="lineno"> 538</span> </div> +<div class="line"><a id="l00539" name="l00539"></a><span class="lineno"> 539</span> </div> +<div class="line"><a id="l00540" name="l00540"></a><span class="lineno"> 540</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00547" data-start="{" data-end="}"> +<div class="line"><a id="l00547" name="l00547"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#ace5d95b855ec1aa8eacdb5bbeea58197"> 547</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00548" name="l00548"></a><span class="lineno"> 548</span> </div> +<div class="line"><a id="l00549" name="l00549"></a><span class="lineno"> 549</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00550" name="l00550"></a><span class="lineno"> 550</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00551" name="l00551"></a><span class="lineno"> 551</span> </div> +<div class="line"><a id="l00552" name="l00552"></a><span class="lineno"> 552</span> <span class="keywordtype">float</span> res = opa - opb;</div> +<div class="line"><a id="l00553" name="l00553"></a><span class="lineno"> 553</span> </div> +<div class="line"><a id="l00554" name="l00554"></a><span class="lineno"> 554</span> <span class="comment">// make NAN canonical</span></div> +<div class="line"><a id="l00555" name="l00555"></a><span class="lineno"> 555</span> <span class="keywordflow">if</span> (fpclassify(res) == FP_NAN) {</div> +<div class="line"><a id="l00556" name="l00556"></a><span class="lineno"> 556</span> res = NAN;</div> +<div class="line"><a id="l00557" name="l00557"></a><span class="lineno"> 557</span> }</div> +<div class="line"><a id="l00558" name="l00558"></a><span class="lineno"> 558</span> </div> +<div class="line"><a id="l00559" name="l00559"></a><span class="lineno"> 559</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l00560" name="l00560"></a><span class="lineno"> 560</span>}</div> +</div> +<div class="line"><a id="l00561" name="l00561"></a><span class="lineno"> 561</span> </div> +<div class="line"><a id="l00562" name="l00562"></a><span class="lineno"> 562</span> </div> +<div class="line"><a id="l00563" name="l00563"></a><span class="lineno"> 563</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00570" data-start="{" data-end="}"> +<div class="line"><a id="l00570" name="l00570"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#ad43e8bdf4a6fbe229d22d24680f2be80"> 570</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmuls(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00571" name="l00571"></a><span class="lineno"> 571</span> </div> +<div class="line"><a id="l00572" name="l00572"></a><span class="lineno"> 572</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00573" name="l00573"></a><span class="lineno"> 573</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00574" name="l00574"></a><span class="lineno"> 574</span> </div> +<div class="line"><a id="l00575" name="l00575"></a><span class="lineno"> 575</span> <span class="keywordtype">float</span> res = opa * opb;</div> +<div class="line"><a id="l00576" name="l00576"></a><span class="lineno"> 576</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l00577" name="l00577"></a><span class="lineno"> 577</span>}</div> +</div> +<div class="line"><a id="l00578" name="l00578"></a><span class="lineno"> 578</span> </div> +<div class="line"><a id="l00579" name="l00579"></a><span class="lineno"> 579</span> </div> +<div class="line"><a id="l00580" name="l00580"></a><span class="lineno"> 580</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00587" data-start="{" data-end="}"> +<div class="line"><a id="l00587" name="l00587"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a872cd30fb61190bd1ac719d25b01f5a3"> 587</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmins(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00588" name="l00588"></a><span class="lineno"> 588</span> </div> +<div class="line"><a id="l00589" name="l00589"></a><span class="lineno"> 589</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00590" name="l00590"></a><span class="lineno"> 590</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00591" name="l00591"></a><span class="lineno"> 591</span> </div> +<div class="line"><a id="l00592" name="l00592"></a><span class="lineno"> 592</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00593" name="l00593"></a><span class="lineno"> 593</span> uint32_t binary_value; </div> +<div class="line"><a id="l00594" name="l00594"></a><span class="lineno"> 594</span> <span class="keywordtype">float</span> float_value; </div> +<div class="line"><a id="l00595" name="l00595"></a><span class="lineno"> 595</span> } tmp_a, tmp_b;</div> +<div class="line"><a id="l00596" name="l00596"></a><span class="lineno"> 596</span> </div> +<div class="line"><a id="l00597" name="l00597"></a><span class="lineno"> 597</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) &amp;&amp; (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00598" name="l00598"></a><span class="lineno"> 598</span> <span class="keywordflow">return</span> nanf(<span class="stringliteral">&quot;&quot;</span>);</div> +<div class="line"><a id="l00599" name="l00599"></a><span class="lineno"> 599</span> }</div> +<div class="line"><a id="l00600" name="l00600"></a><span class="lineno"> 600</span> </div> +<div class="line"><a id="l00601" name="l00601"></a><span class="lineno"> 601</span> <span class="keywordflow">if</span> (fpclassify(opa) == FP_NAN) {</div> +<div class="line"><a id="l00602" name="l00602"></a><span class="lineno"> 602</span> <span class="keywordflow">return</span> opb;</div> +<div class="line"><a id="l00603" name="l00603"></a><span class="lineno"> 603</span> }</div> +<div class="line"><a id="l00604" name="l00604"></a><span class="lineno"> 604</span> </div> +<div class="line"><a id="l00605" name="l00605"></a><span class="lineno"> 605</span> <span class="keywordflow">if</span> (fpclassify(opb) == FP_NAN) {</div> +<div class="line"><a id="l00606" name="l00606"></a><span class="lineno"> 606</span> <span class="keywordflow">return</span> opa;</div> +<div class="line"><a id="l00607" name="l00607"></a><span class="lineno"> 607</span> }</div> +<div class="line"><a id="l00608" name="l00608"></a><span class="lineno"> 608</span> </div> +<div class="line"><a id="l00609" name="l00609"></a><span class="lineno"> 609</span> <span class="comment">// RISC-V spec: -0 &lt; +0</span></div> +<div class="line"><a id="l00610" name="l00610"></a><span class="lineno"> 610</span> tmp_a.float_value = opa;</div> +<div class="line"><a id="l00611" name="l00611"></a><span class="lineno"> 611</span> tmp_b.float_value = opb;</div> +<div class="line"><a id="l00612" name="l00612"></a><span class="lineno"> 612</span> <span class="keywordflow">if</span> (((tmp_a.binary_value == 0x80000000) &amp;&amp; (tmp_b.binary_value == 0x00000000)) ||</div> +<div class="line"><a id="l00613" name="l00613"></a><span class="lineno"> 613</span> ((tmp_a.binary_value == 0x00000000) &amp;&amp; (tmp_b.binary_value == 0x80000000))) {</div> +<div class="line"><a id="l00614" name="l00614"></a><span class="lineno"> 614</span> <span class="keywordflow">return</span> -0.0f;</div> +<div class="line"><a id="l00615" name="l00615"></a><span class="lineno"> 615</span> }</div> +<div class="line"><a id="l00616" name="l00616"></a><span class="lineno"> 616</span> </div> +<div class="line"><a id="l00617" name="l00617"></a><span class="lineno"> 617</span> <span class="keywordflow">return</span> fmin(opa, opb);</div> +<div class="line"><a id="l00618" name="l00618"></a><span class="lineno"> 618</span>}</div> +</div> +<div class="line"><a id="l00619" name="l00619"></a><span class="lineno"> 619</span> </div> +<div class="line"><a id="l00620" name="l00620"></a><span class="lineno"> 620</span> </div> +<div class="line"><a id="l00621" name="l00621"></a><span class="lineno"> 621</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00628" data-start="{" data-end="}"> +<div class="line"><a id="l00628" name="l00628"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#af9b16a32d2bb13c8af5a678271d74889"> 628</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmaxs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00629" name="l00629"></a><span class="lineno"> 629</span> </div> +<div class="line"><a id="l00630" name="l00630"></a><span class="lineno"> 630</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00631" name="l00631"></a><span class="lineno"> 631</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00632" name="l00632"></a><span class="lineno"> 632</span> </div> +<div class="line"><a id="l00633" name="l00633"></a><span class="lineno"> 633</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00634" name="l00634"></a><span class="lineno"> 634</span> uint32_t binary_value; </div> +<div class="line"><a id="l00635" name="l00635"></a><span class="lineno"> 635</span> <span class="keywordtype">float</span> float_value; </div> +<div class="line"><a id="l00636" name="l00636"></a><span class="lineno"> 636</span> } tmp_a, tmp_b;</div> +<div class="line"><a id="l00637" name="l00637"></a><span class="lineno"> 637</span> </div> +<div class="line"><a id="l00638" name="l00638"></a><span class="lineno"> 638</span> </div> +<div class="line"><a id="l00639" name="l00639"></a><span class="lineno"> 639</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) &amp;&amp; (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00640" name="l00640"></a><span class="lineno"> 640</span> <span class="keywordflow">return</span> nanf(<span class="stringliteral">&quot;&quot;</span>);</div> +<div class="line"><a id="l00641" name="l00641"></a><span class="lineno"> 641</span> }</div> +<div class="line"><a id="l00642" name="l00642"></a><span class="lineno"> 642</span> </div> +<div class="line"><a id="l00643" name="l00643"></a><span class="lineno"> 643</span> <span class="keywordflow">if</span> (fpclassify(opa) == FP_NAN) {</div> +<div class="line"><a id="l00644" name="l00644"></a><span class="lineno"> 644</span> <span class="keywordflow">return</span> opb;</div> +<div class="line"><a id="l00645" name="l00645"></a><span class="lineno"> 645</span> }</div> +<div class="line"><a id="l00646" name="l00646"></a><span class="lineno"> 646</span> </div> +<div class="line"><a id="l00647" name="l00647"></a><span class="lineno"> 647</span> <span class="keywordflow">if</span> (fpclassify(opb) == FP_NAN) {</div> +<div class="line"><a id="l00648" name="l00648"></a><span class="lineno"> 648</span> <span class="keywordflow">return</span> opa;</div> +<div class="line"><a id="l00649" name="l00649"></a><span class="lineno"> 649</span> }</div> +<div class="line"><a id="l00650" name="l00650"></a><span class="lineno"> 650</span> </div> +<div class="line"><a id="l00651" name="l00651"></a><span class="lineno"> 651</span> <span class="comment">// RISC-V spec: -0 &lt; +0</span></div> +<div class="line"><a id="l00652" name="l00652"></a><span class="lineno"> 652</span> tmp_a.float_value = opa;</div> +<div class="line"><a id="l00653" name="l00653"></a><span class="lineno"> 653</span> tmp_b.float_value = opb;</div> +<div class="line"><a id="l00654" name="l00654"></a><span class="lineno"> 654</span> <span class="keywordflow">if</span> (((tmp_a.binary_value == 0x80000000) &amp;&amp; (tmp_b.binary_value == 0x00000000)) ||</div> +<div class="line"><a id="l00655" name="l00655"></a><span class="lineno"> 655</span> ((tmp_a.binary_value == 0x00000000) &amp;&amp; (tmp_b.binary_value == 0x80000000))) {</div> +<div class="line"><a id="l00656" name="l00656"></a><span class="lineno"> 656</span> <span class="keywordflow">return</span> +0.0f;</div> +<div class="line"><a id="l00657" name="l00657"></a><span class="lineno"> 657</span> }</div> +<div class="line"><a id="l00658" name="l00658"></a><span class="lineno"> 658</span> </div> +<div class="line"><a id="l00659" name="l00659"></a><span class="lineno"> 659</span> <span class="keywordflow">return</span> fmax(opa, opb);</div> +<div class="line"><a id="l00660" name="l00660"></a><span class="lineno"> 660</span>}</div> +</div> +<div class="line"><a id="l00661" name="l00661"></a><span class="lineno"> 661</span> </div> +<div class="line"><a id="l00662" name="l00662"></a><span class="lineno"> 662</span> </div> +<div class="line"><a id="l00663" name="l00663"></a><span class="lineno"> 663</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00669" data-start="{" data-end="}"> +<div class="line"><a id="l00669" name="l00669"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#aad9fc7337e09081cf8c5bff8c28776c8"> 669</a></span>uint32_t __attribute__ ((noinline)) riscv_emulate_fcvt_wus(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00670" name="l00670"></a><span class="lineno"> 670</span> </div> +<div class="line"><a id="l00671" name="l00671"></a><span class="lineno"> 671</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00672" name="l00672"></a><span class="lineno"> 672</span> </div> +<div class="line"><a id="l00673" name="l00673"></a><span class="lineno"> 673</span> <span class="keywordflow">return</span> (uint32_t)rint(opa);</div> +<div class="line"><a id="l00674" name="l00674"></a><span class="lineno"> 674</span>}</div> +</div> +<div class="line"><a id="l00675" name="l00675"></a><span class="lineno"> 675</span> </div> +<div class="line"><a id="l00676" name="l00676"></a><span class="lineno"> 676</span> </div> +<div class="line"><a id="l00677" name="l00677"></a><span class="lineno"> 677</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00683" data-start="{" data-end="}"> +<div class="line"><a id="l00683" name="l00683"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a292365fe41a7a661e61ae746306ba5e9"> 683</a></span>int32_t __attribute__ ((noinline)) riscv_emulate_fcvt_ws(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00684" name="l00684"></a><span class="lineno"> 684</span> </div> +<div class="line"><a id="l00685" name="l00685"></a><span class="lineno"> 685</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00686" name="l00686"></a><span class="lineno"> 686</span> </div> +<div class="line"><a id="l00687" name="l00687"></a><span class="lineno"> 687</span> <span class="keywordflow">return</span> (int32_t)rint(opa);</div> +<div class="line"><a id="l00688" name="l00688"></a><span class="lineno"> 688</span>}</div> +</div> +<div class="line"><a id="l00689" name="l00689"></a><span class="lineno"> 689</span> </div> +<div class="line"><a id="l00690" name="l00690"></a><span class="lineno"> 690</span> </div> +<div class="line"><a id="l00691" name="l00691"></a><span class="lineno"> 691</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00697" data-start="{" data-end="}"> +<div class="line"><a id="l00697" name="l00697"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a10a05bface37bff32c78ed0746845794"> 697</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fcvt_swu(uint32_t rs1) {</div> +<div class="line"><a id="l00698" name="l00698"></a><span class="lineno"> 698</span> </div> +<div class="line"><a id="l00699" name="l00699"></a><span class="lineno"> 699</span> <span class="keywordflow">return</span> (<span class="keywordtype">float</span>)rs1;</div> +<div class="line"><a id="l00700" name="l00700"></a><span class="lineno"> 700</span>}</div> +</div> +<div class="line"><a id="l00701" name="l00701"></a><span class="lineno"> 701</span> </div> +<div class="line"><a id="l00702" name="l00702"></a><span class="lineno"> 702</span> </div> +<div class="line"><a id="l00703" name="l00703"></a><span class="lineno"> 703</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00709" data-start="{" data-end="}"> +<div class="line"><a id="l00709" name="l00709"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a0f2260b7b5793a95c49670379fc89617"> 709</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fcvt_sw(int32_t rs1) {</div> +<div class="line"><a id="l00710" name="l00710"></a><span class="lineno"> 710</span> </div> +<div class="line"><a id="l00711" name="l00711"></a><span class="lineno"> 711</span> <span class="keywordflow">return</span> (<span class="keywordtype">float</span>)rs1;</div> +<div class="line"><a id="l00712" name="l00712"></a><span class="lineno"> 712</span>}</div> +</div> +<div class="line"><a id="l00713" name="l00713"></a><span class="lineno"> 713</span> </div> +<div class="line"><a id="l00714" name="l00714"></a><span class="lineno"> 714</span> </div> +<div class="line"><a id="l00715" name="l00715"></a><span class="lineno"> 715</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00722" data-start="{" data-end="}"> +<div class="line"><a id="l00722" name="l00722"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a7cb3c6570b911cd1dfb7b6e798cc1d21"> 722</a></span>uint32_t __attribute__ ((noinline)) riscv_emulate_feqs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00723" name="l00723"></a><span class="lineno"> 723</span> </div> +<div class="line"><a id="l00724" name="l00724"></a><span class="lineno"> 724</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00725" name="l00725"></a><span class="lineno"> 725</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00726" name="l00726"></a><span class="lineno"> 726</span> </div> +<div class="line"><a id="l00727" name="l00727"></a><span class="lineno"> 727</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00728" name="l00728"></a><span class="lineno"> 728</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00729" name="l00729"></a><span class="lineno"> 729</span> }</div> +<div class="line"><a id="l00730" name="l00730"></a><span class="lineno"> 730</span> </div> +<div class="line"><a id="l00731" name="l00731"></a><span class="lineno"> 731</span> <span class="keywordflow">if</span> isless(opa, opb) {</div> +<div class="line"><a id="l00732" name="l00732"></a><span class="lineno"> 732</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00733" name="l00733"></a><span class="lineno"> 733</span> }</div> +<div class="line"><a id="l00734" name="l00734"></a><span class="lineno"> 734</span> <span class="keywordflow">else</span> <span class="keywordflow">if</span> isgreater(opa, opb) {</div> +<div class="line"><a id="l00735" name="l00735"></a><span class="lineno"> 735</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00736" name="l00736"></a><span class="lineno"> 736</span> }</div> +<div class="line"><a id="l00737" name="l00737"></a><span class="lineno"> 737</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00738" name="l00738"></a><span class="lineno"> 738</span> <span class="keywordflow">return</span> 1;</div> +<div class="line"><a id="l00739" name="l00739"></a><span class="lineno"> 739</span> }</div> +<div class="line"><a id="l00740" name="l00740"></a><span class="lineno"> 740</span>}</div> +</div> +<div class="line"><a id="l00741" name="l00741"></a><span class="lineno"> 741</span> </div> +<div class="line"><a id="l00742" name="l00742"></a><span class="lineno"> 742</span> </div> +<div class="line"><a id="l00743" name="l00743"></a><span class="lineno"> 743</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00750" data-start="{" data-end="}"> +<div class="line"><a id="l00750" name="l00750"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a2b802122d53a2ce517b3d39fec34d7e0"> 750</a></span>uint32_t __attribute__ ((noinline)) riscv_emulate_flts(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00751" name="l00751"></a><span class="lineno"> 751</span> </div> +<div class="line"><a id="l00752" name="l00752"></a><span class="lineno"> 752</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00753" name="l00753"></a><span class="lineno"> 753</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00754" name="l00754"></a><span class="lineno"> 754</span> </div> +<div class="line"><a id="l00755" name="l00755"></a><span class="lineno"> 755</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00756" name="l00756"></a><span class="lineno"> 756</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00757" name="l00757"></a><span class="lineno"> 757</span> }</div> +<div class="line"><a id="l00758" name="l00758"></a><span class="lineno"> 758</span> </div> +<div class="line"><a id="l00759" name="l00759"></a><span class="lineno"> 759</span> <span class="keywordflow">if</span> isless(opa, opb) {</div> +<div class="line"><a id="l00760" name="l00760"></a><span class="lineno"> 760</span> <span class="keywordflow">return</span> 1;</div> +<div class="line"><a id="l00761" name="l00761"></a><span class="lineno"> 761</span> }</div> +<div class="line"><a id="l00762" name="l00762"></a><span class="lineno"> 762</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00763" name="l00763"></a><span class="lineno"> 763</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00764" name="l00764"></a><span class="lineno"> 764</span> }</div> +<div class="line"><a id="l00765" name="l00765"></a><span class="lineno"> 765</span>}</div> +</div> +<div class="line"><a id="l00766" name="l00766"></a><span class="lineno"> 766</span> </div> +<div class="line"><a id="l00767" name="l00767"></a><span class="lineno"> 767</span> </div> +<div class="line"><a id="l00768" name="l00768"></a><span class="lineno"> 768</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00775" data-start="{" data-end="}"> +<div class="line"><a id="l00775" name="l00775"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#ac5fdef0607602fa0bdb93b3535fd709e"> 775</a></span>uint32_t __attribute__ ((noinline)) riscv_emulate_fles(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00776" name="l00776"></a><span class="lineno"> 776</span> </div> +<div class="line"><a id="l00777" name="l00777"></a><span class="lineno"> 777</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00778" name="l00778"></a><span class="lineno"> 778</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00779" name="l00779"></a><span class="lineno"> 779</span> </div> +<div class="line"><a id="l00780" name="l00780"></a><span class="lineno"> 780</span> <span class="keywordflow">if</span> ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {</div> +<div class="line"><a id="l00781" name="l00781"></a><span class="lineno"> 781</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00782" name="l00782"></a><span class="lineno"> 782</span> }</div> +<div class="line"><a id="l00783" name="l00783"></a><span class="lineno"> 783</span> </div> +<div class="line"><a id="l00784" name="l00784"></a><span class="lineno"> 784</span> <span class="keywordflow">if</span> islessequal(opa, opb) {</div> +<div class="line"><a id="l00785" name="l00785"></a><span class="lineno"> 785</span> <span class="keywordflow">return</span> 1;</div> +<div class="line"><a id="l00786" name="l00786"></a><span class="lineno"> 786</span> }</div> +<div class="line"><a id="l00787" name="l00787"></a><span class="lineno"> 787</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00788" name="l00788"></a><span class="lineno"> 788</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00789" name="l00789"></a><span class="lineno"> 789</span> }</div> +<div class="line"><a id="l00790" name="l00790"></a><span class="lineno"> 790</span>}</div> +</div> +<div class="line"><a id="l00791" name="l00791"></a><span class="lineno"> 791</span> </div> +<div class="line"><a id="l00792" name="l00792"></a><span class="lineno"> 792</span> </div> +<div class="line"><a id="l00793" name="l00793"></a><span class="lineno"> 793</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00800" data-start="{" data-end="}"> +<div class="line"><a id="l00800" name="l00800"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a12498d635f422f607b9b83facf3050dd"> 800</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsgnjs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00801" name="l00801"></a><span class="lineno"> 801</span> </div> +<div class="line"><a id="l00802" name="l00802"></a><span class="lineno"> 802</span> <span class="keywordtype">float</span> opa = rs1;</div> +<div class="line"><a id="l00803" name="l00803"></a><span class="lineno"> 803</span> <span class="keywordtype">float</span> opb = rs2;</div> +<div class="line"><a id="l00804" name="l00804"></a><span class="lineno"> 804</span> </div> +<div class="line"><a id="l00805" name="l00805"></a><span class="lineno"> 805</span> <span class="keywordtype">int</span> sign_1 = (int)signbit(opa);</div> +<div class="line"><a id="l00806" name="l00806"></a><span class="lineno"> 806</span> <span class="keywordtype">int</span> sign_2 = (int)signbit(opb);</div> +<div class="line"><a id="l00807" name="l00807"></a><span class="lineno"> 807</span> <span class="keywordtype">float</span> res = 0;</div> +<div class="line"><a id="l00808" name="l00808"></a><span class="lineno"> 808</span> </div> +<div class="line"><a id="l00809" name="l00809"></a><span class="lineno"> 809</span> <span class="keywordflow">if</span> (sign_2 != 0) { <span class="comment">// opb is negative</span></div> +<div class="line"><a id="l00810" name="l00810"></a><span class="lineno"> 810</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00811" name="l00811"></a><span class="lineno"> 811</span> res = -opa;</div> +<div class="line"><a id="l00812" name="l00812"></a><span class="lineno"> 812</span> }</div> +<div class="line"><a id="l00813" name="l00813"></a><span class="lineno"> 813</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00814" name="l00814"></a><span class="lineno"> 814</span> res = opa;</div> +<div class="line"><a id="l00815" name="l00815"></a><span class="lineno"> 815</span> }</div> +<div class="line"><a id="l00816" name="l00816"></a><span class="lineno"> 816</span> }</div> +<div class="line"><a id="l00817" name="l00817"></a><span class="lineno"> 817</span> <span class="keywordflow">else</span> { <span class="comment">// opb is positive</span></div> +<div class="line"><a id="l00818" name="l00818"></a><span class="lineno"> 818</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00819" name="l00819"></a><span class="lineno"> 819</span> res = opa;</div> +<div class="line"><a id="l00820" name="l00820"></a><span class="lineno"> 820</span> }</div> +<div class="line"><a id="l00821" name="l00821"></a><span class="lineno"> 821</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00822" name="l00822"></a><span class="lineno"> 822</span> res = -opa;</div> +<div class="line"><a id="l00823" name="l00823"></a><span class="lineno"> 823</span> }</div> +<div class="line"><a id="l00824" name="l00824"></a><span class="lineno"> 824</span> }</div> +<div class="line"><a id="l00825" name="l00825"></a><span class="lineno"> 825</span> </div> +<div class="line"><a id="l00826" name="l00826"></a><span class="lineno"> 826</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00827" name="l00827"></a><span class="lineno"> 827</span>}</div> +</div> +<div class="line"><a id="l00828" name="l00828"></a><span class="lineno"> 828</span> </div> +<div class="line"><a id="l00829" name="l00829"></a><span class="lineno"> 829</span> </div> +<div class="line"><a id="l00830" name="l00830"></a><span class="lineno"> 830</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00837" data-start="{" data-end="}"> +<div class="line"><a id="l00837" name="l00837"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a0c985e626ed1d69314f4e3a0f1f58624"> 837</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsgnjns(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00838" name="l00838"></a><span class="lineno"> 838</span> </div> +<div class="line"><a id="l00839" name="l00839"></a><span class="lineno"> 839</span> <span class="keywordtype">float</span> opa = rs1;</div> +<div class="line"><a id="l00840" name="l00840"></a><span class="lineno"> 840</span> <span class="keywordtype">float</span> opb = rs2;</div> +<div class="line"><a id="l00841" name="l00841"></a><span class="lineno"> 841</span> </div> +<div class="line"><a id="l00842" name="l00842"></a><span class="lineno"> 842</span> <span class="keywordtype">int</span> sign_1 = (int)signbit(opa);</div> +<div class="line"><a id="l00843" name="l00843"></a><span class="lineno"> 843</span> <span class="keywordtype">int</span> sign_2 = (int)signbit(opb);</div> +<div class="line"><a id="l00844" name="l00844"></a><span class="lineno"> 844</span> <span class="keywordtype">float</span> res = 0;</div> +<div class="line"><a id="l00845" name="l00845"></a><span class="lineno"> 845</span> </div> +<div class="line"><a id="l00846" name="l00846"></a><span class="lineno"> 846</span> <span class="keywordflow">if</span> (sign_2 != 0) { <span class="comment">// opb is negative</span></div> +<div class="line"><a id="l00847" name="l00847"></a><span class="lineno"> 847</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00848" name="l00848"></a><span class="lineno"> 848</span> res = opa;</div> +<div class="line"><a id="l00849" name="l00849"></a><span class="lineno"> 849</span> }</div> +<div class="line"><a id="l00850" name="l00850"></a><span class="lineno"> 850</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00851" name="l00851"></a><span class="lineno"> 851</span> res = -opa;</div> +<div class="line"><a id="l00852" name="l00852"></a><span class="lineno"> 852</span> }</div> +<div class="line"><a id="l00853" name="l00853"></a><span class="lineno"> 853</span> }</div> +<div class="line"><a id="l00854" name="l00854"></a><span class="lineno"> 854</span> <span class="keywordflow">else</span> { <span class="comment">// opb is positive</span></div> +<div class="line"><a id="l00855" name="l00855"></a><span class="lineno"> 855</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00856" name="l00856"></a><span class="lineno"> 856</span> res = -opa;</div> +<div class="line"><a id="l00857" name="l00857"></a><span class="lineno"> 857</span> }</div> +<div class="line"><a id="l00858" name="l00858"></a><span class="lineno"> 858</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00859" name="l00859"></a><span class="lineno"> 859</span> res = opa;</div> +<div class="line"><a id="l00860" name="l00860"></a><span class="lineno"> 860</span> }</div> +<div class="line"><a id="l00861" name="l00861"></a><span class="lineno"> 861</span> }</div> +<div class="line"><a id="l00862" name="l00862"></a><span class="lineno"> 862</span> </div> +<div class="line"><a id="l00863" name="l00863"></a><span class="lineno"> 863</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00864" name="l00864"></a><span class="lineno"> 864</span>}</div> +</div> +<div class="line"><a id="l00865" name="l00865"></a><span class="lineno"> 865</span> </div> +<div class="line"><a id="l00866" name="l00866"></a><span class="lineno"> 866</span> </div> +<div class="line"><a id="l00867" name="l00867"></a><span class="lineno"> 867</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00874" data-start="{" data-end="}"> +<div class="line"><a id="l00874" name="l00874"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a98caf7f310820052ae96ce0f45e6cd26"> 874</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsgnjxs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00875" name="l00875"></a><span class="lineno"> 875</span> </div> +<div class="line"><a id="l00876" name="l00876"></a><span class="lineno"> 876</span> <span class="keywordtype">float</span> opa = rs1;</div> +<div class="line"><a id="l00877" name="l00877"></a><span class="lineno"> 877</span> <span class="keywordtype">float</span> opb = rs2;</div> +<div class="line"><a id="l00878" name="l00878"></a><span class="lineno"> 878</span> </div> +<div class="line"><a id="l00879" name="l00879"></a><span class="lineno"> 879</span> <span class="keywordtype">int</span> sign_1 = (int)signbit(opa);</div> +<div class="line"><a id="l00880" name="l00880"></a><span class="lineno"> 880</span> <span class="keywordtype">int</span> sign_2 = (int)signbit(opb);</div> +<div class="line"><a id="l00881" name="l00881"></a><span class="lineno"> 881</span> <span class="keywordtype">float</span> res = 0;</div> +<div class="line"><a id="l00882" name="l00882"></a><span class="lineno"> 882</span> </div> +<div class="line"><a id="l00883" name="l00883"></a><span class="lineno"> 883</span> <span class="keywordflow">if</span> (((sign_1 == 0) &amp;&amp; (sign_2 != 0)) || ((sign_1 != 0) &amp;&amp; (sign_2 == 0))) {</div> +<div class="line"><a id="l00884" name="l00884"></a><span class="lineno"> 884</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00885" name="l00885"></a><span class="lineno"> 885</span> res = -opa;</div> +<div class="line"><a id="l00886" name="l00886"></a><span class="lineno"> 886</span> }</div> +<div class="line"><a id="l00887" name="l00887"></a><span class="lineno"> 887</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00888" name="l00888"></a><span class="lineno"> 888</span> res = opa;</div> +<div class="line"><a id="l00889" name="l00889"></a><span class="lineno"> 889</span> }</div> +<div class="line"><a id="l00890" name="l00890"></a><span class="lineno"> 890</span> }</div> +<div class="line"><a id="l00891" name="l00891"></a><span class="lineno"> 891</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00892" name="l00892"></a><span class="lineno"> 892</span> <span class="keywordflow">if</span> (sign_1 == 0) {</div> +<div class="line"><a id="l00893" name="l00893"></a><span class="lineno"> 893</span> res = opa;</div> +<div class="line"><a id="l00894" name="l00894"></a><span class="lineno"> 894</span> }</div> +<div class="line"><a id="l00895" name="l00895"></a><span class="lineno"> 895</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00896" name="l00896"></a><span class="lineno"> 896</span> res = -opa;</div> +<div class="line"><a id="l00897" name="l00897"></a><span class="lineno"> 897</span> }</div> +<div class="line"><a id="l00898" name="l00898"></a><span class="lineno"> 898</span> }</div> +<div class="line"><a id="l00899" name="l00899"></a><span class="lineno"> 899</span> </div> +<div class="line"><a id="l00900" name="l00900"></a><span class="lineno"> 900</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00901" name="l00901"></a><span class="lineno"> 901</span>}</div> +</div> +<div class="line"><a id="l00902" name="l00902"></a><span class="lineno"> 902</span> </div> +<div class="line"><a id="l00903" name="l00903"></a><span class="lineno"> 903</span> </div> +<div class="line"><a id="l00904" name="l00904"></a><span class="lineno"> 904</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00910" data-start="{" data-end="}"> +<div class="line"><a id="l00910" name="l00910"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#ae41a0bf9d28c35f4d6db7177ccf8ee06"> 910</a></span>uint32_t __attribute__ ((noinline)) riscv_emulate_fclasss(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00911" name="l00911"></a><span class="lineno"> 911</span> </div> +<div class="line"><a id="l00912" name="l00912"></a><span class="lineno"> 912</span> <span class="keywordtype">float</span> opa = rs1;</div> +<div class="line"><a id="l00913" name="l00913"></a><span class="lineno"> 913</span> </div> +<div class="line"><a id="l00914" name="l00914"></a><span class="lineno"> 914</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00915" name="l00915"></a><span class="lineno"> 915</span> uint32_t binary_value; </div> +<div class="line"><a id="l00916" name="l00916"></a><span class="lineno"> 916</span> <span class="keywordtype">float</span> float_value; </div> +<div class="line"><a id="l00917" name="l00917"></a><span class="lineno"> 917</span> } aux;</div> +<div class="line"><a id="l00918" name="l00918"></a><span class="lineno"> 918</span> </div> +<div class="line"><a id="l00919" name="l00919"></a><span class="lineno"> 919</span> <span class="comment">// RISC-V classify result layout</span></div> +<div class="line"><a id="l00920" name="l00920"></a><span class="lineno"> 920</span> <span class="keyword">const</span> uint32_t CLASS_NEG_INF = 1 &lt;&lt; 0; <span class="comment">// negative infinity</span></div> +<div class="line"><a id="l00921" name="l00921"></a><span class="lineno"> 921</span> <span class="keyword">const</span> uint32_t CLASS_NEG_NORM = 1 &lt;&lt; 1; <span class="comment">// negative normal number</span></div> +<div class="line"><a id="l00922" name="l00922"></a><span class="lineno"> 922</span> <span class="keyword">const</span> uint32_t CLASS_NEG_DENORM = 1 &lt;&lt; 2; <span class="comment">// negative subnormal number</span></div> +<div class="line"><a id="l00923" name="l00923"></a><span class="lineno"> 923</span> <span class="keyword">const</span> uint32_t CLASS_NEG_ZERO = 1 &lt;&lt; 3; <span class="comment">// negative zero</span></div> +<div class="line"><a id="l00924" name="l00924"></a><span class="lineno"> 924</span> <span class="keyword">const</span> uint32_t CLASS_POS_ZERO = 1 &lt;&lt; 4; <span class="comment">// positive zero</span></div> +<div class="line"><a id="l00925" name="l00925"></a><span class="lineno"> 925</span> <span class="keyword">const</span> uint32_t CLASS_POS_DENORM = 1 &lt;&lt; 5; <span class="comment">// positive subnormal number</span></div> +<div class="line"><a id="l00926" name="l00926"></a><span class="lineno"> 926</span> <span class="keyword">const</span> uint32_t CLASS_POS_NORM = 1 &lt;&lt; 6; <span class="comment">// positive normal number</span></div> +<div class="line"><a id="l00927" name="l00927"></a><span class="lineno"> 927</span> <span class="keyword">const</span> uint32_t CLASS_POS_INF = 1 &lt;&lt; 7; <span class="comment">// positive infinity</span></div> +<div class="line"><a id="l00928" name="l00928"></a><span class="lineno"> 928</span> <span class="keyword">const</span> uint32_t CLASS_SNAN = 1 &lt;&lt; 8; <span class="comment">// signaling NaN (sNaN)</span></div> +<div class="line"><a id="l00929" name="l00929"></a><span class="lineno"> 929</span> <span class="keyword">const</span> uint32_t CLASS_QNAN = 1 &lt;&lt; 9; <span class="comment">// quiet NaN (qNaN)</span></div> +<div class="line"><a id="l00930" name="l00930"></a><span class="lineno"> 930</span> </div> +<div class="line"><a id="l00931" name="l00931"></a><span class="lineno"> 931</span> <span class="keywordtype">int</span> tmp = fpclassify(opa);</div> +<div class="line"><a id="l00932" name="l00932"></a><span class="lineno"> 932</span> <span class="keywordtype">int</span> sgn = (int)signbit(opa);</div> +<div class="line"><a id="l00933" name="l00933"></a><span class="lineno"> 933</span> </div> +<div class="line"><a id="l00934" name="l00934"></a><span class="lineno"> 934</span> uint32_t res = 0;</div> +<div class="line"><a id="l00935" name="l00935"></a><span class="lineno"> 935</span> </div> +<div class="line"><a id="l00936" name="l00936"></a><span class="lineno"> 936</span> <span class="comment">// infinity</span></div> +<div class="line"><a id="l00937" name="l00937"></a><span class="lineno"> 937</span> <span class="keywordflow">if</span> (tmp == FP_INFINITE) {</div> +<div class="line"><a id="l00938" name="l00938"></a><span class="lineno"> 938</span> <span class="keywordflow">if</span> (sgn) { res |= CLASS_NEG_INF; }</div> +<div class="line"><a id="l00939" name="l00939"></a><span class="lineno"> 939</span> <span class="keywordflow">else</span> { res |= CLASS_POS_INF; }</div> +<div class="line"><a id="l00940" name="l00940"></a><span class="lineno"> 940</span> }</div> +<div class="line"><a id="l00941" name="l00941"></a><span class="lineno"> 941</span> </div> +<div class="line"><a id="l00942" name="l00942"></a><span class="lineno"> 942</span> <span class="comment">// zero</span></div> +<div class="line"><a id="l00943" name="l00943"></a><span class="lineno"> 943</span> <span class="keywordflow">if</span> (tmp == FP_ZERO) {</div> +<div class="line"><a id="l00944" name="l00944"></a><span class="lineno"> 944</span> <span class="keywordflow">if</span> (sgn) { res |= CLASS_NEG_ZERO; }</div> +<div class="line"><a id="l00945" name="l00945"></a><span class="lineno"> 945</span> <span class="keywordflow">else</span> { res |= CLASS_POS_ZERO; }</div> +<div class="line"><a id="l00946" name="l00946"></a><span class="lineno"> 946</span> }</div> +<div class="line"><a id="l00947" name="l00947"></a><span class="lineno"> 947</span> </div> +<div class="line"><a id="l00948" name="l00948"></a><span class="lineno"> 948</span> <span class="comment">// normal</span></div> +<div class="line"><a id="l00949" name="l00949"></a><span class="lineno"> 949</span> <span class="keywordflow">if</span> (tmp == FP_NORMAL) {</div> +<div class="line"><a id="l00950" name="l00950"></a><span class="lineno"> 950</span> <span class="keywordflow">if</span> (sgn) { res |= CLASS_NEG_NORM; }</div> +<div class="line"><a id="l00951" name="l00951"></a><span class="lineno"> 951</span> <span class="keywordflow">else</span> { res |= CLASS_POS_NORM; }</div> +<div class="line"><a id="l00952" name="l00952"></a><span class="lineno"> 952</span> }</div> +<div class="line"><a id="l00953" name="l00953"></a><span class="lineno"> 953</span> </div> +<div class="line"><a id="l00954" name="l00954"></a><span class="lineno"> 954</span> <span class="comment">// subnormal</span></div> +<div class="line"><a id="l00955" name="l00955"></a><span class="lineno"> 955</span> <span class="keywordflow">if</span> (tmp == FP_SUBNORMAL) {</div> +<div class="line"><a id="l00956" name="l00956"></a><span class="lineno"> 956</span> <span class="keywordflow">if</span> (sgn) { res |= CLASS_NEG_DENORM; }</div> +<div class="line"><a id="l00957" name="l00957"></a><span class="lineno"> 957</span> <span class="keywordflow">else</span> { res |= CLASS_POS_DENORM; }</div> +<div class="line"><a id="l00958" name="l00958"></a><span class="lineno"> 958</span> }</div> +<div class="line"><a id="l00959" name="l00959"></a><span class="lineno"> 959</span> </div> +<div class="line"><a id="l00960" name="l00960"></a><span class="lineno"> 960</span> <span class="comment">// NaN</span></div> +<div class="line"><a id="l00961" name="l00961"></a><span class="lineno"> 961</span> <span class="keywordflow">if</span> (tmp == FP_NAN) {</div> +<div class="line"><a id="l00962" name="l00962"></a><span class="lineno"> 962</span> aux.float_value = opa;</div> +<div class="line"><a id="l00963" name="l00963"></a><span class="lineno"> 963</span> <span class="keywordflow">if</span> ((aux.binary_value &gt;&gt; 22) &amp; 0b1) { <span class="comment">// bit 22 (mantissa&#39;s MSB) is set -&gt; canonical (quiet) NAN</span></div> +<div class="line"><a id="l00964" name="l00964"></a><span class="lineno"> 964</span> res |= CLASS_QNAN;</div> +<div class="line"><a id="l00965" name="l00965"></a><span class="lineno"> 965</span> }</div> +<div class="line"><a id="l00966" name="l00966"></a><span class="lineno"> 966</span> <span class="keywordflow">else</span> {</div> +<div class="line"><a id="l00967" name="l00967"></a><span class="lineno"> 967</span> res |= CLASS_SNAN;</div> +<div class="line"><a id="l00968" name="l00968"></a><span class="lineno"> 968</span> }</div> +<div class="line"><a id="l00969" name="l00969"></a><span class="lineno"> 969</span> }</div> +<div class="line"><a id="l00970" name="l00970"></a><span class="lineno"> 970</span> </div> +<div class="line"><a id="l00971" name="l00971"></a><span class="lineno"> 971</span> <span class="keywordflow">return</span> res;</div> +<div class="line"><a id="l00972" name="l00972"></a><span class="lineno"> 972</span>}</div> +</div> +<div class="line"><a id="l00973" name="l00973"></a><span class="lineno"> 973</span> </div> +<div class="line"><a id="l00974" name="l00974"></a><span class="lineno"> 974</span> </div> +<div class="line"><a id="l00975" name="l00975"></a><span class="lineno"> 975</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00982" data-start="{" data-end="}"> +<div class="line"><a id="l00982" name="l00982"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#aeaf46a17b671278be2bf804159827a40"> 982</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fdivs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2) {</div> +<div class="line"><a id="l00983" name="l00983"></a><span class="lineno"> 983</span> </div> +<div class="line"><a id="l00984" name="l00984"></a><span class="lineno"> 984</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l00985" name="l00985"></a><span class="lineno"> 985</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l00986" name="l00986"></a><span class="lineno"> 986</span> </div> +<div class="line"><a id="l00987" name="l00987"></a><span class="lineno"> 987</span> <span class="keywordtype">float</span> res = opa / opb;</div> +<div class="line"><a id="l00988" name="l00988"></a><span class="lineno"> 988</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l00989" name="l00989"></a><span class="lineno"> 989</span>}</div> +</div> +<div class="line"><a id="l00990" name="l00990"></a><span class="lineno"> 990</span> </div> +<div class="line"><a id="l00991" name="l00991"></a><span class="lineno"> 991</span> </div> +<div class="line"><a id="l00992" name="l00992"></a><span class="lineno"> 992</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00998" data-start="{" data-end="}"> +<div class="line"><a id="l00998" name="l00998"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a1ceb3450f1e5c62d3079cd0e93c03501"> 998</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fsqrts(<span class="keywordtype">float</span> rs1) {</div> +<div class="line"><a id="l00999" name="l00999"></a><span class="lineno"> 999</span> </div> +<div class="line"><a id="l01000" name="l01000"></a><span class="lineno"> 1000</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01001" name="l01001"></a><span class="lineno"> 1001</span> </div> +<div class="line"><a id="l01002" name="l01002"></a><span class="lineno"> 1002</span> <span class="keywordtype">float</span> res = sqrtf(opa);</div> +<div class="line"><a id="l01003" name="l01003"></a><span class="lineno"> 1003</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01004" name="l01004"></a><span class="lineno"> 1004</span>}</div> +</div> +<div class="line"><a id="l01005" name="l01005"></a><span class="lineno"> 1005</span> </div> +<div class="line"><a id="l01006" name="l01006"></a><span class="lineno"> 1006</span> </div> +<div class="line"><a id="l01007" name="l01007"></a><span class="lineno"> 1007</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen01017" data-start="{" data-end="}"> +<div class="line"><a id="l01017" name="l01017"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a39212f2e2bb0f1752092a1732f93edf3"> 1017</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l01018" name="l01018"></a><span class="lineno"> 1018</span> </div> +<div class="line"><a id="l01019" name="l01019"></a><span class="lineno"> 1019</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01020" name="l01020"></a><span class="lineno"> 1020</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01021" name="l01021"></a><span class="lineno"> 1021</span> <span class="keywordtype">float</span> opc = subnormal_flush(rs3);</div> +<div class="line"><a id="l01022" name="l01022"></a><span class="lineno"> 1022</span> </div> +<div class="line"><a id="l01023" name="l01023"></a><span class="lineno"> 1023</span> <span class="keywordtype">float</span> res = (opa * opb) + opc;</div> +<div class="line"><a id="l01024" name="l01024"></a><span class="lineno"> 1024</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01025" name="l01025"></a><span class="lineno"> 1025</span>}</div> +</div> +<div class="line"><a id="l01026" name="l01026"></a><span class="lineno"> 1026</span> </div> +<div class="line"><a id="l01027" name="l01027"></a><span class="lineno"> 1027</span> </div> +<div class="line"><a id="l01028" name="l01028"></a><span class="lineno"> 1028</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen01036" data-start="{" data-end="}"> +<div class="line"><a id="l01036" name="l01036"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a05d0d5a8eb9422e93448efdeb679cabf"> 1036</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fmsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l01037" name="l01037"></a><span class="lineno"> 1037</span> </div> +<div class="line"><a id="l01038" name="l01038"></a><span class="lineno"> 1038</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01039" name="l01039"></a><span class="lineno"> 1039</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01040" name="l01040"></a><span class="lineno"> 1040</span> <span class="keywordtype">float</span> opc = subnormal_flush(rs3);</div> +<div class="line"><a id="l01041" name="l01041"></a><span class="lineno"> 1041</span> </div> +<div class="line"><a id="l01042" name="l01042"></a><span class="lineno"> 1042</span> <span class="keywordtype">float</span> res = (opa * opb) - opc;</div> +<div class="line"><a id="l01043" name="l01043"></a><span class="lineno"> 1043</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01044" name="l01044"></a><span class="lineno"> 1044</span>}</div> +</div> +<div class="line"><a id="l01045" name="l01045"></a><span class="lineno"> 1045</span> </div> +<div class="line"><a id="l01046" name="l01046"></a><span class="lineno"> 1046</span> </div> +<div class="line"><a id="l01047" name="l01047"></a><span class="lineno"> 1047</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen01055" data-start="{" data-end="}"> +<div class="line"><a id="l01055" name="l01055"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#a833638b346722dfa9d7d5c8d60998ec8"> 1055</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fnmsubs(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l01056" name="l01056"></a><span class="lineno"> 1056</span> </div> +<div class="line"><a id="l01057" name="l01057"></a><span class="lineno"> 1057</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01058" name="l01058"></a><span class="lineno"> 1058</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01059" name="l01059"></a><span class="lineno"> 1059</span> <span class="keywordtype">float</span> opc = subnormal_flush(rs3);</div> +<div class="line"><a id="l01060" name="l01060"></a><span class="lineno"> 1060</span> </div> +<div class="line"><a id="l01061" name="l01061"></a><span class="lineno"> 1061</span> <span class="keywordtype">float</span> res = -(opa * opb) + opc;</div> +<div class="line"><a id="l01062" name="l01062"></a><span class="lineno"> 1062</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01063" name="l01063"></a><span class="lineno"> 1063</span>}</div> +</div> +<div class="line"><a id="l01064" name="l01064"></a><span class="lineno"> 1064</span> </div> +<div class="line"><a id="l01065" name="l01065"></a><span class="lineno"> 1065</span> </div> +<div class="line"><a id="l01066" name="l01066"></a><span class="lineno"> 1066</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen01074" data-start="{" data-end="}"> +<div class="line"><a id="l01074" name="l01074"></a><span class="lineno"><a class="line" href="floating__point__test_2neorv32__zfinx__extension__intrinsics_8h.html#ac8bb4450b39854ab07839e8f3505361c"> 1074</a></span><span class="keywordtype">float</span> __attribute__ ((noinline)) riscv_emulate_fnmadds(<span class="keywordtype">float</span> rs1, <span class="keywordtype">float</span> rs2, <span class="keywordtype">float</span> rs3) {</div> +<div class="line"><a id="l01075" name="l01075"></a><span class="lineno"> 1075</span> </div> +<div class="line"><a id="l01076" name="l01076"></a><span class="lineno"> 1076</span> <span class="keywordtype">float</span> opa = subnormal_flush(rs1);</div> +<div class="line"><a id="l01077" name="l01077"></a><span class="lineno"> 1077</span> <span class="keywordtype">float</span> opb = subnormal_flush(rs2);</div> +<div class="line"><a id="l01078" name="l01078"></a><span class="lineno"> 1078</span> <span class="keywordtype">float</span> opc = subnormal_flush(rs3);</div> +<div class="line"><a id="l01079" name="l01079"></a><span class="lineno"> 1079</span> </div> +<div class="line"><a id="l01080" name="l01080"></a><span class="lineno"> 1080</span> <span class="keywordtype">float</span> res = -(opa * opb) - opc;</div> +<div class="line"><a id="l01081" name="l01081"></a><span class="lineno"> 1081</span> <span class="keywordflow">return</span> subnormal_flush(res);</div> +<div class="line"><a id="l01082" name="l01082"></a><span class="lineno"> 1082</span>}</div> +</div> +<div class="line"><a id="l01083" name="l01083"></a><span class="lineno"> 1083</span> </div> +<div class="line"><a id="l01084" name="l01084"></a><span class="lineno"> 1084</span> </div> +<div class="line"><a id="l01085" name="l01085"></a><span class="lineno"> 1085</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_zfinx_extension_intrinsics_h</span></div> +<div class="line"><a id="l01086" name="l01086"></a><span class="lineno"> 1086</span> </div> +<div class="ttc" id="aunionfloat__conv__t_html"><div class="ttname"><a href="unionfloat__conv__t.html">float_conv_t</a></div><div class="ttdef"><b>Definition</b> neorv32_zfinx_extension_intrinsics.h:78</div></div> +<div class="ttc" id="aunionfloat__conv__t_html_a59ad19d41b1d973a6bda9032e1937606"><div class="ttname"><a href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">float_conv_t::binary_value</a></div><div class="ttdeci">uint32_t binary_value</div><div class="ttdef"><b>Definition</b> neorv32_zfinx_extension_intrinsics.h:79</div></div> +<div class="ttc" id="aunionfloat__conv__t_html_a95f2e38b437bd8d4e8de7f61d7474788"><div class="ttname"><a href="unionfloat__conv__t.html#a95f2e38b437bd8d4e8de7f61d7474788">float_conv_t::float_value</a></div><div class="ttdeci">float float_value</div><div class="ttdef"><b>Definition</b> neorv32_zfinx_extension_intrinsics.h:80</div></div> +</div><!-- fragment --></div><!-- contents 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http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Data Fields</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> 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class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div> + +<h3><a id="index_b" name="index_b"></a>- b -</h3><ul> +<li>binary_value&#160;:&#160;<a class="el" href="unionfloat__conv__t.html#a59ad19d41b1d973a6bda9032e1937606">float_conv_t</a></li> +</ul> + + +<h3><a id="index_c" name="index_c"></a>- c -</h3><ul> +<li>CACHE&#160;:&#160;<a class="el" href="structneorv32__sysinfo__t.html#ada99a36ccda38b254d5b6a84883101f6">neorv32_sysinfo_t</a></li> +<li>CHANNEL_CFG&#160;:&#160;<a class="el" href="structneorv32__pwm__t.html#a5df0cf6c7c250365db3ada8db7cc19e9">neorv32_pwm_t</a></li> +<li>CLK&#160;:&#160;<a class="el" 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Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Data Fields - Variables</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license 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onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_46981071cfd8ec44311b09fdcf6c06a8.html">game_of_life</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> &#124; +<a href="#var-members">Variables</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Conway's game of life in a UART terminal. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr 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class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9a455dea83a25f656fcc5217ad513dac" id="r_a9a455dea83a25f656fcc5217ad513dac"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9a455dea83a25f656fcc5217ad513dac">print_universe</a> (int u)</td></tr> +<tr class="separator:a9a455dea83a25f656fcc5217ad513dac"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aac4bec7738b12f5a4b4d7a3a6cb1ab8d" id="r_aac4bec7738b12f5a4b4d7a3a6cb1ab8d"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aac4bec7738b12f5a4b4d7a3a6cb1ab8d">pop_count</a> (int u)</td></tr> +<tr class="separator:aac4bec7738b12f5a4b4d7a3a6cb1ab8d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a840291bc02cba5474a4cb46a9b9566fe" id="r_a840291bc02cba5474a4cb46a9b9566fe"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a840291bc02cba5474a4cb46a9b9566fe">main</a> (void)</td></tr> +<tr class="separator:a840291bc02cba5474a4cb46a9b9566fe"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:ae0b5214cf0cd93049e9df8a95a09d826" id="r_ae0b5214cf0cd93049e9df8a95a09d826"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae0b5214cf0cd93049e9df8a95a09d826">universe</a> [2][<a class="el" href="#a78c5b500f0f057bcaedf6fedeca7c537">NUM_CELLS_X</a>/8][<a class="el" href="#aed77778557404b38bebb05b5830368b4">NUM_CELLS_Y</a>]</td></tr> +<tr class="separator:ae0b5214cf0cd93049e9df8a95a09d826"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Conway's game of life in a UART terminal. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<a id="afa6488273e16792d9c3da5e40e3f572d" name="afa6488273e16792d9c3da5e40e3f572d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afa6488273e16792d9c3da5e40e3f572d">&#9670;&#160;</a></span>CELL_ALIVE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CELL_ALIVE&#160;&#160;&#160;('#')</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Symbol for alive cell </p> + +</div> +</div> +<a id="abe6bebcf1cb4f5b4d522c1706eb48663" name="abe6bebcf1cb4f5b4d522c1706eb48663"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abe6bebcf1cb4f5b4d522c1706eb48663">&#9670;&#160;</a></span>CELL_DEAD</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CELL_DEAD&#160;&#160;&#160;(' ')</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Symbol for dead cell </p> + +</div> +</div> +<a id="a3f33bf77abbf35c245956489f8f7e3a7" name="a3f33bf77abbf35c245956489f8f7e3a7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3f33bf77abbf35c245956489f8f7e3a7">&#9670;&#160;</a></span>GEN_DELAY</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define GEN_DELAY&#160;&#160;&#160;500</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Delay between generations in ms </p> + +</div> +</div> +<a id="a78c5b500f0f057bcaedf6fedeca7c537" name="a78c5b500f0f057bcaedf6fedeca7c537"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a78c5b500f0f057bcaedf6fedeca7c537">&#9670;&#160;</a></span>NUM_CELLS_X</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NUM_CELLS_X&#160;&#160;&#160;160</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Universe x size (has to be a multiple of 8) </p> + +</div> +</div> +<a id="aed77778557404b38bebb05b5830368b4" name="aed77778557404b38bebb05b5830368b4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aed77778557404b38bebb05b5830368b4">&#9670;&#160;</a></span>NUM_CELLS_Y</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NUM_CELLS_Y&#160;&#160;&#160;40</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Universe y size </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a819f10c5b644a07eeb069b6e7f12050e" name="a819f10c5b644a07eeb069b6e7f12050e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a819f10c5b644a07eeb069b6e7f12050e">&#9670;&#160;</a></span>clear_universe()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void clear_universe </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>u</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Kill all cells in universe.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">u</td><td>Universe select (0 or 1). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a6bd541a19c62ea9ec620eaad3f218d16" name="a6bd541a19c62ea9ec620eaad3f218d16"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6bd541a19c62ea9ec620eaad3f218d16">&#9670;&#160;</a></span>get_cell()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int get_cell </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>u</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>x</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>y</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get state of cell.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">u</td><td>Universe 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class="paramname"><em>x</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>y</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get number of living cells in neighborhood.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">u</td><td>Universe select (0 or 1). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">x</td><td>X coordinate of the neighborhood's center cell. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">y</td><td>Y coordinate of the neighborhood's center cell. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Number of living cells in neighborhood (0..9). </dd></dl> + +</div> +</div> +<a id="a840291bc02cba5474a4cb46a9b9566fe" name="a840291bc02cba5474a4cb46a9b9566fe"></a> +<h2 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class="memname">int pop_count </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>u</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Count living cells in universe.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">u</td><td>Universe select (0 or 1). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Number of living cells. </dd></dl> + +</div> +</div> +<a id="a9a455dea83a25f656fcc5217ad513dac" name="a9a455dea83a25f656fcc5217ad513dac"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9a455dea83a25f656fcc5217ad513dac">&#9670;&#160;</a></span>print_universe()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void print_universe </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>u</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print universe via UARt.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">u</td><td>Universe select (0 or 1). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a5315eb56128f1ca40d9f4d477c345dd7" name="a5315eb56128f1ca40d9f4d477c345dd7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5315eb56128f1ca40d9f4d477c345dd7">&#9670;&#160;</a></span>set_cell()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void set_cell </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>u</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>x</em></span>, </td> + </tr> + <tr> + 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not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script 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src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + 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doc-content --> +</body> +</html> diff --git a/sw/globals_defs_b.html b/sw/globals_defs_b.html new file mode 100644 index 000000000..d9f363d6c --- /dev/null +++ b/sw/globals_defs_b.html @@ -0,0 +1,103 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_b" name="index_b"></a>- b -</h3><ul> +<li>BAUD_RATE&#160;:&#160;<a class="el" href="atomic__test_2main_8c.html#ad4455691936f92fdd6c37566fc58ba1f">main.c</a></li> +<li>BOOTLOADER_BASE_ADDRESS&#160;:&#160;<a class="el" href="neorv32_8h.html#abd8c9b7d79f49de1722611b2835cde58">neorv32.h</a></li> +<li>BUFFER_SIZE&#160;:&#160;<a class="el" href="demo__xip_2main_8c.html#a6b20d41d6252e9871430c242cb1a56e7">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_c.html b/sw/globals_defs_c.html new file mode 100644 index 000000000..97ee542c8 --- /dev/null +++ b/sw/globals_defs_c.html @@ -0,0 +1,106 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html 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href="neorv32_8h.html#aae182648a2c23d070b9db0295388e001">neorv32.h</a></li> +<li>CFS_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#a095f41fbefaa7acc1bfdd65cd3ce06ea">neorv32.h</a></li> +<li>CFS_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#aae6b2ae3fba20ff80bfb59735f179c26">neorv32.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_d.html b/sw/globals_defs_d.html new file mode 100644 index 000000000..d474b70fd --- /dev/null +++ b/sw/globals_defs_d.html @@ -0,0 +1,115 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> 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+</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" 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href="neorv32_8h.html#ace46f95dec73b33bf2535eb653bf8f65">neorv32.h</a></li> +<li>DMA_FIRQ_PENDING&#160;:&#160;<a class="el" href="neorv32_8h.html#a1fa2b25383e6d05cf26f3517091ddbbf">neorv32.h</a></li> +<li>DMA_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#a568b54ba7dfdae736d8d685dc4d32113">neorv32.h</a></li> +<li>DMA_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#ad2e81443af8a4ce2db3a4e3c1a8fb784">neorv32.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_e.html b/sw/globals_defs_e.html new file mode 100644 index 000000000..2a26f0b9f --- /dev/null +++ b/sw/globals_defs_e.html @@ -0,0 +1,102 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 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list of all documented macros with links to the documentation:</div> + +<h3><a id="index_f" name="index_f"></a>- f -</h3><ul> +<li>FLASH_ABYTES&#160;:&#160;<a class="el" href="demo__xip_2main_8c.html#af9b3c37c806499fc435302f5bce6a122">main.c</a></li> +<li>FLASH_BASE&#160;:&#160;<a class="el" href="demo__xip_2main_8c.html#a23a9099a5f8fc9c6e253c0eecb2be8db">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_g.html b/sw/globals_defs_g.html new file mode 100644 index 000000000..ffd777def --- /dev/null +++ b/sw/globals_defs_g.html @@ -0,0 +1,105 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 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href="neorv32_8h.html#aac38deeef36de0a474ab238a3054f860">neorv32.h</a></li> +<li>GPTMR_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#a445543c36d1f78477aa8ea4841c720a1">neorv32.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_i.html b/sw/globals_defs_i.html new file mode 100644 index 000000000..9def4966d --- /dev/null +++ b/sw/globals_defs_i.html @@ -0,0 +1,101 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" 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PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license 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+ onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_m" name="index_m"></a>- m -</h3><ul> +<li>MAX_DUTY&#160;:&#160;<a class="el" href="demo__pwm_2main_8c.html#a2351f30f0895b552e5fe9944d69e645d">main.c</a></li> +<li>MAX_INTENSITY&#160;:&#160;<a class="el" href="demo__neopixel_2main_8c.html#a1d1d5e7ff16f25b68fdf779befd298f7">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_n.html b/sw/globals_defs_n.html new file mode 100644 index 000000000..3abd05184 --- /dev/null +++ b/sw/globals_defs_n.html @@ -0,0 +1,155 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div 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href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ 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initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_p" name="index_p"></a>- p -</h3><ul> +<li>PRINT_GETC&#160;:&#160;<a class="el" href="bootloader_8c.html#a999b04603115ce08b0cb33e333312480">bootloader.c</a></li> +<li>PRINT_PUTC&#160;:&#160;<a class="el" href="bootloader_8c.html#aa7afbe8348ebd1a876a4d247553292e9">bootloader.c</a></li> +<li>PRINT_TEXT&#160;:&#160;<a class="el" href="bootloader_8c.html#a0e5a66f68ecc7a6f42088f349707e852">bootloader.c</a></li> +<li>PRINT_XNUM&#160;:&#160;<a class="el" href="bootloader_8c.html#a2f5cc04cf9c85f5d2958b384e053053b">bootloader.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_r.html b/sw/globals_defs_r.html new file mode 100644 index 000000000..d75174466 --- /dev/null +++ b/sw/globals_defs_r.html @@ -0,0 +1,111 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_r" name="index_r"></a>- r -</h3><ul> +<li>RUN_ADDSUB_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#a2d16b9e484b7af7897c7ae83f945ceca">main.c</a></li> +<li>RUN_CLASSIFY_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#a7e134923925fa24fd1090281c3a416c3">main.c</a></li> +<li>RUN_COMPARE_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#a4ee0f6d28896a97d2c0cad866e77b874">main.c</a></li> +<li>RUN_CONV_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#aa3b6c4d49be7372de9e771a0475306ac">main.c</a></li> +<li>RUN_CSR_TESTS&#160;:&#160;<a class="el" href="floating__point__test_2main_8c.html#a7ec330b668b5b24d666d7769ccecfee3">main.c</a></li> +<li>RUN_EXC_TESTS&#160;:&#160;<a class="el" href="floating__point__test_2main_8c.html#a1a1af220e72c69b03d13b2df53650e10">main.c</a></li> +<li>RUN_MINMAX_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#aed386f612417aeeeac8b08db27d515e4">main.c</a></li> +<li>RUN_MUL_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#a97323ecaf1ae85e68a736b06bc3b58f8">main.c</a></li> +<li>RUN_SGNINJ_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#a94f0b0908f48f383145ed61ef8eb0713">main.c</a></li> +<li>RUN_TIMING_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#a6969308bd3633928893a2666f1df66fc">main.c</a></li> +<li>RUN_UNAVAIL_TESTS&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#a923de9c3e55322d85522740c0d0ff867">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_s.html b/sw/globals_defs_s.html new file mode 100644 index 000000000..6afec1c93 --- /dev/null +++ b/sw/globals_defs_s.html @@ -0,0 +1,126 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_s" name="index_s"></a>- s -</h3><ul> +<li>SDI_FIRQ_ENABLE&#160;:&#160;<a class="el" href="neorv32_8h.html#a30cf20b6d704c50cc5c46238bb43646f">neorv32.h</a></li> +<li>SDI_FIRQ_PENDING&#160;:&#160;<a class="el" href="neorv32_8h.html#a68611c0dfbe331739eff10230ac3fede">neorv32.h</a></li> +<li>SDI_RTE_ID&#160;:&#160;<a class="el" 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+<li>SPI_FLASH_CLK_PRSC&#160;:&#160;<a class="el" href="bootloader_8c.html#a709071a651213770b4efe6e6e055ec3d">bootloader.c</a></li> +<li>SPI_FLASH_CS&#160;:&#160;<a class="el" href="bootloader_8c.html#aa2132454aada86216009f3af206899b1">bootloader.c</a></li> +<li>SPI_FLASH_SECTOR_SIZE&#160;:&#160;<a class="el" href="bootloader_8c.html#a00924a8ba223b2ca0e7031259b292c84">bootloader.c</a></li> +<li>SPI_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#a4c1cd9ec9f80da2080e5d0d35cc524dd">neorv32.h</a></li> +<li>SPI_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#a83c212f1f5d8ee2a5921b3b2b19e9cc4">neorv32.h</a></li> +<li>STATUS_LED_EN&#160;:&#160;<a class="el" href="bootloader_8c.html#aa9696325b450773c7a87c991abca3a54">bootloader.c</a></li> +<li>STATUS_LED_PIN&#160;:&#160;<a class="el" href="bootloader_8c.html#a089a71f836911c71b3f73fdd3b4b890b">bootloader.c</a></li> +<li>str&#160;:&#160;<a class="el" href="bootloader_8c.html#af6cf19e40e97afb5a7c29f7b439d091d">bootloader.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_t.html b/sw/globals_defs_t.html new file mode 100644 index 000000000..357a01f97 --- /dev/null +++ b/sw/globals_defs_t.html @@ -0,0 +1,109 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_t" name="index_t"></a>- t -</h3><ul> +<li>TESTCASES&#160;:&#160;<a class="el" href="demo__cfs_2main_8c.html#a906949f076e3e0d0082af3c3b1acb518">main.c</a></li> +<li>TRNG_FIRQ_ENABLE&#160;:&#160;<a class="el" href="neorv32_8h.html#a2896d832852c016eb85210b523642f11">neorv32.h</a></li> +<li>TRNG_FIRQ_PENDING&#160;:&#160;<a class="el" href="neorv32_8h.html#a9c387ca4e2736a27056c11819947c84a">neorv32.h</a></li> +<li>TRNG_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#afaa705a674acf3fd6c8cb294eaf11c5e">neorv32.h</a></li> +<li>TRNG_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#a11e34802c61a01fd6cba46e3f92d5ac1">neorv32.h</a></li> +<li>TWI_FIRQ_ENABLE&#160;:&#160;<a class="el" href="neorv32_8h.html#a0913144fce247e24ccd0f178b9ac32b7">neorv32.h</a></li> +<li>TWI_FIRQ_PENDING&#160;:&#160;<a class="el" href="neorv32_8h.html#a48b80113ca718fbdc50d75e1ec96a1ff">neorv32.h</a></li> +<li>TWI_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#a1ac29f2f7bace5ba92b2b68a4541a60c">neorv32.h</a></li> +<li>TWI_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#a0afc1a759116d4d73a199ef769bced47">neorv32.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_u.html b/sw/globals_defs_u.html new file mode 100644 index 000000000..202cccb13 --- /dev/null +++ b/sw/globals_defs_u.html @@ -0,0 +1,119 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html 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href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_u" name="index_u"></a>- u -</h3><ul> +<li>UART0_RX_FIRQ_ENABLE&#160;:&#160;<a class="el" href="neorv32_8h.html#a6b55ce6abe6b141000a6bb00949169e9">neorv32.h</a></li> +<li>UART0_RX_FIRQ_PENDING&#160;:&#160;<a class="el" href="neorv32_8h.html#a0b738b26abb2b951f1f5c5d9525d7701">neorv32.h</a></li> +<li>UART0_RX_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#ae8588cca20d5e36f74c5207c376389a1">neorv32.h</a></li> +<li>UART0_RX_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#a7a849638eff31f2e1955bdc53d4fc84d">neorv32.h</a></li> +<li>UART0_TX_FIRQ_ENABLE&#160;:&#160;<a class="el" href="neorv32_8h.html#aff756a395771f22c5f412f23f177ea7d">neorv32.h</a></li> +<li>UART0_TX_FIRQ_PENDING&#160;:&#160;<a class="el" href="neorv32_8h.html#addbe29166bb77bc045ad0e3db68e57e9">neorv32.h</a></li> +<li>UART0_TX_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#a9dc37695ca169bc0eb93898e7aeeee58">neorv32.h</a></li> +<li>UART0_TX_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#ab50df423fdba86bb83bc5d90a4c3bb20">neorv32.h</a></li> +<li>UART1_RX_FIRQ_ENABLE&#160;:&#160;<a class="el" href="neorv32_8h.html#a6c118c1784d8446360b00cde97437ca7">neorv32.h</a></li> +<li>UART1_RX_FIRQ_PENDING&#160;:&#160;<a class="el" href="neorv32_8h.html#a2e70d3a4e2973d224643813fcf315a20">neorv32.h</a></li> +<li>UART1_RX_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#ab1c351f5ea19ac9ea864155be9cc0b4b">neorv32.h</a></li> +<li>UART1_RX_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#ad0b9eb2ee1f411d7fccdf4fe263214e1">neorv32.h</a></li> +<li>UART1_TX_FIRQ_ENABLE&#160;:&#160;<a class="el" href="neorv32_8h.html#a0039bae3454a22e71d64e70d674f5d6a">neorv32.h</a></li> +<li>UART1_TX_FIRQ_PENDING&#160;:&#160;<a class="el" href="neorv32_8h.html#ac4060532b7aa390623f54720460a2680">neorv32.h</a></li> +<li>UART1_TX_RTE_ID&#160;:&#160;<a class="el" href="neorv32_8h.html#a6af270d7ae8b1cde30e44eb9142491d3">neorv32.h</a></li> +<li>UART1_TX_TRAP_CODE&#160;:&#160;<a class="el" href="neorv32_8h.html#a4cc50287c7a53982761a8116396ff7dd">neorv32.h</a></li> +<li>UART_BAUD&#160;:&#160;<a class="el" href="bootloader_8c.html#a1fac9153314479ad0ad495d752f0224a">bootloader.c</a></li> +<li>UART_EN&#160;:&#160;<a class="el" href="bootloader_8c.html#af1c2f103ac6e3183f08b39099fab2be9">bootloader.c</a></li> +<li>UART_HW_HANDSHAKE_EN&#160;:&#160;<a class="el" href="bootloader_8c.html#a20e93d623ce07939c3fdd53898f9d583">bootloader.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_w.html b/sw/globals_defs_w.html new file mode 100644 index 000000000..d48083279 --- /dev/null +++ b/sw/globals_defs_w.html @@ -0,0 +1,102 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_w" name="index_w"></a>- w -</h3><ul> +<li>WDT_PASSWORD&#160;:&#160;<a class="el" href="neorv32__wdt_8h.html#af2a2bd9c74bdba1b46bd92025bd00ab6">neorv32_wdt.h</a></li> +<li>WDT_TIMEOUT_S&#160;:&#160;<a class="el" href="demo__wdt_2main_8c.html#a01af3905e60b1869f669315f4a1297f5">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_defs_x.html b/sw/globals_defs_x.html new file mode 100644 index 000000000..adc8b76bc --- /dev/null +++ b/sw/globals_defs_x.html @@ -0,0 +1,113 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 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+<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented macros with links to the documentation:</div> + +<h3><a id="index_x" name="index_x"></a>- x -</h3><ul> +<li>XIP_CLK_PRSC&#160;:&#160;<a class="el" href="demo__xip_2main_8c.html#aec72efe062dbdb149ae6d4f8b1be6793">main.c</a></li> +<li>XIP_EN&#160;:&#160;<a class="el" href="bootloader_8c.html#a2cf31934b909299fb93bb5eebdbc7c9e">bootloader.c</a></li> +<li>XIP_MEM_BASE_ADDRESS&#160;:&#160;<a class="el" href="neorv32_8h.html#aa01bea676e878a9e87ca10ce2d91e51f">neorv32.h</a></li> +<li>XIRQ_FIRQ_ENABLE&#160;:&#160;<a class="el" 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+<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" 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id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license 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diff --git a/sw/globals_eval.html b/sw/globals_eval.html new file mode 100644 index 000000000..5e021af05 --- /dev/null +++ b/sw/globals_eval.html @@ -0,0 +1,334 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_c" name="index_c"></a>- c -</h3><ul> +<li>CLK_PRSC_1024&#160;:&#160;<a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a18aac15afd5ebd8d3a00dd6e513daf17">neorv32.h</a></li> +<li>CLK_PRSC_128&#160;:&#160;<a class="el" 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src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_eval_d.html b/sw/globals_eval_d.html new file mode 100644 index 000000000..2e21b19f0 --- /dev/null +++ b/sw/globals_eval_d.html @@ -0,0 +1,121 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_d" name="index_d"></a>- d -</h3><ul> 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b/sw/globals_eval_e.html new file mode 100644 index 000000000..b42cb7a04 --- /dev/null +++ b/sw/globals_eval_e.html @@ -0,0 +1,110 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_e" name="index_e"></a>- e -</h3><ul> +<li>ERROR_CHECKSUM&#160;:&#160;<a class="el" href="bootloader_8c.html#aa0c639898508ff8e4fab6290101f3088a471ebe6c0766abc6fa4e82a09bfdb985">bootloader.c</a></li> +<li>ERROR_FLASH&#160;:&#160;<a class="el" href="bootloader_8c.html#aa0c639898508ff8e4fab6290101f3088a684d6723fa25e7651e13d99fb249363c">bootloader.c</a></li> +<li>ERROR_SIGNATURE&#160;:&#160;<a class="el" href="bootloader_8c.html#aa0c639898508ff8e4fab6290101f3088ad41014563cb3ca69ab69b94d43e97caa">bootloader.c</a></li> +<li>ERROR_SIZE&#160;:&#160;<a class="el" href="bootloader_8c.html#aa0c639898508ff8e4fab6290101f3088a2d77ed1c715fb969a1faa01c71625f2d">bootloader.c</a></li> +<li>EXE_OFFSET_CHECKSUM&#160;:&#160;<a class="el" href="bootloader_8c.html#a165a347c51d8aae06a564a2f297f2febabc27a855096a70dca0f8bc148a123be4">bootloader.c</a></li> +<li>EXE_OFFSET_DATA&#160;:&#160;<a class="el" href="bootloader_8c.html#a165a347c51d8aae06a564a2f297f2febaea032c54a21057710ef2021638972ce6">bootloader.c</a></li> +<li>EXE_OFFSET_SIGNATURE&#160;:&#160;<a class="el" href="bootloader_8c.html#a165a347c51d8aae06a564a2f297f2feba61100996f309c45b8b628ade2e3acc7f">bootloader.c</a></li> +<li>EXE_OFFSET_SIZE&#160;:&#160;<a class="el" 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Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_f" name="index_f"></a>- f -</h3><ul> +<li>FLASH_SREG_BUSY&#160;:&#160;<a class="el" href="bootloader_8c.html#a97299f563ebc1fca4c663b025a15136fa133cd87673ce9a612da494583e03dae9">bootloader.c</a></li> +<li>FLASH_SREG_WEL&#160;:&#160;<a class="el" href="bootloader_8c.html#a97299f563ebc1fca4c663b025a15136fa22e8c983d74430ea0930e37781e88bf9">bootloader.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_eval_g.html b/sw/globals_eval_g.html new file mode 100644 index 000000000..2074a8d93 --- /dev/null +++ b/sw/globals_eval_g.html @@ -0,0 +1,107 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all 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src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_o" name="index_o"></a>- o -</h3><ul> +<li>ONEWIRE_CTRL_BUSY&#160;:&#160;<a class="el" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aac8933755e80d72e1e9c293198d831b9">neorv32_onewire.h</a></li> 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"-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" 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class="el" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175af5d9dcb5740c39cfe8f9bfb5c1b66341">neorv32_pwm.h</a></li> +<li>PWM_CFG_EN&#160;:&#160;<a class="el" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a2b766bfa9653705025b745e0809c432a">neorv32_pwm.h</a></li> +<li>PWM_CFG_PRSC_LSB&#160;:&#160;<a class="el" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175aefe2211fe39acffb40ca738639b3d5f5">neorv32_pwm.h</a></li> +<li>PWM_CFG_PRSC_MSB&#160;:&#160;<a class="el" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175aa100b419699cd3c6787a9168a3ffec3d">neorv32_pwm.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_eval_r.html b/sw/globals_eval_r.html new file mode 100644 index 000000000..774662fd4 --- /dev/null +++ b/sw/globals_eval_r.html @@ -0,0 +1,129 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_r" name="index_r"></a>- r -</h3><ul> +<li>RTE_TRAP_BREAKPOINT&#160;:&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa463611404367b5910c42dd31c0a218a2">neorv32_rte.h</a></li> +<li>RTE_TRAP_FIRQ_0&#160;:&#160;<a class="el" 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href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aacf17d4b2454c43a1cb544e532d247fff">neorv32_rte.h</a></li> +<li>RTE_TRAP_S_ACCESS&#160;:&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaa9b8334712ecad0500c7610a25741ec7">neorv32_rte.h</a></li> +<li>RTE_TRAP_S_MISALIGNED&#160;:&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa85934b3fd8b5268340f84810b3f67232">neorv32_rte.h</a></li> +<li>RTE_TRAP_UENV_CALL&#160;:&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa155f84a52bace69f81a99de59701decc">neorv32_rte.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_eval_s.html b/sw/globals_eval_s.html new file mode 100644 index 000000000..bc18aea6d --- /dev/null +++ b/sw/globals_eval_s.html @@ -0,0 +1,226 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_s" name="index_s"></a>- s -</h3><ul> +<li>SDI_CTRL_CS_ACTIVE&#160;:&#160;<a class="el" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ad288a52f2bdaa1ea6ddbadf7f32a3a63">neorv32_sdi.h</a></li> +<li>SDI_CTRL_EN&#160;:&#160;<a class="el" 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a/sw/globals_eval_t.html b/sw/globals_eval_t.html new file mode 100644 index 000000000..9a9b4bfd0 --- /dev/null +++ b/sw/globals_eval_t.html @@ -0,0 +1,157 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_t" name="index_t"></a>- t -</h3><ul> +<li>TRAP_CODE_BREAKPOINT&#160;:&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a2c9510cb7583a0144f96678fc217335e">neorv32_cpu_csr.h</a></li> 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<td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented enum values with links to the documentation:</div> + +<h3><a id="index_u" name="index_u"></a>- u -</h3><ul> +<li>UART_CTRL_BAUD0&#160;:&#160;<a class="el" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcad38432e7e050276d4667daf92c1e3fd5">neorv32_uart.h</a></li> +<li>UART_CTRL_BAUD1&#160;:&#160;<a class="el" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca1e702002402897eca82bf398504bc439">neorv32_uart.h</a></li> +<li>UART_CTRL_BAUD2&#160;:&#160;<a class="el" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca36266026e11f22aca1584bd81cd38cd6">neorv32_uart.h</a></li> +<li>UART_CTRL_BAUD3&#160;:&#160;<a class="el" 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class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_a.html b/sw/globals_func_a.html new file mode 100644 index 000000000..6bec563e5 --- /dev/null +++ b/sw/globals_func_a.html @@ -0,0 +1,102 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script 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MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented functions with links to the documentation:</div> + +<h3><a id="index_c" name="index_c"></a>- c -</h3><ul> +<li>check_result()&#160;:&#160;<a class="el" href="atomic__test_2main_8c.html#a4f4c6d8481b4100f90955ba5a70428a4">main.c</a></li> +<li>clear_universe()&#160;:&#160;<a class="el" href="game__of__life_2main_8c.html#a819f10c5b644a07eeb069b6e7f12050e">main.c</a></li> +<li>compute_rate()&#160;:&#160;<a class="el" href="demo__trng_2main_8c.html#abbde1237eed617466fb971a78c3acd1e">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_d.html b/sw/globals_func_d.html new file mode 100644 index 000000000..066ea2408 --- /dev/null +++ b/sw/globals_func_d.html @@ -0,0 +1,102 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta 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--> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div 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src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented functions with links to the documentation:</div> + +<h3><a id="index_g" name="index_g"></a>- g -</h3><ul> +<li>generate_histogram()&#160;:&#160;<a class="el" href="demo__trng_2main_8c.html#a4e49f5e3feb4bd5755f919cd3310b506">main.c</a></li> +<li>get_cell()&#160;:&#160;<a class="el" href="game__of__life_2main_8c.html#a6bd541a19c62ea9ec620eaad3f218d16">main.c</a></li> +<li>get_exe()&#160;:&#160;<a class="el" href="bootloader_8c.html#ac18819795adb6dbdd52b0587e7fbb569">bootloader.c</a></li> +<li>get_exe_word()&#160;:&#160;<a class="el" href="bootloader_8c.html#ac58d9f7dc79a549bde1cb50f619c19af">bootloader.c</a></li> +<li>get_neighborhood()&#160;:&#160;<a class="el" href="game__of__life_2main_8c.html#a977190adaa24a3f49fca1540b51d25a0">main.c</a></li> +<li>get_test_vector()&#160;:&#160;<a class="el" href="float__corner__test_2main_8c.html#a73c70bd0fb6d695cb113eaeb50923e3e">main.c</a></li> +<li>global_trap_handler()&#160;:&#160;<a class="el" href="processor__check_2main_8c.html#a9a64ce0ee69c4c32cecc8b2b2746604c">main.c</a></li> +<li>gptmr_firq_handler()&#160;:&#160;<a class="el" href="demo__gptmr_2main_8c.html#a2bd89412466a65329711bfd5c29199c9">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_h.html b/sw/globals_func_h.html new file mode 100644 index 000000000..31db95f6e --- /dev/null +++ b/sw/globals_func_h.html @@ -0,0 +1,103 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div 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id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented functions with links to the documentation:</div> + +<h3><a id="index_h" name="index_h"></a>- h -</h3><ul> +<li>hexdump()&#160;:&#160;<a class="el" href="bus__explorer_2main_8c.html#a02640a99db37b8d92b9edffc9720a210">main.c</a></li> +<li>hsv2rgb()&#160;:&#160;<a class="el" href="demo__neopixel_2main_8c.html#a2736ec755f9e10c80bf66f727f870ffc">main.c</a></li> +<li>hw_breakpoint_handler()&#160;:&#160;<a class="el" href="processor__check_2main_8c.html#a31d9e432f6a368e6222f5e0907eeb6f4">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_m.html b/sw/globals_func_m.html new file mode 100644 index 000000000..3c68cafb1 --- /dev/null +++ b/sw/globals_func_m.html @@ -0,0 +1,103 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license 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+<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license 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diff --git a/sw/globals_func_p.html b/sw/globals_func_p.html new file mode 100644 index 000000000..ce22d3873 --- /dev/null +++ b/sw/globals_func_p.html @@ -0,0 +1,107 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented functions with links to the documentation:</div> + +<h3><a id="index_p" name="index_p"></a>- p -</h3><ul> +<li>pop_count()&#160;:&#160;<a class="el" href="game__of__life_2main_8c.html#aac4bec7738b12f5a4b4d7a3a6cb1ab8d">main.c</a></li> +<li>print_help()&#160;:&#160;<a class="el" href="bootloader_8c.html#a402ea961bfc2ffeee61e3a7c330b1559">bootloader.c</a></li> +<li>print_hex_byte()&#160;:&#160;<a class="el" href="demo__twi_2main_8c.html#a2ebc688bc1dad328693fc0974b378fa0">main.c</a></li> +<li>print_hex_word()&#160;:&#160;<a class="el" href="bootloader_8c.html#a70b7d5c3b3ae97e4e72e84c4bc28fb8a">bootloader.c</a></li> +<li>print_random_data()&#160;:&#160;<a class="el" href="demo__trng_2main_8c.html#a64205d97b57c99dc5e95b8621827f4a4">main.c</a></li> +<li>print_report()&#160;:&#160;<a class="el" href="atomic__test_2main_8c.html#a99377a057d14aaa9b45f8cab890e8cf7">main.c</a></li> +<li>print_universe()&#160;:&#160;<a class="el" href="game__of__life_2main_8c.html#a9a455dea83a25f656fcc5217ad513dac">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_r.html b/sw/globals_func_r.html new file mode 100644 index 000000000..34cd69cd4 --- /dev/null +++ b/sw/globals_func_r.html @@ -0,0 +1,148 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented functions with links to the documentation:</div> + +<h3><a id="index_r" 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+</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_s.html b/sw/globals_func_s.html new file mode 100644 index 000000000..8c72d59df --- /dev/null +++ b/sw/globals_func_s.html @@ -0,0 +1,131 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented functions with links to the documentation:</div> + +<h3><a id="index_s" name="index_s"></a>- s -</h3><ul> +<li>save_exe()&#160;:&#160;<a class="el" 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href="bootloader_8c.html#a3bdfe2f25b1bfb42f80624ffff22ab01">bootloader.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_t.html b/sw/globals_func_t.html new file mode 100644 index 000000000..3e5ff3edc --- /dev/null +++ b/sw/globals_func_t.html @@ -0,0 +1,105 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, 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with links to the documentation:</div> + +<h3><a id="index_u" name="index_u"></a>- u -</h3><ul> +<li>uart_get_executable()&#160;:&#160;<a class="el" href="demo__xip_2main_8c.html#a0458656f8a108ff31f4bbbd005f029a0">main.c</a></li> +<li>uart_get_word()&#160;:&#160;<a class="el" href="demo__xip_2main_8c.html#a3043d09bdc155f57f45cd91e0cd4d15b">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_v.html b/sw/globals_func_v.html new file mode 100644 index 000000000..f29e417c7 --- /dev/null +++ b/sw/globals_func_v.html @@ -0,0 +1,104 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html 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href="float__corner__test_2main_8c.html#a941ef8d24fd8e8fe4536626b2ce72410">main.c</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_func_w.html b/sw/globals_func_w.html new file mode 100644 index 000000000..b0c619738 --- /dev/null +++ b/sw/globals_func_w.html @@ -0,0 +1,102 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" 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--> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/globals_o.html b/sw/globals_o.html new file mode 100644 index 000000000..7391c5cc3 --- /dev/null +++ b/sw/globals_o.html @@ -0,0 +1,123 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div 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functions, variables, defines, enums, and typedefs with links to the documentation:</div> + +<h3><a id="index_o" name="index_o"></a>- o -</h3><ul> +<li>ONEWIRE_CTRL_BUSY&#160;:&#160;<a class="el" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aac8933755e80d72e1e9c293198d831b9">neorv32_onewire.h</a></li> +<li>ONEWIRE_CTRL_CLKDIV0&#160;:&#160;<a class="el" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831acdfca08f34d7379aaf8505ba3425c6f5">neorv32_onewire.h</a></li> +<li>ONEWIRE_CTRL_CLKDIV1&#160;:&#160;<a class="el" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831afa1476a5e04eb4eabf4d7a595eca2df9">neorv32_onewire.h</a></li> +<li>ONEWIRE_CTRL_CLKDIV2&#160;:&#160;<a class="el" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aec9f056072e1db747e74a5c695d2a1df">neorv32_onewire.h</a></li> +<li>ONEWIRE_CTRL_CLKDIV3&#160;:&#160;<a class="el" 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href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +</div><!-- top --> +<div id="doc-content"> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div> + +<h3><a id="index_s" name="index_s"></a>- s -</h3><ul> +<li>save_exe()&#160;:&#160;<a class="el" href="bootloader_8c.html#ababfffe8e7036179e150ad3b9bda3a74">bootloader.c</a></li> +<li>scan_bus()&#160;:&#160;<a class="el" href="demo__onewire_2main_8c.html#ac07c9cfd80ac2e24be9dac6cf943b7de">main.c</a></li> +<li>scan_twi()&#160;:&#160;<a class="el" href="demo__twi_2main_8c.html#aace46ee34e954f9ebee5873beb0785f1">main.c</a></li> +<li>SDI_CTRL_CS_ACTIVE&#160;:&#160;<a class="el" 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"https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT 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"-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license 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not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script 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class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_d4640980cbf1943e4a4aee6e8b810c7a.html">hello_world</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">main.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Classic 'hello world' demo program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4455691936f92fdd6c37566fc58ba1f">BAUD_RATE</a>&#160;&#160;&#160;19200</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4" id="r_ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr> +<tr class="separator:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Classic 'hello world' demo program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4455691936f92fdd6c37566fc58ba1f">&#9670;&#160;</a></span>BAUD_RATE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define BAUD_RATE&#160;&#160;&#160;19200</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART BAUD rate </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Main function; prints some fancy stuff via UART.</p> +<dl class="section note"><dt>Note</dt><dd>This program requires the UART interface to be synthesized.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address 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tipContent;if(!element.data(DATA_HASACTIVEHOVER)){return}if( +session.isTipOpen){if(!session.isClosing){hideTip(session.activeHover)}tipElement.delay(100).queue(function queueTipAgain(next){showTip(element);next()});return}element.trigger("powerTipPreRender");tipContent=getTooltipContent(element);if(tipContent){tipElement.empty().append(tipContent)}else{return}element.trigger("powerTipRender");session.activeHover=element;session.isTipOpen=true;tipElement.data(DATA_MOUSEONTOTIP,options.mouseOnToPopup);tipElement.addClass(options.popupClass);if(!options.followMouse||element.data(DATA_FORCEDOPEN)){positionTipOnElement(element);session.isFixedTipOpen=true}else{positionTipOnCursor()}if(!element.data(DATA_FORCEDOPEN)&&!options.followMouse){$document.on("click"+EVENT_NAMESPACE,function documentClick(event){var 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t=$(this);0==t.attr("id" +).indexOf(i.accessIdPrefix)&&t.removeAttr("id")}).removeClass("has-submenu").removeDataSM("sub").removeAttr("aria-haspopup").removeAttr("aria-controls").removeAttr("aria-expanded").closest("li").removeDataSM("sub"),this.opts.subIndicators&&this.$root.find("span.sub-arrow").remove(),this.opts.markCurrentItem&&this.$root.find("a.current").removeClass("current"),t||(this.$root=null,this.$firstLink=null,this.$firstSub=null,this.$disableOverlay&&(this.$disableOverlay.remove(),this.$disableOverlay=null),menuTrees.splice($.inArray(this,menuTrees),1))},disable:function(t){if(!this.disabled){if(this.menuHideAll(),!t&&!this.opts.isPopup&&this.$root.is(":visible")){var e=this.$root.offset();this.$disableOverlay=$('<div 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i=this.activatedItems[e].dataSM("sub");i&&this.menuHide(i)}},menuInit:function(t){if(!t.dataSM("in-mega")){ +t.hasClass("mega-menu")&&t.find("ul").dataSM("in-mega",!0);for(var e=2,i=t[0];(i=i.parentNode.parentNode)!=this.$root[0];)e++;var s=t.prevAll("a").eq(-1);s.length||(s=t.prevAll().find("a").eq(-1)),s.addClass("has-submenu").dataSM("sub",t),t.dataSM("parent-a",s).dataSM("level",e).parent().dataSM("sub",t);var o=s.attr("id")||this.accessIdPrefix+ ++this.idInc,a=t.attr("id")||this.accessIdPrefix+ ++this.idInc;s.attr({id:o,"aria-haspopup":"true","aria-controls":a,"aria-expanded":"false"}),t.attr({id:a,role:"group","aria-hidden":"true","aria-labelledby":o,"aria-expanded":"false"}),this.opts.subIndicators&&s[this.opts.subIndicatorsPos](this.$subArrow.clone())}},menuPosition:function(t){var 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e=t.dataSM("scroll"),i=$(window).scrollTop()-t.dataSM("parent-a").offset().top-e.itemH;this.cssTransforms3d&&(i=-(parseFloat(t.css("margin-top"))-i)),$.extend(e,{upEnd:i, +downEnd:i+this.getViewportHeight()-e.subH})},menuScrollStop:function(t){return this.scrollTimeout?(cancelAnimationFrame(this.scrollTimeout),this.scrollTimeout=0,t.dataSM("scroll").step=1,!0):void 0},menuScrollTouch:function(t,e){if(e=e.originalEvent,isTouchEvent(e)){var i=this.getTouchPoint(e);if(this.getClosestMenu(i.target)==t[0]){var s=t.dataSM("scroll");if(/(start|down)$/i.test(e.type))this.menuScrollStop(t)?(e.preventDefault(),this.$touchScrollingSub=t):this.$touchScrollingSub=null,this.menuScrollRefreshData(t),$.extend(s,{touchStartY:i.pageY,touchStartTime:e.timeStamp});else if(/move$/i.test(e.type)){var o=void 0!==s.touchY?s.touchY:s.touchStartY;if(void 0!==o&&o!=i.pageY){this.$touchScrollingSub=t;var a=i.pageY>o;void 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src="https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&amp;style=flat-square&amp;logo=asciidoctor&amp;colorA=273274" alt="datasheet (pdf)" class="inline"/></a> <a href="https://stnolting.github.io/neorv32"><img src="https://img.shields.io/badge/-HTML-ffbd00?longCache=true&amp;style=flat-square" alt="datasheet (html)" class="inline"/></a> <a href="https://github.com/stnolting/neorv32/releases/tag/nightly"><img src="https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&amp;style=flat-square&amp;logo=asciidoctor&amp;colorA=273274" alt="userguide (pdf)" class="inline"/></a> <a href="https://stnolting.github.io/neorv32/ug"><img src="https://img.shields.io/badge/-HTML-ffbd00?longCache=true&amp;style=flat-square" alt="userguide (html)" class="inline"/></a> <a href="https://stnolting.github.io/neorv32/sw/files.html"><img src="https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&amp;style=flat-square&amp;logo=Doxygen&amp;colorA=273274" alt="doxygen" class="inline"/></a></p> +<ol type="1"> +<li>Overview<ul> +<li>Key Features</li> +<li>Project Status</li> +</ul> +</li> +<li>Features</li> +<li>FPGA Implementation Results</li> +<li>Performance</li> +<li>**Getting Started** :rocket:</li> +</ol> +<h2><a class="anchor" id="autotoc_md1"></a> +1. Overview</h2> +<p><img src="docs/figures/neorv32_processor.png" alt="neorv32 Overview" class="inline"/></p> +<p>The NEORV32 Processor is a <b>customizable microcontroller-like system on chip (SoC)</b> built around the NEORV32 <a href="https://riscv.org/">RISC-V</a> CPU that is written in <b>platform-independent VHDL</b>. The processor is intended as auxiliary controller in larger SoC designs or as tiny and customized microcontroller that even fits into a Lattice iCE40 UltraPlus low-power &amp; low-density FPGA. The project is intended to work <em>out of the box</em> and targets FPGA / RISC-V beginners as well as advanced users.</p> +<p>Special focus is paid on <b>execution safety</b> to provide defined and predictable behavior at any time. For example, the CPU ensures <em>all</em> memory accesses are properly acknowledged and <em>all</em> invalid/malformed instructions are always detected as such. Whenever an unexpected state occurs the application software is informed via <em>precise</em> and resumable hardware exceptions.</p> +<ul> +<li>:recycle: Looking for an <b>all-Verilog</b> version? Have a look at <a href="https://github.com/stnolting/neorv32-verilog">neorv32-verilog</a>.</li> +<li>:heavy_check_mark: Continuous integration to check for regressions (including RISC-V ISA compatibility check using <b>RISCOF</b>).</li> +<li>:open_file_folder: <a href="https://github.com/stnolting/neorv32-setups">Exemplary setups</a> and <a href="https://github.com/stnolting/neorv32-setups/blob/main/README.md#Community-Projects">community projects</a> targeting various FPGA boards and toolchains to get started.</li> +<li>:package: The entire processor is also available as <a href="https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block">Vivado IP Block</a>.</li> +<li>:kite: Support for <a href="https://github.com/stnolting/neorv32-freertos">FreeRTOS</a>, <a href="https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html">Zephyr OS</a> and <a href="https://github.com/enjoy-digital/litex/wiki/CPUs#risc-v---neorv32">LiteX</a> SoC Builder Framework.</li> +<li>:desktop_computer: Pre-configured <a href="https://stnolting.github.io/neorv32/ug/#_eclipse_ide">Eclipse project</a> for developing and debugging code using an IDE.</li> +<li>:label: The project's change log is available in <a href="https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md">CHANGELOG.md</a>.</li> +<li>:rocket: Check out the quick links below and the <a href="https://stnolting.github.io/neorv32/ug/"><em>User Guide</em></a> to get started setting up <em>your</em> NEORV32 processor!</li> +<li>:books: For detailed information see the <a href="https://stnolting.github.io/neorv32/">NEORV32 online documentation</a>.</li> +<li>:interrobang: Want to know more? Check out the <a href="https://stnolting.github.io/neorv32/#_rationale">project's rationale</a>.</li> +</ul> +<p>Feel free to open a new <a href="https://github.com/stnolting/neorv32/issues">issue</a> or start a new <a href="https://github.com/stnolting/neorv32/discussions">discussion</a> if you have questions, comments, ideas, feedback or if something is not working as expected. See how to <a href="https://github.com/stnolting/neorv32/blob/main/CONTRIBUTING.md">contribute</a>.</p> +<h3><a class="anchor" id="autotoc_md2"></a> +Key Features</h3> +<ul class="check"> +<li class="checked">all-in-one package: <b>CPU</b> + <b>SoC</b> + <b>Software Framework &amp; Tooling</b></li> +</ul> +<ul class="check"> +<li class="checked">completely described in behavioral, platform-independent VHDL - <b>no</b> platform-specific primitives, macros, attributes, etc.; an all-Verilog "version" is also <a href="https://github.com/stnolting/neorv32-verilog">available</a></li> +</ul> +<ul class="check"> +<li class="checked">extensive configuration options for adapting the processor to the requirements of the application</li> +</ul> +<ul class="check"> +<li class="checked">highly <a href="https://stnolting.github.io/neorv32/ug/#_comparative_summary">extensible hardware</a> - on CPU, processor and system level</li> +</ul> +<ul class="check"> +<li class="checked">aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off</li> +</ul> +<ul class="check"> +<li class="checked">FPGA friendly (e.g. <em>all</em> internal memories can be mapped to block RAM - including the CPU's register file)</li> +</ul> +<ul class="check"> +<li class="checked">optimized for high clock frequencies to ease integration / timing closure</li> +</ul> +<ul class="check"> +<li class="checked">from zero to <em>"hello world!"</em> - completely open source and documented</li> +</ul> +<ul class="check"> +<li class="checked">highly documented - on software and hardware side</li> +</ul> +<ul class="check"> +<li class="checked">easy to use even for FPGA / RISC-V starters โ€“ intended to work <em>out of the box</em></li> +</ul> +<h3><a class="anchor" id="autotoc_md3"></a> +Project Status</h3> +<p><a href="https://github.com/stnolting/neorv32/releases"><img src="https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&amp;style=flat-square&amp;logo=GitHub" alt="release" class="inline"/></a> <a href="https://github.com/stnolting/neorv32/activity"><img src="https://img.shields.io/github/commits-since/stnolting/neorv32/latest?longCache=true&amp;style=flat-square&amp;logo=GitHub" alt="commits-since-latest-release" class="inline"/></a></p> +<table class="markdownTable"> +<tr class="markdownTableHead"> +<th class="markdownTableHeadLeft">Task / Subproject </th><th class="markdownTableHeadLeft">Repository </th><th class="markdownTableHeadLeft">CI Status </th></tr> +<tr class="markdownTableRowOdd"> +<td class="markdownTableBodyLeft">GitHub pages (docs) </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32">neorv32</a> </td><td class="markdownTableBodyLeft"><a href="https://stnolting.github.io/neorv32"><img src="https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&amp;longCache=true&amp;style=flat-square&amp;url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&amp;logo=GitHub" alt="GitHub Pages" style="pointer-events: none;" class="inline"/></a> </td></tr> +<tr class="markdownTableRowEven"> +<td class="markdownTableBodyLeft">Build documentation </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32">neorv32</a> </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation"><img src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Documentation.yml?branch=main&amp;longCache=true&amp;style=flat-square&amp;label=Documentation&amp;logo=Github%20Actions&amp;logoColor=fff" alt="Documentation" class="inline"/></a> </td></tr> +<tr class="markdownTableRowOdd"> +<td class="markdownTableBodyLeft">Processor verification </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32">neorv32</a> </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor"><img src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Processor.yml?branch=main&amp;longCache=true&amp;style=flat-square&amp;label=Processor%20Check&amp;logo=Github%20Actions&amp;logoColor=fff" alt="Processor" class="inline"/></a> </td></tr> +<tr class="markdownTableRowEven"> +<td class="markdownTableBodyLeft">RISCOF core verification </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32-riscof">neorv32-riscof</a> </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml"><img src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-riscof/main.yml?branch=main&amp;longCache=true&amp;style=flat-square&amp;label=neorv32-riscof&amp;logo=Github%20Actions&amp;logoColor=fff" alt="neorv32-riscof" class="inline"/></a> </td></tr> +<tr class="markdownTableRowOdd"> +<td class="markdownTableBodyLeft">FPGA implementations </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32-setups">neorv32-setups</a> </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation"><img src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-setups/Implementation.yml?branch=main&amp;longCache=true&amp;style=flat-square&amp;label=Implementation&amp;logo=Github%20Actions&amp;logoColor=fff" alt="Implementation" class="inline"/></a> </td></tr> +<tr class="markdownTableRowEven"> +<td class="markdownTableBodyLeft">All-Verilog version </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32-verilog">neorv32-verilog</a> </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32-verilog/actions/workflows/main.yml"><img src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-verilog/main.yml?branch=main&amp;longCache=true&amp;style=flat-square&amp;label=neorv32-verilog&amp;logo=Github%20Actions&amp;logoColor=fff" alt="neorv32-verilog" class="inline"/></a> </td></tr> +<tr class="markdownTableRowOdd"> +<td class="markdownTableBodyLeft">FreeRTOS port </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32-freertos">neorv32-freertos</a> </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/neorv32-freertos/actions/workflows/main.yml"><img src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-freertos/main.yml?branch=main&amp;longCache=true&amp;style=flat-square&amp;label=neorv32-freertos%20sim&amp;logo=Github%20Actions&amp;logoColor=fff" alt="neorv32-freertos" class="inline"/></a> </td></tr> +<tr class="markdownTableRowEven"> +<td class="markdownTableBodyLeft">Prebuilt GCC toolchains </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/riscv-gcc-prebuilt">riscv-gcc-prebuilt</a> </td><td class="markdownTableBodyLeft"><a href="https://github.com/stnolting/riscv-gcc-prebuilt/actions/workflows/main.yml"><img src="https://img.shields.io/github/actions/workflow/status/stnolting/riscv-gcc-prebuilt/main.yml?branch=main&amp;longCache=true&amp;style=flat-square&amp;label=Prebuilt%20Toolchains&amp;logo=Github%20Actions&amp;logoColor=fff" alt="Prebuilt_Toolchains" class="inline"/></a> </td></tr> +</table> +<p>The processor passes the official RISC-V architecture tests to ensure compatibility with the RISC-V ISA specs., which is checked by the <a href="https://github.com/stnolting/neorv32-riscof">neorv32-riscof</a> repository. It can successfully run <em>any</em> C program (for example from the <a href="https://github.com/stnolting/neorv32/tree/main/sw/example"><code>sw/example</code></a> folder) including CoreMark and FreeRTOS and can be synthesized for <em>any</em> target technology - <a href="https://github.com/stnolting/neorv32-setups">tested</a> on Intel, AMD, Cologne Chip and Lattice FPGAs. The conversion into a single, plain-Verilog module file is automatically checked by the <a href="https://github.com/stnolting/neorv32-verilog">neorv32-verilog</a> repository.</p> +<h2><a class="anchor" id="autotoc_md4"></a> +2. Features</h2> +<p>The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. By using generics the design is highly configurable and allows a flexible customization to tailor the setup according to your needs. Note that all of the following SoC modules are entirely <em>optional</em>.</p> +<p><b>CPU Core</b></p> +<ul> +<li><a href="https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md"><img src="https://img.shields.io/badge/RISC--V%20Architecture%20ID-19-000000.svg?longCache=true&amp;style=flat-square&amp;logo=riscv&amp;colorA=273274&amp;colorB=fbb517" alt="RISCV-ARCHID" style="pointer-events: none;" class="inline"/></a></li> +<li>RISC-V 32-bit little-endian single-core pipelined/multi-cycle modified Harvard architecture</li> +<li>configurable <a href="https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions">instruction sets and extensions</a>: \ <code>RV32</code> [<a href="https://stnolting.github.io/neorv32/#_i_isa_extension"><code>I</code></a>/<a href="https://stnolting.github.io/neorv32/#_e_isa_extension"><code>E</code></a>] [<a href="https://stnolting.github.io/neorv32/#_m_isa_extension"><code>M</code></a>] [<a href="https://stnolting.github.io/neorv32/#_c_isa_extension"><code>C</code></a>] [<a href="https://stnolting.github.io/neorv32/#_b_isa_extension"><code>B</code></a>] [<a href="https://stnolting.github.io/neorv32/#_u_isa_extension"><code>U</code></a>] [<a href="https://stnolting.github.io/neorv32/#_x_isa_extension"><code>X</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zalrsc_isa_extension"><code>Zalrsc</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zba_isa_extension"><code>Zba</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbb_isa_extension"><code>Zbb</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbkb_isa_extension"><code>Zbkb</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbkc_isa_extension"><code>Zbkc</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbkx_isa_extension"><code>Zbkx</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbs_isa_extension"><code>Zbs</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zicntr_isa_extension"><code>Zicntr</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zicond_isa_extension"><code>Zicond</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zicsr_isa_extension"><code>Zicsr</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zifencei_isa_extension"><code>Zifencei</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zihpm_isa_extension"><code>Zihpm</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zfinx_isa_extension"><code>Zfinx</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zkn_isa_extension"><code>Zkn</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zknd_isa_extension"><code>Zknd</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zkne_isa_extension"><code>Zkne</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zknh_isa_extension"><code>Zknh</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zkt_isa_extension"><code>Zkt</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zks_isa_extension"><code>Zks</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zksed_isa_extension"><code>Zksed</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zksh_isa_extension"><code>Zksh</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zmmul_isa_extension"><code>Zmmul</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zxcfu_isa_extension"><code>Zxcfu</code></a>] [<a href="https://stnolting.github.io/neorv32/#_sdext_isa_extension"><code>Sdext</code></a>] [<a href="https://stnolting.github.io/neorv32/#_sdtrig_isa_extension"><code>Sdtrig</code></a>] [<a href="https://stnolting.github.io/neorv32/#_smpmp_isa_extension"><code>Smpmp</code></a>]</li> +<li>compatible to subsets of the RISC-V <em>Unprivileged ISA Specification</em> (<a href="https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf">pdf</a>) and <em>Privileged Architecture Specification</em> (<a href="https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf">pdf</a>).</li> +<li><code>machine</code> and <code>user</code> privilege modes</li> +<li>implements <b>all</b> standard RISC-V exceptions and interrupts + 16 fast interrupt request channels as NEORV32-specific extension</li> +<li>custom functions unit (<a href="https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu">CFU</a> as <code>Zxcfu</code> ISA extension) for <b>custom RISC-V instructions</b>;</li> +<li><em>intrinsic</em> libraries for CPU extensions that are not yet supported by GCC</li> +</ul> +<p><b>Memories</b></p> +<ul> +<li>processor-internal data and instruction memories (<a href="https://stnolting.github.io/neorv32/#_data_memory_dmem">DMEM</a> / <a href="https://stnolting.github.io/neorv32/#_instruction_memory_imem">IMEM</a>) &amp; caches (<a href="https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache">iCACHE</a> and <a href="https://stnolting.github.io/neorv32/#_processor_internal_data_cache_dcache">dCACHE</a>)</li> +<li>pre-installed bootloader (<a href="https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom">BOOTLDROM</a>) with serial user interface; allows booting application code via UART or from external SPI flash</li> +</ul> +<p><b>Timers and Counters</b></p> +<ul> +<li>64-bit machine timer (<a href="https://stnolting.github.io/neorv32/#_machine_system_timer_mtime">MTIME</a>), RISC-V spec. compatible</li> +<li>32-bit general purpose timer (<a href="https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr">GPTMR</a>)</li> +<li>watchdog timer (<a href="https://stnolting.github.io/neorv32/#_watchdog_timer_wdt">WDT</a>)</li> +</ul> +<p><b>Input / Output</b></p> +<ul> +<li>standard serial interfaces (<a href="https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0">UART</a>, <a href="https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi">SPI</a> (SPI host), <a href="https://stnolting.github.io/neorv32/#_serial_data_interface_controller_sdi">SDI</a> (SPI device), <a href="https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi">TWI/IยฒC</a>, <a href="https://stnolting.github.io/neorv32/#_one_wire_serial_interface_controller_onewire">ONEWIRE/1-Wire</a>)</li> +<li>general purpose IOs (<a href="https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio">GPIO</a>) and <a href="https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm">PWM</a></li> +<li>smart LED interface (<a href="https://stnolting.github.io/neorv32/#_smart_led_interface_neoled">NEOLED</a>) to directly control NeoPixel(TM) LEDs</li> +</ul> +<p><b>SoC Connectivity</b></p> +<ul> +<li>32-bit external bus interface - Wishbone b4 compatible (<a href="https://stnolting.github.io/neorv32/#_processor_external_bus_interface_xbus">XBUS</a>) with optional cache (XCACHE); <a href="https://github.com/stnolting/neorv32/blob/main/rtl/system_integration">wrappers</a> for AXI4-Lite and Avalon-MM host interfaces</li> +<li>stream link interface with independent RX and TX channels - AXI4-Stream compatible (<a href="https://stnolting.github.io/neorv32/#_stream_link_interface_slink">SLINK</a>)</li> +<li>external interrupts controller with up to 32 channels (<a href="https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq">XIRQ</a>)</li> +</ul> +<p><b>Advanced</b></p> +<ul> +<li>true-random number generator (<a href="https://stnolting.github.io/neorv32/#_true_random_number_generator_trng">TRNG</a>) based on the <a href="https://github.com/stnolting/neoTRNG">neoTRNG</a></li> +<li>execute-in-place module (<a href="https://stnolting.github.io/neorv32/#_execute_in_place_module_xip">XIP</a>) to execute code right out of a SPI flash</li> +<li>custom functions subsystem (<a href="https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs">CFS</a>) for custom tightly-coupled co-processors, accelerators or interfaces</li> +<li>direct memory access controller (<a href="https://stnolting.github.io/neorv32/#_direct_memory_access_controller_dma">DMA</a>) for CPU-independent data transfers and conversions</li> +<li>cyclic redundancy check unit (<a href="https://stnolting.github.io/neorv32/#_cyclic_redundancy_check_crc">CRC</a>) to test data integrity (CRC8/16/32)</li> +</ul> +<p><b>Debugging</b></p> +<ul> +<li>on-chip debugger (<a href="https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd">OCD</a>) accessible via standard JTAG interface</li> +<li>compatible to the "Minimal RISC-V Debug Specification Version 1.0"</li> +<li>compatible with <b>OpenOCD</b>, <b>GDB</b> and <b>Segger Embedded Studio</b></li> +<li>RISC-V <a href="https://stnolting.github.io/neorv32/#_trigger_module">trigger module</a> for hardware-assisted breakpoints</li> +</ul> +<h2><a class="anchor" id="autotoc_md5"></a> +3. FPGA Implementation Results</h2> +<p>Implementation results for <b>exemplary CPU configurations</b> generated for an Intel Cyclone IV <code>EP4CE22F17C6</code> FPGA using Intel Quartus Prime Lite 21.1 (no timing constrains, <em>balanced optimization</em>, f_max from <em>Slow 1200mV 0C Model</em>).</p> +<table class="markdownTable"> +<tr class="markdownTableHead"> +<th class="markdownTableHeadLeft">CPU Configuration (version <a href="https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md">1.7.8.5</a>) </th><th class="markdownTableHeadCenter">LEs </th><th class="markdownTableHeadCenter">FFs </th><th class="markdownTableHeadCenter">Memory bits </th><th class="markdownTableHeadCenter">DSPs </th><th class="markdownTableHeadCenter">f_max </th></tr> +<tr class="markdownTableRowOdd"> +<td class="markdownTableBodyLeft"><code>rv32i_Zicsr</code> </td><td class="markdownTableBodyCenter">1223 </td><td class="markdownTableBodyCenter">607 </td><td class="markdownTableBodyCenter">1024 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">130 MHz </td></tr> +<tr class="markdownTableRowEven"> +<td class="markdownTableBodyLeft"><code>rv32i_Zicsr_Zicntr</code> </td><td class="markdownTableBodyCenter">1578 </td><td class="markdownTableBodyCenter">773 </td><td class="markdownTableBodyCenter">1024 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">130 MHz </td></tr> +<tr class="markdownTableRowOdd"> +<td class="markdownTableBodyLeft"><code>rv32imc_Zicsr_Zicntr</code> </td><td class="markdownTableBodyCenter">2338 </td><td class="markdownTableBodyCenter">992 </td><td class="markdownTableBodyCenter">1024 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">130 MHz </td></tr> +</table> +<p>An incremental list of CPU extensions and processor modules can be found in the <a href="https://stnolting.github.io/neorv32/#_fpga_implementation_results">Data Sheet: FPGA Implementation Results</a>.</p> +<h2><a class="anchor" id="autotoc_md6"></a> +4. Performance</h2> +<p>The NEORV32 CPU is based on a two-stages pipelined/multi-cycle architecture (fetch and execute). The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing 2000 iterations of the <a href="https://github.com/stnolting/neorv32/blob/main/sw/example/coremark">CoreMark</a> CPU benchmark (using plain GCC10 rv32i built-in libraries only!).</p> +<table class="markdownTable"> +<tr class="markdownTableHead"> +<th class="markdownTableHeadLeft">CPU Configuration (version <a href="https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md">1.5.7.10</a>) </th><th class="markdownTableHeadCenter">CoreMark Score </th></tr> +<tr class="markdownTableRowOdd"> +<td class="markdownTableBodyLeft"><em>small</em> (<code>rv32i_Zicsr_Zifencei</code>) </td><td class="markdownTableBodyCenter">33.89 </td></tr> +<tr class="markdownTableRowEven"> +<td class="markdownTableBodyLeft"><em>medium</em> (<code>rv32imc_Zicsr_Zifencei</code>) </td><td class="markdownTableBodyCenter">62.50 </td></tr> +<tr class="markdownTableRowOdd"> +<td class="markdownTableBodyLeft"><em>performance</em> (<code>rv32imc_Zicsr_Zifencei</code> + perf. options) </td><td class="markdownTableBodyCenter">95.23 </td></tr> +</table> +<p>More information regarding the CPU performance can be found in the <a href="https://stnolting.github.io/neorv32/#_cpu_performance">Data Sheet: CPU Performance</a>. The CPU &amp; SoC provide further "tuning" options to optimize the design for maximum performance, maximum clock speed, minimal area or minimal power consumption: <a href="https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration">User Guide: Application-Specific Processor Configuration</a></p> +<h2><a class="anchor" id="autotoc_md7"></a> +5. Getting Started</h2> +<p>This overview provides some <em>quick links</em> to the most important sections of the <a href="https://stnolting.github.io/neorv32">online Data Sheet</a> and the <a href="https://stnolting.github.io/neorv32/ug">online User Guide</a>.</p> +<h3><a class="anchor" id="autotoc_md8"></a> +:mag: <a href="https://stnolting.github.io/neorv32/#_overview">NEORV32 Project</a> - An Introduction</h3> +<ul> +<li><a href="https://stnolting.github.io/neorv32/#_rationale">Rationale</a> - why? how come? what for?</li> +<li><a href="https://stnolting.github.io/neorv32/#_project_key_features">Key Features</a> - what makes it special</li> +<li><a href="https://stnolting.github.io/neorv32/#_project_folder_structure">Structure</a> - folders, RTL files and compile order</li> +<li><a href="https://stnolting.github.io/neorv32/#_file_list_files">File-List Files</a> - to simplify HDL setup</li> +<li><a href="https://stnolting.github.io/neorv32/#_fpga_implementation_results">Metrics</a> - FPGA implementation and performance evaluation</li> +</ul> +<h3><a class="anchor" id="autotoc_md9"></a> +:desktop_computer: <a href="https://stnolting.github.io/neorv32/#_neorv32_processor_soc">NEORV32 Processor</a> - The SoC</h3> +<ul> +<li><a href="https://stnolting.github.io/neorv32/#_processor_top_entity_signals">Top Entity - Signals</a> - how to connect to the processor</li> +<li><a href="https://stnolting.github.io/neorv32/#_processor_top_entity_generics">Top Entity - Generics</a> - processor/CPU configuration options</li> +<li><a href="https://stnolting.github.io/neorv32/#_address_space">Address Space</a> - memory layout and boot configurations</li> +<li><a href="https://stnolting.github.io/neorv32/#_processor_internal_modules">SoC Modules</a> - IO/peripheral modules and memories</li> +<li><a href="https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd">On-Chip Debugger</a> - in-system debugging of the processor via JTAG</li> +</ul> +<h3><a class="anchor" id="autotoc_md10"></a> +:abacus: <a href="https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu">NEORV32 CPU</a> - The Core</h3> +<ul> +<li><a href="https://stnolting.github.io/neorv32/#_risc_v_compatibility">RISC-V Compatibility</a> - what is compatible to the specs and what is not</li> +<li><a href="https://stnolting.github.io/neorv32/#_architecture">Architecture</a> - a look under the hood</li> +<li><a href="https://stnolting.github.io/neorv32/#_full_virtualization">Full Virtualization</a> - execution safety</li> +<li><a href="https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions">ISA and Extensions</a> - available (RISC-V) ISA extensions</li> +<li><a href="https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs">CSRs</a> - control and status registers</li> +<li><a href="https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts">Traps</a> - interrupts and exceptions</li> +</ul> +<h3><a class="anchor" id="autotoc_md11"></a> +:floppy_disk: <a href="https://stnolting.github.io/neorv32/#_software_framework">Software Framework</a> - The Software Ecosystem</h3> +<ul> +<li><a href="https://github.com/stnolting/neorv32/tree/main/sw/example">Example Programs</a> - examples how to use the processor's IO/peripheral modules</li> +<li><a href="https://stnolting.github.io/neorv32/#_core_libraries">Core Libraries</a> - high-level functions for accessing the processor's peripherals</li> +<li><a href="https://stnolting.github.io/neorv32/sw/files.html">Software Framework Documentation</a> - <em>doxygen</em>-based</li> +<li><a href="https://stnolting.github.io/neorv32/#_application_makefile">Application Makefile</a> - turning <em>your</em> application into an executable</li> +<li><a href="https://stnolting.github.io/neorv32/#_bootloader">Bootloader</a> - the build-in NEORV32 bootloader</li> +<li><a href="https://stnolting.github.io/neorv32/#_executable_image_format">Image Generator</a> - create (FPGA) memory initialization files from your application</li> +</ul> +<h3><a class="anchor" id="autotoc_md12"></a> +:rocket: <a href="https://stnolting.github.io/neorv32/ug/">User Guide</a> - Let's Get It Started</h3> +<ul> +<li><a href="https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup">Toolchain Setup</a> - install and set up the RISC-V GCC toolchain</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_general_hardware_setup">General Hardware Setup</a> - set up a new NEORV32 FPGA project</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup">General Software Setup</a> - configure the software framework</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_application_program_compilation">Application Compilation</a> - compile an application using <em>make</em></li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart">Upload via Bootloader</a> - upload and execute executables</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration">Application-Specific Processor Configuration</a> - tailor the processor to your needs</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules">Adding Custom Hardware Modules</a> - add <em>your</em> custom hardware</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger">Debugging via the On-Chip Debugger</a> - step through code <em>online</em> and <em>in-system</em></li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_simulating_the_processor">Simulation</a> - simulate the whole SoC</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support">LiteX Integration</a> - build a SoC using NEORV32 + <a href="https://github.com/enjoy-digital/litex">LiteX</a></li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_neorv32_in_verilog">Convert to Verilog</a> - turn the NEORV32 into an all-Verilog design</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block">Package as Vivado IP block</a> - turn the entire processor into an interactive AMD Vivado IP block</li> +<li><a href="https://stnolting.github.io/neorv32/ug/#_eclipse_ide">Using Eclipse</a> - use the Eclipse IDE for developing and debugging</li> +</ul> +<h3><a class="anchor" id="autotoc_md13"></a> +:copyright: Legal</h3> +<p><a href="https://github.com/stnolting/neorv32/blob/main/LICENSE"><img src="https://img.shields.io/github/license/stnolting/neorv32?longCache=true&amp;style=flat" alt="license" class="inline"/></a> <a href="https://doi.org/10.5281/zenodo.5018888"><img src="https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg" alt="DOI" style="pointer-events: none;" class="inline"/></a></p> +<ul> +<li><a href="https://stnolting.github.io/neorv32/#_legal">Overview</a> - license, disclaimer, limitation of liability for external links, proprietary notice, etc.</li> +<li><a href="https://stnolting.github.io/neorv32/#_citing">Citing</a> - citing information</li> +</ul> +<p>This is an open-source project that is free of charge. Use this project in any way you like (as long as it complies to the permissive <a href="https://github.com/stnolting/neorv32/blob/main/LICENSE">license</a>). Please cite it appropriately. :+1:</p> +<hr /> +<p><b>:heart: A big shout-out to the community and all the <a href="https://github.com/stnolting/neorv32/graphs/contributors">contributors</a> - this project would not be where it is without them!</b> </p> +</div></div><!-- contents --> +</div><!-- PageDoc --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/menu.js b/sw/menu.js new file mode 100644 index 000000000..0fd1e9901 --- /dev/null +++ b/sw/menu.js @@ -0,0 +1,134 @@ +/* + @licstart The following is the entire license notice for the JavaScript code in this file. + + The MIT License (MIT) + + Copyright (C) 1997-2020 by Dimitri van Heesch + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software + and associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file + */ +function initMenu(relPath,searchEnabled,serverSide,searchPage,search,treeview) { + function makeTree(data,relPath) { + let result=''; + if ('children' in data) { + result+='<ul>'; + for (let i in data.children) { + let url; + const link = data.children[i].url; + if (link.substring(0,1)=='^') { + url = link.substring(1); + } else { + url = relPath+link; + } + result+='<li><a href="'+url+'">'+ + data.children[i].text+'</a>'+ + makeTree(data.children[i],relPath)+'</li>'; + } + result+='</ul>'; + } + return result; + } + let searchBoxHtml; + if (searchEnabled) { + if (serverSide) { + searchBoxHtml='<div id="MSearchBox" class="MSearchBoxInactive">'+ + '<div class="left">'+ + '<form id="FSearchBox" action="'+relPath+searchPage+ + '" method="get"><span id="MSearchSelectExt">&#160;</span>'+ + '<input type="text" id="MSearchField" name="query" value="" placeholder="'+search+ + '" size="20" accesskey="S" onfocus="searchBox.OnSearchFieldFocus(true)"'+ + ' onblur="searchBox.OnSearchFieldFocus(false)"/>'+ + '</form>'+ + '</div>'+ + '<div class="right"></div>'+ + '</div>'; + } else { + searchBoxHtml='<div id="MSearchBox" class="MSearchBoxInactive">'+ + '<span class="left">'+ + '<span id="MSearchSelect" onmouseover="return searchBox.OnSearchSelectShow()"'+ + ' onmouseout="return searchBox.OnSearchSelectHide()">&#160;</span>'+ + '<input type="text" id="MSearchField" value="" placeholder="'+search+ + '" accesskey="S" onfocus="searchBox.OnSearchFieldFocus(true)" '+ + 'onblur="searchBox.OnSearchFieldFocus(false)" '+ + 'onkeyup="searchBox.OnSearchFieldChange(event)"/>'+ + '</span>'+ + '<span class="right"><a id="MSearchClose" '+ + 'href="javascript:searchBox.CloseResultsWindow()">'+ + '<img id="MSearchCloseImg" border="0" src="'+relPath+ + 'search/close.svg" alt=""/></a>'+ + '</span>'+ + '</div>'; + } + } + + $('#main-nav').before('<div class="sm sm-dox"><input id="main-menu-state" type="checkbox"/>'+ + '<label class="main-menu-btn" for="main-menu-state">'+ + '<span class="main-menu-btn-icon"></span> '+ + 'Toggle main menu visibility</label>'+ + '<span id="searchBoxPos1" style="position:absolute;right:8px;top:8px;height:36px;"></span>'+ + '</div>'); + $('#main-nav').append(makeTree(menudata,relPath)); + $('#main-nav').children(':first').addClass('sm sm-dox').attr('id','main-menu'); + if (searchBoxHtml) { + $('#main-menu').append('<li id="searchBoxPos2" style="float:right"></li>'); + } + const $mainMenuState = $('#main-menu-state'); + let prevWidth = 0; + if ($mainMenuState.length) { + const initResizableIfExists = function() { + if (typeof initResizable==='function') initResizable(treeview); + } + // animate mobile menu + $mainMenuState.change(function() { + const $menu = $('#main-menu'); + let options = { duration: 250, step: initResizableIfExists }; + if (this.checked) { + options['complete'] = () => $menu.css('display', 'block'); + $menu.hide().slideDown(options); + } else { + options['complete'] = () => $menu.css('display', 'none'); + $menu.show().slideUp(options); + } + }); + // set default menu visibility + const resetState = function() { + const $menu = $('#main-menu'); + const newWidth = $(window).outerWidth(); + if (newWidth!=prevWidth) { + if ($(window).outerWidth()<768) { + $mainMenuState.prop('checked',false); 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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file +*/ +var menudata={children:[ +{text:"Main Page",url:"index.html"}, +{text:"Related Pages",url:"pages.html"}, +{text:"Data Structures",url:"annotated.html",children:[ +{text:"Data Structures",url:"annotated.html"}, +{text:"Data Structure Index",url:"classes.html"}, +{text:"Data Fields",url:"functions.html",children:[ +{text:"All",url:"functions.html",children:[ +{text:"b",url:"functions.html#index_b"}, +{text:"c",url:"functions.html#index_c"}, +{text:"d",url:"functions.html#index_d"}, +{text:"e",url:"functions.html#index_e"}, +{text:"f",url:"functions.html#index_f"}, +{text:"h",url:"functions.html#index_h"}, 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+</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#nested-classes">Data Structures</a> </div> + <div class="headertitle"><div class="title">neorv32.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Main NEORV32 core library / driver / HAL include file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +<code>#include &lt;inttypes.h&gt;</code><br /> +<code>#include &lt;unistd.h&gt;</code><br /> +<code>#include &lt;stdlib.h&gt;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__intrinsics_8h_source.html">neorv32_intrinsics.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__aux_8h_source.html">neorv32_aux.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__legacy_8h_source.html">neorv32_legacy.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__cpu_8h_source.html">neorv32_cpu.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__cpu__amo_8h_source.html">neorv32_cpu_amo.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__cpu__csr_8h_source.html">neorv32_cpu_csr.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__cpu__cfu_8h_source.html">neorv32_cpu_cfu.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__rte_8h_source.html">neorv32_rte.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__cfs_8h_source.html">neorv32_cfs.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__crc_8h_source.html">neorv32_crc.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__dma_8h_source.html">neorv32_dma.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__gpio_8h_source.html">neorv32_gpio.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__gptmr_8h_source.html">neorv32_gptmr.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__mtime_8h_source.html">neorv32_mtime.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__neoled_8h_source.html">neorv32_neoled.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__onewire_8h_source.html">neorv32_onewire.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__pwm_8h_source.html">neorv32_pwm.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__sdi_8h_source.html">neorv32_sdi.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__slink_8h_source.html">neorv32_slink.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__spi_8h_source.html">neorv32_spi.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__sysinfo_8h_source.html">neorv32_sysinfo.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__trng_8h_source.html">neorv32_trng.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__twi_8h_source.html">neorv32_twi.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__uart_8h_source.html">neorv32_uart.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__wdt_8h_source.html">neorv32_wdt.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__xip_8h_source.html">neorv32_xip.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__xirq_8h_source.html">neorv32_xirq.h</a>&quot;</code><br /> +</div> +<p><a href="neorv32_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionsubwords64__t.html">subwords64_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionsubwords32__t.html">subwords32_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionsubwords16__t.html">subwords16_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Main Address Space 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id="r_a1eb0cb7fed7e154e15cb4009880a879c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1eb0cb7fed7e154e15cb4009880a879c">IO_BASE_ADDRESS</a>&#160;&#160;&#160;(0xFFFFE000U)</td></tr> +<tr class="separator:a1eb0cb7fed7e154e15cb4009880a879c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">IO Address Space Map - Peripheral/IO Devices</div></td></tr> +<tr class="memitem:a41d6f97daef61641da96b9f72f6b272f" id="r_a41d6f97daef61641da96b9f72f6b272f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a41d6f97daef61641da96b9f72f6b272f">NEORV32_CFS_BASE</a>&#160;&#160;&#160;(0xFFFFEB00U)</td></tr> +<tr class="separator:a41d6f97daef61641da96b9f72f6b272f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ab5e6dc57886cd5ed98b86f22fc37d7cc" id="r_ab5e6dc57886cd5ed98b86f22fc37d7cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab5e6dc57886cd5ed98b86f22fc37d7cc">NEORV32_SLINK_BASE</a>&#160;&#160;&#160;(0xFFFFEC00U)</td></tr> +<tr class="separator:ab5e6dc57886cd5ed98b86f22fc37d7cc"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa8d3a83ffad1e71f0832a5da78d62008" id="r_aa8d3a83ffad1e71f0832a5da78d62008"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa8d3a83ffad1e71f0832a5da78d62008">NEORV32_DMA_BASE</a>&#160;&#160;&#160;(0xFFFFED00U)</td></tr> +<tr class="separator:aa8d3a83ffad1e71f0832a5da78d62008"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0e2377055bdc0f416b5ae4385610600d" id="r_a0e2377055bdc0f416b5ae4385610600d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0e2377055bdc0f416b5ae4385610600d">NEORV32_CRC_BASE</a>&#160;&#160;&#160;(0xFFFFEE00U)</td></tr> +<tr class="separator:a0e2377055bdc0f416b5ae4385610600d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae0978315beac8399f96f520bda81c7fe" id="r_ae0978315beac8399f96f520bda81c7fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae0978315beac8399f96f520bda81c7fe">NEORV32_XIP_BASE</a>&#160;&#160;&#160;(0xFFFFEF00U)</td></tr> +<tr class="separator:ae0978315beac8399f96f520bda81c7fe"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afef7a6b121a788560b29e2ee2a58c725" id="r_afef7a6b121a788560b29e2ee2a58c725"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afef7a6b121a788560b29e2ee2a58c725">NEORV32_PWM_BASE</a>&#160;&#160;&#160;(0xFFFFF000U)</td></tr> +<tr class="separator:afef7a6b121a788560b29e2ee2a58c725"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0991b1a5ba1e8c3550eb9770d43589d0" id="r_a0991b1a5ba1e8c3550eb9770d43589d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0991b1a5ba1e8c3550eb9770d43589d0">NEORV32_GPTMR_BASE</a>&#160;&#160;&#160;(0xFFFFF100U)</td></tr> +<tr class="separator:a0991b1a5ba1e8c3550eb9770d43589d0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8d0b612e52b77395a05d4f18af6fcf00" id="r_a8d0b612e52b77395a05d4f18af6fcf00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8d0b612e52b77395a05d4f18af6fcf00">NEORV32_ONEWIRE_BASE</a>&#160;&#160;&#160;(0xFFFFF200U)</td></tr> +<tr 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align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9b316ec038bd94ada42c9dab57a0a3cb">NEORV32_SDI_BASE</a>&#160;&#160;&#160;(0xFFFFF700U)</td></tr> +<tr class="separator:a9b316ec038bd94ada42c9dab57a0a3cb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa466dc5eace7351bd438606f0f7475a7" id="r_aa466dc5eace7351bd438606f0f7475a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa466dc5eace7351bd438606f0f7475a7">NEORV32_SPI_BASE</a>&#160;&#160;&#160;(0xFFFFF800U)</td></tr> +<tr class="separator:aa466dc5eace7351bd438606f0f7475a7"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4a741408a4bb0938e03b99555306db9c" id="r_a4a741408a4bb0938e03b99555306db9c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="ace46f95dec73b33bf2535eb653bf8f65" name="ace46f95dec73b33bf2535eb653bf8f65"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ace46f95dec73b33bf2535eb653bf8f65">&#9670;&#160;</a></span>DMA_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33affcb52dc57bb8c0cb1e7d3c1392d544a">CSR_MIE_FIRQ10E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a1fa2b25383e6d05cf26f3517091ddbbf" name="a1fa2b25383e6d05cf26f3517091ddbbf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1fa2b25383e6d05cf26f3517091ddbbf">&#9670;&#160;</a></span>DMA_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba2b50cfa8be461b088ea8506ce4c741ba">CSR_MIP_FIRQ10P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a568b54ba7dfdae736d8d685dc4d32113" name="a568b54ba7dfdae736d8d685dc4d32113"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a568b54ba7dfdae736d8d685dc4d32113">&#9670;&#160;</a></span>DMA_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aadebcc4d91aea1364b1481111f1060c52">RTE_TRAP_FIRQ_10</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="ad2e81443af8a4ce2db3a4e3c1a8fb784" name="ad2e81443af8a4ce2db3a4e3c1a8fb784"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad2e81443af8a4ce2db3a4e3c1a8fb784">&#9670;&#160;</a></span>DMA_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a4f6b9c6bba91fe04becb776ad22dcf42">TRAP_CODE_FIRQ_10</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a0a59186908b498cb92273b7767966e26" name="a0a59186908b498cb92273b7767966e26"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0a59186908b498cb92273b7767966e26">&#9670;&#160;</a></span>GPTMR_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define GPTMR_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a41f91a37f7e0c75c783312af6a72e943">CSR_MIE_FIRQ12E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a4a3164d123ddddd07750f868e67d82d8" name="a4a3164d123ddddd07750f868e67d82d8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4a3164d123ddddd07750f868e67d82d8">&#9670;&#160;</a></span>GPTMR_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define GPTMR_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba03edd398920b817150d29107c0b40792">CSR_MIP_FIRQ12P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="aac38deeef36de0a474ab238a3054f860" name="aac38deeef36de0a474ab238a3054f860"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aac38deeef36de0a474ab238a3054f860">&#9670;&#160;</a></span>GPTMR_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define GPTMR_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaecea4f1d524a33d02324382357b2bcb9">RTE_TRAP_FIRQ_12</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a445543c36d1f78477aa8ea4841c720a1" name="a445543c36d1f78477aa8ea4841c720a1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a445543c36d1f78477aa8ea4841c720a1">&#9670;&#160;</a></span>GPTMR_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define GPTMR_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a151f01e5f284f876cafafc7427720e4c">TRAP_CODE_FIRQ_12</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a1eb0cb7fed7e154e15cb4009880a879c" name="a1eb0cb7fed7e154e15cb4009880a879c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1eb0cb7fed7e154e15cb4009880a879c">&#9670;&#160;</a></span>IO_BASE_ADDRESS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IO_BASE_ADDRESS&#160;&#160;&#160;(0xFFFFE000U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>peripheral/IO devices memory base address </p> + +</div> +</div> +<a id="a8d0409818600c0b2acfe8253e8f027b8" name="a8d0409818600c0b2acfe8253e8f027b8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8d0409818600c0b2acfe8253e8f027b8">&#9670;&#160;</a></span>NEOLED_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEOLED_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a06fdb61dab31c3490da6c37d47914f19">CSR_MIE_FIRQ9E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="aded7d7f5f4ba3a6d90f9a29e62a8cfab" name="aded7d7f5f4ba3a6d90f9a29e62a8cfab"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aded7d7f5f4ba3a6d90f9a29e62a8cfab">&#9670;&#160;</a></span>NEOLED_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEOLED_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21bad94c9691ce59b97fcfec14d345046c3e">CSR_MIP_FIRQ9P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="aca6cfc3f580c4dfe1e213009ee450c58" name="aca6cfc3f580c4dfe1e213009ee450c58"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aca6cfc3f580c4dfe1e213009ee450c58">&#9670;&#160;</a></span>NEOLED_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEOLED_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa2cd04189d91465dad2bc2a8852406b76">RTE_TRAP_FIRQ_9</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="ab4a2ac455d7426992de6877ea7325f21" name="ab4a2ac455d7426992de6877ea7325f21"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab4a2ac455d7426992de6877ea7325f21">&#9670;&#160;</a></span>NEOLED_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEOLED_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a350e762a599479fb2c6d23ccc5ee22b4">TRAP_CODE_FIRQ_9</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a41d6f97daef61641da96b9f72f6b272f" name="a41d6f97daef61641da96b9f72f6b272f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a41d6f97daef61641da96b9f72f6b272f">&#9670;&#160;</a></span>NEORV32_CFS_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_CFS_BASE&#160;&#160;&#160;(0xFFFFEB00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Custom Functions Subsystem (CFS) </p> + +</div> +</div> +<a id="a0e2377055bdc0f416b5ae4385610600d" name="a0e2377055bdc0f416b5ae4385610600d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0e2377055bdc0f416b5ae4385610600d">&#9670;&#160;</a></span>NEORV32_CRC_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_CRC_BASE&#160;&#160;&#160;(0xFFFFEE00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Cyclic Redundancy Check Unit (DMA) </p> + +</div> +</div> +<a id="a9bf0149681677f7d87abf8f62e2d9a3d" name="a9bf0149681677f7d87abf8f62e2d9a3d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9bf0149681677f7d87abf8f62e2d9a3d">&#9670;&#160;</a></span>NEORV32_DM_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_DM_BASE&#160;&#160;&#160;(0xFFFFFF00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>On-Chip Debugger - Debug Module (OCD) </p> + +</div> +</div> +<a id="aa8d3a83ffad1e71f0832a5da78d62008" name="aa8d3a83ffad1e71f0832a5da78d62008"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa8d3a83ffad1e71f0832a5da78d62008">&#9670;&#160;</a></span>NEORV32_DMA_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_DMA_BASE&#160;&#160;&#160;(0xFFFFED00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Direct Memory Access Controller (DMA) </p> + +</div> +</div> +<a id="a7fd1e24d4de2eed7bf9cd5391562c7f4" name="a7fd1e24d4de2eed7bf9cd5391562c7f4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7fd1e24d4de2eed7bf9cd5391562c7f4">&#9670;&#160;</a></span>NEORV32_GPIO_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_GPIO_BASE&#160;&#160;&#160;(0xFFFFFC00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>General Purpose Input/Output Port Controller (GPIO) </p> + +</div> +</div> +<a id="a0991b1a5ba1e8c3550eb9770d43589d0" name="a0991b1a5ba1e8c3550eb9770d43589d0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0991b1a5ba1e8c3550eb9770d43589d0">&#9670;&#160;</a></span>NEORV32_GPTMR_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_GPTMR_BASE&#160;&#160;&#160;(0xFFFFF100U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>General Purpose Timer (GPTMR) </p> + +</div> +</div> +<a id="aca22a64c8c580dfde1676732d97ead7c" name="aca22a64c8c580dfde1676732d97ead7c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aca22a64c8c580dfde1676732d97ead7c">&#9670;&#160;</a></span>neorv32_heap_begin_c</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_heap_begin_c&#160;&#160;&#160;((uint32_t)&amp;<a class="el" href="#a0eaa3dcfb1db0c72534046feb9fa9b60">__heap_start</a>[0])</td> + </tr> + </table> +</div><div class="memdoc"> +<p>heap start address </p> + +</div> +</div> +<a id="ac8b656bd05c05176638ea3f922228ca5" name="ac8b656bd05c05176638ea3f922228ca5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac8b656bd05c05176638ea3f922228ca5">&#9670;&#160;</a></span>neorv32_heap_end_c</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_heap_end_c&#160;&#160;&#160;((uint32_t)&amp;<a class="el" href="#ae6ef7c715931df8bdc331577da14119b">__heap_end</a>[0])</td> + </tr> + </table> +</div><div class="memdoc"> +<p>heap start address </p> + +</div> +</div> +<a id="a32904e45632a47e21f7c9d873720cdc5" name="a32904e45632a47e21f7c9d873720cdc5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a32904e45632a47e21f7c9d873720cdc5">&#9670;&#160;</a></span>neorv32_heap_size_c</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_heap_size_c&#160;&#160;&#160;((uint32_t)&amp;<a class="el" href="#aaa2cb9e7075a852870fd67eff2861b18">__crt0_max_heap</a>[0])</td> + </tr> + </table> +</div><div class="memdoc"> +<p>heap start address </p> + +</div> +</div> +<a id="ab98f762df259a2bbc28d19d2acfe9e23" name="ab98f762df259a2bbc28d19d2acfe9e23"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab98f762df259a2bbc28d19d2acfe9e23">&#9670;&#160;</a></span>NEORV32_MTIME_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_MTIME_BASE&#160;&#160;&#160;(0xFFFFF400U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Machine System Timer (MTIME) </p> + +</div> +</div> +<a id="a559fdce92e8af5efc426c8fc48d14f99" name="a559fdce92e8af5efc426c8fc48d14f99"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a559fdce92e8af5efc426c8fc48d14f99">&#9670;&#160;</a></span>NEORV32_NEOLED_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_NEOLED_BASE&#160;&#160;&#160;(0xFFFFFD00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Smart LED Hardware Interface (NEOLED) </p> + +</div> +</div> +<a id="a8d0b612e52b77395a05d4f18af6fcf00" name="a8d0b612e52b77395a05d4f18af6fcf00"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8d0b612e52b77395a05d4f18af6fcf00">&#9670;&#160;</a></span>NEORV32_ONEWIRE_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_ONEWIRE_BASE&#160;&#160;&#160;(0xFFFFF200U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>1-Wire Interface Controller (ONEWIRE) </p> + +</div> +</div> +<a id="afef7a6b121a788560b29e2ee2a58c725" name="afef7a6b121a788560b29e2ee2a58c725"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afef7a6b121a788560b29e2ee2a58c725">&#9670;&#160;</a></span>NEORV32_PWM_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_PWM_BASE&#160;&#160;&#160;(0xFFFFF000U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Pulse Width Modulation Controller (PWM) </p> + +</div> +</div> +<a id="a9b316ec038bd94ada42c9dab57a0a3cb" name="a9b316ec038bd94ada42c9dab57a0a3cb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9b316ec038bd94ada42c9dab57a0a3cb">&#9670;&#160;</a></span>NEORV32_SDI_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_SDI_BASE&#160;&#160;&#160;(0xFFFFF700U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Serial Data Interface (SDI) </p> + +</div> +</div> +<a id="ab5e6dc57886cd5ed98b86f22fc37d7cc" name="ab5e6dc57886cd5ed98b86f22fc37d7cc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab5e6dc57886cd5ed98b86f22fc37d7cc">&#9670;&#160;</a></span>NEORV32_SLINK_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_SLINK_BASE&#160;&#160;&#160;(0xFFFFEC00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Stream Link Interface (SLINK) </p> + +</div> +</div> +<a id="aa466dc5eace7351bd438606f0f7475a7" name="aa466dc5eace7351bd438606f0f7475a7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa466dc5eace7351bd438606f0f7475a7">&#9670;&#160;</a></span>NEORV32_SPI_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_SPI_BASE&#160;&#160;&#160;(0xFFFFF800U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Serial Peripheral Interface Controller (SPI) </p> + +</div> +</div> +<a id="a5aa936f38782232c7ed3eab1283ee536" name="a5aa936f38782232c7ed3eab1283ee536"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5aa936f38782232c7ed3eab1283ee536">&#9670;&#160;</a></span>NEORV32_SYSINFO_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_SYSINFO_BASE&#160;&#160;&#160;(0xFFFFFE00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>System Information Memory (SYSINFO) </p> + +</div> +</div> +<a id="ab4846cd153e8a23deec45d81cc8372a2" name="ab4846cd153e8a23deec45d81cc8372a2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab4846cd153e8a23deec45d81cc8372a2">&#9670;&#160;</a></span>NEORV32_TRNG_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_TRNG_BASE&#160;&#160;&#160;(0xFFFFFA00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>True Random Number Generator (TRNG) </p> + +</div> +</div> +<a id="a4a741408a4bb0938e03b99555306db9c" name="a4a741408a4bb0938e03b99555306db9c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4a741408a4bb0938e03b99555306db9c">&#9670;&#160;</a></span>NEORV32_TWI_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_TWI_BASE&#160;&#160;&#160;(0xFFFFF900U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Two-Wire Interface Controller (TWI) </p> + +</div> +</div> +<a id="a000b37f710043fe21e49b2fdbc039d94" name="a000b37f710043fe21e49b2fdbc039d94"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a000b37f710043fe21e49b2fdbc039d94">&#9670;&#160;</a></span>NEORV32_UART0_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_UART0_BASE&#160;&#160;&#160;(0xFFFFF500U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Primary Universal Asynchronous Receiver and Transmitter (UART0) </p> + +</div> +</div> +<a id="a26a1defe18ce222b8b4ed1c760344700" name="a26a1defe18ce222b8b4ed1c760344700"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a26a1defe18ce222b8b4ed1c760344700">&#9670;&#160;</a></span>NEORV32_UART1_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_UART1_BASE&#160;&#160;&#160;(0xFFFFF600U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Secondary Universal Asynchronous Receiver and Transmitter (UART1) </p> + +</div> +</div> +<a id="a3012986cdd5748ee96bcc74cd7108dea" name="a3012986cdd5748ee96bcc74cd7108dea"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3012986cdd5748ee96bcc74cd7108dea">&#9670;&#160;</a></span>NEORV32_WDT_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_WDT_BASE&#160;&#160;&#160;(0xFFFFFB00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Watchdog Timer (WDT) </p> + +</div> +</div> +<a id="ae0978315beac8399f96f520bda81c7fe" name="ae0978315beac8399f96f520bda81c7fe"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae0978315beac8399f96f520bda81c7fe">&#9670;&#160;</a></span>NEORV32_XIP_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_XIP_BASE&#160;&#160;&#160;(0xFFFFEF00U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Execute In Place Module (XIP) </p> + +</div> +</div> +<a id="a942a897be2d4ae6820bee0f7bb3a0ff1" name="a942a897be2d4ae6820bee0f7bb3a0ff1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a942a897be2d4ae6820bee0f7bb3a0ff1">&#9670;&#160;</a></span>NEORV32_XIRQ_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_XIRQ_BASE&#160;&#160;&#160;(0xFFFFF300U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>External Interrupt Controller (XIRQ) </p> + +</div> +</div> +<a id="a8bb1918679e32e898af2d485cfa44afb" name="a8bb1918679e32e898af2d485cfa44afb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8bb1918679e32e898af2d485cfa44afb">&#9670;&#160;</a></span>ONEWIRE_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ONEWIRE_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a134ed02c7293008b21b1df472be8f11f">CSR_MIE_FIRQ13E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a3853ef999f99ca062e6025038811d0f0" name="a3853ef999f99ca062e6025038811d0f0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3853ef999f99ca062e6025038811d0f0">&#9670;&#160;</a></span>ONEWIRE_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ONEWIRE_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba14da6a2a962bf82970638a948ffbc570">CSR_MIP_FIRQ13P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a142f4a1c754edfab292706618d427b94" name="a142f4a1c754edfab292706618d427b94"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a142f4a1c754edfab292706618d427b94">&#9670;&#160;</a></span>ONEWIRE_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ONEWIRE_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa609613cf25bb8f2d0e323089d6798220">RTE_TRAP_FIRQ_13</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a3e7aaa405a7d1fcd71a36c4b6b5a4081" name="a3e7aaa405a7d1fcd71a36c4b6b5a4081"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3e7aaa405a7d1fcd71a36c4b6b5a4081">&#9670;&#160;</a></span>ONEWIRE_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ONEWIRE_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a7c8e97297cc4dcd6d5a1de65a124f3e9">TRAP_CODE_FIRQ_13</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a30cf20b6d704c50cc5c46238bb43646f" name="a30cf20b6d704c50cc5c46238bb43646f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a30cf20b6d704c50cc5c46238bb43646f">&#9670;&#160;</a></span>SDI_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SDI_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33af058342854a0becd3bcc33877d9244cd">CSR_MIE_FIRQ11E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a68611c0dfbe331739eff10230ac3fede" name="a68611c0dfbe331739eff10230ac3fede"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a68611c0dfbe331739eff10230ac3fede">&#9670;&#160;</a></span>SDI_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SDI_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba69ea0d3d76d4cec398f3b96959cc3544">CSR_MIP_FIRQ11P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="aa0ff72ea560d7e1462787dc31bd467cf" name="aa0ff72ea560d7e1462787dc31bd467cf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa0ff72ea560d7e1462787dc31bd467cf">&#9670;&#160;</a></span>SDI_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SDI_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab49ff0110481f22da22a085d2633a0e0">RTE_TRAP_FIRQ_11</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a68925ca3f482f148caedd36118fd8d79" name="a68925ca3f482f148caedd36118fd8d79"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a68925ca3f482f148caedd36118fd8d79">&#9670;&#160;</a></span>SDI_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SDI_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a874dcc43cf8fbbf2e0614e7db9e38334">TRAP_CODE_FIRQ_11</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a8680ab1f14e512f21913572b35cbbf77" name="a8680ab1f14e512f21913572b35cbbf77"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8680ab1f14e512f21913572b35cbbf77">&#9670;&#160;</a></span>SLINK_RX_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SLINK_RX_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a864d135708530016cfc52a65a1e4d79b">CSR_MIE_FIRQ14E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a5c48d5c4effb47cdb019aa2da7c84526" name="a5c48d5c4effb47cdb019aa2da7c84526"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5c48d5c4effb47cdb019aa2da7c84526">&#9670;&#160;</a></span>SLINK_RX_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SLINK_RX_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baad1e5e452a9c37561308765431f0260d">CSR_MIP_FIRQ14P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a4fff18e72d10377cdcb8d2ac0a617a5d" name="a4fff18e72d10377cdcb8d2ac0a617a5d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4fff18e72d10377cdcb8d2ac0a617a5d">&#9670;&#160;</a></span>SLINK_RX_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SLINK_RX_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaadd66d9b9c33a6869fa3c30e1e434313">RTE_TRAP_FIRQ_14</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="ab1fdaedb2c4c8753ef3be87c82568dda" name="ab1fdaedb2c4c8753ef3be87c82568dda"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab1fdaedb2c4c8753ef3be87c82568dda">&#9670;&#160;</a></span>SLINK_RX_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SLINK_RX_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a821f813de47eb781ab7715f780da3b1e">TRAP_CODE_FIRQ_14</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a232fe0eb5665373b6e2b464bdc228df2" name="a232fe0eb5665373b6e2b464bdc228df2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a232fe0eb5665373b6e2b464bdc228df2">&#9670;&#160;</a></span>SLINK_TX_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SLINK_TX_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33aa2dfa1183af312de2959dadd217fddc1">CSR_MIE_FIRQ15E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="ac8e98b2af75c8e31f9815dee3dcbaf8e" name="ac8e98b2af75c8e31f9815dee3dcbaf8e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac8e98b2af75c8e31f9815dee3dcbaf8e">&#9670;&#160;</a></span>SLINK_TX_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SLINK_TX_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba12da8c32d38d5a3539a0b766718bfd2d">CSR_MIP_FIRQ15P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a4e039d13b8d3f20453e1bb6b40512e43" name="a4e039d13b8d3f20453e1bb6b40512e43"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4e039d13b8d3f20453e1bb6b40512e43">&#9670;&#160;</a></span>SLINK_TX_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SLINK_TX_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa1d18312227bfd5332ebcc1f74c979dbe">RTE_TRAP_FIRQ_15</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a7fbe28901775e284d5700086f0b0bfcd" name="a7fbe28901775e284d5700086f0b0bfcd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7fbe28901775e284d5700086f0b0bfcd">&#9670;&#160;</a></span>SLINK_TX_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SLINK_TX_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aa4eeafe2f6f59aff01e29461c664a110">TRAP_CODE_FIRQ_15</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="ab8fcd3f80c373eb0f9d0fc6bf64ca626" name="ab8fcd3f80c373eb0f9d0fc6bf64ca626"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab8fcd3f80c373eb0f9d0fc6bf64ca626">&#9670;&#160;</a></span>SPI_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SPI_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a96315d6b5b9531bcbc1e78a3c9ab166a">CSR_MIE_FIRQ6E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="ab2f58f746febb29a9828447c733f8043" name="ab2f58f746febb29a9828447c733f8043"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab2f58f746febb29a9828447c733f8043">&#9670;&#160;</a></span>SPI_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SPI_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baffa7342631aa0526aaa44c0c549b1f3e">CSR_MIP_FIRQ6P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a4c1cd9ec9f80da2080e5d0d35cc524dd" name="a4c1cd9ec9f80da2080e5d0d35cc524dd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4c1cd9ec9f80da2080e5d0d35cc524dd">&#9670;&#160;</a></span>SPI_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SPI_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aac9fb28ea8bafff182f12c29d2fad6998">RTE_TRAP_FIRQ_6</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a83c212f1f5d8ee2a5921b3b2b19e9cc4" name="a83c212f1f5d8ee2a5921b3b2b19e9cc4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a83c212f1f5d8ee2a5921b3b2b19e9cc4">&#9670;&#160;</a></span>SPI_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define SPI_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a809e997f55e83c6812c965655511d473">TRAP_CODE_FIRQ_6</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a2896d832852c016eb85210b523642f11" name="a2896d832852c016eb85210b523642f11"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2896d832852c016eb85210b523642f11">&#9670;&#160;</a></span>TRNG_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TRNG_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a99f43f8bbfb29fba6224f081c363ac7d">CSR_MIE_FIRQ0E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a9c387ca4e2736a27056c11819947c84a" name="a9c387ca4e2736a27056c11819947c84a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9c387ca4e2736a27056c11819947c84a">&#9670;&#160;</a></span>TRNG_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TRNG_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba28a85ad8bd4c30fd3a91298dfa4fdb00">CSR_MIP_FIRQ0P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="afaa705a674acf3fd6c8cb294eaf11c5e" name="afaa705a674acf3fd6c8cb294eaf11c5e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afaa705a674acf3fd6c8cb294eaf11c5e">&#9670;&#160;</a></span>TRNG_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TRNG_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab36a403cd7b833439ce7f9a708c33922">RTE_TRAP_FIRQ_0</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a11e34802c61a01fd6cba46e3f92d5ac1" name="a11e34802c61a01fd6cba46e3f92d5ac1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a11e34802c61a01fd6cba46e3f92d5ac1">&#9670;&#160;</a></span>TRNG_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TRNG_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a0cef77904935798d247d8396838297c1">TRAP_CODE_FIRQ_0</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a0913144fce247e24ccd0f178b9ac32b7" name="a0913144fce247e24ccd0f178b9ac32b7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0913144fce247e24ccd0f178b9ac32b7">&#9670;&#160;</a></span>TWI_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TWI_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3d9d729940170609affbc6813054ebe8">CSR_MIE_FIRQ7E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a48b80113ca718fbdc50d75e1ec96a1ff" name="a48b80113ca718fbdc50d75e1ec96a1ff"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a48b80113ca718fbdc50d75e1ec96a1ff">&#9670;&#160;</a></span>TWI_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TWI_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baad691486001a68f2375dcf5793ee795a">CSR_MIP_FIRQ7P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a1ac29f2f7bace5ba92b2b68a4541a60c" name="a1ac29f2f7bace5ba92b2b68a4541a60c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1ac29f2f7bace5ba92b2b68a4541a60c">&#9670;&#160;</a></span>TWI_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TWI_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa73bb84f7b6c7528bec552ac1d3e9ccdb">RTE_TRAP_FIRQ_7</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a0afc1a759116d4d73a199ef769bced47" name="a0afc1a759116d4d73a199ef769bced47"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0afc1a759116d4d73a199ef769bced47">&#9670;&#160;</a></span>TWI_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define TWI_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aeab719bcce9e9551bd6da65a7ae08a26">TRAP_CODE_FIRQ_7</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a6b55ce6abe6b141000a6bb00949169e9" name="a6b55ce6abe6b141000a6bb00949169e9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6b55ce6abe6b141000a6bb00949169e9">&#9670;&#160;</a></span>UART0_RX_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART0_RX_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33afc805280e20ffface116ca61e11645f7">CSR_MIE_FIRQ2E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a0b738b26abb2b951f1f5c5d9525d7701" name="a0b738b26abb2b951f1f5c5d9525d7701"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0b738b26abb2b951f1f5c5d9525d7701">&#9670;&#160;</a></span>UART0_RX_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART0_RX_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21badf45c5a135431f958fa63574c1dfac6e">CSR_MIP_FIRQ2P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="ae8588cca20d5e36f74c5207c376389a1" name="ae8588cca20d5e36f74c5207c376389a1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae8588cca20d5e36f74c5207c376389a1">&#9670;&#160;</a></span>UART0_RX_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART0_RX_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa29ffa3108fadc78bf375773c3232c489">RTE_TRAP_FIRQ_2</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a7a849638eff31f2e1955bdc53d4fc84d" name="a7a849638eff31f2e1955bdc53d4fc84d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7a849638eff31f2e1955bdc53d4fc84d">&#9670;&#160;</a></span>UART0_RX_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART0_RX_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ad753d3e2563b4fd663430af9f3888dc7">TRAP_CODE_FIRQ_2</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="aff756a395771f22c5f412f23f177ea7d" name="aff756a395771f22c5f412f23f177ea7d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aff756a395771f22c5f412f23f177ea7d">&#9670;&#160;</a></span>UART0_TX_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART0_TX_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a666066099d6cebadbef21d81c179e8db">CSR_MIE_FIRQ3E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="addbe29166bb77bc045ad0e3db68e57e9" name="addbe29166bb77bc045ad0e3db68e57e9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#addbe29166bb77bc045ad0e3db68e57e9">&#9670;&#160;</a></span>UART0_TX_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART0_TX_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba7512bb6c4841ddd477422b49ebb2a155">CSR_MIP_FIRQ3P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a9dc37695ca169bc0eb93898e7aeeee58" name="a9dc37695ca169bc0eb93898e7aeeee58"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9dc37695ca169bc0eb93898e7aeeee58">&#9670;&#160;</a></span>UART0_TX_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART0_TX_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa4a74188fd87ea17a594ac6fe8ddf71be">RTE_TRAP_FIRQ_3</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="ab50df423fdba86bb83bc5d90a4c3bb20" name="ab50df423fdba86bb83bc5d90a4c3bb20"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab50df423fdba86bb83bc5d90a4c3bb20">&#9670;&#160;</a></span>UART0_TX_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART0_TX_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a356f8485166529503d0fb246bd0aeeb0">TRAP_CODE_FIRQ_3</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a6c118c1784d8446360b00cde97437ca7" name="a6c118c1784d8446360b00cde97437ca7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6c118c1784d8446360b00cde97437ca7">&#9670;&#160;</a></span>UART1_RX_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART1_RX_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a592939f1b7d79097f7f13d6ab0c268dc">CSR_MIE_FIRQ4E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a2e70d3a4e2973d224643813fcf315a20" name="a2e70d3a4e2973d224643813fcf315a20"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2e70d3a4e2973d224643813fcf315a20">&#9670;&#160;</a></span>UART1_RX_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART1_RX_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21bab6421f242bb8a487a986346e11196eb8">CSR_MIP_FIRQ4P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="ab1c351f5ea19ac9ea864155be9cc0b4b" name="ab1c351f5ea19ac9ea864155be9cc0b4b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab1c351f5ea19ac9ea864155be9cc0b4b">&#9670;&#160;</a></span>UART1_RX_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART1_RX_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa8b39868bf91da54f9ec492918e0c01ff">RTE_TRAP_FIRQ_4</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="ad0b9eb2ee1f411d7fccdf4fe263214e1" name="ad0b9eb2ee1f411d7fccdf4fe263214e1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad0b9eb2ee1f411d7fccdf4fe263214e1">&#9670;&#160;</a></span>UART1_RX_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART1_RX_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aaa8e7bb251852ef75a78be71eef0b547">TRAP_CODE_FIRQ_4</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="a0039bae3454a22e71d64e70d674f5d6a" name="a0039bae3454a22e71d64e70d674f5d6a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0039bae3454a22e71d64e70d674f5d6a">&#9670;&#160;</a></span>UART1_TX_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART1_TX_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3079a8fbf3b8e376865bff76f2173698">CSR_MIE_FIRQ5E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="ac4060532b7aa390623f54720460a2680" name="ac4060532b7aa390623f54720460a2680"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac4060532b7aa390623f54720460a2680">&#9670;&#160;</a></span>UART1_TX_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART1_TX_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baaa55d19f9a47889bc364c94bda04b677">CSR_MIP_FIRQ5P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a6af270d7ae8b1cde30e44eb9142491d3" name="a6af270d7ae8b1cde30e44eb9142491d3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6af270d7ae8b1cde30e44eb9142491d3">&#9670;&#160;</a></span>UART1_TX_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART1_TX_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa01f562418ddbbb6b84be168673deeea9">RTE_TRAP_FIRQ_5</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a4cc50287c7a53982761a8116396ff7dd" name="a4cc50287c7a53982761a8116396ff7dd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4cc50287c7a53982761a8116396ff7dd">&#9670;&#160;</a></span>UART1_TX_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define UART1_TX_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a5789dfabd8ec265fa0734ddd94e98757">TRAP_CODE_FIRQ_5</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<a id="aa01bea676e878a9e87ca10ce2d91e51f" name="aa01bea676e878a9e87ca10ce2d91e51f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa01bea676e878a9e87ca10ce2d91e51f">&#9670;&#160;</a></span>XIP_MEM_BASE_ADDRESS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIP_MEM_BASE_ADDRESS&#160;&#160;&#160;(0xE0000000U)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIP-mapped memory base address </p> + +</div> +</div> +<a id="afe0cb262d517c7da73d6b5dc78886334" name="afe0cb262d517c7da73d6b5dc78886334"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afe0cb262d517c7da73d6b5dc78886334">&#9670;&#160;</a></span>XIRQ_FIRQ_ENABLE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIRQ_FIRQ_ENABLE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a396c6c4b425b3fff598e2f846052f98e">CSR_MIE_FIRQ8E</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIE CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> + +</div> +</div> +<a id="a866768963f8648363dce40de9f34d61b" name="a866768963f8648363dce40de9f34d61b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a866768963f8648363dce40de9f34d61b">&#9670;&#160;</a></span>XIRQ_FIRQ_PENDING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIRQ_FIRQ_PENDING&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baf5bbd23d4f311f640db42e9015f87580">CSR_MIP_FIRQ8P</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MIP CSR bit (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> + +</div> +</div> +<a id="a95387d3482ec8e5c1d734805fdf64fa5" name="a95387d3482ec8e5c1d734805fdf64fa5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a95387d3482ec8e5c1d734805fdf64fa5">&#9670;&#160;</a></span>XIRQ_RTE_ID</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIRQ_RTE_ID&#160;&#160;&#160;<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa3edbf47bd9a278e100bb808c8bb68308">RTE_TRAP_FIRQ_8</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>RTE entry code (<a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>) </p> + +</div> +</div> +<a id="a16b9a7444833b5581df073661deb8f3a" name="a16b9a7444833b5581df073661deb8f3a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a16b9a7444833b5581df073661deb8f3a">&#9670;&#160;</a></span>XIRQ_TRAP_CODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIRQ_TRAP_CODE&#160;&#160;&#160;<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1abfd21d1380dcacb9282e525da104d916">TRAP_CODE_FIRQ_8</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>MCAUSE CSR trap code (<a class="el" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a10022df4c223533b04d5aebe222e8b73" name="a10022df4c223533b04d5aebe222e8b73"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a10022df4c223533b04d5aebe222e8b73">&#9670;&#160;</a></span>NEORV32_CLOCK_PRSC_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Processor clock prescaler select (relative to processor's main clock) </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a10022df4c223533b04d5aebe222e8b73ad63d40139c50d76618cf1258cbdc0d05" name="a10022df4c223533b04d5aebe222e8b73ad63d40139c50d76618cf1258cbdc0d05"></a>CLK_PRSC_2&#160;</td><td class="fielddoc"><p>CPU_CLK / 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="a10022df4c223533b04d5aebe222e8b73a648249b3ab8c2500880c1e68b98f81d1" name="a10022df4c223533b04d5aebe222e8b73a648249b3ab8c2500880c1e68b98f81d1"></a>CLK_PRSC_4&#160;</td><td class="fielddoc"><p>CPU_CLK / 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="a10022df4c223533b04d5aebe222e8b73aa4e3a6a5b3cd895f63b4544f63ce22c9" name="a10022df4c223533b04d5aebe222e8b73aa4e3a6a5b3cd895f63b4544f63ce22c9"></a>CLK_PRSC_8&#160;</td><td class="fielddoc"><p>CPU_CLK / 8 </p> +</td></tr> +<tr><td class="fieldname"><a id="a10022df4c223533b04d5aebe222e8b73a5990532893f2d9606e3c02aff60ca5da" name="a10022df4c223533b04d5aebe222e8b73a5990532893f2d9606e3c02aff60ca5da"></a>CLK_PRSC_64&#160;</td><td class="fielddoc"><p>CPU_CLK / 64 </p> +</td></tr> +<tr><td class="fieldname"><a id="a10022df4c223533b04d5aebe222e8b73a933045a5405de55781d687315f42054e" name="a10022df4c223533b04d5aebe222e8b73a933045a5405de55781d687315f42054e"></a>CLK_PRSC_128&#160;</td><td class="fielddoc"><p>CPU_CLK / 128 </p> +</td></tr> +<tr><td class="fieldname"><a id="a10022df4c223533b04d5aebe222e8b73a18aac15afd5ebd8d3a00dd6e513daf17" name="a10022df4c223533b04d5aebe222e8b73a18aac15afd5ebd8d3a00dd6e513daf17"></a>CLK_PRSC_1024&#160;</td><td class="fielddoc"><p>CPU_CLK / 1024 </p> +</td></tr> +<tr><td class="fieldname"><a id="a10022df4c223533b04d5aebe222e8b73aa138f0cad547028d5124f89d6dcc8c79" name="a10022df4c223533b04d5aebe222e8b73aa138f0cad547028d5124f89d6dcc8c79"></a>CLK_PRSC_2048&#160;</td><td class="fielddoc"><p>CPU_CLK / 2048 </p> +</td></tr> +<tr><td class="fieldname"><a id="a10022df4c223533b04d5aebe222e8b73a0f20c29722bf9afc478b1a286a6b7eee" name="a10022df4c223533b04d5aebe222e8b73a0f20c29722bf9afc478b1a286a6b7eee"></a>CLK_PRSC_4096&#160;</td><td class="fielddoc"><p>CPU_CLK / 4096 </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a id="aaa2cb9e7075a852870fd67eff2861b18" name="aaa2cb9e7075a852870fd67eff2861b18"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaa2cb9e7075a852870fd67eff2861b18">&#9670;&#160;</a></span>__crt0_max_heap</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">char __crt0_max_heap[]</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">extern</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>heap size in bytes </p> + +</div> +</div> +<a id="ae6ef7c715931df8bdc331577da14119b" name="ae6ef7c715931df8bdc331577da14119b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae6ef7c715931df8bdc331577da14119b">&#9670;&#160;</a></span>__heap_end</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">char __heap_end[]</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">extern</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>heap last address </p> + +</div> +</div> +<a id="a0eaa3dcfb1db0c72534046feb9fa9b60" name="a0eaa3dcfb1db0c72534046feb9fa9b60"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0eaa3dcfb1db0c72534046feb9fa9b60">&#9670;&#160;</a></span>__heap_start</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">char __heap_start[]</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">extern</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>heap start address </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32_8h_source.html b/sw/neorv32_8h_source.html new file mode 100644 index 000000000..9c79b507d --- /dev/null +++ b/sw/neorv32_8h_source.html @@ -0,0 +1,360 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#ifdef __cplusplus</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span><span class="comment">// Standard libraries</span></div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span><span class="preprocessor">#include &lt;inttypes.h&gt;</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span><span class="preprocessor">#include &lt;unistd.h&gt;</span></div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span><span class="preprocessor">#include &lt;stdlib.h&gt;</span></div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span> </div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span> </div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aa01bea676e878a9e87ca10ce2d91e51f"> 35</a></span><span class="preprocessor">#define XIP_MEM_BASE_ADDRESS (0xE0000000U)</span></div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32_8h.html#abd8c9b7d79f49de1722611b2835cde58"> 37</a></span><span class="preprocessor">#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U)</span></div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a1eb0cb7fed7e154e15cb4009880a879c"> 39</a></span><span class="preprocessor">#define IO_BASE_ADDRESS (0xFFFFE000U)</span></div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE000U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE100U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE200U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE300U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE400U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE500U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE600U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE700U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE800U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFE900U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="comment">//#define NEORV32_???_BASE (0xFFFFEA00U) /**&lt; reserved */</span></div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a41d6f97daef61641da96b9f72f6b272f"> 58</a></span><span class="preprocessor">#define NEORV32_CFS_BASE (0xFFFFEB00U) </span></div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab5e6dc57886cd5ed98b86f22fc37d7cc"> 59</a></span><span class="preprocessor">#define NEORV32_SLINK_BASE (0xFFFFEC00U) </span></div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aa8d3a83ffad1e71f0832a5da78d62008"> 60</a></span><span class="preprocessor">#define NEORV32_DMA_BASE (0xFFFFED00U) </span></div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a0e2377055bdc0f416b5ae4385610600d"> 61</a></span><span class="preprocessor">#define NEORV32_CRC_BASE (0xFFFFEE00U) </span></div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ae0978315beac8399f96f520bda81c7fe"> 62</a></span><span class="preprocessor">#define NEORV32_XIP_BASE (0xFFFFEF00U) </span></div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32_8h.html#afef7a6b121a788560b29e2ee2a58c725"> 63</a></span><span class="preprocessor">#define NEORV32_PWM_BASE (0xFFFFF000U) </span></div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a0991b1a5ba1e8c3550eb9770d43589d0"> 64</a></span><span class="preprocessor">#define NEORV32_GPTMR_BASE (0xFFFFF100U) </span></div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a8d0b612e52b77395a05d4f18af6fcf00"> 65</a></span><span class="preprocessor">#define NEORV32_ONEWIRE_BASE (0xFFFFF200U) </span></div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a942a897be2d4ae6820bee0f7bb3a0ff1"> 66</a></span><span class="preprocessor">#define NEORV32_XIRQ_BASE (0xFFFFF300U) </span></div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab98f762df259a2bbc28d19d2acfe9e23"> 67</a></span><span class="preprocessor">#define NEORV32_MTIME_BASE (0xFFFFF400U) </span></div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a000b37f710043fe21e49b2fdbc039d94"> 68</a></span><span class="preprocessor">#define NEORV32_UART0_BASE (0xFFFFF500U) </span></div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a26a1defe18ce222b8b4ed1c760344700"> 69</a></span><span class="preprocessor">#define NEORV32_UART1_BASE (0xFFFFF600U) </span></div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a9b316ec038bd94ada42c9dab57a0a3cb"> 70</a></span><span class="preprocessor">#define NEORV32_SDI_BASE (0xFFFFF700U) </span></div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aa466dc5eace7351bd438606f0f7475a7"> 71</a></span><span class="preprocessor">#define NEORV32_SPI_BASE (0xFFFFF800U) </span></div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a4a741408a4bb0938e03b99555306db9c"> 72</a></span><span class="preprocessor">#define NEORV32_TWI_BASE (0xFFFFF900U) </span></div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab4846cd153e8a23deec45d81cc8372a2"> 73</a></span><span class="preprocessor">#define NEORV32_TRNG_BASE (0xFFFFFA00U) </span></div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a3012986cdd5748ee96bcc74cd7108dea"> 74</a></span><span class="preprocessor">#define NEORV32_WDT_BASE (0xFFFFFB00U) </span></div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a7fd1e24d4de2eed7bf9cd5391562c7f4"> 75</a></span><span class="preprocessor">#define NEORV32_GPIO_BASE (0xFFFFFC00U) </span></div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a559fdce92e8af5efc426c8fc48d14f99"> 76</a></span><span class="preprocessor">#define NEORV32_NEOLED_BASE (0xFFFFFD00U) </span></div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a5aa936f38782232c7ed3eab1283ee536"> 77</a></span><span class="preprocessor">#define NEORV32_SYSINFO_BASE (0xFFFFFE00U) </span></div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a9bf0149681677f7d87abf8f62e2d9a3d"> 78</a></span><span class="preprocessor">#define NEORV32_DM_BASE (0xFFFFFF00U) </span></div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a2896d832852c016eb85210b523642f11"> 88</a></span><span class="preprocessor">#define TRNG_FIRQ_ENABLE CSR_MIE_FIRQ0E </span></div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a9c387ca4e2736a27056c11819947c84a"> 89</a></span><span class="preprocessor">#define TRNG_FIRQ_PENDING CSR_MIP_FIRQ0P </span></div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"><a class="line" href="neorv32_8h.html#afaa705a674acf3fd6c8cb294eaf11c5e"> 90</a></span><span class="preprocessor">#define TRNG_RTE_ID RTE_TRAP_FIRQ_0 </span></div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a11e34802c61a01fd6cba46e3f92d5ac1"> 91</a></span><span class="preprocessor">#define TRNG_TRAP_CODE TRAP_CODE_FIRQ_0 </span></div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ace79ee46daf3a1b689d9fe79dfcd6627"> 95</a></span><span class="preprocessor">#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E </span></div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aae182648a2c23d070b9db0295388e001"> 96</a></span><span class="preprocessor">#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P </span></div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a095f41fbefaa7acc1bfdd65cd3ce06ea"> 97</a></span><span class="preprocessor">#define CFS_RTE_ID RTE_TRAP_FIRQ_1 </span></div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aae6b2ae3fba20ff80bfb59735f179c26"> 98</a></span><span class="preprocessor">#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1 </span></div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a6b55ce6abe6b141000a6bb00949169e9"> 102</a></span><span class="preprocessor">#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E </span></div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a0b738b26abb2b951f1f5c5d9525d7701"> 103</a></span><span class="preprocessor">#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P </span></div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ae8588cca20d5e36f74c5207c376389a1"> 104</a></span><span class="preprocessor">#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2 </span></div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a7a849638eff31f2e1955bdc53d4fc84d"> 105</a></span><span class="preprocessor">#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2 </span></div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aff756a395771f22c5f412f23f177ea7d"> 106</a></span><span class="preprocessor">#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E </span></div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"><a class="line" href="neorv32_8h.html#addbe29166bb77bc045ad0e3db68e57e9"> 107</a></span><span class="preprocessor">#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P </span></div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a9dc37695ca169bc0eb93898e7aeeee58"> 108</a></span><span class="preprocessor">#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3 </span></div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab50df423fdba86bb83bc5d90a4c3bb20"> 109</a></span><span class="preprocessor">#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_3 </span></div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a6c118c1784d8446360b00cde97437ca7"> 113</a></span><span class="preprocessor">#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E </span></div> +<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a2e70d3a4e2973d224643813fcf315a20"> 114</a></span><span class="preprocessor">#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P </span></div> +<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab1c351f5ea19ac9ea864155be9cc0b4b"> 115</a></span><span class="preprocessor">#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4 </span></div> +<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ad0b9eb2ee1f411d7fccdf4fe263214e1"> 116</a></span><span class="preprocessor">#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4 </span></div> +<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a0039bae3454a22e71d64e70d674f5d6a"> 117</a></span><span class="preprocessor">#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E </span></div> +<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ac4060532b7aa390623f54720460a2680"> 118</a></span><span class="preprocessor">#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P </span></div> +<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a6af270d7ae8b1cde30e44eb9142491d3"> 119</a></span><span class="preprocessor">#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5 </span></div> +<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a4cc50287c7a53982761a8116396ff7dd"> 120</a></span><span class="preprocessor">#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5 </span></div> +<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab8fcd3f80c373eb0f9d0fc6bf64ca626"> 124</a></span><span class="preprocessor">#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E </span></div> +<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab2f58f746febb29a9828447c733f8043"> 125</a></span><span class="preprocessor">#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P </span></div> +<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a4c1cd9ec9f80da2080e5d0d35cc524dd"> 126</a></span><span class="preprocessor">#define SPI_RTE_ID RTE_TRAP_FIRQ_6 </span></div> +<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a83c212f1f5d8ee2a5921b3b2b19e9cc4"> 127</a></span><span class="preprocessor">#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6 </span></div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a0913144fce247e24ccd0f178b9ac32b7"> 131</a></span><span class="preprocessor">#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E </span></div> +<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a48b80113ca718fbdc50d75e1ec96a1ff"> 132</a></span><span class="preprocessor">#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P </span></div> +<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a1ac29f2f7bace5ba92b2b68a4541a60c"> 133</a></span><span class="preprocessor">#define TWI_RTE_ID RTE_TRAP_FIRQ_7 </span></div> +<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a0afc1a759116d4d73a199ef769bced47"> 134</a></span><span class="preprocessor">#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7 </span></div> +<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"><a class="line" href="neorv32_8h.html#afe0cb262d517c7da73d6b5dc78886334"> 138</a></span><span class="preprocessor">#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E </span></div> +<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a866768963f8648363dce40de9f34d61b"> 139</a></span><span class="preprocessor">#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P </span></div> +<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a95387d3482ec8e5c1d734805fdf64fa5"> 140</a></span><span class="preprocessor">#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8 </span></div> +<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a16b9a7444833b5581df073661deb8f3a"> 141</a></span><span class="preprocessor">#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8 </span></div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a8d0409818600c0b2acfe8253e8f027b8"> 145</a></span><span class="preprocessor">#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E </span></div> +<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aded7d7f5f4ba3a6d90f9a29e62a8cfab"> 146</a></span><span class="preprocessor">#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P </span></div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aca6cfc3f580c4dfe1e213009ee450c58"> 147</a></span><span class="preprocessor">#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9 </span></div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab4a2ac455d7426992de6877ea7325f21"> 148</a></span><span class="preprocessor">#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9 </span></div> +<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ace46f95dec73b33bf2535eb653bf8f65"> 152</a></span><span class="preprocessor">#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E </span></div> +<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a1fa2b25383e6d05cf26f3517091ddbbf"> 153</a></span><span class="preprocessor">#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P </span></div> +<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a568b54ba7dfdae736d8d685dc4d32113"> 154</a></span><span class="preprocessor">#define DMA_RTE_ID RTE_TRAP_FIRQ_10 </span></div> +<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ad2e81443af8a4ce2db3a4e3c1a8fb784"> 155</a></span><span class="preprocessor">#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10 </span></div> +<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a30cf20b6d704c50cc5c46238bb43646f"> 159</a></span><span class="preprocessor">#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E </span></div> +<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a68611c0dfbe331739eff10230ac3fede"> 160</a></span><span class="preprocessor">#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P </span></div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aa0ff72ea560d7e1462787dc31bd467cf"> 161</a></span><span class="preprocessor">#define SDI_RTE_ID RTE_TRAP_FIRQ_11 </span></div> +<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a68925ca3f482f148caedd36118fd8d79"> 162</a></span><span class="preprocessor">#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11 </span></div> +<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a0a59186908b498cb92273b7767966e26"> 166</a></span><span class="preprocessor">#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E </span></div> +<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a4a3164d123ddddd07750f868e67d82d8"> 167</a></span><span class="preprocessor">#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P </span></div> +<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aac38deeef36de0a474ab238a3054f860"> 168</a></span><span class="preprocessor">#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12 </span></div> +<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a445543c36d1f78477aa8ea4841c720a1"> 169</a></span><span class="preprocessor">#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12 </span></div> +<div class="line"><a id="l00173" name="l00173"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a8bb1918679e32e898af2d485cfa44afb"> 173</a></span><span class="preprocessor">#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E </span></div> +<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a3853ef999f99ca062e6025038811d0f0"> 174</a></span><span class="preprocessor">#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P </span></div> +<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a142f4a1c754edfab292706618d427b94"> 175</a></span><span class="preprocessor">#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13 </span></div> +<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a3e7aaa405a7d1fcd71a36c4b6b5a4081"> 176</a></span><span class="preprocessor">#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13 </span></div> +<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a8680ab1f14e512f21913572b35cbbf77"> 180</a></span><span class="preprocessor">#define SLINK_RX_FIRQ_ENABLE CSR_MIE_FIRQ14E </span></div> +<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a5c48d5c4effb47cdb019aa2da7c84526"> 181</a></span><span class="preprocessor">#define SLINK_RX_FIRQ_PENDING CSR_MIP_FIRQ14P </span></div> +<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a4fff18e72d10377cdcb8d2ac0a617a5d"> 182</a></span><span class="preprocessor">#define SLINK_RX_RTE_ID RTE_TRAP_FIRQ_14 </span></div> +<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ab1fdaedb2c4c8753ef3be87c82568dda"> 183</a></span><span class="preprocessor">#define SLINK_RX_TRAP_CODE TRAP_CODE_FIRQ_14 </span></div> +<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a232fe0eb5665373b6e2b464bdc228df2"> 184</a></span><span class="preprocessor">#define SLINK_TX_FIRQ_ENABLE CSR_MIE_FIRQ15E </span></div> +<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ac8e98b2af75c8e31f9815dee3dcbaf8e"> 185</a></span><span class="preprocessor">#define SLINK_TX_FIRQ_PENDING CSR_MIP_FIRQ15P </span></div> +<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a4e039d13b8d3f20453e1bb6b40512e43"> 186</a></span><span class="preprocessor">#define SLINK_TX_RTE_ID RTE_TRAP_FIRQ_15 </span></div> +<div class="line"><a id="l00187" name="l00187"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a7fbe28901775e284d5700086f0b0bfcd"> 187</a></span><span class="preprocessor">#define SLINK_TX_TRAP_CODE TRAP_CODE_FIRQ_15 </span></div> +<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"> 192</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span><span class="keyword">extern</span> <span class="keywordtype">char</span> <a class="code hl_variable" href="neorv32_8h.html#a0eaa3dcfb1db0c72534046feb9fa9b60">__heap_start</a>[]; </div> +<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span><span class="keyword">extern</span> <span class="keywordtype">char</span> <a class="code hl_variable" href="neorv32_8h.html#ae6ef7c715931df8bdc331577da14119b">__heap_end</a>[]; </div> +<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span><span class="keyword">extern</span> <span class="keywordtype">char</span> <a class="code hl_variable" href="neorv32_8h.html#aaa2cb9e7075a852870fd67eff2861b18">__crt0_max_heap</a>[]; </div> +<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span><span class="comment">// aliases</span></div> +<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"><a class="line" href="neorv32_8h.html#aca22a64c8c580dfde1676732d97ead7c"> 200</a></span><span class="preprocessor">#define neorv32_heap_begin_c ((uint32_t)&amp;__heap_start[0])</span></div> +<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"><a class="line" href="neorv32_8h.html#ac8b656bd05c05176638ea3f922228ca5"> 201</a></span><span class="preprocessor">#define neorv32_heap_end_c ((uint32_t)&amp;__heap_end[0])</span></div> +<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a32904e45632a47e21f7c9d873720cdc5"> 202</a></span><span class="preprocessor">#define neorv32_heap_size_c ((uint32_t)&amp;__crt0_max_heap[0])</span></div> +<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"> 206</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00210" data-start="{" data-end="};"> +<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73"> 210</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a> {</div> +<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73ad63d40139c50d76618cf1258cbdc0d05"> 211</a></span> <a class="code hl_enumvalue" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73ad63d40139c50d76618cf1258cbdc0d05">CLK_PRSC_2</a> = 0, </div> +<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a648249b3ab8c2500880c1e68b98f81d1"> 212</a></span> <a class="code hl_enumvalue" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a648249b3ab8c2500880c1e68b98f81d1">CLK_PRSC_4</a> = 1, </div> +<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73aa4e3a6a5b3cd895f63b4544f63ce22c9"> 213</a></span> <a class="code hl_enumvalue" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73aa4e3a6a5b3cd895f63b4544f63ce22c9">CLK_PRSC_8</a> = 2, </div> +<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a5990532893f2d9606e3c02aff60ca5da"> 214</a></span> <a class="code hl_enumvalue" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a5990532893f2d9606e3c02aff60ca5da">CLK_PRSC_64</a> = 3, </div> +<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a933045a5405de55781d687315f42054e"> 215</a></span> <a class="code hl_enumvalue" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a933045a5405de55781d687315f42054e">CLK_PRSC_128</a> = 4, </div> +<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a18aac15afd5ebd8d3a00dd6e513daf17"> 216</a></span> <a class="code hl_enumvalue" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a18aac15afd5ebd8d3a00dd6e513daf17">CLK_PRSC_1024</a> = 5, </div> +<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73aa138f0cad547028d5124f89d6dcc8c79"> 217</a></span> <a class="code hl_enumvalue" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73aa138f0cad547028d5124f89d6dcc8c79">CLK_PRSC_2048</a> = 6, </div> +<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span> <a class="code hl_enumvalue" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a0f20c29722bf9afc478b1a286a6b7eee">CLK_PRSC_4096</a> = 7 </div> +<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"><a class="line" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a0f20c29722bf9afc478b1a286a6b7eee"> 219</a></span>};</div> +</div> +<div class="line"><a id="l00223" name="l00223"></a><span class="lineno"> 223</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00228" data-start="{" data-end="};"> +<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"><a class="line" href="unionsubwords64__t.html"> 228</a></span><span class="keyword">typedef</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span> uint64_t uint64;</div> +<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span> uint32_t uint32[<span class="keyword">sizeof</span>(uint64_t)/<span class="keyword">sizeof</span>(uint32_t)];</div> +<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span> uint16_t uint16[<span class="keyword">sizeof</span>(uint64_t)/<span class="keyword">sizeof</span>(uint16_t)];</div> +<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span> uint8_t uint8[ <span class="keyword">sizeof</span>(uint64_t)/<span class="keyword">sizeof</span>(uint8_t)];</div> +<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span>} <a class="code hl_union" href="unionsubwords64__t.html">subwords64_t</a>;</div> +</div> +<div class="foldopen" id="foldopen00235" data-start="{" data-end="};"> +<div class="line"><a id="l00235" name="l00235"></a><span class="lineno"><a class="line" href="unionsubwords32__t.html"> 235</a></span><span class="keyword">typedef</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"> 236</span> uint32_t uint32[<span class="keyword">sizeof</span>(uint32_t)/<span class="keyword">sizeof</span>(uint32_t)];</div> +<div class="line"><a id="l00237" name="l00237"></a><span class="lineno"> 237</span> uint16_t uint16[<span class="keyword">sizeof</span>(uint32_t)/<span class="keyword">sizeof</span>(uint16_t)];</div> +<div class="line"><a id="l00238" name="l00238"></a><span class="lineno"> 238</span> uint8_t uint8[ <span class="keyword">sizeof</span>(uint32_t)/<span class="keyword">sizeof</span>(uint8_t)];</div> +<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"> 239</span>} <a class="code hl_union" href="unionsubwords32__t.html">subwords32_t</a>;</div> +</div> +<div class="foldopen" id="foldopen00241" data-start="{" data-end="};"> +<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"><a class="line" href="unionsubwords16__t.html"> 241</a></span><span class="keyword">typedef</span> <span class="keyword">union </span>{</div> +<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"> 242</span> uint16_t uint16[<span class="keyword">sizeof</span>(uint16_t)/<span class="keyword">sizeof</span>(uint16_t)];</div> +<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"> 243</span> uint8_t uint8[ <span class="keyword">sizeof</span>(uint16_t)/<span class="keyword">sizeof</span>(uint8_t)];</div> +<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"> 244</span>} <a class="code hl_union" href="unionsubwords16__t.html">subwords16_t</a>;</div> +</div> +<div class="line"><a id="l00248" name="l00248"></a><span class="lineno"> 248</span><span class="comment">// ----------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00249" name="l00249"></a><span class="lineno"> 249</span><span class="comment">// Include all system header files</span></div> +<div class="line"><a id="l00250" name="l00250"></a><span class="lineno"> 250</span><span class="comment">// ----------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00251" name="l00251"></a><span class="lineno"> 251</span><span class="comment">// intrinsics</span></div> +<div class="line"><a id="l00252" name="l00252"></a><span class="lineno"> 252</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__intrinsics_8h.html">neorv32_intrinsics.h</a>&quot;</span></div> +<div class="line"><a id="l00253" name="l00253"></a><span class="lineno"> 253</span> </div> +<div class="line"><a id="l00254" name="l00254"></a><span class="lineno"> 254</span><span class="comment">// helper functions</span></div> +<div class="line"><a id="l00255" name="l00255"></a><span class="lineno"> 255</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__aux_8h.html">neorv32_aux.h</a>&quot;</span></div> +<div class="line"><a id="l00256" name="l00256"></a><span class="lineno"> 256</span> </div> +<div class="line"><a id="l00257" name="l00257"></a><span class="lineno"> 257</span><span class="comment">// legacy compatibility layer</span></div> +<div class="line"><a id="l00258" name="l00258"></a><span class="lineno"> 258</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__legacy_8h.html">neorv32_legacy.h</a>&quot;</span></div> +<div class="line"><a id="l00259" name="l00259"></a><span class="lineno"> 259</span> </div> +<div class="line"><a id="l00260" name="l00260"></a><span class="lineno"> 260</span><span class="comment">// cpu core</span></div> +<div class="line"><a id="l00261" name="l00261"></a><span class="lineno"> 261</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__cpu_8h.html">neorv32_cpu.h</a>&quot;</span></div> +<div class="line"><a id="l00262" name="l00262"></a><span class="lineno"> 262</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__cpu__amo_8h.html">neorv32_cpu_amo.h</a>&quot;</span></div> +<div class="line"><a id="l00263" name="l00263"></a><span class="lineno"> 263</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__cpu__csr_8h.html">neorv32_cpu_csr.h</a>&quot;</span></div> +<div class="line"><a id="l00264" name="l00264"></a><span class="lineno"> 264</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__cpu__cfu_8h.html">neorv32_cpu_cfu.h</a>&quot;</span></div> +<div class="line"><a id="l00265" name="l00265"></a><span class="lineno"> 265</span> </div> +<div class="line"><a id="l00266" name="l00266"></a><span class="lineno"> 266</span><span class="comment">// NEORV32 runtime environment</span></div> +<div class="line"><a id="l00267" name="l00267"></a><span class="lineno"> 267</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__rte_8h.html">neorv32_rte.h</a>&quot;</span></div> +<div class="line"><a id="l00268" name="l00268"></a><span class="lineno"> 268</span> </div> +<div class="line"><a id="l00269" name="l00269"></a><span class="lineno"> 269</span><span class="comment">// IO/peripheral devices</span></div> +<div class="line"><a id="l00270" name="l00270"></a><span class="lineno"> 270</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__cfs_8h.html">neorv32_cfs.h</a>&quot;</span></div> +<div class="line"><a id="l00271" name="l00271"></a><span class="lineno"> 271</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__crc_8h.html">neorv32_crc.h</a>&quot;</span></div> +<div class="line"><a id="l00272" name="l00272"></a><span class="lineno"> 272</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__dma_8h.html">neorv32_dma.h</a>&quot;</span></div> +<div class="line"><a id="l00273" name="l00273"></a><span class="lineno"> 273</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__gpio_8h.html">neorv32_gpio.h</a>&quot;</span></div> +<div class="line"><a id="l00274" name="l00274"></a><span class="lineno"> 274</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__gptmr_8h.html">neorv32_gptmr.h</a>&quot;</span></div> +<div class="line"><a id="l00275" name="l00275"></a><span class="lineno"> 275</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__mtime_8h.html">neorv32_mtime.h</a>&quot;</span></div> +<div class="line"><a id="l00276" name="l00276"></a><span class="lineno"> 276</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__neoled_8h.html">neorv32_neoled.h</a>&quot;</span></div> +<div class="line"><a id="l00277" name="l00277"></a><span class="lineno"> 277</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__onewire_8h.html">neorv32_onewire.h</a>&quot;</span></div> +<div class="line"><a id="l00278" name="l00278"></a><span class="lineno"> 278</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__pwm_8h.html">neorv32_pwm.h</a>&quot;</span></div> +<div class="line"><a id="l00279" name="l00279"></a><span class="lineno"> 279</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__sdi_8h.html">neorv32_sdi.h</a>&quot;</span></div> +<div class="line"><a id="l00280" name="l00280"></a><span class="lineno"> 280</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__slink_8h.html">neorv32_slink.h</a>&quot;</span></div> +<div class="line"><a id="l00281" name="l00281"></a><span class="lineno"> 281</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__spi_8h.html">neorv32_spi.h</a>&quot;</span></div> +<div class="line"><a id="l00282" name="l00282"></a><span class="lineno"> 282</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__sysinfo_8h.html">neorv32_sysinfo.h</a>&quot;</span></div> +<div class="line"><a id="l00283" name="l00283"></a><span class="lineno"> 283</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__trng_8h.html">neorv32_trng.h</a>&quot;</span></div> +<div class="line"><a id="l00284" name="l00284"></a><span class="lineno"> 284</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__twi_8h.html">neorv32_twi.h</a>&quot;</span></div> +<div class="line"><a id="l00285" name="l00285"></a><span class="lineno"> 285</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__uart_8h.html">neorv32_uart.h</a>&quot;</span></div> +<div class="line"><a id="l00286" name="l00286"></a><span class="lineno"> 286</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__wdt_8h.html">neorv32_wdt.h</a>&quot;</span></div> +<div class="line"><a id="l00287" name="l00287"></a><span class="lineno"> 287</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__xip_8h.html">neorv32_xip.h</a>&quot;</span></div> +<div class="line"><a id="l00288" name="l00288"></a><span class="lineno"> 288</span><span class="preprocessor">#include &quot;<a class="code" href="neorv32__xirq_8h.html">neorv32_xirq.h</a>&quot;</span></div> +<div class="line"><a id="l00289" name="l00289"></a><span class="lineno"> 289</span> </div> +<div class="line"><a id="l00290" name="l00290"></a><span class="lineno"> 290</span> </div> +<div class="line"><a id="l00291" name="l00291"></a><span class="lineno"> 291</span><span class="preprocessor">#ifdef __cplusplus</span></div> +<div class="line"><a id="l00292" name="l00292"></a><span class="lineno"> 292</span>}</div> +<div class="line"><a id="l00293" name="l00293"></a><span class="lineno"> 293</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00294" name="l00294"></a><span class="lineno"> 294</span> </div> +<div class="line"><a id="l00295" name="l00295"></a><span class="lineno"> 295</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_h</span></div> +<div class="ttc" id="aneorv32_8h_html_a0eaa3dcfb1db0c72534046feb9fa9b60"><div class="ttname"><a href="neorv32_8h.html#a0eaa3dcfb1db0c72534046feb9fa9b60">__heap_start</a></div><div class="ttdeci">char __heap_start[]</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a></div><div class="ttdeci">NEORV32_CLOCK_PRSC_enum</div><div class="ttdef"><b>Definition</b> neorv32.h:210</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73a0f20c29722bf9afc478b1a286a6b7eee"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a0f20c29722bf9afc478b1a286a6b7eee">CLK_PRSC_4096</a></div><div class="ttdeci">@ CLK_PRSC_4096</div><div class="ttdef"><b>Definition</b> neorv32.h:218</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73a18aac15afd5ebd8d3a00dd6e513daf17"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a18aac15afd5ebd8d3a00dd6e513daf17">CLK_PRSC_1024</a></div><div class="ttdeci">@ CLK_PRSC_1024</div><div class="ttdef"><b>Definition</b> neorv32.h:216</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73a5990532893f2d9606e3c02aff60ca5da"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a5990532893f2d9606e3c02aff60ca5da">CLK_PRSC_64</a></div><div class="ttdeci">@ CLK_PRSC_64</div><div class="ttdef"><b>Definition</b> neorv32.h:214</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73a648249b3ab8c2500880c1e68b98f81d1"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a648249b3ab8c2500880c1e68b98f81d1">CLK_PRSC_4</a></div><div class="ttdeci">@ CLK_PRSC_4</div><div class="ttdef"><b>Definition</b> neorv32.h:212</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73a933045a5405de55781d687315f42054e"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73a933045a5405de55781d687315f42054e">CLK_PRSC_128</a></div><div class="ttdeci">@ CLK_PRSC_128</div><div class="ttdef"><b>Definition</b> neorv32.h:215</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73aa138f0cad547028d5124f89d6dcc8c79"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73aa138f0cad547028d5124f89d6dcc8c79">CLK_PRSC_2048</a></div><div class="ttdeci">@ CLK_PRSC_2048</div><div class="ttdef"><b>Definition</b> neorv32.h:217</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73aa4e3a6a5b3cd895f63b4544f63ce22c9"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73aa4e3a6a5b3cd895f63b4544f63ce22c9">CLK_PRSC_8</a></div><div class="ttdeci">@ CLK_PRSC_8</div><div class="ttdef"><b>Definition</b> neorv32.h:213</div></div> +<div class="ttc" id="aneorv32_8h_html_a10022df4c223533b04d5aebe222e8b73ad63d40139c50d76618cf1258cbdc0d05"><div class="ttname"><a href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73ad63d40139c50d76618cf1258cbdc0d05">CLK_PRSC_2</a></div><div class="ttdeci">@ CLK_PRSC_2</div><div class="ttdef"><b>Definition</b> neorv32.h:211</div></div> +<div class="ttc" id="aneorv32_8h_html_aaa2cb9e7075a852870fd67eff2861b18"><div class="ttname"><a href="neorv32_8h.html#aaa2cb9e7075a852870fd67eff2861b18">__crt0_max_heap</a></div><div class="ttdeci">char __crt0_max_heap[]</div></div> +<div class="ttc" id="aneorv32_8h_html_ae6ef7c715931df8bdc331577da14119b"><div class="ttname"><a href="neorv32_8h.html#ae6ef7c715931df8bdc331577da14119b">__heap_end</a></div><div class="ttdeci">char __heap_end[]</div></div> +<div class="ttc" id="aneorv32__aux_8h_html"><div class="ttname"><a href="neorv32__aux_8h.html">neorv32_aux.h</a></div><div class="ttdoc">General auxiliary functions header file.</div></div> +<div class="ttc" id="aneorv32__cfs_8h_html"><div class="ttname"><a href="neorv32__cfs_8h.html">neorv32_cfs.h</a></div><div class="ttdoc">Custom Functions Subsystem (CFS) HW driver header file.</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html"><div class="ttname"><a href="neorv32__cpu_8h.html">neorv32_cpu.h</a></div><div class="ttdoc">CPU Core Functions HW driver header file.</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html"><div class="ttname"><a href="neorv32__cpu__amo_8h.html">neorv32_cpu_amo.h</a></div><div class="ttdoc">Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - header file.</div></div> +<div class="ttc" id="aneorv32__cpu__cfu_8h_html"><div class="ttname"><a href="neorv32__cpu__cfu_8h.html">neorv32_cpu_cfu.h</a></div><div class="ttdoc">CPU Core custom functions unit HW driver header file.</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html"><div class="ttname"><a href="neorv32__cpu__csr_8h.html">neorv32_cpu_csr.h</a></div><div class="ttdoc">Control and Status Registers (CSR) definitions.</div></div> +<div class="ttc" id="aneorv32__crc_8h_html"><div class="ttname"><a href="neorv32__crc_8h.html">neorv32_crc.h</a></div><div class="ttdoc">Cyclic redundancy check unit (CRC) HW driver header file.</div></div> +<div class="ttc" id="aneorv32__dma_8h_html"><div class="ttname"><a href="neorv32__dma_8h.html">neorv32_dma.h</a></div><div class="ttdoc">Direct Memory Access Controller (DMA) HW driver header file.</div></div> +<div class="ttc" id="aneorv32__gpio_8h_html"><div class="ttname"><a href="neorv32__gpio_8h.html">neorv32_gpio.h</a></div><div class="ttdoc">General purpose input/output port unit (GPIO) HW driver header file.</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html"><div class="ttname"><a href="neorv32__gptmr_8h.html">neorv32_gptmr.h</a></div><div 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class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a94aa8369ba5f4ebdf5628fcb1ab2ba1c" id="r_a94aa8369ba5f4ebdf5628fcb1ab2ba1c"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a94aa8369ba5f4ebdf5628fcb1ab2ba1c">neorv32_aux_date2unixtime</a> (<a class="el" href="structdate__t.html">date_t</a> *date)</td></tr> +<tr class="separator:a94aa8369ba5f4ebdf5628fcb1ab2ba1c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a885a81838a91b57797e849cb835c6887" id="r_a885a81838a91b57797e849cb835c6887"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a885a81838a91b57797e849cb835c6887">neorv32_aux_unixtime2date</a> (uint64_t unixtime, <a class="el" href="structdate__t.html">date_t</a> *date)</td></tr> +<tr class="separator:a885a81838a91b57797e849cb835c6887"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a05a5482da3b72a5bdf2181e754143d79" id="r_a05a5482da3b72a5bdf2181e754143d79"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a05a5482da3b72a5bdf2181e754143d79">neorv32_aux_hexstr2uint64</a> (char *buffer, unsigned int length)</td></tr> +<tr class="separator:a05a5482da3b72a5bdf2181e754143d79"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aff31dd983f75f70eeae331c65acaa50e" id="r_aff31dd983f75f70eeae331c65acaa50e"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aff31dd983f75f70eeae331c65acaa50e">neorv32_aux_xorshift32</a> (void)</td></tr> +<tr class="separator:aff31dd983f75f70eeae331c65acaa50e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af72230251bc58d3142353849f63d5667" id="r_af72230251bc58d3142353849f63d5667"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af72230251bc58d3142353849f63d5667">neorv32_aux_itoa</a> (char *buffer, uint32_t num, uint32_t base)</td></tr> +<tr class="separator:af72230251bc58d3142353849f63d5667"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>General auxiliary functions source file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a94aa8369ba5f4ebdf5628fcb1ab2ba1c" name="a94aa8369ba5f4ebdf5628fcb1ab2ba1c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a94aa8369ba5f4ebdf5628fcb1ab2ba1c">&#9670;&#160;</a></span>neorv32_aux_date2unixtime()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_aux_date2unixtime </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structdate__t.html">date_t</a> *</td> <td class="paramname"><span class="paramname"><em>date</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Convert date to Unix time stamp.</p> +<dl class="section copyright"><dt>Copyright</dt><dd>Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved. SPDX-License-Identifier: GPL-2.0-or-later <a href="https://github.com/Oryx-Embedded/Common/blob/master/date_time.c">https://github.com/Oryx-Embedded/Common/blob/master/date_time.c</a></dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">date</td><td>Pointer to date and time struct (<a class="el" href="structdate__t.html">date_t</a>). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Unix time since 00:00:00 UTC, January 1, 1970 in seconds. </dd></dl> + +</div> +</div> +<a id="a05a5482da3b72a5bdf2181e754143d79" name="a05a5482da3b72a5bdf2181e754143d79"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a05a5482da3b72a5bdf2181e754143d79">&#9670;&#160;</a></span>neorv32_aux_hexstr2uint64()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_aux_hexstr2uint64 </td> + <td>(</td> + <td class="paramtype">char *</td> <td class="paramname"><span class="paramname"><em>buffer</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">unsigned int</td> <td class="paramname"><span class="paramname"><em>length</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Helper function to convert up to 16 hex chars string into uint64_t</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">buffer</td><td>Pointer to array of chars to convert into number. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">length</td><td>Length of the conversion string. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Converted number (uint64_t). </dd></dl> + +</div> +</div> +<a id="af72230251bc58d3142353849f63d5667" name="af72230251bc58d3142353849f63d5667"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af72230251bc58d3142353849f63d5667">&#9670;&#160;</a></span>neorv32_aux_itoa()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_aux_itoa </td> + <td>(</td> + <td class="paramtype">char *</td> <td class="paramname"><span class="paramname"><em>buffer</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>base</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Simplified version of "itoa": convert number to string.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">buffer</td><td>Pointer to array for the result string [33 chars]. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Number to convert. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">base</td><td>Base of number representation (2..16). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a885a81838a91b57797e849cb835c6887" name="a885a81838a91b57797e849cb835c6887"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a885a81838a91b57797e849cb835c6887">&#9670;&#160;</a></span>neorv32_aux_unixtime2date()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_aux_unixtime2date </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>unixtime</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"><a class="el" href="structdate__t.html">date_t</a> *</td> <td class="paramname"><span class="paramname"><em>date</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Convert Unix time stamp to date.</p> +<dl class="section copyright"><dt>Copyright</dt><dd>Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved. SPDX-License-Identifier: GPL-2.0-or-later <a href="https://github.com/Oryx-Embedded/Common/blob/master/date_time.c">https://github.com/Oryx-Embedded/Common/blob/master/date_time.c</a></dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">unixtime</td><td>Unix time since 00:00:00 UTC, January 1, 1970 in seconds. </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">date</td><td>Pointer to date and time struct (<a class="el" href="structdate__t.html">date_t</a>). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aff31dd983f75f70eeae331c65acaa50e" name="aff31dd983f75f70eeae331c65acaa50e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aff31dd983f75f70eeae331c65acaa50e">&#9670;&#160;</a></span>neorv32_aux_xorshift32()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_aux_xorshift32 </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>XORSHIFT pseudo random number generator.</p> +<dl class="section return"><dt>Returns</dt><dd>Random number (uint32_t). </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__aux_8h.html b/sw/neorv32__aux_8h.html new file mode 100644 index 000000000..733a368f3 --- /dev/null +++ b/sw/neorv32__aux_8h.html @@ -0,0 +1,328 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" 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+<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__aux_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdate__t.html">date_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Select minimum/maximum</div></td></tr> +<tr class="memitem:aa18754c48dc72c66679e024e074f0f47" id="r_aa18754c48dc72c66679e024e074f0f47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa18754c48dc72c66679e024e074f0f47">neorv32_aux_min</a>(a, b)</td></tr> +<tr class="separator:aa18754c48dc72c66679e024e074f0f47"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7be19d0ada72a1071a4baac9367702d1" id="r_a7be19d0ada72a1071a4baac9367702d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7be19d0ada72a1071a4baac9367702d1">neorv32_aux_max</a>(a, b)</td></tr> +<tr class="separator:a7be19d0ada72a1071a4baac9367702d1"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">AUX prototypes</div></td></tr> +<tr class="memitem:a94aa8369ba5f4ebdf5628fcb1ab2ba1c" id="r_a94aa8369ba5f4ebdf5628fcb1ab2ba1c"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a94aa8369ba5f4ebdf5628fcb1ab2ba1c">neorv32_aux_date2unixtime</a> (<a class="el" href="structdate__t.html">date_t</a> *date)</td></tr> +<tr class="separator:a94aa8369ba5f4ebdf5628fcb1ab2ba1c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a885a81838a91b57797e849cb835c6887" id="r_a885a81838a91b57797e849cb835c6887"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a885a81838a91b57797e849cb835c6887">neorv32_aux_unixtime2date</a> (uint64_t unixtime, <a class="el" href="structdate__t.html">date_t</a> *date)</td></tr> +<tr class="separator:a885a81838a91b57797e849cb835c6887"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a05a5482da3b72a5bdf2181e754143d79" id="r_a05a5482da3b72a5bdf2181e754143d79"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a05a5482da3b72a5bdf2181e754143d79">neorv32_aux_hexstr2uint64</a> (char *buffer, unsigned int length)</td></tr> +<tr class="separator:a05a5482da3b72a5bdf2181e754143d79"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aff31dd983f75f70eeae331c65acaa50e" id="r_aff31dd983f75f70eeae331c65acaa50e"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aff31dd983f75f70eeae331c65acaa50e">neorv32_aux_xorshift32</a> (void)</td></tr> +<tr class="separator:aff31dd983f75f70eeae331c65acaa50e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af72230251bc58d3142353849f63d5667" id="r_af72230251bc58d3142353849f63d5667"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af72230251bc58d3142353849f63d5667">neorv32_aux_itoa</a> (char *buffer, uint32_t num, uint32_t base)</td></tr> +<tr class="separator:af72230251bc58d3142353849f63d5667"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>General auxiliary functions header file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a7be19d0ada72a1071a4baac9367702d1" name="a7be19d0ada72a1071a4baac9367702d1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7be19d0ada72a1071a4baac9367702d1">&#9670;&#160;</a></span>neorv32_aux_max</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_aux_max</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>a</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>b</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a &gt; _b ? _a : _b; })</div> +</div><!-- fragment --> +</div> +</div> +<a id="aa18754c48dc72c66679e024e074f0f47" name="aa18754c48dc72c66679e024e074f0f47"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa18754c48dc72c66679e024e074f0f47">&#9670;&#160;</a></span>neorv32_aux_min</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_aux_min</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>a</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>b</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a &lt; _b ? _a : _b; })</div> +</div><!-- fragment --> +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a94aa8369ba5f4ebdf5628fcb1ab2ba1c" name="a94aa8369ba5f4ebdf5628fcb1ab2ba1c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a94aa8369ba5f4ebdf5628fcb1ab2ba1c">&#9670;&#160;</a></span>neorv32_aux_date2unixtime()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_aux_date2unixtime </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structdate__t.html">date_t</a> *</td> <td class="paramname"><span class="paramname"><em>date</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Convert date to Unix time stamp.</p> +<dl class="section copyright"><dt>Copyright</dt><dd>Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved. SPDX-License-Identifier: GPL-2.0-or-later <a href="https://github.com/Oryx-Embedded/Common/blob/master/date_time.c">https://github.com/Oryx-Embedded/Common/blob/master/date_time.c</a></dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">date</td><td>Pointer to date and time struct (<a class="el" href="structdate__t.html">date_t</a>). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Unix time since 00:00:00 UTC, January 1, 1970 in seconds. </dd></dl> + +</div> +</div> +<a id="a05a5482da3b72a5bdf2181e754143d79" name="a05a5482da3b72a5bdf2181e754143d79"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a05a5482da3b72a5bdf2181e754143d79">&#9670;&#160;</a></span>neorv32_aux_hexstr2uint64()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_aux_hexstr2uint64 </td> + <td>(</td> + <td class="paramtype">char *</td> <td class="paramname"><span class="paramname"><em>buffer</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">unsigned int</td> <td class="paramname"><span class="paramname"><em>length</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Helper function to convert up to 16 hex chars string into uint64_t</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">buffer</td><td>Pointer to array of chars to convert into number. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">length</td><td>Length of the conversion string. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Converted number (uint64_t). </dd></dl> + +</div> +</div> +<a id="af72230251bc58d3142353849f63d5667" name="af72230251bc58d3142353849f63d5667"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af72230251bc58d3142353849f63d5667">&#9670;&#160;</a></span>neorv32_aux_itoa()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_aux_itoa </td> + <td>(</td> + <td class="paramtype">char *</td> <td class="paramname"><span class="paramname"><em>buffer</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>base</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Simplified version of "itoa": convert number to string.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">buffer</td><td>Pointer to array for the result string [33 chars]. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Number to convert. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">base</td><td>Base of number representation (2..16). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a885a81838a91b57797e849cb835c6887" name="a885a81838a91b57797e849cb835c6887"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a885a81838a91b57797e849cb835c6887">&#9670;&#160;</a></span>neorv32_aux_unixtime2date()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_aux_unixtime2date </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>unixtime</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"><a class="el" href="structdate__t.html">date_t</a> *</td> <td class="paramname"><span class="paramname"><em>date</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Convert Unix time stamp to date.</p> +<dl class="section copyright"><dt>Copyright</dt><dd>Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved. SPDX-License-Identifier: GPL-2.0-or-later <a href="https://github.com/Oryx-Embedded/Common/blob/master/date_time.c">https://github.com/Oryx-Embedded/Common/blob/master/date_time.c</a></dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">unixtime</td><td>Unix time since 00:00:00 UTC, January 1, 1970 in seconds. </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">date</td><td>Pointer to date and time struct (<a class="el" href="structdate__t.html">date_t</a>). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aff31dd983f75f70eeae331c65acaa50e" name="aff31dd983f75f70eeae331c65acaa50e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aff31dd983f75f70eeae331c65acaa50e">&#9670;&#160;</a></span>neorv32_aux_xorshift32()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_aux_xorshift32 </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>XORSHIFT pseudo random number generator.</p> +<dl class="section return"><dt>Returns</dt><dd>Random number (uint32_t). </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__aux_8h_source.html b/sw/neorv32__aux_8h_source.html new file mode 100644 index 000000000..e80fdd6f7 --- /dev/null +++ b/sw/neorv32__aux_8h_source.html @@ -0,0 +1,154 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_aux.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_aux.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__aux_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="preprocessor">#ifndef neorv32_aux_h</span></div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#define neorv32_aux_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span> </div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span><span class="preprocessor">#define neorv32_aux_min(a, b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a &lt; _b ? _a : _b; })</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span><span class="preprocessor">#define neorv32_aux_max(a, b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a &gt; _b ? _a : _b; })</span></div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00033" data-start="{" data-end="};"> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"><a class="line" href="structdate__t.html"> 33</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"><a class="line" href="structdate__t.html#aabab1b1efd94b69bfb28b639c612dd4f"> 34</a></span> uint16_t <a class="code hl_variable" href="structdate__t.html#aabab1b1efd94b69bfb28b639c612dd4f">year</a>; </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="structdate__t.html#a1a97f6a755cd4209a0880cf811d52c7b"> 35</a></span> uint8_t <a class="code hl_variable" href="structdate__t.html#a1a97f6a755cd4209a0880cf811d52c7b">month</a>; </div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"><a class="line" href="structdate__t.html#a482ad87226bae7841dfec63e035aeace"> 36</a></span> uint8_t <a class="code hl_variable" href="structdate__t.html#a482ad87226bae7841dfec63e035aeace">day</a>; </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="structdate__t.html#a44167cd71416886e55048310af6d4e1b"> 37</a></span> uint8_t <a class="code hl_variable" href="structdate__t.html#a44167cd71416886e55048310af6d4e1b">weekday</a>; </div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="structdate__t.html#a39a23695634a2814d827984f4eea54eb"> 38</a></span> uint8_t <a class="code hl_variable" href="structdate__t.html#a39a23695634a2814d827984f4eea54eb">hours</a>; </div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="structdate__t.html#a2ab79834ebae42979e359bf30ad5f67a"> 39</a></span> uint8_t <a class="code hl_variable" href="structdate__t.html#a2ab79834ebae42979e359bf30ad5f67a">minutes</a>; </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="structdate__t.html#a1071948e7754cb415da9714d59a315bf"> 40</a></span> uint8_t <a class="code hl_variable" href="structdate__t.html#a1071948e7754cb415da9714d59a315bf">seconds</a>; </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span>} <a class="code hl_struct" href="structdate__t.html">date_t</a>;</div> +</div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span> </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span>uint64_t <a class="code hl_function" href="neorv32__aux_8h.html#a94aa8369ba5f4ebdf5628fcb1ab2ba1c">neorv32_aux_date2unixtime</a>(<a class="code hl_struct" href="structdate__t.html">date_t</a>* date);</div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__aux_8h.html#a885a81838a91b57797e849cb835c6887">neorv32_aux_unixtime2date</a>(uint64_t unixtime, <a class="code hl_struct" href="structdate__t.html">date_t</a>* date);</div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span>uint64_t <a class="code hl_function" href="neorv32__aux_8h.html#a05a5482da3b72a5bdf2181e754143d79">neorv32_aux_hexstr2uint64</a>(<span class="keywordtype">char</span> *buffer, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length);</div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span>uint32_t <a class="code hl_function" href="neorv32__aux_8h.html#aff31dd983f75f70eeae331c65acaa50e">neorv32_aux_xorshift32</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__aux_8h.html#af72230251bc58d3142353849f63d5667">neorv32_aux_itoa</a>(<span class="keywordtype">char</span> *buffer, uint32_t num, uint32_t base);</div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_aux_h</span></div> +<div class="ttc" id="aneorv32__aux_8h_html_a05a5482da3b72a5bdf2181e754143d79"><div class="ttname"><a href="neorv32__aux_8h.html#a05a5482da3b72a5bdf2181e754143d79">neorv32_aux_hexstr2uint64</a></div><div class="ttdeci">uint64_t neorv32_aux_hexstr2uint64(char *buffer, unsigned int length)</div><div class="ttdef"><b>Definition</b> neorv32_aux.c:151</div></div> +<div class="ttc" id="aneorv32__aux_8h_html_a885a81838a91b57797e849cb835c6887"><div class="ttname"><a href="neorv32__aux_8h.html#a885a81838a91b57797e849cb835c6887">neorv32_aux_unixtime2date</a></div><div class="ttdeci">void neorv32_aux_unixtime2date(uint64_t unixtime, date_t *date)</div><div class="ttdef"><b>Definition</b> neorv32_aux.c:85</div></div> +<div class="ttc" id="aneorv32__aux_8h_html_a94aa8369ba5f4ebdf5628fcb1ab2ba1c"><div class="ttname"><a href="neorv32__aux_8h.html#a94aa8369ba5f4ebdf5628fcb1ab2ba1c">neorv32_aux_date2unixtime</a></div><div class="ttdeci">uint64_t neorv32_aux_date2unixtime(date_t *date)</div><div class="ttdef"><b>Definition</b> neorv32_aux.c:28</div></div> +<div class="ttc" id="aneorv32__aux_8h_html_af72230251bc58d3142353849f63d5667"><div class="ttname"><a href="neorv32__aux_8h.html#af72230251bc58d3142353849f63d5667">neorv32_aux_itoa</a></div><div class="ttdeci">void neorv32_aux_itoa(char *buffer, uint32_t num, uint32_t base)</div><div class="ttdef"><b>Definition</b> neorv32_aux.c:214</div></div> +<div class="ttc" id="aneorv32__aux_8h_html_aff31dd983f75f70eeae331c65acaa50e"><div class="ttname"><a href="neorv32__aux_8h.html#aff31dd983f75f70eeae331c65acaa50e">neorv32_aux_xorshift32</a></div><div class="ttdeci">uint32_t neorv32_aux_xorshift32(void)</div><div class="ttdef"><b>Definition</b> neorv32_aux.c:195</div></div> +<div class="ttc" id="astructdate__t_html"><div class="ttname"><a href="structdate__t.html">date_t</a></div><div class="ttdef"><b>Definition</b> neorv32_aux.h:33</div></div> +<div class="ttc" id="astructdate__t_html_a1071948e7754cb415da9714d59a315bf"><div class="ttname"><a href="structdate__t.html#a1071948e7754cb415da9714d59a315bf">date_t::seconds</a></div><div class="ttdeci">uint8_t seconds</div><div class="ttdef"><b>Definition</b> neorv32_aux.h:40</div></div> +<div class="ttc" id="astructdate__t_html_a1a97f6a755cd4209a0880cf811d52c7b"><div class="ttname"><a href="structdate__t.html#a1a97f6a755cd4209a0880cf811d52c7b">date_t::month</a></div><div class="ttdeci">uint8_t month</div><div class="ttdef"><b>Definition</b> neorv32_aux.h:35</div></div> +<div class="ttc" id="astructdate__t_html_a2ab79834ebae42979e359bf30ad5f67a"><div class="ttname"><a href="structdate__t.html#a2ab79834ebae42979e359bf30ad5f67a">date_t::minutes</a></div><div class="ttdeci">uint8_t minutes</div><div class="ttdef"><b>Definition</b> neorv32_aux.h:39</div></div> +<div class="ttc" id="astructdate__t_html_a39a23695634a2814d827984f4eea54eb"><div class="ttname"><a href="structdate__t.html#a39a23695634a2814d827984f4eea54eb">date_t::hours</a></div><div class="ttdeci">uint8_t hours</div><div class="ttdef"><b>Definition</b> neorv32_aux.h:38</div></div> +<div class="ttc" id="astructdate__t_html_a44167cd71416886e55048310af6d4e1b"><div class="ttname"><a href="structdate__t.html#a44167cd71416886e55048310af6d4e1b">date_t::weekday</a></div><div class="ttdeci">uint8_t weekday</div><div class="ttdef"><b>Definition</b> neorv32_aux.h:37</div></div> +<div class="ttc" id="astructdate__t_html_a482ad87226bae7841dfec63e035aeace"><div class="ttname"><a href="structdate__t.html#a482ad87226bae7841dfec63e035aeace">date_t::day</a></div><div class="ttdeci">uint8_t day</div><div class="ttdef"><b>Definition</b> neorv32_aux.h:36</div></div> +<div class="ttc" id="astructdate__t_html_aabab1b1efd94b69bfb28b639c612dd4f"><div class="ttname"><a href="structdate__t.html#aabab1b1efd94b69bfb28b639c612dd4f">date_t::year</a></div><div class="ttdeci">uint16_t year</div><div class="ttdef"><b>Definition</b> neorv32_aux.h:34</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> 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id="r_abac96dfaefe433eca1c0b93fa6183d2e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abac96dfaefe433eca1c0b93fa6183d2e">neorv32_cfs_available</a> (void)</td></tr> +<tr class="separator:abac96dfaefe433eca1c0b93fa6183d2e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Custom Functions Subsystem (CFS) HW driver source file. </p> +<dl class="section warning"><dt>Warning</dt><dd>There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware. </dd> +<dd> +Hence, the CFS designer has to provide the actual driver functions.</dd></dl> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the CFS was synthesized (IO_CFS_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="abac96dfaefe433eca1c0b93fa6183d2e" name="abac96dfaefe433eca1c0b93fa6183d2e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abac96dfaefe433eca1c0b93fa6183d2e">&#9670;&#160;</a></span>neorv32_cfs_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_cfs_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if custom functions subsystem was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if CFS was not synthesized, 1 if CFS is available. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__cfs_8h.html b/sw/neorv32__cfs_8h.html new file mode 100644 index 000000000..4af6c7f6d --- /dev/null +++ b/sw/neorv32__cfs_8h.html @@ -0,0 +1,172 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_cfs.h File Reference</title> +<link href="tabs.css" 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class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__cfs__t.html">neorv32_cfs_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">IO Device: Custom Functions Subsystem (CFS)</div></td></tr> +<tr class="memitem:a6c101b306bd096f78d351e39b308d3e2" id="r_a6c101b306bd096f78d351e39b308d3e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6c101b306bd096f78d351e39b308d3e2">NEORV32_CFS</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__cfs__t.html">neorv32_cfs_t</a>*) (<a class="el" href="neorv32_8h.html#a41d6f97daef61641da96b9f72f6b272f">NEORV32_CFS_BASE</a>))</td></tr> +<tr class="separator:a6c101b306bd096f78d351e39b308d3e2"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:abac96dfaefe433eca1c0b93fa6183d2e" id="r_abac96dfaefe433eca1c0b93fa6183d2e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abac96dfaefe433eca1c0b93fa6183d2e">neorv32_cfs_available</a> (void)</td></tr> +<tr class="separator:abac96dfaefe433eca1c0b93fa6183d2e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Custom Functions Subsystem (CFS) HW driver header file. </p> +<dl class="section warning"><dt>Warning</dt><dd>There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware. </dd> +<dd> +The CFS designer has to provide the actual driver functions.</dd></dl> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the CFS was synthesized (IO_CFS_EN = true). </dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a6c101b306bd096f78d351e39b308d3e2" name="a6c101b306bd096f78d351e39b308d3e2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6c101b306bd096f78d351e39b308d3e2">&#9670;&#160;</a></span>NEORV32_CFS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_CFS&#160;&#160;&#160;((<a class="el" href="structneorv32__cfs__t.html">neorv32_cfs_t</a>*) (<a class="el" href="neorv32_8h.html#a41d6f97daef61641da96b9f72f6b272f">NEORV32_CFS_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CFS module hardware access (<a class="el" href="structneorv32__cfs__t.html">neorv32_cfs_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="abac96dfaefe433eca1c0b93fa6183d2e" name="abac96dfaefe433eca1c0b93fa6183d2e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abac96dfaefe433eca1c0b93fa6183d2e">&#9670;&#160;</a></span>neorv32_cfs_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_cfs_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if custom functions subsystem was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if CFS was not synthesized, 1 if CFS is available. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__cfs_8h_source.html b/sw/neorv32__cfs_8h_source.html new file mode 100644 index 000000000..74b113e5d --- /dev/null +++ b/sw/neorv32__cfs_8h_source.html @@ -0,0 +1,130 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta 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id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_cfs.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__cfs_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="preprocessor">#ifndef neorv32_cfs_h</span></div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#define neorv32_cfs_h</span></div> +<div class="line"><a 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name="l00032"></a><span class="lineno"><a class="line" href="structneorv32__cfs__t.html#a48d3e81b207f4dcce0b0cc901583dc4d"> 32</a></span> uint32_t REG[64]; </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span>} <a class="code hl_struct" href="structneorv32__cfs__t.html">neorv32_cfs_t</a>;</div> +</div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> </div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"><a class="line" href="neorv32__cfs_8h.html#a6c101b306bd096f78d351e39b308d3e2"> 36</a></span><span class="preprocessor">#define NEORV32_CFS ((neorv32_cfs_t*) (NEORV32_CFS_BASE))</span></div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__cfs_8h.html#abac96dfaefe433eca1c0b93fa6183d2e">neorv32_cfs_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_cfs_h</span></div> +<div class="ttc" id="aneorv32__cfs_8h_html_abac96dfaefe433eca1c0b93fa6183d2e"><div class="ttname"><a href="neorv32__cfs_8h.html#abac96dfaefe433eca1c0b93fa6183d2e">neorv32_cfs_available</a></div><div class="ttdeci">int neorv32_cfs_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_cfs.c:29</div></div> +<div class="ttc" id="astructneorv32__cfs__t_html"><div class="ttname"><a href="structneorv32__cfs__t.html">neorv32_cfs_t</a></div><div class="ttdef"><b>Definition</b> neorv32_cfs.h:31</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address 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href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_cpu.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>CPU Core Functions HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ac3fd7dc7cd1e0a08225c41820af27f92" id="r_ac3fd7dc7cd1e0a08225c41820af27f92"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac3fd7dc7cd1e0a08225c41820af27f92">neorv32_cpu_get_cycle</a> (void)</td></tr> +<tr class="separator:ac3fd7dc7cd1e0a08225c41820af27f92"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a232d0290c459dc790d989fcdc4d121bf" id="r_a232d0290c459dc790d989fcdc4d121bf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a232d0290c459dc790d989fcdc4d121bf">neorv32_cpu_set_mcycle</a> (uint64_t value)</td></tr> +<tr class="separator:a232d0290c459dc790d989fcdc4d121bf"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a387aa304770b05594c4acca128a60a75" id="r_a387aa304770b05594c4acca128a60a75"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a387aa304770b05594c4acca128a60a75">neorv32_cpu_get_instret</a> (void)</td></tr> +<tr class="separator:a387aa304770b05594c4acca128a60a75"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5c3cf52498abb3cf3c14a724b287ecf0" id="r_a5c3cf52498abb3cf3c14a724b287ecf0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5c3cf52498abb3cf3c14a724b287ecf0">neorv32_cpu_set_minstret</a> (uint64_t value)</td></tr> +<tr class="separator:a5c3cf52498abb3cf3c14a724b287ecf0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa9027535b13d9f9325e734997fc4a137" id="r_aa9027535b13d9f9325e734997fc4a137"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa9027535b13d9f9325e734997fc4a137">neorv32_cpu_delay_ms</a> (uint32_t time_ms)</td></tr> +<tr class="separator:aa9027535b13d9f9325e734997fc4a137"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8346fb926f84f3d7bccbb4741105505f" id="r_a8346fb926f84f3d7bccbb4741105505f"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8346fb926f84f3d7bccbb4741105505f">neorv32_cpu_get_clk_from_prsc</a> (int prsc)</td></tr> +<tr class="separator:a8346fb926f84f3d7bccbb4741105505f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a27dd614bc270dfa30ed73323ebda2d2d" id="r_a27dd614bc270dfa30ed73323ebda2d2d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a27dd614bc270dfa30ed73323ebda2d2d">neorv32_cpu_pmp_get_num_regions</a> (void)</td></tr> +<tr class="separator:a27dd614bc270dfa30ed73323ebda2d2d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad4f8160f4821b6691e9682ef60c7cd7b" id="r_ad4f8160f4821b6691e9682ef60c7cd7b"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4f8160f4821b6691e9682ef60c7cd7b">neorv32_cpu_pmp_get_granularity</a> (void)</td></tr> +<tr class="separator:ad4f8160f4821b6691e9682ef60c7cd7b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa458a700619b2f7666cfcffe02ec2e2c" id="r_aa458a700619b2f7666cfcffe02ec2e2c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa458a700619b2f7666cfcffe02ec2e2c">neorv32_cpu_pmp_configure_region</a> (int index, uint32_t addr, uint8_t config)</td></tr> +<tr class="separator:aa458a700619b2f7666cfcffe02ec2e2c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a70f49b80322aa457f29f7671f94a183d" id="r_a70f49b80322aa457f29f7671f94a183d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a70f49b80322aa457f29f7671f94a183d">neorv32_cpu_hpm_get_num_counters</a> (void)</td></tr> +<tr class="separator:a70f49b80322aa457f29f7671f94a183d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adb3ae542bbb0ddf9f562a4e42bc24d10" id="r_adb3ae542bbb0ddf9f562a4e42bc24d10"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adb3ae542bbb0ddf9f562a4e42bc24d10">neorv32_cpu_hpm_get_size</a> (void)</td></tr> +<tr class="separator:adb3ae542bbb0ddf9f562a4e42bc24d10"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aca49efb45d3808ad76cf65ba291f546d" id="r_aca49efb45d3808ad76cf65ba291f546d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aca49efb45d3808ad76cf65ba291f546d">neorv32_cpu_goto_user_mode</a> (void)</td></tr> +<tr class="separator:aca49efb45d3808ad76cf65ba291f546d"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>CPU Core Functions HW driver source file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="aa9027535b13d9f9325e734997fc4a137" name="aa9027535b13d9f9325e734997fc4a137"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa9027535b13d9f9325e734997fc4a137">&#9670;&#160;</a></span>neorv32_cpu_delay_ms()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_delay_ms </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>time_ms</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Delay function using busy wait.</p> +<dl class="section note"><dt>Note</dt><dd>This function uses the cycle CPU counter if available. Otherwise the MTIME system timer is used if available. A simple loop is used as alternative fall-back (imprecise!).</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">time_ms</td><td>Time in ms to wait (unsigned 32-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a8346fb926f84f3d7bccbb4741105505f" name="a8346fb926f84f3d7bccbb4741105505f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8346fb926f84f3d7bccbb4741105505f">&#9670;&#160;</a></span>neorv32_cpu_get_clk_from_prsc()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_get_clk_from_prsc </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get actual clocking frequency from prescaler select <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a></p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Prescaler select <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. return Actual <em>raw</em> clock frequency in Hz. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac3fd7dc7cd1e0a08225c41820af27f92" name="ac3fd7dc7cd1e0a08225c41820af27f92"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac3fd7dc7cd1e0a08225c41820af27f92">&#9670;&#160;</a></span>neorv32_cpu_get_cycle()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_cpu_get_cycle </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Unavailable extensions warnings. Get cycle counter from cycle[h].</p> +<dl class="section return"><dt>Returns</dt><dd>Current cycle counter (64 bit). </dd></dl> + +</div> +</div> +<a id="a387aa304770b05594c4acca128a60a75" name="a387aa304770b05594c4acca128a60a75"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a387aa304770b05594c4acca128a60a75">&#9670;&#160;</a></span>neorv32_cpu_get_instret()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_cpu_get_instret </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get retired instructions counter from instret[h].</p> +<dl class="section return"><dt>Returns</dt><dd>Current instructions counter (64 bit). </dd></dl> + +</div> +</div> +<a id="aca49efb45d3808ad76cf65ba291f546d" name="aca49efb45d3808ad76cf65ba291f546d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aca49efb45d3808ad76cf65ba291f546d">&#9670;&#160;</a></span>neorv32_cpu_goto_user_mode()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_goto_user_mode </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Switch from privilege mode MACHINE to privilege mode USER. </p> + +</div> +</div> +<a id="a70f49b80322aa457f29f7671f94a183d" name="a70f49b80322aa457f29f7671f94a183d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a70f49b80322aa457f29f7671f94a183d">&#9670;&#160;</a></span>neorv32_cpu_hpm_get_num_counters()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_hpm_get_num_counters </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Hardware performance monitors (HPM): Get number of available HPM counters.</p> +<dl class="section return"><dt>Returns</dt><dd>Returns number of available HPM counters. </dd></dl> + +</div> +</div> +<a id="adb3ae542bbb0ddf9f562a4e42bc24d10" name="adb3ae542bbb0ddf9f562a4e42bc24d10"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adb3ae542bbb0ddf9f562a4e42bc24d10">&#9670;&#160;</a></span>neorv32_cpu_hpm_get_size()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_hpm_get_size </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Hardware performance monitors (HPM): Get total counter width</p> +<dl class="section warning"><dt>Warning</dt><dd>This function overrides the mhpmcounter3[h] CSRs.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Size of HPM counters (1-64, 0 if not implemented at all). </dd></dl> + +</div> +</div> +<a id="aa458a700619b2f7666cfcffe02ec2e2c" name="aa458a700619b2f7666cfcffe02ec2e2c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa458a700619b2f7666cfcffe02ec2e2c">&#9670;&#160;</a></span>neorv32_cpu_pmp_configure_region()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_cpu_pmp_configure_region </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>index</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>config</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Physical memory protection (PMP): Configure region.</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the PMP CPU extension.</dd></dl> +<dl class="section warning"><dt>Warning</dt><dd>This function expects a WORD address!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">index</td><td>Region number (index, 0..PMP_NUM_REGIONS-1). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Region address (word address!). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>Region configuration byte (see <a class="el" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a>). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, !=0 on failure. </dd></dl> + +</div> +</div> +<a id="ad4f8160f4821b6691e9682ef60c7cd7b" name="ad4f8160f4821b6691e9682ef60c7cd7b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4f8160f4821b6691e9682ef60c7cd7b">&#9670;&#160;</a></span>neorv32_cpu_pmp_get_granularity()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_pmp_get_granularity </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Physical memory protection (PMP): Get minimal region size (granularity).</p> +<dl class="section warning"><dt>Warning</dt><dd>This function overrides PMPCFG0[0] and PMPADDR0 CSRs! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function requires the PMP CPU extension.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Returns minimal region size in bytes. Returns zero on error. </dd></dl> + +</div> +</div> +<a id="a27dd614bc270dfa30ed73323ebda2d2d" name="a27dd614bc270dfa30ed73323ebda2d2d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a27dd614bc270dfa30ed73323ebda2d2d">&#9670;&#160;</a></span>neorv32_cpu_pmp_get_num_regions()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_pmp_get_num_regions </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Physical memory protection (PMP): Get number of available regions.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function overrides all available PMPCFG* CSRs! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function requires the PMP CPU extension.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Returns number of available PMP regions. </dd></dl> + +</div> +</div> +<a id="a232d0290c459dc790d989fcdc4d121bf" name="a232d0290c459dc790d989fcdc4d121bf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a232d0290c459dc790d989fcdc4d121bf">&#9670;&#160;</a></span>neorv32_cpu_set_mcycle()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_set_mcycle </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>value</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set machine cycle counter mcycle[h].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>New value for mcycle[h] CSR (64-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a5c3cf52498abb3cf3c14a724b287ecf0" name="a5c3cf52498abb3cf3c14a724b287ecf0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5c3cf52498abb3cf3c14a724b287ecf0">&#9670;&#160;</a></span>neorv32_cpu_set_minstret()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_set_minstret </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>value</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set machine retired instructions counter minstret[h].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>New value for mcycle[h] CSR (64-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 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href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_cpu.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>CPU Core Functions HW driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__cpu_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a173bb06b4ae9c8964469068dafcb7b0e" id="r_a173bb06b4ae9c8964469068dafcb7b0e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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colspan="2">&#160;</td></tr> +<tr class="memitem:a232d0290c459dc790d989fcdc4d121bf" id="r_a232d0290c459dc790d989fcdc4d121bf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a232d0290c459dc790d989fcdc4d121bf">neorv32_cpu_set_mcycle</a> (uint64_t value)</td></tr> +<tr class="separator:a232d0290c459dc790d989fcdc4d121bf"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a387aa304770b05594c4acca128a60a75" id="r_a387aa304770b05594c4acca128a60a75"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a387aa304770b05594c4acca128a60a75">neorv32_cpu_get_instret</a> (void)</td></tr> +<tr class="separator:a387aa304770b05594c4acca128a60a75"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5c3cf52498abb3cf3c14a724b287ecf0" id="r_a5c3cf52498abb3cf3c14a724b287ecf0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5c3cf52498abb3cf3c14a724b287ecf0">neorv32_cpu_set_minstret</a> (uint64_t value)</td></tr> +<tr class="separator:a5c3cf52498abb3cf3c14a724b287ecf0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa9027535b13d9f9325e734997fc4a137" id="r_aa9027535b13d9f9325e734997fc4a137"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa9027535b13d9f9325e734997fc4a137">neorv32_cpu_delay_ms</a> (uint32_t time_ms)</td></tr> +<tr class="separator:aa9027535b13d9f9325e734997fc4a137"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8346fb926f84f3d7bccbb4741105505f" id="r_a8346fb926f84f3d7bccbb4741105505f"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8346fb926f84f3d7bccbb4741105505f">neorv32_cpu_get_clk_from_prsc</a> (int prsc)</td></tr> +<tr class="separator:a8346fb926f84f3d7bccbb4741105505f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a27dd614bc270dfa30ed73323ebda2d2d" id="r_a27dd614bc270dfa30ed73323ebda2d2d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a27dd614bc270dfa30ed73323ebda2d2d">neorv32_cpu_pmp_get_num_regions</a> (void)</td></tr> +<tr class="separator:a27dd614bc270dfa30ed73323ebda2d2d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad4f8160f4821b6691e9682ef60c7cd7b" id="r_ad4f8160f4821b6691e9682ef60c7cd7b"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4f8160f4821b6691e9682ef60c7cd7b">neorv32_cpu_pmp_get_granularity</a> (void)</td></tr> +<tr class="separator:ad4f8160f4821b6691e9682ef60c7cd7b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa458a700619b2f7666cfcffe02ec2e2c" id="r_aa458a700619b2f7666cfcffe02ec2e2c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa458a700619b2f7666cfcffe02ec2e2c">neorv32_cpu_pmp_configure_region</a> (int index, uint32_t addr, uint8_t config)</td></tr> +<tr class="separator:aa458a700619b2f7666cfcffe02ec2e2c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a70f49b80322aa457f29f7671f94a183d" id="r_a70f49b80322aa457f29f7671f94a183d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a70f49b80322aa457f29f7671f94a183d">neorv32_cpu_hpm_get_num_counters</a> (void)</td></tr> +<tr class="separator:a70f49b80322aa457f29f7671f94a183d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adb3ae542bbb0ddf9f562a4e42bc24d10" id="r_adb3ae542bbb0ddf9f562a4e42bc24d10"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adb3ae542bbb0ddf9f562a4e42bc24d10">neorv32_cpu_hpm_get_size</a> (void)</td></tr> +<tr class="separator:adb3ae542bbb0ddf9f562a4e42bc24d10"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aca49efb45d3808ad76cf65ba291f546d" id="r_aca49efb45d3808ad76cf65ba291f546d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aca49efb45d3808ad76cf65ba291f546d">neorv32_cpu_goto_user_mode</a> (void)</td></tr> +<tr class="separator:aca49efb45d3808ad76cf65ba291f546d"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>CPU Core Functions HW driver header file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="ab8f533ddbc3a3af5e3bca2287ac10122" name="ab8f533ddbc3a3af5e3bca2287ac10122"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab8f533ddbc3a3af5e3bca2287ac10122">&#9670;&#160;</a></span>neorv32_cpu_csr_clr()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_csr_clr </td> + <td>(</td> + <td class="paramtype">const int</td> <td class="paramname"><span class="paramname"><em>csr_id</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>mask</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Clear bit(s) in CPU control and status register (CSR).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">csr_id</td><td>ID of CSR to write. See <a class="el" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49">NEORV32_CSR_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>Bit mask (high-active) to clear bits (uint32_t). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aab7a9f9cf608599f2b124dd499cb8418" name="aab7a9f9cf608599f2b124dd499cb8418"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aab7a9f9cf608599f2b124dd499cb8418">&#9670;&#160;</a></span>neorv32_cpu_csr_read()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_csr_read </td> + <td>(</td> + <td class="paramtype">const int</td> <td class="paramname"><span class="paramname"><em>csr_id</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Read data from CPU control and status register (CSR).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">csr_id</td><td>ID of CSR to read. See <a class="el" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49">NEORV32_CSR_enum</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Read data (uint32_t). </dd></dl> + +</div> +</div> +<a id="a25a09de97229aac839ef6f74da604acf" name="a25a09de97229aac839ef6f74da604acf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a25a09de97229aac839ef6f74da604acf">&#9670;&#160;</a></span>neorv32_cpu_csr_set()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_csr_set </td> + <td>(</td> + <td class="paramtype">const int</td> <td class="paramname"><span class="paramname"><em>csr_id</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>mask</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Set bit(s) in CPU control and status register (CSR).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">csr_id</td><td>ID of CSR to write. See <a class="el" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49">NEORV32_CSR_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>Bit mask (high-active) to set bits (uint32_t). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="afb5ef6e0b1a3e26570edfd8379490455" name="afb5ef6e0b1a3e26570edfd8379490455"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afb5ef6e0b1a3e26570edfd8379490455">&#9670;&#160;</a></span>neorv32_cpu_csr_write()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_csr_write </td> + <td>(</td> + <td class="paramtype">const int</td> <td class="paramname"><span class="paramname"><em>csr_id</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>data</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Write data to CPU control and status register (CSR).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">csr_id</td><td>ID of CSR to write. See <a class="el" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49">NEORV32_CSR_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>Data to write (uint32_t). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aa9027535b13d9f9325e734997fc4a137" name="aa9027535b13d9f9325e734997fc4a137"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa9027535b13d9f9325e734997fc4a137">&#9670;&#160;</a></span>neorv32_cpu_delay_ms()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_delay_ms </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>time_ms</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Delay function using busy wait.</p> +<dl class="section note"><dt>Note</dt><dd>This function uses the cycle CPU counter if available. Otherwise the MTIME system timer is used if available. A simple loop is used as alternative fall-back (imprecise!).</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">time_ms</td><td>Time in ms to wait (unsigned 32-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a8346fb926f84f3d7bccbb4741105505f" name="a8346fb926f84f3d7bccbb4741105505f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8346fb926f84f3d7bccbb4741105505f">&#9670;&#160;</a></span>neorv32_cpu_get_clk_from_prsc()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_get_clk_from_prsc </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get actual clocking frequency from prescaler select <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a></p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Prescaler select <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. return Actual <em>raw</em> clock frequency in Hz. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac3fd7dc7cd1e0a08225c41820af27f92" name="ac3fd7dc7cd1e0a08225c41820af27f92"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac3fd7dc7cd1e0a08225c41820af27f92">&#9670;&#160;</a></span>neorv32_cpu_get_cycle()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_cpu_get_cycle </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Unavailable extensions warnings. Get cycle counter from cycle[h].</p> +<dl class="section return"><dt>Returns</dt><dd>Current cycle counter (64 bit). </dd></dl> + +</div> +</div> +<a id="a387aa304770b05594c4acca128a60a75" name="a387aa304770b05594c4acca128a60a75"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a387aa304770b05594c4acca128a60a75">&#9670;&#160;</a></span>neorv32_cpu_get_instret()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_cpu_get_instret </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get retired instructions counter from instret[h].</p> +<dl class="section return"><dt>Returns</dt><dd>Current instructions counter (64 bit). </dd></dl> + +</div> +</div> +<a id="aca49efb45d3808ad76cf65ba291f546d" name="aca49efb45d3808ad76cf65ba291f546d"></a> +<h2 class="memtitle"><span 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class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Hardware performance monitors (HPM): Get number of available HPM counters.</p> +<dl class="section return"><dt>Returns</dt><dd>Returns number of available HPM counters. </dd></dl> + +</div> +</div> +<a id="adb3ae542bbb0ddf9f562a4e42bc24d10" name="adb3ae542bbb0ddf9f562a4e42bc24d10"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adb3ae542bbb0ddf9f562a4e42bc24d10">&#9670;&#160;</a></span>neorv32_cpu_hpm_get_size()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_hpm_get_size </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Hardware performance monitors (HPM): Get total counter width</p> +<dl class="section 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signed byte from address space.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Read data byte (8-bit). </dd></dl> + +</div> +</div> +<a id="ae9c8b6c681536ddea3aff0e63f30ef70" name="ae9c8b6c681536ddea3aff0e63f30ef70"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae9c8b6c681536ddea3aff0e63f30ef70">&#9670;&#160;</a></span>neorv32_cpu_load_signed_half()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">int16_t neorv32_cpu_load_signed_half </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Load signed half-word from address space.</p> +<dl class="section note"><dt>Note</dt><dd>An unaligned access address will raise an alignment exception.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Read data half-word (16-bit). </dd></dl> + +</div> +</div> +<a id="ac54ec9b59e17c7cd9b9907abee82ce95" name="ac54ec9b59e17c7cd9b9907abee82ce95"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac54ec9b59e17c7cd9b9907abee82ce95">&#9670;&#160;</a></span>neorv32_cpu_load_unsigned_byte()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_cpu_load_unsigned_byte </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Load unsigned byte from address space.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Read data byte (8-bit). </dd></dl> + +</div> +</div> +<a id="a32544cd652debb4affb308806a115d5b" name="a32544cd652debb4affb308806a115d5b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a32544cd652debb4affb308806a115d5b">&#9670;&#160;</a></span>neorv32_cpu_load_unsigned_half()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint16_t neorv32_cpu_load_unsigned_half </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Load unsigned half-word from address space.</p> +<dl class="section note"><dt>Note</dt><dd>An unaligned access address will raise an alignment exception.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Read data half-word (16-bit). </dd></dl> + +</div> +</div> +<a id="a3b6cf445e2136486564ef3d3473c91dd" name="a3b6cf445e2136486564ef3d3473c91dd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3b6cf445e2136486564ef3d3473c91dd">&#9670;&#160;</a></span>neorv32_cpu_load_unsigned_word()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_load_unsigned_word </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Load unsigned word from address space.</p> +<dl class="section note"><dt>Note</dt><dd>An unaligned access address will raise an alignment exception.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Read data word (32-bit). </dd></dl> + +</div> +</div> +<a id="aa458a700619b2f7666cfcffe02ec2e2c" name="aa458a700619b2f7666cfcffe02ec2e2c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa458a700619b2f7666cfcffe02ec2e2c">&#9670;&#160;</a></span>neorv32_cpu_pmp_configure_region()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_cpu_pmp_configure_region </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>index</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>config</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Physical memory protection (PMP): Configure region.</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the PMP CPU extension.</dd></dl> +<dl class="section warning"><dt>Warning</dt><dd>This function expects a WORD address!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">index</td><td>Region number (index, 0..PMP_NUM_REGIONS-1). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Region address (word address!). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>Region configuration byte (see <a class="el" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a>). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, !=0 on failure. </dd></dl> + +</div> +</div> +<a id="ad4f8160f4821b6691e9682ef60c7cd7b" name="ad4f8160f4821b6691e9682ef60c7cd7b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4f8160f4821b6691e9682ef60c7cd7b">&#9670;&#160;</a></span>neorv32_cpu_pmp_get_granularity()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_pmp_get_granularity </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Physical memory protection (PMP): Get minimal region size (granularity).</p> +<dl class="section warning"><dt>Warning</dt><dd>This function overrides PMPCFG0[0] and PMPADDR0 CSRs! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function requires the PMP CPU extension.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Returns minimal region size in bytes. Returns zero on error. </dd></dl> + +</div> +</div> +<a id="a27dd614bc270dfa30ed73323ebda2d2d" name="a27dd614bc270dfa30ed73323ebda2d2d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a27dd614bc270dfa30ed73323ebda2d2d">&#9670;&#160;</a></span>neorv32_cpu_pmp_get_num_regions()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_pmp_get_num_regions </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Physical memory protection (PMP): Get number of available regions.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function overrides all available PMPCFG* CSRs! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function requires the PMP CPU extension.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Returns number of available PMP regions. </dd></dl> + +</div> +</div> +<a id="a232d0290c459dc790d989fcdc4d121bf" name="a232d0290c459dc790d989fcdc4d121bf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a232d0290c459dc790d989fcdc4d121bf">&#9670;&#160;</a></span>neorv32_cpu_set_mcycle()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_set_mcycle </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>value</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set machine cycle counter mcycle[h].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>New value for mcycle[h] CSR (64-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a5c3cf52498abb3cf3c14a724b287ecf0" name="a5c3cf52498abb3cf3c14a724b287ecf0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5c3cf52498abb3cf3c14a724b287ecf0">&#9670;&#160;</a></span>neorv32_cpu_set_minstret()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_set_minstret </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>value</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set machine retired instructions counter minstret[h].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>New value for mcycle[h] CSR (64-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a769ca4556213619f6fea4ff6bfb979dd" name="a769ca4556213619f6fea4ff6bfb979dd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a769ca4556213619f6fea4ff6bfb979dd">&#9670;&#160;</a></span>neorv32_cpu_sleep()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_sleep </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Put CPU into sleep / power-down mode.</p> +<dl class="section note"><dt>Note</dt><dd>The WFI (wait for interrupt) instruction will make the CPU halt until any enabled interrupt source becomes pending. </dd></dl> + +</div> +</div> +<a id="aeec8ad2a82885c40a307346f9003483e" name="aeec8ad2a82885c40a307346f9003483e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aeec8ad2a82885c40a307346f9003483e">&#9670;&#160;</a></span>neorv32_cpu_store_unsigned_byte()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_store_unsigned_byte </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Store unsigned byte to address space.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data byte (8-bit) to store. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a31f30f6d6542758cd3073a9939b07653" name="a31f30f6d6542758cd3073a9939b07653"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a31f30f6d6542758cd3073a9939b07653">&#9670;&#160;</a></span>neorv32_cpu_store_unsigned_half()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_store_unsigned_half </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint16_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Store unsigned half-word to address space.</p> +<dl class="section note"><dt>Note</dt><dd>An unaligned access address will raise an alignment exception.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data half-word (16-bit) to store. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a173bb06b4ae9c8964469068dafcb7b0e" name="a173bb06b4ae9c8964469068dafcb7b0e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a173bb06b4ae9c8964469068dafcb7b0e">&#9670;&#160;</a></span>neorv32_cpu_store_unsigned_word()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_cpu_store_unsigned_word </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Store unsigned word to address space.</p> +<dl class="section note"><dt>Note</dt><dd>An unaligned access address will raise an alignment exception.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word (32-bit) to store. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated 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href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_cpu.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__cpu_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_cpu_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_cpu_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span>uint64_t <a class="code hl_function" href="neorv32__cpu_8h.html#ac3fd7dc7cd1e0a08225c41820af27f92">neorv32_cpu_get_cycle</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__cpu_8h.html#a232d0290c459dc790d989fcdc4d121bf">neorv32_cpu_set_mcycle</a>(uint64_t value);</div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span>uint64_t <a class="code hl_function" href="neorv32__cpu_8h.html#a387aa304770b05594c4acca128a60a75">neorv32_cpu_get_instret</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__cpu_8h.html#a5c3cf52498abb3cf3c14a724b287ecf0">neorv32_cpu_set_minstret</a>(uint64_t value);</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__cpu_8h.html#aa9027535b13d9f9325e734997fc4a137">neorv32_cpu_delay_ms</a>(uint32_t time_ms);</div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span>uint32_t <a class="code hl_function" href="neorv32__cpu_8h.html#a8346fb926f84f3d7bccbb4741105505f">neorv32_cpu_get_clk_from_prsc</a>(<span class="keywordtype">int</span> prsc);</div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>uint32_t <a class="code hl_function" href="neorv32__cpu_8h.html#a27dd614bc270dfa30ed73323ebda2d2d">neorv32_cpu_pmp_get_num_regions</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span>uint32_t <a class="code hl_function" href="neorv32__cpu_8h.html#ad4f8160f4821b6691e9682ef60c7cd7b">neorv32_cpu_pmp_get_granularity</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__cpu_8h.html#aa458a700619b2f7666cfcffe02ec2e2c">neorv32_cpu_pmp_configure_region</a>(<span class="keywordtype">int</span> index, uint32_t addr, uint8_t config);</div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span>uint32_t <a class="code hl_function" href="neorv32__cpu_8h.html#a70f49b80322aa457f29f7671f94a183d">neorv32_cpu_hpm_get_num_counters</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span>uint32_t <a class="code hl_function" href="neorv32__cpu_8h.html#adb3ae542bbb0ddf9f562a4e42bc24d10">neorv32_cpu_hpm_get_size</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__cpu_8h.html#aca49efb45d3808ad76cf65ba291f546d">neorv32_cpu_goto_user_mode</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00049" data-start="{" data-end="}"> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#a173bb06b4ae9c8964469068dafcb7b0e"> 49</a></span><span class="keyword">inline</span> <span class="keywordtype">void</span> __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#a173bb06b4ae9c8964469068dafcb7b0e">neorv32_cpu_store_unsigned_word</a>(uint32_t addr, uint32_t wdata) {</div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span> </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span> uint32_t reg_addr = addr;</div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span> uint32_t reg_data = wdata;</div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;sw %[da], 0(%[ad])&quot;</span> : : [da] <span class="stringliteral">&quot;r&quot;</span> (reg_data), [ad] <span class="stringliteral">&quot;r&quot;</span> (reg_addr));</div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span>}</div> +</div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span> </div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00065" data-start="{" data-end="}"> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#a31f30f6d6542758cd3073a9939b07653"> 65</a></span><span class="keyword">inline</span> <span class="keywordtype">void</span> __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#a31f30f6d6542758cd3073a9939b07653">neorv32_cpu_store_unsigned_half</a>(uint32_t addr, uint16_t wdata) {</div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span> </div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span> uint32_t reg_addr = addr;</div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span> uint32_t reg_data = (uint32_t)wdata;</div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;sh %[da], 0(%[ad])&quot;</span> : : [da] <span class="stringliteral">&quot;r&quot;</span> (reg_data), [ad] <span class="stringliteral">&quot;r&quot;</span> (reg_addr));</div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span>}</div> +</div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span> </div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span> </div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00079" data-start="{" data-end="}"> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#aeec8ad2a82885c40a307346f9003483e"> 79</a></span><span class="keyword">inline</span> <span class="keywordtype">void</span> __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#aeec8ad2a82885c40a307346f9003483e">neorv32_cpu_store_unsigned_byte</a>(uint32_t addr, uint8_t wdata) {</div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span> </div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span> uint32_t reg_addr = addr;</div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span> uint32_t reg_data = (uint32_t)wdata;</div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;sb %[da], 0(%[ad])&quot;</span> : : [da] <span class="stringliteral">&quot;r&quot;</span> (reg_data), [ad] <span class="stringliteral">&quot;r&quot;</span> (reg_addr));</div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span>}</div> +</div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span> </div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span> </div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00095" data-start="{" data-end="}"> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#a3b6cf445e2136486564ef3d3473c91dd"> 95</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#a3b6cf445e2136486564ef3d3473c91dd">neorv32_cpu_load_unsigned_word</a>(uint32_t addr) {</div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span> </div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> uint32_t reg_addr = addr;</div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> uint32_t reg_data;</div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;lw %[da], 0(%[ad])&quot;</span> : [da] <span class="stringliteral">&quot;=r&quot;</span> (reg_data) : [ad] <span class="stringliteral">&quot;r&quot;</span> (reg_addr));</div> +<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span> <span class="keywordflow">return</span> reg_data;</div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span>}</div> +</div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span> </div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span> </div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00112" data-start="{" data-end="}"> +<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#a32544cd652debb4affb308806a115d5b"> 112</a></span><span class="keyword">inline</span> uint16_t __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#a32544cd652debb4affb308806a115d5b">neorv32_cpu_load_unsigned_half</a>(uint32_t addr) {</div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span> </div> +<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span> uint32_t reg_addr = addr;</div> +<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span> uint16_t reg_data;</div> +<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;lhu %[da], 0(%[ad])&quot;</span> : [da] <span class="stringliteral">&quot;=r&quot;</span> (reg_data) : [ad] <span class="stringliteral">&quot;r&quot;</span> (reg_addr));</div> +<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span> <span class="keywordflow">return</span> reg_data;</div> +<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span>}</div> +</div> +<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"> 119</span> </div> +<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"> 120</span> </div> +<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00129" data-start="{" data-end="}"> +<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#ae9c8b6c681536ddea3aff0e63f30ef70"> 129</a></span><span class="keyword">inline</span> int16_t __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#ae9c8b6c681536ddea3aff0e63f30ef70">neorv32_cpu_load_signed_half</a>(uint32_t addr) {</div> +<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span> </div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span> uint32_t reg_addr = addr;</div> +<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span> int16_t reg_data;</div> +<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;lh %[da], 0(%[ad])&quot;</span> : [da] <span class="stringliteral">&quot;=r&quot;</span> (reg_data) : [ad] <span class="stringliteral">&quot;r&quot;</span> (reg_addr));</div> +<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"> 134</span> <span class="keywordflow">return</span> reg_data;</div> +<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"> 135</span>}</div> +</div> +<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"> 136</span> </div> +<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"> 137</span> </div> +<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"> 138</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00144" data-start="{" data-end="}"> +<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#ac54ec9b59e17c7cd9b9907abee82ce95"> 144</a></span><span class="keyword">inline</span> uint8_t __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#ac54ec9b59e17c7cd9b9907abee82ce95">neorv32_cpu_load_unsigned_byte</a>(uint32_t addr) {</div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span> </div> +<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span> uint32_t reg_addr = addr;</div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span> uint8_t reg_data;</div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;lbu %[da], 0(%[ad])&quot;</span> : [da] <span class="stringliteral">&quot;=r&quot;</span> (reg_data) : [ad] <span class="stringliteral">&quot;r&quot;</span> (reg_addr));</div> +<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span> <span class="keywordflow">return</span> reg_data;</div> +<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span>}</div> +</div> +<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span> </div> +<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span> </div> +<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00159" data-start="{" data-end="}"> +<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#a31f903596ab1bcddea79fdf608eaa666"> 159</a></span><span class="keyword">inline</span> int8_t __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#a31f903596ab1bcddea79fdf608eaa666">neorv32_cpu_load_signed_byte</a>(uint32_t addr) {</div> +<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span> </div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span> uint32_t reg_addr = addr;</div> +<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span> int8_t reg_data;</div> +<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"> 163</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;lb %[da], 0(%[ad])&quot;</span> : [da] <span class="stringliteral">&quot;=r&quot;</span> (reg_data) : [ad] <span class="stringliteral">&quot;r&quot;</span> (reg_addr));</div> +<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span> <span class="keywordflow">return</span> reg_data;</div> +<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span>}</div> +</div> +<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"> 166</span> </div> +<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span> </div> +<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00174" data-start="{" data-end="}"> +<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#aab7a9f9cf608599f2b124dd499cb8418"> 174</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#aab7a9f9cf608599f2b124dd499cb8418">neorv32_cpu_csr_read</a>(<span class="keyword">const</span> <span class="keywordtype">int</span> csr_id) {</div> +<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span> </div> +<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span> uint32_t csr_data;</div> +<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;csrr %[result], %[input_i]&quot;</span> : [result] <span class="stringliteral">&quot;=r&quot;</span> (csr_data) : [input_i] <span class="stringliteral">&quot;i&quot;</span> (csr_id));</div> +<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span> <span class="keywordflow">return</span> csr_data;</div> +<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span>}</div> +</div> +<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span> </div> +<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span> </div> +<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"> 182</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00188" data-start="{" data-end="}"> +<div class="line"><a id="l00188" name="l00188"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#afb5ef6e0b1a3e26570edfd8379490455"> 188</a></span><span class="keyword">inline</span> <span class="keywordtype">void</span> __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#afb5ef6e0b1a3e26570edfd8379490455">neorv32_cpu_csr_write</a>(<span class="keyword">const</span> <span class="keywordtype">int</span> csr_id, uint32_t data) {</div> +<div class="line"><a id="l00189" name="l00189"></a><span class="lineno"> 189</span> </div> +<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"> 190</span> uint32_t csr_data = data;</div> +<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;csrw %[input_i], %[input_j]&quot;</span> : : [input_i] <span class="stringliteral">&quot;i&quot;</span> (csr_id), [input_j] <span class="stringliteral">&quot;r&quot;</span> (csr_data));</div> +<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"> 192</span>}</div> +</div> +<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span> </div> +<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span> </div> +<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00201" data-start="{" data-end="}"> +<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#a25a09de97229aac839ef6f74da604acf"> 201</a></span><span class="keyword">inline</span> <span class="keywordtype">void</span> __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#a25a09de97229aac839ef6f74da604acf">neorv32_cpu_csr_set</a>(<span class="keyword">const</span> <span class="keywordtype">int</span> csr_id, uint32_t mask) {</div> +<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span> </div> +<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span> uint32_t csr_data = mask;</div> +<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"> 204</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;csrs %[input_i], %[input_j]&quot;</span> : : [input_i] <span class="stringliteral">&quot;i&quot;</span> (csr_id), [input_j] <span class="stringliteral">&quot;r&quot;</span> (csr_data));</div> +<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"> 205</span>}</div> +</div> +<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"> 206</span> </div> +<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"> 207</span> </div> +<div class="line"><a id="l00208" name="l00208"></a><span class="lineno"> 208</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00214" data-start="{" data-end="}"> +<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#ab8f533ddbc3a3af5e3bca2287ac10122"> 214</a></span><span class="keyword">inline</span> <span class="keywordtype">void</span> __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#ab8f533ddbc3a3af5e3bca2287ac10122">neorv32_cpu_csr_clr</a>(<span class="keyword">const</span> <span class="keywordtype">int</span> csr_id, uint32_t mask) {</div> +<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"> 215</span> </div> +<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"> 216</span> uint32_t csr_data = mask;</div> +<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"> 217</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;csrc %[input_i], %[input_j]&quot;</span> : : [input_i] <span class="stringliteral">&quot;i&quot;</span> (csr_id), [input_j] <span class="stringliteral">&quot;r&quot;</span> (csr_data));</div> +<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span>}</div> +</div> +<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"> 219</span> </div> +<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"> 220</span> </div> +<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"> 221</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00227" data-start="{" data-end="}"> +<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"><a class="line" href="neorv32__cpu_8h.html#a769ca4556213619f6fea4ff6bfb979dd"> 227</a></span><span class="keyword">inline</span> <span class="keywordtype">void</span> __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu_8h.html#a769ca4556213619f6fea4ff6bfb979dd">neorv32_cpu_sleep</a>(<span class="keywordtype">void</span>) {</div> +<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span> </div> +<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;wfi&quot;</span>);</div> +<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span>}</div> +</div> +<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span> </div> +<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span> </div> +<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_cpu_h</span></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a173bb06b4ae9c8964469068dafcb7b0e"><div class="ttname"><a href="neorv32__cpu_8h.html#a173bb06b4ae9c8964469068dafcb7b0e">neorv32_cpu_store_unsigned_word</a></div><div class="ttdeci">void neorv32_cpu_store_unsigned_word(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:49</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a232d0290c459dc790d989fcdc4d121bf"><div class="ttname"><a href="neorv32__cpu_8h.html#a232d0290c459dc790d989fcdc4d121bf">neorv32_cpu_set_mcycle</a></div><div class="ttdeci">void neorv32_cpu_set_mcycle(uint64_t value)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:72</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a25a09de97229aac839ef6f74da604acf"><div class="ttname"><a href="neorv32__cpu_8h.html#a25a09de97229aac839ef6f74da604acf">neorv32_cpu_csr_set</a></div><div class="ttdeci">void neorv32_cpu_csr_set(const int csr_id, uint32_t mask)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:201</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a27dd614bc270dfa30ed73323ebda2d2d"><div class="ttname"><a href="neorv32__cpu_8h.html#a27dd614bc270dfa30ed73323ebda2d2d">neorv32_cpu_pmp_get_num_regions</a></div><div class="ttdeci">uint32_t neorv32_cpu_pmp_get_num_regions(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:221</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a31f30f6d6542758cd3073a9939b07653"><div class="ttname"><a href="neorv32__cpu_8h.html#a31f30f6d6542758cd3073a9939b07653">neorv32_cpu_store_unsigned_half</a></div><div class="ttdeci">void neorv32_cpu_store_unsigned_half(uint32_t addr, uint16_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:65</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a31f903596ab1bcddea79fdf608eaa666"><div class="ttname"><a href="neorv32__cpu_8h.html#a31f903596ab1bcddea79fdf608eaa666">neorv32_cpu_load_signed_byte</a></div><div class="ttdeci">int8_t neorv32_cpu_load_signed_byte(uint32_t addr)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:159</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a32544cd652debb4affb308806a115d5b"><div class="ttname"><a href="neorv32__cpu_8h.html#a32544cd652debb4affb308806a115d5b">neorv32_cpu_load_unsigned_half</a></div><div class="ttdeci">uint16_t neorv32_cpu_load_unsigned_half(uint32_t addr)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:112</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a387aa304770b05594c4acca128a60a75"><div class="ttname"><a href="neorv32__cpu_8h.html#a387aa304770b05594c4acca128a60a75">neorv32_cpu_get_instret</a></div><div class="ttdeci">uint64_t neorv32_cpu_get_instret(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:90</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a3b6cf445e2136486564ef3d3473c91dd"><div class="ttname"><a href="neorv32__cpu_8h.html#a3b6cf445e2136486564ef3d3473c91dd">neorv32_cpu_load_unsigned_word</a></div><div class="ttdeci">uint32_t neorv32_cpu_load_unsigned_word(uint32_t addr)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:95</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a5c3cf52498abb3cf3c14a724b287ecf0"><div class="ttname"><a href="neorv32__cpu_8h.html#a5c3cf52498abb3cf3c14a724b287ecf0">neorv32_cpu_set_minstret</a></div><div class="ttdeci">void neorv32_cpu_set_minstret(uint64_t value)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:116</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a70f49b80322aa457f29f7671f94a183d"><div class="ttname"><a href="neorv32__cpu_8h.html#a70f49b80322aa457f29f7671f94a183d">neorv32_cpu_hpm_get_num_counters</a></div><div class="ttdeci">uint32_t neorv32_cpu_hpm_get_num_counters(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:374</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a769ca4556213619f6fea4ff6bfb979dd"><div class="ttname"><a href="neorv32__cpu_8h.html#a769ca4556213619f6fea4ff6bfb979dd">neorv32_cpu_sleep</a></div><div class="ttdeci">void neorv32_cpu_sleep(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:227</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_a8346fb926f84f3d7bccbb4741105505f"><div class="ttname"><a href="neorv32__cpu_8h.html#a8346fb926f84f3d7bccbb4741105505f">neorv32_cpu_get_clk_from_prsc</a></div><div class="ttdeci">uint32_t neorv32_cpu_get_clk_from_prsc(int prsc)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:188</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_aa458a700619b2f7666cfcffe02ec2e2c"><div class="ttname"><a href="neorv32__cpu_8h.html#aa458a700619b2f7666cfcffe02ec2e2c">neorv32_cpu_pmp_configure_region</a></div><div class="ttdeci">int neorv32_cpu_pmp_configure_region(int index, uint32_t addr, uint8_t config)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:308</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_aa9027535b13d9f9325e734997fc4a137"><div class="ttname"><a href="neorv32__cpu_8h.html#aa9027535b13d9f9325e734997fc4a137">neorv32_cpu_delay_ms</a></div><div class="ttdeci">void neorv32_cpu_delay_ms(uint32_t time_ms)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:138</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_aab7a9f9cf608599f2b124dd499cb8418"><div class="ttname"><a href="neorv32__cpu_8h.html#aab7a9f9cf608599f2b124dd499cb8418">neorv32_cpu_csr_read</a></div><div class="ttdeci">uint32_t neorv32_cpu_csr_read(const int csr_id)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:174</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_ab8f533ddbc3a3af5e3bca2287ac10122"><div class="ttname"><a href="neorv32__cpu_8h.html#ab8f533ddbc3a3af5e3bca2287ac10122">neorv32_cpu_csr_clr</a></div><div class="ttdeci">void neorv32_cpu_csr_clr(const int csr_id, uint32_t mask)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:214</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_ac3fd7dc7cd1e0a08225c41820af27f92"><div class="ttname"><a href="neorv32__cpu_8h.html#ac3fd7dc7cd1e0a08225c41820af27f92">neorv32_cpu_get_cycle</a></div><div class="ttdeci">uint64_t neorv32_cpu_get_cycle(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:46</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_ac54ec9b59e17c7cd9b9907abee82ce95"><div class="ttname"><a href="neorv32__cpu_8h.html#ac54ec9b59e17c7cd9b9907abee82ce95">neorv32_cpu_load_unsigned_byte</a></div><div class="ttdeci">uint8_t neorv32_cpu_load_unsigned_byte(uint32_t addr)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:144</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_aca49efb45d3808ad76cf65ba291f546d"><div class="ttname"><a href="neorv32__cpu_8h.html#aca49efb45d3808ad76cf65ba291f546d">neorv32_cpu_goto_user_mode</a></div><div class="ttdeci">void neorv32_cpu_goto_user_mode(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:447</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_ad4f8160f4821b6691e9682ef60c7cd7b"><div class="ttname"><a href="neorv32__cpu_8h.html#ad4f8160f4821b6691e9682ef60c7cd7b">neorv32_cpu_pmp_get_granularity</a></div><div class="ttdeci">uint32_t neorv32_cpu_pmp_get_granularity(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:266</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_adb3ae542bbb0ddf9f562a4e42bc24d10"><div class="ttname"><a href="neorv32__cpu_8h.html#adb3ae542bbb0ddf9f562a4e42bc24d10">neorv32_cpu_hpm_get_size</a></div><div class="ttdeci">uint32_t neorv32_cpu_hpm_get_size(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.c:409</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_ae9c8b6c681536ddea3aff0e63f30ef70"><div class="ttname"><a href="neorv32__cpu_8h.html#ae9c8b6c681536ddea3aff0e63f30ef70">neorv32_cpu_load_signed_half</a></div><div class="ttdeci">int16_t neorv32_cpu_load_signed_half(uint32_t addr)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:129</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_aeec8ad2a82885c40a307346f9003483e"><div class="ttname"><a href="neorv32__cpu_8h.html#aeec8ad2a82885c40a307346f9003483e">neorv32_cpu_store_unsigned_byte</a></div><div class="ttdeci">void neorv32_cpu_store_unsigned_byte(uint32_t addr, uint8_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:79</div></div> +<div class="ttc" id="aneorv32__cpu_8h_html_afb5ef6e0b1a3e26570edfd8379490455"><div class="ttname"><a href="neorv32__cpu_8h.html#afb5ef6e0b1a3e26570edfd8379490455">neorv32_cpu_csr_write</a></div><div class="ttdeci">void neorv32_cpu_csr_write(const int csr_id, uint32_t data)</div><div class="ttdef"><b>Definition</b> neorv32_cpu.h:188</div></div> +</div><!-- fragment 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_cpu_amo.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:aad0d96e61bacc3af13ff471dd44ca8e9" id="r_aad0d96e61bacc3af13ff471dd44ca8e9"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aad0d96e61bacc3af13ff471dd44ca8e9">neorv32_cpu_amoswapw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:aad0d96e61bacc3af13ff471dd44ca8e9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ada27ec89b2530f7b7f14de947cc82bf9" id="r_ada27ec89b2530f7b7f14de947cc82bf9"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ada27ec89b2530f7b7f14de947cc82bf9">neorv32_cpu_amoaddw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:ada27ec89b2530f7b7f14de947cc82bf9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9b4540dadbfd5da907117570d8006e36" id="r_a9b4540dadbfd5da907117570d8006e36"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9b4540dadbfd5da907117570d8006e36">neorv32_cpu_amoandw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a9b4540dadbfd5da907117570d8006e36"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adc80b1f2b3a4e70fee44c0edb08fc402" id="r_adc80b1f2b3a4e70fee44c0edb08fc402"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adc80b1f2b3a4e70fee44c0edb08fc402">neorv32_cpu_amoorw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:adc80b1f2b3a4e70fee44c0edb08fc402"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a65b67f48356fa9b30596485473311377" id="r_a65b67f48356fa9b30596485473311377"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a65b67f48356fa9b30596485473311377">neorv32_cpu_amoxorw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a65b67f48356fa9b30596485473311377"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a62cf36637d7a04079228acecfe8a5cf3" id="r_a62cf36637d7a04079228acecfe8a5cf3"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a62cf36637d7a04079228acecfe8a5cf3">neorv32_cpu_amomaxw</a> (uint32_t addr, int32_t wdata)</td></tr> +<tr class="separator:a62cf36637d7a04079228acecfe8a5cf3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a31a6a3b5a33655f4a7b27d4c85b75f07" id="r_a31a6a3b5a33655f4a7b27d4c85b75f07"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a31a6a3b5a33655f4a7b27d4c85b75f07">neorv32_cpu_amomaxuw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a31a6a3b5a33655f4a7b27d4c85b75f07"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8e383fb8825538b5579d5ce075830697" id="r_a8e383fb8825538b5579d5ce075830697"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8e383fb8825538b5579d5ce075830697">neorv32_cpu_amominw</a> (uint32_t addr, int32_t wdata)</td></tr> +<tr class="separator:a8e383fb8825538b5579d5ce075830697"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1281e18b95cd525073e1123c5d04e9e2" id="r_a1281e18b95cd525073e1123c5d04e9e2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1281e18b95cd525073e1123c5d04e9e2">neorv32_cpu_amominuw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a1281e18b95cd525073e1123c5d04e9e2"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - source file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="ada27ec89b2530f7b7f14de947cc82bf9" name="ada27ec89b2530f7b7f14de947cc82bf9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ada27ec89b2530f7b7f14de947cc82bf9">&#9670;&#160;</a></span>neorv32_cpu_amoaddw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoaddw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic ADD (AMOADD.W). return &lt;= MEM[addr]; MEM[addr] &lt;= MEM[addr] + wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically added to original data at address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +<a id="a9b4540dadbfd5da907117570d8006e36" name="a9b4540dadbfd5da907117570d8006e36"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9b4540dadbfd5da907117570d8006e36">&#9670;&#160;</a></span>neorv32_cpu_amoandw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoandw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic AND (AMOAND.W). return &lt;= MEM[addr]; MEM[addr] &lt;= MEM[addr] and wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically AND-ed with original data at address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +<a id="a31a6a3b5a33655f4a7b27d4c85b75f07" name="a31a6a3b5a33655f4a7b27d4c85b75f07"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a31a6a3b5a33655f4a7b27d4c85b75f07">&#9670;&#160;</a></span>neorv32_cpu_amomaxuw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amomaxuw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic unsigned MAX (AMOMAXU.W). return &lt;= MEM[addr]; MEM[addr] &lt;= maximum_unsigned(MEM[addr], wdata)</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically MAX-ed with original data at address (unsigned 32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (unsigned 32-bit) </dd></dl> + +</div> +</div> +<a id="a62cf36637d7a04079228acecfe8a5cf3" name="a62cf36637d7a04079228acecfe8a5cf3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a62cf36637d7a04079228acecfe8a5cf3">&#9670;&#160;</a></span>neorv32_cpu_amomaxw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t neorv32_cpu_amomaxw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic signed MAX (AMOMAX.W). return &lt;= MEM[addr]; MEM[addr] &lt;= maximum_signed(MEM[addr], wdata)</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically MAX-ed with original data at address (signed 32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (signed 32-bit) </dd></dl> + +</div> +</div> +<a id="a1281e18b95cd525073e1123c5d04e9e2" name="a1281e18b95cd525073e1123c5d04e9e2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1281e18b95cd525073e1123c5d04e9e2">&#9670;&#160;</a></span>neorv32_cpu_amominuw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amominuw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic unsigned MIN (AMOMINU.W). return &lt;= MEM[addr]; MEM[addr] &lt;= minimum_unsigned(MEM[addr], wdata)</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically MIN-ed with original data at address (unsigned 32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (unsigned 32-bit) </dd></dl> + +</div> +</div> +<a id="a8e383fb8825538b5579d5ce075830697" name="a8e383fb8825538b5579d5ce075830697"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8e383fb8825538b5579d5ce075830697">&#9670;&#160;</a></span>neorv32_cpu_amominw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t neorv32_cpu_amominw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic signed MIN (AMOMIN.W). return &lt;= MEM[addr]; MEM[addr] &lt;= minimum_signed(MEM[addr], wdata)</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically MIN-ed with original data at address (signed 32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (signed 32-bit) </dd></dl> + +</div> +</div> +<a id="adc80b1f2b3a4e70fee44c0edb08fc402" name="adc80b1f2b3a4e70fee44c0edb08fc402"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adc80b1f2b3a4e70fee44c0edb08fc402">&#9670;&#160;</a></span>neorv32_cpu_amoorw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoorw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic OR (AMOOR.W). return &lt;= MEM[addr]; MEM[addr] &lt;= MEM[addr] or wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically OR-ed with original data at address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +<a id="aad0d96e61bacc3af13ff471dd44ca8e9" name="aad0d96e61bacc3af13ff471dd44ca8e9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aad0d96e61bacc3af13ff471dd44ca8e9">&#9670;&#160;</a></span>neorv32_cpu_amoswapw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoswapw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic SWAP (AMOSWAP.W). return &lt;= MEM[addr]; MEM[addr] &lt;= wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically stored to address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +<a id="a65b67f48356fa9b30596485473311377" name="a65b67f48356fa9b30596485473311377"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a65b67f48356fa9b30596485473311377">&#9670;&#160;</a></span>neorv32_cpu_amoxorw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoxorw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic XOR (AMOXOR.W). return &lt;= MEM[addr]; MEM[addr] &lt;= MEM[addr] xor wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically XOR-ed with original data at address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__cpu__amo_8h.html b/sw/neorv32__cpu__amo_8h.html new file mode 100644 index 000000000..9c82f65eb --- /dev/null +++ b/sw/neorv32__cpu__amo_8h.html @@ -0,0 +1,496 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__cpu__amo_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ad4437bbc61a4e40d7d01dfe9459f6639" id="r_ad4437bbc61a4e40d7d01dfe9459f6639"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4437bbc61a4e40d7d01dfe9459f6639">neorv32_cpu_amolr</a> (uint32_t addr)</td></tr> +<tr class="separator:ad4437bbc61a4e40d7d01dfe9459f6639"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5e73eaa273c41a06972e862976fda53c" id="r_a5e73eaa273c41a06972e862976fda53c"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5e73eaa273c41a06972e862976fda53c">neorv32_cpu_amosc</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a5e73eaa273c41a06972e862976fda53c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:aad0d96e61bacc3af13ff471dd44ca8e9" id="r_aad0d96e61bacc3af13ff471dd44ca8e9"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aad0d96e61bacc3af13ff471dd44ca8e9">neorv32_cpu_amoswapw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:aad0d96e61bacc3af13ff471dd44ca8e9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ada27ec89b2530f7b7f14de947cc82bf9" id="r_ada27ec89b2530f7b7f14de947cc82bf9"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ada27ec89b2530f7b7f14de947cc82bf9">neorv32_cpu_amoaddw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:ada27ec89b2530f7b7f14de947cc82bf9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9b4540dadbfd5da907117570d8006e36" id="r_a9b4540dadbfd5da907117570d8006e36"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9b4540dadbfd5da907117570d8006e36">neorv32_cpu_amoandw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a9b4540dadbfd5da907117570d8006e36"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adc80b1f2b3a4e70fee44c0edb08fc402" id="r_adc80b1f2b3a4e70fee44c0edb08fc402"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adc80b1f2b3a4e70fee44c0edb08fc402">neorv32_cpu_amoorw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:adc80b1f2b3a4e70fee44c0edb08fc402"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a65b67f48356fa9b30596485473311377" id="r_a65b67f48356fa9b30596485473311377"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a65b67f48356fa9b30596485473311377">neorv32_cpu_amoxorw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a65b67f48356fa9b30596485473311377"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a62cf36637d7a04079228acecfe8a5cf3" id="r_a62cf36637d7a04079228acecfe8a5cf3"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a62cf36637d7a04079228acecfe8a5cf3">neorv32_cpu_amomaxw</a> (uint32_t addr, int32_t wdata)</td></tr> +<tr class="separator:a62cf36637d7a04079228acecfe8a5cf3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a31a6a3b5a33655f4a7b27d4c85b75f07" id="r_a31a6a3b5a33655f4a7b27d4c85b75f07"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a31a6a3b5a33655f4a7b27d4c85b75f07">neorv32_cpu_amomaxuw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a31a6a3b5a33655f4a7b27d4c85b75f07"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8e383fb8825538b5579d5ce075830697" id="r_a8e383fb8825538b5579d5ce075830697"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8e383fb8825538b5579d5ce075830697">neorv32_cpu_amominw</a> (uint32_t addr, int32_t wdata)</td></tr> +<tr class="separator:a8e383fb8825538b5579d5ce075830697"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1281e18b95cd525073e1123c5d04e9e2" id="r_a1281e18b95cd525073e1123c5d04e9e2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1281e18b95cd525073e1123c5d04e9e2">neorv32_cpu_amominuw</a> (uint32_t addr, uint32_t wdata)</td></tr> +<tr class="separator:a1281e18b95cd525073e1123c5d04e9e2"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - header file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="ada27ec89b2530f7b7f14de947cc82bf9" name="ada27ec89b2530f7b7f14de947cc82bf9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ada27ec89b2530f7b7f14de947cc82bf9">&#9670;&#160;</a></span>neorv32_cpu_amoaddw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoaddw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic ADD (AMOADD.W). return &lt;= MEM[addr]; MEM[addr] &lt;= MEM[addr] + wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically added to original data at address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +<a id="a9b4540dadbfd5da907117570d8006e36" name="a9b4540dadbfd5da907117570d8006e36"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9b4540dadbfd5da907117570d8006e36">&#9670;&#160;</a></span>neorv32_cpu_amoandw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoandw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic AND (AMOAND.W). return &lt;= MEM[addr]; MEM[addr] &lt;= MEM[addr] and wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically AND-ed with original data at address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +<a id="ad4437bbc61a4e40d7d01dfe9459f6639" name="ad4437bbc61a4e40d7d01dfe9459f6639"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4437bbc61a4e40d7d01dfe9459f6639">&#9670;&#160;</a></span>neorv32_cpu_amolr()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amolr </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Atomic memory access: load-reservate word.</p> +<dl class="section note"><dt>Note</dt><dd>The address has to be word-aligned - otherwise an alignment exception will be raised. </dd></dl> +<dl class="section warning"><dt>Warning</dt><dd>This function requires the A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Read data word (32-bit). </dd></dl> + +</div> +</div> +<a id="a31a6a3b5a33655f4a7b27d4c85b75f07" name="a31a6a3b5a33655f4a7b27d4c85b75f07"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a31a6a3b5a33655f4a7b27d4c85b75f07">&#9670;&#160;</a></span>neorv32_cpu_amomaxuw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amomaxuw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic unsigned MAX (AMOMAXU.W). return &lt;= MEM[addr]; MEM[addr] &lt;= maximum_unsigned(MEM[addr], wdata)</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically MAX-ed with original data at address (unsigned 32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (unsigned 32-bit) </dd></dl> + +</div> +</div> +<a id="a62cf36637d7a04079228acecfe8a5cf3" name="a62cf36637d7a04079228acecfe8a5cf3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a62cf36637d7a04079228acecfe8a5cf3">&#9670;&#160;</a></span>neorv32_cpu_amomaxw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t neorv32_cpu_amomaxw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic signed MAX (AMOMAX.W). return &lt;= MEM[addr]; MEM[addr] &lt;= maximum_signed(MEM[addr], wdata)</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically MAX-ed with original data at address (signed 32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (signed 32-bit) </dd></dl> + +</div> +</div> +<a id="a1281e18b95cd525073e1123c5d04e9e2" name="a1281e18b95cd525073e1123c5d04e9e2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1281e18b95cd525073e1123c5d04e9e2">&#9670;&#160;</a></span>neorv32_cpu_amominuw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amominuw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic unsigned MIN (AMOMINU.W). return &lt;= MEM[addr]; MEM[addr] &lt;= minimum_unsigned(MEM[addr], wdata)</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically MIN-ed with original data at address (unsigned 32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (unsigned 32-bit) </dd></dl> + +</div> +</div> +<a id="a8e383fb8825538b5579d5ce075830697" name="a8e383fb8825538b5579d5ce075830697"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8e383fb8825538b5579d5ce075830697">&#9670;&#160;</a></span>neorv32_cpu_amominw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t neorv32_cpu_amominw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic signed MIN (AMOMIN.W). return &lt;= MEM[addr]; MEM[addr] &lt;= minimum_signed(MEM[addr], wdata)</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically MIN-ed with original data at address (signed 32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (signed 32-bit) </dd></dl> + +</div> +</div> +<a id="adc80b1f2b3a4e70fee44c0edb08fc402" name="adc80b1f2b3a4e70fee44c0edb08fc402"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adc80b1f2b3a4e70fee44c0edb08fc402">&#9670;&#160;</a></span>neorv32_cpu_amoorw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoorw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic OR (AMOOR.W). return &lt;= MEM[addr]; MEM[addr] &lt;= MEM[addr] or wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically OR-ed with original data at address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +<a id="a5e73eaa273c41a06972e862976fda53c" name="a5e73eaa273c41a06972e862976fda53c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5e73eaa273c41a06972e862976fda53c">&#9670;&#160;</a></span>neorv32_cpu_amosc()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amosc </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Atomic memory access: store-conditional word.</p> +<dl class="section note"><dt>Note</dt><dd>The address has to be word-aligned - otherwise an alignment exception will be raised. </dd></dl> +<dl class="section warning"><dt>Warning</dt><dd>This function requires the A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>Address (32-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to-be-written conditionally (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Status: 0 = ok, 1 = failed (32-bit). </dd></dl> + +</div> +</div> +<a id="aad0d96e61bacc3af13ff471dd44ca8e9" name="aad0d96e61bacc3af13ff471dd44ca8e9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aad0d96e61bacc3af13ff471dd44ca8e9">&#9670;&#160;</a></span>neorv32_cpu_amoswapw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoswapw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic SWAP (AMOSWAP.W). return &lt;= MEM[addr]; MEM[addr] &lt;= wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically stored to address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +<a id="a65b67f48356fa9b30596485473311377" name="a65b67f48356fa9b30596485473311377"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a65b67f48356fa9b30596485473311377">&#9670;&#160;</a></span>neorv32_cpu_amoxorw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cpu_amoxorw </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Atomic XOR (AMOXOR.W). return &lt;= MEM[addr]; MEM[addr] &lt;= MEM[addr] xor wdata</p> +<dl class="section note"><dt>Note</dt><dd>This function requires the CPU A ISA extension.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>32-bit memory address, word-aligned. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">wdata</td><td>Data word to be atomically XOR-ed with original data at address (32-bit). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Pre-operation data loaded from address (32-bit) </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> 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href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_cpu_amo.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__cpu__amo_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_cpu_amo_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_cpu_amo_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00031" data-start="{" data-end="}"> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="neorv32__cpu__amo_8h.html#ad4437bbc61a4e40d7d01dfe9459f6639"> 31</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu__amo_8h.html#ad4437bbc61a4e40d7d01dfe9459f6639">neorv32_cpu_amolr</a>(uint32_t addr) {</div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span><span class="preprocessor">#if defined __riscv_atomic</span></div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> uint32_t amo_addr = addr;</div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> uint32_t amo_rdata;</div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;lr.w %[dst], 0(%[addr])&quot;</span> : [dst] <span class="stringliteral">&quot;=r&quot;</span> (amo_rdata) : [addr] <span class="stringliteral">&quot;r&quot;</span> (amo_addr));</div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> </div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span> <span class="keywordflow">return</span> amo_rdata;</div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span><span class="preprocessor">#else</span></div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span> (void)addr;</div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span> <span class="keywordflow">return</span> 0;</div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span>}</div> +</div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span> </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00058" data-start="{" data-end="}"> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__cpu__amo_8h.html#a5e73eaa273c41a06972e862976fda53c"> 58</a></span><span class="keyword">inline</span> uint32_t __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__cpu__amo_8h.html#a5e73eaa273c41a06972e862976fda53c">neorv32_cpu_amosc</a>(uint32_t addr, uint32_t wdata) {</div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="preprocessor">#if defined __riscv_atomic</span></div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span> uint32_t amo_addr = addr;</div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> uint32_t amo_wdata = wdata;</div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span> uint32_t amo_status;</div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span> </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span> <span class="keyword">asm</span> <span class="keyword">volatile</span> (<span class="stringliteral">&quot;sc.w %[dst], %[src], (%[addr])&quot;</span> : [dst] <span class="stringliteral">&quot;=r&quot;</span> (amo_status) : [src] <span class="stringliteral">&quot;r&quot;</span> (amo_wdata), [addr] <span class="stringliteral">&quot;r&quot;</span> (amo_addr));</div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span> </div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span> <span class="keywordflow">return</span> amo_status;</div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="preprocessor">#else</span></div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span> (void)addr;</div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span> (void)wdata;</div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span> </div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span> <span class="keywordflow">return</span> 1; <span class="comment">// always fail</span></div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span>}</div> +</div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span> </div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span> </div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span>uint32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#aad0d96e61bacc3af13ff471dd44ca8e9">neorv32_cpu_amoswapw</a>(uint32_t addr, uint32_t wdata);</div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span>uint32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#ada27ec89b2530f7b7f14de947cc82bf9">neorv32_cpu_amoaddw</a>(uint32_t addr, uint32_t wdata);</div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span>uint32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#a9b4540dadbfd5da907117570d8006e36">neorv32_cpu_amoandw</a>(uint32_t addr, uint32_t wdata);</div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span>uint32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#adc80b1f2b3a4e70fee44c0edb08fc402">neorv32_cpu_amoorw</a>(uint32_t addr, uint32_t wdata);</div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span>uint32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#a65b67f48356fa9b30596485473311377">neorv32_cpu_amoxorw</a>(uint32_t addr, uint32_t wdata);</div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span>int32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#a62cf36637d7a04079228acecfe8a5cf3">neorv32_cpu_amomaxw</a>(uint32_t addr, int32_t wdata);</div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span>uint32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#a31a6a3b5a33655f4a7b27d4c85b75f07">neorv32_cpu_amomaxuw</a>(uint32_t addr, uint32_t wdata);</div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span>int32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#a8e383fb8825538b5579d5ce075830697">neorv32_cpu_amominw</a>(uint32_t addr, int32_t wdata);</div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span>uint32_t <a class="code hl_function" href="neorv32__cpu__amo_8h.html#a1281e18b95cd525073e1123c5d04e9e2">neorv32_cpu_amominuw</a>(uint32_t addr, uint32_t wdata);</div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_cpu_amo_h</span></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_a1281e18b95cd525073e1123c5d04e9e2"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#a1281e18b95cd525073e1123c5d04e9e2">neorv32_cpu_amominuw</a></div><div class="ttdeci">uint32_t neorv32_cpu_amominuw(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:315</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_a31a6a3b5a33655f4a7b27d4c85b75f07"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#a31a6a3b5a33655f4a7b27d4c85b75f07">neorv32_cpu_amomaxuw</a></div><div class="ttdeci">uint32_t neorv32_cpu_amomaxuw(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:243</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_a5e73eaa273c41a06972e862976fda53c"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#a5e73eaa273c41a06972e862976fda53c">neorv32_cpu_amosc</a></div><div class="ttdeci">uint32_t neorv32_cpu_amosc(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.h:58</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_a62cf36637d7a04079228acecfe8a5cf3"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#a62cf36637d7a04079228acecfe8a5cf3">neorv32_cpu_amomaxw</a></div><div class="ttdeci">int32_t neorv32_cpu_amomaxw(uint32_t addr, int32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:207</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_a65b67f48356fa9b30596485473311377"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#a65b67f48356fa9b30596485473311377">neorv32_cpu_amoxorw</a></div><div class="ttdeci">uint32_t neorv32_cpu_amoxorw(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:171</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_a8e383fb8825538b5579d5ce075830697"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#a8e383fb8825538b5579d5ce075830697">neorv32_cpu_amominw</a></div><div class="ttdeci">int32_t neorv32_cpu_amominw(uint32_t addr, int32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:279</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_a9b4540dadbfd5da907117570d8006e36"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#a9b4540dadbfd5da907117570d8006e36">neorv32_cpu_amoandw</a></div><div class="ttdeci">uint32_t neorv32_cpu_amoandw(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:99</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_aad0d96e61bacc3af13ff471dd44ca8e9"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#aad0d96e61bacc3af13ff471dd44ca8e9">neorv32_cpu_amoswapw</a></div><div class="ttdeci">uint32_t neorv32_cpu_amoswapw(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:29</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_ad4437bbc61a4e40d7d01dfe9459f6639"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#ad4437bbc61a4e40d7d01dfe9459f6639">neorv32_cpu_amolr</a></div><div class="ttdeci">uint32_t neorv32_cpu_amolr(uint32_t addr)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.h:31</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_ada27ec89b2530f7b7f14de947cc82bf9"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#ada27ec89b2530f7b7f14de947cc82bf9">neorv32_cpu_amoaddw</a></div><div class="ttdeci">uint32_t neorv32_cpu_amoaddw(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:63</div></div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_adc80b1f2b3a4e70fee44c0edb08fc402"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#adc80b1f2b3a4e70fee44c0edb08fc402">neorv32_cpu_amoorw</a></div><div class="ttdeci">uint32_t neorv32_cpu_amoorw(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.c:135</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a 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id="r_a13019b8afa1a80c0e5c24eb4d72e75c1"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a13019b8afa1a80c0e5c24eb4d72e75c1">neorv32_cpu_cfu_available</a> (void)</td></tr> +<tr class="separator:a13019b8afa1a80c0e5c24eb4d72e75c1"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>CPU Core custom functions unit HW driver source file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a13019b8afa1a80c0e5c24eb4d72e75c1" name="a13019b8afa1a80c0e5c24eb4d72e75c1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a13019b8afa1a80c0e5c24eb4d72e75c1">&#9670;&#160;</a></span>neorv32_cpu_cfu_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_cpu_cfu_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if custom functions unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if CFU was not synthesized, 1 if CFU is available. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__cpu__cfu_8h.html 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+</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_cpu_cfu.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>CPU Core custom functions unit HW driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__cpu__cfu_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Low-level CFU custom instruction prototypes ("intrinsics").</div></td></tr> +<tr><td colspan="2"><div class="groupText"><p>Note that each instruction provides a uint32_t return value. </p> +</div></td></tr> +<tr class="memitem:a69d60ccd0cee950b08ce585c3f13b85c" id="r_a69d60ccd0cee950b08ce585c3f13b85c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a69d60ccd0cee950b08ce585c3f13b85c">neorv32_cfu_r3_instr</a>(funct7, funct3, rs1, rs2)</td></tr> +<tr class="separator:a69d60ccd0cee950b08ce585c3f13b85c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a046a640f7f4a7b1b99a824fb325e2079" id="r_a046a640f7f4a7b1b99a824fb325e2079"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a046a640f7f4a7b1b99a824fb325e2079">neorv32_cfu_r4_instr</a>(funct3, rs1, rs2, rs3)</td></tr> +<tr class="separator:a046a640f7f4a7b1b99a824fb325e2079"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:a13019b8afa1a80c0e5c24eb4d72e75c1" id="r_a13019b8afa1a80c0e5c24eb4d72e75c1"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a13019b8afa1a80c0e5c24eb4d72e75c1">neorv32_cpu_cfu_available</a> (void)</td></tr> +<tr class="separator:a13019b8afa1a80c0e5c24eb4d72e75c1"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>CPU Core custom functions unit HW driver header file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a69d60ccd0cee950b08ce585c3f13b85c" name="a69d60ccd0cee950b08ce585c3f13b85c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a69d60ccd0cee950b08ce585c3f13b85c">&#9670;&#160;</a></span>neorv32_cfu_r3_instr</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_cfu_r3_instr</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct7</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct3</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs2</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">CUSTOM_INSTR_R3_TYPE(funct7, rs2, rs1, funct3, 0b0001011)</div> +</div><!-- fragment --><p>R3-type CFU custom instruction (CUSTOM-0 opcode) </p> + +</div> +</div> +<a id="a046a640f7f4a7b1b99a824fb325e2079" name="a046a640f7f4a7b1b99a824fb325e2079"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a046a640f7f4a7b1b99a824fb325e2079">&#9670;&#160;</a></span>neorv32_cfu_r4_instr</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_cfu_r4_instr</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct3</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs3</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">CUSTOM_INSTR_R4_TYPE(rs3, rs2, rs1, funct3, 0b0101011)</div> +</div><!-- fragment --><p>R4-type CFU custom instruction (CUSTOM-1 opcode) </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a13019b8afa1a80c0e5c24eb4d72e75c1" name="a13019b8afa1a80c0e5c24eb4d72e75c1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a13019b8afa1a80c0e5c24eb4d72e75c1">&#9670;&#160;</a></span>neorv32_cpu_cfu_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_cpu_cfu_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if custom functions unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if CFU was not synthesized, 1 if CFU is available. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__cpu__cfu_8h_source.html b/sw/neorv32__cpu__cfu_8h_source.html new file mode 100644 index 000000000..5314bba35 --- /dev/null +++ b/sw/neorv32__cpu__cfu_8h_source.html @@ -0,0 +1,126 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" 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+<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_cpu_cfu.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__cpu__cfu_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_cpu_cfu_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_cpu_cfu_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__cpu__cfu_8h.html#a13019b8afa1a80c0e5c24eb4d72e75c1">neorv32_cpu_cfu_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span> </div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span> </div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"><a class="line" href="neorv32__cpu__cfu_8h.html#a69d60ccd0cee950b08ce585c3f13b85c"> 34</a></span><span class="preprocessor">#define neorv32_cfu_r3_instr(funct7, funct3, rs1, rs2) CUSTOM_INSTR_R3_TYPE(funct7, rs2, rs1, funct3, 0b0001011)</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"><a class="line" href="neorv32__cpu__cfu_8h.html#a046a640f7f4a7b1b99a824fb325e2079"> 36</a></span><span class="preprocessor">#define neorv32_cfu_r4_instr(funct3, rs1, rs2, rs3) CUSTOM_INSTR_R4_TYPE(rs3, rs2, rs1, funct3, 0b0101011)</span></div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_cpu_cfu_h</span></div> +<div class="ttc" id="aneorv32__cpu__cfu_8h_html_a13019b8afa1a80c0e5c24eb4d72e75c1"><div class="ttname"><a href="neorv32__cpu__cfu_8h.html#a13019b8afa1a80c0e5c24eb4d72e75c1">neorv32_cpu_cfu_available</a></div><div class="ttdeci">int neorv32_cpu_cfu_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_cfu.c:24</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__cpu__csr_8h.html b/sw/neorv32__cpu__csr_8h.html new file mode 100644 index 000000000..134a5fdc7 --- /dev/null +++ b/sw/neorv32__cpu__csr_8h.html @@ -0,0 +1,1271 @@ +<!DOCTYPE html PUBLIC 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class="title">neorv32_cpu_csr.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Control and Status Registers (CSR) definitions. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__cpu__csr_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a> +Enumerations</h2></td></tr> +<tr class="memitem:ac065a8cc32eed9a69ea1798492a69f49" id="r_ac065a8cc32eed9a69ea1798492a69f49"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49">NEORV32_CSR_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a">CSR_FFLAGS</a> = 0x001 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a7f198c465959dde37b7056dd06d45812">CSR_FRM</a> = 0x002 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a5e1abf46b4f55bd18e1d132b32696ab6">CSR_FCSR</a> = 0x003 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ad0e5de789d6390f750b8af03cdd15450">CSR_MSTATUS</a> = 0x300 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ade079242596ce14ce1ba9842ed29b84c">CSR_MISA</a> = 0x301 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49acc0f9f5f3b5702f1b57f2ba3b6b62610">CSR_MIE</a> = 0x304 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49aa632d218400268df6dc6b289ff088d21">CSR_MTVEC</a> = 0x305 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a1860dd9579906c67a3565063043dcf78">CSR_MCOUNTEREN</a> = 0x306 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ac2541060307369b2031e9ec07bbd0067">CSR_MSTATUSH</a> = 0x310 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a3ce1dc0e2810f0df78feaa1c607a5ca6">CSR_MCOUNTINHIBIT</a> = 0x320 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a9c55619ffb05e84b7210e2d47326fa98">CSR_MENVCFG</a> = 0x30a +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a46b8d3c288cbbfbf5a0af6e5cd8c5bc8">CSR_MENVCFGH</a> = 0x31a +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a4a93ac5ab276cfd2f9cd296c8ce1bff6">CSR_MHPMEVENT3</a> = 0x323 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ab5f998725e002ffc2ff516ee973fe459">CSR_MHPMEVENT4</a> = 0x324 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a2524659ca2785af51af7acf9cd560a9d">CSR_MHPMEVENT5</a> = 0x325 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a1cfa1e3bc3c8a1c9a86c251a510d11cd">CSR_MHPMEVENT6</a> = 0x326 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a2e53e6e01ca8d1b801f6dfba602f3f59">CSR_MHPMEVENT7</a> = 0x327 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ad6296ca83bbe1280624f3c21adbd8a79">CSR_MHPMEVENT8</a> = 0x328 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af6727a9bdd60ccf020812095b7396632">CSR_MHPMEVENT9</a> = 0x329 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a23850b1804966cde2c1e84cde752d512">CSR_MHPMEVENT10</a> = 0x32a +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a7fb1de2019dd2b548084d5ca1630efbf">CSR_MHPMEVENT11</a> = 0x32b +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ad648b5ece209d47e9484fd7aa83e8e5f">CSR_MHPMEVENT12</a> = 0x32c +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a8c31899b81bb5dba9b92a0f0ca71aea6">CSR_MHPMEVENT13</a> = 0x32d +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a964a6a50d0138447fad47e9c982a7ba4">CSR_MHPMEVENT14</a> = 0x32e +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a06dfdeed757606529e4a99c033691b54">CSR_MHPMEVENT15</a> = 0x32f +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ae29976bb072639975ad0cdb985c7f004">CSR_MSCRATCH</a> = 0x340 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a5d60a25a66754066589e8facb7d41153">CSR_MEPC</a> = 0x341 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a2e14b57fee5376741634db7980a5005b">CSR_MCAUSE</a> = 0x342 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a76d30359e3b54197fb53f9939734cf1e">CSR_MTVAL</a> = 0x343 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49addb485275c954d1181d5bd4e4609082c">CSR_MIP</a> = 0x344 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a4f229c169ada239033a1383412ce58c8">CSR_MTINST</a> = 0x34a +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af1a79349e46a4829af78d2cdfd0dc44f">CSR_PMPCFG0</a> = 0x3a0 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a22eea318ec1ac72cc14e133b71ef4b16">CSR_PMPCFG1</a> = 0x3a1 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a0c9492f6b956f088847f72b28e7b1446">CSR_PMPCFG2</a> = 0x3a2 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a067ed3778590ae97dc9b16069f0ed850">CSR_PMPCFG3</a> = 0x3a3 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a8941071db6145d34fff842249c0dcb9f">CSR_PMPADDR0</a> = 0x3b0 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a6a2933f3a1fa243de02db8a795e3ca41">CSR_PMPADDR1</a> = 0x3b1 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49aa0b8c0561e8a778dce9c3b86499ffc50">CSR_PMPADDR2</a> = 0x3b2 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a89bad989197e9358563557311b3c97e9">CSR_PMPADDR3</a> = 0x3b3 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ace4529c53ad2d46767f86d920eada507">CSR_PMPADDR4</a> = 0x3b4 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ad9e78f71409fd7783cc2ae7c28b5e42c">CSR_PMPADDR5</a> = 0x3b5 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af57b5b7b57cd6e8b3489a27dfd702444">CSR_PMPADDR6</a> = 0x3b6 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ae8ea19cf3e527dbc0d36a43dfd1b7346">CSR_PMPADDR7</a> = 0x3b7 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49aec68bf7e26e44170c24599f7c6a8365b">CSR_PMPADDR8</a> = 0x3b8 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a54d38c8cf364d886eb7ac64463eedf77">CSR_PMPADDR9</a> = 0x3b9 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ad97b6fe934a3bed6b02d0c8d81165d60">CSR_PMPADDR10</a> = 0x3ba +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a3e5708c0f79cf58ae761b6bb8c2a4383">CSR_PMPADDR11</a> = 0x3bb +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a23026793ee53c8d55d23f63195368a6b">CSR_PMPADDR12</a> = 0x3bc +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a30879e88b250d3e94d9d9e728ffcc2cc">CSR_PMPADDR13</a> = 0x3bd +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a91a8b5008b4e08ab34c1516e21bf0ba8">CSR_PMPADDR14</a> = 0x3be +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a6879b4bf5d2db92d236b9091df4841f2">CSR_PMPADDR15</a> = 0x3bf +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49aaae2f0b2e3f5a31dff933868873f6d5d">CSR_TSELECT</a> = 0x7a0 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a80eab0e17f5fe41edde485044674dc57">CSR_TDATA1</a> = 0x7a1 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49acf336638697242b691b691dc56b9aadc">CSR_TDATA2</a> = 0x7a2 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af67c819c104f7e3ec34f2cbb847cf83b">CSR_TINFO</a> = 0x7a4 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a6bb3ba59a25803d6f98faad67609a9a9">CSR_DCSR</a> = 0x7b0 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af4c98d949d2eb44f2518fdf314344d3b">CSR_DPC</a> = 0x7b1 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a0f4a1ae740efd80d14d21e90f355e9d7">CSR_DSCRATCH0</a> = 0x7b2 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ae0e9cf0b99b8614ea0b870d38970281f">CSR_CFUREG0</a> = 0x800 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a382304065a6db773f925b80b9447b8a8">CSR_CFUREG1</a> = 0x801 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a427d7cf036b49efd46166c01f0504b68">CSR_CFUREG2</a> = 0x802 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49aefefa1cff0cf5d01109486e5a8bebedf">CSR_CFUREG3</a> = 0x803 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a32c22641ed66c6d20902306a2b1fad77">CSR_MCYCLE</a> = 0xb00 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a98f5e2cf2d5dbb0125a222b0065c86eb">CSR_MINSTRET</a> = 0xb02 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ae0a96f499dcde474af6ee620fbb1ebdc">CSR_MHPMCOUNTER3</a> = 0xb03 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a9b84bd948dd52a7779b5fd16beddaab9">CSR_MHPMCOUNTER4</a> = 0xb04 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af15d389bb8f91c989df488d231666394">CSR_MHPMCOUNTER5</a> = 0xb05 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af65b9e99b9cadb3cb8d37f97cdbfeb9d">CSR_MHPMCOUNTER6</a> = 0xb06 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a919f39b0d299feb80403b42a466de444">CSR_MHPMCOUNTER7</a> = 0xb07 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a5a4cde90c547e913bddc719b3ab75e79">CSR_MHPMCOUNTER8</a> = 0xb08 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a18c2a249f1f7852f42f9e10dc59d46bb">CSR_MHPMCOUNTER9</a> = 0xb09 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a575e5342d8ec304c32dbbe99d6fd6c0f">CSR_MHPMCOUNTER10</a> = 0xb0a +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a8840b3d4f45453fc96813ccb369a68e5">CSR_MHPMCOUNTER11</a> = 0xb0b +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a1328a226d36d23cc81740397bde47a4e">CSR_MHPMCOUNTER12</a> = 0xb0c +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a9bdd102877ff50d38c86c3d741aeb4b0">CSR_MHPMCOUNTER13</a> = 0xb0d +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49adae22d860d8162e15120051951e45229">CSR_MHPMCOUNTER14</a> = 0xb0e +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a20400929087fabba410a098667d2d4ff">CSR_MHPMCOUNTER15</a> = 0xb0f +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a28fcfd06ca1012c19cf053e57689687b">CSR_MCYCLEH</a> = 0xb80 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49afffb28b62b9baa127ae3bad919208988">CSR_MINSTRETH</a> = 0xb82 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a252980a4da90c1f5c1ef85d164f72f25">CSR_MHPMCOUNTER3H</a> = 0xb83 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a2e9cfbf3c2828dd4bd92d2b8a1c99f85">CSR_MHPMCOUNTER4H</a> = 0xb84 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a7648dd0a47007d44a14e95ba47726599">CSR_MHPMCOUNTER5H</a> = 0xb85 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a49b7bc2df67a6c73a68757de9b218f77">CSR_MHPMCOUNTER6H</a> = 0xb86 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ac0183bb6f357ed33136493ae7ded987a">CSR_MHPMCOUNTER7H</a> = 0xb87 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a9e75518df7d14a009e3a0d5588641ddc">CSR_MHPMCOUNTER8H</a> = 0xb88 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a7341886c7a4aed6fc7d8677c016a2cb8">CSR_MHPMCOUNTER9H</a> = 0xb89 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a1e41d2b27d7e8da14871852d81123cfd">CSR_MHPMCOUNTER10H</a> = 0xb8a +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a7fd76fcfc0d0dd47e112786bea5e4071">CSR_MHPMCOUNTER11H</a> = 0xb8b +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a332ec2b0740f8e899a1b2ec86f7ee9f2">CSR_MHPMCOUNTER12H</a> = 0xb8c +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a5de5c5a036dc594a554d37df9ccf657d">CSR_MHPMCOUNTER13H</a> = 0xb8d +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ac65bab6fd71439600c8fc549171251fa">CSR_MHPMCOUNTER14H</a> = 0xb8e +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af609807e2917f73e27e5f27b38a0fa46">CSR_MHPMCOUNTER15H</a> = 0xb8f +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49aaaf0f6b17a06d5922bcfdb47b382137e">CSR_CYCLE</a> = 0xc00 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a8144da8cd8691ac54aa0712685865b66">CSR_INSTRET</a> = 0xc02 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49aa276bedb7dab28935163397b4879f6db">CSR_CYCLEH</a> = 0xc80 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a9b66978d76260283007d399fc735d153">CSR_INSTRETH</a> = 0xc82 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49af5c5a21909aaca2b57f9a15f4bac246b">CSR_MVENDORID</a> = 0xf11 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49ad95cb95266533123447ff0e917f890e4">CSR_MARCHID</a> = 0xf12 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a06d39cf0f13d6401dcf426d56149c8cd">CSR_MIMPID</a> = 0xf13 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a6ba48e2306ae92f498552e1ea04d6790">CSR_MHARTID</a> = 0xf14 +, <br /> +&#160;&#160;<a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a0545d0921b3f90d037dbb25bc5fcc2f9">CSR_MCONFIGPTR</a> = 0xf15 +, <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49a396847bcf1634a1602ab117bfb57bdd2">CSR_MXISA</a> = 0xfc0 +<br /> + }</td></tr> +<tr class="separator:ac065a8cc32eed9a69ea1798492a69f49"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afde0761e3150d82511136f56179c204b" id="r_afde0761e3150d82511136f56179c204b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afde0761e3150d82511136f56179c204b">NEORV32_CSR_FFLAGS_enum</a> { <br /> +&#160;&#160;<a class="el" href="#afde0761e3150d82511136f56179c204ba91a314defd310786a9ed67f7ef2ef5a6">CSR_FFLAGS_NX</a> = 0 +, <a class="el" href="#afde0761e3150d82511136f56179c204babc6d405724563844569028f463885819">CSR_FFLAGS_UF</a> = 1 +, <a class="el" href="#afde0761e3150d82511136f56179c204ba612390e07a065fa13eeaeac84af48c6e">CSR_FFLAGS_OF</a> = 2 +, <a class="el" href="#afde0761e3150d82511136f56179c204ba365f3f519bca34a349907c82c873d52b">CSR_FFLAGS_DZ</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#afde0761e3150d82511136f56179c204ba3ac330a4b03178e756c980eaa48ad165">CSR_FFLAGS_NV</a> = 4 +<br /> + }</td></tr> +<tr class="separator:afde0761e3150d82511136f56179c204b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6d3c6aaee79b679e954c54563d7ee500" id="r_a6d3c6aaee79b679e954c54563d7ee500"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6d3c6aaee79b679e954c54563d7ee500">NEORV32_CSR_MCOUNTEREN_enum</a> { <a class="el" href="#a6d3c6aaee79b679e954c54563d7ee500a3d0c8ff6ba2c557cb5b5d353bdb95790">CSR_MCOUNTEREN_CY</a> = 0 +, <a class="el" href="#a6d3c6aaee79b679e954c54563d7ee500a97e36c94b71fa2f9a805bbe47b0bc1b5">CSR_MCOUNTEREN_IR</a> = 2 + }</td></tr> +<tr class="separator:a6d3c6aaee79b679e954c54563d7ee500"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a76b70a2334131e7589d84c1ee96de485" id="r_a76b70a2334131e7589d84c1ee96de485"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a76b70a2334131e7589d84c1ee96de485">NEORV32_CSR_MSTATUS_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a76b70a2334131e7589d84c1ee96de485ae2603e365b3f1abfb46d53ed6b13dc56">CSR_MSTATUS_MIE</a> = 3 +, <a class="el" href="#a76b70a2334131e7589d84c1ee96de485aaa1d482f828ac9cafc40fcfc298bec34">CSR_MSTATUS_MPIE</a> = 7 +, <a class="el" href="#a76b70a2334131e7589d84c1ee96de485af0ae9aca74144aa7dbdf656f71cc5c97">CSR_MSTATUS_MPP_L</a> = 11 +, <a class="el" href="#a76b70a2334131e7589d84c1ee96de485a8067c609c2360cab3bafa3c43e03dbf0">CSR_MSTATUS_MPP_H</a> = 12 +, <br /> +&#160;&#160;<a class="el" href="#a76b70a2334131e7589d84c1ee96de485a75cefdbdef36b7fc248765b27c606a44">CSR_MSTATUS_MPRV</a> = 17 +, <a class="el" href="#a76b70a2334131e7589d84c1ee96de485ac94a070f3fe7962e8c49a81545cacf2d">CSR_MSTATUS_TW</a> = 21 +<br /> + }</td></tr> +<tr class="separator:a76b70a2334131e7589d84c1ee96de485"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ab6886ca6858d57854495986ef9b5cbfe" id="r_ab6886ca6858d57854495986ef9b5cbfe"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab6886ca6858d57854495986ef9b5cbfe">NEORV32_CSR_MCOUNTINHIBIT_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea201ac39b0eba389b0d02c3951a3311a3">CSR_MCOUNTINHIBIT_CY</a> = 0 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea5f182f39f9a4b871a097a51e57865bfa">CSR_MCOUNTINHIBIT_IR</a> = 2 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeaf7020159e0ba346561bfba101d22c752">CSR_MCOUNTINHIBIT_HPM3</a> = 3 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea40427b799da049413c5536afa623c61d">CSR_MCOUNTINHIBIT_HPM4</a> = 4 +, <br /> +&#160;&#160;<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea2769a6e6a75f2f903523e4e95a899bb6">CSR_MCOUNTINHIBIT_HPM5</a> = 5 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfead55b6af15841617d7dca3ab4fab893db">CSR_MCOUNTINHIBIT_HPM6</a> = 6 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea3b3571fceb687da2d3807b0e59bdf7ab">CSR_MCOUNTINHIBIT_HPM7</a> = 7 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeabd21344124eda4402523203185a58b8a">CSR_MCOUNTINHIBIT_HPM8</a> = 8 +, <br /> +&#160;&#160;<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea0f207455df0fed75fa68ba49c435889a">CSR_MCOUNTINHIBIT_HPM9</a> = 9 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea9517cd32744c5064fa30780f911cd22e">CSR_MCOUNTINHIBIT_HPM10</a> = 10 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeacaf997fe8b912596224e2bb632e6a806">CSR_MCOUNTINHIBIT_HPM11</a> = 11 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea8d866a4c815d8ba890a1e00ce9600486">CSR_MCOUNTINHIBIT_HPM12</a> = 12 +, <br /> +&#160;&#160;<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfead9f6c4eb4284ee82b9e8d0c79f62b3ed">CSR_MCOUNTINHIBIT_HPM13</a> = 13 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeaa83c0688869b1c43de0c4474e940f987">CSR_MCOUNTINHIBIT_HPM14</a> = 14 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea0b547cb5876c0e7956e3d062e0784085">CSR_MCOUNTINHIBIT_HPM15</a> = 15 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea68aba71ea77aba4005fb24a945ef38e4">CSR_MCOUNTINHIBIT_HPM16</a> = 16 +, <br /> +&#160;&#160;<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea8d57acf13a086635a63bc13ccdf479b3">CSR_MCOUNTINHIBIT_HPM17</a> = 17 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeaa680d196d2ba0e403801a860bb9d8ce0">CSR_MCOUNTINHIBIT_HPM18</a> = 18 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea3683e296caafe771b6dd57f4cf86f3dc">CSR_MCOUNTINHIBIT_HPM19</a> = 19 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeaeb4b1b6abafd22eec0764d5503878cca">CSR_MCOUNTINHIBIT_HPM20</a> = 20 +, <br /> +&#160;&#160;<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea1dc0276a5354c805ac56fd46c5037d38">CSR_MCOUNTINHIBIT_HPM21</a> = 21 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeaf1b6153a0c664367bfefb78b2ca8b34e">CSR_MCOUNTINHIBIT_HPM22</a> = 22 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea85c0c2b2a5101380dec72516dda1a904">CSR_MCOUNTINHIBIT_HPM23</a> = 23 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea74ec85a2e94aa0b9e8af29401ef7ecb1">CSR_MCOUNTINHIBIT_HPM24</a> = 24 +, <br /> +&#160;&#160;<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeaee2b5a2b7bd7ac07dae45900bc2faf46">CSR_MCOUNTINHIBIT_HPM25</a> = 25 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea141a4a211c496d2af1c79d8e8e0c2a74">CSR_MCOUNTINHIBIT_HPM26</a> = 26 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea46def851d4582b4bcec1f9d8bafd58db">CSR_MCOUNTINHIBIT_HPM27</a> = 27 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea33d0fd3378ec3a2fcc3c8738c6cd2f32">CSR_MCOUNTINHIBIT_HPM28</a> = 28 +, <br /> +&#160;&#160;<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfeaa39882f7dad9b7e16b317c75bad31382">CSR_MCOUNTINHIBIT_HPM29</a> = 29 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea0f45818fa4cb9033a3093987fa8515c7">CSR_MCOUNTINHIBIT_HPM30</a> = 30 +, <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfea1da1186ef2f4e7297a4fecaaccdc1d05">CSR_MCOUNTINHIBIT_HPM31</a> = 31 +<br /> + }</td></tr> +<tr class="separator:ab6886ca6858d57854495986ef9b5cbfe"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0e9714690687badee43180c3cb62be33" id="r_a0e9714690687badee43180c3cb62be33"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a0e9714690687badee43180c3cb62be33afd2f1c78c442c8c29ab075cacee0a27a">CSR_MIE_MSIE</a> = 3 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a3658e8663e94cd8eaa7201b7a850d083">CSR_MIE_MTIE</a> = 7 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33ae8e4f0ee46abbbb3361de035a57b8324">CSR_MIE_MEIE</a> = 11 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a99f43f8bbfb29fba6224f081c363ac7d">CSR_MIE_FIRQ0E</a> = 16 +, <br /> +&#160;&#160;<a class="el" href="#a0e9714690687badee43180c3cb62be33ac1e1d44becec1b393f79a118ed3d8beb">CSR_MIE_FIRQ1E</a> = 17 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33afc805280e20ffface116ca61e11645f7">CSR_MIE_FIRQ2E</a> = 18 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a666066099d6cebadbef21d81c179e8db">CSR_MIE_FIRQ3E</a> = 19 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a592939f1b7d79097f7f13d6ab0c268dc">CSR_MIE_FIRQ4E</a> = 20 +, <br /> +&#160;&#160;<a class="el" href="#a0e9714690687badee43180c3cb62be33a3079a8fbf3b8e376865bff76f2173698">CSR_MIE_FIRQ5E</a> = 21 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a96315d6b5b9531bcbc1e78a3c9ab166a">CSR_MIE_FIRQ6E</a> = 22 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a3d9d729940170609affbc6813054ebe8">CSR_MIE_FIRQ7E</a> = 23 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a396c6c4b425b3fff598e2f846052f98e">CSR_MIE_FIRQ8E</a> = 24 +, <br /> +&#160;&#160;<a class="el" href="#a0e9714690687badee43180c3cb62be33a06fdb61dab31c3490da6c37d47914f19">CSR_MIE_FIRQ9E</a> = 25 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33affcb52dc57bb8c0cb1e7d3c1392d544a">CSR_MIE_FIRQ10E</a> = 26 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33af058342854a0becd3bcc33877d9244cd">CSR_MIE_FIRQ11E</a> = 27 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a41f91a37f7e0c75c783312af6a72e943">CSR_MIE_FIRQ12E</a> = 28 +, <br /> +&#160;&#160;<a class="el" href="#a0e9714690687badee43180c3cb62be33a134ed02c7293008b21b1df472be8f11f">CSR_MIE_FIRQ13E</a> = 29 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33a864d135708530016cfc52a65a1e4d79b">CSR_MIE_FIRQ14E</a> = 30 +, <a class="el" href="#a0e9714690687badee43180c3cb62be33aa2dfa1183af312de2959dadd217fddc1">CSR_MIE_FIRQ15E</a> = 31 +<br /> + }</td></tr> +<tr class="separator:a0e9714690687badee43180c3cb62be33"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6301c554bf831b97fc28f9984a1ec21b" id="r_a6301c554bf831b97fc28f9984a1ec21b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba1470cfe04f9d3ce45b7156b2a7fae159">CSR_MIP_MSIP</a> = 3 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba344943c62922561378d33ec51ac236e4">CSR_MIP_MTIP</a> = 7 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba1d761ef98f88c40509168ac66b7a4872">CSR_MIP_MEIP</a> = 11 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba28a85ad8bd4c30fd3a91298dfa4fdb00">CSR_MIP_FIRQ0P</a> = 16 +, <br /> +&#160;&#160;<a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba2b577b1da1074c29ad58005af1f91d52">CSR_MIP_FIRQ1P</a> = 17 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21badf45c5a135431f958fa63574c1dfac6e">CSR_MIP_FIRQ2P</a> = 18 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba7512bb6c4841ddd477422b49ebb2a155">CSR_MIP_FIRQ3P</a> = 19 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21bab6421f242bb8a487a986346e11196eb8">CSR_MIP_FIRQ4P</a> = 20 +, <br /> +&#160;&#160;<a class="el" href="#a6301c554bf831b97fc28f9984a1ec21baaa55d19f9a47889bc364c94bda04b677">CSR_MIP_FIRQ5P</a> = 21 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21baffa7342631aa0526aaa44c0c549b1f3e">CSR_MIP_FIRQ6P</a> = 22 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21baad691486001a68f2375dcf5793ee795a">CSR_MIP_FIRQ7P</a> = 23 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21baf5bbd23d4f311f640db42e9015f87580">CSR_MIP_FIRQ8P</a> = 24 +, <br /> +&#160;&#160;<a class="el" href="#a6301c554bf831b97fc28f9984a1ec21bad94c9691ce59b97fcfec14d345046c3e">CSR_MIP_FIRQ9P</a> = 25 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba2b50cfa8be461b088ea8506ce4c741ba">CSR_MIP_FIRQ10P</a> = 26 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba69ea0d3d76d4cec398f3b96959cc3544">CSR_MIP_FIRQ11P</a> = 27 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba03edd398920b817150d29107c0b40792">CSR_MIP_FIRQ12P</a> = 28 +, <br /> +&#160;&#160;<a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba14da6a2a962bf82970638a948ffbc570">CSR_MIP_FIRQ13P</a> = 29 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21baad1e5e452a9c37561308765431f0260d">CSR_MIP_FIRQ14P</a> = 30 +, <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21ba12da8c32d38d5a3539a0b766718bfd2d">CSR_MIP_FIRQ15P</a> = 31 +<br /> + }</td></tr> +<tr class="separator:a6301c554bf831b97fc28f9984a1ec21b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afed7f00bbb39468f038d9ca6fbac830c" id="r_afed7f00bbb39468f038d9ca6fbac830c"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afed7f00bbb39468f038d9ca6fbac830c">NEORV32_CSR_MISA_enum</a> { <br /> +&#160;&#160;<a class="el" href="#afed7f00bbb39468f038d9ca6fbac830cadd469404a928e012a298773ec46926ad">CSR_MISA_B</a> = 1 +, <a class="el" href="#afed7f00bbb39468f038d9ca6fbac830ca886699013158c74810598fa2fd6b07fa">CSR_MISA_C</a> = 2 +, <a class="el" href="#afed7f00bbb39468f038d9ca6fbac830ca0ac798fd19cb7dbe1146afecda448fec">CSR_MISA_E</a> = 4 +, <a class="el" href="#afed7f00bbb39468f038d9ca6fbac830ca6091fd2c7ae38ad33be68a0fdfa50cca">CSR_MISA_I</a> = 8 +, <br /> +&#160;&#160;<a class="el" href="#afed7f00bbb39468f038d9ca6fbac830ca317a631e4598532f5bffe8fb93aff94b">CSR_MISA_M</a> = 12 +, <a class="el" href="#afed7f00bbb39468f038d9ca6fbac830cacd9d71e674d3a6d04984b6df706d9deb">CSR_MISA_U</a> = 20 +, <a class="el" href="#afed7f00bbb39468f038d9ca6fbac830ca0b119a20be29fcae8fecf2a81c60d193">CSR_MISA_X</a> = 23 +, <a class="el" href="#afed7f00bbb39468f038d9ca6fbac830cab5a55e97b8511f42fe68559a38f7f138">CSR_MISA_MXL_LO</a> = 30 +, <br /> +&#160;&#160;<a class="el" href="#afed7f00bbb39468f038d9ca6fbac830cafb3e4b08b87f5c161468a9e58ade12cc">CSR_MISA_MXL_HI</a> = 31 +<br /> + }</td></tr> +<tr class="separator:afed7f00bbb39468f038d9ca6fbac830c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af05490a8af176ab4ba945d327d448387" id="r_af05490a8af176ab4ba945d327d448387"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af05490a8af176ab4ba945d327d448387">NEORV32_CSR_XISA_enum</a> { <br /> +&#160;&#160;<a class="el" href="#af05490a8af176ab4ba945d327d448387accf1dd12be89e45df1423a5600789f2c">CSR_MXISA_ZICSR</a> = 0 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a6979d4389ed9f8605d338fc616d29f0e">CSR_MXISA_ZIFENCEI</a> = 1 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a79b2b4b20e08ad31b50724a7a27fb20f">CSR_MXISA_ZMMUL</a> = 2 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387af422ae3b5caba59e33a29b5d069597e0">CSR_MXISA_ZXCFU</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#af05490a8af176ab4ba945d327d448387a31788af612f04bc6b2a2bd15c1fb63c1">CSR_MXISA_ZKT</a> = 4 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a56ec3195d0d27f362f58fadb2e037ed1">CSR_MXISA_ZFINX</a> = 5 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387ab1f289cfaa9f54f7831a2abcdf9fca2e">CSR_MXISA_ZICOND</a> = 6 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a42a3b78195741af4b6aeeb98cbea46fe">CSR_MXISA_ZICNTR</a> = 7 +, <br /> +&#160;&#160;<a class="el" href="#af05490a8af176ab4ba945d327d448387a6938948290d86b0ad25923f35d6c86d3">CSR_MXISA_SMPMP</a> = 8 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387ac13e6883af3a9da18057462239b9fb34">CSR_MXISA_ZIHPM</a> = 9 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387ab6aec595e6aa5ce7c98c7806d23d7af5">CSR_MXISA_SDEXT</a> = 10 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a59eae4272528f589f299ef9cce45af5b">CSR_MXISA_SDTRIG</a> = 11 +, <br /> +&#160;&#160;<a class="el" href="#af05490a8af176ab4ba945d327d448387a34519a66e749d63dc5bc7c145c297b64">CSR_MXISA_ZBKX</a> = 12 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a48f1de7f79a0633644ae02c463d49375">CSR_MXISA_ZKND</a> = 13 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a216ec44d5be3b158acb7e033e352bad1">CSR_MXISA_ZKNE</a> = 14 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a5fe8e591901e0fd7ba6706c70e9c76ec">CSR_MXISA_ZKNH</a> = 15 +, <br /> +&#160;&#160;<a class="el" href="#af05490a8af176ab4ba945d327d448387adb26c1e5bf6ae112625621dddd331735">CSR_MXISA_ZBKB</a> = 16 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387ac9e87153c096d656b40cb7abdf3afd55">CSR_MXISA_ZBKC</a> = 17 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387ad7e7454a30c82c3d91acbc8c259e8c25">CSR_MXISA_ZKN</a> = 18 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a5e4bf05830b66410bbf2ef2c68e5fd18">CSR_MXISA_ZKSH</a> = 19 +, <br /> +&#160;&#160;<a class="el" href="#af05490a8af176ab4ba945d327d448387a43213190abb77304a78c15196c90a044">CSR_MXISA_ZKSED</a> = 20 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a2649bee3397c74ada7b72677308f38c0">CSR_MXISA_ZKS</a> = 21 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387adfc9122d93a71bf6df178022a52d22c4">CSR_MXISA_ZBA</a> = 22 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a815cbe0149cba2a69025f6bec9946a85">CSR_MXISA_ZBB</a> = 23 +, <br /> +&#160;&#160;<a class="el" href="#af05490a8af176ab4ba945d327d448387a469e8e449f0e442df531c8cf2c4f35c5">CSR_MXISA_ZBS</a> = 24 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387adf45adc0bcbec0c1ffa944099257a947">CSR_MXISA_ZALRSC</a> = 25 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a6843c660d75f33e4252c7fccd4565a2d">CSR_MXISA_RFHWRST</a> = 28 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a48e57689f8a5b51d9ee9d648da7efc64">CSR_MXISA_FASTMUL</a> = 29 +, <br /> +&#160;&#160;<a class="el" href="#af05490a8af176ab4ba945d327d448387ad5ac9e2188757e6c42c159f0c5887868">CSR_MXISA_FASTSHIFT</a> = 30 +, <a class="el" href="#af05490a8af176ab4ba945d327d448387a9b121ec0ad6271b6e07658f861015f6a">CSR_MXISA_IS_SIM</a> = 31 +<br /> + }</td></tr> +<tr class="separator:af05490a8af176ab4ba945d327d448387"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5cb925a3e41efd5e767bb39b3ee60cfe" id="r_a5cb925a3e41efd5e767bb39b3ee60cfe"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea2b683572525adc02ce0910031cfea914">HPMCNT_EVENT_CY</a> = 0 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea578ef6fc107c22b5cb7be5950f695640">HPMCNT_EVENT_TM</a> = 1 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfeaab438295e5f00ffe4c2457a54ee9bfc4">HPMCNT_EVENT_IR</a> = 2 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea685ed663611d988702ec59c254eb61dd">HPMCNT_EVENT_COMPR</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfeabcb123b5b150b4413e5fd48475faab27">HPMCNT_EVENT_WAIT_DIS</a> = 4 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfeaffbb04d0053ebd079c6cacb4e5e7ed6b">HPMCNT_EVENT_WAIT_ALU</a> = 5 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea9e1e2b50352b2555e9c64e76776919a6">HPMCNT_EVENT_BRANCH</a> = 6 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea0f15c5a824cb1678423ac4ef72a5f4f5">HPMCNT_EVENT_BRANCHED</a> = 7 +, <br /> +&#160;&#160;<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea1a06f216e1a12afa0b90d6e1218b3c91">HPMCNT_EVENT_LOAD</a> = 8 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea6a942852e3cd85616a63addb8e9d76f2">HPMCNT_EVENT_STORE</a> = 9 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea67a59934bc66bc7ccf82d24fe8a18a3b">HPMCNT_EVENT_WAIT_LSU</a> = 10 +, <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfea3a4f5bf9251def87a71162dbcf9043c5">HPMCNT_EVENT_TRAP</a> = 11 +<br /> + }</td></tr> +<tr class="separator:a5cb925a3e41efd5e767bb39b3ee60cfe"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abc0e8daad1e9beda4d9950452cc930ea" id="r_abc0e8daad1e9beda4d9950452cc930ea"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a> { <br /> +&#160;&#160;<a class="el" href="#abc0e8daad1e9beda4d9950452cc930eaad3aca82a2ab57364e83f677d3d4f71a6">PMPCFG_R</a> = 0 +, <a class="el" href="#abc0e8daad1e9beda4d9950452cc930eaa7689905760f917499b1151cced384d2f">PMPCFG_W</a> = 1 +, <a class="el" href="#abc0e8daad1e9beda4d9950452cc930eaaec94712deafba09c0cf956c6fd68fa8d">PMPCFG_X</a> = 2 +, <a class="el" href="#abc0e8daad1e9beda4d9950452cc930eaaae1e6440956ad6b7cbf6062aa50f43b1">PMPCFG_A_LSB</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#abc0e8daad1e9beda4d9950452cc930eaa67ad3243eeb74f86a01efbade76f21e4">PMPCFG_A_MSB</a> = 4 +, <a class="el" href="#abc0e8daad1e9beda4d9950452cc930eaa59c294bc43d2117bb55e301eec683f14">PMPCFG_L</a> = 7 +<br /> + }</td></tr> +<tr class="separator:abc0e8daad1e9beda4d9950452cc930ea"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8f2418fb5e2175f35ee2362469ce01f5" id="r_a8f2418fb5e2175f35ee2362469ce01f5"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a> { <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5a003ccfae4aae1dad4fd65d5d4c7737c4">PMP_OFF</a> = 0 +, <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5a629a81a205abee94bad9d5bb5dfa26b1">PMP_TOR</a> = 1 +, <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5aae0e0c33b0d034cb50286239f955d892">PMP_NA4</a> = 2 +, <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5ad555e9dfc0c00612bdea623617ff2820">PMP_NAPOT</a> = 3 + }</td></tr> +<tr class="separator:a8f2418fb5e2175f35ee2362469ce01f5"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acb0fcbc551fec4c45676ff1317be24e1" id="r_acb0fcbc551fec4c45676ff1317be24e1"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a> { <br /> +&#160;&#160;<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a0a8010d7cc91b9557973a7a118828bee">TRAP_CODE_I_MISALIGNED</a> = 0x00000000U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a6a0ebfce4e18f36aeb43d5a65445cfe1">TRAP_CODE_I_ACCESS</a> = 0x00000001U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1af1ad8f557f3b685b59a913611e1da173">TRAP_CODE_I_ILLEGAL</a> = 0x00000002U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a2c9510cb7583a0144f96678fc217335e">TRAP_CODE_BREAKPOINT</a> = 0x00000003U +, <br /> +&#160;&#160;<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a69e68a954da0bb33d1624484a6777ff9">TRAP_CODE_L_MISALIGNED</a> = 0x00000004U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a28448f0c670169140dc28b6794310cea">TRAP_CODE_L_ACCESS</a> = 0x00000005U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a19708405f9f6300edf6b992c6d408a2d">TRAP_CODE_S_MISALIGNED</a> = 0x00000006U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a70bcfc75fe1056d93a3606f78c0cb887">TRAP_CODE_S_ACCESS</a> = 0x00000007U +, <br /> +&#160;&#160;<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1aa102472d6a264bb92e0581ccaa413e02">TRAP_CODE_UENV_CALL</a> = 0x00000008U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a20e5a2680f2f5956bfa92852d5544eac">TRAP_CODE_MENV_CALL</a> = 0x0000000bU +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1ae0cebf99f36ef6be60e4a9d2c9f894b0">TRAP_CODE_MSI</a> = 0x80000003U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a187ae38819b81672c15808e63c3b46b7">TRAP_CODE_MTI</a> = 0x80000007U +, <br /> +&#160;&#160;<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a1a412b9d8eefba7880555d34625d2cc0">TRAP_CODE_MEI</a> = 0x8000000bU +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a0cef77904935798d247d8396838297c1">TRAP_CODE_FIRQ_0</a> = 0x80000010U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1ae0b1049ae7f8cbfb6ff216e69ed5dae7">TRAP_CODE_FIRQ_1</a> = 0x80000011U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1ad753d3e2563b4fd663430af9f3888dc7">TRAP_CODE_FIRQ_2</a> = 0x80000012U +, <br /> +&#160;&#160;<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a356f8485166529503d0fb246bd0aeeb0">TRAP_CODE_FIRQ_3</a> = 0x80000013U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1aaa8e7bb251852ef75a78be71eef0b547">TRAP_CODE_FIRQ_4</a> = 0x80000014U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a5789dfabd8ec265fa0734ddd94e98757">TRAP_CODE_FIRQ_5</a> = 0x80000015U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a809e997f55e83c6812c965655511d473">TRAP_CODE_FIRQ_6</a> = 0x80000016U +, <br /> +&#160;&#160;<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1aeab719bcce9e9551bd6da65a7ae08a26">TRAP_CODE_FIRQ_7</a> = 0x80000017U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1abfd21d1380dcacb9282e525da104d916">TRAP_CODE_FIRQ_8</a> = 0x80000018U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a350e762a599479fb2c6d23ccc5ee22b4">TRAP_CODE_FIRQ_9</a> = 0x80000019U +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a4f6b9c6bba91fe04becb776ad22dcf42">TRAP_CODE_FIRQ_10</a> = 0x8000001aU +, <br /> +&#160;&#160;<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a874dcc43cf8fbbf2e0614e7db9e38334">TRAP_CODE_FIRQ_11</a> = 0x8000001bU +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a151f01e5f284f876cafafc7427720e4c">TRAP_CODE_FIRQ_12</a> = 0x8000001cU +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a7c8e97297cc4dcd6d5a1de65a124f3e9">TRAP_CODE_FIRQ_13</a> = 0x8000001dU +, <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1a821f813de47eb781ab7715f780da3b1e">TRAP_CODE_FIRQ_14</a> = 0x8000001eU +, <br /> +&#160;&#160;<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1aa4eeafe2f6f59aff01e29461c664a110">TRAP_CODE_FIRQ_15</a> = 0x8000001fU +<br /> + }</td></tr> +<tr class="separator:acb0fcbc551fec4c45676ff1317be24e1"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Control and Status Registers (CSR) definitions. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="ac065a8cc32eed9a69ea1798492a69f49" name="ac065a8cc32eed9a69ea1798492a69f49"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac065a8cc32eed9a69ea1798492a69f49">&#9670;&#160;</a></span>NEORV32_CSR_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ac065a8cc32eed9a69ea1798492a69f49">NEORV32_CSR_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Available CPU Control and Status Registers (CSRs) </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a" name="ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a"></a>CSR_FFLAGS&#160;</td><td class="fielddoc"><p>0x001 - fflags: Floating-point accrued exception flags (<a class="el" href="#afde0761e3150d82511136f56179c204b">NEORV32_CSR_FFLAGS_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a7f198c465959dde37b7056dd06d45812" name="ac065a8cc32eed9a69ea1798492a69f49a7f198c465959dde37b7056dd06d45812"></a>CSR_FRM&#160;</td><td class="fielddoc"><p>0x002 - frm: Floating-point dynamic rounding mode </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a5e1abf46b4f55bd18e1d132b32696ab6" name="ac065a8cc32eed9a69ea1798492a69f49a5e1abf46b4f55bd18e1d132b32696ab6"></a>CSR_FCSR&#160;</td><td class="fielddoc"><p>0x003 - fcsr: Floating-point control/status register (frm + fflags) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ad0e5de789d6390f750b8af03cdd15450" name="ac065a8cc32eed9a69ea1798492a69f49ad0e5de789d6390f750b8af03cdd15450"></a>CSR_MSTATUS&#160;</td><td class="fielddoc"><p>0x300 - mstatus: Machine status register (<a class="el" href="#a76b70a2334131e7589d84c1ee96de485">NEORV32_CSR_MSTATUS_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ade079242596ce14ce1ba9842ed29b84c" name="ac065a8cc32eed9a69ea1798492a69f49ade079242596ce14ce1ba9842ed29b84c"></a>CSR_MISA&#160;</td><td class="fielddoc"><p>0x301 - misa: Machine ISA and extensions (<a class="el" href="#afed7f00bbb39468f038d9ca6fbac830c">NEORV32_CSR_MISA_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49acc0f9f5f3b5702f1b57f2ba3b6b62610" name="ac065a8cc32eed9a69ea1798492a69f49acc0f9f5f3b5702f1b57f2ba3b6b62610"></a>CSR_MIE&#160;</td><td class="fielddoc"><p>0x304 - mie: Machine interrupt-enable register (<a class="el" href="#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49aa632d218400268df6dc6b289ff088d21" name="ac065a8cc32eed9a69ea1798492a69f49aa632d218400268df6dc6b289ff088d21"></a>CSR_MTVEC&#160;</td><td class="fielddoc"><p>0x305 - mtvec: Machine trap-handler base address </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a1860dd9579906c67a3565063043dcf78" name="ac065a8cc32eed9a69ea1798492a69f49a1860dd9579906c67a3565063043dcf78"></a>CSR_MCOUNTEREN&#160;</td><td class="fielddoc"><p>0x305 - mcounteren: Machine counter enable register (<a class="el" href="#a6d3c6aaee79b679e954c54563d7ee500">NEORV32_CSR_MCOUNTEREN_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ac2541060307369b2031e9ec07bbd0067" name="ac065a8cc32eed9a69ea1798492a69f49ac2541060307369b2031e9ec07bbd0067"></a>CSR_MSTATUSH&#160;</td><td class="fielddoc"><p>0x310 - mstatush: Machine status register - high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a3ce1dc0e2810f0df78feaa1c607a5ca6" name="ac065a8cc32eed9a69ea1798492a69f49a3ce1dc0e2810f0df78feaa1c607a5ca6"></a>CSR_MCOUNTINHIBIT&#160;</td><td class="fielddoc"><p>0x320 - mcountinhibit: Machine counter-inhibit register (<a class="el" href="#ab6886ca6858d57854495986ef9b5cbfe">NEORV32_CSR_MCOUNTINHIBIT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a9c55619ffb05e84b7210e2d47326fa98" name="ac065a8cc32eed9a69ea1798492a69f49a9c55619ffb05e84b7210e2d47326fa98"></a>CSR_MENVCFG&#160;</td><td class="fielddoc"><p>0x30a - menvcfg: Machine environment configuration register - low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a46b8d3c288cbbfbf5a0af6e5cd8c5bc8" name="ac065a8cc32eed9a69ea1798492a69f49a46b8d3c288cbbfbf5a0af6e5cd8c5bc8"></a>CSR_MENVCFGH&#160;</td><td class="fielddoc"><p>0x31a - menvcfgh: Machine environment configuration register - high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a4a93ac5ab276cfd2f9cd296c8ce1bff6" name="ac065a8cc32eed9a69ea1798492a69f49a4a93ac5ab276cfd2f9cd296c8ce1bff6"></a>CSR_MHPMEVENT3&#160;</td><td class="fielddoc"><p>0x323 - mhpmevent3: Machine hardware performance monitor event selector 3 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ab5f998725e002ffc2ff516ee973fe459" name="ac065a8cc32eed9a69ea1798492a69f49ab5f998725e002ffc2ff516ee973fe459"></a>CSR_MHPMEVENT4&#160;</td><td class="fielddoc"><p>0x324 - mhpmevent4: Machine hardware performance monitor event selector 4 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a2524659ca2785af51af7acf9cd560a9d" name="ac065a8cc32eed9a69ea1798492a69f49a2524659ca2785af51af7acf9cd560a9d"></a>CSR_MHPMEVENT5&#160;</td><td class="fielddoc"><p>0x325 - mhpmevent5: Machine hardware performance monitor event selector 5 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a1cfa1e3bc3c8a1c9a86c251a510d11cd" name="ac065a8cc32eed9a69ea1798492a69f49a1cfa1e3bc3c8a1c9a86c251a510d11cd"></a>CSR_MHPMEVENT6&#160;</td><td class="fielddoc"><p>0x326 - mhpmevent6: Machine hardware performance monitor event selector 6 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a2e53e6e01ca8d1b801f6dfba602f3f59" name="ac065a8cc32eed9a69ea1798492a69f49a2e53e6e01ca8d1b801f6dfba602f3f59"></a>CSR_MHPMEVENT7&#160;</td><td class="fielddoc"><p>0x327 - mhpmevent7: Machine hardware performance monitor event selector 7 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ad6296ca83bbe1280624f3c21adbd8a79" name="ac065a8cc32eed9a69ea1798492a69f49ad6296ca83bbe1280624f3c21adbd8a79"></a>CSR_MHPMEVENT8&#160;</td><td class="fielddoc"><p>0x328 - mhpmevent8: Machine hardware performance monitor event selector 8 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af6727a9bdd60ccf020812095b7396632" name="ac065a8cc32eed9a69ea1798492a69f49af6727a9bdd60ccf020812095b7396632"></a>CSR_MHPMEVENT9&#160;</td><td class="fielddoc"><p>0x329 - mhpmevent9: Machine hardware performance monitor event selector 9 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a23850b1804966cde2c1e84cde752d512" name="ac065a8cc32eed9a69ea1798492a69f49a23850b1804966cde2c1e84cde752d512"></a>CSR_MHPMEVENT10&#160;</td><td class="fielddoc"><p>0x32a - mhpmevent10: Machine hardware performance monitor event selector 10 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a7fb1de2019dd2b548084d5ca1630efbf" name="ac065a8cc32eed9a69ea1798492a69f49a7fb1de2019dd2b548084d5ca1630efbf"></a>CSR_MHPMEVENT11&#160;</td><td class="fielddoc"><p>0x32b - mhpmevent11: Machine hardware performance monitor event selector 11 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ad648b5ece209d47e9484fd7aa83e8e5f" name="ac065a8cc32eed9a69ea1798492a69f49ad648b5ece209d47e9484fd7aa83e8e5f"></a>CSR_MHPMEVENT12&#160;</td><td class="fielddoc"><p>0x32c - mhpmevent12: Machine hardware performance monitor event selector 12 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a8c31899b81bb5dba9b92a0f0ca71aea6" name="ac065a8cc32eed9a69ea1798492a69f49a8c31899b81bb5dba9b92a0f0ca71aea6"></a>CSR_MHPMEVENT13&#160;</td><td class="fielddoc"><p>0x32d - mhpmevent13: Machine hardware performance monitor event selector 13 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a964a6a50d0138447fad47e9c982a7ba4" name="ac065a8cc32eed9a69ea1798492a69f49a964a6a50d0138447fad47e9c982a7ba4"></a>CSR_MHPMEVENT14&#160;</td><td class="fielddoc"><p>0x32e - mhpmevent14: Machine hardware performance monitor event selector 14 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a06dfdeed757606529e4a99c033691b54" name="ac065a8cc32eed9a69ea1798492a69f49a06dfdeed757606529e4a99c033691b54"></a>CSR_MHPMEVENT15&#160;</td><td class="fielddoc"><p>0x32f - mhpmevent15: Machine hardware performance monitor event selector 15 (<a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ae29976bb072639975ad0cdb985c7f004" name="ac065a8cc32eed9a69ea1798492a69f49ae29976bb072639975ad0cdb985c7f004"></a>CSR_MSCRATCH&#160;</td><td class="fielddoc"><p>0x340 - mscratch: Machine scratch register </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a5d60a25a66754066589e8facb7d41153" name="ac065a8cc32eed9a69ea1798492a69f49a5d60a25a66754066589e8facb7d41153"></a>CSR_MEPC&#160;</td><td class="fielddoc"><p>0x341 - mepc: Machine exception program counter </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a2e14b57fee5376741634db7980a5005b" name="ac065a8cc32eed9a69ea1798492a69f49a2e14b57fee5376741634db7980a5005b"></a>CSR_MCAUSE&#160;</td><td class="fielddoc"><p>0x342 - mcause: Machine trap cause (<a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a76d30359e3b54197fb53f9939734cf1e" name="ac065a8cc32eed9a69ea1798492a69f49a76d30359e3b54197fb53f9939734cf1e"></a>CSR_MTVAL&#160;</td><td class="fielddoc"><p>0x343 - mtval: Machine trap value </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49addb485275c954d1181d5bd4e4609082c" name="ac065a8cc32eed9a69ea1798492a69f49addb485275c954d1181d5bd4e4609082c"></a>CSR_MIP&#160;</td><td class="fielddoc"><p>0x344 - mip: Machine interrupt pending register (<a class="el" href="#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a4f229c169ada239033a1383412ce58c8" name="ac065a8cc32eed9a69ea1798492a69f49a4f229c169ada239033a1383412ce58c8"></a>CSR_MTINST&#160;</td><td class="fielddoc"><p>0x34a - mtinst: Machine trap instruction </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af1a79349e46a4829af78d2cdfd0dc44f" name="ac065a8cc32eed9a69ea1798492a69f49af1a79349e46a4829af78d2cdfd0dc44f"></a>CSR_PMPCFG0&#160;</td><td class="fielddoc"><p>0x3a0 - pmpcfg0: Physical memory protection configuration register 0: regions 0..3 (<a class="el" href="#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a>, <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a22eea318ec1ac72cc14e133b71ef4b16" name="ac065a8cc32eed9a69ea1798492a69f49a22eea318ec1ac72cc14e133b71ef4b16"></a>CSR_PMPCFG1&#160;</td><td class="fielddoc"><p>0x3a1 - pmpcfg1: Physical memory protection configuration register 1: regions 4..7 (<a class="el" href="#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a>, <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a0c9492f6b956f088847f72b28e7b1446" name="ac065a8cc32eed9a69ea1798492a69f49a0c9492f6b956f088847f72b28e7b1446"></a>CSR_PMPCFG2&#160;</td><td class="fielddoc"><p>0x3a2 - pmpcfg2: Physical memory protection configuration register 2: regions 8..11 (<a class="el" href="#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a>, <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a067ed3778590ae97dc9b16069f0ed850" name="ac065a8cc32eed9a69ea1798492a69f49a067ed3778590ae97dc9b16069f0ed850"></a>CSR_PMPCFG3&#160;</td><td class="fielddoc"><p>0x3a3 - pmpcfg3: Physical memory protection configuration register 3: regions 12..15 (<a class="el" href="#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a>, <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a>) </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a8941071db6145d34fff842249c0dcb9f" name="ac065a8cc32eed9a69ea1798492a69f49a8941071db6145d34fff842249c0dcb9f"></a>CSR_PMPADDR0&#160;</td><td class="fielddoc"><p>0x3b0 - pmpaddr0: Physical memory protection address register 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a6a2933f3a1fa243de02db8a795e3ca41" name="ac065a8cc32eed9a69ea1798492a69f49a6a2933f3a1fa243de02db8a795e3ca41"></a>CSR_PMPADDR1&#160;</td><td class="fielddoc"><p>0x3b1 - pmpaddr1: Physical memory protection address register 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49aa0b8c0561e8a778dce9c3b86499ffc50" name="ac065a8cc32eed9a69ea1798492a69f49aa0b8c0561e8a778dce9c3b86499ffc50"></a>CSR_PMPADDR2&#160;</td><td class="fielddoc"><p>0x3b2 - pmpaddr2: Physical memory protection address register 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a89bad989197e9358563557311b3c97e9" name="ac065a8cc32eed9a69ea1798492a69f49a89bad989197e9358563557311b3c97e9"></a>CSR_PMPADDR3&#160;</td><td class="fielddoc"><p>0x3b3 - pmpaddr3: Physical memory protection address register 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ace4529c53ad2d46767f86d920eada507" name="ac065a8cc32eed9a69ea1798492a69f49ace4529c53ad2d46767f86d920eada507"></a>CSR_PMPADDR4&#160;</td><td class="fielddoc"><p>0x3b4 - pmpaddr4: Physical memory protection address register 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ad9e78f71409fd7783cc2ae7c28b5e42c" name="ac065a8cc32eed9a69ea1798492a69f49ad9e78f71409fd7783cc2ae7c28b5e42c"></a>CSR_PMPADDR5&#160;</td><td class="fielddoc"><p>0x3b5 - pmpaddr5: Physical memory protection address register 5 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af57b5b7b57cd6e8b3489a27dfd702444" name="ac065a8cc32eed9a69ea1798492a69f49af57b5b7b57cd6e8b3489a27dfd702444"></a>CSR_PMPADDR6&#160;</td><td class="fielddoc"><p>0x3b6 - pmpaddr6: Physical memory protection address register 6 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ae8ea19cf3e527dbc0d36a43dfd1b7346" name="ac065a8cc32eed9a69ea1798492a69f49ae8ea19cf3e527dbc0d36a43dfd1b7346"></a>CSR_PMPADDR7&#160;</td><td class="fielddoc"><p>0x3b7 - pmpaddr7: Physical memory protection address register 7 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49aec68bf7e26e44170c24599f7c6a8365b" name="ac065a8cc32eed9a69ea1798492a69f49aec68bf7e26e44170c24599f7c6a8365b"></a>CSR_PMPADDR8&#160;</td><td class="fielddoc"><p>0x3b8 - pmpaddr8: Physical memory protection address register 8 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a54d38c8cf364d886eb7ac64463eedf77" name="ac065a8cc32eed9a69ea1798492a69f49a54d38c8cf364d886eb7ac64463eedf77"></a>CSR_PMPADDR9&#160;</td><td class="fielddoc"><p>0x3b9 - pmpaddr9: Physical memory protection address register 9 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ad97b6fe934a3bed6b02d0c8d81165d60" name="ac065a8cc32eed9a69ea1798492a69f49ad97b6fe934a3bed6b02d0c8d81165d60"></a>CSR_PMPADDR10&#160;</td><td class="fielddoc"><p>0x3ba - pmpaddr10: Physical memory protection address register 10 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a3e5708c0f79cf58ae761b6bb8c2a4383" name="ac065a8cc32eed9a69ea1798492a69f49a3e5708c0f79cf58ae761b6bb8c2a4383"></a>CSR_PMPADDR11&#160;</td><td class="fielddoc"><p>0x3bb - pmpaddr11: Physical memory protection address register 11 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a23026793ee53c8d55d23f63195368a6b" name="ac065a8cc32eed9a69ea1798492a69f49a23026793ee53c8d55d23f63195368a6b"></a>CSR_PMPADDR12&#160;</td><td class="fielddoc"><p>0x3bc - pmpaddr12: Physical memory protection address register 12 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a30879e88b250d3e94d9d9e728ffcc2cc" name="ac065a8cc32eed9a69ea1798492a69f49a30879e88b250d3e94d9d9e728ffcc2cc"></a>CSR_PMPADDR13&#160;</td><td class="fielddoc"><p>0x3bd - pmpaddr13: Physical memory protection address register 13 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a91a8b5008b4e08ab34c1516e21bf0ba8" name="ac065a8cc32eed9a69ea1798492a69f49a91a8b5008b4e08ab34c1516e21bf0ba8"></a>CSR_PMPADDR14&#160;</td><td class="fielddoc"><p>0x3be - pmpaddr14: Physical memory protection address register 14 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a6879b4bf5d2db92d236b9091df4841f2" name="ac065a8cc32eed9a69ea1798492a69f49a6879b4bf5d2db92d236b9091df4841f2"></a>CSR_PMPADDR15&#160;</td><td class="fielddoc"><p>0x3bf - pmpaddr15: Physical memory protection address register 15 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49aaae2f0b2e3f5a31dff933868873f6d5d" name="ac065a8cc32eed9a69ea1798492a69f49aaae2f0b2e3f5a31dff933868873f6d5d"></a>CSR_TSELECT&#160;</td><td class="fielddoc"><p>0x7a0 - tselect: Trigger select </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a80eab0e17f5fe41edde485044674dc57" name="ac065a8cc32eed9a69ea1798492a69f49a80eab0e17f5fe41edde485044674dc57"></a>CSR_TDATA1&#160;</td><td class="fielddoc"><p>0x7a1 - tdata1: Trigger data register 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49acf336638697242b691b691dc56b9aadc" name="ac065a8cc32eed9a69ea1798492a69f49acf336638697242b691b691dc56b9aadc"></a>CSR_TDATA2&#160;</td><td class="fielddoc"><p>0x7a2 - tdata2: Trigger data register 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af67c819c104f7e3ec34f2cbb847cf83b" name="ac065a8cc32eed9a69ea1798492a69f49af67c819c104f7e3ec34f2cbb847cf83b"></a>CSR_TINFO&#160;</td><td class="fielddoc"><p>0x7a4 - tinfo: Trigger info </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a6bb3ba59a25803d6f98faad67609a9a9" name="ac065a8cc32eed9a69ea1798492a69f49a6bb3ba59a25803d6f98faad67609a9a9"></a>CSR_DCSR&#160;</td><td class="fielddoc"><p>0x7b0 - dcsr: Debug status and control register </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af4c98d949d2eb44f2518fdf314344d3b" name="ac065a8cc32eed9a69ea1798492a69f49af4c98d949d2eb44f2518fdf314344d3b"></a>CSR_DPC&#160;</td><td class="fielddoc"><p>0x7b1 - dpc: Debug program counter </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a0f4a1ae740efd80d14d21e90f355e9d7" name="ac065a8cc32eed9a69ea1798492a69f49a0f4a1ae740efd80d14d21e90f355e9d7"></a>CSR_DSCRATCH0&#160;</td><td class="fielddoc"><p>0x7b2 - dscratch0: Debug scratch register </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ae0e9cf0b99b8614ea0b870d38970281f" name="ac065a8cc32eed9a69ea1798492a69f49ae0e9cf0b99b8614ea0b870d38970281f"></a>CSR_CFUREG0&#160;</td><td class="fielddoc"><p>0x800 - cfureg0: custom CFU CSR 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a382304065a6db773f925b80b9447b8a8" name="ac065a8cc32eed9a69ea1798492a69f49a382304065a6db773f925b80b9447b8a8"></a>CSR_CFUREG1&#160;</td><td class="fielddoc"><p>0x801 - cfureg1: custom CFU CSR 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a427d7cf036b49efd46166c01f0504b68" name="ac065a8cc32eed9a69ea1798492a69f49a427d7cf036b49efd46166c01f0504b68"></a>CSR_CFUREG2&#160;</td><td class="fielddoc"><p>0x802 - cfureg2: custom CFU CSR 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49aefefa1cff0cf5d01109486e5a8bebedf" name="ac065a8cc32eed9a69ea1798492a69f49aefefa1cff0cf5d01109486e5a8bebedf"></a>CSR_CFUREG3&#160;</td><td class="fielddoc"><p>0x803 - cfureg3: custom CFU CSR 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a32c22641ed66c6d20902306a2b1fad77" name="ac065a8cc32eed9a69ea1798492a69f49a32c22641ed66c6d20902306a2b1fad77"></a>CSR_MCYCLE&#160;</td><td class="fielddoc"><p>0xb00 - mcycle: Machine cycle counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a98f5e2cf2d5dbb0125a222b0065c86eb" name="ac065a8cc32eed9a69ea1798492a69f49a98f5e2cf2d5dbb0125a222b0065c86eb"></a>CSR_MINSTRET&#160;</td><td class="fielddoc"><p>0xb02 - minstret: Machine instructions-retired counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ae0a96f499dcde474af6ee620fbb1ebdc" name="ac065a8cc32eed9a69ea1798492a69f49ae0a96f499dcde474af6ee620fbb1ebdc"></a>CSR_MHPMCOUNTER3&#160;</td><td class="fielddoc"><p>0xb03 - mhpmcounter3: Machine hardware performance monitor 3 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a9b84bd948dd52a7779b5fd16beddaab9" name="ac065a8cc32eed9a69ea1798492a69f49a9b84bd948dd52a7779b5fd16beddaab9"></a>CSR_MHPMCOUNTER4&#160;</td><td class="fielddoc"><p>0xb04 - mhpmcounter4: Machine hardware performance monitor 4 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af15d389bb8f91c989df488d231666394" name="ac065a8cc32eed9a69ea1798492a69f49af15d389bb8f91c989df488d231666394"></a>CSR_MHPMCOUNTER5&#160;</td><td class="fielddoc"><p>0xb05 - mhpmcounter5: Machine hardware performance monitor 5 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af65b9e99b9cadb3cb8d37f97cdbfeb9d" name="ac065a8cc32eed9a69ea1798492a69f49af65b9e99b9cadb3cb8d37f97cdbfeb9d"></a>CSR_MHPMCOUNTER6&#160;</td><td class="fielddoc"><p>0xb06 - mhpmcounter6: Machine hardware performance monitor 6 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a919f39b0d299feb80403b42a466de444" name="ac065a8cc32eed9a69ea1798492a69f49a919f39b0d299feb80403b42a466de444"></a>CSR_MHPMCOUNTER7&#160;</td><td class="fielddoc"><p>0xb07 - mhpmcounter7: Machine hardware performance monitor 7 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a5a4cde90c547e913bddc719b3ab75e79" name="ac065a8cc32eed9a69ea1798492a69f49a5a4cde90c547e913bddc719b3ab75e79"></a>CSR_MHPMCOUNTER8&#160;</td><td class="fielddoc"><p>0xb08 - mhpmcounter8: Machine hardware performance monitor 8 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a18c2a249f1f7852f42f9e10dc59d46bb" name="ac065a8cc32eed9a69ea1798492a69f49a18c2a249f1f7852f42f9e10dc59d46bb"></a>CSR_MHPMCOUNTER9&#160;</td><td class="fielddoc"><p>0xb09 - mhpmcounter9: Machine hardware performance monitor 9 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a575e5342d8ec304c32dbbe99d6fd6c0f" name="ac065a8cc32eed9a69ea1798492a69f49a575e5342d8ec304c32dbbe99d6fd6c0f"></a>CSR_MHPMCOUNTER10&#160;</td><td class="fielddoc"><p>0xb0a - mhpmcounter10: Machine hardware performance monitor 10 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a8840b3d4f45453fc96813ccb369a68e5" name="ac065a8cc32eed9a69ea1798492a69f49a8840b3d4f45453fc96813ccb369a68e5"></a>CSR_MHPMCOUNTER11&#160;</td><td class="fielddoc"><p>0xb0b - mhpmcounter11: Machine hardware performance monitor 11 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a1328a226d36d23cc81740397bde47a4e" name="ac065a8cc32eed9a69ea1798492a69f49a1328a226d36d23cc81740397bde47a4e"></a>CSR_MHPMCOUNTER12&#160;</td><td class="fielddoc"><p>0xb0c - mhpmcounter12: Machine hardware performance monitor 12 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a9bdd102877ff50d38c86c3d741aeb4b0" name="ac065a8cc32eed9a69ea1798492a69f49a9bdd102877ff50d38c86c3d741aeb4b0"></a>CSR_MHPMCOUNTER13&#160;</td><td class="fielddoc"><p>0xb0d - mhpmcounter13: Machine hardware performance monitor 13 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49adae22d860d8162e15120051951e45229" name="ac065a8cc32eed9a69ea1798492a69f49adae22d860d8162e15120051951e45229"></a>CSR_MHPMCOUNTER14&#160;</td><td class="fielddoc"><p>0xb0e - mhpmcounter14: Machine hardware performance monitor 14 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a20400929087fabba410a098667d2d4ff" name="ac065a8cc32eed9a69ea1798492a69f49a20400929087fabba410a098667d2d4ff"></a>CSR_MHPMCOUNTER15&#160;</td><td class="fielddoc"><p>0xb0f - mhpmcounter15: Machine hardware performance monitor 15 counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a28fcfd06ca1012c19cf053e57689687b" name="ac065a8cc32eed9a69ea1798492a69f49a28fcfd06ca1012c19cf053e57689687b"></a>CSR_MCYCLEH&#160;</td><td class="fielddoc"><p>0xb80 - mcycleh: Machine cycle counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49afffb28b62b9baa127ae3bad919208988" name="ac065a8cc32eed9a69ea1798492a69f49afffb28b62b9baa127ae3bad919208988"></a>CSR_MINSTRETH&#160;</td><td class="fielddoc"><p>0xb82 - minstreth: Machine instructions-retired counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a252980a4da90c1f5c1ef85d164f72f25" name="ac065a8cc32eed9a69ea1798492a69f49a252980a4da90c1f5c1ef85d164f72f25"></a>CSR_MHPMCOUNTER3H&#160;</td><td class="fielddoc"><p>0xb83 - mhpmcounter3 : Machine hardware performance monitor 3 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a2e9cfbf3c2828dd4bd92d2b8a1c99f85" name="ac065a8cc32eed9a69ea1798492a69f49a2e9cfbf3c2828dd4bd92d2b8a1c99f85"></a>CSR_MHPMCOUNTER4H&#160;</td><td class="fielddoc"><p>0xb84 - mhpmcounter4h: Machine hardware performance monitor 4 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a7648dd0a47007d44a14e95ba47726599" name="ac065a8cc32eed9a69ea1798492a69f49a7648dd0a47007d44a14e95ba47726599"></a>CSR_MHPMCOUNTER5H&#160;</td><td class="fielddoc"><p>0xb85 - mhpmcounter5h: Machine hardware performance monitor 5 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a49b7bc2df67a6c73a68757de9b218f77" name="ac065a8cc32eed9a69ea1798492a69f49a49b7bc2df67a6c73a68757de9b218f77"></a>CSR_MHPMCOUNTER6H&#160;</td><td class="fielddoc"><p>0xb86 - mhpmcounter6h: Machine hardware performance monitor 6 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ac0183bb6f357ed33136493ae7ded987a" name="ac065a8cc32eed9a69ea1798492a69f49ac0183bb6f357ed33136493ae7ded987a"></a>CSR_MHPMCOUNTER7H&#160;</td><td class="fielddoc"><p>0xb87 - mhpmcounter7h: Machine hardware performance monitor 7 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a9e75518df7d14a009e3a0d5588641ddc" name="ac065a8cc32eed9a69ea1798492a69f49a9e75518df7d14a009e3a0d5588641ddc"></a>CSR_MHPMCOUNTER8H&#160;</td><td class="fielddoc"><p>0xb88 - mhpmcounter8h: Machine hardware performance monitor 8 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a7341886c7a4aed6fc7d8677c016a2cb8" name="ac065a8cc32eed9a69ea1798492a69f49a7341886c7a4aed6fc7d8677c016a2cb8"></a>CSR_MHPMCOUNTER9H&#160;</td><td class="fielddoc"><p>0xb89 - mhpmcounter9h: Machine hardware performance monitor 9 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a1e41d2b27d7e8da14871852d81123cfd" name="ac065a8cc32eed9a69ea1798492a69f49a1e41d2b27d7e8da14871852d81123cfd"></a>CSR_MHPMCOUNTER10H&#160;</td><td class="fielddoc"><p>0xb8a - mhpmcounter10h: Machine hardware performance monitor 10 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a7fd76fcfc0d0dd47e112786bea5e4071" name="ac065a8cc32eed9a69ea1798492a69f49a7fd76fcfc0d0dd47e112786bea5e4071"></a>CSR_MHPMCOUNTER11H&#160;</td><td class="fielddoc"><p>0xb8b - mhpmcounter11h: Machine hardware performance monitor 11 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a332ec2b0740f8e899a1b2ec86f7ee9f2" name="ac065a8cc32eed9a69ea1798492a69f49a332ec2b0740f8e899a1b2ec86f7ee9f2"></a>CSR_MHPMCOUNTER12H&#160;</td><td class="fielddoc"><p>0xb8c - mhpmcounter12h: Machine hardware performance monitor 12 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a5de5c5a036dc594a554d37df9ccf657d" name="ac065a8cc32eed9a69ea1798492a69f49a5de5c5a036dc594a554d37df9ccf657d"></a>CSR_MHPMCOUNTER13H&#160;</td><td class="fielddoc"><p>0xb8d - mhpmcounter13h: Machine hardware performance monitor 13 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ac65bab6fd71439600c8fc549171251fa" name="ac065a8cc32eed9a69ea1798492a69f49ac65bab6fd71439600c8fc549171251fa"></a>CSR_MHPMCOUNTER14H&#160;</td><td class="fielddoc"><p>0xb8e - mhpmcounter14h: Machine hardware performance monitor 14 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af609807e2917f73e27e5f27b38a0fa46" name="ac065a8cc32eed9a69ea1798492a69f49af609807e2917f73e27e5f27b38a0fa46"></a>CSR_MHPMCOUNTER15H&#160;</td><td class="fielddoc"><p>0xb8f - mhpmcounter15h: Machine hardware performance monitor 15 counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49aaaf0f6b17a06d5922bcfdb47b382137e" name="ac065a8cc32eed9a69ea1798492a69f49aaaf0f6b17a06d5922bcfdb47b382137e"></a>CSR_CYCLE&#160;</td><td class="fielddoc"><p>0xc00 - cycle: User cycle counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a8144da8cd8691ac54aa0712685865b66" name="ac065a8cc32eed9a69ea1798492a69f49a8144da8cd8691ac54aa0712685865b66"></a>CSR_INSTRET&#160;</td><td class="fielddoc"><p>0xc02 - instret: User instructions-retired counter low word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49aa276bedb7dab28935163397b4879f6db" name="ac065a8cc32eed9a69ea1798492a69f49aa276bedb7dab28935163397b4879f6db"></a>CSR_CYCLEH&#160;</td><td class="fielddoc"><p>0xc80 - cycleh: User cycle counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a9b66978d76260283007d399fc735d153" name="ac065a8cc32eed9a69ea1798492a69f49a9b66978d76260283007d399fc735d153"></a>CSR_INSTRETH&#160;</td><td class="fielddoc"><p>0xc82 - instreth: User instructions-retired counter high word </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49af5c5a21909aaca2b57f9a15f4bac246b" name="ac065a8cc32eed9a69ea1798492a69f49af5c5a21909aaca2b57f9a15f4bac246b"></a>CSR_MVENDORID&#160;</td><td class="fielddoc"><p>0xf11 - mvendorid: Machine vendor ID </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49ad95cb95266533123447ff0e917f890e4" name="ac065a8cc32eed9a69ea1798492a69f49ad95cb95266533123447ff0e917f890e4"></a>CSR_MARCHID&#160;</td><td class="fielddoc"><p>0xf12 - marchid: Machine architecture ID </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a06d39cf0f13d6401dcf426d56149c8cd" name="ac065a8cc32eed9a69ea1798492a69f49a06d39cf0f13d6401dcf426d56149c8cd"></a>CSR_MIMPID&#160;</td><td class="fielddoc"><p>0xf13 - mimpid: Machine implementation ID </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a6ba48e2306ae92f498552e1ea04d6790" name="ac065a8cc32eed9a69ea1798492a69f49a6ba48e2306ae92f498552e1ea04d6790"></a>CSR_MHARTID&#160;</td><td class="fielddoc"><p>0xf14 - mhartid: Machine hardware thread ID </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a0545d0921b3f90d037dbb25bc5fcc2f9" name="ac065a8cc32eed9a69ea1798492a69f49a0545d0921b3f90d037dbb25bc5fcc2f9"></a>CSR_MCONFIGPTR&#160;</td><td class="fielddoc"><p>0xf15 - mconfigptr: Machine configuration pointer register </p> +</td></tr> +<tr><td class="fieldname"><a id="ac065a8cc32eed9a69ea1798492a69f49a396847bcf1634a1602ab117bfb57bdd2" name="ac065a8cc32eed9a69ea1798492a69f49a396847bcf1634a1602ab117bfb57bdd2"></a>CSR_MXISA&#160;</td><td class="fielddoc"><p>0xfc0 - mxisa: Machine extended ISA and extensions (<a class="el" href="#af05490a8af176ab4ba945d327d448387">NEORV32_CSR_XISA_enum</a>) </p> +</td></tr> +</table> + +</div> +</div> +<a id="afde0761e3150d82511136f56179c204b" name="afde0761e3150d82511136f56179c204b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afde0761e3150d82511136f56179c204b">&#9670;&#160;</a></span>NEORV32_CSR_FFLAGS_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#afde0761e3150d82511136f56179c204b">NEORV32_CSR_FFLAGS_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU fflags (fcsr) CSR (r/w): FPU accrued exception flags </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="afde0761e3150d82511136f56179c204ba91a314defd310786a9ed67f7ef2ef5a6" name="afde0761e3150d82511136f56179c204ba91a314defd310786a9ed67f7ef2ef5a6"></a>CSR_FFLAGS_NX&#160;</td><td class="fielddoc"><p>CPU fflags CSR (0): NX - inexact (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="afde0761e3150d82511136f56179c204babc6d405724563844569028f463885819" name="afde0761e3150d82511136f56179c204babc6d405724563844569028f463885819"></a>CSR_FFLAGS_UF&#160;</td><td class="fielddoc"><p>CPU fflags CSR (1): UF - underflow (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="afde0761e3150d82511136f56179c204ba612390e07a065fa13eeaeac84af48c6e" name="afde0761e3150d82511136f56179c204ba612390e07a065fa13eeaeac84af48c6e"></a>CSR_FFLAGS_OF&#160;</td><td class="fielddoc"><p>CPU fflags CSR (2): OF - overflow (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="afde0761e3150d82511136f56179c204ba365f3f519bca34a349907c82c873d52b" name="afde0761e3150d82511136f56179c204ba365f3f519bca34a349907c82c873d52b"></a>CSR_FFLAGS_DZ&#160;</td><td class="fielddoc"><p>CPU fflags CSR (3): DZ - divide by zero (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="afde0761e3150d82511136f56179c204ba3ac330a4b03178e756c980eaa48ad165" name="afde0761e3150d82511136f56179c204ba3ac330a4b03178e756c980eaa48ad165"></a>CSR_FFLAGS_NV&#160;</td><td class="fielddoc"><p>CPU fflags CSR (4): NV - invalid operation (r/w) </p> +</td></tr> +</table> + +</div> +</div> +<a id="a6d3c6aaee79b679e954c54563d7ee500" name="a6d3c6aaee79b679e954c54563d7ee500"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6d3c6aaee79b679e954c54563d7ee500">&#9670;&#160;</a></span>NEORV32_CSR_MCOUNTEREN_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a6d3c6aaee79b679e954c54563d7ee500">NEORV32_CSR_MCOUNTEREN_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU mcountern CSR (r/w): Machine counter-enable register </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6d3c6aaee79b679e954c54563d7ee500a3d0c8ff6ba2c557cb5b5d353bdb95790" name="a6d3c6aaee79b679e954c54563d7ee500a3d0c8ff6ba2c557cb5b5d353bdb95790"></a>CSR_MCOUNTEREN_CY&#160;</td><td class="fielddoc"><p>CPU mcountern CSR (0): CY - cycle counter (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6d3c6aaee79b679e954c54563d7ee500a97e36c94b71fa2f9a805bbe47b0bc1b5" name="a6d3c6aaee79b679e954c54563d7ee500a97e36c94b71fa2f9a805bbe47b0bc1b5"></a>CSR_MCOUNTEREN_IR&#160;</td><td class="fielddoc"><p>CPU mcountern CSR (2): IR instruction-retired counter (r/w) </p> +</td></tr> +</table> + +</div> +</div> +<a id="ab6886ca6858d57854495986ef9b5cbfe" name="ab6886ca6858d57854495986ef9b5cbfe"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab6886ca6858d57854495986ef9b5cbfe">&#9670;&#160;</a></span>NEORV32_CSR_MCOUNTINHIBIT_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ab6886ca6858d57854495986ef9b5cbfe">NEORV32_CSR_MCOUNTINHIBIT_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU mcountinhibitCSR (r/w): Machine counter-inhibit </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea201ac39b0eba389b0d02c3951a3311a3" name="ab6886ca6858d57854495986ef9b5cbfea201ac39b0eba389b0d02c3951a3311a3"></a>CSR_MCOUNTINHIBIT_CY&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h] CSR when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea5f182f39f9a4b871a097a51e57865bfa" name="ab6886ca6858d57854495986ef9b5cbfea5f182f39f9a4b871a097a51e57865bfa"></a>CSR_MCOUNTINHIBIT_IR&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeaf7020159e0ba346561bfba101d22c752" name="ab6886ca6858d57854495986ef9b5cbfeaf7020159e0ba346561bfba101d22c752"></a>CSR_MCOUNTINHIBIT_HPM3&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (3): HPM3 - Enable auto-increment of hpmcnt3[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea40427b799da049413c5536afa623c61d" name="ab6886ca6858d57854495986ef9b5cbfea40427b799da049413c5536afa623c61d"></a>CSR_MCOUNTINHIBIT_HPM4&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (4): HPM4 - Enable auto-increment of hpmcnt4[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea2769a6e6a75f2f903523e4e95a899bb6" name="ab6886ca6858d57854495986ef9b5cbfea2769a6e6a75f2f903523e4e95a899bb6"></a>CSR_MCOUNTINHIBIT_HPM5&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (5): HPM5 - Enable auto-increment of hpmcnt5[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfead55b6af15841617d7dca3ab4fab893db" name="ab6886ca6858d57854495986ef9b5cbfead55b6af15841617d7dca3ab4fab893db"></a>CSR_MCOUNTINHIBIT_HPM6&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (6): HPM6 - Enable auto-increment of hpmcnt6[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea3b3571fceb687da2d3807b0e59bdf7ab" name="ab6886ca6858d57854495986ef9b5cbfea3b3571fceb687da2d3807b0e59bdf7ab"></a>CSR_MCOUNTINHIBIT_HPM7&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (7): HPM7 - Enable auto-increment of hpmcnt7[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeabd21344124eda4402523203185a58b8a" name="ab6886ca6858d57854495986ef9b5cbfeabd21344124eda4402523203185a58b8a"></a>CSR_MCOUNTINHIBIT_HPM8&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (8): HPM8 - Enable auto-increment of hpmcnt8[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea0f207455df0fed75fa68ba49c435889a" name="ab6886ca6858d57854495986ef9b5cbfea0f207455df0fed75fa68ba49c435889a"></a>CSR_MCOUNTINHIBIT_HPM9&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (9): HPM9 - Enable auto-increment of hpmcnt9[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea9517cd32744c5064fa30780f911cd22e" name="ab6886ca6858d57854495986ef9b5cbfea9517cd32744c5064fa30780f911cd22e"></a>CSR_MCOUNTINHIBIT_HPM10&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (10): HPM10 - Enable auto-increment of hpmcnt10[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeacaf997fe8b912596224e2bb632e6a806" name="ab6886ca6858d57854495986ef9b5cbfeacaf997fe8b912596224e2bb632e6a806"></a>CSR_MCOUNTINHIBIT_HPM11&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (11): HPM11 - Enable auto-increment of hpmcnt11[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea8d866a4c815d8ba890a1e00ce9600486" name="ab6886ca6858d57854495986ef9b5cbfea8d866a4c815d8ba890a1e00ce9600486"></a>CSR_MCOUNTINHIBIT_HPM12&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (12): HPM12 - Enable auto-increment of hpmcnt12[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfead9f6c4eb4284ee82b9e8d0c79f62b3ed" name="ab6886ca6858d57854495986ef9b5cbfead9f6c4eb4284ee82b9e8d0c79f62b3ed"></a>CSR_MCOUNTINHIBIT_HPM13&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (13): HPM13 - Enable auto-increment of hpmcnt13[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeaa83c0688869b1c43de0c4474e940f987" name="ab6886ca6858d57854495986ef9b5cbfeaa83c0688869b1c43de0c4474e940f987"></a>CSR_MCOUNTINHIBIT_HPM14&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (14): HPM14 - Enable auto-increment of hpmcnt14[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea0b547cb5876c0e7956e3d062e0784085" name="ab6886ca6858d57854495986ef9b5cbfea0b547cb5876c0e7956e3d062e0784085"></a>CSR_MCOUNTINHIBIT_HPM15&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (15): HPM15 - Enable auto-increment of hpmcnt15[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea68aba71ea77aba4005fb24a945ef38e4" name="ab6886ca6858d57854495986ef9b5cbfea68aba71ea77aba4005fb24a945ef38e4"></a>CSR_MCOUNTINHIBIT_HPM16&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (16): HPM16 - Enable auto-increment of hpmcnt16[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea8d57acf13a086635a63bc13ccdf479b3" name="ab6886ca6858d57854495986ef9b5cbfea8d57acf13a086635a63bc13ccdf479b3"></a>CSR_MCOUNTINHIBIT_HPM17&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (17): HPM17 - Enable auto-increment of hpmcnt17[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeaa680d196d2ba0e403801a860bb9d8ce0" name="ab6886ca6858d57854495986ef9b5cbfeaa680d196d2ba0e403801a860bb9d8ce0"></a>CSR_MCOUNTINHIBIT_HPM18&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (18): HPM18 - Enable auto-increment of hpmcnt18[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea3683e296caafe771b6dd57f4cf86f3dc" name="ab6886ca6858d57854495986ef9b5cbfea3683e296caafe771b6dd57f4cf86f3dc"></a>CSR_MCOUNTINHIBIT_HPM19&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (19): HPM19 - Enable auto-increment of hpmcnt19[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeaeb4b1b6abafd22eec0764d5503878cca" name="ab6886ca6858d57854495986ef9b5cbfeaeb4b1b6abafd22eec0764d5503878cca"></a>CSR_MCOUNTINHIBIT_HPM20&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (20): HPM20 - Enable auto-increment of hpmcnt20[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea1dc0276a5354c805ac56fd46c5037d38" name="ab6886ca6858d57854495986ef9b5cbfea1dc0276a5354c805ac56fd46c5037d38"></a>CSR_MCOUNTINHIBIT_HPM21&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (21): HPM21 - Enable auto-increment of hpmcnt21[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeaf1b6153a0c664367bfefb78b2ca8b34e" name="ab6886ca6858d57854495986ef9b5cbfeaf1b6153a0c664367bfefb78b2ca8b34e"></a>CSR_MCOUNTINHIBIT_HPM22&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (22): HPM22 - Enable auto-increment of hpmcnt22[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea85c0c2b2a5101380dec72516dda1a904" name="ab6886ca6858d57854495986ef9b5cbfea85c0c2b2a5101380dec72516dda1a904"></a>CSR_MCOUNTINHIBIT_HPM23&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (23): HPM23 - Enable auto-increment of hpmcnt23[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea74ec85a2e94aa0b9e8af29401ef7ecb1" name="ab6886ca6858d57854495986ef9b5cbfea74ec85a2e94aa0b9e8af29401ef7ecb1"></a>CSR_MCOUNTINHIBIT_HPM24&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (24): HPM24 - Enable auto-increment of hpmcnt24[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeaee2b5a2b7bd7ac07dae45900bc2faf46" name="ab6886ca6858d57854495986ef9b5cbfeaee2b5a2b7bd7ac07dae45900bc2faf46"></a>CSR_MCOUNTINHIBIT_HPM25&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (25): HPM25 - Enable auto-increment of hpmcnt25[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea141a4a211c496d2af1c79d8e8e0c2a74" name="ab6886ca6858d57854495986ef9b5cbfea141a4a211c496d2af1c79d8e8e0c2a74"></a>CSR_MCOUNTINHIBIT_HPM26&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (26): HPM26 - Enable auto-increment of hpmcnt26[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea46def851d4582b4bcec1f9d8bafd58db" name="ab6886ca6858d57854495986ef9b5cbfea46def851d4582b4bcec1f9d8bafd58db"></a>CSR_MCOUNTINHIBIT_HPM27&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (27): HPM27 - Enable auto-increment of hpmcnt27[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea33d0fd3378ec3a2fcc3c8738c6cd2f32" name="ab6886ca6858d57854495986ef9b5cbfea33d0fd3378ec3a2fcc3c8738c6cd2f32"></a>CSR_MCOUNTINHIBIT_HPM28&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (28): HPM28 - Enable auto-increment of hpmcnt28[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfeaa39882f7dad9b7e16b317c75bad31382" name="ab6886ca6858d57854495986ef9b5cbfeaa39882f7dad9b7e16b317c75bad31382"></a>CSR_MCOUNTINHIBIT_HPM29&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (29): HPM29 - Enable auto-increment of hpmcnt29[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea0f45818fa4cb9033a3093987fa8515c7" name="ab6886ca6858d57854495986ef9b5cbfea0f45818fa4cb9033a3093987fa8515c7"></a>CSR_MCOUNTINHIBIT_HPM30&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (30): HPM30 - Enable auto-increment of hpmcnt30[h] when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab6886ca6858d57854495986ef9b5cbfea1da1186ef2f4e7297a4fecaaccdc1d05" name="ab6886ca6858d57854495986ef9b5cbfea1da1186ef2f4e7297a4fecaaccdc1d05"></a>CSR_MCOUNTINHIBIT_HPM31&#160;</td><td class="fielddoc"><p>CPU mcountinhibit CSR (31): HPM31 - Enable auto-increment of hpmcnt31[h] when set (r/w) </p> +</td></tr> +</table> + +</div> +</div> +<a id="a0e9714690687badee43180c3cb62be33" name="a0e9714690687badee43180c3cb62be33"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0e9714690687badee43180c3cb62be33">&#9670;&#160;</a></span>NEORV32_CSR_MIE_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU mie CSR (r/w): Machine interrupt enable </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33afd2f1c78c442c8c29ab075cacee0a27a" name="a0e9714690687badee43180c3cb62be33afd2f1c78c442c8c29ab075cacee0a27a"></a>CSR_MIE_MSIE&#160;</td><td class="fielddoc"><p>CPU mie CSR (3): MSIE - Machine software interrupt enable (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a3658e8663e94cd8eaa7201b7a850d083" name="a0e9714690687badee43180c3cb62be33a3658e8663e94cd8eaa7201b7a850d083"></a>CSR_MIE_MTIE&#160;</td><td class="fielddoc"><p>CPU mie CSR (7): MTIE - Machine timer interrupt enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33ae8e4f0ee46abbbb3361de035a57b8324" name="a0e9714690687badee43180c3cb62be33ae8e4f0ee46abbbb3361de035a57b8324"></a>CSR_MIE_MEIE&#160;</td><td class="fielddoc"><p>CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a99f43f8bbfb29fba6224f081c363ac7d" name="a0e9714690687badee43180c3cb62be33a99f43f8bbfb29fba6224f081c363ac7d"></a>CSR_MIE_FIRQ0E&#160;</td><td class="fielddoc"><p>CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33ac1e1d44becec1b393f79a118ed3d8beb" name="a0e9714690687badee43180c3cb62be33ac1e1d44becec1b393f79a118ed3d8beb"></a>CSR_MIE_FIRQ1E&#160;</td><td class="fielddoc"><p>CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33afc805280e20ffface116ca61e11645f7" name="a0e9714690687badee43180c3cb62be33afc805280e20ffface116ca61e11645f7"></a>CSR_MIE_FIRQ2E&#160;</td><td class="fielddoc"><p>CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a666066099d6cebadbef21d81c179e8db" name="a0e9714690687badee43180c3cb62be33a666066099d6cebadbef21d81c179e8db"></a>CSR_MIE_FIRQ3E&#160;</td><td class="fielddoc"><p>CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a592939f1b7d79097f7f13d6ab0c268dc" name="a0e9714690687badee43180c3cb62be33a592939f1b7d79097f7f13d6ab0c268dc"></a>CSR_MIE_FIRQ4E&#160;</td><td class="fielddoc"><p>CPU mie CSR (20): FIRQ4E - Fast interrupt channel 4 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a3079a8fbf3b8e376865bff76f2173698" name="a0e9714690687badee43180c3cb62be33a3079a8fbf3b8e376865bff76f2173698"></a>CSR_MIE_FIRQ5E&#160;</td><td class="fielddoc"><p>CPU mie CSR (21): FIRQ5E - Fast interrupt channel 5 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a96315d6b5b9531bcbc1e78a3c9ab166a" name="a0e9714690687badee43180c3cb62be33a96315d6b5b9531bcbc1e78a3c9ab166a"></a>CSR_MIE_FIRQ6E&#160;</td><td class="fielddoc"><p>CPU mie CSR (22): FIRQ6E - Fast interrupt channel 6 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a3d9d729940170609affbc6813054ebe8" name="a0e9714690687badee43180c3cb62be33a3d9d729940170609affbc6813054ebe8"></a>CSR_MIE_FIRQ7E&#160;</td><td class="fielddoc"><p>CPU mie CSR (23): FIRQ7E - Fast interrupt channel 7 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a396c6c4b425b3fff598e2f846052f98e" name="a0e9714690687badee43180c3cb62be33a396c6c4b425b3fff598e2f846052f98e"></a>CSR_MIE_FIRQ8E&#160;</td><td class="fielddoc"><p>CPU mie CSR (24): FIRQ8E - Fast interrupt channel 8 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a06fdb61dab31c3490da6c37d47914f19" name="a0e9714690687badee43180c3cb62be33a06fdb61dab31c3490da6c37d47914f19"></a>CSR_MIE_FIRQ9E&#160;</td><td class="fielddoc"><p>CPU mie CSR (25): FIRQ9E - Fast interrupt channel 9 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33affcb52dc57bb8c0cb1e7d3c1392d544a" name="a0e9714690687badee43180c3cb62be33affcb52dc57bb8c0cb1e7d3c1392d544a"></a>CSR_MIE_FIRQ10E&#160;</td><td class="fielddoc"><p>CPU mie CSR (26): FIRQ10E - Fast interrupt channel 10 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33af058342854a0becd3bcc33877d9244cd" name="a0e9714690687badee43180c3cb62be33af058342854a0becd3bcc33877d9244cd"></a>CSR_MIE_FIRQ11E&#160;</td><td class="fielddoc"><p>CPU mie CSR (27): FIRQ11E - Fast interrupt channel 11 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a41f91a37f7e0c75c783312af6a72e943" name="a0e9714690687badee43180c3cb62be33a41f91a37f7e0c75c783312af6a72e943"></a>CSR_MIE_FIRQ12E&#160;</td><td class="fielddoc"><p>CPU mie CSR (28): FIRQ12E - Fast interrupt channel 12 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a134ed02c7293008b21b1df472be8f11f" name="a0e9714690687badee43180c3cb62be33a134ed02c7293008b21b1df472be8f11f"></a>CSR_MIE_FIRQ13E&#160;</td><td class="fielddoc"><p>CPU mie CSR (29): FIRQ13E - Fast interrupt channel 13 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33a864d135708530016cfc52a65a1e4d79b" name="a0e9714690687badee43180c3cb62be33a864d135708530016cfc52a65a1e4d79b"></a>CSR_MIE_FIRQ14E&#160;</td><td class="fielddoc"><p>CPU mie CSR (30): FIRQ14E - Fast interrupt channel 14 enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a0e9714690687badee43180c3cb62be33aa2dfa1183af312de2959dadd217fddc1" name="a0e9714690687badee43180c3cb62be33aa2dfa1183af312de2959dadd217fddc1"></a>CSR_MIE_FIRQ15E&#160;</td><td class="fielddoc"><p>CPU mie CSR (31): FIRQ15E - Fast interrupt channel 15 enable bit (r/w) </p> +</td></tr> +</table> + +</div> +</div> +<a id="a6301c554bf831b97fc28f9984a1ec21b" name="a6301c554bf831b97fc28f9984a1ec21b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6301c554bf831b97fc28f9984a1ec21b">&#9670;&#160;</a></span>NEORV32_CSR_MIP_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU mip CSR (r/-): Machine interrupt pending </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba1470cfe04f9d3ce45b7156b2a7fae159" name="a6301c554bf831b97fc28f9984a1ec21ba1470cfe04f9d3ce45b7156b2a7fae159"></a>CSR_MIP_MSIP&#160;</td><td class="fielddoc"><p>CPU mip CSR (3): MSIP - Machine software interrupt pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba344943c62922561378d33ec51ac236e4" name="a6301c554bf831b97fc28f9984a1ec21ba344943c62922561378d33ec51ac236e4"></a>CSR_MIP_MTIP&#160;</td><td class="fielddoc"><p>CPU mip CSR (7): MTIP - Machine timer interrupt pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba1d761ef98f88c40509168ac66b7a4872" name="a6301c554bf831b97fc28f9984a1ec21ba1d761ef98f88c40509168ac66b7a4872"></a>CSR_MIP_MEIP&#160;</td><td class="fielddoc"><p>CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba28a85ad8bd4c30fd3a91298dfa4fdb00" name="a6301c554bf831b97fc28f9984a1ec21ba28a85ad8bd4c30fd3a91298dfa4fdb00"></a>CSR_MIP_FIRQ0P&#160;</td><td class="fielddoc"><p>CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba2b577b1da1074c29ad58005af1f91d52" name="a6301c554bf831b97fc28f9984a1ec21ba2b577b1da1074c29ad58005af1f91d52"></a>CSR_MIP_FIRQ1P&#160;</td><td class="fielddoc"><p>CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21badf45c5a135431f958fa63574c1dfac6e" name="a6301c554bf831b97fc28f9984a1ec21badf45c5a135431f958fa63574c1dfac6e"></a>CSR_MIP_FIRQ2P&#160;</td><td class="fielddoc"><p>CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba7512bb6c4841ddd477422b49ebb2a155" name="a6301c554bf831b97fc28f9984a1ec21ba7512bb6c4841ddd477422b49ebb2a155"></a>CSR_MIP_FIRQ3P&#160;</td><td class="fielddoc"><p>CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21bab6421f242bb8a487a986346e11196eb8" name="a6301c554bf831b97fc28f9984a1ec21bab6421f242bb8a487a986346e11196eb8"></a>CSR_MIP_FIRQ4P&#160;</td><td class="fielddoc"><p>CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21baaa55d19f9a47889bc364c94bda04b677" name="a6301c554bf831b97fc28f9984a1ec21baaa55d19f9a47889bc364c94bda04b677"></a>CSR_MIP_FIRQ5P&#160;</td><td class="fielddoc"><p>CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21baffa7342631aa0526aaa44c0c549b1f3e" name="a6301c554bf831b97fc28f9984a1ec21baffa7342631aa0526aaa44c0c549b1f3e"></a>CSR_MIP_FIRQ6P&#160;</td><td class="fielddoc"><p>CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21baad691486001a68f2375dcf5793ee795a" name="a6301c554bf831b97fc28f9984a1ec21baad691486001a68f2375dcf5793ee795a"></a>CSR_MIP_FIRQ7P&#160;</td><td class="fielddoc"><p>CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21baf5bbd23d4f311f640db42e9015f87580" name="a6301c554bf831b97fc28f9984a1ec21baf5bbd23d4f311f640db42e9015f87580"></a>CSR_MIP_FIRQ8P&#160;</td><td class="fielddoc"><p>CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21bad94c9691ce59b97fcfec14d345046c3e" name="a6301c554bf831b97fc28f9984a1ec21bad94c9691ce59b97fcfec14d345046c3e"></a>CSR_MIP_FIRQ9P&#160;</td><td class="fielddoc"><p>CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba2b50cfa8be461b088ea8506ce4c741ba" name="a6301c554bf831b97fc28f9984a1ec21ba2b50cfa8be461b088ea8506ce4c741ba"></a>CSR_MIP_FIRQ10P&#160;</td><td class="fielddoc"><p>CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba69ea0d3d76d4cec398f3b96959cc3544" name="a6301c554bf831b97fc28f9984a1ec21ba69ea0d3d76d4cec398f3b96959cc3544"></a>CSR_MIP_FIRQ11P&#160;</td><td class="fielddoc"><p>CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba03edd398920b817150d29107c0b40792" name="a6301c554bf831b97fc28f9984a1ec21ba03edd398920b817150d29107c0b40792"></a>CSR_MIP_FIRQ12P&#160;</td><td class="fielddoc"><p>CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba14da6a2a962bf82970638a948ffbc570" name="a6301c554bf831b97fc28f9984a1ec21ba14da6a2a962bf82970638a948ffbc570"></a>CSR_MIP_FIRQ13P&#160;</td><td class="fielddoc"><p>CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21baad1e5e452a9c37561308765431f0260d" name="a6301c554bf831b97fc28f9984a1ec21baad1e5e452a9c37561308765431f0260d"></a>CSR_MIP_FIRQ14P&#160;</td><td class="fielddoc"><p>CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6301c554bf831b97fc28f9984a1ec21ba12da8c32d38d5a3539a0b766718bfd2d" name="a6301c554bf831b97fc28f9984a1ec21ba12da8c32d38d5a3539a0b766718bfd2d"></a>CSR_MIP_FIRQ15P&#160;</td><td class="fielddoc"><p>CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/-) </p> +</td></tr> +</table> + +</div> +</div> +<a id="afed7f00bbb39468f038d9ca6fbac830c" name="afed7f00bbb39468f038d9ca6fbac830c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afed7f00bbb39468f038d9ca6fbac830c">&#9670;&#160;</a></span>NEORV32_CSR_MISA_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#afed7f00bbb39468f038d9ca6fbac830c">NEORV32_CSR_MISA_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU misa CSR (r/-): Machine instruction set extensions </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830cadd469404a928e012a298773ec46926ad" name="afed7f00bbb39468f038d9ca6fbac830cadd469404a928e012a298773ec46926ad"></a>CSR_MISA_B&#160;</td><td class="fielddoc"><p>CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830ca886699013158c74810598fa2fd6b07fa" name="afed7f00bbb39468f038d9ca6fbac830ca886699013158c74810598fa2fd6b07fa"></a>CSR_MISA_C&#160;</td><td class="fielddoc"><p>CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830ca0ac798fd19cb7dbe1146afecda448fec" name="afed7f00bbb39468f038d9ca6fbac830ca0ac798fd19cb7dbe1146afecda448fec"></a>CSR_MISA_E&#160;</td><td class="fielddoc"><p>CPU misa CSR (4): E: Embedded CPU extension available (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830ca6091fd2c7ae38ad33be68a0fdfa50cca" name="afed7f00bbb39468f038d9ca6fbac830ca6091fd2c7ae38ad33be68a0fdfa50cca"></a>CSR_MISA_I&#160;</td><td class="fielddoc"><p>CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830ca317a631e4598532f5bffe8fb93aff94b" name="afed7f00bbb39468f038d9ca6fbac830ca317a631e4598532f5bffe8fb93aff94b"></a>CSR_MISA_M&#160;</td><td class="fielddoc"><p>CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830cacd9d71e674d3a6d04984b6df706d9deb" name="afed7f00bbb39468f038d9ca6fbac830cacd9d71e674d3a6d04984b6df706d9deb"></a>CSR_MISA_U&#160;</td><td class="fielddoc"><p>CPU misa CSR (20): U: User mode CPU extension available (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830ca0b119a20be29fcae8fecf2a81c60d193" name="afed7f00bbb39468f038d9ca6fbac830ca0b119a20be29fcae8fecf2a81c60d193"></a>CSR_MISA_X&#160;</td><td class="fielddoc"><p>CPU misa CSR (23): X: Non-standard CPU extension available (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830cab5a55e97b8511f42fe68559a38f7f138" name="afed7f00bbb39468f038d9ca6fbac830cab5a55e97b8511f42fe68559a38f7f138"></a>CSR_MISA_MXL_LO&#160;</td><td class="fielddoc"><p>CPU misa CSR (30): MXL.lo: CPU data width (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="afed7f00bbb39468f038d9ca6fbac830cafb3e4b08b87f5c161468a9e58ade12cc" name="afed7f00bbb39468f038d9ca6fbac830cafb3e4b08b87f5c161468a9e58ade12cc"></a>CSR_MISA_MXL_HI&#160;</td><td class="fielddoc"><p>CPU misa CSR (31): MXL.Hi: CPU data width (r/-) </p> +</td></tr> +</table> + +</div> +</div> +<a id="a76b70a2334131e7589d84c1ee96de485" name="a76b70a2334131e7589d84c1ee96de485"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a76b70a2334131e7589d84c1ee96de485">&#9670;&#160;</a></span>NEORV32_CSR_MSTATUS_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a76b70a2334131e7589d84c1ee96de485">NEORV32_CSR_MSTATUS_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU mstatus CSR (r/w): Machine status </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a76b70a2334131e7589d84c1ee96de485ae2603e365b3f1abfb46d53ed6b13dc56" name="a76b70a2334131e7589d84c1ee96de485ae2603e365b3f1abfb46d53ed6b13dc56"></a>CSR_MSTATUS_MIE&#160;</td><td class="fielddoc"><p>CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a76b70a2334131e7589d84c1ee96de485aaa1d482f828ac9cafc40fcfc298bec34" name="a76b70a2334131e7589d84c1ee96de485aaa1d482f828ac9cafc40fcfc298bec34"></a>CSR_MSTATUS_MPIE&#160;</td><td class="fielddoc"><p>CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a76b70a2334131e7589d84c1ee96de485af0ae9aca74144aa7dbdf656f71cc5c97" name="a76b70a2334131e7589d84c1ee96de485af0ae9aca74144aa7dbdf656f71cc5c97"></a>CSR_MSTATUS_MPP_L&#160;</td><td class="fielddoc"><p>CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a76b70a2334131e7589d84c1ee96de485a8067c609c2360cab3bafa3c43e03dbf0" name="a76b70a2334131e7589d84c1ee96de485a8067c609c2360cab3bafa3c43e03dbf0"></a>CSR_MSTATUS_MPP_H&#160;</td><td class="fielddoc"><p>CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a76b70a2334131e7589d84c1ee96de485a75cefdbdef36b7fc248765b27c606a44" name="a76b70a2334131e7589d84c1ee96de485a75cefdbdef36b7fc248765b27c606a44"></a>CSR_MSTATUS_MPRV&#160;</td><td class="fielddoc"><p>CPU mstatus CSR (17): MPRV - Use MPP as effective privilege for M-mode load/stores when set (r/w) </p> +</td></tr> +<tr><td class="fieldname"><a id="a76b70a2334131e7589d84c1ee96de485ac94a070f3fe7962e8c49a81545cacf2d" name="a76b70a2334131e7589d84c1ee96de485ac94a070f3fe7962e8c49a81545cacf2d"></a>CSR_MSTATUS_TW&#160;</td><td class="fielddoc"><p>CPU mstatus CSR (21): TW - Disallow execution of wfi instruction in user mode when set (r/w) </p> +</td></tr> +</table> + +</div> +</div> +<a id="af05490a8af176ab4ba945d327d448387" name="af05490a8af176ab4ba945d327d448387"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af05490a8af176ab4ba945d327d448387">&#9670;&#160;</a></span>NEORV32_CSR_XISA_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#af05490a8af176ab4ba945d327d448387">NEORV32_CSR_XISA_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU mxisa CSR (r/-): Machine <em>extended</em> instruction set extensions (NEORV32-specific) </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387accf1dd12be89e45df1423a5600789f2c" name="af05490a8af176ab4ba945d327d448387accf1dd12be89e45df1423a5600789f2c"></a>CSR_MXISA_ZICSR&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (0): privileged architecture (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a6979d4389ed9f8605d338fc616d29f0e" name="af05490a8af176ab4ba945d327d448387a6979d4389ed9f8605d338fc616d29f0e"></a>CSR_MXISA_ZIFENCEI&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (1): instruction stream sync (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a79b2b4b20e08ad31b50724a7a27fb20f" name="af05490a8af176ab4ba945d327d448387a79b2b4b20e08ad31b50724a7a27fb20f"></a>CSR_MXISA_ZMMUL&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (2): hardware mul/div (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387af422ae3b5caba59e33a29b5d069597e0" name="af05490a8af176ab4ba945d327d448387af422ae3b5caba59e33a29b5d069597e0"></a>CSR_MXISA_ZXCFU&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (3): custom RISC-V instructions (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a31788af612f04bc6b2a2bd15c1fb63c1" name="af05490a8af176ab4ba945d327d448387a31788af612f04bc6b2a2bd15c1fb63c1"></a>CSR_MXISA_ZKT&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (4): data independent execution time (of cryptographic operations) (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a56ec3195d0d27f362f58fadb2e037ed1" name="af05490a8af176ab4ba945d327d448387a56ec3195d0d27f362f58fadb2e037ed1"></a>CSR_MXISA_ZFINX&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (5): FPU using x registers (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387ab1f289cfaa9f54f7831a2abcdf9fca2e" name="af05490a8af176ab4ba945d327d448387ab1f289cfaa9f54f7831a2abcdf9fca2e"></a>CSR_MXISA_ZICOND&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (6): integer conditional operations (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a42a3b78195741af4b6aeeb98cbea46fe" name="af05490a8af176ab4ba945d327d448387a42a3b78195741af4b6aeeb98cbea46fe"></a>CSR_MXISA_ZICNTR&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (7): standard instruction, cycle and time counter CSRs (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a6938948290d86b0ad25923f35d6c86d3" name="af05490a8af176ab4ba945d327d448387a6938948290d86b0ad25923f35d6c86d3"></a>CSR_MXISA_SMPMP&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (8): physical memory protection (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387ac13e6883af3a9da18057462239b9fb34" name="af05490a8af176ab4ba945d327d448387ac13e6883af3a9da18057462239b9fb34"></a>CSR_MXISA_ZIHPM&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (9): hardware performance monitors (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387ab6aec595e6aa5ce7c98c7806d23d7af5" name="af05490a8af176ab4ba945d327d448387ab6aec595e6aa5ce7c98c7806d23d7af5"></a>CSR_MXISA_SDEXT&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (10): RISC-V debug mode (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a59eae4272528f589f299ef9cce45af5b" name="af05490a8af176ab4ba945d327d448387a59eae4272528f589f299ef9cce45af5b"></a>CSR_MXISA_SDTRIG&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (11): RISC-V trigger module (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a34519a66e749d63dc5bc7c145c297b64" name="af05490a8af176ab4ba945d327d448387a34519a66e749d63dc5bc7c145c297b64"></a>CSR_MXISA_ZBKX&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (12): scalar cryptography - crossbar permutation (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a48f1de7f79a0633644ae02c463d49375" name="af05490a8af176ab4ba945d327d448387a48f1de7f79a0633644ae02c463d49375"></a>CSR_MXISA_ZKND&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (13): scalar cryptography - NIST AES decryption (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a216ec44d5be3b158acb7e033e352bad1" name="af05490a8af176ab4ba945d327d448387a216ec44d5be3b158acb7e033e352bad1"></a>CSR_MXISA_ZKNE&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (14): scalar cryptography - NIST AES encryption (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a5fe8e591901e0fd7ba6706c70e9c76ec" name="af05490a8af176ab4ba945d327d448387a5fe8e591901e0fd7ba6706c70e9c76ec"></a>CSR_MXISA_ZKNH&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (15): scalar cryptography - NIST hash functions (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387adb26c1e5bf6ae112625621dddd331735" name="af05490a8af176ab4ba945d327d448387adb26c1e5bf6ae112625621dddd331735"></a>CSR_MXISA_ZBKB&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (16): scalar cryptography - bit manipulation instructions (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387ac9e87153c096d656b40cb7abdf3afd55" name="af05490a8af176ab4ba945d327d448387ac9e87153c096d656b40cb7abdf3afd55"></a>CSR_MXISA_ZBKC&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (17): scalar cryptography - carry-less multiplication instructions (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387ad7e7454a30c82c3d91acbc8c259e8c25" name="af05490a8af176ab4ba945d327d448387ad7e7454a30c82c3d91acbc8c259e8c25"></a>CSR_MXISA_ZKN&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (18): scalar cryptography - NIST algorithm suite (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a5e4bf05830b66410bbf2ef2c68e5fd18" name="af05490a8af176ab4ba945d327d448387a5e4bf05830b66410bbf2ef2c68e5fd18"></a>CSR_MXISA_ZKSH&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (19): scalar cryptography - ShangMi hash functions (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a43213190abb77304a78c15196c90a044" name="af05490a8af176ab4ba945d327d448387a43213190abb77304a78c15196c90a044"></a>CSR_MXISA_ZKSED&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (20): scalar cryptography - ShangMi block cyphers (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a2649bee3397c74ada7b72677308f38c0" name="af05490a8af176ab4ba945d327d448387a2649bee3397c74ada7b72677308f38c0"></a>CSR_MXISA_ZKS&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (21): scalar cryptography - ShangMi algorithm suite (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387adfc9122d93a71bf6df178022a52d22c4" name="af05490a8af176ab4ba945d327d448387adfc9122d93a71bf6df178022a52d22c4"></a>CSR_MXISA_ZBA&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (22): shifted-add bit-manipulation operations (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a815cbe0149cba2a69025f6bec9946a85" name="af05490a8af176ab4ba945d327d448387a815cbe0149cba2a69025f6bec9946a85"></a>CSR_MXISA_ZBB&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (23): basic bit-manipulation operations (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a469e8e449f0e442df531c8cf2c4f35c5" name="af05490a8af176ab4ba945d327d448387a469e8e449f0e442df531c8cf2c4f35c5"></a>CSR_MXISA_ZBS&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (24): single-bit bit-manipulation operations (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387adf45adc0bcbec0c1ffa944099257a947" name="af05490a8af176ab4ba945d327d448387adf45adc0bcbec0c1ffa944099257a947"></a>CSR_MXISA_ZALRSC&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (25): atomic reservation-set operations (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a6843c660d75f33e4252c7fccd4565a2d" name="af05490a8af176ab4ba945d327d448387a6843c660d75f33e4252c7fccd4565a2d"></a>CSR_MXISA_RFHWRST&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (28): register file has full hardware reset (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a48e57689f8a5b51d9ee9d648da7efc64" name="af05490a8af176ab4ba945d327d448387a48e57689f8a5b51d9ee9d648da7efc64"></a>CSR_MXISA_FASTMUL&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (29): DSP-based multiplication (M extensions only) (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387ad5ac9e2188757e6c42c159f0c5887868" name="af05490a8af176ab4ba945d327d448387ad5ac9e2188757e6c42c159f0c5887868"></a>CSR_MXISA_FASTSHIFT&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (30): parallel logic for shifts (barrel shifters) (r/-) </p> +</td></tr> +<tr><td class="fieldname"><a id="af05490a8af176ab4ba945d327d448387a9b121ec0ad6271b6e07658f861015f6a" name="af05490a8af176ab4ba945d327d448387a9b121ec0ad6271b6e07658f861015f6a"></a>CSR_MXISA_IS_SIM&#160;</td><td class="fielddoc"><p>CPU mxisa CSR (31): this might be a simulation when set (r/-) </p> +</td></tr> +</table> + +</div> +</div> +<a id="acb0fcbc551fec4c45676ff1317be24e1" name="acb0fcbc551fec4c45676ff1317be24e1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acb0fcbc551fec4c45676ff1317be24e1">&#9670;&#160;</a></span>NEORV32_EXCEPTION_CODES_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Trap codes from mcause CSR. </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a0a8010d7cc91b9557973a7a118828bee" name="acb0fcbc551fec4c45676ff1317be24e1a0a8010d7cc91b9557973a7a118828bee"></a>TRAP_CODE_I_MISALIGNED&#160;</td><td class="fielddoc"><p>0.0: Instruction address misaligned </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a6a0ebfce4e18f36aeb43d5a65445cfe1" name="acb0fcbc551fec4c45676ff1317be24e1a6a0ebfce4e18f36aeb43d5a65445cfe1"></a>TRAP_CODE_I_ACCESS&#160;</td><td class="fielddoc"><p>0.1: Instruction (bus) access fault </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1af1ad8f557f3b685b59a913611e1da173" name="acb0fcbc551fec4c45676ff1317be24e1af1ad8f557f3b685b59a913611e1da173"></a>TRAP_CODE_I_ILLEGAL&#160;</td><td class="fielddoc"><p>0.2: Illegal instruction </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a2c9510cb7583a0144f96678fc217335e" name="acb0fcbc551fec4c45676ff1317be24e1a2c9510cb7583a0144f96678fc217335e"></a>TRAP_CODE_BREAKPOINT&#160;</td><td class="fielddoc"><p>0.3: Breakpoint (EBREAK instruction) </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a69e68a954da0bb33d1624484a6777ff9" name="acb0fcbc551fec4c45676ff1317be24e1a69e68a954da0bb33d1624484a6777ff9"></a>TRAP_CODE_L_MISALIGNED&#160;</td><td class="fielddoc"><p>0.4: Load address misaligned </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a28448f0c670169140dc28b6794310cea" name="acb0fcbc551fec4c45676ff1317be24e1a28448f0c670169140dc28b6794310cea"></a>TRAP_CODE_L_ACCESS&#160;</td><td class="fielddoc"><p>0.5: Load (bus) access fault </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a19708405f9f6300edf6b992c6d408a2d" name="acb0fcbc551fec4c45676ff1317be24e1a19708405f9f6300edf6b992c6d408a2d"></a>TRAP_CODE_S_MISALIGNED&#160;</td><td class="fielddoc"><p>0.6: Store address misaligned </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a70bcfc75fe1056d93a3606f78c0cb887" name="acb0fcbc551fec4c45676ff1317be24e1a70bcfc75fe1056d93a3606f78c0cb887"></a>TRAP_CODE_S_ACCESS&#160;</td><td class="fielddoc"><p>0.7: Store (bus) access fault </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1aa102472d6a264bb92e0581ccaa413e02" name="acb0fcbc551fec4c45676ff1317be24e1aa102472d6a264bb92e0581ccaa413e02"></a>TRAP_CODE_UENV_CALL&#160;</td><td class="fielddoc"><p>0.8: Environment call from user mode (ECALL instruction) </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a20e5a2680f2f5956bfa92852d5544eac" name="acb0fcbc551fec4c45676ff1317be24e1a20e5a2680f2f5956bfa92852d5544eac"></a>TRAP_CODE_MENV_CALL&#160;</td><td class="fielddoc"><p>0.11: Environment call from machine mode (ECALL instruction) </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1ae0cebf99f36ef6be60e4a9d2c9f894b0" name="acb0fcbc551fec4c45676ff1317be24e1ae0cebf99f36ef6be60e4a9d2c9f894b0"></a>TRAP_CODE_MSI&#160;</td><td class="fielddoc"><p>1.3: Machine software interrupt </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a187ae38819b81672c15808e63c3b46b7" name="acb0fcbc551fec4c45676ff1317be24e1a187ae38819b81672c15808e63c3b46b7"></a>TRAP_CODE_MTI&#160;</td><td class="fielddoc"><p>1.7: Machine timer interrupt </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a1a412b9d8eefba7880555d34625d2cc0" name="acb0fcbc551fec4c45676ff1317be24e1a1a412b9d8eefba7880555d34625d2cc0"></a>TRAP_CODE_MEI&#160;</td><td class="fielddoc"><p>1.11: Machine external interrupt </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a0cef77904935798d247d8396838297c1" name="acb0fcbc551fec4c45676ff1317be24e1a0cef77904935798d247d8396838297c1"></a>TRAP_CODE_FIRQ_0&#160;</td><td class="fielddoc"><p>1.16: Fast interrupt channel 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1ae0b1049ae7f8cbfb6ff216e69ed5dae7" name="acb0fcbc551fec4c45676ff1317be24e1ae0b1049ae7f8cbfb6ff216e69ed5dae7"></a>TRAP_CODE_FIRQ_1&#160;</td><td class="fielddoc"><p>1.17: Fast interrupt channel 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1ad753d3e2563b4fd663430af9f3888dc7" name="acb0fcbc551fec4c45676ff1317be24e1ad753d3e2563b4fd663430af9f3888dc7"></a>TRAP_CODE_FIRQ_2&#160;</td><td class="fielddoc"><p>1.18: Fast interrupt channel 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a356f8485166529503d0fb246bd0aeeb0" name="acb0fcbc551fec4c45676ff1317be24e1a356f8485166529503d0fb246bd0aeeb0"></a>TRAP_CODE_FIRQ_3&#160;</td><td class="fielddoc"><p>1.19: Fast interrupt channel 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1aaa8e7bb251852ef75a78be71eef0b547" name="acb0fcbc551fec4c45676ff1317be24e1aaa8e7bb251852ef75a78be71eef0b547"></a>TRAP_CODE_FIRQ_4&#160;</td><td class="fielddoc"><p>1.20: Fast interrupt channel 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a5789dfabd8ec265fa0734ddd94e98757" name="acb0fcbc551fec4c45676ff1317be24e1a5789dfabd8ec265fa0734ddd94e98757"></a>TRAP_CODE_FIRQ_5&#160;</td><td class="fielddoc"><p>1.21: Fast interrupt channel 5 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a809e997f55e83c6812c965655511d473" name="acb0fcbc551fec4c45676ff1317be24e1a809e997f55e83c6812c965655511d473"></a>TRAP_CODE_FIRQ_6&#160;</td><td class="fielddoc"><p>1.22: Fast interrupt channel 6 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1aeab719bcce9e9551bd6da65a7ae08a26" name="acb0fcbc551fec4c45676ff1317be24e1aeab719bcce9e9551bd6da65a7ae08a26"></a>TRAP_CODE_FIRQ_7&#160;</td><td class="fielddoc"><p>1.23: Fast interrupt channel 7 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1abfd21d1380dcacb9282e525da104d916" name="acb0fcbc551fec4c45676ff1317be24e1abfd21d1380dcacb9282e525da104d916"></a>TRAP_CODE_FIRQ_8&#160;</td><td class="fielddoc"><p>1.24: Fast interrupt channel 8 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a350e762a599479fb2c6d23ccc5ee22b4" name="acb0fcbc551fec4c45676ff1317be24e1a350e762a599479fb2c6d23ccc5ee22b4"></a>TRAP_CODE_FIRQ_9&#160;</td><td class="fielddoc"><p>1.25: Fast interrupt channel 9 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a4f6b9c6bba91fe04becb776ad22dcf42" name="acb0fcbc551fec4c45676ff1317be24e1a4f6b9c6bba91fe04becb776ad22dcf42"></a>TRAP_CODE_FIRQ_10&#160;</td><td class="fielddoc"><p>1.26: Fast interrupt channel 10 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a874dcc43cf8fbbf2e0614e7db9e38334" name="acb0fcbc551fec4c45676ff1317be24e1a874dcc43cf8fbbf2e0614e7db9e38334"></a>TRAP_CODE_FIRQ_11&#160;</td><td class="fielddoc"><p>1.27: Fast interrupt channel 11 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a151f01e5f284f876cafafc7427720e4c" name="acb0fcbc551fec4c45676ff1317be24e1a151f01e5f284f876cafafc7427720e4c"></a>TRAP_CODE_FIRQ_12&#160;</td><td class="fielddoc"><p>1.28: Fast interrupt channel 12 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a7c8e97297cc4dcd6d5a1de65a124f3e9" name="acb0fcbc551fec4c45676ff1317be24e1a7c8e97297cc4dcd6d5a1de65a124f3e9"></a>TRAP_CODE_FIRQ_13&#160;</td><td class="fielddoc"><p>1.29: Fast interrupt channel 13 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1a821f813de47eb781ab7715f780da3b1e" name="acb0fcbc551fec4c45676ff1317be24e1a821f813de47eb781ab7715f780da3b1e"></a>TRAP_CODE_FIRQ_14&#160;</td><td class="fielddoc"><p>1.30: Fast interrupt channel 14 </p> +</td></tr> +<tr><td class="fieldname"><a id="acb0fcbc551fec4c45676ff1317be24e1aa4eeafe2f6f59aff01e29461c664a110" name="acb0fcbc551fec4c45676ff1317be24e1aa4eeafe2f6f59aff01e29461c664a110"></a>TRAP_CODE_FIRQ_15&#160;</td><td class="fielddoc"><p>1.31: Fast interrupt channel 15 </p> +</td></tr> +</table> + +</div> +</div> +<a id="a5cb925a3e41efd5e767bb39b3ee60cfe" name="a5cb925a3e41efd5e767bb39b3ee60cfe"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5cb925a3e41efd5e767bb39b3ee60cfe">&#9670;&#160;</a></span>NEORV32_HPMCNT_EVENT_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU mhpmevent hardware performance monitor events </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea2b683572525adc02ce0910031cfea914" name="a5cb925a3e41efd5e767bb39b3ee60cfea2b683572525adc02ce0910031cfea914"></a>HPMCNT_EVENT_CY&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (0): Active cycle </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea578ef6fc107c22b5cb7be5950f695640" name="a5cb925a3e41efd5e767bb39b3ee60cfea578ef6fc107c22b5cb7be5950f695640"></a>HPMCNT_EVENT_TM&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (1): Reserved </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfeaab438295e5f00ffe4c2457a54ee9bfc4" name="a5cb925a3e41efd5e767bb39b3ee60cfeaab438295e5f00ffe4c2457a54ee9bfc4"></a>HPMCNT_EVENT_IR&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (2): Retired instruction </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea685ed663611d988702ec59c254eb61dd" name="a5cb925a3e41efd5e767bb39b3ee60cfea685ed663611d988702ec59c254eb61dd"></a>HPMCNT_EVENT_COMPR&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (3): Executed compressed instruction </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfeabcb123b5b150b4413e5fd48475faab27" name="a5cb925a3e41efd5e767bb39b3ee60cfeabcb123b5b150b4413e5fd48475faab27"></a>HPMCNT_EVENT_WAIT_DIS&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (4): Instruction dispatch wait cycle </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfeaffbb04d0053ebd079c6cacb4e5e7ed6b" name="a5cb925a3e41efd5e767bb39b3ee60cfeaffbb04d0053ebd079c6cacb4e5e7ed6b"></a>HPMCNT_EVENT_WAIT_ALU&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (5): Multi-cycle ALU co-processor wait cycle </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea9e1e2b50352b2555e9c64e76776919a6" name="a5cb925a3e41efd5e767bb39b3ee60cfea9e1e2b50352b2555e9c64e76776919a6"></a>HPMCNT_EVENT_BRANCH&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (6): Executed branch instruction </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea0f15c5a824cb1678423ac4ef72a5f4f5" name="a5cb925a3e41efd5e767bb39b3ee60cfea0f15c5a824cb1678423ac4ef72a5f4f5"></a>HPMCNT_EVENT_BRANCHED&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (7): Control flow transfer </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea1a06f216e1a12afa0b90d6e1218b3c91" name="a5cb925a3e41efd5e767bb39b3ee60cfea1a06f216e1a12afa0b90d6e1218b3c91"></a>HPMCNT_EVENT_LOAD&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (8): Executed load operation </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea6a942852e3cd85616a63addb8e9d76f2" name="a5cb925a3e41efd5e767bb39b3ee60cfea6a942852e3cd85616a63addb8e9d76f2"></a>HPMCNT_EVENT_STORE&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (9): Executed store operation </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea67a59934bc66bc7ccf82d24fe8a18a3b" name="a5cb925a3e41efd5e767bb39b3ee60cfea67a59934bc66bc7ccf82d24fe8a18a3b"></a>HPMCNT_EVENT_WAIT_LSU&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (10): Load-store unit memory wait cycle </p> +</td></tr> +<tr><td class="fieldname"><a id="a5cb925a3e41efd5e767bb39b3ee60cfea3a4f5bf9251def87a71162dbcf9043c5" name="a5cb925a3e41efd5e767bb39b3ee60cfea3a4f5bf9251def87a71162dbcf9043c5"></a>HPMCNT_EVENT_TRAP&#160;</td><td class="fielddoc"><p>CPU mhpmevent CSR (11): Entered trap </p> +</td></tr> +</table> + +</div> +</div> +<a id="a8f2418fb5e2175f35ee2362469ce01f5" name="a8f2418fb5e2175f35ee2362469ce01f5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8f2418fb5e2175f35ee2362469ce01f5">&#9670;&#160;</a></span>NEORV32_PMP_MODES_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>PMP modes </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a8f2418fb5e2175f35ee2362469ce01f5a003ccfae4aae1dad4fd65d5d4c7737c4" name="a8f2418fb5e2175f35ee2362469ce01f5a003ccfae4aae1dad4fd65d5d4c7737c4"></a>PMP_OFF&#160;</td><td class="fielddoc"><p>'00': entry disabled </p> +</td></tr> +<tr><td class="fieldname"><a id="a8f2418fb5e2175f35ee2362469ce01f5a629a81a205abee94bad9d5bb5dfa26b1" name="a8f2418fb5e2175f35ee2362469ce01f5a629a81a205abee94bad9d5bb5dfa26b1"></a>PMP_TOR&#160;</td><td class="fielddoc"><p>'01': TOR mode (top of region) </p> +</td></tr> +<tr><td class="fieldname"><a id="a8f2418fb5e2175f35ee2362469ce01f5aae0e0c33b0d034cb50286239f955d892" name="a8f2418fb5e2175f35ee2362469ce01f5aae0e0c33b0d034cb50286239f955d892"></a>PMP_NA4&#160;</td><td class="fielddoc"><p>'10': Naturally-aligned power of two region (4 bytes) </p> +</td></tr> +<tr><td class="fieldname"><a id="a8f2418fb5e2175f35ee2362469ce01f5ad555e9dfc0c00612bdea623617ff2820" name="a8f2418fb5e2175f35ee2362469ce01f5ad555e9dfc0c00612bdea623617ff2820"></a>PMP_NAPOT&#160;</td><td class="fielddoc"><p>'11': Naturally-aligned power of two region (greater than 4 bytes ) </p> +</td></tr> +</table> + +</div> +</div> +<a id="abc0e8daad1e9beda4d9950452cc930ea" name="abc0e8daad1e9beda4d9950452cc930ea"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abc0e8daad1e9beda4d9950452cc930ea">&#9670;&#160;</a></span>NEORV32_PMPCFG_ATTRIBUTES_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU pmpcfg PMP configuration attributes </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="abc0e8daad1e9beda4d9950452cc930eaad3aca82a2ab57364e83f677d3d4f71a6" name="abc0e8daad1e9beda4d9950452cc930eaad3aca82a2ab57364e83f677d3d4f71a6"></a>PMPCFG_R&#160;</td><td class="fielddoc"><p>CPU pmpcfg attribute (0): Read </p> +</td></tr> +<tr><td class="fieldname"><a id="abc0e8daad1e9beda4d9950452cc930eaa7689905760f917499b1151cced384d2f" name="abc0e8daad1e9beda4d9950452cc930eaa7689905760f917499b1151cced384d2f"></a>PMPCFG_W&#160;</td><td class="fielddoc"><p>CPU pmpcfg attribute (1): Write </p> +</td></tr> +<tr><td class="fieldname"><a id="abc0e8daad1e9beda4d9950452cc930eaaec94712deafba09c0cf956c6fd68fa8d" name="abc0e8daad1e9beda4d9950452cc930eaaec94712deafba09c0cf956c6fd68fa8d"></a>PMPCFG_X&#160;</td><td class="fielddoc"><p>CPU pmpcfg attribute (2): Execute </p> +</td></tr> +<tr><td class="fieldname"><a id="abc0e8daad1e9beda4d9950452cc930eaaae1e6440956ad6b7cbf6062aa50f43b1" name="abc0e8daad1e9beda4d9950452cc930eaaae1e6440956ad6b7cbf6062aa50f43b1"></a>PMPCFG_A_LSB&#160;</td><td class="fielddoc"><p>CPU pmpcfg attribute (3): Mode LSB <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a> </p> +</td></tr> +<tr><td class="fieldname"><a id="abc0e8daad1e9beda4d9950452cc930eaa67ad3243eeb74f86a01efbade76f21e4" name="abc0e8daad1e9beda4d9950452cc930eaa67ad3243eeb74f86a01efbade76f21e4"></a>PMPCFG_A_MSB&#160;</td><td class="fielddoc"><p>CPU pmpcfg attribute (4): Mode MSB <a class="el" href="#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a> </p> +</td></tr> +<tr><td class="fieldname"><a id="abc0e8daad1e9beda4d9950452cc930eaa59c294bc43d2117bb55e301eec683f14" name="abc0e8daad1e9beda4d9950452cc930eaa59c294bc43d2117bb55e301eec683f14"></a>PMPCFG_L&#160;</td><td class="fielddoc"><p>CPU pmpcfg attribute (7): Locked </p> +</td></tr> +</table> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__cpu__csr_8h_source.html b/sw/neorv32__cpu__csr_8h_source.html new file mode 100644 index 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class="title">neorv32_cpu_csr.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__cpu__csr_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_cpu_csr_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_cpu_csr_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00025" data-start="{" data-end="};"> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49"> 25</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49">NEORV32_CSR_enum</a> {</div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span> <span class="comment">/* floating-point unit control and status */</span></div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a"> 27</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a">CSR_FFLAGS</a> = 0x001, </div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7f198c465959dde37b7056dd06d45812"> 28</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7f198c465959dde37b7056dd06d45812">CSR_FRM</a> = 0x002, </div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5e1abf46b4f55bd18e1d132b32696ab6"> 29</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5e1abf46b4f55bd18e1d132b32696ab6">CSR_FCSR</a> = 0x003, </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span> <span class="comment">/* machine control and status */</span></div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad0e5de789d6390f750b8af03cdd15450"> 32</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad0e5de789d6390f750b8af03cdd15450">CSR_MSTATUS</a> = 0x300, </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ade079242596ce14ce1ba9842ed29b84c"> 33</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ade079242596ce14ce1ba9842ed29b84c">CSR_MISA</a> = 0x301, </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49acc0f9f5f3b5702f1b57f2ba3b6b62610"> 34</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49acc0f9f5f3b5702f1b57f2ba3b6b62610">CSR_MIE</a> = 0x304, </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa632d218400268df6dc6b289ff088d21"> 35</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa632d218400268df6dc6b289ff088d21">CSR_MTVEC</a> = 0x305, </div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1860dd9579906c67a3565063043dcf78"> 36</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1860dd9579906c67a3565063043dcf78">CSR_MCOUNTEREN</a> = 0x306, </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac2541060307369b2031e9ec07bbd0067"> 37</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac2541060307369b2031e9ec07bbd0067">CSR_MSTATUSH</a> = 0x310, </div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a3ce1dc0e2810f0df78feaa1c607a5ca6"> 38</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a3ce1dc0e2810f0df78feaa1c607a5ca6">CSR_MCOUNTINHIBIT</a> = 0x320, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> <span class="comment">/* machine configuration */</span></div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9c55619ffb05e84b7210e2d47326fa98"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9c55619ffb05e84b7210e2d47326fa98">CSR_MENVCFG</a> = 0x30a, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a46b8d3c288cbbfbf5a0af6e5cd8c5bc8"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a46b8d3c288cbbfbf5a0af6e5cd8c5bc8">CSR_MENVCFGH</a> = 0x31a, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span> <span class="comment">/* hardware performance monitors - event configuration */</span></div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a4a93ac5ab276cfd2f9cd296c8ce1bff6"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a4a93ac5ab276cfd2f9cd296c8ce1bff6">CSR_MHPMEVENT3</a> = 0x323, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ab5f998725e002ffc2ff516ee973fe459"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ab5f998725e002ffc2ff516ee973fe459">CSR_MHPMEVENT4</a> = 0x324, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2524659ca2785af51af7acf9cd560a9d"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2524659ca2785af51af7acf9cd560a9d">CSR_MHPMEVENT5</a> = 0x325, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1cfa1e3bc3c8a1c9a86c251a510d11cd"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1cfa1e3bc3c8a1c9a86c251a510d11cd">CSR_MHPMEVENT6</a> = 0x326, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e53e6e01ca8d1b801f6dfba602f3f59"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e53e6e01ca8d1b801f6dfba602f3f59">CSR_MHPMEVENT7</a> = 0x327, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad6296ca83bbe1280624f3c21adbd8a79"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad6296ca83bbe1280624f3c21adbd8a79">CSR_MHPMEVENT8</a> = 0x328, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af6727a9bdd60ccf020812095b7396632"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af6727a9bdd60ccf020812095b7396632">CSR_MHPMEVENT9</a> = 0x329, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a23850b1804966cde2c1e84cde752d512"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a23850b1804966cde2c1e84cde752d512">CSR_MHPMEVENT10</a> = 0x32a, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7fb1de2019dd2b548084d5ca1630efbf"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7fb1de2019dd2b548084d5ca1630efbf">CSR_MHPMEVENT11</a> = 0x32b, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad648b5ece209d47e9484fd7aa83e8e5f"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad648b5ece209d47e9484fd7aa83e8e5f">CSR_MHPMEVENT12</a> = 0x32c, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8c31899b81bb5dba9b92a0f0ca71aea6"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8c31899b81bb5dba9b92a0f0ca71aea6">CSR_MHPMEVENT13</a> = 0x32d, </div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a964a6a50d0138447fad47e9c982a7ba4"> 56</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a964a6a50d0138447fad47e9c982a7ba4">CSR_MHPMEVENT14</a> = 0x32e, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a06dfdeed757606529e4a99c033691b54"> 57</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a06dfdeed757606529e4a99c033691b54">CSR_MHPMEVENT15</a> = 0x32f, </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> <span class="comment">/* machine trap control */</span></div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae29976bb072639975ad0cdb985c7f004"> 60</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae29976bb072639975ad0cdb985c7f004">CSR_MSCRATCH</a> = 0x340, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5d60a25a66754066589e8facb7d41153"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5d60a25a66754066589e8facb7d41153">CSR_MEPC</a> = 0x341, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e14b57fee5376741634db7980a5005b"> 62</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e14b57fee5376741634db7980a5005b">CSR_MCAUSE</a> = 0x342, </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a76d30359e3b54197fb53f9939734cf1e"> 63</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a76d30359e3b54197fb53f9939734cf1e">CSR_MTVAL</a> = 0x343, </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49addb485275c954d1181d5bd4e4609082c"> 64</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49addb485275c954d1181d5bd4e4609082c">CSR_MIP</a> = 0x344, </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a4f229c169ada239033a1383412ce58c8"> 65</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a4f229c169ada239033a1383412ce58c8">CSR_MTINST</a> = 0x34a, </div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span> <span class="comment">/* physical memory protection */</span></div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af1a79349e46a4829af78d2cdfd0dc44f"> 68</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af1a79349e46a4829af78d2cdfd0dc44f">CSR_PMPCFG0</a> = 0x3a0, </div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a22eea318ec1ac72cc14e133b71ef4b16"> 69</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a22eea318ec1ac72cc14e133b71ef4b16">CSR_PMPCFG1</a> = 0x3a1, </div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0c9492f6b956f088847f72b28e7b1446"> 70</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0c9492f6b956f088847f72b28e7b1446">CSR_PMPCFG2</a> = 0x3a2, </div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a067ed3778590ae97dc9b16069f0ed850"> 71</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a067ed3778590ae97dc9b16069f0ed850">CSR_PMPCFG3</a> = 0x3a3, </div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8941071db6145d34fff842249c0dcb9f"> 73</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8941071db6145d34fff842249c0dcb9f">CSR_PMPADDR0</a> = 0x3b0, </div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6a2933f3a1fa243de02db8a795e3ca41"> 74</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6a2933f3a1fa243de02db8a795e3ca41">CSR_PMPADDR1</a> = 0x3b1, </div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa0b8c0561e8a778dce9c3b86499ffc50"> 75</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa0b8c0561e8a778dce9c3b86499ffc50">CSR_PMPADDR2</a> = 0x3b2, </div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a89bad989197e9358563557311b3c97e9"> 76</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a89bad989197e9358563557311b3c97e9">CSR_PMPADDR3</a> = 0x3b3, </div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ace4529c53ad2d46767f86d920eada507"> 77</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ace4529c53ad2d46767f86d920eada507">CSR_PMPADDR4</a> = 0x3b4, </div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad9e78f71409fd7783cc2ae7c28b5e42c"> 78</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad9e78f71409fd7783cc2ae7c28b5e42c">CSR_PMPADDR5</a> = 0x3b5, </div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af57b5b7b57cd6e8b3489a27dfd702444"> 79</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af57b5b7b57cd6e8b3489a27dfd702444">CSR_PMPADDR6</a> = 0x3b6, </div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae8ea19cf3e527dbc0d36a43dfd1b7346"> 80</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae8ea19cf3e527dbc0d36a43dfd1b7346">CSR_PMPADDR7</a> = 0x3b7, </div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aec68bf7e26e44170c24599f7c6a8365b"> 81</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aec68bf7e26e44170c24599f7c6a8365b">CSR_PMPADDR8</a> = 0x3b8, </div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a54d38c8cf364d886eb7ac64463eedf77"> 82</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a54d38c8cf364d886eb7ac64463eedf77">CSR_PMPADDR9</a> = 0x3b9, </div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad97b6fe934a3bed6b02d0c8d81165d60"> 83</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad97b6fe934a3bed6b02d0c8d81165d60">CSR_PMPADDR10</a> = 0x3ba, </div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a3e5708c0f79cf58ae761b6bb8c2a4383"> 84</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a3e5708c0f79cf58ae761b6bb8c2a4383">CSR_PMPADDR11</a> = 0x3bb, </div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a23026793ee53c8d55d23f63195368a6b"> 85</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a23026793ee53c8d55d23f63195368a6b">CSR_PMPADDR12</a> = 0x3bc, </div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a30879e88b250d3e94d9d9e728ffcc2cc"> 86</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a30879e88b250d3e94d9d9e728ffcc2cc">CSR_PMPADDR13</a> = 0x3bd, </div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a91a8b5008b4e08ab34c1516e21bf0ba8"> 87</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a91a8b5008b4e08ab34c1516e21bf0ba8">CSR_PMPADDR14</a> = 0x3be, </div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6879b4bf5d2db92d236b9091df4841f2"> 88</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6879b4bf5d2db92d236b9091df4841f2">CSR_PMPADDR15</a> = 0x3bf, </div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span> <span class="comment">/* on-chip debugger - hardware trigger module */</span></div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aaae2f0b2e3f5a31dff933868873f6d5d"> 91</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aaae2f0b2e3f5a31dff933868873f6d5d">CSR_TSELECT</a> = 0x7a0, </div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a80eab0e17f5fe41edde485044674dc57"> 92</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a80eab0e17f5fe41edde485044674dc57">CSR_TDATA1</a> = 0x7a1, </div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49acf336638697242b691b691dc56b9aadc"> 93</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49acf336638697242b691b691dc56b9aadc">CSR_TDATA2</a> = 0x7a2, </div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af67c819c104f7e3ec34f2cbb847cf83b"> 94</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af67c819c104f7e3ec34f2cbb847cf83b">CSR_TINFO</a> = 0x7a4, </div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span> <span class="comment">/* CPU debug mode CSRs - not accessible by software running outside of debug mode */</span></div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6bb3ba59a25803d6f98faad67609a9a9"> 97</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6bb3ba59a25803d6f98faad67609a9a9">CSR_DCSR</a> = 0x7b0, </div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af4c98d949d2eb44f2518fdf314344d3b"> 98</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af4c98d949d2eb44f2518fdf314344d3b">CSR_DPC</a> = 0x7b1, </div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0f4a1ae740efd80d14d21e90f355e9d7"> 99</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0f4a1ae740efd80d14d21e90f355e9d7">CSR_DSCRATCH0</a> = 0x7b2, </div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span> <span class="comment">/* custom functions unit (CFU) registers */</span></div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae0e9cf0b99b8614ea0b870d38970281f"> 102</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae0e9cf0b99b8614ea0b870d38970281f">CSR_CFUREG0</a> = 0x800, </div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a382304065a6db773f925b80b9447b8a8"> 103</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a382304065a6db773f925b80b9447b8a8">CSR_CFUREG1</a> = 0x801, </div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a427d7cf036b49efd46166c01f0504b68"> 104</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a427d7cf036b49efd46166c01f0504b68">CSR_CFUREG2</a> = 0x802, </div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aefefa1cff0cf5d01109486e5a8bebedf"> 105</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aefefa1cff0cf5d01109486e5a8bebedf">CSR_CFUREG3</a> = 0x803, </div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span> <span class="comment">/* machine counters and timers */</span></div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a32c22641ed66c6d20902306a2b1fad77"> 108</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a32c22641ed66c6d20902306a2b1fad77">CSR_MCYCLE</a> = 0xb00, </div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a98f5e2cf2d5dbb0125a222b0065c86eb"> 109</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a98f5e2cf2d5dbb0125a222b0065c86eb">CSR_MINSTRET</a> = 0xb02, </div> +<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae0a96f499dcde474af6ee620fbb1ebdc"> 110</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae0a96f499dcde474af6ee620fbb1ebdc">CSR_MHPMCOUNTER3</a> = 0xb03, </div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9b84bd948dd52a7779b5fd16beddaab9"> 111</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9b84bd948dd52a7779b5fd16beddaab9">CSR_MHPMCOUNTER4</a> = 0xb04, </div> +<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af15d389bb8f91c989df488d231666394"> 112</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af15d389bb8f91c989df488d231666394">CSR_MHPMCOUNTER5</a> = 0xb05, </div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af65b9e99b9cadb3cb8d37f97cdbfeb9d"> 113</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af65b9e99b9cadb3cb8d37f97cdbfeb9d">CSR_MHPMCOUNTER6</a> = 0xb06, </div> +<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a919f39b0d299feb80403b42a466de444"> 114</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a919f39b0d299feb80403b42a466de444">CSR_MHPMCOUNTER7</a> = 0xb07, </div> +<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5a4cde90c547e913bddc719b3ab75e79"> 115</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5a4cde90c547e913bddc719b3ab75e79">CSR_MHPMCOUNTER8</a> = 0xb08, </div> +<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a18c2a249f1f7852f42f9e10dc59d46bb"> 116</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a18c2a249f1f7852f42f9e10dc59d46bb">CSR_MHPMCOUNTER9</a> = 0xb09, </div> +<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a575e5342d8ec304c32dbbe99d6fd6c0f"> 117</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a575e5342d8ec304c32dbbe99d6fd6c0f">CSR_MHPMCOUNTER10</a> = 0xb0a, </div> +<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8840b3d4f45453fc96813ccb369a68e5"> 118</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8840b3d4f45453fc96813ccb369a68e5">CSR_MHPMCOUNTER11</a> = 0xb0b, </div> +<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1328a226d36d23cc81740397bde47a4e"> 119</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1328a226d36d23cc81740397bde47a4e">CSR_MHPMCOUNTER12</a> = 0xb0c, </div> +<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9bdd102877ff50d38c86c3d741aeb4b0"> 120</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9bdd102877ff50d38c86c3d741aeb4b0">CSR_MHPMCOUNTER13</a> = 0xb0d, </div> +<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49adae22d860d8162e15120051951e45229"> 121</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49adae22d860d8162e15120051951e45229">CSR_MHPMCOUNTER14</a> = 0xb0e, </div> +<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a20400929087fabba410a098667d2d4ff"> 122</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a20400929087fabba410a098667d2d4ff">CSR_MHPMCOUNTER15</a> = 0xb0f, </div> +<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a28fcfd06ca1012c19cf053e57689687b"> 124</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a28fcfd06ca1012c19cf053e57689687b">CSR_MCYCLEH</a> = 0xb80, </div> +<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49afffb28b62b9baa127ae3bad919208988"> 125</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49afffb28b62b9baa127ae3bad919208988">CSR_MINSTRETH</a> = 0xb82, </div> +<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a252980a4da90c1f5c1ef85d164f72f25"> 126</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a252980a4da90c1f5c1ef85d164f72f25">CSR_MHPMCOUNTER3H</a> = 0xb83, </div> +<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e9cfbf3c2828dd4bd92d2b8a1c99f85"> 127</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e9cfbf3c2828dd4bd92d2b8a1c99f85">CSR_MHPMCOUNTER4H</a> = 0xb84, </div> +<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7648dd0a47007d44a14e95ba47726599"> 128</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7648dd0a47007d44a14e95ba47726599">CSR_MHPMCOUNTER5H</a> = 0xb85, </div> +<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a49b7bc2df67a6c73a68757de9b218f77"> 129</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a49b7bc2df67a6c73a68757de9b218f77">CSR_MHPMCOUNTER6H</a> = 0xb86, </div> +<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac0183bb6f357ed33136493ae7ded987a"> 130</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac0183bb6f357ed33136493ae7ded987a">CSR_MHPMCOUNTER7H</a> = 0xb87, </div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9e75518df7d14a009e3a0d5588641ddc"> 131</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9e75518df7d14a009e3a0d5588641ddc">CSR_MHPMCOUNTER8H</a> = 0xb88, </div> +<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7341886c7a4aed6fc7d8677c016a2cb8"> 132</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7341886c7a4aed6fc7d8677c016a2cb8">CSR_MHPMCOUNTER9H</a> = 0xb89, </div> +<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1e41d2b27d7e8da14871852d81123cfd"> 133</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1e41d2b27d7e8da14871852d81123cfd">CSR_MHPMCOUNTER10H</a> = 0xb8a, </div> +<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7fd76fcfc0d0dd47e112786bea5e4071"> 134</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7fd76fcfc0d0dd47e112786bea5e4071">CSR_MHPMCOUNTER11H</a> = 0xb8b, </div> +<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a332ec2b0740f8e899a1b2ec86f7ee9f2"> 135</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a332ec2b0740f8e899a1b2ec86f7ee9f2">CSR_MHPMCOUNTER12H</a> = 0xb8c, </div> +<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5de5c5a036dc594a554d37df9ccf657d"> 136</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5de5c5a036dc594a554d37df9ccf657d">CSR_MHPMCOUNTER13H</a> = 0xb8d, </div> +<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac65bab6fd71439600c8fc549171251fa"> 137</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac65bab6fd71439600c8fc549171251fa">CSR_MHPMCOUNTER14H</a> = 0xb8e, </div> +<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af609807e2917f73e27e5f27b38a0fa46"> 138</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af609807e2917f73e27e5f27b38a0fa46">CSR_MHPMCOUNTER15H</a> = 0xb8f, </div> +<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span> <span class="comment">/* user counters and timers */</span></div> +<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aaaf0f6b17a06d5922bcfdb47b382137e"> 141</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aaaf0f6b17a06d5922bcfdb47b382137e">CSR_CYCLE</a> = 0xc00, </div> +<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8144da8cd8691ac54aa0712685865b66"> 142</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8144da8cd8691ac54aa0712685865b66">CSR_INSTRET</a> = 0xc02, </div> +<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa276bedb7dab28935163397b4879f6db"> 144</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa276bedb7dab28935163397b4879f6db">CSR_CYCLEH</a> = 0xc80, </div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9b66978d76260283007d399fc735d153"> 145</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9b66978d76260283007d399fc735d153">CSR_INSTRETH</a> = 0xc82, </div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span> <span class="comment">/* machine information registers */</span></div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af5c5a21909aaca2b57f9a15f4bac246b"> 148</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af5c5a21909aaca2b57f9a15f4bac246b">CSR_MVENDORID</a> = 0xf11, </div> +<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad95cb95266533123447ff0e917f890e4"> 149</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad95cb95266533123447ff0e917f890e4">CSR_MARCHID</a> = 0xf12, </div> +<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a06d39cf0f13d6401dcf426d56149c8cd"> 150</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a06d39cf0f13d6401dcf426d56149c8cd">CSR_MIMPID</a> = 0xf13, </div> +<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6ba48e2306ae92f498552e1ea04d6790"> 151</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6ba48e2306ae92f498552e1ea04d6790">CSR_MHARTID</a> = 0xf14, </div> +<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0545d0921b3f90d037dbb25bc5fcc2f9"> 152</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0545d0921b3f90d037dbb25bc5fcc2f9">CSR_MCONFIGPTR</a> = 0xf15, </div> +<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a396847bcf1634a1602ab117bfb57bdd2">CSR_MXISA</a> = 0xfc0 </div> +<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a396847bcf1634a1602ab117bfb57bdd2"> 154</a></span>};</div> +</div> +<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span> </div> +<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span> </div> +<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00160" data-start="{" data-end="};"> +<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204b"> 160</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204b">NEORV32_CSR_FFLAGS_enum</a> {</div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba91a314defd310786a9ed67f7ef2ef5a6"> 161</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba91a314defd310786a9ed67f7ef2ef5a6">CSR_FFLAGS_NX</a> = 0, </div> +<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204babc6d405724563844569028f463885819"> 162</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204babc6d405724563844569028f463885819">CSR_FFLAGS_UF</a> = 1, </div> +<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba612390e07a065fa13eeaeac84af48c6e"> 163</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba612390e07a065fa13eeaeac84af48c6e">CSR_FFLAGS_OF</a> = 2, </div> +<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba365f3f519bca34a349907c82c873d52b"> 164</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba365f3f519bca34a349907c82c873d52b">CSR_FFLAGS_DZ</a> = 3, </div> +<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba3ac330a4b03178e756c980eaa48ad165">CSR_FFLAGS_NV</a> = 4 </div> +<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba3ac330a4b03178e756c980eaa48ad165"> 166</a></span>};</div> +</div> +<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span> </div> +<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span> </div> +<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"> 169</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00172" data-start="{" data-end="};"> +<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500"> 172</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500">NEORV32_CSR_MCOUNTEREN_enum</a> {</div> +<div class="line"><a id="l00173" name="l00173"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500a3d0c8ff6ba2c557cb5b5d353bdb95790"> 173</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500a3d0c8ff6ba2c557cb5b5d353bdb95790">CSR_MCOUNTEREN_CY</a> = 0, </div> +<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"> 174</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500a97e36c94b71fa2f9a805bbe47b0bc1b5">CSR_MCOUNTEREN_IR</a> = 2 </div> +<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500a97e36c94b71fa2f9a805bbe47b0bc1b5"> 175</a></span>};</div> +</div> +<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span> </div> +<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span> </div> +<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00181" data-start="{" data-end="};"> +<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485"> 181</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485">NEORV32_CSR_MSTATUS_enum</a> {</div> +<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485ae2603e365b3f1abfb46d53ed6b13dc56"> 182</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485ae2603e365b3f1abfb46d53ed6b13dc56">CSR_MSTATUS_MIE</a> = 3, </div> +<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485aaa1d482f828ac9cafc40fcfc298bec34"> 183</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485aaa1d482f828ac9cafc40fcfc298bec34">CSR_MSTATUS_MPIE</a> = 7, </div> +<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485af0ae9aca74144aa7dbdf656f71cc5c97"> 184</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485af0ae9aca74144aa7dbdf656f71cc5c97">CSR_MSTATUS_MPP_L</a> = 11, </div> +<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485a8067c609c2360cab3bafa3c43e03dbf0"> 185</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485a8067c609c2360cab3bafa3c43e03dbf0">CSR_MSTATUS_MPP_H</a> = 12, </div> +<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485a75cefdbdef36b7fc248765b27c606a44"> 186</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485a75cefdbdef36b7fc248765b27c606a44">CSR_MSTATUS_MPRV</a> = 17, </div> +<div class="line"><a id="l00187" name="l00187"></a><span class="lineno"> 187</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485ac94a070f3fe7962e8c49a81545cacf2d">CSR_MSTATUS_TW</a> = 21 </div> +<div class="line"><a id="l00188" name="l00188"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485ac94a070f3fe7962e8c49a81545cacf2d"> 188</a></span>};</div> +</div> +<div class="line"><a id="l00189" name="l00189"></a><span class="lineno"> 189</span> </div> +<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"> 190</span> </div> +<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00194" data-start="{" data-end="};"> +<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfe"> 194</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfe">NEORV32_CSR_MCOUNTINHIBIT_enum</a> {</div> +<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea201ac39b0eba389b0d02c3951a3311a3"> 195</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea201ac39b0eba389b0d02c3951a3311a3">CSR_MCOUNTINHIBIT_CY</a> = 0, </div> +<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea5f182f39f9a4b871a097a51e57865bfa"> 196</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea5f182f39f9a4b871a097a51e57865bfa">CSR_MCOUNTINHIBIT_IR</a> = 2, </div> +<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaf7020159e0ba346561bfba101d22c752"> 198</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaf7020159e0ba346561bfba101d22c752">CSR_MCOUNTINHIBIT_HPM3</a> = 3, </div> +<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea40427b799da049413c5536afa623c61d"> 199</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea40427b799da049413c5536afa623c61d">CSR_MCOUNTINHIBIT_HPM4</a> = 4, </div> +<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea2769a6e6a75f2f903523e4e95a899bb6"> 200</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea2769a6e6a75f2f903523e4e95a899bb6">CSR_MCOUNTINHIBIT_HPM5</a> = 5, </div> +<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfead55b6af15841617d7dca3ab4fab893db"> 201</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfead55b6af15841617d7dca3ab4fab893db">CSR_MCOUNTINHIBIT_HPM6</a> = 6, </div> +<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea3b3571fceb687da2d3807b0e59bdf7ab"> 202</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea3b3571fceb687da2d3807b0e59bdf7ab">CSR_MCOUNTINHIBIT_HPM7</a> = 7, </div> +<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeabd21344124eda4402523203185a58b8a"> 203</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeabd21344124eda4402523203185a58b8a">CSR_MCOUNTINHIBIT_HPM8</a> = 8, </div> +<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0f207455df0fed75fa68ba49c435889a"> 204</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0f207455df0fed75fa68ba49c435889a">CSR_MCOUNTINHIBIT_HPM9</a> = 9, </div> +<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea9517cd32744c5064fa30780f911cd22e"> 205</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea9517cd32744c5064fa30780f911cd22e">CSR_MCOUNTINHIBIT_HPM10</a> = 10, </div> +<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeacaf997fe8b912596224e2bb632e6a806"> 206</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeacaf997fe8b912596224e2bb632e6a806">CSR_MCOUNTINHIBIT_HPM11</a> = 11, </div> +<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea8d866a4c815d8ba890a1e00ce9600486"> 207</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea8d866a4c815d8ba890a1e00ce9600486">CSR_MCOUNTINHIBIT_HPM12</a> = 12, </div> +<div class="line"><a id="l00208" name="l00208"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfead9f6c4eb4284ee82b9e8d0c79f62b3ed"> 208</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfead9f6c4eb4284ee82b9e8d0c79f62b3ed">CSR_MCOUNTINHIBIT_HPM13</a> = 13, </div> +<div class="line"><a id="l00209" name="l00209"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa83c0688869b1c43de0c4474e940f987"> 209</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa83c0688869b1c43de0c4474e940f987">CSR_MCOUNTINHIBIT_HPM14</a> = 14, </div> +<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0b547cb5876c0e7956e3d062e0784085"> 210</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0b547cb5876c0e7956e3d062e0784085">CSR_MCOUNTINHIBIT_HPM15</a> = 15, </div> +<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea68aba71ea77aba4005fb24a945ef38e4"> 211</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea68aba71ea77aba4005fb24a945ef38e4">CSR_MCOUNTINHIBIT_HPM16</a> = 16, </div> +<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea8d57acf13a086635a63bc13ccdf479b3"> 212</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea8d57acf13a086635a63bc13ccdf479b3">CSR_MCOUNTINHIBIT_HPM17</a> = 17, </div> +<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa680d196d2ba0e403801a860bb9d8ce0"> 213</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa680d196d2ba0e403801a860bb9d8ce0">CSR_MCOUNTINHIBIT_HPM18</a> = 18, </div> +<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea3683e296caafe771b6dd57f4cf86f3dc"> 214</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea3683e296caafe771b6dd57f4cf86f3dc">CSR_MCOUNTINHIBIT_HPM19</a> = 19, </div> +<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaeb4b1b6abafd22eec0764d5503878cca"> 215</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaeb4b1b6abafd22eec0764d5503878cca">CSR_MCOUNTINHIBIT_HPM20</a> = 20, </div> +<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea1dc0276a5354c805ac56fd46c5037d38"> 216</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea1dc0276a5354c805ac56fd46c5037d38">CSR_MCOUNTINHIBIT_HPM21</a> = 21, </div> +<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaf1b6153a0c664367bfefb78b2ca8b34e"> 217</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaf1b6153a0c664367bfefb78b2ca8b34e">CSR_MCOUNTINHIBIT_HPM22</a> = 22, </div> +<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea85c0c2b2a5101380dec72516dda1a904"> 218</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea85c0c2b2a5101380dec72516dda1a904">CSR_MCOUNTINHIBIT_HPM23</a> = 23, </div> +<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea74ec85a2e94aa0b9e8af29401ef7ecb1"> 219</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea74ec85a2e94aa0b9e8af29401ef7ecb1">CSR_MCOUNTINHIBIT_HPM24</a> = 24, </div> +<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaee2b5a2b7bd7ac07dae45900bc2faf46"> 220</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaee2b5a2b7bd7ac07dae45900bc2faf46">CSR_MCOUNTINHIBIT_HPM25</a> = 25, </div> +<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea141a4a211c496d2af1c79d8e8e0c2a74"> 221</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea141a4a211c496d2af1c79d8e8e0c2a74">CSR_MCOUNTINHIBIT_HPM26</a> = 26, </div> +<div class="line"><a id="l00222" name="l00222"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea46def851d4582b4bcec1f9d8bafd58db"> 222</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea46def851d4582b4bcec1f9d8bafd58db">CSR_MCOUNTINHIBIT_HPM27</a> = 27, </div> +<div class="line"><a id="l00223" name="l00223"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea33d0fd3378ec3a2fcc3c8738c6cd2f32"> 223</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea33d0fd3378ec3a2fcc3c8738c6cd2f32">CSR_MCOUNTINHIBIT_HPM28</a> = 28, </div> +<div class="line"><a id="l00224" name="l00224"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa39882f7dad9b7e16b317c75bad31382"> 224</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa39882f7dad9b7e16b317c75bad31382">CSR_MCOUNTINHIBIT_HPM29</a> = 29, </div> +<div class="line"><a id="l00225" name="l00225"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0f45818fa4cb9033a3093987fa8515c7"> 225</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0f45818fa4cb9033a3093987fa8515c7">CSR_MCOUNTINHIBIT_HPM30</a> = 30, </div> +<div class="line"><a id="l00226" name="l00226"></a><span class="lineno"> 226</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea1da1186ef2f4e7297a4fecaaccdc1d05">CSR_MCOUNTINHIBIT_HPM31</a> = 31 </div> +<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea1da1186ef2f4e7297a4fecaaccdc1d05"> 227</a></span>};</div> +</div> +<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span> </div> +<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span> </div> +<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00233" data-start="{" data-end="};"> +<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33"> 233</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a> {</div> +<div class="line"><a id="l00234" name="l00234"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33afd2f1c78c442c8c29ab075cacee0a27a"> 234</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33afd2f1c78c442c8c29ab075cacee0a27a">CSR_MIE_MSIE</a> = 3, </div> +<div class="line"><a id="l00235" name="l00235"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3658e8663e94cd8eaa7201b7a850d083"> 235</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3658e8663e94cd8eaa7201b7a850d083">CSR_MIE_MTIE</a> = 7, </div> +<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33ae8e4f0ee46abbbb3361de035a57b8324"> 236</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33ae8e4f0ee46abbbb3361de035a57b8324">CSR_MIE_MEIE</a> = 11, </div> +<div class="line"><a id="l00238" name="l00238"></a><span class="lineno"> 238</span> <span class="comment">/* NEORV32-specific extension: Fast Interrupt Requests (FIRQ) */</span></div> +<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a99f43f8bbfb29fba6224f081c363ac7d"> 239</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a99f43f8bbfb29fba6224f081c363ac7d">CSR_MIE_FIRQ0E</a> = 16, </div> +<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33ac1e1d44becec1b393f79a118ed3d8beb"> 240</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33ac1e1d44becec1b393f79a118ed3d8beb">CSR_MIE_FIRQ1E</a> = 17, </div> +<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33afc805280e20ffface116ca61e11645f7"> 241</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33afc805280e20ffface116ca61e11645f7">CSR_MIE_FIRQ2E</a> = 18, </div> +<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a666066099d6cebadbef21d81c179e8db"> 242</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a666066099d6cebadbef21d81c179e8db">CSR_MIE_FIRQ3E</a> = 19, </div> +<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a592939f1b7d79097f7f13d6ab0c268dc"> 243</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a592939f1b7d79097f7f13d6ab0c268dc">CSR_MIE_FIRQ4E</a> = 20, </div> +<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3079a8fbf3b8e376865bff76f2173698"> 244</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3079a8fbf3b8e376865bff76f2173698">CSR_MIE_FIRQ5E</a> = 21, </div> +<div class="line"><a id="l00245" name="l00245"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a96315d6b5b9531bcbc1e78a3c9ab166a"> 245</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a96315d6b5b9531bcbc1e78a3c9ab166a">CSR_MIE_FIRQ6E</a> = 22, </div> +<div class="line"><a id="l00246" name="l00246"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3d9d729940170609affbc6813054ebe8"> 246</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3d9d729940170609affbc6813054ebe8">CSR_MIE_FIRQ7E</a> = 23, </div> +<div class="line"><a id="l00247" name="l00247"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a396c6c4b425b3fff598e2f846052f98e"> 247</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a396c6c4b425b3fff598e2f846052f98e">CSR_MIE_FIRQ8E</a> = 24, </div> +<div class="line"><a id="l00248" name="l00248"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a06fdb61dab31c3490da6c37d47914f19"> 248</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a06fdb61dab31c3490da6c37d47914f19">CSR_MIE_FIRQ9E</a> = 25, </div> +<div class="line"><a id="l00249" name="l00249"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33affcb52dc57bb8c0cb1e7d3c1392d544a"> 249</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33affcb52dc57bb8c0cb1e7d3c1392d544a">CSR_MIE_FIRQ10E</a> = 26, </div> +<div class="line"><a id="l00250" name="l00250"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33af058342854a0becd3bcc33877d9244cd"> 250</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33af058342854a0becd3bcc33877d9244cd">CSR_MIE_FIRQ11E</a> = 27, </div> +<div class="line"><a id="l00251" name="l00251"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a41f91a37f7e0c75c783312af6a72e943"> 251</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a41f91a37f7e0c75c783312af6a72e943">CSR_MIE_FIRQ12E</a> = 28, </div> +<div class="line"><a id="l00252" name="l00252"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a134ed02c7293008b21b1df472be8f11f"> 252</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a134ed02c7293008b21b1df472be8f11f">CSR_MIE_FIRQ13E</a> = 29, </div> +<div class="line"><a id="l00253" name="l00253"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a864d135708530016cfc52a65a1e4d79b"> 253</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a864d135708530016cfc52a65a1e4d79b">CSR_MIE_FIRQ14E</a> = 30, </div> +<div class="line"><a id="l00254" name="l00254"></a><span class="lineno"> 254</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33aa2dfa1183af312de2959dadd217fddc1">CSR_MIE_FIRQ15E</a> = 31 </div> +<div class="line"><a id="l00255" name="l00255"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33aa2dfa1183af312de2959dadd217fddc1"> 255</a></span>};</div> +</div> +<div class="line"><a id="l00256" name="l00256"></a><span class="lineno"> 256</span> </div> +<div class="line"><a id="l00257" name="l00257"></a><span class="lineno"> 257</span> </div> +<div class="line"><a id="l00258" name="l00258"></a><span class="lineno"> 258</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00261" data-start="{" data-end="};"> +<div class="line"><a id="l00261" name="l00261"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b"> 261</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a> {</div> +<div class="line"><a id="l00262" name="l00262"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba1470cfe04f9d3ce45b7156b2a7fae159"> 262</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba1470cfe04f9d3ce45b7156b2a7fae159">CSR_MIP_MSIP</a> = 3, </div> +<div class="line"><a id="l00263" name="l00263"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba344943c62922561378d33ec51ac236e4"> 263</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba344943c62922561378d33ec51ac236e4">CSR_MIP_MTIP</a> = 7, </div> +<div class="line"><a id="l00264" name="l00264"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba1d761ef98f88c40509168ac66b7a4872"> 264</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba1d761ef98f88c40509168ac66b7a4872">CSR_MIP_MEIP</a> = 11, </div> +<div class="line"><a id="l00266" name="l00266"></a><span class="lineno"> 266</span> <span class="comment">/* NEORV32-specific extension: Fast Interrupt Requests (FIRQ) */</span></div> +<div class="line"><a id="l00267" name="l00267"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba28a85ad8bd4c30fd3a91298dfa4fdb00"> 267</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba28a85ad8bd4c30fd3a91298dfa4fdb00">CSR_MIP_FIRQ0P</a> = 16, </div> +<div class="line"><a id="l00268" name="l00268"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba2b577b1da1074c29ad58005af1f91d52"> 268</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba2b577b1da1074c29ad58005af1f91d52">CSR_MIP_FIRQ1P</a> = 17, </div> +<div class="line"><a id="l00269" name="l00269"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21badf45c5a135431f958fa63574c1dfac6e"> 269</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21badf45c5a135431f958fa63574c1dfac6e">CSR_MIP_FIRQ2P</a> = 18, </div> +<div class="line"><a id="l00270" name="l00270"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba7512bb6c4841ddd477422b49ebb2a155"> 270</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba7512bb6c4841ddd477422b49ebb2a155">CSR_MIP_FIRQ3P</a> = 19, </div> +<div class="line"><a id="l00271" name="l00271"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21bab6421f242bb8a487a986346e11196eb8"> 271</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21bab6421f242bb8a487a986346e11196eb8">CSR_MIP_FIRQ4P</a> = 20, </div> +<div class="line"><a id="l00272" name="l00272"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baaa55d19f9a47889bc364c94bda04b677"> 272</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baaa55d19f9a47889bc364c94bda04b677">CSR_MIP_FIRQ5P</a> = 21, </div> +<div class="line"><a id="l00273" name="l00273"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baffa7342631aa0526aaa44c0c549b1f3e"> 273</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baffa7342631aa0526aaa44c0c549b1f3e">CSR_MIP_FIRQ6P</a> = 22, </div> +<div class="line"><a id="l00274" name="l00274"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baad691486001a68f2375dcf5793ee795a"> 274</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baad691486001a68f2375dcf5793ee795a">CSR_MIP_FIRQ7P</a> = 23, </div> +<div class="line"><a id="l00275" name="l00275"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baf5bbd23d4f311f640db42e9015f87580"> 275</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baf5bbd23d4f311f640db42e9015f87580">CSR_MIP_FIRQ8P</a> = 24, </div> +<div class="line"><a id="l00276" name="l00276"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21bad94c9691ce59b97fcfec14d345046c3e"> 276</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21bad94c9691ce59b97fcfec14d345046c3e">CSR_MIP_FIRQ9P</a> = 25, </div> +<div class="line"><a id="l00277" name="l00277"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba2b50cfa8be461b088ea8506ce4c741ba"> 277</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba2b50cfa8be461b088ea8506ce4c741ba">CSR_MIP_FIRQ10P</a> = 26, </div> +<div class="line"><a id="l00278" name="l00278"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba69ea0d3d76d4cec398f3b96959cc3544"> 278</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba69ea0d3d76d4cec398f3b96959cc3544">CSR_MIP_FIRQ11P</a> = 27, </div> +<div class="line"><a id="l00279" name="l00279"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba03edd398920b817150d29107c0b40792"> 279</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba03edd398920b817150d29107c0b40792">CSR_MIP_FIRQ12P</a> = 28, </div> +<div class="line"><a id="l00280" name="l00280"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba14da6a2a962bf82970638a948ffbc570"> 280</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba14da6a2a962bf82970638a948ffbc570">CSR_MIP_FIRQ13P</a> = 29, </div> +<div class="line"><a id="l00281" name="l00281"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baad1e5e452a9c37561308765431f0260d"> 281</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baad1e5e452a9c37561308765431f0260d">CSR_MIP_FIRQ14P</a> = 30, </div> +<div class="line"><a id="l00282" name="l00282"></a><span class="lineno"> 282</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba12da8c32d38d5a3539a0b766718bfd2d">CSR_MIP_FIRQ15P</a> = 31 </div> +<div class="line"><a id="l00283" name="l00283"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba12da8c32d38d5a3539a0b766718bfd2d"> 283</a></span>};</div> +</div> +<div class="line"><a id="l00284" name="l00284"></a><span class="lineno"> 284</span> </div> +<div class="line"><a id="l00285" name="l00285"></a><span class="lineno"> 285</span> </div> +<div class="line"><a id="l00286" name="l00286"></a><span class="lineno"> 286</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00289" data-start="{" data-end="};"> +<div class="line"><a id="l00289" name="l00289"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830c"> 289</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830c">NEORV32_CSR_MISA_enum</a> {</div> +<div class="line"><a id="l00290" name="l00290"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cadd469404a928e012a298773ec46926ad"> 290</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cadd469404a928e012a298773ec46926ad">CSR_MISA_B</a> = 1, </div> +<div class="line"><a id="l00291" name="l00291"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca886699013158c74810598fa2fd6b07fa"> 291</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca886699013158c74810598fa2fd6b07fa">CSR_MISA_C</a> = 2, </div> +<div class="line"><a id="l00292" name="l00292"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca0ac798fd19cb7dbe1146afecda448fec"> 292</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca0ac798fd19cb7dbe1146afecda448fec">CSR_MISA_E</a> = 4, </div> +<div class="line"><a id="l00293" name="l00293"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca6091fd2c7ae38ad33be68a0fdfa50cca"> 293</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca6091fd2c7ae38ad33be68a0fdfa50cca">CSR_MISA_I</a> = 8, </div> +<div class="line"><a id="l00294" name="l00294"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca317a631e4598532f5bffe8fb93aff94b"> 294</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca317a631e4598532f5bffe8fb93aff94b">CSR_MISA_M</a> = 12, </div> +<div class="line"><a id="l00295" name="l00295"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cacd9d71e674d3a6d04984b6df706d9deb"> 295</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cacd9d71e674d3a6d04984b6df706d9deb">CSR_MISA_U</a> = 20, </div> +<div class="line"><a id="l00296" name="l00296"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca0b119a20be29fcae8fecf2a81c60d193"> 296</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca0b119a20be29fcae8fecf2a81c60d193">CSR_MISA_X</a> = 23, </div> +<div class="line"><a id="l00297" name="l00297"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cab5a55e97b8511f42fe68559a38f7f138"> 297</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cab5a55e97b8511f42fe68559a38f7f138">CSR_MISA_MXL_LO</a> = 30, </div> +<div class="line"><a id="l00298" name="l00298"></a><span class="lineno"> 298</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cafb3e4b08b87f5c161468a9e58ade12cc">CSR_MISA_MXL_HI</a> = 31 </div> +<div class="line"><a id="l00299" name="l00299"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cafb3e4b08b87f5c161468a9e58ade12cc"> 299</a></span>};</div> +</div> +<div class="line"><a id="l00300" name="l00300"></a><span class="lineno"> 300</span> </div> +<div class="line"><a id="l00301" name="l00301"></a><span class="lineno"> 301</span> </div> +<div class="line"><a id="l00302" name="l00302"></a><span class="lineno"> 302</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00305" data-start="{" data-end="};"> +<div class="line"><a id="l00305" name="l00305"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387"> 305</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387">NEORV32_CSR_XISA_enum</a> {</div> +<div class="line"><a id="l00306" name="l00306"></a><span class="lineno"> 306</span> <span class="comment">// ISA (sub-)extensions</span></div> +<div class="line"><a id="l00307" name="l00307"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387accf1dd12be89e45df1423a5600789f2c"> 307</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387accf1dd12be89e45df1423a5600789f2c">CSR_MXISA_ZICSR</a> = 0, </div> +<div class="line"><a id="l00308" name="l00308"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6979d4389ed9f8605d338fc616d29f0e"> 308</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6979d4389ed9f8605d338fc616d29f0e">CSR_MXISA_ZIFENCEI</a> = 1, </div> +<div class="line"><a id="l00309" name="l00309"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a79b2b4b20e08ad31b50724a7a27fb20f"> 309</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a79b2b4b20e08ad31b50724a7a27fb20f">CSR_MXISA_ZMMUL</a> = 2, </div> +<div class="line"><a id="l00310" name="l00310"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387af422ae3b5caba59e33a29b5d069597e0"> 310</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387af422ae3b5caba59e33a29b5d069597e0">CSR_MXISA_ZXCFU</a> = 3, </div> +<div class="line"><a id="l00311" name="l00311"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a31788af612f04bc6b2a2bd15c1fb63c1"> 311</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a31788af612f04bc6b2a2bd15c1fb63c1">CSR_MXISA_ZKT</a> = 4, </div> +<div class="line"><a id="l00312" name="l00312"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a56ec3195d0d27f362f58fadb2e037ed1"> 312</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a56ec3195d0d27f362f58fadb2e037ed1">CSR_MXISA_ZFINX</a> = 5, </div> +<div class="line"><a id="l00313" name="l00313"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ab1f289cfaa9f54f7831a2abcdf9fca2e"> 313</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ab1f289cfaa9f54f7831a2abcdf9fca2e">CSR_MXISA_ZICOND</a> = 6, </div> +<div class="line"><a id="l00314" name="l00314"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a42a3b78195741af4b6aeeb98cbea46fe"> 314</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a42a3b78195741af4b6aeeb98cbea46fe">CSR_MXISA_ZICNTR</a> = 7, </div> +<div class="line"><a id="l00315" name="l00315"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6938948290d86b0ad25923f35d6c86d3"> 315</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6938948290d86b0ad25923f35d6c86d3">CSR_MXISA_SMPMP</a> = 8, </div> +<div class="line"><a id="l00316" name="l00316"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ac13e6883af3a9da18057462239b9fb34"> 316</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ac13e6883af3a9da18057462239b9fb34">CSR_MXISA_ZIHPM</a> = 9, </div> +<div class="line"><a id="l00317" name="l00317"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ab6aec595e6aa5ce7c98c7806d23d7af5"> 317</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ab6aec595e6aa5ce7c98c7806d23d7af5">CSR_MXISA_SDEXT</a> = 10, </div> +<div class="line"><a id="l00318" name="l00318"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a59eae4272528f589f299ef9cce45af5b"> 318</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a59eae4272528f589f299ef9cce45af5b">CSR_MXISA_SDTRIG</a> = 11, </div> +<div class="line"><a id="l00319" name="l00319"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a34519a66e749d63dc5bc7c145c297b64"> 319</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a34519a66e749d63dc5bc7c145c297b64">CSR_MXISA_ZBKX</a> = 12, </div> +<div class="line"><a id="l00320" name="l00320"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a48f1de7f79a0633644ae02c463d49375"> 320</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a48f1de7f79a0633644ae02c463d49375">CSR_MXISA_ZKND</a> = 13, </div> +<div class="line"><a id="l00321" name="l00321"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a216ec44d5be3b158acb7e033e352bad1"> 321</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a216ec44d5be3b158acb7e033e352bad1">CSR_MXISA_ZKNE</a> = 14, </div> +<div class="line"><a id="l00322" name="l00322"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a5fe8e591901e0fd7ba6706c70e9c76ec"> 322</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a5fe8e591901e0fd7ba6706c70e9c76ec">CSR_MXISA_ZKNH</a> = 15, </div> +<div class="line"><a id="l00323" name="l00323"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adb26c1e5bf6ae112625621dddd331735"> 323</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adb26c1e5bf6ae112625621dddd331735">CSR_MXISA_ZBKB</a> = 16, </div> +<div class="line"><a id="l00324" name="l00324"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ac9e87153c096d656b40cb7abdf3afd55"> 324</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ac9e87153c096d656b40cb7abdf3afd55">CSR_MXISA_ZBKC</a> = 17, </div> +<div class="line"><a id="l00325" name="l00325"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ad7e7454a30c82c3d91acbc8c259e8c25"> 325</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ad7e7454a30c82c3d91acbc8c259e8c25">CSR_MXISA_ZKN</a> = 18, </div> +<div class="line"><a id="l00326" name="l00326"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a5e4bf05830b66410bbf2ef2c68e5fd18"> 326</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a5e4bf05830b66410bbf2ef2c68e5fd18">CSR_MXISA_ZKSH</a> = 19, </div> +<div class="line"><a id="l00327" name="l00327"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a43213190abb77304a78c15196c90a044"> 327</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a43213190abb77304a78c15196c90a044">CSR_MXISA_ZKSED</a> = 20, </div> +<div class="line"><a id="l00328" name="l00328"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a2649bee3397c74ada7b72677308f38c0"> 328</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a2649bee3397c74ada7b72677308f38c0">CSR_MXISA_ZKS</a> = 21, </div> +<div class="line"><a id="l00329" name="l00329"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adfc9122d93a71bf6df178022a52d22c4"> 329</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adfc9122d93a71bf6df178022a52d22c4">CSR_MXISA_ZBA</a> = 22, </div> +<div class="line"><a id="l00330" name="l00330"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a815cbe0149cba2a69025f6bec9946a85"> 330</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a815cbe0149cba2a69025f6bec9946a85">CSR_MXISA_ZBB</a> = 23, </div> +<div class="line"><a id="l00331" name="l00331"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a469e8e449f0e442df531c8cf2c4f35c5"> 331</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a469e8e449f0e442df531c8cf2c4f35c5">CSR_MXISA_ZBS</a> = 24, </div> +<div class="line"><a id="l00332" name="l00332"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adf45adc0bcbec0c1ffa944099257a947"> 332</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adf45adc0bcbec0c1ffa944099257a947">CSR_MXISA_ZALRSC</a> = 25, </div> +<div class="line"><a id="l00333" name="l00333"></a><span class="lineno"> 333</span> <span class="comment">// Tuning options</span></div> +<div class="line"><a id="l00334" name="l00334"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6843c660d75f33e4252c7fccd4565a2d"> 334</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6843c660d75f33e4252c7fccd4565a2d">CSR_MXISA_RFHWRST</a> = 28, </div> +<div class="line"><a id="l00335" name="l00335"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a48e57689f8a5b51d9ee9d648da7efc64"> 335</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a48e57689f8a5b51d9ee9d648da7efc64">CSR_MXISA_FASTMUL</a> = 29, </div> +<div class="line"><a id="l00336" name="l00336"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ad5ac9e2188757e6c42c159f0c5887868"> 336</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ad5ac9e2188757e6c42c159f0c5887868">CSR_MXISA_FASTSHIFT</a> = 30, </div> +<div class="line"><a id="l00337" name="l00337"></a><span class="lineno"> 337</span> <span class="comment">// Misc</span></div> +<div class="line"><a id="l00338" name="l00338"></a><span class="lineno"> 338</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a9b121ec0ad6271b6e07658f861015f6a">CSR_MXISA_IS_SIM</a> = 31 </div> +<div class="line"><a id="l00339" name="l00339"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a9b121ec0ad6271b6e07658f861015f6a"> 339</a></span>};</div> +</div> +<div class="line"><a id="l00340" name="l00340"></a><span class="lineno"> 340</span> </div> +<div class="line"><a id="l00341" name="l00341"></a><span class="lineno"> 341</span> </div> +<div class="line"><a id="l00342" name="l00342"></a><span class="lineno"> 342</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00345" data-start="{" data-end="};"> +<div class="line"><a id="l00345" name="l00345"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfe"> 345</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a> {</div> +<div class="line"><a id="l00346" name="l00346"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea2b683572525adc02ce0910031cfea914"> 346</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea2b683572525adc02ce0910031cfea914">HPMCNT_EVENT_CY</a> = 0, </div> +<div class="line"><a id="l00347" name="l00347"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea578ef6fc107c22b5cb7be5950f695640"> 347</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea578ef6fc107c22b5cb7be5950f695640">HPMCNT_EVENT_TM</a> = 1, </div> +<div class="line"><a id="l00348" name="l00348"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeaab438295e5f00ffe4c2457a54ee9bfc4"> 348</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeaab438295e5f00ffe4c2457a54ee9bfc4">HPMCNT_EVENT_IR</a> = 2, </div> +<div class="line"><a id="l00349" name="l00349"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea685ed663611d988702ec59c254eb61dd"> 349</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea685ed663611d988702ec59c254eb61dd">HPMCNT_EVENT_COMPR</a> = 3, </div> +<div class="line"><a id="l00350" name="l00350"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeabcb123b5b150b4413e5fd48475faab27"> 350</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeabcb123b5b150b4413e5fd48475faab27">HPMCNT_EVENT_WAIT_DIS</a> = 4, </div> +<div class="line"><a id="l00351" name="l00351"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeaffbb04d0053ebd079c6cacb4e5e7ed6b"> 351</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeaffbb04d0053ebd079c6cacb4e5e7ed6b">HPMCNT_EVENT_WAIT_ALU</a> = 5, </div> +<div class="line"><a id="l00352" name="l00352"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea9e1e2b50352b2555e9c64e76776919a6"> 352</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea9e1e2b50352b2555e9c64e76776919a6">HPMCNT_EVENT_BRANCH</a> = 6, </div> +<div class="line"><a id="l00353" name="l00353"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea0f15c5a824cb1678423ac4ef72a5f4f5"> 353</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea0f15c5a824cb1678423ac4ef72a5f4f5">HPMCNT_EVENT_BRANCHED</a> = 7, </div> +<div class="line"><a id="l00354" name="l00354"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea1a06f216e1a12afa0b90d6e1218b3c91"> 354</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea1a06f216e1a12afa0b90d6e1218b3c91">HPMCNT_EVENT_LOAD</a> = 8, </div> +<div class="line"><a id="l00355" name="l00355"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea6a942852e3cd85616a63addb8e9d76f2"> 355</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea6a942852e3cd85616a63addb8e9d76f2">HPMCNT_EVENT_STORE</a> = 9, </div> +<div class="line"><a id="l00356" name="l00356"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea67a59934bc66bc7ccf82d24fe8a18a3b"> 356</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea67a59934bc66bc7ccf82d24fe8a18a3b">HPMCNT_EVENT_WAIT_LSU</a> = 10, </div> +<div class="line"><a id="l00357" name="l00357"></a><span class="lineno"> 357</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea3a4f5bf9251def87a71162dbcf9043c5">HPMCNT_EVENT_TRAP</a> = 11 </div> +<div class="line"><a id="l00358" name="l00358"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea3a4f5bf9251def87a71162dbcf9043c5"> 358</a></span>};</div> +</div> +<div class="line"><a id="l00359" name="l00359"></a><span class="lineno"> 359</span> </div> +<div class="line"><a id="l00360" name="l00360"></a><span class="lineno"> 360</span> </div> +<div class="line"><a id="l00361" name="l00361"></a><span class="lineno"> 361</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00364" data-start="{" data-end="};"> +<div class="line"><a id="l00364" name="l00364"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930ea"> 364</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a> {</div> +<div class="line"><a id="l00365" name="l00365"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaad3aca82a2ab57364e83f677d3d4f71a6"> 365</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaad3aca82a2ab57364e83f677d3d4f71a6">PMPCFG_R</a> = 0, </div> +<div class="line"><a id="l00366" name="l00366"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa7689905760f917499b1151cced384d2f"> 366</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa7689905760f917499b1151cced384d2f">PMPCFG_W</a> = 1, </div> +<div class="line"><a id="l00367" name="l00367"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaaec94712deafba09c0cf956c6fd68fa8d"> 367</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaaec94712deafba09c0cf956c6fd68fa8d">PMPCFG_X</a> = 2, </div> +<div class="line"><a id="l00368" name="l00368"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaaae1e6440956ad6b7cbf6062aa50f43b1"> 368</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaaae1e6440956ad6b7cbf6062aa50f43b1">PMPCFG_A_LSB</a> = 3, </div> +<div class="line"><a id="l00369" name="l00369"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa67ad3243eeb74f86a01efbade76f21e4"> 369</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa67ad3243eeb74f86a01efbade76f21e4">PMPCFG_A_MSB</a> = 4, </div> +<div class="line"><a id="l00370" name="l00370"></a><span class="lineno"> 370</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa59c294bc43d2117bb55e301eec683f14">PMPCFG_L</a> = 7 </div> +<div class="line"><a id="l00371" name="l00371"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa59c294bc43d2117bb55e301eec683f14"> 371</a></span>};</div> +</div> +<div class="line"><a id="l00372" name="l00372"></a><span class="lineno"> 372</span> </div> +<div class="line"><a id="l00373" name="l00373"></a><span class="lineno"> 373</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00376" data-start="{" data-end="};"> +<div class="line"><a id="l00376" name="l00376"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5"> 376</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a> {</div> +<div class="line"><a id="l00377" name="l00377"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5a003ccfae4aae1dad4fd65d5d4c7737c4"> 377</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5a003ccfae4aae1dad4fd65d5d4c7737c4">PMP_OFF</a> = 0, </div> +<div class="line"><a id="l00378" name="l00378"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5a629a81a205abee94bad9d5bb5dfa26b1"> 378</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5a629a81a205abee94bad9d5bb5dfa26b1">PMP_TOR</a> = 1, </div> +<div class="line"><a id="l00379" name="l00379"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5aae0e0c33b0d034cb50286239f955d892"> 379</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5aae0e0c33b0d034cb50286239f955d892">PMP_NA4</a> = 2, </div> +<div class="line"><a id="l00380" name="l00380"></a><span class="lineno"> 380</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5ad555e9dfc0c00612bdea623617ff2820">PMP_NAPOT</a> = 3 </div> +<div class="line"><a id="l00381" name="l00381"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5ad555e9dfc0c00612bdea623617ff2820"> 381</a></span>};</div> +</div> +<div class="line"><a id="l00382" name="l00382"></a><span class="lineno"> 382</span> </div> +<div class="line"><a id="l00383" name="l00383"></a><span class="lineno"> 383</span> </div> +<div class="line"><a id="l00384" name="l00384"></a><span class="lineno"> 384</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00387" data-start="{" data-end="};"> +<div class="line"><a id="l00387" name="l00387"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1"> 387</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a> {</div> +<div class="line"><a id="l00388" name="l00388"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a0a8010d7cc91b9557973a7a118828bee"> 388</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a0a8010d7cc91b9557973a7a118828bee">TRAP_CODE_I_MISALIGNED</a> = 0x00000000U, </div> +<div class="line"><a id="l00389" name="l00389"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a6a0ebfce4e18f36aeb43d5a65445cfe1"> 389</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a6a0ebfce4e18f36aeb43d5a65445cfe1">TRAP_CODE_I_ACCESS</a> = 0x00000001U, </div> +<div class="line"><a id="l00390" name="l00390"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1af1ad8f557f3b685b59a913611e1da173"> 390</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1af1ad8f557f3b685b59a913611e1da173">TRAP_CODE_I_ILLEGAL</a> = 0x00000002U, </div> +<div class="line"><a id="l00391" name="l00391"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a2c9510cb7583a0144f96678fc217335e"> 391</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a2c9510cb7583a0144f96678fc217335e">TRAP_CODE_BREAKPOINT</a> = 0x00000003U, </div> +<div class="line"><a id="l00392" name="l00392"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a69e68a954da0bb33d1624484a6777ff9"> 392</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a69e68a954da0bb33d1624484a6777ff9">TRAP_CODE_L_MISALIGNED</a> = 0x00000004U, </div> +<div class="line"><a id="l00393" name="l00393"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a28448f0c670169140dc28b6794310cea"> 393</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a28448f0c670169140dc28b6794310cea">TRAP_CODE_L_ACCESS</a> = 0x00000005U, </div> +<div class="line"><a id="l00394" name="l00394"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a19708405f9f6300edf6b992c6d408a2d"> 394</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a19708405f9f6300edf6b992c6d408a2d">TRAP_CODE_S_MISALIGNED</a> = 0x00000006U, </div> +<div class="line"><a id="l00395" name="l00395"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a70bcfc75fe1056d93a3606f78c0cb887"> 395</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a70bcfc75fe1056d93a3606f78c0cb887">TRAP_CODE_S_ACCESS</a> = 0x00000007U, </div> +<div class="line"><a id="l00396" name="l00396"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aa102472d6a264bb92e0581ccaa413e02"> 396</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aa102472d6a264bb92e0581ccaa413e02">TRAP_CODE_UENV_CALL</a> = 0x00000008U, </div> +<div class="line"><a id="l00397" name="l00397"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a20e5a2680f2f5956bfa92852d5544eac"> 397</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a20e5a2680f2f5956bfa92852d5544eac">TRAP_CODE_MENV_CALL</a> = 0x0000000bU, </div> +<div class="line"><a id="l00398" name="l00398"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ae0cebf99f36ef6be60e4a9d2c9f894b0"> 398</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ae0cebf99f36ef6be60e4a9d2c9f894b0">TRAP_CODE_MSI</a> = 0x80000003U, </div> +<div class="line"><a id="l00399" name="l00399"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a187ae38819b81672c15808e63c3b46b7"> 399</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a187ae38819b81672c15808e63c3b46b7">TRAP_CODE_MTI</a> = 0x80000007U, </div> +<div class="line"><a id="l00400" name="l00400"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a1a412b9d8eefba7880555d34625d2cc0"> 400</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a1a412b9d8eefba7880555d34625d2cc0">TRAP_CODE_MEI</a> = 0x8000000bU, </div> +<div class="line"><a id="l00401" name="l00401"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a0cef77904935798d247d8396838297c1"> 401</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a0cef77904935798d247d8396838297c1">TRAP_CODE_FIRQ_0</a> = 0x80000010U, </div> +<div class="line"><a id="l00402" name="l00402"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ae0b1049ae7f8cbfb6ff216e69ed5dae7"> 402</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ae0b1049ae7f8cbfb6ff216e69ed5dae7">TRAP_CODE_FIRQ_1</a> = 0x80000011U, </div> +<div class="line"><a id="l00403" name="l00403"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ad753d3e2563b4fd663430af9f3888dc7"> 403</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ad753d3e2563b4fd663430af9f3888dc7">TRAP_CODE_FIRQ_2</a> = 0x80000012U, </div> +<div class="line"><a id="l00404" name="l00404"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a356f8485166529503d0fb246bd0aeeb0"> 404</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a356f8485166529503d0fb246bd0aeeb0">TRAP_CODE_FIRQ_3</a> = 0x80000013U, </div> +<div class="line"><a id="l00405" name="l00405"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aaa8e7bb251852ef75a78be71eef0b547"> 405</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aaa8e7bb251852ef75a78be71eef0b547">TRAP_CODE_FIRQ_4</a> = 0x80000014U, </div> +<div class="line"><a id="l00406" name="l00406"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a5789dfabd8ec265fa0734ddd94e98757"> 406</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a5789dfabd8ec265fa0734ddd94e98757">TRAP_CODE_FIRQ_5</a> = 0x80000015U, </div> +<div class="line"><a id="l00407" name="l00407"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a809e997f55e83c6812c965655511d473"> 407</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a809e997f55e83c6812c965655511d473">TRAP_CODE_FIRQ_6</a> = 0x80000016U, </div> +<div class="line"><a id="l00408" name="l00408"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aeab719bcce9e9551bd6da65a7ae08a26"> 408</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aeab719bcce9e9551bd6da65a7ae08a26">TRAP_CODE_FIRQ_7</a> = 0x80000017U, </div> +<div class="line"><a id="l00409" name="l00409"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1abfd21d1380dcacb9282e525da104d916"> 409</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1abfd21d1380dcacb9282e525da104d916">TRAP_CODE_FIRQ_8</a> = 0x80000018U, </div> +<div class="line"><a id="l00410" name="l00410"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a350e762a599479fb2c6d23ccc5ee22b4"> 410</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a350e762a599479fb2c6d23ccc5ee22b4">TRAP_CODE_FIRQ_9</a> = 0x80000019U, </div> +<div class="line"><a id="l00411" name="l00411"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a4f6b9c6bba91fe04becb776ad22dcf42"> 411</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a4f6b9c6bba91fe04becb776ad22dcf42">TRAP_CODE_FIRQ_10</a> = 0x8000001aU, </div> +<div class="line"><a id="l00412" name="l00412"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a874dcc43cf8fbbf2e0614e7db9e38334"> 412</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a874dcc43cf8fbbf2e0614e7db9e38334">TRAP_CODE_FIRQ_11</a> = 0x8000001bU, </div> +<div class="line"><a id="l00413" name="l00413"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a151f01e5f284f876cafafc7427720e4c"> 413</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a151f01e5f284f876cafafc7427720e4c">TRAP_CODE_FIRQ_12</a> = 0x8000001cU, </div> +<div class="line"><a id="l00414" name="l00414"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a7c8e97297cc4dcd6d5a1de65a124f3e9"> 414</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a7c8e97297cc4dcd6d5a1de65a124f3e9">TRAP_CODE_FIRQ_13</a> = 0x8000001dU, </div> +<div class="line"><a id="l00415" name="l00415"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a821f813de47eb781ab7715f780da3b1e"> 415</a></span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a821f813de47eb781ab7715f780da3b1e">TRAP_CODE_FIRQ_14</a> = 0x8000001eU, </div> +<div class="line"><a id="l00416" name="l00416"></a><span class="lineno"> 416</span> <a class="code hl_enumvalue" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aa4eeafe2f6f59aff01e29461c664a110">TRAP_CODE_FIRQ_15</a> = 0x8000001fU </div> +<div class="line"><a id="l00417" name="l00417"></a><span class="lineno"><a class="line" href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aa4eeafe2f6f59aff01e29461c664a110"> 417</a></span>};</div> +</div> +<div class="line"><a id="l00418" name="l00418"></a><span class="lineno"> 418</span> </div> +<div class="line"><a id="l00419" name="l00419"></a><span class="lineno"> 419</span> </div> +<div class="line"><a id="l00420" name="l00420"></a><span class="lineno"> 420</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_cpu_csr_h</span></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33">NEORV32_CSR_MIE_enum</a></div><div class="ttdeci">NEORV32_CSR_MIE_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:233</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a06fdb61dab31c3490da6c37d47914f19"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a06fdb61dab31c3490da6c37d47914f19">CSR_MIE_FIRQ9E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ9E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:248</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a134ed02c7293008b21b1df472be8f11f"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a134ed02c7293008b21b1df472be8f11f">CSR_MIE_FIRQ13E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ13E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:252</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a3079a8fbf3b8e376865bff76f2173698"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3079a8fbf3b8e376865bff76f2173698">CSR_MIE_FIRQ5E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ5E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:244</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a3658e8663e94cd8eaa7201b7a850d083"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3658e8663e94cd8eaa7201b7a850d083">CSR_MIE_MTIE</a></div><div class="ttdeci">@ CSR_MIE_MTIE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:235</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a396c6c4b425b3fff598e2f846052f98e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a396c6c4b425b3fff598e2f846052f98e">CSR_MIE_FIRQ8E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ8E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:247</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a3d9d729940170609affbc6813054ebe8"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a3d9d729940170609affbc6813054ebe8">CSR_MIE_FIRQ7E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ7E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:246</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a41f91a37f7e0c75c783312af6a72e943"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a41f91a37f7e0c75c783312af6a72e943">CSR_MIE_FIRQ12E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ12E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:251</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a592939f1b7d79097f7f13d6ab0c268dc"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a592939f1b7d79097f7f13d6ab0c268dc">CSR_MIE_FIRQ4E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ4E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:243</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a666066099d6cebadbef21d81c179e8db"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a666066099d6cebadbef21d81c179e8db">CSR_MIE_FIRQ3E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ3E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:242</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a864d135708530016cfc52a65a1e4d79b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a864d135708530016cfc52a65a1e4d79b">CSR_MIE_FIRQ14E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ14E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:253</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a96315d6b5b9531bcbc1e78a3c9ab166a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a96315d6b5b9531bcbc1e78a3c9ab166a">CSR_MIE_FIRQ6E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ6E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:245</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33a99f43f8bbfb29fba6224f081c363ac7d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33a99f43f8bbfb29fba6224f081c363ac7d">CSR_MIE_FIRQ0E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ0E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:239</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33aa2dfa1183af312de2959dadd217fddc1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33aa2dfa1183af312de2959dadd217fddc1">CSR_MIE_FIRQ15E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ15E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:254</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33ac1e1d44becec1b393f79a118ed3d8beb"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33ac1e1d44becec1b393f79a118ed3d8beb">CSR_MIE_FIRQ1E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ1E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:240</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33ae8e4f0ee46abbbb3361de035a57b8324"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33ae8e4f0ee46abbbb3361de035a57b8324">CSR_MIE_MEIE</a></div><div class="ttdeci">@ CSR_MIE_MEIE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:236</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33af058342854a0becd3bcc33877d9244cd"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33af058342854a0becd3bcc33877d9244cd">CSR_MIE_FIRQ11E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ11E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:250</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33afc805280e20ffface116ca61e11645f7"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33afc805280e20ffface116ca61e11645f7">CSR_MIE_FIRQ2E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ2E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:241</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33afd2f1c78c442c8c29ab075cacee0a27a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33afd2f1c78c442c8c29ab075cacee0a27a">CSR_MIE_MSIE</a></div><div class="ttdeci">@ CSR_MIE_MSIE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:234</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a0e9714690687badee43180c3cb62be33affcb52dc57bb8c0cb1e7d3c1392d544a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a0e9714690687badee43180c3cb62be33affcb52dc57bb8c0cb1e7d3c1392d544a">CSR_MIE_FIRQ10E</a></div><div class="ttdeci">@ CSR_MIE_FIRQ10E</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:249</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfe"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfe">NEORV32_HPMCNT_EVENT_enum</a></div><div class="ttdeci">NEORV32_HPMCNT_EVENT_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:345</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea0f15c5a824cb1678423ac4ef72a5f4f5"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea0f15c5a824cb1678423ac4ef72a5f4f5">HPMCNT_EVENT_BRANCHED</a></div><div class="ttdeci">@ HPMCNT_EVENT_BRANCHED</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:353</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea1a06f216e1a12afa0b90d6e1218b3c91"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea1a06f216e1a12afa0b90d6e1218b3c91">HPMCNT_EVENT_LOAD</a></div><div class="ttdeci">@ HPMCNT_EVENT_LOAD</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:354</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea2b683572525adc02ce0910031cfea914"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea2b683572525adc02ce0910031cfea914">HPMCNT_EVENT_CY</a></div><div class="ttdeci">@ HPMCNT_EVENT_CY</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:346</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea3a4f5bf9251def87a71162dbcf9043c5"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea3a4f5bf9251def87a71162dbcf9043c5">HPMCNT_EVENT_TRAP</a></div><div class="ttdeci">@ HPMCNT_EVENT_TRAP</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:357</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea578ef6fc107c22b5cb7be5950f695640"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea578ef6fc107c22b5cb7be5950f695640">HPMCNT_EVENT_TM</a></div><div class="ttdeci">@ HPMCNT_EVENT_TM</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:347</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea67a59934bc66bc7ccf82d24fe8a18a3b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea67a59934bc66bc7ccf82d24fe8a18a3b">HPMCNT_EVENT_WAIT_LSU</a></div><div class="ttdeci">@ HPMCNT_EVENT_WAIT_LSU</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:356</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea685ed663611d988702ec59c254eb61dd"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea685ed663611d988702ec59c254eb61dd">HPMCNT_EVENT_COMPR</a></div><div class="ttdeci">@ HPMCNT_EVENT_COMPR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:349</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea6a942852e3cd85616a63addb8e9d76f2"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea6a942852e3cd85616a63addb8e9d76f2">HPMCNT_EVENT_STORE</a></div><div class="ttdeci">@ HPMCNT_EVENT_STORE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:355</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfea9e1e2b50352b2555e9c64e76776919a6"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfea9e1e2b50352b2555e9c64e76776919a6">HPMCNT_EVENT_BRANCH</a></div><div class="ttdeci">@ HPMCNT_EVENT_BRANCH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:352</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfeaab438295e5f00ffe4c2457a54ee9bfc4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeaab438295e5f00ffe4c2457a54ee9bfc4">HPMCNT_EVENT_IR</a></div><div class="ttdeci">@ HPMCNT_EVENT_IR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:348</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfeabcb123b5b150b4413e5fd48475faab27"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeabcb123b5b150b4413e5fd48475faab27">HPMCNT_EVENT_WAIT_DIS</a></div><div class="ttdeci">@ HPMCNT_EVENT_WAIT_DIS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:350</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a5cb925a3e41efd5e767bb39b3ee60cfeaffbb04d0053ebd079c6cacb4e5e7ed6b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a5cb925a3e41efd5e767bb39b3ee60cfeaffbb04d0053ebd079c6cacb4e5e7ed6b">HPMCNT_EVENT_WAIT_ALU</a></div><div class="ttdeci">@ HPMCNT_EVENT_WAIT_ALU</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:351</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a></div><div class="ttdeci">NEORV32_CSR_MIP_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:261</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba03edd398920b817150d29107c0b40792"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba03edd398920b817150d29107c0b40792">CSR_MIP_FIRQ12P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ12P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:279</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba12da8c32d38d5a3539a0b766718bfd2d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba12da8c32d38d5a3539a0b766718bfd2d">CSR_MIP_FIRQ15P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ15P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:282</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba1470cfe04f9d3ce45b7156b2a7fae159"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba1470cfe04f9d3ce45b7156b2a7fae159">CSR_MIP_MSIP</a></div><div class="ttdeci">@ CSR_MIP_MSIP</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:262</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba14da6a2a962bf82970638a948ffbc570"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba14da6a2a962bf82970638a948ffbc570">CSR_MIP_FIRQ13P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ13P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:280</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba1d761ef98f88c40509168ac66b7a4872"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba1d761ef98f88c40509168ac66b7a4872">CSR_MIP_MEIP</a></div><div class="ttdeci">@ CSR_MIP_MEIP</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:264</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba28a85ad8bd4c30fd3a91298dfa4fdb00"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba28a85ad8bd4c30fd3a91298dfa4fdb00">CSR_MIP_FIRQ0P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ0P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:267</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba2b50cfa8be461b088ea8506ce4c741ba"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba2b50cfa8be461b088ea8506ce4c741ba">CSR_MIP_FIRQ10P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ10P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:277</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba2b577b1da1074c29ad58005af1f91d52"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba2b577b1da1074c29ad58005af1f91d52">CSR_MIP_FIRQ1P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ1P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:268</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba344943c62922561378d33ec51ac236e4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba344943c62922561378d33ec51ac236e4">CSR_MIP_MTIP</a></div><div class="ttdeci">@ CSR_MIP_MTIP</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:263</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba69ea0d3d76d4cec398f3b96959cc3544"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba69ea0d3d76d4cec398f3b96959cc3544">CSR_MIP_FIRQ11P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ11P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:278</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21ba7512bb6c4841ddd477422b49ebb2a155"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21ba7512bb6c4841ddd477422b49ebb2a155">CSR_MIP_FIRQ3P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ3P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:270</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21baaa55d19f9a47889bc364c94bda04b677"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baaa55d19f9a47889bc364c94bda04b677">CSR_MIP_FIRQ5P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ5P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:272</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21baad1e5e452a9c37561308765431f0260d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baad1e5e452a9c37561308765431f0260d">CSR_MIP_FIRQ14P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ14P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:281</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21baad691486001a68f2375dcf5793ee795a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baad691486001a68f2375dcf5793ee795a">CSR_MIP_FIRQ7P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ7P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:274</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21bab6421f242bb8a487a986346e11196eb8"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21bab6421f242bb8a487a986346e11196eb8">CSR_MIP_FIRQ4P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ4P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:271</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21bad94c9691ce59b97fcfec14d345046c3e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21bad94c9691ce59b97fcfec14d345046c3e">CSR_MIP_FIRQ9P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ9P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:276</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21badf45c5a135431f958fa63574c1dfac6e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21badf45c5a135431f958fa63574c1dfac6e">CSR_MIP_FIRQ2P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ2P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:269</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21baf5bbd23d4f311f640db42e9015f87580"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baf5bbd23d4f311f640db42e9015f87580">CSR_MIP_FIRQ8P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ8P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:275</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6301c554bf831b97fc28f9984a1ec21baffa7342631aa0526aaa44c0c549b1f3e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21baffa7342631aa0526aaa44c0c549b1f3e">CSR_MIP_FIRQ6P</a></div><div class="ttdeci">@ CSR_MIP_FIRQ6P</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:273</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6d3c6aaee79b679e954c54563d7ee500"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500">NEORV32_CSR_MCOUNTEREN_enum</a></div><div class="ttdeci">NEORV32_CSR_MCOUNTEREN_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:172</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6d3c6aaee79b679e954c54563d7ee500a3d0c8ff6ba2c557cb5b5d353bdb95790"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500a3d0c8ff6ba2c557cb5b5d353bdb95790">CSR_MCOUNTEREN_CY</a></div><div class="ttdeci">@ CSR_MCOUNTEREN_CY</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:173</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a6d3c6aaee79b679e954c54563d7ee500a97e36c94b71fa2f9a805bbe47b0bc1b5"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a6d3c6aaee79b679e954c54563d7ee500a97e36c94b71fa2f9a805bbe47b0bc1b5">CSR_MCOUNTEREN_IR</a></div><div class="ttdeci">@ CSR_MCOUNTEREN_IR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:174</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a76b70a2334131e7589d84c1ee96de485"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485">NEORV32_CSR_MSTATUS_enum</a></div><div class="ttdeci">NEORV32_CSR_MSTATUS_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:181</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a76b70a2334131e7589d84c1ee96de485a75cefdbdef36b7fc248765b27c606a44"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485a75cefdbdef36b7fc248765b27c606a44">CSR_MSTATUS_MPRV</a></div><div class="ttdeci">@ CSR_MSTATUS_MPRV</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:186</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a76b70a2334131e7589d84c1ee96de485a8067c609c2360cab3bafa3c43e03dbf0"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485a8067c609c2360cab3bafa3c43e03dbf0">CSR_MSTATUS_MPP_H</a></div><div class="ttdeci">@ CSR_MSTATUS_MPP_H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:185</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a76b70a2334131e7589d84c1ee96de485aaa1d482f828ac9cafc40fcfc298bec34"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485aaa1d482f828ac9cafc40fcfc298bec34">CSR_MSTATUS_MPIE</a></div><div class="ttdeci">@ CSR_MSTATUS_MPIE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:183</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a76b70a2334131e7589d84c1ee96de485ac94a070f3fe7962e8c49a81545cacf2d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485ac94a070f3fe7962e8c49a81545cacf2d">CSR_MSTATUS_TW</a></div><div class="ttdeci">@ CSR_MSTATUS_TW</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:187</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a76b70a2334131e7589d84c1ee96de485ae2603e365b3f1abfb46d53ed6b13dc56"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485ae2603e365b3f1abfb46d53ed6b13dc56">CSR_MSTATUS_MIE</a></div><div class="ttdeci">@ CSR_MSTATUS_MIE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:182</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a76b70a2334131e7589d84c1ee96de485af0ae9aca74144aa7dbdf656f71cc5c97"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a76b70a2334131e7589d84c1ee96de485af0ae9aca74144aa7dbdf656f71cc5c97">CSR_MSTATUS_MPP_L</a></div><div class="ttdeci">@ CSR_MSTATUS_MPP_L</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:184</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a8f2418fb5e2175f35ee2362469ce01f5"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5">NEORV32_PMP_MODES_enum</a></div><div class="ttdeci">NEORV32_PMP_MODES_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:376</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a8f2418fb5e2175f35ee2362469ce01f5a003ccfae4aae1dad4fd65d5d4c7737c4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5a003ccfae4aae1dad4fd65d5d4c7737c4">PMP_OFF</a></div><div class="ttdeci">@ PMP_OFF</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:377</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a8f2418fb5e2175f35ee2362469ce01f5a629a81a205abee94bad9d5bb5dfa26b1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5a629a81a205abee94bad9d5bb5dfa26b1">PMP_TOR</a></div><div class="ttdeci">@ PMP_TOR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:378</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a8f2418fb5e2175f35ee2362469ce01f5aae0e0c33b0d034cb50286239f955d892"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5aae0e0c33b0d034cb50286239f955d892">PMP_NA4</a></div><div class="ttdeci">@ PMP_NA4</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:379</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_a8f2418fb5e2175f35ee2362469ce01f5ad555e9dfc0c00612bdea623617ff2820"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#a8f2418fb5e2175f35ee2362469ce01f5ad555e9dfc0c00612bdea623617ff2820">PMP_NAPOT</a></div><div class="ttdeci">@ PMP_NAPOT</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:380</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfe"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfe">NEORV32_CSR_MCOUNTINHIBIT_enum</a></div><div class="ttdeci">NEORV32_CSR_MCOUNTINHIBIT_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:194</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea0b547cb5876c0e7956e3d062e0784085"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0b547cb5876c0e7956e3d062e0784085">CSR_MCOUNTINHIBIT_HPM15</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM15</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:210</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea0f207455df0fed75fa68ba49c435889a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0f207455df0fed75fa68ba49c435889a">CSR_MCOUNTINHIBIT_HPM9</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM9</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:204</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea0f45818fa4cb9033a3093987fa8515c7"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea0f45818fa4cb9033a3093987fa8515c7">CSR_MCOUNTINHIBIT_HPM30</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM30</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:225</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea141a4a211c496d2af1c79d8e8e0c2a74"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea141a4a211c496d2af1c79d8e8e0c2a74">CSR_MCOUNTINHIBIT_HPM26</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM26</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:221</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea1da1186ef2f4e7297a4fecaaccdc1d05"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea1da1186ef2f4e7297a4fecaaccdc1d05">CSR_MCOUNTINHIBIT_HPM31</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM31</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:226</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea1dc0276a5354c805ac56fd46c5037d38"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea1dc0276a5354c805ac56fd46c5037d38">CSR_MCOUNTINHIBIT_HPM21</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM21</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:216</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea201ac39b0eba389b0d02c3951a3311a3"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea201ac39b0eba389b0d02c3951a3311a3">CSR_MCOUNTINHIBIT_CY</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_CY</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:195</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea2769a6e6a75f2f903523e4e95a899bb6"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea2769a6e6a75f2f903523e4e95a899bb6">CSR_MCOUNTINHIBIT_HPM5</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM5</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:200</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea33d0fd3378ec3a2fcc3c8738c6cd2f32"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea33d0fd3378ec3a2fcc3c8738c6cd2f32">CSR_MCOUNTINHIBIT_HPM28</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM28</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:223</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea3683e296caafe771b6dd57f4cf86f3dc"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea3683e296caafe771b6dd57f4cf86f3dc">CSR_MCOUNTINHIBIT_HPM19</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM19</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:214</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea3b3571fceb687da2d3807b0e59bdf7ab"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea3b3571fceb687da2d3807b0e59bdf7ab">CSR_MCOUNTINHIBIT_HPM7</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM7</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:202</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea40427b799da049413c5536afa623c61d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea40427b799da049413c5536afa623c61d">CSR_MCOUNTINHIBIT_HPM4</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM4</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:199</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea46def851d4582b4bcec1f9d8bafd58db"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea46def851d4582b4bcec1f9d8bafd58db">CSR_MCOUNTINHIBIT_HPM27</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM27</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:222</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea5f182f39f9a4b871a097a51e57865bfa"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea5f182f39f9a4b871a097a51e57865bfa">CSR_MCOUNTINHIBIT_IR</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_IR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:196</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea68aba71ea77aba4005fb24a945ef38e4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea68aba71ea77aba4005fb24a945ef38e4">CSR_MCOUNTINHIBIT_HPM16</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM16</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:211</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea74ec85a2e94aa0b9e8af29401ef7ecb1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea74ec85a2e94aa0b9e8af29401ef7ecb1">CSR_MCOUNTINHIBIT_HPM24</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM24</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:219</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea85c0c2b2a5101380dec72516dda1a904"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea85c0c2b2a5101380dec72516dda1a904">CSR_MCOUNTINHIBIT_HPM23</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM23</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:218</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea8d57acf13a086635a63bc13ccdf479b3"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea8d57acf13a086635a63bc13ccdf479b3">CSR_MCOUNTINHIBIT_HPM17</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM17</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:212</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea8d866a4c815d8ba890a1e00ce9600486"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea8d866a4c815d8ba890a1e00ce9600486">CSR_MCOUNTINHIBIT_HPM12</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM12</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:207</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfea9517cd32744c5064fa30780f911cd22e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfea9517cd32744c5064fa30780f911cd22e">CSR_MCOUNTINHIBIT_HPM10</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM10</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:205</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeaa39882f7dad9b7e16b317c75bad31382"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa39882f7dad9b7e16b317c75bad31382">CSR_MCOUNTINHIBIT_HPM29</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM29</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:224</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeaa680d196d2ba0e403801a860bb9d8ce0"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa680d196d2ba0e403801a860bb9d8ce0">CSR_MCOUNTINHIBIT_HPM18</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM18</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:213</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeaa83c0688869b1c43de0c4474e940f987"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaa83c0688869b1c43de0c4474e940f987">CSR_MCOUNTINHIBIT_HPM14</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM14</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:209</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeabd21344124eda4402523203185a58b8a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeabd21344124eda4402523203185a58b8a">CSR_MCOUNTINHIBIT_HPM8</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM8</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:203</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeacaf997fe8b912596224e2bb632e6a806"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeacaf997fe8b912596224e2bb632e6a806">CSR_MCOUNTINHIBIT_HPM11</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM11</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:206</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfead55b6af15841617d7dca3ab4fab893db"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfead55b6af15841617d7dca3ab4fab893db">CSR_MCOUNTINHIBIT_HPM6</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM6</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:201</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfead9f6c4eb4284ee82b9e8d0c79f62b3ed"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfead9f6c4eb4284ee82b9e8d0c79f62b3ed">CSR_MCOUNTINHIBIT_HPM13</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM13</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:208</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeaeb4b1b6abafd22eec0764d5503878cca"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaeb4b1b6abafd22eec0764d5503878cca">CSR_MCOUNTINHIBIT_HPM20</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM20</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:215</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeaee2b5a2b7bd7ac07dae45900bc2faf46"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaee2b5a2b7bd7ac07dae45900bc2faf46">CSR_MCOUNTINHIBIT_HPM25</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM25</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:220</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeaf1b6153a0c664367bfefb78b2ca8b34e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaf1b6153a0c664367bfefb78b2ca8b34e">CSR_MCOUNTINHIBIT_HPM22</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM22</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:217</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ab6886ca6858d57854495986ef9b5cbfeaf7020159e0ba346561bfba101d22c752"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ab6886ca6858d57854495986ef9b5cbfeaf7020159e0ba346561bfba101d22c752">CSR_MCOUNTINHIBIT_HPM3</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT_HPM3</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:198</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_abc0e8daad1e9beda4d9950452cc930ea"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930ea">NEORV32_PMPCFG_ATTRIBUTES_enum</a></div><div class="ttdeci">NEORV32_PMPCFG_ATTRIBUTES_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:364</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_abc0e8daad1e9beda4d9950452cc930eaa59c294bc43d2117bb55e301eec683f14"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa59c294bc43d2117bb55e301eec683f14">PMPCFG_L</a></div><div class="ttdeci">@ PMPCFG_L</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:370</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_abc0e8daad1e9beda4d9950452cc930eaa67ad3243eeb74f86a01efbade76f21e4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa67ad3243eeb74f86a01efbade76f21e4">PMPCFG_A_MSB</a></div><div class="ttdeci">@ PMPCFG_A_MSB</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:369</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_abc0e8daad1e9beda4d9950452cc930eaa7689905760f917499b1151cced384d2f"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaa7689905760f917499b1151cced384d2f">PMPCFG_W</a></div><div class="ttdeci">@ PMPCFG_W</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:366</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_abc0e8daad1e9beda4d9950452cc930eaaae1e6440956ad6b7cbf6062aa50f43b1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaaae1e6440956ad6b7cbf6062aa50f43b1">PMPCFG_A_LSB</a></div><div class="ttdeci">@ PMPCFG_A_LSB</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:368</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_abc0e8daad1e9beda4d9950452cc930eaad3aca82a2ab57364e83f677d3d4f71a6"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaad3aca82a2ab57364e83f677d3d4f71a6">PMPCFG_R</a></div><div class="ttdeci">@ PMPCFG_R</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:365</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_abc0e8daad1e9beda4d9950452cc930eaaec94712deafba09c0cf956c6fd68fa8d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#abc0e8daad1e9beda4d9950452cc930eaaec94712deafba09c0cf956c6fd68fa8d">PMPCFG_X</a></div><div class="ttdeci">@ PMPCFG_X</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:367</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49">NEORV32_CSR_enum</a></div><div class="ttdeci">NEORV32_CSR_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:25</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a0545d0921b3f90d037dbb25bc5fcc2f9"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0545d0921b3f90d037dbb25bc5fcc2f9">CSR_MCONFIGPTR</a></div><div class="ttdeci">@ CSR_MCONFIGPTR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:152</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a067ed3778590ae97dc9b16069f0ed850"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a067ed3778590ae97dc9b16069f0ed850">CSR_PMPCFG3</a></div><div class="ttdeci">@ CSR_PMPCFG3</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:71</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a06d39cf0f13d6401dcf426d56149c8cd"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a06d39cf0f13d6401dcf426d56149c8cd">CSR_MIMPID</a></div><div class="ttdeci">@ CSR_MIMPID</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:150</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a06dfdeed757606529e4a99c033691b54"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a06dfdeed757606529e4a99c033691b54">CSR_MHPMEVENT15</a></div><div class="ttdeci">@ CSR_MHPMEVENT15</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:57</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a0c9492f6b956f088847f72b28e7b1446"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0c9492f6b956f088847f72b28e7b1446">CSR_PMPCFG2</a></div><div class="ttdeci">@ CSR_PMPCFG2</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:70</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a0f4a1ae740efd80d14d21e90f355e9d7"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a0f4a1ae740efd80d14d21e90f355e9d7">CSR_DSCRATCH0</a></div><div class="ttdeci">@ CSR_DSCRATCH0</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:99</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a1328a226d36d23cc81740397bde47a4e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1328a226d36d23cc81740397bde47a4e">CSR_MHPMCOUNTER12</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER12</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:119</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a1860dd9579906c67a3565063043dcf78"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1860dd9579906c67a3565063043dcf78">CSR_MCOUNTEREN</a></div><div class="ttdeci">@ CSR_MCOUNTEREN</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:36</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a18c2a249f1f7852f42f9e10dc59d46bb"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a18c2a249f1f7852f42f9e10dc59d46bb">CSR_MHPMCOUNTER9</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER9</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:116</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a1cfa1e3bc3c8a1c9a86c251a510d11cd"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1cfa1e3bc3c8a1c9a86c251a510d11cd">CSR_MHPMEVENT6</a></div><div class="ttdeci">@ CSR_MHPMEVENT6</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:48</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a1e41d2b27d7e8da14871852d81123cfd"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a1e41d2b27d7e8da14871852d81123cfd">CSR_MHPMCOUNTER10H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER10H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:133</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a20400929087fabba410a098667d2d4ff"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a20400929087fabba410a098667d2d4ff">CSR_MHPMCOUNTER15</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER15</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:122</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a22eea318ec1ac72cc14e133b71ef4b16"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a22eea318ec1ac72cc14e133b71ef4b16">CSR_PMPCFG1</a></div><div class="ttdeci">@ CSR_PMPCFG1</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:69</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a23026793ee53c8d55d23f63195368a6b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a23026793ee53c8d55d23f63195368a6b">CSR_PMPADDR12</a></div><div class="ttdeci">@ CSR_PMPADDR12</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:85</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a23850b1804966cde2c1e84cde752d512"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a23850b1804966cde2c1e84cde752d512">CSR_MHPMEVENT10</a></div><div class="ttdeci">@ CSR_MHPMEVENT10</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:52</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a2524659ca2785af51af7acf9cd560a9d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2524659ca2785af51af7acf9cd560a9d">CSR_MHPMEVENT5</a></div><div class="ttdeci">@ CSR_MHPMEVENT5</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:47</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a252980a4da90c1f5c1ef85d164f72f25"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a252980a4da90c1f5c1ef85d164f72f25">CSR_MHPMCOUNTER3H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER3H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:126</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a28fcfd06ca1012c19cf053e57689687b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a28fcfd06ca1012c19cf053e57689687b">CSR_MCYCLEH</a></div><div class="ttdeci">@ CSR_MCYCLEH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:124</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a2e14b57fee5376741634db7980a5005b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e14b57fee5376741634db7980a5005b">CSR_MCAUSE</a></div><div class="ttdeci">@ CSR_MCAUSE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:62</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a2e53e6e01ca8d1b801f6dfba602f3f59"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e53e6e01ca8d1b801f6dfba602f3f59">CSR_MHPMEVENT7</a></div><div class="ttdeci">@ CSR_MHPMEVENT7</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:49</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a2e9cfbf3c2828dd4bd92d2b8a1c99f85"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a2e9cfbf3c2828dd4bd92d2b8a1c99f85">CSR_MHPMCOUNTER4H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER4H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:127</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a30879e88b250d3e94d9d9e728ffcc2cc"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a30879e88b250d3e94d9d9e728ffcc2cc">CSR_PMPADDR13</a></div><div class="ttdeci">@ CSR_PMPADDR13</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:86</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a32c22641ed66c6d20902306a2b1fad77"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a32c22641ed66c6d20902306a2b1fad77">CSR_MCYCLE</a></div><div class="ttdeci">@ CSR_MCYCLE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:108</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a332ec2b0740f8e899a1b2ec86f7ee9f2"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a332ec2b0740f8e899a1b2ec86f7ee9f2">CSR_MHPMCOUNTER12H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER12H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:135</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a382304065a6db773f925b80b9447b8a8"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a382304065a6db773f925b80b9447b8a8">CSR_CFUREG1</a></div><div class="ttdeci">@ CSR_CFUREG1</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:103</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a396847bcf1634a1602ab117bfb57bdd2"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a396847bcf1634a1602ab117bfb57bdd2">CSR_MXISA</a></div><div class="ttdeci">@ CSR_MXISA</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:153</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a3ce1dc0e2810f0df78feaa1c607a5ca6"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a3ce1dc0e2810f0df78feaa1c607a5ca6">CSR_MCOUNTINHIBIT</a></div><div class="ttdeci">@ CSR_MCOUNTINHIBIT</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:38</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a3e5708c0f79cf58ae761b6bb8c2a4383"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a3e5708c0f79cf58ae761b6bb8c2a4383">CSR_PMPADDR11</a></div><div class="ttdeci">@ CSR_PMPADDR11</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:84</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a427d7cf036b49efd46166c01f0504b68"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a427d7cf036b49efd46166c01f0504b68">CSR_CFUREG2</a></div><div class="ttdeci">@ CSR_CFUREG2</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:104</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a46b8d3c288cbbfbf5a0af6e5cd8c5bc8"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a46b8d3c288cbbfbf5a0af6e5cd8c5bc8">CSR_MENVCFGH</a></div><div class="ttdeci">@ CSR_MENVCFGH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:42</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a49b7bc2df67a6c73a68757de9b218f77"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a49b7bc2df67a6c73a68757de9b218f77">CSR_MHPMCOUNTER6H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER6H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:129</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a4a93ac5ab276cfd2f9cd296c8ce1bff6"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a4a93ac5ab276cfd2f9cd296c8ce1bff6">CSR_MHPMEVENT3</a></div><div class="ttdeci">@ CSR_MHPMEVENT3</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:45</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a4f229c169ada239033a1383412ce58c8"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a4f229c169ada239033a1383412ce58c8">CSR_MTINST</a></div><div class="ttdeci">@ CSR_MTINST</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:65</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a54d38c8cf364d886eb7ac64463eedf77"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a54d38c8cf364d886eb7ac64463eedf77">CSR_PMPADDR9</a></div><div class="ttdeci">@ CSR_PMPADDR9</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:82</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a575e5342d8ec304c32dbbe99d6fd6c0f"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a575e5342d8ec304c32dbbe99d6fd6c0f">CSR_MHPMCOUNTER10</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER10</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:117</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a5a4cde90c547e913bddc719b3ab75e79"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5a4cde90c547e913bddc719b3ab75e79">CSR_MHPMCOUNTER8</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER8</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:115</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a5d60a25a66754066589e8facb7d41153"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5d60a25a66754066589e8facb7d41153">CSR_MEPC</a></div><div class="ttdeci">@ CSR_MEPC</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:61</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a5de5c5a036dc594a554d37df9ccf657d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5de5c5a036dc594a554d37df9ccf657d">CSR_MHPMCOUNTER13H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER13H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:136</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a5e1abf46b4f55bd18e1d132b32696ab6"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a5e1abf46b4f55bd18e1d132b32696ab6">CSR_FCSR</a></div><div class="ttdeci">@ CSR_FCSR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:29</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a625f606c14fd4d7224d7109e10508e7a">CSR_FFLAGS</a></div><div class="ttdeci">@ CSR_FFLAGS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:27</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a6879b4bf5d2db92d236b9091df4841f2"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6879b4bf5d2db92d236b9091df4841f2">CSR_PMPADDR15</a></div><div class="ttdeci">@ CSR_PMPADDR15</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:88</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a6a2933f3a1fa243de02db8a795e3ca41"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6a2933f3a1fa243de02db8a795e3ca41">CSR_PMPADDR1</a></div><div class="ttdeci">@ CSR_PMPADDR1</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:74</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a6ba48e2306ae92f498552e1ea04d6790"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6ba48e2306ae92f498552e1ea04d6790">CSR_MHARTID</a></div><div class="ttdeci">@ CSR_MHARTID</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:151</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a6bb3ba59a25803d6f98faad67609a9a9"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a6bb3ba59a25803d6f98faad67609a9a9">CSR_DCSR</a></div><div class="ttdeci">@ CSR_DCSR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:97</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a7341886c7a4aed6fc7d8677c016a2cb8"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7341886c7a4aed6fc7d8677c016a2cb8">CSR_MHPMCOUNTER9H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER9H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:132</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a7648dd0a47007d44a14e95ba47726599"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7648dd0a47007d44a14e95ba47726599">CSR_MHPMCOUNTER5H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER5H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:128</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a76d30359e3b54197fb53f9939734cf1e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a76d30359e3b54197fb53f9939734cf1e">CSR_MTVAL</a></div><div class="ttdeci">@ CSR_MTVAL</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:63</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a7f198c465959dde37b7056dd06d45812"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7f198c465959dde37b7056dd06d45812">CSR_FRM</a></div><div class="ttdeci">@ CSR_FRM</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:28</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a7fb1de2019dd2b548084d5ca1630efbf"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7fb1de2019dd2b548084d5ca1630efbf">CSR_MHPMEVENT11</a></div><div class="ttdeci">@ CSR_MHPMEVENT11</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:53</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a7fd76fcfc0d0dd47e112786bea5e4071"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a7fd76fcfc0d0dd47e112786bea5e4071">CSR_MHPMCOUNTER11H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER11H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:134</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a80eab0e17f5fe41edde485044674dc57"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a80eab0e17f5fe41edde485044674dc57">CSR_TDATA1</a></div><div class="ttdeci">@ CSR_TDATA1</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:92</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a8144da8cd8691ac54aa0712685865b66"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8144da8cd8691ac54aa0712685865b66">CSR_INSTRET</a></div><div class="ttdeci">@ CSR_INSTRET</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:142</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a8840b3d4f45453fc96813ccb369a68e5"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8840b3d4f45453fc96813ccb369a68e5">CSR_MHPMCOUNTER11</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER11</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:118</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a8941071db6145d34fff842249c0dcb9f"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8941071db6145d34fff842249c0dcb9f">CSR_PMPADDR0</a></div><div class="ttdeci">@ CSR_PMPADDR0</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:73</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a89bad989197e9358563557311b3c97e9"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a89bad989197e9358563557311b3c97e9">CSR_PMPADDR3</a></div><div class="ttdeci">@ CSR_PMPADDR3</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:76</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a8c31899b81bb5dba9b92a0f0ca71aea6"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a8c31899b81bb5dba9b92a0f0ca71aea6">CSR_MHPMEVENT13</a></div><div class="ttdeci">@ CSR_MHPMEVENT13</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:55</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a919f39b0d299feb80403b42a466de444"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a919f39b0d299feb80403b42a466de444">CSR_MHPMCOUNTER7</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER7</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:114</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a91a8b5008b4e08ab34c1516e21bf0ba8"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a91a8b5008b4e08ab34c1516e21bf0ba8">CSR_PMPADDR14</a></div><div class="ttdeci">@ CSR_PMPADDR14</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:87</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a964a6a50d0138447fad47e9c982a7ba4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a964a6a50d0138447fad47e9c982a7ba4">CSR_MHPMEVENT14</a></div><div class="ttdeci">@ CSR_MHPMEVENT14</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:56</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a98f5e2cf2d5dbb0125a222b0065c86eb"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a98f5e2cf2d5dbb0125a222b0065c86eb">CSR_MINSTRET</a></div><div class="ttdeci">@ CSR_MINSTRET</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:109</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a9b66978d76260283007d399fc735d153"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9b66978d76260283007d399fc735d153">CSR_INSTRETH</a></div><div class="ttdeci">@ CSR_INSTRETH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:145</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a9b84bd948dd52a7779b5fd16beddaab9"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9b84bd948dd52a7779b5fd16beddaab9">CSR_MHPMCOUNTER4</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER4</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:111</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a9bdd102877ff50d38c86c3d741aeb4b0"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9bdd102877ff50d38c86c3d741aeb4b0">CSR_MHPMCOUNTER13</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER13</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:120</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a9c55619ffb05e84b7210e2d47326fa98"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9c55619ffb05e84b7210e2d47326fa98">CSR_MENVCFG</a></div><div class="ttdeci">@ CSR_MENVCFG</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:41</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49a9e75518df7d14a009e3a0d5588641ddc"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49a9e75518df7d14a009e3a0d5588641ddc">CSR_MHPMCOUNTER8H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER8H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:131</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49aa0b8c0561e8a778dce9c3b86499ffc50"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa0b8c0561e8a778dce9c3b86499ffc50">CSR_PMPADDR2</a></div><div class="ttdeci">@ CSR_PMPADDR2</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:75</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49aa276bedb7dab28935163397b4879f6db"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa276bedb7dab28935163397b4879f6db">CSR_CYCLEH</a></div><div class="ttdeci">@ CSR_CYCLEH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:144</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49aa632d218400268df6dc6b289ff088d21"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aa632d218400268df6dc6b289ff088d21">CSR_MTVEC</a></div><div class="ttdeci">@ CSR_MTVEC</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:35</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49aaae2f0b2e3f5a31dff933868873f6d5d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aaae2f0b2e3f5a31dff933868873f6d5d">CSR_TSELECT</a></div><div class="ttdeci">@ CSR_TSELECT</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:91</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49aaaf0f6b17a06d5922bcfdb47b382137e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aaaf0f6b17a06d5922bcfdb47b382137e">CSR_CYCLE</a></div><div class="ttdeci">@ CSR_CYCLE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:141</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ab5f998725e002ffc2ff516ee973fe459"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ab5f998725e002ffc2ff516ee973fe459">CSR_MHPMEVENT4</a></div><div class="ttdeci">@ CSR_MHPMEVENT4</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:46</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ac0183bb6f357ed33136493ae7ded987a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac0183bb6f357ed33136493ae7ded987a">CSR_MHPMCOUNTER7H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER7H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:130</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ac2541060307369b2031e9ec07bbd0067"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac2541060307369b2031e9ec07bbd0067">CSR_MSTATUSH</a></div><div class="ttdeci">@ CSR_MSTATUSH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:37</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ac65bab6fd71439600c8fc549171251fa"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ac65bab6fd71439600c8fc549171251fa">CSR_MHPMCOUNTER14H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER14H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:137</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49acc0f9f5f3b5702f1b57f2ba3b6b62610"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49acc0f9f5f3b5702f1b57f2ba3b6b62610">CSR_MIE</a></div><div class="ttdeci">@ CSR_MIE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:34</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ace4529c53ad2d46767f86d920eada507"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ace4529c53ad2d46767f86d920eada507">CSR_PMPADDR4</a></div><div class="ttdeci">@ CSR_PMPADDR4</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:77</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49acf336638697242b691b691dc56b9aadc"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49acf336638697242b691b691dc56b9aadc">CSR_TDATA2</a></div><div class="ttdeci">@ CSR_TDATA2</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:93</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ad0e5de789d6390f750b8af03cdd15450"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad0e5de789d6390f750b8af03cdd15450">CSR_MSTATUS</a></div><div class="ttdeci">@ CSR_MSTATUS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:32</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ad6296ca83bbe1280624f3c21adbd8a79"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad6296ca83bbe1280624f3c21adbd8a79">CSR_MHPMEVENT8</a></div><div class="ttdeci">@ CSR_MHPMEVENT8</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:50</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ad648b5ece209d47e9484fd7aa83e8e5f"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad648b5ece209d47e9484fd7aa83e8e5f">CSR_MHPMEVENT12</a></div><div class="ttdeci">@ CSR_MHPMEVENT12</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:54</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ad95cb95266533123447ff0e917f890e4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad95cb95266533123447ff0e917f890e4">CSR_MARCHID</a></div><div class="ttdeci">@ CSR_MARCHID</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:149</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ad97b6fe934a3bed6b02d0c8d81165d60"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad97b6fe934a3bed6b02d0c8d81165d60">CSR_PMPADDR10</a></div><div class="ttdeci">@ CSR_PMPADDR10</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:83</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ad9e78f71409fd7783cc2ae7c28b5e42c"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ad9e78f71409fd7783cc2ae7c28b5e42c">CSR_PMPADDR5</a></div><div class="ttdeci">@ CSR_PMPADDR5</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:78</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49adae22d860d8162e15120051951e45229"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49adae22d860d8162e15120051951e45229">CSR_MHPMCOUNTER14</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER14</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:121</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49addb485275c954d1181d5bd4e4609082c"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49addb485275c954d1181d5bd4e4609082c">CSR_MIP</a></div><div class="ttdeci">@ CSR_MIP</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:64</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ade079242596ce14ce1ba9842ed29b84c"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ade079242596ce14ce1ba9842ed29b84c">CSR_MISA</a></div><div class="ttdeci">@ CSR_MISA</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:33</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ae0a96f499dcde474af6ee620fbb1ebdc"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae0a96f499dcde474af6ee620fbb1ebdc">CSR_MHPMCOUNTER3</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER3</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:110</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ae0e9cf0b99b8614ea0b870d38970281f"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae0e9cf0b99b8614ea0b870d38970281f">CSR_CFUREG0</a></div><div class="ttdeci">@ CSR_CFUREG0</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:102</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ae29976bb072639975ad0cdb985c7f004"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae29976bb072639975ad0cdb985c7f004">CSR_MSCRATCH</a></div><div class="ttdeci">@ CSR_MSCRATCH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:60</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49ae8ea19cf3e527dbc0d36a43dfd1b7346"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49ae8ea19cf3e527dbc0d36a43dfd1b7346">CSR_PMPADDR7</a></div><div class="ttdeci">@ CSR_PMPADDR7</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:80</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49aec68bf7e26e44170c24599f7c6a8365b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aec68bf7e26e44170c24599f7c6a8365b">CSR_PMPADDR8</a></div><div class="ttdeci">@ CSR_PMPADDR8</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:81</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49aefefa1cff0cf5d01109486e5a8bebedf"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49aefefa1cff0cf5d01109486e5a8bebedf">CSR_CFUREG3</a></div><div class="ttdeci">@ CSR_CFUREG3</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:105</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af15d389bb8f91c989df488d231666394"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af15d389bb8f91c989df488d231666394">CSR_MHPMCOUNTER5</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER5</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:112</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af1a79349e46a4829af78d2cdfd0dc44f"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af1a79349e46a4829af78d2cdfd0dc44f">CSR_PMPCFG0</a></div><div class="ttdeci">@ CSR_PMPCFG0</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:68</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af4c98d949d2eb44f2518fdf314344d3b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af4c98d949d2eb44f2518fdf314344d3b">CSR_DPC</a></div><div class="ttdeci">@ CSR_DPC</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:98</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af57b5b7b57cd6e8b3489a27dfd702444"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af57b5b7b57cd6e8b3489a27dfd702444">CSR_PMPADDR6</a></div><div class="ttdeci">@ CSR_PMPADDR6</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:79</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af5c5a21909aaca2b57f9a15f4bac246b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af5c5a21909aaca2b57f9a15f4bac246b">CSR_MVENDORID</a></div><div class="ttdeci">@ CSR_MVENDORID</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:148</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af609807e2917f73e27e5f27b38a0fa46"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af609807e2917f73e27e5f27b38a0fa46">CSR_MHPMCOUNTER15H</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER15H</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:138</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af65b9e99b9cadb3cb8d37f97cdbfeb9d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af65b9e99b9cadb3cb8d37f97cdbfeb9d">CSR_MHPMCOUNTER6</a></div><div class="ttdeci">@ CSR_MHPMCOUNTER6</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:113</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af6727a9bdd60ccf020812095b7396632"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af6727a9bdd60ccf020812095b7396632">CSR_MHPMEVENT9</a></div><div class="ttdeci">@ CSR_MHPMEVENT9</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:51</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49af67c819c104f7e3ec34f2cbb847cf83b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49af67c819c104f7e3ec34f2cbb847cf83b">CSR_TINFO</a></div><div class="ttdeci">@ CSR_TINFO</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:94</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_ac065a8cc32eed9a69ea1798492a69f49afffb28b62b9baa127ae3bad919208988"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#ac065a8cc32eed9a69ea1798492a69f49afffb28b62b9baa127ae3bad919208988">CSR_MINSTRETH</a></div><div class="ttdeci">@ CSR_MINSTRETH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:125</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1">NEORV32_EXCEPTION_CODES_enum</a></div><div class="ttdeci">NEORV32_EXCEPTION_CODES_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:387</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a0a8010d7cc91b9557973a7a118828bee"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a0a8010d7cc91b9557973a7a118828bee">TRAP_CODE_I_MISALIGNED</a></div><div class="ttdeci">@ TRAP_CODE_I_MISALIGNED</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:388</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a0cef77904935798d247d8396838297c1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a0cef77904935798d247d8396838297c1">TRAP_CODE_FIRQ_0</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_0</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:401</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a151f01e5f284f876cafafc7427720e4c"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a151f01e5f284f876cafafc7427720e4c">TRAP_CODE_FIRQ_12</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_12</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:413</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a187ae38819b81672c15808e63c3b46b7"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a187ae38819b81672c15808e63c3b46b7">TRAP_CODE_MTI</a></div><div class="ttdeci">@ TRAP_CODE_MTI</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:399</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a19708405f9f6300edf6b992c6d408a2d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a19708405f9f6300edf6b992c6d408a2d">TRAP_CODE_S_MISALIGNED</a></div><div class="ttdeci">@ TRAP_CODE_S_MISALIGNED</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:394</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a1a412b9d8eefba7880555d34625d2cc0"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a1a412b9d8eefba7880555d34625d2cc0">TRAP_CODE_MEI</a></div><div class="ttdeci">@ TRAP_CODE_MEI</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:400</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a20e5a2680f2f5956bfa92852d5544eac"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a20e5a2680f2f5956bfa92852d5544eac">TRAP_CODE_MENV_CALL</a></div><div class="ttdeci">@ TRAP_CODE_MENV_CALL</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:397</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a28448f0c670169140dc28b6794310cea"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a28448f0c670169140dc28b6794310cea">TRAP_CODE_L_ACCESS</a></div><div class="ttdeci">@ TRAP_CODE_L_ACCESS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:393</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a2c9510cb7583a0144f96678fc217335e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a2c9510cb7583a0144f96678fc217335e">TRAP_CODE_BREAKPOINT</a></div><div class="ttdeci">@ TRAP_CODE_BREAKPOINT</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:391</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a350e762a599479fb2c6d23ccc5ee22b4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a350e762a599479fb2c6d23ccc5ee22b4">TRAP_CODE_FIRQ_9</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_9</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:410</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a356f8485166529503d0fb246bd0aeeb0"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a356f8485166529503d0fb246bd0aeeb0">TRAP_CODE_FIRQ_3</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_3</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:404</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a4f6b9c6bba91fe04becb776ad22dcf42"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a4f6b9c6bba91fe04becb776ad22dcf42">TRAP_CODE_FIRQ_10</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_10</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:411</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a5789dfabd8ec265fa0734ddd94e98757"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a5789dfabd8ec265fa0734ddd94e98757">TRAP_CODE_FIRQ_5</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_5</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:406</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a69e68a954da0bb33d1624484a6777ff9"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a69e68a954da0bb33d1624484a6777ff9">TRAP_CODE_L_MISALIGNED</a></div><div class="ttdeci">@ TRAP_CODE_L_MISALIGNED</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:392</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a6a0ebfce4e18f36aeb43d5a65445cfe1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a6a0ebfce4e18f36aeb43d5a65445cfe1">TRAP_CODE_I_ACCESS</a></div><div class="ttdeci">@ TRAP_CODE_I_ACCESS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:389</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a70bcfc75fe1056d93a3606f78c0cb887"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a70bcfc75fe1056d93a3606f78c0cb887">TRAP_CODE_S_ACCESS</a></div><div class="ttdeci">@ TRAP_CODE_S_ACCESS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:395</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a7c8e97297cc4dcd6d5a1de65a124f3e9"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a7c8e97297cc4dcd6d5a1de65a124f3e9">TRAP_CODE_FIRQ_13</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_13</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:414</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a809e997f55e83c6812c965655511d473"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a809e997f55e83c6812c965655511d473">TRAP_CODE_FIRQ_6</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_6</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:407</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a821f813de47eb781ab7715f780da3b1e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a821f813de47eb781ab7715f780da3b1e">TRAP_CODE_FIRQ_14</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_14</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:415</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1a874dcc43cf8fbbf2e0614e7db9e38334"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1a874dcc43cf8fbbf2e0614e7db9e38334">TRAP_CODE_FIRQ_11</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_11</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:412</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1aa102472d6a264bb92e0581ccaa413e02"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aa102472d6a264bb92e0581ccaa413e02">TRAP_CODE_UENV_CALL</a></div><div class="ttdeci">@ TRAP_CODE_UENV_CALL</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:396</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1aa4eeafe2f6f59aff01e29461c664a110"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aa4eeafe2f6f59aff01e29461c664a110">TRAP_CODE_FIRQ_15</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_15</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:416</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1aaa8e7bb251852ef75a78be71eef0b547"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aaa8e7bb251852ef75a78be71eef0b547">TRAP_CODE_FIRQ_4</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_4</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:405</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1abfd21d1380dcacb9282e525da104d916"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1abfd21d1380dcacb9282e525da104d916">TRAP_CODE_FIRQ_8</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_8</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:409</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1ad753d3e2563b4fd663430af9f3888dc7"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ad753d3e2563b4fd663430af9f3888dc7">TRAP_CODE_FIRQ_2</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_2</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:403</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1ae0b1049ae7f8cbfb6ff216e69ed5dae7"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ae0b1049ae7f8cbfb6ff216e69ed5dae7">TRAP_CODE_FIRQ_1</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_1</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:402</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1ae0cebf99f36ef6be60e4a9d2c9f894b0"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1ae0cebf99f36ef6be60e4a9d2c9f894b0">TRAP_CODE_MSI</a></div><div class="ttdeci">@ TRAP_CODE_MSI</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:398</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1aeab719bcce9e9551bd6da65a7ae08a26"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1aeab719bcce9e9551bd6da65a7ae08a26">TRAP_CODE_FIRQ_7</a></div><div class="ttdeci">@ TRAP_CODE_FIRQ_7</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:408</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_acb0fcbc551fec4c45676ff1317be24e1af1ad8f557f3b685b59a913611e1da173"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#acb0fcbc551fec4c45676ff1317be24e1af1ad8f557f3b685b59a913611e1da173">TRAP_CODE_I_ILLEGAL</a></div><div class="ttdeci">@ TRAP_CODE_I_ILLEGAL</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:390</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387">NEORV32_CSR_XISA_enum</a></div><div class="ttdeci">NEORV32_CSR_XISA_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:305</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a216ec44d5be3b158acb7e033e352bad1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a216ec44d5be3b158acb7e033e352bad1">CSR_MXISA_ZKNE</a></div><div class="ttdeci">@ CSR_MXISA_ZKNE</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:321</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a2649bee3397c74ada7b72677308f38c0"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a2649bee3397c74ada7b72677308f38c0">CSR_MXISA_ZKS</a></div><div class="ttdeci">@ CSR_MXISA_ZKS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:328</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a31788af612f04bc6b2a2bd15c1fb63c1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a31788af612f04bc6b2a2bd15c1fb63c1">CSR_MXISA_ZKT</a></div><div class="ttdeci">@ CSR_MXISA_ZKT</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:311</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a34519a66e749d63dc5bc7c145c297b64"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a34519a66e749d63dc5bc7c145c297b64">CSR_MXISA_ZBKX</a></div><div class="ttdeci">@ CSR_MXISA_ZBKX</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:319</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a42a3b78195741af4b6aeeb98cbea46fe"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a42a3b78195741af4b6aeeb98cbea46fe">CSR_MXISA_ZICNTR</a></div><div class="ttdeci">@ CSR_MXISA_ZICNTR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:314</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a43213190abb77304a78c15196c90a044"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a43213190abb77304a78c15196c90a044">CSR_MXISA_ZKSED</a></div><div class="ttdeci">@ CSR_MXISA_ZKSED</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:327</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a469e8e449f0e442df531c8cf2c4f35c5"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a469e8e449f0e442df531c8cf2c4f35c5">CSR_MXISA_ZBS</a></div><div class="ttdeci">@ CSR_MXISA_ZBS</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:331</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a48e57689f8a5b51d9ee9d648da7efc64"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a48e57689f8a5b51d9ee9d648da7efc64">CSR_MXISA_FASTMUL</a></div><div class="ttdeci">@ CSR_MXISA_FASTMUL</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:335</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a48f1de7f79a0633644ae02c463d49375"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a48f1de7f79a0633644ae02c463d49375">CSR_MXISA_ZKND</a></div><div class="ttdeci">@ CSR_MXISA_ZKND</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:320</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a56ec3195d0d27f362f58fadb2e037ed1"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a56ec3195d0d27f362f58fadb2e037ed1">CSR_MXISA_ZFINX</a></div><div class="ttdeci">@ CSR_MXISA_ZFINX</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:312</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a59eae4272528f589f299ef9cce45af5b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a59eae4272528f589f299ef9cce45af5b">CSR_MXISA_SDTRIG</a></div><div class="ttdeci">@ CSR_MXISA_SDTRIG</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:318</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a5e4bf05830b66410bbf2ef2c68e5fd18"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a5e4bf05830b66410bbf2ef2c68e5fd18">CSR_MXISA_ZKSH</a></div><div class="ttdeci">@ CSR_MXISA_ZKSH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:326</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a5fe8e591901e0fd7ba6706c70e9c76ec"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a5fe8e591901e0fd7ba6706c70e9c76ec">CSR_MXISA_ZKNH</a></div><div class="ttdeci">@ CSR_MXISA_ZKNH</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:322</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a6843c660d75f33e4252c7fccd4565a2d"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6843c660d75f33e4252c7fccd4565a2d">CSR_MXISA_RFHWRST</a></div><div class="ttdeci">@ CSR_MXISA_RFHWRST</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:334</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a6938948290d86b0ad25923f35d6c86d3"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6938948290d86b0ad25923f35d6c86d3">CSR_MXISA_SMPMP</a></div><div class="ttdeci">@ CSR_MXISA_SMPMP</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:315</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a6979d4389ed9f8605d338fc616d29f0e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a6979d4389ed9f8605d338fc616d29f0e">CSR_MXISA_ZIFENCEI</a></div><div class="ttdeci">@ CSR_MXISA_ZIFENCEI</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:308</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a79b2b4b20e08ad31b50724a7a27fb20f"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a79b2b4b20e08ad31b50724a7a27fb20f">CSR_MXISA_ZMMUL</a></div><div class="ttdeci">@ CSR_MXISA_ZMMUL</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:309</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a815cbe0149cba2a69025f6bec9946a85"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a815cbe0149cba2a69025f6bec9946a85">CSR_MXISA_ZBB</a></div><div class="ttdeci">@ CSR_MXISA_ZBB</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:330</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387a9b121ec0ad6271b6e07658f861015f6a"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387a9b121ec0ad6271b6e07658f861015f6a">CSR_MXISA_IS_SIM</a></div><div class="ttdeci">@ CSR_MXISA_IS_SIM</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:338</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387ab1f289cfaa9f54f7831a2abcdf9fca2e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ab1f289cfaa9f54f7831a2abcdf9fca2e">CSR_MXISA_ZICOND</a></div><div class="ttdeci">@ CSR_MXISA_ZICOND</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:313</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387ab6aec595e6aa5ce7c98c7806d23d7af5"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ab6aec595e6aa5ce7c98c7806d23d7af5">CSR_MXISA_SDEXT</a></div><div class="ttdeci">@ CSR_MXISA_SDEXT</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:317</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387ac13e6883af3a9da18057462239b9fb34"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ac13e6883af3a9da18057462239b9fb34">CSR_MXISA_ZIHPM</a></div><div class="ttdeci">@ CSR_MXISA_ZIHPM</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:316</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387ac9e87153c096d656b40cb7abdf3afd55"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ac9e87153c096d656b40cb7abdf3afd55">CSR_MXISA_ZBKC</a></div><div class="ttdeci">@ CSR_MXISA_ZBKC</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:324</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387accf1dd12be89e45df1423a5600789f2c"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387accf1dd12be89e45df1423a5600789f2c">CSR_MXISA_ZICSR</a></div><div class="ttdeci">@ CSR_MXISA_ZICSR</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:307</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387ad5ac9e2188757e6c42c159f0c5887868"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ad5ac9e2188757e6c42c159f0c5887868">CSR_MXISA_FASTSHIFT</a></div><div class="ttdeci">@ CSR_MXISA_FASTSHIFT</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:336</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387ad7e7454a30c82c3d91acbc8c259e8c25"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387ad7e7454a30c82c3d91acbc8c259e8c25">CSR_MXISA_ZKN</a></div><div class="ttdeci">@ CSR_MXISA_ZKN</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:325</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387adb26c1e5bf6ae112625621dddd331735"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adb26c1e5bf6ae112625621dddd331735">CSR_MXISA_ZBKB</a></div><div class="ttdeci">@ CSR_MXISA_ZBKB</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:323</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387adf45adc0bcbec0c1ffa944099257a947"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adf45adc0bcbec0c1ffa944099257a947">CSR_MXISA_ZALRSC</a></div><div class="ttdeci">@ CSR_MXISA_ZALRSC</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:332</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387adfc9122d93a71bf6df178022a52d22c4"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387adfc9122d93a71bf6df178022a52d22c4">CSR_MXISA_ZBA</a></div><div class="ttdeci">@ CSR_MXISA_ZBA</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:329</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_af05490a8af176ab4ba945d327d448387af422ae3b5caba59e33a29b5d069597e0"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#af05490a8af176ab4ba945d327d448387af422ae3b5caba59e33a29b5d069597e0">CSR_MXISA_ZXCFU</a></div><div class="ttdeci">@ CSR_MXISA_ZXCFU</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:310</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afde0761e3150d82511136f56179c204b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204b">NEORV32_CSR_FFLAGS_enum</a></div><div class="ttdeci">NEORV32_CSR_FFLAGS_enum</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:160</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afde0761e3150d82511136f56179c204ba365f3f519bca34a349907c82c873d52b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba365f3f519bca34a349907c82c873d52b">CSR_FFLAGS_DZ</a></div><div class="ttdeci">@ CSR_FFLAGS_DZ</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:164</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afde0761e3150d82511136f56179c204ba3ac330a4b03178e756c980eaa48ad165"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba3ac330a4b03178e756c980eaa48ad165">CSR_FFLAGS_NV</a></div><div class="ttdeci">@ CSR_FFLAGS_NV</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:165</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afde0761e3150d82511136f56179c204ba612390e07a065fa13eeaeac84af48c6e"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba612390e07a065fa13eeaeac84af48c6e">CSR_FFLAGS_OF</a></div><div class="ttdeci">@ CSR_FFLAGS_OF</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:163</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afde0761e3150d82511136f56179c204ba91a314defd310786a9ed67f7ef2ef5a6"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204ba91a314defd310786a9ed67f7ef2ef5a6">CSR_FFLAGS_NX</a></div><div class="ttdeci">@ CSR_FFLAGS_NX</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:161</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afde0761e3150d82511136f56179c204babc6d405724563844569028f463885819"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afde0761e3150d82511136f56179c204babc6d405724563844569028f463885819">CSR_FFLAGS_UF</a></div><div class="ttdeci">@ CSR_FFLAGS_UF</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:162</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afed7f00bbb39468f038d9ca6fbac830c"><div class="ttname"><a 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id="aneorv32__cpu__csr_8h_html_afed7f00bbb39468f038d9ca6fbac830ca317a631e4598532f5bffe8fb93aff94b"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca317a631e4598532f5bffe8fb93aff94b">CSR_MISA_M</a></div><div class="ttdeci">@ CSR_MISA_M</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:294</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afed7f00bbb39468f038d9ca6fbac830ca6091fd2c7ae38ad33be68a0fdfa50cca"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca6091fd2c7ae38ad33be68a0fdfa50cca">CSR_MISA_I</a></div><div class="ttdeci">@ CSR_MISA_I</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:293</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afed7f00bbb39468f038d9ca6fbac830ca886699013158c74810598fa2fd6b07fa"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830ca886699013158c74810598fa2fd6b07fa">CSR_MISA_C</a></div><div class="ttdeci">@ CSR_MISA_C</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:291</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afed7f00bbb39468f038d9ca6fbac830cab5a55e97b8511f42fe68559a38f7f138"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cab5a55e97b8511f42fe68559a38f7f138">CSR_MISA_MXL_LO</a></div><div class="ttdeci">@ CSR_MISA_MXL_LO</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:297</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afed7f00bbb39468f038d9ca6fbac830cacd9d71e674d3a6d04984b6df706d9deb"><div class="ttname"><a href="neorv32__cpu__csr_8h.html#afed7f00bbb39468f038d9ca6fbac830cacd9d71e674d3a6d04984b6df706d9deb">CSR_MISA_U</a></div><div class="ttdeci">@ CSR_MISA_U</div><div class="ttdef"><b>Definition</b> neorv32_cpu_csr.h:295</div></div> +<div class="ttc" id="aneorv32__cpu__csr_8h_html_afed7f00bbb39468f038d9ca6fbac830cadd469404a928e012a298773ec46926ad"><div class="ttname"><a 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+<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_crc.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Cyclic redundancy check unit (CRC) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:aa46c647317752f8bb6d5836d4876a704" id="r_aa46c647317752f8bb6d5836d4876a704"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa46c647317752f8bb6d5836d4876a704">neorv32_crc_available</a> (void)</td></tr> +<tr class="separator:aa46c647317752f8bb6d5836d4876a704"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4ff5f7b91e9f668535ed33b6382ae623" id="r_a4ff5f7b91e9f668535ed33b6382ae623"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4ff5f7b91e9f668535ed33b6382ae623">neorv32_crc_setup</a> (uint32_t mode, uint32_t poly, uint32_t start)</td></tr> +<tr class="separator:a4ff5f7b91e9f668535ed33b6382ae623"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9243006e6cc94c03450646d26a7289b2" id="r_a9243006e6cc94c03450646d26a7289b2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9243006e6cc94c03450646d26a7289b2">neorv32_crc_block</a> (uint8_t *byte, int length)</td></tr> +<tr class="separator:a9243006e6cc94c03450646d26a7289b2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad9d50c76a485160667d486bce32cbeb8" id="r_ad9d50c76a485160667d486bce32cbeb8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad9d50c76a485160667d486bce32cbeb8">neorv32_crc_single</a> (uint8_t byte)</td></tr> +<tr class="separator:ad9d50c76a485160667d486bce32cbeb8"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a444b88f1536f65acc301fb19eddcf227" id="r_a444b88f1536f65acc301fb19eddcf227"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a444b88f1536f65acc301fb19eddcf227">neorv32_crc_get</a> (void)</td></tr> +<tr class="separator:a444b88f1536f65acc301fb19eddcf227"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Cyclic redundancy check unit (CRC) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the CRC unit was synthesized (IO_CRC_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="aa46c647317752f8bb6d5836d4876a704" name="aa46c647317752f8bb6d5836d4876a704"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa46c647317752f8bb6d5836d4876a704">&#9670;&#160;</a></span>neorv32_crc_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_crc_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if CRC unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if CRC was not synthesized, 1 if CRC is available. </dd></dl> + +</div> +</div> +<a id="a9243006e6cc94c03450646d26a7289b2" name="a9243006e6cc94c03450646d26a7289b2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9243006e6cc94c03450646d26a7289b2">&#9670;&#160;</a></span>neorv32_crc_block()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_crc_block </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>byte</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>length</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Compute pre-configured CRC for entire data block.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Pointer to byte (uint8_t) source data array. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">length</td><td>Length of source data array. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>32-bit CRC result. </dd></dl> + +</div> +</div> +<a id="a444b88f1536f65acc301fb19eddcf227" name="a444b88f1536f65acc301fb19eddcf227"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a444b88f1536f65acc301fb19eddcf227">&#9670;&#160;</a></span>neorv32_crc_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_crc_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get current CRC shift register data.</p> +<dl class="section return"><dt>Returns</dt><dd>32-bit CRC result. </dd></dl> + +</div> +</div> +<a id="a4ff5f7b91e9f668535ed33b6382ae623" name="a4ff5f7b91e9f668535ed33b6382ae623"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4ff5f7b91e9f668535ed33b6382ae623">&#9670;&#160;</a></span>neorv32_crc_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_crc_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>mode</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>poly</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>start</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Setup CRC unit.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>Operation mode (<a class="el" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447">NEORV32_CRC_MODE_enum</a>). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">poly</td><td>CRC polynomial. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">start</td><td>CRC shift register start value. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ad9d50c76a485160667d486bce32cbeb8" name="ad9d50c76a485160667d486bce32cbeb8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad9d50c76a485160667d486bce32cbeb8">&#9670;&#160;</a></span>neorv32_crc_single()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_crc_single </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>byte</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Compute pre-configured CRC for single data byte.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Data byte (uint8_t). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__crc_8h.html b/sw/neorv32__crc_8h.html new file mode 100644 index 000000000..656e6de96 --- /dev/null +++ b/sw/neorv32__crc_8h.html @@ -0,0 +1,312 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta 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class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__crc_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__crc__t.html">neorv32_crc_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:aa46c647317752f8bb6d5836d4876a704" id="r_aa46c647317752f8bb6d5836d4876a704"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa46c647317752f8bb6d5836d4876a704">neorv32_crc_available</a> (void)</td></tr> +<tr class="separator:aa46c647317752f8bb6d5836d4876a704"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4ff5f7b91e9f668535ed33b6382ae623" id="r_a4ff5f7b91e9f668535ed33b6382ae623"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4ff5f7b91e9f668535ed33b6382ae623">neorv32_crc_setup</a> (uint32_t mode, uint32_t poly, uint32_t start)</td></tr> +<tr class="separator:a4ff5f7b91e9f668535ed33b6382ae623"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9243006e6cc94c03450646d26a7289b2" id="r_a9243006e6cc94c03450646d26a7289b2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9243006e6cc94c03450646d26a7289b2">neorv32_crc_block</a> (uint8_t *byte, int length)</td></tr> +<tr class="separator:a9243006e6cc94c03450646d26a7289b2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad9d50c76a485160667d486bce32cbeb8" id="r_ad9d50c76a485160667d486bce32cbeb8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad9d50c76a485160667d486bce32cbeb8">neorv32_crc_single</a> (uint8_t byte)</td></tr> +<tr class="separator:ad9d50c76a485160667d486bce32cbeb8"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a444b88f1536f65acc301fb19eddcf227" id="r_a444b88f1536f65acc301fb19eddcf227"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a444b88f1536f65acc301fb19eddcf227">neorv32_crc_get</a> (void)</td></tr> +<tr class="separator:a444b88f1536f65acc301fb19eddcf227"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Cyclic Redundancy Check Unit (CRC)</h2></td></tr> +<tr class="memitem:a110962d2b370f9d7997e459d9fd34271" id="r_a110962d2b370f9d7997e459d9fd34271"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a110962d2b370f9d7997e459d9fd34271">NEORV32_CRC</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__crc__t.html">neorv32_crc_t</a>*) (<a class="el" href="neorv32_8h.html#a0e2377055bdc0f416b5ae4385610600d">NEORV32_CRC_BASE</a>))</td></tr> +<tr class="separator:a110962d2b370f9d7997e459d9fd34271"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1ae84a58f475bafc2fc3f2c690fd6447" id="r_a1ae84a58f475bafc2fc3f2c690fd6447"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1ae84a58f475bafc2fc3f2c690fd6447">NEORV32_CRC_MODE_enum</a> { <a class="el" href="#a1ae84a58f475bafc2fc3f2c690fd6447a9409185edbae1bd0afdeda4e58aa6d1a">CRC_MODE8</a> = 0b00 +, <a class="el" href="#a1ae84a58f475bafc2fc3f2c690fd6447aa5cfd5d285b4cb8997c7e754491d050f">CRC_MODE16</a> = 0b01 +, <a class="el" href="#a1ae84a58f475bafc2fc3f2c690fd6447a7cf26bd4a7e8d6e45016633f650f00aa">CRC_MODE32</a> = 0b10 + }</td></tr> +<tr class="separator:a1ae84a58f475bafc2fc3f2c690fd6447"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Cyclic redundancy check unit (CRC) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the CRC unit was synthesized (IO_CRC_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a110962d2b370f9d7997e459d9fd34271" name="a110962d2b370f9d7997e459d9fd34271"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a110962d2b370f9d7997e459d9fd34271">&#9670;&#160;</a></span>NEORV32_CRC</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_CRC&#160;&#160;&#160;((<a class="el" href="structneorv32__crc__t.html">neorv32_crc_t</a>*) (<a class="el" href="neorv32_8h.html#a0e2377055bdc0f416b5ae4385610600d">NEORV32_CRC_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CRC module hardware access (<a class="el" href="structneorv32__crc__t.html">neorv32_crc_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a1ae84a58f475bafc2fc3f2c690fd6447" name="a1ae84a58f475bafc2fc3f2c690fd6447"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1ae84a58f475bafc2fc3f2c690fd6447">&#9670;&#160;</a></span>NEORV32_CRC_MODE_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a1ae84a58f475bafc2fc3f2c690fd6447">NEORV32_CRC_MODE_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>CRC mode select </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a1ae84a58f475bafc2fc3f2c690fd6447a9409185edbae1bd0afdeda4e58aa6d1a" name="a1ae84a58f475bafc2fc3f2c690fd6447a9409185edbae1bd0afdeda4e58aa6d1a"></a>CRC_MODE8&#160;</td><td class="fielddoc"><p>(0) crc8 </p> +</td></tr> +<tr><td class="fieldname"><a id="a1ae84a58f475bafc2fc3f2c690fd6447aa5cfd5d285b4cb8997c7e754491d050f" name="a1ae84a58f475bafc2fc3f2c690fd6447aa5cfd5d285b4cb8997c7e754491d050f"></a>CRC_MODE16&#160;</td><td class="fielddoc"><p>(1) crc16 </p> +</td></tr> +<tr><td class="fieldname"><a id="a1ae84a58f475bafc2fc3f2c690fd6447a7cf26bd4a7e8d6e45016633f650f00aa" name="a1ae84a58f475bafc2fc3f2c690fd6447a7cf26bd4a7e8d6e45016633f650f00aa"></a>CRC_MODE32&#160;</td><td class="fielddoc"><p>(3) crc32 </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="aa46c647317752f8bb6d5836d4876a704" name="aa46c647317752f8bb6d5836d4876a704"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa46c647317752f8bb6d5836d4876a704">&#9670;&#160;</a></span>neorv32_crc_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_crc_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if CRC unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if CRC was not synthesized, 1 if CRC is available. </dd></dl> + +</div> +</div> +<a id="a9243006e6cc94c03450646d26a7289b2" name="a9243006e6cc94c03450646d26a7289b2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9243006e6cc94c03450646d26a7289b2">&#9670;&#160;</a></span>neorv32_crc_block()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_crc_block </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>byte</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>length</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Compute pre-configured CRC for entire data block.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Pointer to byte (uint8_t) source data array. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">length</td><td>Length of source data array. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>32-bit CRC result. </dd></dl> + +</div> +</div> +<a id="a444b88f1536f65acc301fb19eddcf227" name="a444b88f1536f65acc301fb19eddcf227"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a444b88f1536f65acc301fb19eddcf227">&#9670;&#160;</a></span>neorv32_crc_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_crc_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get current CRC shift register data.</p> +<dl class="section return"><dt>Returns</dt><dd>32-bit CRC result. </dd></dl> + +</div> +</div> +<a id="a4ff5f7b91e9f668535ed33b6382ae623" name="a4ff5f7b91e9f668535ed33b6382ae623"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4ff5f7b91e9f668535ed33b6382ae623">&#9670;&#160;</a></span>neorv32_crc_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_crc_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>mode</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>poly</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>start</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Setup CRC unit.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>Operation mode (<a class="el" href="#a1ae84a58f475bafc2fc3f2c690fd6447">NEORV32_CRC_MODE_enum</a>). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">poly</td><td>CRC polynomial. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">start</td><td>CRC shift register start value. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ad9d50c76a485160667d486bce32cbeb8" name="ad9d50c76a485160667d486bce32cbeb8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad9d50c76a485160667d486bce32cbeb8">&#9670;&#160;</a></span>neorv32_crc_single()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_crc_single </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>byte</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Compute pre-configured CRC for single data byte.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Data byte (uint8_t). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__crc_8h_source.html b/sw/neorv32__crc_8h_source.html new file mode 100644 index 000000000..e67aaefc6 --- /dev/null +++ b/sw/neorv32__crc_8h_source.html @@ -0,0 +1,157 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta 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================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_crc_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_crc_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__crc__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__crc__t.html#ad720502701f16e6e952bbcaee980017c"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__crc__t.html#ad720502701f16e6e952bbcaee980017c">MODE</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__crc__t.html#a9bbcab843ddba4f9772d07478947a661"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__crc__t.html#a9bbcab843ddba4f9772d07478947a661">POLY</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"><a class="line" href="structneorv32__crc__t.html#a47f286612848f597859aaef0d2d5da4d"> 32</a></span> uint32_t <a class="code hl_variable" href="structneorv32__crc__t.html#a47f286612848f597859aaef0d2d5da4d">DATA</a>; </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"><a class="line" href="structneorv32__crc__t.html#abf2b419f2aefdb6f2a6b81a02cb8612d"> 33</a></span> uint32_t <a class="code hl_variable" href="structneorv32__crc__t.html#abf2b419f2aefdb6f2a6b81a02cb8612d">SREG</a>; </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span>} <a class="code hl_struct" href="structneorv32__crc__t.html">neorv32_crc_t</a>;</div> +</div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__crc_8h.html#a110962d2b370f9d7997e459d9fd34271"> 37</a></span><span class="preprocessor">#define NEORV32_CRC ((neorv32_crc_t*) (NEORV32_CRC_BASE))</span></div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> </div> +<div class="foldopen" id="foldopen00040" data-start="{" data-end="};"> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447"> 40</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447">NEORV32_CRC_MODE_enum</a> {</div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447a9409185edbae1bd0afdeda4e58aa6d1a"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447a9409185edbae1bd0afdeda4e58aa6d1a">CRC_MODE8</a> = 0b00, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447aa5cfd5d285b4cb8997c7e754491d050f"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447aa5cfd5d285b4cb8997c7e754491d050f">CRC_MODE16</a> = 0b01, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447a7cf26bd4a7e8d6e45016633f650f00aa"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447a7cf26bd4a7e8d6e45016633f650f00aa">CRC_MODE32</a> = 0b10, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span>};</div> +</div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__crc_8h.html#aa46c647317752f8bb6d5836d4876a704">neorv32_crc_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__crc_8h.html#a4ff5f7b91e9f668535ed33b6382ae623">neorv32_crc_setup</a>(uint32_t mode, uint32_t poly, uint32_t start);</div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span>uint32_t <a class="code hl_function" href="neorv32__crc_8h.html#a9243006e6cc94c03450646d26a7289b2">neorv32_crc_block</a>(uint8_t *<span class="keywordtype">byte</span>, <span class="keywordtype">int</span> length);</div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__crc_8h.html#ad9d50c76a485160667d486bce32cbeb8">neorv32_crc_single</a>(uint8_t <span class="keywordtype">byte</span>);</div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span>uint32_t <a class="code hl_function" href="neorv32__crc_8h.html#a444b88f1536f65acc301fb19eddcf227">neorv32_crc_get</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_crc_h</span></div> +<div class="ttc" id="aneorv32__crc_8h_html_a1ae84a58f475bafc2fc3f2c690fd6447"><div class="ttname"><a href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447">NEORV32_CRC_MODE_enum</a></div><div class="ttdeci">NEORV32_CRC_MODE_enum</div><div class="ttdef"><b>Definition</b> neorv32_crc.h:40</div></div> +<div class="ttc" id="aneorv32__crc_8h_html_a1ae84a58f475bafc2fc3f2c690fd6447a7cf26bd4a7e8d6e45016633f650f00aa"><div class="ttname"><a href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447a7cf26bd4a7e8d6e45016633f650f00aa">CRC_MODE32</a></div><div class="ttdeci">@ CRC_MODE32</div><div class="ttdef"><b>Definition</b> neorv32_crc.h:43</div></div> +<div class="ttc" id="aneorv32__crc_8h_html_a1ae84a58f475bafc2fc3f2c690fd6447a9409185edbae1bd0afdeda4e58aa6d1a"><div class="ttname"><a href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447a9409185edbae1bd0afdeda4e58aa6d1a">CRC_MODE8</a></div><div class="ttdeci">@ CRC_MODE8</div><div class="ttdef"><b>Definition</b> neorv32_crc.h:41</div></div> +<div class="ttc" id="aneorv32__crc_8h_html_a1ae84a58f475bafc2fc3f2c690fd6447aa5cfd5d285b4cb8997c7e754491d050f"><div class="ttname"><a href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447aa5cfd5d285b4cb8997c7e754491d050f">CRC_MODE16</a></div><div class="ttdeci">@ CRC_MODE16</div><div class="ttdef"><b>Definition</b> neorv32_crc.h:42</div></div> +<div class="ttc" id="aneorv32__crc_8h_html_a444b88f1536f65acc301fb19eddcf227"><div class="ttname"><a href="neorv32__crc_8h.html#a444b88f1536f65acc301fb19eddcf227">neorv32_crc_get</a></div><div class="ttdeci">uint32_t neorv32_crc_get(void)</div><div class="ttdef"><b>Definition</b> neorv32_crc.c:86</div></div> +<div class="ttc" id="aneorv32__crc_8h_html_a4ff5f7b91e9f668535ed33b6382ae623"><div class="ttname"><a href="neorv32__crc_8h.html#a4ff5f7b91e9f668535ed33b6382ae623">neorv32_crc_setup</a></div><div class="ttdeci">void neorv32_crc_setup(uint32_t mode, uint32_t poly, uint32_t start)</div><div class="ttdef"><b>Definition</b> neorv32_crc.c:44</div></div> +<div class="ttc" id="aneorv32__crc_8h_html_a9243006e6cc94c03450646d26a7289b2"><div class="ttname"><a href="neorv32__crc_8h.html#a9243006e6cc94c03450646d26a7289b2">neorv32_crc_block</a></div><div class="ttdeci">uint32_t neorv32_crc_block(uint8_t *byte, int length)</div><div class="ttdef"><b>Definition</b> neorv32_crc.c:59</div></div> +<div class="ttc" id="aneorv32__crc_8h_html_aa46c647317752f8bb6d5836d4876a704"><div class="ttname"><a href="neorv32__crc_8h.html#aa46c647317752f8bb6d5836d4876a704">neorv32_crc_available</a></div><div class="ttdeci">int neorv32_crc_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_crc.c:26</div></div> +<div class="ttc" id="aneorv32__crc_8h_html_ad9d50c76a485160667d486bce32cbeb8"><div class="ttname"><a href="neorv32__crc_8h.html#ad9d50c76a485160667d486bce32cbeb8">neorv32_crc_single</a></div><div class="ttdeci">void neorv32_crc_single(uint8_t byte)</div><div class="ttdef"><b>Definition</b> neorv32_crc.c:75</div></div> +<div class="ttc" id="astructneorv32__crc__t_html"><div class="ttname"><a href="structneorv32__crc__t.html">neorv32_crc_t</a></div><div class="ttdef"><b>Definition</b> neorv32_crc.h:29</div></div> +<div class="ttc" id="astructneorv32__crc__t_html_a47f286612848f597859aaef0d2d5da4d"><div class="ttname"><a href="structneorv32__crc__t.html#a47f286612848f597859aaef0d2d5da4d">neorv32_crc_t::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition</b> neorv32_crc.h:32</div></div> +<div class="ttc" id="astructneorv32__crc__t_html_a9bbcab843ddba4f9772d07478947a661"><div class="ttname"><a href="structneorv32__crc__t.html#a9bbcab843ddba4f9772d07478947a661">neorv32_crc_t::POLY</a></div><div class="ttdeci">uint32_t POLY</div><div class="ttdef"><b>Definition</b> neorv32_crc.h:31</div></div> +<div class="ttc" id="astructneorv32__crc__t_html_abf2b419f2aefdb6f2a6b81a02cb8612d"><div class="ttname"><a href="structneorv32__crc__t.html#abf2b419f2aefdb6f2a6b81a02cb8612d">neorv32_crc_t::SREG</a></div><div class="ttdeci">uint32_t SREG</div><div class="ttdef"><b>Definition</b> neorv32_crc.h:33</div></div> +<div class="ttc" id="astructneorv32__crc__t_html_ad720502701f16e6e952bbcaee980017c"><div class="ttname"><a href="structneorv32__crc__t.html#ad720502701f16e6e952bbcaee980017c">neorv32_crc_t::MODE</a></div><div class="ttdeci">uint32_t MODE</div><div class="ttdef"><b>Definition</b> neorv32_crc.h:30</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a 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id="r_aa116f9714174abbe8a3583e441fee24b"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa116f9714174abbe8a3583e441fee24b">neorv32_dma_status</a> (void)</td></tr> +<tr class="separator:aa116f9714174abbe8a3583e441fee24b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afc8cc32f7d80d0f5ab33b2f1ecf77956" id="r_afc8cc32f7d80d0f5ab33b2f1ecf77956"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afc8cc32f7d80d0f5ab33b2f1ecf77956">neorv32_dma_done</a> (void)</td></tr> +<tr class="separator:afc8cc32f7d80d0f5ab33b2f1ecf77956"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Direct Memory Access Controller (DMA)</h2></td></tr> +<tr class="memitem:a0dcb61a0e0d2b45beb7818015adc8639" id="r_a0dcb61a0e0d2b45beb7818015adc8639"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0dcb61a0e0d2b45beb7818015adc8639">NEORV32_DMA</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__dma__t.html">neorv32_dma_t</a>*) (<a class="el" href="neorv32_8h.html#aa8d3a83ffad1e71f0832a5da78d62008">NEORV32_DMA_BASE</a>))</td></tr> +<tr class="separator:a0dcb61a0e0d2b45beb7818015adc8639"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6716eddb145b80ad38799da3b87cb2a4" id="r_a6716eddb145b80ad38799da3b87cb2a4"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4">NEORV32_DMA_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4a5f39deea0212f45423243c8100c40838">DMA_CTRL_EN</a> = 0 +, <a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4a5aeeb05d6365d94d92808df2490daa3b">DMA_CTRL_AUTO</a> = 1 +, <a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4ace9fdcdfa8784abad30e033c273e7d00">DMA_CTRL_FENCE</a> = 2 +, <a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4a539609fc4d80867b3eb98c78206f5f96">DMA_CTRL_ERROR_RD</a> = 8 +, <br /> +&#160;&#160;<a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4af7e038b0b0e3ac64f5a2c598eb9c5101">DMA_CTRL_ERROR_WR</a> = 9 +, <a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4a8e5ff34ac48eea4b352378bb2af47bcb">DMA_CTRL_BUSY</a> = 10 +, <a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4a0d51df1bb87dc54d331891c5db787bcc">DMA_CTRL_DONE</a> = 11 +, <a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4aeaf5ee8f6a84668aa15cd3e21f076afe">DMA_CTRL_FIRQ_TYPE</a> = 15 +, <br /> +&#160;&#160;<a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4aaf040e663494b39b890d7171d0a584b9">DMA_CTRL_FIRQ_SEL_LSB</a> = 16 +, <a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4a3eba1f7868f0c985effb69785ced011a">DMA_CTRL_FIRQ_SEL_MSB</a> = 19 +<br /> + }</td></tr> +<tr class="separator:a6716eddb145b80ad38799da3b87cb2a4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a33187c5a074d62b46d2262e352edb8d9" id="r_a33187c5a074d62b46d2262e352edb8d9"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a33187c5a074d62b46d2262e352edb8d9">NEORV32_DMA_TTYPE_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a33187c5a074d62b46d2262e352edb8d9a8dba4160c033c763f5102928c471e450">DMA_TTYPE_NUM_LSB</a> = 0 +, <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9a61553eee00ed2382565bf826074c44bd">DMA_TTYPE_NUM_MSB</a> = 23 +, <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2">DMA_TTYPE_QSEL_LSB</a> = 27 +, <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9a4217c9a8ac4ccc52bb45944f30a598c5">DMA_TTYPE_QSEL_MSB</a> = 28 +, <br /> +&#160;&#160;<a class="el" href="#a33187c5a074d62b46d2262e352edb8d9a4b99a30b851851f3388dd4e77effacec">DMA_TTYPE_SRC_INC</a> = 29 +, <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da">DMA_TTYPE_DST_INC</a> = 30 +, <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9a37ea8ef1e6b342db330d3885545fc802">DMA_TTYPE_ENDIAN</a> = 31 +<br /> + }</td></tr> +<tr class="separator:a33187c5a074d62b46d2262e352edb8d9"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Direct Memory Access Controller (DMA) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the DMA controller was synthesized (IO_DMA_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a5e01d4454c97eb8e4ecd1455090bbfa9" name="a5e01d4454c97eb8e4ecd1455090bbfa9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5e01d4454c97eb8e4ecd1455090bbfa9">&#9670;&#160;</a></span>DMA_CMD_B2B</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_CMD_B2B&#160;&#160;&#160;(0b00 &lt;&lt; <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2">DMA_TTYPE_QSEL_LSB</a>)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type commands </p> + +</div> +</div> +<a id="adfecb3debff251070e4f6eb809412129" name="adfecb3debff251070e4f6eb809412129"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adfecb3debff251070e4f6eb809412129">&#9670;&#160;</a></span>DMA_CMD_B2SW</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_CMD_B2SW&#160;&#160;&#160;(0b10 &lt;&lt; <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2">DMA_TTYPE_QSEL_LSB</a>)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type commands </p> + +</div> +</div> +<a id="aeb63f99217f14d1ddde35c1f6c104e72" name="aeb63f99217f14d1ddde35c1f6c104e72"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aeb63f99217f14d1ddde35c1f6c104e72">&#9670;&#160;</a></span>DMA_CMD_B2UW</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_CMD_B2UW&#160;&#160;&#160;(0b01 &lt;&lt; <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2">DMA_TTYPE_QSEL_LSB</a>)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type commands </p> + +</div> +</div> +<a id="a6a0ce532aad39e6489e9d52bcb6f4cd2" name="a6a0ce532aad39e6489e9d52bcb6f4cd2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6a0ce532aad39e6489e9d52bcb6f4cd2">&#9670;&#160;</a></span>DMA_CMD_DST_CONST</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_CMD_DST_CONST&#160;&#160;&#160;(0b0 &lt;&lt; <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da">DMA_TTYPE_DST_INC</a>)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type commands </p> + +</div> +</div> +<a id="a61caa2602c6b148af55d990e3c0ae6be" name="a61caa2602c6b148af55d990e3c0ae6be"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a61caa2602c6b148af55d990e3c0ae6be">&#9670;&#160;</a></span>DMA_CMD_DST_INC</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_CMD_DST_INC&#160;&#160;&#160;(0b1 &lt;&lt; <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da">DMA_TTYPE_DST_INC</a>)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type commands </p> + +</div> +</div> +<a id="a18fb7faa0a35f562821ca854d7c648b4" name="a18fb7faa0a35f562821ca854d7c648b4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a18fb7faa0a35f562821ca854d7c648b4">&#9670;&#160;</a></span>DMA_CMD_ENDIAN</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_CMD_ENDIAN&#160;&#160;&#160;(0b1 &lt;&lt; <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9a37ea8ef1e6b342db330d3885545fc802">DMA_TTYPE_ENDIAN</a>)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type commands </p> + +</div> +</div> +<a id="ae380022d8b8fb70da91f0892f2bc32c8" name="ae380022d8b8fb70da91f0892f2bc32c8"></a> +<h2 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href="#a33187c5a074d62b46d2262e352edb8d9a4b99a30b851851f3388dd4e77effacec">DMA_TTYPE_SRC_INC</a>)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type commands </p> + +</div> +</div> +<a id="a13a16ba8d6daf9c82312bf4d392d15a8" name="a13a16ba8d6daf9c82312bf4d392d15a8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a13a16ba8d6daf9c82312bf4d392d15a8">&#9670;&#160;</a></span>DMA_CMD_W2W</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define DMA_CMD_W2W&#160;&#160;&#160;(0b11 &lt;&lt; <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2">DMA_TTYPE_QSEL_LSB</a>)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type commands </p> + +</div> +</div> +<a id="a0dcb61a0e0d2b45beb7818015adc8639" name="a0dcb61a0e0d2b45beb7818015adc8639"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0dcb61a0e0d2b45beb7818015adc8639">&#9670;&#160;</a></span>NEORV32_DMA</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_DMA&#160;&#160;&#160;((<a class="el" href="structneorv32__dma__t.html">neorv32_dma_t</a>*) (<a class="el" href="neorv32_8h.html#aa8d3a83ffad1e71f0832a5da78d62008">NEORV32_DMA_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA module hardware access (<a class="el" href="structneorv32__dma__t.html">neorv32_dma_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a6716eddb145b80ad38799da3b87cb2a4" name="a6716eddb145b80ad38799da3b87cb2a4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6716eddb145b80ad38799da3b87cb2a4">&#9670;&#160;</a></span>NEORV32_DMA_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a6716eddb145b80ad38799da3b87cb2a4">NEORV32_DMA_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA control and status register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4a5f39deea0212f45423243c8100c40838" name="a6716eddb145b80ad38799da3b87cb2a4a5f39deea0212f45423243c8100c40838"></a>DMA_CTRL_EN&#160;</td><td class="fielddoc"><p>DMA control register(0) (r/w): DMA enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4a5aeeb05d6365d94d92808df2490daa3b" name="a6716eddb145b80ad38799da3b87cb2a4a5aeeb05d6365d94d92808df2490daa3b"></a>DMA_CTRL_AUTO&#160;</td><td class="fielddoc"><p>DMA control register(1) (r/w): Automatic trigger mode enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4ace9fdcdfa8784abad30e033c273e7d00" name="a6716eddb145b80ad38799da3b87cb2a4ace9fdcdfa8784abad30e033c273e7d00"></a>DMA_CTRL_FENCE&#160;</td><td class="fielddoc"><p>DMA control register(2) (r/w): Issue FENCE downstream operation when DMA transfer is completed </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4a539609fc4d80867b3eb98c78206f5f96" name="a6716eddb145b80ad38799da3b87cb2a4a539609fc4d80867b3eb98c78206f5f96"></a>DMA_CTRL_ERROR_RD&#160;</td><td class="fielddoc"><p>DMA control register(8) (r/-): Error during read access; SRC_BASE shows the faulting address </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4af7e038b0b0e3ac64f5a2c598eb9c5101" name="a6716eddb145b80ad38799da3b87cb2a4af7e038b0b0e3ac64f5a2c598eb9c5101"></a>DMA_CTRL_ERROR_WR&#160;</td><td class="fielddoc"><p>DMA control register(9) (r/-): Error during write access; DST_BASE shows the faulting address </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4a8e5ff34ac48eea4b352378bb2af47bcb" name="a6716eddb145b80ad38799da3b87cb2a4a8e5ff34ac48eea4b352378bb2af47bcb"></a>DMA_CTRL_BUSY&#160;</td><td class="fielddoc"><p>DMA control register(10) (r/-): DMA busy / transfer in progress </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4a0d51df1bb87dc54d331891c5db787bcc" name="a6716eddb145b80ad38799da3b87cb2a4a0d51df1bb87dc54d331891c5db787bcc"></a>DMA_CTRL_DONE&#160;</td><td class="fielddoc"><p>DMA control register(11) (r/c): A transfer was executed when set </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4aeaf5ee8f6a84668aa15cd3e21f076afe" name="a6716eddb145b80ad38799da3b87cb2a4aeaf5ee8f6a84668aa15cd3e21f076afe"></a>DMA_CTRL_FIRQ_TYPE&#160;</td><td class="fielddoc"><p>DMA control register(15) (r/w): Trigger on FIRQ rising-edge (0) or high-level (1) </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4aaf040e663494b39b890d7171d0a584b9" name="a6716eddb145b80ad38799da3b87cb2a4aaf040e663494b39b890d7171d0a584b9"></a>DMA_CTRL_FIRQ_SEL_LSB&#160;</td><td class="fielddoc"><p>DMA control register(16) (r/w): FIRQ trigger select LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a6716eddb145b80ad38799da3b87cb2a4a3eba1f7868f0c985effb69785ced011a" name="a6716eddb145b80ad38799da3b87cb2a4a3eba1f7868f0c985effb69785ced011a"></a>DMA_CTRL_FIRQ_SEL_MSB&#160;</td><td class="fielddoc"><p>DMA control register(19) (r/w): FIRQ trigger select MSB </p> +</td></tr> +</table> + +</div> +</div> +<a id="a002cb188ea5156df0ba282e239a6e74b" name="a002cb188ea5156df0ba282e239a6e74b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a002cb188ea5156df0ba282e239a6e74b">&#9670;&#160;</a></span>NEORV32_DMA_STATUS_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a002cb188ea5156df0ba282e239a6e74b">NEORV32_DMA_STATUS_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA status </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a002cb188ea5156df0ba282e239a6e74ba038b6ef194c3db158cb59168f763a7b8" name="a002cb188ea5156df0ba282e239a6e74ba038b6ef194c3db158cb59168f763a7b8"></a>DMA_STATUS_ERR_WR&#160;</td><td class="fielddoc"><p>write access error during last transfer (-2) </p> +</td></tr> +<tr><td class="fieldname"><a id="a002cb188ea5156df0ba282e239a6e74baed7242b847e3cc8cf20d7da99f9b1492" name="a002cb188ea5156df0ba282e239a6e74baed7242b847e3cc8cf20d7da99f9b1492"></a>DMA_STATUS_ERR_RD&#160;</td><td class="fielddoc"><p>read access error during last transfer (-1) </p> +</td></tr> +<tr><td class="fieldname"><a id="a002cb188ea5156df0ba282e239a6e74bac9c380cd5729386e5f5673e20b86326f" name="a002cb188ea5156df0ba282e239a6e74bac9c380cd5729386e5f5673e20b86326f"></a>DMA_STATUS_IDLE&#160;</td><td class="fielddoc"><p>DMA idle (0) </p> +</td></tr> +<tr><td class="fieldname"><a id="a002cb188ea5156df0ba282e239a6e74bad0f66e962296f5451d73dc1cae1fdc0d" name="a002cb188ea5156df0ba282e239a6e74bad0f66e962296f5451d73dc1cae1fdc0d"></a>DMA_STATUS_BUSY&#160;</td><td class="fielddoc"><p>DMA busy (1) </p> +</td></tr> +</table> + +</div> +</div> +<a id="a33187c5a074d62b46d2262e352edb8d9" name="a33187c5a074d62b46d2262e352edb8d9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a33187c5a074d62b46d2262e352edb8d9">&#9670;&#160;</a></span>NEORV32_DMA_TTYPE_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a33187c5a074d62b46d2262e352edb8d9">NEORV32_DMA_TTYPE_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>DMA transfer type bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a33187c5a074d62b46d2262e352edb8d9a8dba4160c033c763f5102928c471e450" name="a33187c5a074d62b46d2262e352edb8d9a8dba4160c033c763f5102928c471e450"></a>DMA_TTYPE_NUM_LSB&#160;</td><td class="fielddoc"><p>DMA transfer type register(0) (r/w): Number of elements to transfer, LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a33187c5a074d62b46d2262e352edb8d9a61553eee00ed2382565bf826074c44bd" name="a33187c5a074d62b46d2262e352edb8d9a61553eee00ed2382565bf826074c44bd"></a>DMA_TTYPE_NUM_MSB&#160;</td><td class="fielddoc"><p>DMA transfer type register(23) (r/w): Number of elements to transfer, MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2" name="a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2"></a>DMA_TTYPE_QSEL_LSB&#160;</td><td class="fielddoc"><p>DMA transfer type register(27) (r/w): Data quantity select, LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a33187c5a074d62b46d2262e352edb8d9a4217c9a8ac4ccc52bb45944f30a598c5" name="a33187c5a074d62b46d2262e352edb8d9a4217c9a8ac4ccc52bb45944f30a598c5"></a>DMA_TTYPE_QSEL_MSB&#160;</td><td class="fielddoc"><p>DMA transfer type register(28) (r/w): Data quantity select, MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a33187c5a074d62b46d2262e352edb8d9a4b99a30b851851f3388dd4e77effacec" name="a33187c5a074d62b46d2262e352edb8d9a4b99a30b851851f3388dd4e77effacec"></a>DMA_TTYPE_SRC_INC&#160;</td><td class="fielddoc"><p>DMA transfer type register(29) (r/w): SRC constant (0) or incrementing (1) address </p> +</td></tr> +<tr><td class="fieldname"><a id="a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da" name="a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da"></a>DMA_TTYPE_DST_INC&#160;</td><td class="fielddoc"><p>DMA transfer type register(30) (r/w): SRC constant (0) or incrementing (1) address </p> +</td></tr> +<tr><td class="fieldname"><a id="a33187c5a074d62b46d2262e352edb8d9a37ea8ef1e6b342db330d3885545fc802" name="a33187c5a074d62b46d2262e352edb8d9a37ea8ef1e6b342db330d3885545fc802"></a>DMA_TTYPE_ENDIAN&#160;</td><td class="fielddoc"><p>DMA transfer type register(31) (r/w): Convert Endianness when set </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a13260c3252f0375d8982590d270d7dfd" name="a13260c3252f0375d8982590d270d7dfd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a13260c3252f0375d8982590d270d7dfd">&#9670;&#160;</a></span>neorv32_dma_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_dma_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if DMA controller was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if DMA was not synthesized, 1 if DMA is available. </dd></dl> + +</div> +</div> +<a id="a6df244028455cf7f8d4cf1520c4670a7" name="a6df244028455cf7f8d4cf1520c4670a7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6df244028455cf7f8d4cf1520c4670a7">&#9670;&#160;</a></span>neorv32_dma_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_dma_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable DMA. This will reset the DMA and will also terminate the current transfer. </p> + +</div> +</div> +<a id="afc8cc32f7d80d0f5ab33b2f1ecf77956" name="afc8cc32f7d80d0f5ab33b2f1ecf77956"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afc8cc32f7d80d0f5ab33b2f1ecf77956">&#9670;&#160;</a></span>neorv32_dma_done()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_dma_done </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if a transfer has actually been executed.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if no transfer was executed, 1 if a transfer has actually been executed. Use neorv32_dma_status(void) to check if there was an error during that transfer. </dd></dl> + +</div> +</div> +<a id="ac3b72447e8a132faf26577ac714b8284" name="ac3b72447e8a132faf26577ac714b8284"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac3b72447e8a132faf26577ac714b8284">&#9670;&#160;</a></span>neorv32_dma_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_dma_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable DMA. </p> + +</div> +</div> +<a id="a8f37adfa07050b0a1cb8430c9ce1fcc2" name="a8f37adfa07050b0a1cb8430c9ce1fcc2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8f37adfa07050b0a1cb8430c9ce1fcc2">&#9670;&#160;</a></span>neorv32_dma_fence_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_dma_fence_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable memory barrier (fence). </p> + +</div> +</div> +<a id="a2c7257567ccdb7a986f5ef7c74d3917c" name="a2c7257567ccdb7a986f5ef7c74d3917c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2c7257567ccdb7a986f5ef7c74d3917c">&#9670;&#160;</a></span>neorv32_dma_fence_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_dma_fence_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable memory barrier (fence): issue a FENCE operation when DMA transfer completes without errors. </p> + +</div> +</div> +<a id="aa116f9714174abbe8a3583e441fee24b" name="aa116f9714174abbe8a3583e441fee24b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa116f9714174abbe8a3583e441fee24b">&#9670;&#160;</a></span>neorv32_dma_status()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_dma_status </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get DMA status.</p> +<dl class="section return"><dt>Returns</dt><dd>Current DMA status (<a class="el" href="#a002cb188ea5156df0ba282e239a6e74b">NEORV32_DMA_STATUS_enum</a>) </dd></dl> + +</div> +</div> +<a id="a2ce0d31e04604b2523135d52a877febf" name="a2ce0d31e04604b2523135d52a877febf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2ce0d31e04604b2523135d52a877febf">&#9670;&#160;</a></span>neorv32_dma_transfer()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_dma_transfer </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>base_src</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>base_dst</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>config</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Trigger manual DMA transfer.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">base_src</td><td>Source base address (has to be aligned to source data type!). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">base_dst</td><td>Destination base address (has to be aligned to destination data type!). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Number of elements to transfer (24-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>Transfer type configuration/commands. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a6ebd1595ee6fa0e6cbfbd1ce7476f18e" name="a6ebd1595ee6fa0e6cbfbd1ce7476f18e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6ebd1595ee6fa0e6cbfbd1ce7476f18e">&#9670;&#160;</a></span>neorv32_dma_transfer_auto()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_dma_transfer_auto </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>base_src</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>base_dst</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>config</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>firq_sel</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>firq_type</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure automatic DMA transfer (triggered by CPU FIRQ).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">base_src</td><td>Source base address (has to be aligned to source data type!). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">base_dst</td><td>Destination base address (has to be aligned to destination data type!). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Number of elements to transfer (24-bit). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>Transfer type configuration/commands. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">firq_sel</td><td>FIRQ trigger select (<a class="el" href="neorv32__cpu__csr_8h.html#a6301c554bf831b97fc28f9984a1ec21b">NEORV32_CSR_MIP_enum</a>); only FIRQ0..FIRQ15 = 16..31. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">firq_type</td><td>Trigger on rising-edge (0) or high-level (1) of FIRQ channel. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__dma_8h_source.html b/sw/neorv32__dma_8h_source.html new file mode 100644 index 000000000..c4ef9bb0f --- /dev/null +++ b/sw/neorv32__dma_8h_source.html @@ -0,0 +1,228 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" 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name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_dma_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_dma_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__dma__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__dma__t.html#a8480d6ad3ba5063cdf21dca286711569"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__dma__t.html#a8480d6ad3ba5063cdf21dca286711569">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__dma__t.html#a3b214d1a373c7f15b374e113d7110b42"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__dma__t.html#a3b214d1a373c7f15b374e113d7110b42">SRC_BASE</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"><a class="line" href="structneorv32__dma__t.html#aee8a6cf3cbd9fe3c5995f046ffb9a1c0"> 32</a></span> uint32_t <a class="code hl_variable" href="structneorv32__dma__t.html#aee8a6cf3cbd9fe3c5995f046ffb9a1c0">DST_BASE</a>; </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"><a class="line" href="structneorv32__dma__t.html#a70c28642195765409d97b941e98f47ca"> 33</a></span> uint32_t <a class="code hl_variable" href="structneorv32__dma__t.html#a70c28642195765409d97b941e98f47ca">TTYPE</a>; </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span>} <a class="code hl_struct" href="structneorv32__dma__t.html">neorv32_dma_t</a>;</div> +</div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a0dcb61a0e0d2b45beb7818015adc8639"> 37</a></span><span class="preprocessor">#define NEORV32_DMA ((neorv32_dma_t*) (NEORV32_DMA_BASE))</span></div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> </div> +<div class="foldopen" id="foldopen00040" data-start="{" data-end="};"> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4"> 40</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4">NEORV32_DMA_CTRL_enum</a> {</div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a5f39deea0212f45423243c8100c40838"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a5f39deea0212f45423243c8100c40838">DMA_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a5aeeb05d6365d94d92808df2490daa3b"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a5aeeb05d6365d94d92808df2490daa3b">DMA_CTRL_AUTO</a> = 1, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4ace9fdcdfa8784abad30e033c273e7d00"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4ace9fdcdfa8784abad30e033c273e7d00">DMA_CTRL_FENCE</a> = 2, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a539609fc4d80867b3eb98c78206f5f96"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a539609fc4d80867b3eb98c78206f5f96">DMA_CTRL_ERROR_RD</a> = 8, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4af7e038b0b0e3ac64f5a2c598eb9c5101"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4af7e038b0b0e3ac64f5a2c598eb9c5101">DMA_CTRL_ERROR_WR</a> = 9, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a8e5ff34ac48eea4b352378bb2af47bcb"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a8e5ff34ac48eea4b352378bb2af47bcb">DMA_CTRL_BUSY</a> = 10, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a0d51df1bb87dc54d331891c5db787bcc"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a0d51df1bb87dc54d331891c5db787bcc">DMA_CTRL_DONE</a> = 11, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4aeaf5ee8f6a84668aa15cd3e21f076afe"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4aeaf5ee8f6a84668aa15cd3e21f076afe">DMA_CTRL_FIRQ_TYPE</a> = 15, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4aaf040e663494b39b890d7171d0a584b9"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4aaf040e663494b39b890d7171d0a584b9">DMA_CTRL_FIRQ_SEL_LSB</a> = 16, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a3eba1f7868f0c985effb69785ced011a">DMA_CTRL_FIRQ_SEL_MSB</a> = 19 </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a3eba1f7868f0c985effb69785ced011a"> 53</a></span>};</div> +</div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> </div> +<div class="foldopen" id="foldopen00056" data-start="{" data-end="};"> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9"> 56</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9">NEORV32_DMA_TTYPE_enum</a> {</div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a8dba4160c033c763f5102928c471e450"> 57</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a8dba4160c033c763f5102928c471e450">DMA_TTYPE_NUM_LSB</a> = 0, </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a61553eee00ed2382565bf826074c44bd"> 58</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a61553eee00ed2382565bf826074c44bd">DMA_TTYPE_NUM_MSB</a> = 23, </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2"> 60</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2">DMA_TTYPE_QSEL_LSB</a> = 27, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a4217c9a8ac4ccc52bb45944f30a598c5"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a4217c9a8ac4ccc52bb45944f30a598c5">DMA_TTYPE_QSEL_MSB</a> = 28, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a4b99a30b851851f3388dd4e77effacec"> 62</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a4b99a30b851851f3388dd4e77effacec">DMA_TTYPE_SRC_INC</a> = 29, </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da"> 63</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da">DMA_TTYPE_DST_INC</a> = 30, </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a37ea8ef1e6b342db330d3885545fc802">DMA_TTYPE_ENDIAN</a> = 31 </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a37ea8ef1e6b342db330d3885545fc802"> 65</a></span>};</div> +</div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a5e01d4454c97eb8e4ecd1455090bbfa9"> 73</a></span><span class="preprocessor">#define DMA_CMD_B2B (0b00 &lt;&lt; DMA_TTYPE_QSEL_LSB) </span><span class="comment">// byte to byte</span></div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#aeb63f99217f14d1ddde35c1f6c104e72"> 74</a></span><span class="preprocessor">#define DMA_CMD_B2UW (0b01 &lt;&lt; DMA_TTYPE_QSEL_LSB) </span><span class="comment">// byte to unsigned word</span></div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#adfecb3debff251070e4f6eb809412129"> 75</a></span><span class="preprocessor">#define DMA_CMD_B2SW (0b10 &lt;&lt; DMA_TTYPE_QSEL_LSB) </span><span class="comment">// byte to signed word</span></div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a13a16ba8d6daf9c82312bf4d392d15a8"> 76</a></span><span class="preprocessor">#define DMA_CMD_W2W (0b11 &lt;&lt; DMA_TTYPE_QSEL_LSB) </span><span class="comment">// word to word</span></div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span> </div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#ae380022d8b8fb70da91f0892f2bc32c8"> 78</a></span><span class="preprocessor">#define DMA_CMD_SRC_CONST (0b0 &lt;&lt; DMA_TTYPE_SRC_INC) </span><span class="comment">// constant source address</span></div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#acc081d58b53d1eddd2bff35b128d7da2"> 79</a></span><span class="preprocessor">#define DMA_CMD_SRC_INC (0b1 &lt;&lt; DMA_TTYPE_SRC_INC) </span><span class="comment">// incrementing source address</span></div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span> </div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a6a0ce532aad39e6489e9d52bcb6f4cd2"> 81</a></span><span class="preprocessor">#define DMA_CMD_DST_CONST (0b0 &lt;&lt; DMA_TTYPE_DST_INC) </span><span class="comment">// constant destination address</span></div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a61caa2602c6b148af55d990e3c0ae6be"> 82</a></span><span class="preprocessor">#define DMA_CMD_DST_INC (0b1 &lt;&lt; DMA_TTYPE_DST_INC) </span><span class="comment">// incrementing destination address</span></div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span> </div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a18fb7faa0a35f562821ca854d7c648b4"> 84</a></span><span class="preprocessor">#define DMA_CMD_ENDIAN (0b1 &lt;&lt; DMA_TTYPE_ENDIAN) </span><span class="comment">// convert endianness</span></div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span><span class="comment">/**********************************************************************/</span><span class="preprocessor"></span></div> +<div class="foldopen" id="foldopen00091" data-start="{" data-end="};"> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74b"> 91</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74b">NEORV32_DMA_STATUS_enum</a> {</div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74ba038b6ef194c3db158cb59168f763a7b8"> 92</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74ba038b6ef194c3db158cb59168f763a7b8">DMA_STATUS_ERR_WR</a> = -2, </div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74baed7242b847e3cc8cf20d7da99f9b1492"> 93</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74baed7242b847e3cc8cf20d7da99f9b1492">DMA_STATUS_ERR_RD</a> = -1, </div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74bac9c380cd5729386e5f5673e20b86326f"> 94</a></span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74bac9c380cd5729386e5f5673e20b86326f">DMA_STATUS_IDLE</a> = 0, </div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span> <a class="code hl_enumvalue" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74bad0f66e962296f5451d73dc1cae1fdc0d">DMA_STATUS_BUSY</a> = 1 </div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"><a class="line" href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74bad0f66e962296f5451d73dc1cae1fdc0d"> 96</a></span>};</div> +</div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> </div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> </div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__dma_8h.html#a13260c3252f0375d8982590d270d7dfd">neorv32_dma_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__dma_8h.html#ac3b72447e8a132faf26577ac714b8284">neorv32_dma_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__dma_8h.html#a6df244028455cf7f8d4cf1520c4670a7">neorv32_dma_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__dma_8h.html#a2c7257567ccdb7a986f5ef7c74d3917c">neorv32_dma_fence_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__dma_8h.html#a8f37adfa07050b0a1cb8430c9ce1fcc2">neorv32_dma_fence_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__dma_8h.html#a2ce0d31e04604b2523135d52a877febf">neorv32_dma_transfer</a>(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config);</div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__dma_8h.html#a6ebd1595ee6fa0e6cbfbd1ce7476f18e">neorv32_dma_transfer_auto</a>(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config, <span class="keywordtype">int</span> firq_sel, <span class="keywordtype">int</span> firq_type);</div> +<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__dma_8h.html#aa116f9714174abbe8a3583e441fee24b">neorv32_dma_status</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__dma_8h.html#afc8cc32f7d80d0f5ab33b2f1ecf77956">neorv32_dma_done</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_dma_h</span></div> +<div class="ttc" id="aneorv32__dma_8h_html_a002cb188ea5156df0ba282e239a6e74b"><div class="ttname"><a href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74b">NEORV32_DMA_STATUS_enum</a></div><div class="ttdeci">NEORV32_DMA_STATUS_enum</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:91</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a002cb188ea5156df0ba282e239a6e74ba038b6ef194c3db158cb59168f763a7b8"><div class="ttname"><a href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74ba038b6ef194c3db158cb59168f763a7b8">DMA_STATUS_ERR_WR</a></div><div class="ttdeci">@ DMA_STATUS_ERR_WR</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:92</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a002cb188ea5156df0ba282e239a6e74bac9c380cd5729386e5f5673e20b86326f"><div class="ttname"><a href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74bac9c380cd5729386e5f5673e20b86326f">DMA_STATUS_IDLE</a></div><div class="ttdeci">@ DMA_STATUS_IDLE</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:94</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a002cb188ea5156df0ba282e239a6e74bad0f66e962296f5451d73dc1cae1fdc0d"><div class="ttname"><a href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74bad0f66e962296f5451d73dc1cae1fdc0d">DMA_STATUS_BUSY</a></div><div class="ttdeci">@ DMA_STATUS_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:95</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a002cb188ea5156df0ba282e239a6e74baed7242b847e3cc8cf20d7da99f9b1492"><div class="ttname"><a href="neorv32__dma_8h.html#a002cb188ea5156df0ba282e239a6e74baed7242b847e3cc8cf20d7da99f9b1492">DMA_STATUS_ERR_RD</a></div><div class="ttdeci">@ DMA_STATUS_ERR_RD</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:93</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a13260c3252f0375d8982590d270d7dfd"><div class="ttname"><a href="neorv32__dma_8h.html#a13260c3252f0375d8982590d270d7dfd">neorv32_dma_available</a></div><div class="ttdeci">int neorv32_dma_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:26</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a2c7257567ccdb7a986f5ef7c74d3917c"><div class="ttname"><a href="neorv32__dma_8h.html#a2c7257567ccdb7a986f5ef7c74d3917c">neorv32_dma_fence_enable</a></div><div class="ttdeci">void neorv32_dma_fence_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:59</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a2ce0d31e04604b2523135d52a877febf"><div class="ttname"><a href="neorv32__dma_8h.html#a2ce0d31e04604b2523135d52a877febf">neorv32_dma_transfer</a></div><div class="ttdeci">void neorv32_dma_transfer(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:82</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a33187c5a074d62b46d2262e352edb8d9"><div class="ttname"><a href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9">NEORV32_DMA_TTYPE_enum</a></div><div class="ttdeci">NEORV32_DMA_TTYPE_enum</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:56</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a33187c5a074d62b46d2262e352edb8d9a37ea8ef1e6b342db330d3885545fc802"><div class="ttname"><a href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a37ea8ef1e6b342db330d3885545fc802">DMA_TTYPE_ENDIAN</a></div><div class="ttdeci">@ DMA_TTYPE_ENDIAN</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:64</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a33187c5a074d62b46d2262e352edb8d9a4217c9a8ac4ccc52bb45944f30a598c5"><div class="ttname"><a href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a4217c9a8ac4ccc52bb45944f30a598c5">DMA_TTYPE_QSEL_MSB</a></div><div class="ttdeci">@ DMA_TTYPE_QSEL_MSB</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:61</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a33187c5a074d62b46d2262e352edb8d9a4b99a30b851851f3388dd4e77effacec"><div class="ttname"><a href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a4b99a30b851851f3388dd4e77effacec">DMA_TTYPE_SRC_INC</a></div><div class="ttdeci">@ DMA_TTYPE_SRC_INC</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:62</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a33187c5a074d62b46d2262e352edb8d9a61553eee00ed2382565bf826074c44bd"><div class="ttname"><a href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a61553eee00ed2382565bf826074c44bd">DMA_TTYPE_NUM_MSB</a></div><div class="ttdeci">@ DMA_TTYPE_NUM_MSB</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:58</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a33187c5a074d62b46d2262e352edb8d9a8dba4160c033c763f5102928c471e450"><div class="ttname"><a href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9a8dba4160c033c763f5102928c471e450">DMA_TTYPE_NUM_LSB</a></div><div class="ttdeci">@ DMA_TTYPE_NUM_LSB</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:57</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da"><div class="ttname"><a href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9abb1293915b076e5d37be6724b44ab0da">DMA_TTYPE_DST_INC</a></div><div class="ttdeci">@ DMA_TTYPE_DST_INC</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:63</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2"><div class="ttname"><a href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9afcfdedeca4c4a1def4905660811e31e2">DMA_TTYPE_QSEL_LSB</a></div><div class="ttdeci">@ DMA_TTYPE_QSEL_LSB</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:60</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4">NEORV32_DMA_CTRL_enum</a></div><div class="ttdeci">NEORV32_DMA_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:40</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4a0d51df1bb87dc54d331891c5db787bcc"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a0d51df1bb87dc54d331891c5db787bcc">DMA_CTRL_DONE</a></div><div class="ttdeci">@ DMA_CTRL_DONE</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:48</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4a3eba1f7868f0c985effb69785ced011a"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a3eba1f7868f0c985effb69785ced011a">DMA_CTRL_FIRQ_SEL_MSB</a></div><div class="ttdeci">@ DMA_CTRL_FIRQ_SEL_MSB</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:52</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4a539609fc4d80867b3eb98c78206f5f96"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a539609fc4d80867b3eb98c78206f5f96">DMA_CTRL_ERROR_RD</a></div><div class="ttdeci">@ DMA_CTRL_ERROR_RD</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:45</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4a5aeeb05d6365d94d92808df2490daa3b"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a5aeeb05d6365d94d92808df2490daa3b">DMA_CTRL_AUTO</a></div><div class="ttdeci">@ DMA_CTRL_AUTO</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:42</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4a5f39deea0212f45423243c8100c40838"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a5f39deea0212f45423243c8100c40838">DMA_CTRL_EN</a></div><div class="ttdeci">@ DMA_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:41</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4a8e5ff34ac48eea4b352378bb2af47bcb"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4a8e5ff34ac48eea4b352378bb2af47bcb">DMA_CTRL_BUSY</a></div><div class="ttdeci">@ DMA_CTRL_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:47</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4aaf040e663494b39b890d7171d0a584b9"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4aaf040e663494b39b890d7171d0a584b9">DMA_CTRL_FIRQ_SEL_LSB</a></div><div class="ttdeci">@ DMA_CTRL_FIRQ_SEL_LSB</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:51</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4ace9fdcdfa8784abad30e033c273e7d00"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4ace9fdcdfa8784abad30e033c273e7d00">DMA_CTRL_FENCE</a></div><div class="ttdeci">@ DMA_CTRL_FENCE</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:43</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4aeaf5ee8f6a84668aa15cd3e21f076afe"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4aeaf5ee8f6a84668aa15cd3e21f076afe">DMA_CTRL_FIRQ_TYPE</a></div><div class="ttdeci">@ DMA_CTRL_FIRQ_TYPE</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:50</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6716eddb145b80ad38799da3b87cb2a4af7e038b0b0e3ac64f5a2c598eb9c5101"><div class="ttname"><a href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4af7e038b0b0e3ac64f5a2c598eb9c5101">DMA_CTRL_ERROR_WR</a></div><div class="ttdeci">@ DMA_CTRL_ERROR_WR</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:46</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6df244028455cf7f8d4cf1520c4670a7"><div class="ttname"><a href="neorv32__dma_8h.html#a6df244028455cf7f8d4cf1520c4670a7">neorv32_dma_disable</a></div><div class="ttdeci">void neorv32_dma_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:49</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a6ebd1595ee6fa0e6cbfbd1ce7476f18e"><div class="ttname"><a href="neorv32__dma_8h.html#a6ebd1595ee6fa0e6cbfbd1ce7476f18e">neorv32_dma_transfer_auto</a></div><div class="ttdeci">void neorv32_dma_transfer_auto(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config, int firq_sel, int firq_type)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:101</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_a8f37adfa07050b0a1cb8430c9ce1fcc2"><div class="ttname"><a href="neorv32__dma_8h.html#a8f37adfa07050b0a1cb8430c9ce1fcc2">neorv32_dma_fence_disable</a></div><div class="ttdeci">void neorv32_dma_fence_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:68</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_aa116f9714174abbe8a3583e441fee24b"><div class="ttname"><a href="neorv32__dma_8h.html#aa116f9714174abbe8a3583e441fee24b">neorv32_dma_status</a></div><div class="ttdeci">int neorv32_dma_status(void)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:121</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_ac3b72447e8a132faf26577ac714b8284"><div class="ttname"><a href="neorv32__dma_8h.html#ac3b72447e8a132faf26577ac714b8284">neorv32_dma_enable</a></div><div class="ttdeci">void neorv32_dma_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:40</div></div> +<div class="ttc" id="aneorv32__dma_8h_html_afc8cc32f7d80d0f5ab33b2f1ecf77956"><div class="ttname"><a href="neorv32__dma_8h.html#afc8cc32f7d80d0f5ab33b2f1ecf77956">neorv32_dma_done</a></div><div class="ttdeci">int neorv32_dma_done(void)</div><div class="ttdef"><b>Definition</b> neorv32_dma.c:146</div></div> +<div class="ttc" id="astructneorv32__dma__t_html"><div class="ttname"><a href="structneorv32__dma__t.html">neorv32_dma_t</a></div><div class="ttdef"><b>Definition</b> neorv32_dma.h:29</div></div> +<div class="ttc" id="astructneorv32__dma__t_html_a3b214d1a373c7f15b374e113d7110b42"><div class="ttname"><a href="structneorv32__dma__t.html#a3b214d1a373c7f15b374e113d7110b42">neorv32_dma_t::SRC_BASE</a></div><div class="ttdeci">uint32_t SRC_BASE</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:31</div></div> +<div class="ttc" id="astructneorv32__dma__t_html_a70c28642195765409d97b941e98f47ca"><div class="ttname"><a href="structneorv32__dma__t.html#a70c28642195765409d97b941e98f47ca">neorv32_dma_t::TTYPE</a></div><div class="ttdeci">uint32_t TTYPE</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:33</div></div> +<div class="ttc" id="astructneorv32__dma__t_html_a8480d6ad3ba5063cdf21dca286711569"><div class="ttname"><a href="structneorv32__dma__t.html#a8480d6ad3ba5063cdf21dca286711569">neorv32_dma_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:30</div></div> +<div class="ttc" id="astructneorv32__dma__t_html_aee8a6cf3cbd9fe3c5995f046ffb9a1c0"><div class="ttname"><a href="structneorv32__dma__t.html#aee8a6cf3cbd9fe3c5995f046ffb9a1c0">neorv32_dma_t::DST_BASE</a></div><div class="ttdeci">uint32_t DST_BASE</div><div class="ttdef"><b>Definition</b> neorv32_dma.h:32</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__gpio_8c.html b/sw/neorv32__gpio_8c.html new file mode 100644 index 000000000..cdf64fd38 --- /dev/null +++ b/sw/neorv32__gpio_8c.html @@ -0,0 +1,296 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>General purpose input/output port unit (GPIO) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a41d39a41ba5879eb85d3ed4481fcff81" id="r_a41d39a41ba5879eb85d3ed4481fcff81"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a41d39a41ba5879eb85d3ed4481fcff81">neorv32_gpio_available</a> (void)</td></tr> +<tr class="separator:a41d39a41ba5879eb85d3ed4481fcff81"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a60fd0830d634f0c1f784d815384665cb" id="r_a60fd0830d634f0c1f784d815384665cb"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a60fd0830d634f0c1f784d815384665cb">neorv32_gpio_pin_set</a> (int pin, int value)</td></tr> +<tr class="separator:a60fd0830d634f0c1f784d815384665cb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1958850fc1689eae9ddfcaa4a7513400" id="r_a1958850fc1689eae9ddfcaa4a7513400"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1958850fc1689eae9ddfcaa4a7513400">neorv32_gpio_pin_toggle</a> (int pin)</td></tr> +<tr class="separator:a1958850fc1689eae9ddfcaa4a7513400"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afa3ee54aca47ff35f706b627ac66e95a" id="r_afa3ee54aca47ff35f706b627ac66e95a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afa3ee54aca47ff35f706b627ac66e95a">neorv32_gpio_pin_get</a> (int pin)</td></tr> +<tr class="separator:afa3ee54aca47ff35f706b627ac66e95a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8dc7846945e4609fc96d81caee99ac00" id="r_a8dc7846945e4609fc96d81caee99ac00"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8dc7846945e4609fc96d81caee99ac00">neorv32_gpio_port_set</a> (uint64_t port_data)</td></tr> +<tr class="separator:a8dc7846945e4609fc96d81caee99ac00"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a210529f789779387d3f014e6253e803f" id="r_a210529f789779387d3f014e6253e803f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a210529f789779387d3f014e6253e803f">neorv32_gpio_port_toggle</a> (uint64_t toggle)</td></tr> +<tr class="separator:a210529f789779387d3f014e6253e803f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac42379f2fb5ca0bb63850d7957852b84" id="r_ac42379f2fb5ca0bb63850d7957852b84"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac42379f2fb5ca0bb63850d7957852b84">neorv32_gpio_port_get</a> (void)</td></tr> +<tr class="separator:ac42379f2fb5ca0bb63850d7957852b84"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>General purpose input/output port unit (GPIO) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the GPIO unit was synthesized (IO_GPIO_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a41d39a41ba5879eb85d3ed4481fcff81" name="a41d39a41ba5879eb85d3ed4481fcff81"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a41d39a41ba5879eb85d3ed4481fcff81">&#9670;&#160;</a></span>neorv32_gpio_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_gpio_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if GPIO unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if GPIO was not synthesized, 1 if GPIO is available. </dd></dl> + +</div> +</div> +<a id="afa3ee54aca47ff35f706b627ac66e95a" name="afa3ee54aca47ff35f706b627ac66e95a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afa3ee54aca47ff35f706b627ac66e95a">&#9670;&#160;</a></span>neorv32_gpio_pin_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_gpio_pin_get </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>pin</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get single pin of GPIO's input port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">pin</td><td>Input pin to be read (0..63). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>=0 if pin is low, !=0 if pin is high. </dd></dl> + +</div> +</div> +<a id="a60fd0830d634f0c1f784d815384665cb" name="a60fd0830d634f0c1f784d815384665cb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a60fd0830d634f0c1f784d815384665cb">&#9670;&#160;</a></span>neorv32_gpio_pin_set()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gpio_pin_set </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>pin</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>value</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set single pin of GPIO's output port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">pin</td><td>Output pin number to be set (0..63). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Set pint high (1) or low (0). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a1958850fc1689eae9ddfcaa4a7513400" name="a1958850fc1689eae9ddfcaa4a7513400"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1958850fc1689eae9ddfcaa4a7513400">&#9670;&#160;</a></span>neorv32_gpio_pin_toggle()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gpio_pin_toggle </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>pin</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Toggle single pin of GPIO's output port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">pin</td><td>Output pin number to be toggled (0..63). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac42379f2fb5ca0bb63850d7957852b84" name="ac42379f2fb5ca0bb63850d7957852b84"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac42379f2fb5ca0bb63850d7957852b84">&#9670;&#160;</a></span>neorv32_gpio_port_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_gpio_port_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get complete GPIO input port.</p> +<dl class="section return"><dt>Returns</dt><dd>Current input port state (64-bit). </dd></dl> + +</div> +</div> +<a id="a8dc7846945e4609fc96d81caee99ac00" name="a8dc7846945e4609fc96d81caee99ac00"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8dc7846945e4609fc96d81caee99ac00">&#9670;&#160;</a></span>neorv32_gpio_port_set()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gpio_port_set </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>port_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set complete GPIO output port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">port_data</td><td>New output port value (64-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a210529f789779387d3f014e6253e803f" name="a210529f789779387d3f014e6253e803f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a210529f789779387d3f014e6253e803f">&#9670;&#160;</a></span>neorv32_gpio_port_toggle()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gpio_port_toggle </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>toggle</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Toggle bit in entire GPIO output port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">toggle</td><td>Bit mask; set bits will toggle the according output port (64-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__gpio_8h.html b/sw/neorv32__gpio_8h.html new file mode 100644 index 000000000..972817b10 --- /dev/null +++ b/sw/neorv32__gpio_8h.html @@ -0,0 +1,326 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta 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+<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__gpio_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__gpio__t.html">neorv32_gpio_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">IO Device: General Purpose Input/Output Port Unit (GPIO)</div></td></tr> +<tr class="memitem:a1e35bbf26b9d1aa5373af0b9468eb445" id="r_a1e35bbf26b9d1aa5373af0b9468eb445"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1e35bbf26b9d1aa5373af0b9468eb445">NEORV32_GPIO</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__gpio__t.html">neorv32_gpio_t</a>*) (<a class="el" href="neorv32_8h.html#a7fd1e24d4de2eed7bf9cd5391562c7f4">NEORV32_GPIO_BASE</a>))</td></tr> +<tr class="separator:a1e35bbf26b9d1aa5373af0b9468eb445"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:a41d39a41ba5879eb85d3ed4481fcff81" id="r_a41d39a41ba5879eb85d3ed4481fcff81"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a41d39a41ba5879eb85d3ed4481fcff81">neorv32_gpio_available</a> (void)</td></tr> +<tr class="separator:a41d39a41ba5879eb85d3ed4481fcff81"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a60fd0830d634f0c1f784d815384665cb" id="r_a60fd0830d634f0c1f784d815384665cb"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a60fd0830d634f0c1f784d815384665cb">neorv32_gpio_pin_set</a> (int pin, int value)</td></tr> +<tr class="separator:a60fd0830d634f0c1f784d815384665cb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1958850fc1689eae9ddfcaa4a7513400" id="r_a1958850fc1689eae9ddfcaa4a7513400"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1958850fc1689eae9ddfcaa4a7513400">neorv32_gpio_pin_toggle</a> (int pin)</td></tr> +<tr class="separator:a1958850fc1689eae9ddfcaa4a7513400"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afa3ee54aca47ff35f706b627ac66e95a" id="r_afa3ee54aca47ff35f706b627ac66e95a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afa3ee54aca47ff35f706b627ac66e95a">neorv32_gpio_pin_get</a> (int pin)</td></tr> +<tr class="separator:afa3ee54aca47ff35f706b627ac66e95a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a789222709485cd8467aad5eddf69d2df" id="r_a789222709485cd8467aad5eddf69d2df"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a789222709485cd8467aad5eddf69d2df">neorv32_gpio_port_set</a> (uint64_t d)</td></tr> +<tr class="separator:a789222709485cd8467aad5eddf69d2df"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a210529f789779387d3f014e6253e803f" id="r_a210529f789779387d3f014e6253e803f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a210529f789779387d3f014e6253e803f">neorv32_gpio_port_toggle</a> (uint64_t toggle)</td></tr> +<tr class="separator:a210529f789779387d3f014e6253e803f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac42379f2fb5ca0bb63850d7957852b84" id="r_ac42379f2fb5ca0bb63850d7957852b84"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac42379f2fb5ca0bb63850d7957852b84">neorv32_gpio_port_get</a> (void)</td></tr> +<tr class="separator:ac42379f2fb5ca0bb63850d7957852b84"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>General purpose input/output port unit (GPIO) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the GPIO unit was synthesized (IO_GPIO_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a1e35bbf26b9d1aa5373af0b9468eb445" name="a1e35bbf26b9d1aa5373af0b9468eb445"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1e35bbf26b9d1aa5373af0b9468eb445">&#9670;&#160;</a></span>NEORV32_GPIO</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_GPIO&#160;&#160;&#160;((<a class="el" href="structneorv32__gpio__t.html">neorv32_gpio_t</a>*) (<a class="el" href="neorv32_8h.html#a7fd1e24d4de2eed7bf9cd5391562c7f4">NEORV32_GPIO_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>GPIO module hardware access (<a class="el" href="structneorv32__gpio__t.html">neorv32_gpio_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a41d39a41ba5879eb85d3ed4481fcff81" name="a41d39a41ba5879eb85d3ed4481fcff81"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a41d39a41ba5879eb85d3ed4481fcff81">&#9670;&#160;</a></span>neorv32_gpio_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_gpio_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if GPIO unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if GPIO was not synthesized, 1 if GPIO is available. </dd></dl> + +</div> +</div> +<a id="afa3ee54aca47ff35f706b627ac66e95a" name="afa3ee54aca47ff35f706b627ac66e95a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afa3ee54aca47ff35f706b627ac66e95a">&#9670;&#160;</a></span>neorv32_gpio_pin_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_gpio_pin_get </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>pin</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get single pin of GPIO's input port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">pin</td><td>Input pin to be read (0..63). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>=0 if pin is low, !=0 if pin is high. </dd></dl> + +</div> +</div> +<a id="a60fd0830d634f0c1f784d815384665cb" name="a60fd0830d634f0c1f784d815384665cb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a60fd0830d634f0c1f784d815384665cb">&#9670;&#160;</a></span>neorv32_gpio_pin_set()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gpio_pin_set </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>pin</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>value</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set single pin of GPIO's output port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">pin</td><td>Output pin number to be set (0..63). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Set pint high (1) or low (0). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a1958850fc1689eae9ddfcaa4a7513400" name="a1958850fc1689eae9ddfcaa4a7513400"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1958850fc1689eae9ddfcaa4a7513400">&#9670;&#160;</a></span>neorv32_gpio_pin_toggle()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gpio_pin_toggle </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>pin</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Toggle single pin of GPIO's output port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">pin</td><td>Output pin number to be toggled (0..63). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac42379f2fb5ca0bb63850d7957852b84" name="ac42379f2fb5ca0bb63850d7957852b84"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac42379f2fb5ca0bb63850d7957852b84">&#9670;&#160;</a></span>neorv32_gpio_port_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_gpio_port_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get complete GPIO input port.</p> +<dl class="section return"><dt>Returns</dt><dd>Current input port state (64-bit). </dd></dl> + +</div> +</div> +<a id="a789222709485cd8467aad5eddf69d2df" name="a789222709485cd8467aad5eddf69d2df"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a789222709485cd8467aad5eddf69d2df">&#9670;&#160;</a></span>neorv32_gpio_port_set()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gpio_port_set </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>port_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set complete GPIO output port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">port_data</td><td>New output port value (64-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a210529f789779387d3f014e6253e803f" name="a210529f789779387d3f014e6253e803f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a210529f789779387d3f014e6253e803f">&#9670;&#160;</a></span>neorv32_gpio_port_toggle()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gpio_port_toggle </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>toggle</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Toggle bit in entire GPIO output port.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">toggle</td><td>Bit mask; set bits will toggle the according output port (64-bit). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__gpio_8h_source.html b/sw/neorv32__gpio_8h_source.html new file mode 100644 index 000000000..c6338dbf8 --- /dev/null +++ b/sw/neorv32__gpio_8h_source.html @@ -0,0 +1,143 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> 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================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_gpio_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_gpio_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__gpio__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__gpio__t.html#a208ee622d43fee3574072f19a98c8808"> 30</a></span> <span class="keyword">const</span> uint32_t INPUT[2]; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__gpio__t.html#abaf7de4f79adfc3debcde93fa4a921bb"> 31</a></span> uint32_t OUTPUT[2]; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__gpio__t.html">neorv32_gpio_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__gpio_8h.html#a1e35bbf26b9d1aa5373af0b9468eb445"> 35</a></span><span class="preprocessor">#define NEORV32_GPIO ((neorv32_gpio_t*) (NEORV32_GPIO_BASE))</span></div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__gpio_8h.html#a41d39a41ba5879eb85d3ed4481fcff81">neorv32_gpio_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__gpio_8h.html#a60fd0830d634f0c1f784d815384665cb">neorv32_gpio_pin_set</a>(<span class="keywordtype">int</span> pin, <span class="keywordtype">int</span> value);</div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__gpio_8h.html#a1958850fc1689eae9ddfcaa4a7513400">neorv32_gpio_pin_toggle</a>(<span class="keywordtype">int</span> pin);</div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span>uint32_t <a class="code hl_function" href="neorv32__gpio_8h.html#afa3ee54aca47ff35f706b627ac66e95a">neorv32_gpio_pin_get</a>(<span class="keywordtype">int</span> pin);</div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__gpio_8h.html#a789222709485cd8467aad5eddf69d2df">neorv32_gpio_port_set</a>(uint64_t d);</div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__gpio_8h.html#a210529f789779387d3f014e6253e803f">neorv32_gpio_port_toggle</a>(uint64_t toggle);</div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span>uint64_t <a class="code hl_function" href="neorv32__gpio_8h.html#ac42379f2fb5ca0bb63850d7957852b84">neorv32_gpio_port_get</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_gpio_h</span></div> +<div class="ttc" id="aneorv32__gpio_8h_html_a1958850fc1689eae9ddfcaa4a7513400"><div class="ttname"><a href="neorv32__gpio_8h.html#a1958850fc1689eae9ddfcaa4a7513400">neorv32_gpio_pin_toggle</a></div><div class="ttdeci">void neorv32_gpio_pin_toggle(int pin)</div><div class="ttdef"><b>Definition</b> neorv32_gpio.c:62</div></div> +<div class="ttc" id="aneorv32__gpio_8h_html_a210529f789779387d3f014e6253e803f"><div class="ttname"><a href="neorv32__gpio_8h.html#a210529f789779387d3f014e6253e803f">neorv32_gpio_port_toggle</a></div><div class="ttdeci">void neorv32_gpio_port_toggle(uint64_t toggle)</div><div class="ttdef"><b>Definition</b> neorv32_gpio.c:104</div></div> +<div class="ttc" id="aneorv32__gpio_8h_html_a41d39a41ba5879eb85d3ed4481fcff81"><div class="ttname"><a href="neorv32__gpio_8h.html#a41d39a41ba5879eb85d3ed4481fcff81">neorv32_gpio_available</a></div><div class="ttdeci">int neorv32_gpio_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_gpio.c:26</div></div> +<div class="ttc" id="aneorv32__gpio_8h_html_a60fd0830d634f0c1f784d815384665cb"><div class="ttname"><a href="neorv32__gpio_8h.html#a60fd0830d634f0c1f784d815384665cb">neorv32_gpio_pin_set</a></div><div class="ttdeci">void neorv32_gpio_pin_set(int pin, int value)</div><div class="ttdef"><b>Definition</b> neorv32_gpio.c:43</div></div> +<div class="ttc" id="aneorv32__gpio_8h_html_a789222709485cd8467aad5eddf69d2df"><div class="ttname"><a href="neorv32__gpio_8h.html#a789222709485cd8467aad5eddf69d2df">neorv32_gpio_port_set</a></div><div class="ttdeci">void neorv32_gpio_port_set(uint64_t d)</div><div class="ttdef"><b>Definition</b> neorv32_gpio.c:89</div></div> +<div class="ttc" id="aneorv32__gpio_8h_html_ac42379f2fb5ca0bb63850d7957852b84"><div class="ttname"><a href="neorv32__gpio_8h.html#ac42379f2fb5ca0bb63850d7957852b84">neorv32_gpio_port_get</a></div><div class="ttdeci">uint64_t neorv32_gpio_port_get(void)</div><div class="ttdef"><b>Definition</b> neorv32_gpio.c:119</div></div> +<div class="ttc" id="aneorv32__gpio_8h_html_afa3ee54aca47ff35f706b627ac66e95a"><div class="ttname"><a href="neorv32__gpio_8h.html#afa3ee54aca47ff35f706b627ac66e95a">neorv32_gpio_pin_get</a></div><div class="ttdeci">uint32_t neorv32_gpio_pin_get(int pin)</div><div class="ttdef"><b>Definition</b> neorv32_gpio.c:76</div></div> +<div class="ttc" id="astructneorv32__gpio__t_html"><div class="ttname"><a href="structneorv32__gpio__t.html">neorv32_gpio_t</a></div><div class="ttdef"><b>Definition</b> neorv32_gpio.h:29</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a 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href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_gptmr.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>General purpose timer (GPTMR) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ae79a08c52ad3e83f9c4393acfabf035f" id="r_ae79a08c52ad3e83f9c4393acfabf035f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae79a08c52ad3e83f9c4393acfabf035f">neorv32_gptmr_available</a> (void)</td></tr> +<tr class="separator:ae79a08c52ad3e83f9c4393acfabf035f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6aa27efd2163eebf8fc49fe1c591708f" id="r_a6aa27efd2163eebf8fc49fe1c591708f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6aa27efd2163eebf8fc49fe1c591708f">neorv32_gptmr_setup</a> (int prsc, uint32_t threshold, int cont_mode)</td></tr> +<tr class="separator:a6aa27efd2163eebf8fc49fe1c591708f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7c9bc6d28ad12611b08fa2867c2db874" id="r_a7c9bc6d28ad12611b08fa2867c2db874"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7c9bc6d28ad12611b08fa2867c2db874">neorv32_gptmr_disable</a> (void)</td></tr> +<tr class="separator:a7c9bc6d28ad12611b08fa2867c2db874"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a59e684348835772a7e83446e478d4a13" id="r_a59e684348835772a7e83446e478d4a13"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a59e684348835772a7e83446e478d4a13">neorv32_gptmr_enable</a> (void)</td></tr> +<tr class="separator:a59e684348835772a7e83446e478d4a13"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac73aa4e41a064abb4ca554a389888e67" id="r_ac73aa4e41a064abb4ca554a389888e67"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac73aa4e41a064abb4ca554a389888e67">neorv32_gptmr_irq_ack</a> (void)</td></tr> +<tr class="separator:ac73aa4e41a064abb4ca554a389888e67"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>General purpose timer (GPTMR) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the GPTMR unit was synthesized (IO_GPTMR_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="ae79a08c52ad3e83f9c4393acfabf035f" name="ae79a08c52ad3e83f9c4393acfabf035f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae79a08c52ad3e83f9c4393acfabf035f">&#9670;&#160;</a></span>neorv32_gptmr_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_gptmr_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if general purpose timer unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if GPTMR was not synthesized, 1 if GPTMR is available. </dd></dl> + +</div> +</div> +<a id="a7c9bc6d28ad12611b08fa2867c2db874" name="a7c9bc6d28ad12611b08fa2867c2db874"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7c9bc6d28ad12611b08fa2867c2db874">&#9670;&#160;</a></span>neorv32_gptmr_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gptmr_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable general purpose timer. </p> + +</div> +</div> +<a id="a59e684348835772a7e83446e478d4a13" name="a59e684348835772a7e83446e478d4a13"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a59e684348835772a7e83446e478d4a13">&#9670;&#160;</a></span>neorv32_gptmr_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gptmr_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable general purpose timer. </p> + +</div> +</div> +<a id="ac73aa4e41a064abb4ca554a389888e67" name="ac73aa4e41a064abb4ca554a389888e67"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac73aa4e41a064abb4ca554a389888e67">&#9670;&#160;</a></span>neorv32_gptmr_irq_ack()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gptmr_irq_ack </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear pending timer interrupt. </p> + +</div> +</div> +<a id="a6aa27efd2163eebf8fc49fe1c591708f" name="a6aa27efd2163eebf8fc49fe1c591708f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6aa27efd2163eebf8fc49fe1c591708f">&#9670;&#160;</a></span>neorv32_gptmr_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gptmr_setup </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>threshold</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cont_mode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, enable and configure general purpose timer.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Clock prescaler select (0..7). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">threshold</td><td>Threshold value, counter will reset to zero when reaching this. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cont_mode</td><td>Set to operate timer in continuous mode (instead of single-shot mode). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__gptmr_8h.html b/sw/neorv32__gptmr_8h.html new file mode 100644 index 000000000..c7f49871d --- /dev/null +++ b/sw/neorv32__gptmr_8h.html @@ -0,0 +1,308 @@ +<!DOCTYPE html PUBLIC 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Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>General purpose timer (GPTMR) HW driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__gptmr_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__gptmr__t.html">neorv32_gptmr_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:ae79a08c52ad3e83f9c4393acfabf035f" id="r_ae79a08c52ad3e83f9c4393acfabf035f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae79a08c52ad3e83f9c4393acfabf035f">neorv32_gptmr_available</a> (void)</td></tr> +<tr class="separator:ae79a08c52ad3e83f9c4393acfabf035f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6aa27efd2163eebf8fc49fe1c591708f" id="r_a6aa27efd2163eebf8fc49fe1c591708f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6aa27efd2163eebf8fc49fe1c591708f">neorv32_gptmr_setup</a> (int prsc, uint32_t threshold, int cont_mode)</td></tr> +<tr class="separator:a6aa27efd2163eebf8fc49fe1c591708f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7c9bc6d28ad12611b08fa2867c2db874" id="r_a7c9bc6d28ad12611b08fa2867c2db874"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7c9bc6d28ad12611b08fa2867c2db874">neorv32_gptmr_disable</a> (void)</td></tr> +<tr class="separator:a7c9bc6d28ad12611b08fa2867c2db874"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a59e684348835772a7e83446e478d4a13" id="r_a59e684348835772a7e83446e478d4a13"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a59e684348835772a7e83446e478d4a13">neorv32_gptmr_enable</a> (void)</td></tr> +<tr class="separator:a59e684348835772a7e83446e478d4a13"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac73aa4e41a064abb4ca554a389888e67" id="r_ac73aa4e41a064abb4ca554a389888e67"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac73aa4e41a064abb4ca554a389888e67">neorv32_gptmr_irq_ack</a> (void)</td></tr> +<tr class="separator:ac73aa4e41a064abb4ca554a389888e67"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: General Purpose Timer (GPTMR)</h2></td></tr> +<tr class="memitem:a9e047791588ff21fc4dc1b06456bdfd2" id="r_a9e047791588ff21fc4dc1b06456bdfd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9e047791588ff21fc4dc1b06456bdfd2">NEORV32_GPTMR</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__gptmr__t.html">neorv32_gptmr_t</a>*) (<a class="el" href="neorv32_8h.html#a0991b1a5ba1e8c3550eb9770d43589d0">NEORV32_GPTMR_BASE</a>))</td></tr> +<tr class="separator:a9e047791588ff21fc4dc1b06456bdfd2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a135b0750d4afed16e5867134e3843988" id="r_a135b0750d4afed16e5867134e3843988"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a135b0750d4afed16e5867134e3843988">NEORV32_GPTMR_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a135b0750d4afed16e5867134e3843988abbfa7abcbd80b9c47e83e23e5cefaf90">GPTMR_CTRL_EN</a> = 0 +, <a class="el" href="#a135b0750d4afed16e5867134e3843988ae4716a7a9e356484a8e478f07920cde3">GPTMR_CTRL_PRSC0</a> = 1 +, <a class="el" href="#a135b0750d4afed16e5867134e3843988a1e1e8e516fa4918441e3c77153940298">GPTMR_CTRL_PRSC1</a> = 2 +, <a class="el" href="#a135b0750d4afed16e5867134e3843988a185861fbdc5f276735481237ad844833">GPTMR_CTRL_PRSC2</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#a135b0750d4afed16e5867134e3843988a473870880c0eca71578d6969e816af43">GPTMR_CTRL_MODE</a> = 4 +, <a class="el" href="#a135b0750d4afed16e5867134e3843988aadb663ad9a0dfd37fc65dffc1a289b38">GPTMR_CTRL_IRQ_CLR</a> = 30 +, <a class="el" href="#a135b0750d4afed16e5867134e3843988a3a868dc710ab9add083137e4e3fe888a">GPTMR_CTRL_IRQ_PND</a> = 31 +<br /> + }</td></tr> +<tr class="separator:a135b0750d4afed16e5867134e3843988"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>General purpose timer (GPTMR) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the GPTMR unit was synthesized (IO_GPTMR_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a9e047791588ff21fc4dc1b06456bdfd2" name="a9e047791588ff21fc4dc1b06456bdfd2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9e047791588ff21fc4dc1b06456bdfd2">&#9670;&#160;</a></span>NEORV32_GPTMR</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_GPTMR&#160;&#160;&#160;((<a class="el" href="structneorv32__gptmr__t.html">neorv32_gptmr_t</a>*) (<a class="el" href="neorv32_8h.html#a0991b1a5ba1e8c3550eb9770d43589d0">NEORV32_GPTMR_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>GPTMR module hardware access (<a class="el" href="structneorv32__gptmr__t.html">neorv32_gptmr_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a135b0750d4afed16e5867134e3843988" name="a135b0750d4afed16e5867134e3843988"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a135b0750d4afed16e5867134e3843988">&#9670;&#160;</a></span>NEORV32_GPTMR_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a135b0750d4afed16e5867134e3843988">NEORV32_GPTMR_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>GPTMR control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a135b0750d4afed16e5867134e3843988abbfa7abcbd80b9c47e83e23e5cefaf90" name="a135b0750d4afed16e5867134e3843988abbfa7abcbd80b9c47e83e23e5cefaf90"></a>GPTMR_CTRL_EN&#160;</td><td class="fielddoc"><p>GPTMR control register(0) (r/w): GPTMR enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a135b0750d4afed16e5867134e3843988ae4716a7a9e356484a8e478f07920cde3" name="a135b0750d4afed16e5867134e3843988ae4716a7a9e356484a8e478f07920cde3"></a>GPTMR_CTRL_PRSC0&#160;</td><td class="fielddoc"><p>GPTMR control register(1) (r/w): Clock prescaler select bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="a135b0750d4afed16e5867134e3843988a1e1e8e516fa4918441e3c77153940298" name="a135b0750d4afed16e5867134e3843988a1e1e8e516fa4918441e3c77153940298"></a>GPTMR_CTRL_PRSC1&#160;</td><td class="fielddoc"><p>GPTMR control register(2) (r/w): Clock prescaler select bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="a135b0750d4afed16e5867134e3843988a185861fbdc5f276735481237ad844833" name="a135b0750d4afed16e5867134e3843988a185861fbdc5f276735481237ad844833"></a>GPTMR_CTRL_PRSC2&#160;</td><td class="fielddoc"><p>GPTMR control register(3) (r/w): Clock prescaler select bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="a135b0750d4afed16e5867134e3843988a473870880c0eca71578d6969e816af43" name="a135b0750d4afed16e5867134e3843988a473870880c0eca71578d6969e816af43"></a>GPTMR_CTRL_MODE&#160;</td><td class="fielddoc"><p>GPTMR control register(4) (r/w): Operation mode (0=single-shot, 1=continuous) </p> +</td></tr> +<tr><td class="fieldname"><a id="a135b0750d4afed16e5867134e3843988aadb663ad9a0dfd37fc65dffc1a289b38" name="a135b0750d4afed16e5867134e3843988aadb663ad9a0dfd37fc65dffc1a289b38"></a>GPTMR_CTRL_IRQ_CLR&#160;</td><td class="fielddoc"><p>GPTMR control register(30) (-/w): Set to clear timer-match interrupt </p> +</td></tr> +<tr><td class="fieldname"><a id="a135b0750d4afed16e5867134e3843988a3a868dc710ab9add083137e4e3fe888a" name="a135b0750d4afed16e5867134e3843988a3a868dc710ab9add083137e4e3fe888a"></a>GPTMR_CTRL_IRQ_PND&#160;</td><td class="fielddoc"><p>GPTMR control register(31) (r/-): Timer-match interrupt pending </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ae79a08c52ad3e83f9c4393acfabf035f" name="ae79a08c52ad3e83f9c4393acfabf035f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae79a08c52ad3e83f9c4393acfabf035f">&#9670;&#160;</a></span>neorv32_gptmr_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_gptmr_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if general purpose timer unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if GPTMR was not synthesized, 1 if GPTMR is available. </dd></dl> + +</div> +</div> +<a id="a7c9bc6d28ad12611b08fa2867c2db874" name="a7c9bc6d28ad12611b08fa2867c2db874"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7c9bc6d28ad12611b08fa2867c2db874">&#9670;&#160;</a></span>neorv32_gptmr_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gptmr_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable general purpose timer. </p> + +</div> +</div> +<a id="a59e684348835772a7e83446e478d4a13" name="a59e684348835772a7e83446e478d4a13"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a59e684348835772a7e83446e478d4a13">&#9670;&#160;</a></span>neorv32_gptmr_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gptmr_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable general purpose timer. </p> + +</div> +</div> +<a id="ac73aa4e41a064abb4ca554a389888e67" name="ac73aa4e41a064abb4ca554a389888e67"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac73aa4e41a064abb4ca554a389888e67">&#9670;&#160;</a></span>neorv32_gptmr_irq_ack()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gptmr_irq_ack </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear pending timer interrupt. </p> + +</div> +</div> +<a id="a6aa27efd2163eebf8fc49fe1c591708f" name="a6aa27efd2163eebf8fc49fe1c591708f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6aa27efd2163eebf8fc49fe1c591708f">&#9670;&#160;</a></span>neorv32_gptmr_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_gptmr_setup </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>threshold</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cont_mode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, enable and configure general purpose timer.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Clock prescaler select (0..7). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">threshold</td><td>Threshold value, counter will reset to zero when reaching this. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cont_mode</td><td>Set to operate timer in continuous mode (instead of single-shot mode). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__gptmr_8h_source.html b/sw/neorv32__gptmr_8h_source.html new file mode 100644 index 000000000..edba27931 --- /dev/null +++ b/sw/neorv32__gptmr_8h_source.html @@ -0,0 +1,163 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_gptmr.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_gptmr_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_gptmr_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__gptmr__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__gptmr__t.html#a3c477ccb24ed12122d9d90244431c7e9"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__gptmr__t.html#a3c477ccb24ed12122d9d90244431c7e9">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__gptmr__t.html#a666ebcbea13dafcf1987629f3e0092ee"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__gptmr__t.html#a666ebcbea13dafcf1987629f3e0092ee">THRES</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"><a class="line" href="structneorv32__gptmr__t.html#a1abc5bae1dffc64006e965d4570da479"> 32</a></span> <span class="keyword">const</span> uint32_t <a class="code hl_variable" href="structneorv32__gptmr__t.html#a1abc5bae1dffc64006e965d4570da479">COUNT</a>; </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span>} <a class="code hl_struct" href="structneorv32__gptmr__t.html">neorv32_gptmr_t</a>;</div> +</div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> </div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a9e047791588ff21fc4dc1b06456bdfd2"> 36</a></span><span class="preprocessor">#define NEORV32_GPTMR ((neorv32_gptmr_t*) (NEORV32_GPTMR_BASE))</span></div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> </div> +<div class="foldopen" id="foldopen00039" data-start="{" data-end="};"> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988"> 39</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988">NEORV32_GPTMR_CTRL_enum</a> {</div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988abbfa7abcbd80b9c47e83e23e5cefaf90"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988abbfa7abcbd80b9c47e83e23e5cefaf90">GPTMR_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988ae4716a7a9e356484a8e478f07920cde3"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988ae4716a7a9e356484a8e478f07920cde3">GPTMR_CTRL_PRSC0</a> = 1, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a1e1e8e516fa4918441e3c77153940298"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a1e1e8e516fa4918441e3c77153940298">GPTMR_CTRL_PRSC1</a> = 2, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a185861fbdc5f276735481237ad844833"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a185861fbdc5f276735481237ad844833">GPTMR_CTRL_PRSC2</a> = 3, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a473870880c0eca71578d6969e816af43"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a473870880c0eca71578d6969e816af43">GPTMR_CTRL_MODE</a> = 4, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988aadb663ad9a0dfd37fc65dffc1a289b38"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988aadb663ad9a0dfd37fc65dffc1a289b38">GPTMR_CTRL_IRQ_CLR</a> = 30, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a3a868dc710ab9add083137e4e3fe888a"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a3a868dc710ab9add083137e4e3fe888a">GPTMR_CTRL_IRQ_PND</a> = 31, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span>};</div> +</div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__gptmr_8h.html#ae79a08c52ad3e83f9c4393acfabf035f">neorv32_gptmr_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__gptmr_8h.html#a6aa27efd2163eebf8fc49fe1c591708f">neorv32_gptmr_setup</a>(<span class="keywordtype">int</span> prsc, uint32_t threshold, <span class="keywordtype">int</span> cont_mode);</div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__gptmr_8h.html#a7c9bc6d28ad12611b08fa2867c2db874">neorv32_gptmr_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__gptmr_8h.html#a59e684348835772a7e83446e478d4a13">neorv32_gptmr_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__gptmr_8h.html#ac73aa4e41a064abb4ca554a389888e67">neorv32_gptmr_irq_ack</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_gptmr_h</span></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a135b0750d4afed16e5867134e3843988"><div class="ttname"><a href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988">NEORV32_GPTMR_CTRL_enum</a></div><div class="ttdeci">NEORV32_GPTMR_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:39</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a135b0750d4afed16e5867134e3843988a185861fbdc5f276735481237ad844833"><div class="ttname"><a href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a185861fbdc5f276735481237ad844833">GPTMR_CTRL_PRSC2</a></div><div class="ttdeci">@ GPTMR_CTRL_PRSC2</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:43</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a135b0750d4afed16e5867134e3843988a1e1e8e516fa4918441e3c77153940298"><div class="ttname"><a href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a1e1e8e516fa4918441e3c77153940298">GPTMR_CTRL_PRSC1</a></div><div class="ttdeci">@ GPTMR_CTRL_PRSC1</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:42</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a135b0750d4afed16e5867134e3843988a3a868dc710ab9add083137e4e3fe888a"><div class="ttname"><a href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a3a868dc710ab9add083137e4e3fe888a">GPTMR_CTRL_IRQ_PND</a></div><div class="ttdeci">@ GPTMR_CTRL_IRQ_PND</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:47</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a135b0750d4afed16e5867134e3843988a473870880c0eca71578d6969e816af43"><div class="ttname"><a href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988a473870880c0eca71578d6969e816af43">GPTMR_CTRL_MODE</a></div><div class="ttdeci">@ GPTMR_CTRL_MODE</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:44</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a135b0750d4afed16e5867134e3843988aadb663ad9a0dfd37fc65dffc1a289b38"><div class="ttname"><a href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988aadb663ad9a0dfd37fc65dffc1a289b38">GPTMR_CTRL_IRQ_CLR</a></div><div class="ttdeci">@ GPTMR_CTRL_IRQ_CLR</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:46</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a135b0750d4afed16e5867134e3843988abbfa7abcbd80b9c47e83e23e5cefaf90"><div class="ttname"><a href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988abbfa7abcbd80b9c47e83e23e5cefaf90">GPTMR_CTRL_EN</a></div><div class="ttdeci">@ GPTMR_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:40</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a135b0750d4afed16e5867134e3843988ae4716a7a9e356484a8e478f07920cde3"><div class="ttname"><a href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988ae4716a7a9e356484a8e478f07920cde3">GPTMR_CTRL_PRSC0</a></div><div class="ttdeci">@ GPTMR_CTRL_PRSC0</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:41</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a59e684348835772a7e83446e478d4a13"><div class="ttname"><a href="neorv32__gptmr_8h.html#a59e684348835772a7e83446e478d4a13">neorv32_gptmr_enable</a></div><div class="ttdeci">void neorv32_gptmr_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.c:69</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a6aa27efd2163eebf8fc49fe1c591708f"><div class="ttname"><a href="neorv32__gptmr_8h.html#a6aa27efd2163eebf8fc49fe1c591708f">neorv32_gptmr_setup</a></div><div class="ttdeci">void neorv32_gptmr_setup(int prsc, uint32_t threshold, int cont_mode)</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.c:44</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_a7c9bc6d28ad12611b08fa2867c2db874"><div class="ttname"><a href="neorv32__gptmr_8h.html#a7c9bc6d28ad12611b08fa2867c2db874">neorv32_gptmr_disable</a></div><div class="ttdeci">void neorv32_gptmr_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.c:60</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_ac73aa4e41a064abb4ca554a389888e67"><div class="ttname"><a href="neorv32__gptmr_8h.html#ac73aa4e41a064abb4ca554a389888e67">neorv32_gptmr_irq_ack</a></div><div class="ttdeci">void neorv32_gptmr_irq_ack(void)</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.c:78</div></div> +<div class="ttc" id="aneorv32__gptmr_8h_html_ae79a08c52ad3e83f9c4393acfabf035f"><div class="ttname"><a href="neorv32__gptmr_8h.html#ae79a08c52ad3e83f9c4393acfabf035f">neorv32_gptmr_available</a></div><div class="ttdeci">int neorv32_gptmr_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.c:26</div></div> +<div class="ttc" id="astructneorv32__gptmr__t_html"><div class="ttname"><a href="structneorv32__gptmr__t.html">neorv32_gptmr_t</a></div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:29</div></div> +<div class="ttc" id="astructneorv32__gptmr__t_html_a1abc5bae1dffc64006e965d4570da479"><div class="ttname"><a href="structneorv32__gptmr__t.html#a1abc5bae1dffc64006e965d4570da479">neorv32_gptmr_t::COUNT</a></div><div class="ttdeci">const uint32_t COUNT</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:32</div></div> +<div class="ttc" id="astructneorv32__gptmr__t_html_a3c477ccb24ed12122d9d90244431c7e9"><div class="ttname"><a href="structneorv32__gptmr__t.html#a3c477ccb24ed12122d9d90244431c7e9">neorv32_gptmr_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:30</div></div> +<div class="ttc" id="astructneorv32__gptmr__t_html_a666ebcbea13dafcf1987629f3e0092ee"><div class="ttname"><a href="structneorv32__gptmr__t.html#a666ebcbea13dafcf1987629f3e0092ee">neorv32_gptmr_t::THRES</a></div><div class="ttdeci">uint32_t THRES</div><div class="ttdef"><b>Definition</b> neorv32_gptmr.h:31</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__intrinsics_8h.html b/sw/neorv32__intrinsics_8h.html new file mode 100644 index 000000000..36c6fc8a2 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class="title">neorv32_intrinsics.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Helper macros for custom "intrinsics" / instructions. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__intrinsics_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">R2-type instruction format, RISC-V-standard</div></td></tr> +<tr class="memitem:affee8dbe3b5c3d9276d746f3123a1852" id="r_affee8dbe3b5c3d9276d746f3123a1852"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#affee8dbe3b5c3d9276d746f3123a1852">CUSTOM_INSTR_R2_TYPE</a>(funct7, funct5, rs1, funct3, opcode)</td></tr> +<tr class="separator:affee8dbe3b5c3d9276d746f3123a1852"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">R3-type instruction format, RISC-V-standard</div></td></tr> +<tr class="memitem:aaace8054623412d7799d6796a4e2b0cf" id="r_aaace8054623412d7799d6796a4e2b0cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aaace8054623412d7799d6796a4e2b0cf">CUSTOM_INSTR_R3_TYPE</a>(funct7, rs2, rs1, funct3, opcode)</td></tr> +<tr class="separator:aaace8054623412d7799d6796a4e2b0cf"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">R4-type instruction format, RISC-V-standard</div></td></tr> +<tr class="memitem:ac9c2ca822c98631d8ac29b016c679723" id="r_ac9c2ca822c98631d8ac29b016c679723"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac9c2ca822c98631d8ac29b016c679723">CUSTOM_INSTR_R4_TYPE</a>(rs3, rs2, rs1, funct3, opcode)</td></tr> +<tr class="separator:ac9c2ca822c98631d8ac29b016c679723"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">I-type instruction format, RISC-V-standard</div></td></tr> +<tr class="memitem:a840b2437cd74de8a77f573b3d9d24b06" id="r_a840b2437cd74de8a77f573b3d9d24b06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a840b2437cd74de8a77f573b3d9d24b06">CUSTOM_INSTR_I_TYPE</a>(imm12, rs1, funct3, opcode)</td></tr> +<tr class="separator:a840b2437cd74de8a77f573b3d9d24b06"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">S-type instruction format, RISC-V-standard</div></td></tr> +<tr class="memitem:abb4cad44dc2648f10f0e5153325c84d2" id="r_abb4cad44dc2648f10f0e5153325c84d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abb4cad44dc2648f10f0e5153325c84d2">CUSTOM_INSTR_S_TYPE</a>(imm12, rs2, rs1, funct3, opcode)</td></tr> +<tr class="separator:abb4cad44dc2648f10f0e5153325c84d2"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Register aliases (physical names and ABI names)</div></td></tr> +<tr class="memitem:a71b3ab3e49017d5ba7ccd89665e0cd45" id="r_a71b3ab3e49017d5ba7ccd89665e0cd45"><td class="memItemLeft" align="right" valign="top"><a id="a71b3ab3e49017d5ba7ccd89665e0cd45" name="a71b3ab3e49017d5ba7ccd89665e0cd45"></a> +&#160;</td><td class="memItemRight" valign="bottom"><b>asm</b> (&quot;.set reg_x0, 0 \n&quot; &quot;.set reg_x1, 1 \n&quot; &quot;.set reg_x2, 2 \n&quot; &quot;.set reg_x3, 3 \n&quot; &quot;.set reg_x4, 4 \n&quot; &quot;.set reg_x5, 5 \n&quot; &quot;.set reg_x6, 6 \n&quot; &quot;.set reg_x7, 7 \n&quot; &quot;.set reg_x8, 8 \n&quot; &quot;.set reg_x9, 9 \n&quot; &quot;.set reg_x10, 10 \n&quot; &quot;.set reg_x11, 11 \n&quot; &quot;.set reg_x12, 12 \n&quot; &quot;.set reg_x13, 13 \n&quot; &quot;.set reg_x14, 14 \n&quot; &quot;.set reg_x15, 15 \n&quot; &quot;.set reg_x16, 16 \n&quot; &quot;.set reg_x17, 17 \n&quot; &quot;.set reg_x18, 18 \n&quot; &quot;.set reg_x19, 19 \n&quot; &quot;.set reg_x20, 20 \n&quot; &quot;.set reg_x21, 21 \n&quot; &quot;.set reg_x22, 22 \n&quot; &quot;.set reg_x23, 23 \n&quot; &quot;.set reg_x24, 24 \n&quot; &quot;.set reg_x25, 25 \n&quot; &quot;.set reg_x26, 26 \n&quot; &quot;.set reg_x27, 27 \n&quot; &quot;.set reg_x28, 28 \n&quot; &quot;.set reg_x29, 29 \n&quot; &quot;.set reg_x30, 30 \n&quot; &quot;.set reg_x31, 31 \n&quot; &quot;.set reg_zero, 0 \n&quot; &quot;.set reg_ra, 1 \n&quot; &quot;.set reg_sp, 2 \n&quot; &quot;.set reg_gp, 3 \n&quot; &quot;.set reg_tp, 4 \n&quot; &quot;.set reg_t0, 5 \n&quot; &quot;.set reg_t1, 6 \n&quot; &quot;.set reg_t2, 7 \n&quot; &quot;.set reg_s0, 8 \n&quot; &quot;.set reg_s1, 9 \n&quot; &quot;.set reg_a0, 10 \n&quot; &quot;.set reg_a1, 11 \n&quot; &quot;.set reg_a2, 12 \n&quot; &quot;.set reg_a3, 13 \n&quot; &quot;.set reg_a4, 14 \n&quot; &quot;.set reg_a5, 15 \n&quot; &quot;.set reg_a6, 16 \n&quot; &quot;.set reg_a7, 17 \n&quot; &quot;.set reg_s2, 18 \n&quot; &quot;.set reg_s3, 19 \n&quot; &quot;.set reg_s4, 20 \n&quot; &quot;.set reg_s5, 21 \n&quot; &quot;.set reg_s6, 22 \n&quot; &quot;.set reg_s7, 23 \n&quot; &quot;.set reg_s8, 24 \n&quot; &quot;.set reg_s9, 25 \n&quot; &quot;.set reg_s10, 26 \n&quot; &quot;.set reg_s11, 27 \n&quot; &quot;.set reg_t3, 28 \n&quot; &quot;.set reg_t4, 29 \n&quot; &quot;.set reg_t5, 30 \n&quot; &quot;.set reg_t6, 31 \n&quot;)</td></tr> +<tr class="separator:a71b3ab3e49017d5ba7ccd89665e0cd45"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Helper macros for custom "intrinsics" / instructions. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a840b2437cd74de8a77f573b3d9d24b06" name="a840b2437cd74de8a77f573b3d9d24b06"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a840b2437cd74de8a77f573b3d9d24b06">&#9670;&#160;</a></span>CUSTOM_INSTR_I_TYPE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CUSTOM_INSTR_I_TYPE</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>imm12</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct3</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>opcode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">({ \</div> +<div class="line"> uint32_t __return; \</div> +<div class="line"> <span class="keyword">asm</span> <span class="keyword">volatile</span> ( \</div> +<div class="line"> <span class="stringliteral">&quot;.word ( \ (((&quot;</span> #imm12 <span class="stringliteral">&quot;) &amp; 0xfff) &lt;&lt; 20) | \ ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 15) | \ (((&quot;</span> #funct3 <span class="stringliteral">&quot;) &amp; 0x07) &lt;&lt; 12) | \ ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 7) | \ (((&quot;</span> #opcode <span class="stringliteral">&quot;) &amp; 0x7f) &lt;&lt; 0) \ );&quot;</span> \</div> +<div class="line"> : [rd] <span class="stringliteral">&quot;=r&quot;</span> (__return) \</div> +<div class="line"> : <span class="stringliteral">&quot;r&quot;</span> (rs1) \</div> +<div class="line"> ); \</div> +<div class="line"> __return; \</div> +<div class="line">})</div> +</div><!-- fragment --> +</div> +</div> +<a id="affee8dbe3b5c3d9276d746f3123a1852" name="affee8dbe3b5c3d9276d746f3123a1852"></a> +<h2 class="memtitle"><span class="permalink"><a href="#affee8dbe3b5c3d9276d746f3123a1852">&#9670;&#160;</a></span>CUSTOM_INSTR_R2_TYPE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CUSTOM_INSTR_R2_TYPE</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct7</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct5</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct3</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>opcode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">({ \</div> +<div class="line"> uint32_t __return; \</div> +<div class="line"> <span class="keyword">asm</span> <span class="keyword">volatile</span>( \</div> +<div class="line"> <span class="stringliteral">&quot;.word ( \ (((&quot;</span> #funct7 <span class="stringliteral">&quot;) &amp; 0x7f) &lt;&lt; 25) | \ (((&quot;</span> #funct5 <span class="stringliteral">&quot;) &amp; 0x1f) &lt;&lt; 20) | \ ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 15) | \ (((&quot;</span> #funct3 <span class="stringliteral">&quot;) &amp; 0x07) &lt;&lt; 12) | \ ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 7) | \ (((&quot;</span> #opcode <span class="stringliteral">&quot;) &amp; 0x7f) &lt;&lt; 0) \ );&quot;</span> \</div> +<div class="line"> : [rd] <span class="stringliteral">&quot;=r&quot;</span> (__return) \</div> +<div class="line"> : <span class="stringliteral">&quot;r&quot;</span> (rs1) \</div> +<div class="line"> ); \</div> +<div class="line"> __return; \</div> +<div class="line">})</div> +</div><!-- fragment --> +</div> +</div> +<a id="aaace8054623412d7799d6796a4e2b0cf" name="aaace8054623412d7799d6796a4e2b0cf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaace8054623412d7799d6796a4e2b0cf">&#9670;&#160;</a></span>CUSTOM_INSTR_R3_TYPE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CUSTOM_INSTR_R3_TYPE</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct7</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct3</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>opcode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">({ \</div> +<div class="line"> uint32_t __return; \</div> +<div class="line"> <span class="keyword">asm</span> <span class="keyword">volatile</span> ( \</div> +<div class="line"> <span class="stringliteral">&quot;.word ( \ (((&quot;</span> #funct7 <span class="stringliteral">&quot;) &amp; 0x7f) &lt;&lt; 25) | \ ((( reg_%2 ) &amp; 0x1f) &lt;&lt; 20) | \ ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 15) | \ (((&quot;</span> #funct3 <span class="stringliteral">&quot;) &amp; 0x07) &lt;&lt; 12) | \ ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 7) | \ (((&quot;</span> #opcode <span class="stringliteral">&quot;) &amp; 0x7f) &lt;&lt; 0) \ );&quot;</span> \</div> +<div class="line"> : [rd] <span class="stringliteral">&quot;=r&quot;</span> (__return) \</div> +<div class="line"> : <span class="stringliteral">&quot;r&quot;</span> (rs1), \</div> +<div class="line"> <span class="stringliteral">&quot;r&quot;</span> (rs2) \</div> +<div class="line"> ); \</div> +<div class="line"> __return; \</div> +<div class="line">})</div> +</div><!-- fragment --> +</div> +</div> +<a id="ac9c2ca822c98631d8ac29b016c679723" name="ac9c2ca822c98631d8ac29b016c679723"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac9c2ca822c98631d8ac29b016c679723">&#9670;&#160;</a></span>CUSTOM_INSTR_R4_TYPE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CUSTOM_INSTR_R4_TYPE</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs3</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct3</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>opcode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">({ \</div> +<div class="line"> uint32_t __return; \</div> +<div class="line"> <span class="keyword">asm</span> <span class="keyword">volatile</span> ( \</div> +<div class="line"> <span class="stringliteral">&quot;.word ( \ ((( reg_%3 ) &amp; 0x1f) &lt;&lt; 27) | \ ((( reg_%2 ) &amp; 0x1f) &lt;&lt; 20) | \ ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 15) | \ (((&quot;</span> #funct3 <span class="stringliteral">&quot;) &amp; 0x07) &lt;&lt; 12) | \ ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 7) | \ (((&quot;</span> #opcode <span class="stringliteral">&quot;) &amp; 0x7f) &lt;&lt; 0) \ );&quot;</span> \</div> +<div class="line"> : [rd] <span class="stringliteral">&quot;=r&quot;</span> (__return) \</div> +<div class="line"> : <span class="stringliteral">&quot;r&quot;</span> (rs1), \</div> +<div class="line"> <span class="stringliteral">&quot;r&quot;</span> (rs2), \</div> +<div class="line"> <span class="stringliteral">&quot;r&quot;</span> (rs3) \</div> +<div class="line"> ); \</div> +<div class="line"> __return; \</div> +<div class="line">})</div> +</div><!-- fragment --> +</div> +</div> +<a id="abb4cad44dc2648f10f0e5153325c84d2" name="abb4cad44dc2648f10f0e5153325c84d2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abb4cad44dc2648f10f0e5153325c84d2">&#9670;&#160;</a></span>CUSTOM_INSTR_S_TYPE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CUSTOM_INSTR_S_TYPE</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>imm12</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs2</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>rs1</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>funct3</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>opcode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">({ \</div> +<div class="line"> <span class="keyword">asm</span> <span class="keyword">volatile</span> ( \</div> +<div class="line"> <span class="stringliteral">&quot;.word ( \ ((((&quot;</span> #imm12 <span class="stringliteral">&quot;) &gt;&gt; 5) &amp; 0x7f) &lt;&lt; 25) | \ ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 20) | \ ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 15) | \ (((&quot;</span> #funct3 <span class="stringliteral">&quot;) &amp; 0x07) &lt;&lt; 12) | \ (((&quot;</span> #imm12 <span class="stringliteral">&quot;) &amp; 0x1f) &lt;&lt; 7) | \ (((&quot;</span> #opcode <span class="stringliteral">&quot;) &amp; 0x7f) &lt;&lt; 0) \ );&quot;</span> \</div> +<div class="line"> : \</div> +<div class="line"> : <span class="stringliteral">&quot;r&quot;</span> (rs1), \</div> +<div class="line"> <span class="stringliteral">&quot;r&quot;</span> (rs2) \</div> +<div class="line"> ); \</div> +<div class="line">})</div> +</div><!-- fragment --> +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__intrinsics_8h_source.html b/sw/neorv32__intrinsics_8h_source.html new file mode 100644 index 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class="title">neorv32_intrinsics.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__intrinsics_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_intrinsics_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_intrinsics_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="keyword">asm</span> (</div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span> <span class="stringliteral">&quot;.set reg_x0, 0 \n&quot;</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span> <span class="stringliteral">&quot;.set reg_x1, 1 \n&quot;</span></div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span> <span class="stringliteral">&quot;.set reg_x2, 2 \n&quot;</span></div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span> <span class="stringliteral">&quot;.set reg_x3, 3 \n&quot;</span></div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span> <span class="stringliteral">&quot;.set reg_x4, 4 \n&quot;</span></div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span> <span class="stringliteral">&quot;.set reg_x5, 5 \n&quot;</span></div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span> <span class="stringliteral">&quot;.set reg_x6, 6 \n&quot;</span></div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> <span class="stringliteral">&quot;.set reg_x7, 7 \n&quot;</span></div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> <span class="stringliteral">&quot;.set reg_x8, 8 \n&quot;</span></div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> <span class="stringliteral">&quot;.set reg_x9, 9 \n&quot;</span></div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> <span class="stringliteral">&quot;.set reg_x10, 10 \n&quot;</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> <span class="stringliteral">&quot;.set reg_x11, 11 \n&quot;</span></div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> <span class="stringliteral">&quot;.set reg_x12, 12 \n&quot;</span></div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> <span class="stringliteral">&quot;.set reg_x13, 13 \n&quot;</span></div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span> <span class="stringliteral">&quot;.set reg_x14, 14 \n&quot;</span></div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> <span class="stringliteral">&quot;.set reg_x15, 15 \n&quot;</span></div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span><span class="preprocessor">#ifndef __riscv_32e</span></div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> <span class="stringliteral">&quot;.set reg_x16, 16 \n&quot;</span></div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span> <span class="stringliteral">&quot;.set reg_x17, 17 \n&quot;</span></div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span> <span class="stringliteral">&quot;.set reg_x18, 18 \n&quot;</span></div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span> <span class="stringliteral">&quot;.set reg_x19, 19 \n&quot;</span></div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> <span class="stringliteral">&quot;.set reg_x20, 20 \n&quot;</span></div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span> <span class="stringliteral">&quot;.set reg_x21, 21 \n&quot;</span></div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> <span class="stringliteral">&quot;.set reg_x22, 22 \n&quot;</span></div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span> <span class="stringliteral">&quot;.set reg_x23, 23 \n&quot;</span></div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span> <span class="stringliteral">&quot;.set reg_x24, 24 \n&quot;</span></div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span> <span class="stringliteral">&quot;.set reg_x25, 25 \n&quot;</span></div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span> <span class="stringliteral">&quot;.set reg_x26, 26 \n&quot;</span></div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span> <span class="stringliteral">&quot;.set reg_x27, 27 \n&quot;</span></div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> <span class="stringliteral">&quot;.set reg_x28, 28 \n&quot;</span></div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span> <span class="stringliteral">&quot;.set reg_x29, 29 \n&quot;</span></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> <span class="stringliteral">&quot;.set reg_x30, 30 \n&quot;</span></div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span> <span class="stringliteral">&quot;.set reg_x31, 31 \n&quot;</span></div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> <span class="stringliteral">&quot;.set reg_zero, 0 \n&quot;</span></div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span> <span class="stringliteral">&quot;.set reg_ra, 1 \n&quot;</span></div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span> <span class="stringliteral">&quot;.set reg_sp, 2 \n&quot;</span></div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> <span class="stringliteral">&quot;.set reg_gp, 3 \n&quot;</span></div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span> <span class="stringliteral">&quot;.set reg_tp, 4 \n&quot;</span></div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span> <span class="stringliteral">&quot;.set reg_t0, 5 \n&quot;</span></div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span> <span class="stringliteral">&quot;.set reg_t1, 6 \n&quot;</span></div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span> <span class="stringliteral">&quot;.set reg_t2, 7 \n&quot;</span></div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span> <span class="stringliteral">&quot;.set reg_s0, 8 \n&quot;</span></div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span> <span class="stringliteral">&quot;.set reg_s1, 9 \n&quot;</span></div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span> <span class="stringliteral">&quot;.set reg_a0, 10 \n&quot;</span></div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span> <span class="stringliteral">&quot;.set reg_a1, 11 \n&quot;</span></div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span> <span class="stringliteral">&quot;.set reg_a2, 12 \n&quot;</span></div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span> <span class="stringliteral">&quot;.set reg_a3, 13 \n&quot;</span></div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span> <span class="stringliteral">&quot;.set reg_a4, 14 \n&quot;</span></div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span> <span class="stringliteral">&quot;.set reg_a5, 15 \n&quot;</span></div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="preprocessor">#ifndef __riscv_32e</span></div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span> <span class="stringliteral">&quot;.set reg_a6, 16 \n&quot;</span></div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span> <span class="stringliteral">&quot;.set reg_a7, 17 \n&quot;</span></div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span> <span class="stringliteral">&quot;.set reg_s2, 18 \n&quot;</span></div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span> <span class="stringliteral">&quot;.set reg_s3, 19 \n&quot;</span></div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span> <span class="stringliteral">&quot;.set reg_s4, 20 \n&quot;</span></div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span> <span class="stringliteral">&quot;.set reg_s5, 21 \n&quot;</span></div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span> <span class="stringliteral">&quot;.set reg_s6, 22 \n&quot;</span></div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span> <span class="stringliteral">&quot;.set reg_s7, 23 \n&quot;</span></div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span> <span class="stringliteral">&quot;.set reg_s8, 24 \n&quot;</span></div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span> <span class="stringliteral">&quot;.set reg_s9, 25 \n&quot;</span></div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span> <span class="stringliteral">&quot;.set reg_s10, 26 \n&quot;</span></div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span> <span class="stringliteral">&quot;.set reg_s11, 27 \n&quot;</span></div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span> <span class="stringliteral">&quot;.set reg_t3, 28 \n&quot;</span></div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span> <span class="stringliteral">&quot;.set reg_t4, 29 \n&quot;</span></div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span> <span class="stringliteral">&quot;.set reg_t5, 30 \n&quot;</span></div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span> <span class="stringliteral">&quot;.set reg_t6, 31 \n&quot;</span></div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span><span class="preprocessor">#endif</span></div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span>);</div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span> </div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span> </div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span><span class="preprocessor">#define CUSTOM_INSTR_R2_TYPE(funct7, funct5, rs1, funct3, opcode) \</span></div> +<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span><span class="preprocessor">({ \</span></div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span><span class="preprocessor"> uint32_t __return; \</span></div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span><span class="preprocessor"> asm volatile( \</span></div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span><span class="preprocessor"> &quot;.word ( \</span></div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span><span class="preprocessor"> (((&quot; #funct7 &quot;) &amp; 0x7f) &lt;&lt; 25) | \</span></div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span><span class="preprocessor"> (((&quot; #funct5 &quot;) &amp; 0x1f) &lt;&lt; 20) | \</span></div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span><span class="preprocessor"> ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 15) | \</span></div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span><span class="preprocessor"> (((&quot; #funct3 &quot;) &amp; 0x07) &lt;&lt; 12) | \</span></div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span><span class="preprocessor"> ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 7) | \</span></div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span><span class="preprocessor"> (((&quot; #opcode &quot;) &amp; 0x7f) &lt;&lt; 0) \</span></div> +<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span><span class="preprocessor"> );&quot; \</span></div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span><span class="preprocessor"> : [rd] &quot;=r&quot; (__return) \</span></div> +<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span><span class="preprocessor"> : &quot;r&quot; (rs1) \</span></div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span><span class="preprocessor"> ); \</span></div> +<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span><span class="preprocessor"> __return; \</span></div> +<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span><span class="preprocessor">})</span></div> +<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span> </div> +<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span> </div> +<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span><span class="preprocessor">#define CUSTOM_INSTR_R3_TYPE(funct7, rs2, rs1, funct3, opcode) \</span></div> +<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span><span class="preprocessor">({ \</span></div> +<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span><span class="preprocessor"> uint32_t __return; \</span></div> +<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span><span class="preprocessor"> asm volatile ( \</span></div> +<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span><span class="preprocessor"> &quot;.word ( \</span></div> +<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span><span class="preprocessor"> (((&quot; #funct7 &quot;) &amp; 0x7f) &lt;&lt; 25) | \</span></div> +<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"> 127</span><span class="preprocessor"> ((( reg_%2 ) &amp; 0x1f) &lt;&lt; 20) | \</span></div> +<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"> 128</span><span class="preprocessor"> ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 15) | \</span></div> +<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span><span class="preprocessor"> (((&quot; #funct3 &quot;) &amp; 0x07) &lt;&lt; 12) | \</span></div> +<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span><span class="preprocessor"> ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 7) | \</span></div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span><span class="preprocessor"> (((&quot; #opcode &quot;) &amp; 0x7f) &lt;&lt; 0) \</span></div> +<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span><span class="preprocessor"> );&quot; \</span></div> +<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span><span class="preprocessor"> : [rd] &quot;=r&quot; (__return) \</span></div> +<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"> 134</span><span class="preprocessor"> : &quot;r&quot; (rs1), \</span></div> +<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"> 135</span><span class="preprocessor"> &quot;r&quot; (rs2) \</span></div> +<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"> 136</span><span class="preprocessor"> ); \</span></div> +<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"> 137</span><span class="preprocessor"> __return; \</span></div> +<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"> 138</span><span class="preprocessor">})</span></div> +<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"> 139</span> </div> +<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span> </div> +<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span><span class="preprocessor">#define CUSTOM_INSTR_R4_TYPE(rs3, rs2, rs1, funct3, opcode) \</span></div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span><span class="preprocessor">({ \</span></div> +<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span><span class="preprocessor"> uint32_t __return; \</span></div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span><span class="preprocessor"> asm volatile ( \</span></div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span><span class="preprocessor"> &quot;.word ( \</span></div> +<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span><span class="preprocessor"> ((( reg_%3 ) &amp; 0x1f) &lt;&lt; 27) | \</span></div> +<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span><span class="preprocessor"> ((( reg_%2 ) &amp; 0x1f) &lt;&lt; 20) | \</span></div> +<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span><span class="preprocessor"> ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 15) | \</span></div> +<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span><span class="preprocessor"> (((&quot; #funct3 &quot;) &amp; 0x07) &lt;&lt; 12) | \</span></div> +<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span><span class="preprocessor"> ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 7) | \</span></div> +<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"> 154</span><span class="preprocessor"> (((&quot; #opcode &quot;) &amp; 0x7f) &lt;&lt; 0) \</span></div> +<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span><span class="preprocessor"> );&quot; \</span></div> +<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span><span class="preprocessor"> : [rd] &quot;=r&quot; (__return) \</span></div> +<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span><span class="preprocessor"> : &quot;r&quot; (rs1), \</span></div> +<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"> 158</span><span class="preprocessor"> &quot;r&quot; (rs2), \</span></div> +<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"> 159</span><span class="preprocessor"> &quot;r&quot; (rs3) \</span></div> +<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span><span class="preprocessor"> ); \</span></div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span><span class="preprocessor"> __return; \</span></div> +<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span><span class="preprocessor">})</span></div> +<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"> 163</span> </div> +<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span> </div> +<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span><span class="preprocessor">#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) \</span></div> +<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"> 169</span><span class="preprocessor">({ \</span></div> +<div class="line"><a id="l00170" name="l00170"></a><span class="lineno"> 170</span><span class="preprocessor"> uint32_t __return; \</span></div> +<div class="line"><a id="l00171" name="l00171"></a><span class="lineno"> 171</span><span class="preprocessor"> asm volatile ( \</span></div> +<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"> 172</span><span class="preprocessor"> &quot;.word ( \</span></div> +<div class="line"><a id="l00173" name="l00173"></a><span class="lineno"> 173</span><span class="preprocessor"> (((&quot; #imm12 &quot;) &amp; 0xfff) &lt;&lt; 20) | \</span></div> +<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"> 174</span><span class="preprocessor"> ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 15) | \</span></div> +<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span><span class="preprocessor"> (((&quot; #funct3 &quot;) &amp; 0x07) &lt;&lt; 12) | \</span></div> +<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span><span class="preprocessor"> ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 7) | \</span></div> +<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span><span class="preprocessor"> (((&quot; #opcode &quot;) &amp; 0x7f) &lt;&lt; 0) \</span></div> +<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span><span class="preprocessor"> );&quot; \</span></div> +<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span><span class="preprocessor"> : [rd] &quot;=r&quot; (__return) \</span></div> +<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span><span class="preprocessor"> : &quot;r&quot; (rs1) \</span></div> +<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span><span class="preprocessor"> ); \</span></div> +<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"> 182</span><span class="preprocessor"> __return; \</span></div> +<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"> 183</span><span class="preprocessor">})</span></div> +<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"> 184</span> </div> +<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"> 185</span> </div> +<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"> 186</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00189" name="l00189"></a><span class="lineno"> 189</span><span class="preprocessor">#define CUSTOM_INSTR_S_TYPE(imm12, rs2, rs1, funct3, opcode) \</span></div> +<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"> 190</span><span class="preprocessor">({ \</span></div> +<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span><span class="preprocessor"> asm volatile ( \</span></div> +<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"> 192</span><span class="preprocessor"> &quot;.word ( \</span></div> +<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span><span class="preprocessor"> ((((&quot; #imm12 &quot;) &gt;&gt; 5) &amp; 0x7f) &lt;&lt; 25) | \</span></div> +<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span><span class="preprocessor"> ((( reg_%1 ) &amp; 0x1f) &lt;&lt; 20) | \</span></div> +<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span><span class="preprocessor"> ((( reg_%0 ) &amp; 0x1f) &lt;&lt; 15) | \</span></div> +<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span><span class="preprocessor"> (((&quot; #funct3 &quot;) &amp; 0x07) &lt;&lt; 12) | \</span></div> +<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span><span class="preprocessor"> (((&quot; #imm12 &quot;) &amp; 0x1f) &lt;&lt; 7) | \</span></div> +<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span><span class="preprocessor"> (((&quot; #opcode &quot;) &amp; 0x7f) &lt;&lt; 0) \</span></div> +<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span><span class="preprocessor"> );&quot; \</span></div> +<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"> 200</span><span class="preprocessor"> : \</span></div> +<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"> 201</span><span class="preprocessor"> : &quot;r&quot; (rs1), \</span></div> +<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span><span class="preprocessor"> &quot;r&quot; (rs2) \</span></div> +<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span><span class="preprocessor"> ); \</span></div> +<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"> 204</span><span class="preprocessor">})</span></div> +<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"> 205</span> </div> +<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"> 206</span> </div> +<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"> 207</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_intrinsics_h</span></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__legacy_8h.html b/sw/neorv32__legacy_8h.html new file mode 100644 index 000000000..084f33b00 --- /dev/null +++ b/sw/neorv32__legacy_8h.html @@ -0,0 +1,182 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_legacy.h File Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_legacy.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Legacy compatibility layer. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__legacy_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">GPIO aliases</div></td></tr> +<tr class="memitem:aa6756856812e72ebdbe5a1b837e13330" id="r_aa6756856812e72ebdbe5a1b837e13330"><td class="memItemLeft" align="right" valign="top"><a id="aa6756856812e72ebdbe5a1b837e13330" name="aa6756856812e72ebdbe5a1b837e13330"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>INPUT_LO</b>&#160;&#160;&#160;INPUT[0]</td></tr> +<tr class="separator:aa6756856812e72ebdbe5a1b837e13330"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a328faf236a6a92f47d02f68d2865e5d3" id="r_a328faf236a6a92f47d02f68d2865e5d3"><td class="memItemLeft" align="right" valign="top"><a id="a328faf236a6a92f47d02f68d2865e5d3" name="a328faf236a6a92f47d02f68d2865e5d3"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>INPUT_HI</b>&#160;&#160;&#160;INPUT[1]</td></tr> +<tr class="separator:a328faf236a6a92f47d02f68d2865e5d3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4565c54eb2281f1089b38b4fbfb23ac2" id="r_a4565c54eb2281f1089b38b4fbfb23ac2"><td class="memItemLeft" align="right" valign="top"><a id="a4565c54eb2281f1089b38b4fbfb23ac2" name="a4565c54eb2281f1089b38b4fbfb23ac2"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>OUTPUT_LO</b>&#160;&#160;&#160;OUTPUT[0]</td></tr> +<tr class="separator:a4565c54eb2281f1089b38b4fbfb23ac2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae02c208a2f93a1931c0e2e43ca51cf8c" id="r_ae02c208a2f93a1931c0e2e43ca51cf8c"><td class="memItemLeft" align="right" valign="top"><a id="ae02c208a2f93a1931c0e2e43ca51cf8c" name="ae02c208a2f93a1931c0e2e43ca51cf8c"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>OUTPUT_HI</b>&#160;&#160;&#160;OUTPUT[1]</td></tr> +<tr class="separator:ae02c208a2f93a1931c0e2e43ca51cf8c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">Atomic LR/SC instructions</div></td></tr> +<tr class="memitem:a72a1e09e67f5ce1b522667e8e171d578" id="r_a72a1e09e67f5ce1b522667e8e171d578"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a72a1e09e67f5ce1b522667e8e171d578">neorv32_cpu_load_reservate_word</a>(addr, wdata)</td></tr> +<tr class="separator:a72a1e09e67f5ce1b522667e8e171d578"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac8325c90310ab06d305671b1aa169965" id="r_ac8325c90310ab06d305671b1aa169965"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac8325c90310ab06d305671b1aa169965">neorv32_cpu_store_conditional_word</a>(addr, wdata)</td></tr> +<tr class="separator:ac8325c90310ab06d305671b1aa169965"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Legacy compatibility layer. </p> +<dl class="section warning"><dt>Warning</dt><dd>Deprecated! Do not use for new designs! </dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a72a1e09e67f5ce1b522667e8e171d578" name="a72a1e09e67f5ce1b522667e8e171d578"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a72a1e09e67f5ce1b522667e8e171d578">&#9670;&#160;</a></span>neorv32_cpu_load_reservate_word</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_cpu_load_reservate_word</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="neorv32__cpu__amo_8h.html#ad4437bbc61a4e40d7d01dfe9459f6639">neorv32_cpu_amolr</a>(addr, wdata)</div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_ad4437bbc61a4e40d7d01dfe9459f6639"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#ad4437bbc61a4e40d7d01dfe9459f6639">neorv32_cpu_amolr</a></div><div class="ttdeci">uint32_t neorv32_cpu_amolr(uint32_t addr)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.h:31</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="ac8325c90310ab06d305671b1aa169965" name="ac8325c90310ab06d305671b1aa169965"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac8325c90310ab06d305671b1aa169965">&#9670;&#160;</a></span>neorv32_cpu_store_conditional_word</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_cpu_store_conditional_word</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>addr</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>wdata</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="neorv32__cpu__amo_8h.html#a5e73eaa273c41a06972e862976fda53c">neorv32_cpu_amosc</a>(addr, wdata)</div> +<div class="ttc" id="aneorv32__cpu__amo_8h_html_a5e73eaa273c41a06972e862976fda53c"><div class="ttname"><a href="neorv32__cpu__amo_8h.html#a5e73eaa273c41a06972e862976fda53c">neorv32_cpu_amosc</a></div><div class="ttdeci">uint32_t neorv32_cpu_amosc(uint32_t addr, uint32_t wdata)</div><div class="ttdef"><b>Definition</b> neorv32_cpu_amo.h:58</div></div> +</div><!-- fragment --> +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__legacy_8h_source.html b/sw/neorv32__legacy_8h_source.html new file mode 100644 index 000000000..e47f5309a --- /dev/null +++ b/sw/neorv32__legacy_8h_source.html @@ -0,0 +1,126 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_legacy.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_legacy_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_legacy_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span><span class="preprocessor">#define INPUT_LO INPUT[0]</span></div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span><span class="preprocessor">#define INPUT_HI INPUT[1]</span></div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span><span class="preprocessor">#define OUTPUT_LO OUTPUT[0]</span></div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span><span class="preprocessor">#define OUTPUT_HI OUTPUT[1]</span></div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span><span class="preprocessor">#define neorv32_cpu_load_reservate_word(addr, wdata) neorv32_cpu_amolr(addr, wdata)</span></div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span><span class="preprocessor">#define neorv32_cpu_store_conditional_word(addr, wdata) neorv32_cpu_amosc(addr, wdata)</span></div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_legacy_h</span></div> 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_mtime.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Machine System Timer (MTIME) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ab2b49a0594c66692aedf76ff9935581c" id="r_ab2b49a0594c66692aedf76ff9935581c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab2b49a0594c66692aedf76ff9935581c">neorv32_mtime_available</a> (void)</td></tr> +<tr class="separator:ab2b49a0594c66692aedf76ff9935581c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1c30809d6e887f022a7794f720243015" id="r_a1c30809d6e887f022a7794f720243015"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1c30809d6e887f022a7794f720243015">neorv32_mtime_set_time</a> (uint64_t time)</td></tr> +<tr class="separator:a1c30809d6e887f022a7794f720243015"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adedbbdeb71c06d2d60d3af73451de01e" id="r_adedbbdeb71c06d2d60d3af73451de01e"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adedbbdeb71c06d2d60d3af73451de01e">neorv32_mtime_get_time</a> (void)</td></tr> +<tr class="separator:adedbbdeb71c06d2d60d3af73451de01e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a81ff371c1aa10901264873316ee84a49" id="r_a81ff371c1aa10901264873316ee84a49"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a81ff371c1aa10901264873316ee84a49">neorv32_mtime_set_timecmp</a> (uint64_t timecmp)</td></tr> +<tr class="separator:a81ff371c1aa10901264873316ee84a49"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acb3cc18ff8421ebd6ef471e089c23491" id="r_acb3cc18ff8421ebd6ef471e089c23491"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acb3cc18ff8421ebd6ef471e089c23491">neorv32_mtime_get_timecmp</a> (void)</td></tr> +<tr class="separator:acb3cc18ff8421ebd6ef471e089c23491"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a022c3292c6e75095bb3ffd4c42fd4bfa" id="r_a022c3292c6e75095bb3ffd4c42fd4bfa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a022c3292c6e75095bb3ffd4c42fd4bfa">neorv32_mtime_set_unixtime</a> (uint64_t unixtime)</td></tr> +<tr class="separator:a022c3292c6e75095bb3ffd4c42fd4bfa"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a50d08fcc3d91fc2d88b9a6a80c656f1a" id="r_a50d08fcc3d91fc2d88b9a6a80c656f1a"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a50d08fcc3d91fc2d88b9a6a80c656f1a">neorv32_mtime_get_unixtime</a> (void)</td></tr> +<tr class="separator:a50d08fcc3d91fc2d88b9a6a80c656f1a"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Machine System Timer (MTIME) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the MTIME unit was synthesized (IO_MTIME_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="ab2b49a0594c66692aedf76ff9935581c" name="ab2b49a0594c66692aedf76ff9935581c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab2b49a0594c66692aedf76ff9935581c">&#9670;&#160;</a></span>neorv32_mtime_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_mtime_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if MTIME unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if MTIME was not synthesized, 1 if MTIME is available. </dd></dl> + +</div> +</div> +<a id="adedbbdeb71c06d2d60d3af73451de01e" name="adedbbdeb71c06d2d60d3af73451de01e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adedbbdeb71c06d2d60d3af73451de01e">&#9670;&#160;</a></span>neorv32_mtime_get_time()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_mtime_get_time </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get current system time.</p> +<dl class="section note"><dt>Note</dt><dd>The MTIME timer increments with the primary processor clock.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Current system time (uint64_t) </dd></dl> + +</div> +</div> +<a id="acb3cc18ff8421ebd6ef471e089c23491" name="acb3cc18ff8421ebd6ef471e089c23491"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acb3cc18ff8421ebd6ef471e089c23491">&#9670;&#160;</a></span>neorv32_mtime_get_timecmp()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_mtime_get_timecmp </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get compare time register (MTIMECMP).</p> +<dl class="section return"><dt>Returns</dt><dd>Current MTIMECMP value. </dd></dl> + +</div> +</div> +<a id="a50d08fcc3d91fc2d88b9a6a80c656f1a" name="a50d08fcc3d91fc2d88b9a6a80c656f1a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a50d08fcc3d91fc2d88b9a6a80c656f1a">&#9670;&#160;</a></span>neorv32_mtime_get_unixtime()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_mtime_get_unixtime </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get Unix time from TIME.</p> +<dl class="section return"><dt>Returns</dt><dd>Unix time since 00:00:00 UTC, January 1st, 1970 in seconds. </dd></dl> + +</div> +</div> +<a id="a1c30809d6e887f022a7794f720243015" name="a1c30809d6e887f022a7794f720243015"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1c30809d6e887f022a7794f720243015">&#9670;&#160;</a></span>neorv32_mtime_set_time()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_mtime_set_time </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>time</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set current system time.</p> +<dl class="section note"><dt>Note</dt><dd>The MTIME timer increments with the primary processor clock.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">time</td><td>New system time (uint64_t) </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a81ff371c1aa10901264873316ee84a49" name="a81ff371c1aa10901264873316ee84a49"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a81ff371c1aa10901264873316ee84a49">&#9670;&#160;</a></span>neorv32_mtime_set_timecmp()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_mtime_set_timecmp </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>timecmp</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set compare time register (MTIMECMP) for generating interrupts.</p> +<dl class="section note"><dt>Note</dt><dd>The interrupt is triggered when MTIME &gt;= MTIMECMP. </dd> +<dd> +Global interrupts and the timer interrupt source have to be enabled.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">timecmp</td><td>System time for interrupt (uint64_t) </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a022c3292c6e75095bb3ffd4c42fd4bfa" name="a022c3292c6e75095bb3ffd4c42fd4bfa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a022c3292c6e75095bb3ffd4c42fd4bfa">&#9670;&#160;</a></span>neorv32_mtime_set_unixtime()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_mtime_set_unixtime </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>unixtime</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set TIME to Unix time.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">unixtime</td><td>Unix time since 00:00:00 UTC, January 1st, 1970 in seconds. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__mtime_8h.html b/sw/neorv32__mtime_8h.html new file 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colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">IO Device: Machine System Timer (MTIME)</div></td></tr> +<tr class="memitem:a68935be182e0081039326a9f344a36b3" id="r_a68935be182e0081039326a9f344a36b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a68935be182e0081039326a9f344a36b3">NEORV32_MTIME</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__mtime__t.html">neorv32_mtime_t</a>*) (<a class="el" href="neorv32_8h.html#ab98f762df259a2bbc28d19d2acfe9e23">NEORV32_MTIME_BASE</a>))</td></tr> +<tr class="separator:a68935be182e0081039326a9f344a36b3"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:ab2b49a0594c66692aedf76ff9935581c" id="r_ab2b49a0594c66692aedf76ff9935581c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab2b49a0594c66692aedf76ff9935581c">neorv32_mtime_available</a> (void)</td></tr> +<tr class="separator:ab2b49a0594c66692aedf76ff9935581c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1c30809d6e887f022a7794f720243015" id="r_a1c30809d6e887f022a7794f720243015"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1c30809d6e887f022a7794f720243015">neorv32_mtime_set_time</a> (uint64_t time)</td></tr> +<tr class="separator:a1c30809d6e887f022a7794f720243015"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adedbbdeb71c06d2d60d3af73451de01e" id="r_adedbbdeb71c06d2d60d3af73451de01e"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adedbbdeb71c06d2d60d3af73451de01e">neorv32_mtime_get_time</a> (void)</td></tr> +<tr class="separator:adedbbdeb71c06d2d60d3af73451de01e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a81ff371c1aa10901264873316ee84a49" id="r_a81ff371c1aa10901264873316ee84a49"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a81ff371c1aa10901264873316ee84a49">neorv32_mtime_set_timecmp</a> (uint64_t timecmp)</td></tr> +<tr class="separator:a81ff371c1aa10901264873316ee84a49"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acb3cc18ff8421ebd6ef471e089c23491" id="r_acb3cc18ff8421ebd6ef471e089c23491"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acb3cc18ff8421ebd6ef471e089c23491">neorv32_mtime_get_timecmp</a> (void)</td></tr> +<tr class="separator:acb3cc18ff8421ebd6ef471e089c23491"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a022c3292c6e75095bb3ffd4c42fd4bfa" id="r_a022c3292c6e75095bb3ffd4c42fd4bfa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a022c3292c6e75095bb3ffd4c42fd4bfa">neorv32_mtime_set_unixtime</a> (uint64_t unixtime)</td></tr> +<tr class="separator:a022c3292c6e75095bb3ffd4c42fd4bfa"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a50d08fcc3d91fc2d88b9a6a80c656f1a" id="r_a50d08fcc3d91fc2d88b9a6a80c656f1a"><td class="memItemLeft" align="right" valign="top">uint64_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a50d08fcc3d91fc2d88b9a6a80c656f1a">neorv32_mtime_get_unixtime</a> (void)</td></tr> +<tr class="separator:a50d08fcc3d91fc2d88b9a6a80c656f1a"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Machine System Timer (MTIME) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the MTIME unit was synthesized (IO_MTIME_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a68935be182e0081039326a9f344a36b3" name="a68935be182e0081039326a9f344a36b3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a68935be182e0081039326a9f344a36b3">&#9670;&#160;</a></span>NEORV32_MTIME</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_MTIME&#160;&#160;&#160;((<a class="el" href="structneorv32__mtime__t.html">neorv32_mtime_t</a>*) (<a class="el" href="neorv32_8h.html#ab98f762df259a2bbc28d19d2acfe9e23">NEORV32_MTIME_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>MTIME module hardware access (<a class="el" href="structneorv32__mtime__t.html">neorv32_mtime_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="ab2b49a0594c66692aedf76ff9935581c" name="ab2b49a0594c66692aedf76ff9935581c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab2b49a0594c66692aedf76ff9935581c">&#9670;&#160;</a></span>neorv32_mtime_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_mtime_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if MTIME unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if MTIME was not synthesized, 1 if MTIME is available. </dd></dl> + +</div> +</div> +<a id="adedbbdeb71c06d2d60d3af73451de01e" name="adedbbdeb71c06d2d60d3af73451de01e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adedbbdeb71c06d2d60d3af73451de01e">&#9670;&#160;</a></span>neorv32_mtime_get_time()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_mtime_get_time </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get current system time.</p> +<dl class="section note"><dt>Note</dt><dd>The MTIME timer increments with the primary processor clock.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Current system time (uint64_t) </dd></dl> + +</div> +</div> +<a id="acb3cc18ff8421ebd6ef471e089c23491" name="acb3cc18ff8421ebd6ef471e089c23491"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acb3cc18ff8421ebd6ef471e089c23491">&#9670;&#160;</a></span>neorv32_mtime_get_timecmp()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_mtime_get_timecmp </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get compare time register (MTIMECMP).</p> +<dl class="section return"><dt>Returns</dt><dd>Current MTIMECMP value. </dd></dl> + +</div> +</div> +<a id="a50d08fcc3d91fc2d88b9a6a80c656f1a" name="a50d08fcc3d91fc2d88b9a6a80c656f1a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a50d08fcc3d91fc2d88b9a6a80c656f1a">&#9670;&#160;</a></span>neorv32_mtime_get_unixtime()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t neorv32_mtime_get_unixtime </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get Unix time from TIME.</p> +<dl class="section return"><dt>Returns</dt><dd>Unix time since 00:00:00 UTC, January 1st, 1970 in seconds. </dd></dl> + +</div> +</div> +<a id="a1c30809d6e887f022a7794f720243015" name="a1c30809d6e887f022a7794f720243015"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1c30809d6e887f022a7794f720243015">&#9670;&#160;</a></span>neorv32_mtime_set_time()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_mtime_set_time </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>time</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set current system time.</p> +<dl class="section note"><dt>Note</dt><dd>The MTIME timer increments with the primary processor clock.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">time</td><td>New system time (uint64_t) </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a81ff371c1aa10901264873316ee84a49" name="a81ff371c1aa10901264873316ee84a49"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a81ff371c1aa10901264873316ee84a49">&#9670;&#160;</a></span>neorv32_mtime_set_timecmp()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_mtime_set_timecmp </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>timecmp</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set compare time register (MTIMECMP) for generating interrupts.</p> +<dl class="section note"><dt>Note</dt><dd>The interrupt is triggered when MTIME &gt;= MTIMECMP. </dd> +<dd> +Global interrupts and the timer interrupt source have to be enabled.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">timecmp</td><td>System time for interrupt (uint64_t) </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a022c3292c6e75095bb3ffd4c42fd4bfa" name="a022c3292c6e75095bb3ffd4c42fd4bfa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a022c3292c6e75095bb3ffd4c42fd4bfa">&#9670;&#160;</a></span>neorv32_mtime_set_unixtime()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_mtime_set_unixtime </td> + <td>(</td> + <td class="paramtype">uint64_t</td> <td class="paramname"><span class="paramname"><em>unixtime</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set TIME to Unix time.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">unixtime</td><td>Unix time since 00:00:00 UTC, January 1st, 1970 in seconds. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__mtime_8h_source.html b/sw/neorv32__mtime_8h_source.html new file mode 100644 index 000000000..a8e155002 --- /dev/null +++ b/sw/neorv32__mtime_8h_source.html @@ -0,0 +1,149 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 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name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_mtime_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_mtime_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__mtime__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__mtime__t.html#acccaa3dd87a57ebd5f7ae504771e904e"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__mtime__t.html#acccaa3dd87a57ebd5f7ae504771e904e">TIME_LO</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__mtime__t.html#a1ffe0be2c45f5d7aa2686abf40cd1693"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__mtime__t.html#a1ffe0be2c45f5d7aa2686abf40cd1693">TIME_HI</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"><a class="line" href="structneorv32__mtime__t.html#ab5fa56ca5c2f9d547f58d169d6da96e5"> 32</a></span> uint32_t <a class="code hl_variable" href="structneorv32__mtime__t.html#ab5fa56ca5c2f9d547f58d169d6da96e5">TIMECMP_LO</a>; </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"><a class="line" href="structneorv32__mtime__t.html#af05df268c8f699401cf752e4249ba422"> 33</a></span> uint32_t <a class="code hl_variable" href="structneorv32__mtime__t.html#af05df268c8f699401cf752e4249ba422">TIMECMP_HI</a>; </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span>} <a class="code hl_struct" href="structneorv32__mtime__t.html">neorv32_mtime_t</a>;</div> +</div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__mtime_8h.html#a68935be182e0081039326a9f344a36b3"> 37</a></span><span class="preprocessor">#define NEORV32_MTIME ((neorv32_mtime_t*) (NEORV32_MTIME_BASE))</span></div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__mtime_8h.html#ab2b49a0594c66692aedf76ff9935581c">neorv32_mtime_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__mtime_8h.html#a1c30809d6e887f022a7794f720243015">neorv32_mtime_set_time</a>(uint64_t time);</div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span>uint64_t <a class="code hl_function" href="neorv32__mtime_8h.html#adedbbdeb71c06d2d60d3af73451de01e">neorv32_mtime_get_time</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__mtime_8h.html#a81ff371c1aa10901264873316ee84a49">neorv32_mtime_set_timecmp</a>(uint64_t timecmp);</div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span>uint64_t <a class="code hl_function" href="neorv32__mtime_8h.html#acb3cc18ff8421ebd6ef471e089c23491">neorv32_mtime_get_timecmp</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__mtime_8h.html#a022c3292c6e75095bb3ffd4c42fd4bfa">neorv32_mtime_set_unixtime</a>(uint64_t unixtime);</div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span>uint64_t <a class="code hl_function" href="neorv32__mtime_8h.html#a50d08fcc3d91fc2d88b9a6a80c656f1a">neorv32_mtime_get_unixtime</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_mtime_h</span></div> +<div class="ttc" id="aneorv32__mtime_8h_html_a022c3292c6e75095bb3ffd4c42fd4bfa"><div class="ttname"><a href="neorv32__mtime_8h.html#a022c3292c6e75095bb3ffd4c42fd4bfa">neorv32_mtime_set_unixtime</a></div><div class="ttdeci">void neorv32_mtime_set_unixtime(uint64_t unixtime)</div><div class="ttdef"><b>Definition</b> neorv32_mtime.c:127</div></div> +<div class="ttc" id="aneorv32__mtime_8h_html_a1c30809d6e887f022a7794f720243015"><div class="ttname"><a href="neorv32__mtime_8h.html#a1c30809d6e887f022a7794f720243015">neorv32_mtime_set_time</a></div><div class="ttdeci">void neorv32_mtime_set_time(uint64_t time)</div><div class="ttdef"><b>Definition</b> neorv32_mtime.c:44</div></div> +<div class="ttc" id="aneorv32__mtime_8h_html_a50d08fcc3d91fc2d88b9a6a80c656f1a"><div class="ttname"><a href="neorv32__mtime_8h.html#a50d08fcc3d91fc2d88b9a6a80c656f1a">neorv32_mtime_get_unixtime</a></div><div class="ttdeci">uint64_t neorv32_mtime_get_unixtime(void)</div><div class="ttdef"><b>Definition</b> neorv32_mtime.c:138</div></div> +<div class="ttc" id="aneorv32__mtime_8h_html_a81ff371c1aa10901264873316ee84a49"><div class="ttname"><a href="neorv32__mtime_8h.html#a81ff371c1aa10901264873316ee84a49">neorv32_mtime_set_timecmp</a></div><div class="ttdeci">void neorv32_mtime_set_timecmp(uint64_t timecmp)</div><div class="ttdef"><b>Definition</b> neorv32_mtime.c:93</div></div> +<div class="ttc" id="aneorv32__mtime_8h_html_ab2b49a0594c66692aedf76ff9935581c"><div class="ttname"><a href="neorv32__mtime_8h.html#ab2b49a0594c66692aedf76ff9935581c">neorv32_mtime_available</a></div><div class="ttdeci">int neorv32_mtime_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_mtime.c:26</div></div> +<div class="ttc" id="aneorv32__mtime_8h_html_acb3cc18ff8421ebd6ef471e089c23491"><div class="ttname"><a href="neorv32__mtime_8h.html#acb3cc18ff8421ebd6ef471e089c23491">neorv32_mtime_get_timecmp</a></div><div class="ttdeci">uint64_t neorv32_mtime_get_timecmp(void)</div><div class="ttdef"><b>Definition</b> neorv32_mtime.c:111</div></div> +<div class="ttc" id="aneorv32__mtime_8h_html_adedbbdeb71c06d2d60d3af73451de01e"><div class="ttname"><a href="neorv32__mtime_8h.html#adedbbdeb71c06d2d60d3af73451de01e">neorv32_mtime_get_time</a></div><div class="ttdeci">uint64_t neorv32_mtime_get_time(void)</div><div class="ttdef"><b>Definition</b> neorv32_mtime.c:64</div></div> +<div class="ttc" id="astructneorv32__mtime__t_html"><div class="ttname"><a href="structneorv32__mtime__t.html">neorv32_mtime_t</a></div><div class="ttdef"><b>Definition</b> neorv32_mtime.h:29</div></div> +<div class="ttc" id="astructneorv32__mtime__t_html_a1ffe0be2c45f5d7aa2686abf40cd1693"><div class="ttname"><a href="structneorv32__mtime__t.html#a1ffe0be2c45f5d7aa2686abf40cd1693">neorv32_mtime_t::TIME_HI</a></div><div class="ttdeci">uint32_t TIME_HI</div><div class="ttdef"><b>Definition</b> neorv32_mtime.h:31</div></div> +<div class="ttc" id="astructneorv32__mtime__t_html_ab5fa56ca5c2f9d547f58d169d6da96e5"><div class="ttname"><a href="structneorv32__mtime__t.html#ab5fa56ca5c2f9d547f58d169d6da96e5">neorv32_mtime_t::TIMECMP_LO</a></div><div class="ttdeci">uint32_t TIMECMP_LO</div><div class="ttdef"><b>Definition</b> neorv32_mtime.h:32</div></div> +<div class="ttc" id="astructneorv32__mtime__t_html_acccaa3dd87a57ebd5f7ae504771e904e"><div class="ttname"><a href="structneorv32__mtime__t.html#acccaa3dd87a57ebd5f7ae504771e904e">neorv32_mtime_t::TIME_LO</a></div><div class="ttdeci">uint32_t TIME_LO</div><div class="ttdef"><b>Definition</b> neorv32_mtime.h:30</div></div> +<div class="ttc" id="astructneorv32__mtime__t_html_af05df268c8f699401cf752e4249ba422"><div class="ttname"><a href="structneorv32__mtime__t.html#af05df268c8f699401cf752e4249ba422">neorv32_mtime_t::TIMECMP_HI</a></div><div class="ttdeci">uint32_t TIMECMP_HI</div><div class="ttdef"><b>Definition</b> neorv32_mtime.h:33</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__neoled_8c.html b/sw/neorv32__neoled_8c.html new file mode 100644 index 000000000..e7409baed --- /dev/null +++ b/sw/neorv32__neoled_8c.html @@ -0,0 +1,371 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 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id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_neoled.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Smart LED Interface (NEOLED) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a57398d92fb4fc735b33e89271726e1d6" id="r_a57398d92fb4fc735b33e89271726e1d6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a57398d92fb4fc735b33e89271726e1d6">neorv32_neoled_available</a> (void)</td></tr> +<tr class="separator:a57398d92fb4fc735b33e89271726e1d6"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac6e94602453779a2791bd0734465f5a3" id="r_ac6e94602453779a2791bd0734465f5a3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac6e94602453779a2791bd0734465f5a3">neorv32_neoled_setup</a> (uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one, int irq_mode)</td></tr> +<tr class="separator:ac6e94602453779a2791bd0734465f5a3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adade69c7368c28180b9992d5f0ab6031" id="r_adade69c7368c28180b9992d5f0ab6031"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adade69c7368c28180b9992d5f0ab6031">neorv32_neoled_setup_ws2812</a> (int irq_mode)</td></tr> +<tr class="separator:adade69c7368c28180b9992d5f0ab6031"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a484fcc6797b6d9cef86192e9593ec33d" id="r_a484fcc6797b6d9cef86192e9593ec33d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a484fcc6797b6d9cef86192e9593ec33d">neorv32_neoled_set_mode</a> (uint32_t mode)</td></tr> +<tr class="separator:a484fcc6797b6d9cef86192e9593ec33d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5aa9eb4dd3655fa08e1b61eb0f36589c" id="r_a5aa9eb4dd3655fa08e1b61eb0f36589c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5aa9eb4dd3655fa08e1b61eb0f36589c">neorv32_neoled_strobe_blocking</a> (void)</td></tr> +<tr class="separator:a5aa9eb4dd3655fa08e1b61eb0f36589c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abf7882b949373df0774fc9cc20c2bd2e" id="r_abf7882b949373df0774fc9cc20c2bd2e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abf7882b949373df0774fc9cc20c2bd2e">neorv32_neoled_strobe_nonblocking</a> (void)</td></tr> +<tr class="separator:abf7882b949373df0774fc9cc20c2bd2e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8181d5c1d15b7b5eecdc018341ac14fa" id="r_a8181d5c1d15b7b5eecdc018341ac14fa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8181d5c1d15b7b5eecdc018341ac14fa">neorv32_neoled_enable</a> (void)</td></tr> +<tr class="separator:a8181d5c1d15b7b5eecdc018341ac14fa"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8daaa97a85e0eb94d4a38eb2119ea183" id="r_a8daaa97a85e0eb94d4a38eb2119ea183"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8daaa97a85e0eb94d4a38eb2119ea183">neorv32_neoled_disable</a> (void)</td></tr> +<tr class="separator:a8daaa97a85e0eb94d4a38eb2119ea183"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a3ee5b3602da3ae982628e2802587e451" id="r_a3ee5b3602da3ae982628e2802587e451"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3ee5b3602da3ae982628e2802587e451">neorv32_neoled_write_blocking</a> (uint32_t data)</td></tr> +<tr class="separator:a3ee5b3602da3ae982628e2802587e451"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a81c2c49198531fb6551eb288e29c084e" id="r_a81c2c49198531fb6551eb288e29c084e"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a81c2c49198531fb6551eb288e29c084e">neorv32_neoled_get_buffer_size</a> (void)</td></tr> +<tr class="separator:a81c2c49198531fb6551eb288e29c084e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Smart LED Interface (NEOLED) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the NEOLED unit was synthesized (IO_NEOLED_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a57398d92fb4fc735b33e89271726e1d6" name="a57398d92fb4fc735b33e89271726e1d6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a57398d92fb4fc735b33e89271726e1d6">&#9670;&#160;</a></span>neorv32_neoled_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_neoled_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if NEOLED unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if NEOLED was not synthesized, 1 if NEOLED is available. </dd></dl> + +</div> +</div> +<a id="a8daaa97a85e0eb94d4a38eb2119ea183" name="a8daaa97a85e0eb94d4a38eb2119ea183"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8daaa97a85e0eb94d4a38eb2119ea183">&#9670;&#160;</a></span>neorv32_neoled_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable NEOLED controller. </p> + +</div> +</div> +<a id="a8181d5c1d15b7b5eecdc018341ac14fa" name="a8181d5c1d15b7b5eecdc018341ac14fa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8181d5c1d15b7b5eecdc018341ac14fa">&#9670;&#160;</a></span>neorv32_neoled_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable NEOLED controller. </p> + +</div> +</div> +<a id="a81c2c49198531fb6551eb288e29c084e" name="a81c2c49198531fb6551eb288e29c084e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a81c2c49198531fb6551eb288e29c084e">&#9670;&#160;</a></span>neorv32_neoled_get_buffer_size()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_neoled_get_buffer_size </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get NEOLED hardware buffer size.</p> +<dl class="section return"><dt>Returns</dt><dd>Number of entries in NEOLED TX buffer. </dd></dl> + +</div> +</div> +<a id="a484fcc6797b6d9cef86192e9593ec33d" name="a484fcc6797b6d9cef86192e9593ec33d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a484fcc6797b6d9cef86192e9593ec33d">&#9670;&#160;</a></span>neorv32_neoled_set_mode()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_set_mode </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>mode</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set NEOLED mode (24-bit RGB / 32-bit RGBW).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>0 = 24-bit mode (RGB), 1 = 32-bit mode (RGBW) </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac6e94602453779a2791bd0734465f5a3" name="ac6e94602453779a2791bd0734465f5a3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac6e94602453779a2791bd0734465f5a3">&#9670;&#160;</a></span>neorv32_neoled_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>t_total</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>t_high_zero</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>t_high_one</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>irq_mode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable and configure NEOLED controller. The NEOLED control register bits are listed in <a class="el" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412">NEORV32_NEOLED_CTRL_enum</a>. This function performs a "raw" configuration (just configuring the according control register bit).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Clock prescaler select (0..7). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">t_total</td><td>Number of pre-scaled clock ticks for total bit period (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">t_high_zero</td><td>Number of pre-scaled clock ticks to generate high-time for sending a '0' (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">t_high_one</td><td>Number of pre-scaled clock ticks to generate high-time for sending a '1' (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mode</td><td>Interrupt condition (1=IRQ if FIFO is empty, 1=IRQ if FIFO is less than half-full). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="adade69c7368c28180b9992d5f0ab6031" name="adade69c7368c28180b9992d5f0ab6031"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adade69c7368c28180b9992d5f0ab6031">&#9670;&#160;</a></span>neorv32_neoled_setup_ws2812()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_setup_ws2812 </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>irq_mode</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure NEOLED controller for using WS2812 LEDs (NeoPixel-compatible). This function computes all the required timings and finally calls <a class="el" href="#ac6e94602453779a2791bd0734465f5a3">neorv32_neoled_setup</a>.</p> +<dl class="section note"><dt>Note</dt><dd>WS2812 timing: T_period = 1.2us, T_high_zero = 0.4us, T_high_one = 0.8us. Change the constants if required. </dd> +<dd> +This function uses the SYSINFO_CLK value (from the SYSINFO HW module) to do the timing computations.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mode</td><td>Interrupt condition (1=IRQ if FIFO is empty, 1=IRQ if FIFO is less than half-full). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a5aa9eb4dd3655fa08e1b61eb0f36589c" name="a5aa9eb4dd3655fa08e1b61eb0f36589c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5aa9eb4dd3655fa08e1b61eb0f36589c">&#9670;&#160;</a></span>neorv32_neoled_strobe_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_strobe_blocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send strobe command ("RESET") - blocking. </p> + +</div> +</div> +<a id="abf7882b949373df0774fc9cc20c2bd2e" name="abf7882b949373df0774fc9cc20c2bd2e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abf7882b949373df0774fc9cc20c2bd2e">&#9670;&#160;</a></span>neorv32_neoled_strobe_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_strobe_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send strobe command ("RESET") - non-blocking. </p> + +</div> +</div> +<a id="a3ee5b3602da3ae982628e2802587e451" name="a3ee5b3602da3ae982628e2802587e451"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3ee5b3602da3ae982628e2802587e451">&#9670;&#160;</a></span>neorv32_neoled_write_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_write_blocking </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send single RGB(W) data word to NEOLED module (blocking).</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking as it polls the NEOLED FIFO full flag.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>LSB-aligned 24-bit RGB or 32-bit RGBW data </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" 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href="structneorv32__neoled__t.html">neorv32_neoled_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ad2a318bd59be12de34797ced0f7743c6" id="r_ad2a318bd59be12de34797ced0f7743c6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad2a318bd59be12de34797ced0f7743c6">neorv32_neoled_write_nonblocking</a> (uint32_t data)</td></tr> +<tr class="separator:ad2a318bd59be12de34797ced0f7743c6"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:a57398d92fb4fc735b33e89271726e1d6" id="r_a57398d92fb4fc735b33e89271726e1d6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a57398d92fb4fc735b33e89271726e1d6">neorv32_neoled_available</a> (void)</td></tr> +<tr class="separator:a57398d92fb4fc735b33e89271726e1d6"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac6e94602453779a2791bd0734465f5a3" id="r_ac6e94602453779a2791bd0734465f5a3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac6e94602453779a2791bd0734465f5a3">neorv32_neoled_setup</a> (uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one, int irq_mode)</td></tr> +<tr class="separator:ac6e94602453779a2791bd0734465f5a3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adade69c7368c28180b9992d5f0ab6031" id="r_adade69c7368c28180b9992d5f0ab6031"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adade69c7368c28180b9992d5f0ab6031">neorv32_neoled_setup_ws2812</a> (int irq_mode)</td></tr> +<tr class="separator:adade69c7368c28180b9992d5f0ab6031"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a484fcc6797b6d9cef86192e9593ec33d" id="r_a484fcc6797b6d9cef86192e9593ec33d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a484fcc6797b6d9cef86192e9593ec33d">neorv32_neoled_set_mode</a> (uint32_t mode)</td></tr> +<tr class="separator:a484fcc6797b6d9cef86192e9593ec33d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5aa9eb4dd3655fa08e1b61eb0f36589c" id="r_a5aa9eb4dd3655fa08e1b61eb0f36589c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5aa9eb4dd3655fa08e1b61eb0f36589c">neorv32_neoled_strobe_blocking</a> (void)</td></tr> +<tr class="separator:a5aa9eb4dd3655fa08e1b61eb0f36589c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abf7882b949373df0774fc9cc20c2bd2e" id="r_abf7882b949373df0774fc9cc20c2bd2e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abf7882b949373df0774fc9cc20c2bd2e">neorv32_neoled_strobe_nonblocking</a> (void)</td></tr> +<tr class="separator:abf7882b949373df0774fc9cc20c2bd2e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8181d5c1d15b7b5eecdc018341ac14fa" id="r_a8181d5c1d15b7b5eecdc018341ac14fa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8181d5c1d15b7b5eecdc018341ac14fa">neorv32_neoled_enable</a> (void)</td></tr> +<tr class="separator:a8181d5c1d15b7b5eecdc018341ac14fa"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8daaa97a85e0eb94d4a38eb2119ea183" id="r_a8daaa97a85e0eb94d4a38eb2119ea183"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8daaa97a85e0eb94d4a38eb2119ea183">neorv32_neoled_disable</a> (void)</td></tr> +<tr class="separator:a8daaa97a85e0eb94d4a38eb2119ea183"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a3ee5b3602da3ae982628e2802587e451" id="r_a3ee5b3602da3ae982628e2802587e451"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3ee5b3602da3ae982628e2802587e451">neorv32_neoled_write_blocking</a> (uint32_t data)</td></tr> +<tr class="separator:a3ee5b3602da3ae982628e2802587e451"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a81c2c49198531fb6551eb288e29c084e" id="r_a81c2c49198531fb6551eb288e29c084e"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a81c2c49198531fb6551eb288e29c084e">neorv32_neoled_get_buffer_size</a> (void)</td></tr> +<tr class="separator:a81c2c49198531fb6551eb288e29c084e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Smart LED Hardware Interface (NEOLED)</h2></td></tr> +<tr class="memitem:a3ccc1097bc70f92235d693b612fa994a" id="r_a3ccc1097bc70f92235d693b612fa994a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3ccc1097bc70f92235d693b612fa994a">NEORV32_NEOLED</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__neoled__t.html">neorv32_neoled_t</a>*) (<a class="el" href="neorv32_8h.html#a559fdce92e8af5efc426c8fc48d14f99">NEORV32_NEOLED_BASE</a>))</td></tr> +<tr class="separator:a3ccc1097bc70f92235d693b612fa994a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ab99c7fed050816eae0fa0315562e0412" id="r_ab99c7fed050816eae0fa0315562e0412"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab99c7fed050816eae0fa0315562e0412">NEORV32_NEOLED_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ab99c7fed050816eae0fa0315562e0412af97ab77b33a250d87025c3dd3a21fea7">NEOLED_CTRL_EN</a> = 0 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412abf6779cbeae87ab55efc9573932fc865">NEOLED_CTRL_MODE</a> = 1 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a436ad310b025bd3000af37986c193de5">NEOLED_CTRL_STROBE</a> = 2 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a142ed3fd65e01f853666a1169f920ad0">NEOLED_CTRL_PRSC0</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#ab99c7fed050816eae0fa0315562e0412a0f4178d81ec6fe9a8b0e30230d318a91">NEOLED_CTRL_PRSC1</a> = 4 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a3d8d54c05080fddb16df4176527bafa8">NEOLED_CTRL_PRSC2</a> = 5 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a3bb5d0d1f78cebccbc8620a0194f43b8">NEOLED_CTRL_BUFS_0</a> = 6 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412aed0a878e73ad501bed3bbe6905974368">NEOLED_CTRL_BUFS_1</a> = 7 +, <br /> +&#160;&#160;<a class="el" href="#ab99c7fed050816eae0fa0315562e0412ae7b9d45c4ef69ca15fa13aa107e68156">NEOLED_CTRL_BUFS_2</a> = 8 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412ac1922a5311e91a74710eddbf86ccc1c1">NEOLED_CTRL_BUFS_3</a> = 9 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a44d8f064decabc690ed1f092be2b049b">NEOLED_CTRL_T_TOT_0</a> = 10 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412addf4d6d1fd09f145d8aa497c4a7479c2">NEOLED_CTRL_T_TOT_1</a> = 11 +, <br /> +&#160;&#160;<a class="el" href="#ab99c7fed050816eae0fa0315562e0412a42d09d42d39fc0eb2697853c99f4d5b0">NEOLED_CTRL_T_TOT_2</a> = 12 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412acbcd3c046b528e1900e86428da231df2">NEOLED_CTRL_T_TOT_3</a> = 13 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a3f1a0ad71d9fd892829ec0246be343b3">NEOLED_CTRL_T_TOT_4</a> = 14 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a7285e332ec7c2b3aeb34290e3e60ded7">NEOLED_CTRL_T_ZERO_H_0</a> = 15 +, <br /> +&#160;&#160;<a class="el" href="#ab99c7fed050816eae0fa0315562e0412a1ef56b35c966786c42f2a2f800e30eae">NEOLED_CTRL_T_ZERO_H_1</a> = 16 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a9d9411382d943c1659b6b761c462319b">NEOLED_CTRL_T_ZERO_H_2</a> = 17 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412abf2ea111a4ff34b6cb4dd987c5692f5c">NEOLED_CTRL_T_ZERO_H_3</a> = 18 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a0d5d01b8d30119bb86c1d079f7d5a9ad">NEOLED_CTRL_T_ZERO_H_4</a> = 19 +, <br /> +&#160;&#160;<a class="el" href="#ab99c7fed050816eae0fa0315562e0412a770df505d47353f6c9289059c416d9c8">NEOLED_CTRL_T_ONE_H_0</a> = 20 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412aea15666ad4bb9eb1eba5dc9ed96114a6">NEOLED_CTRL_T_ONE_H_1</a> = 21 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a4d362af8c630823b5104401a9c7d734e">NEOLED_CTRL_T_ONE_H_2</a> = 22 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a369f36e73783c2923d07ca333081a4a6">NEOLED_CTRL_T_ONE_H_3</a> = 23 +, <br /> +&#160;&#160;<a class="el" href="#ab99c7fed050816eae0fa0315562e0412a0c15850d0ab005b075f1a317646e18b1">NEOLED_CTRL_T_ONE_H_4</a> = 24 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a37421074b86a260b276534b7c4949339">NEOLED_CTRL_IRQ_CONF</a> = 27 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a23937f0a728da197590e1d383507cb23">NEOLED_CTRL_TX_EMPTY</a> = 28 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a16c09df2784cfb6fafffaeaf245f1b73">NEOLED_CTRL_TX_HALF</a> = 29 +, <br /> +&#160;&#160;<a class="el" href="#ab99c7fed050816eae0fa0315562e0412acfac5269688b2a03794dc17b11f1b983">NEOLED_CTRL_TX_FULL</a> = 30 +, <a class="el" href="#ab99c7fed050816eae0fa0315562e0412a55da98b018c7cc32cd1e80087ed9018e">NEOLED_CTRL_TX_BUSY</a> = 31 +<br /> + }</td></tr> +<tr class="separator:ab99c7fed050816eae0fa0315562e0412"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Smart LED Interface (NEOLED) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the NEOLED unit was synthesized (IO_NEOLED_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a3ccc1097bc70f92235d693b612fa994a" name="a3ccc1097bc70f92235d693b612fa994a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3ccc1097bc70f92235d693b612fa994a">&#9670;&#160;</a></span>NEORV32_NEOLED</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_NEOLED&#160;&#160;&#160;((<a class="el" href="structneorv32__neoled__t.html">neorv32_neoled_t</a>*) (<a class="el" href="neorv32_8h.html#a559fdce92e8af5efc426c8fc48d14f99">NEORV32_NEOLED_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEOLED module hardware access (<a class="el" href="structneorv32__neoled__t.html">neorv32_neoled_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="ab99c7fed050816eae0fa0315562e0412" name="ab99c7fed050816eae0fa0315562e0412"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab99c7fed050816eae0fa0315562e0412">&#9670;&#160;</a></span>NEORV32_NEOLED_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ab99c7fed050816eae0fa0315562e0412">NEORV32_NEOLED_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEOLED control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412af97ab77b33a250d87025c3dd3a21fea7" name="ab99c7fed050816eae0fa0315562e0412af97ab77b33a250d87025c3dd3a21fea7"></a>NEOLED_CTRL_EN&#160;</td><td class="fielddoc"><p>NEOLED control register(0) (r/w): NEOLED global enable </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412abf6779cbeae87ab55efc9573932fc865" name="ab99c7fed050816eae0fa0315562e0412abf6779cbeae87ab55efc9573932fc865"></a>NEOLED_CTRL_MODE&#160;</td><td class="fielddoc"><p>NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a436ad310b025bd3000af37986c193de5" name="ab99c7fed050816eae0fa0315562e0412a436ad310b025bd3000af37986c193de5"></a>NEOLED_CTRL_STROBE&#160;</td><td class="fielddoc"><p>NEOLED control register(2) (r/w): Strobe (0=send normal data, 1=send RESET command on data write) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a142ed3fd65e01f853666a1169f920ad0" name="ab99c7fed050816eae0fa0315562e0412a142ed3fd65e01f853666a1169f920ad0"></a>NEOLED_CTRL_PRSC0&#160;</td><td class="fielddoc"><p>NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a0f4178d81ec6fe9a8b0e30230d318a91" name="ab99c7fed050816eae0fa0315562e0412a0f4178d81ec6fe9a8b0e30230d318a91"></a>NEOLED_CTRL_PRSC1&#160;</td><td class="fielddoc"><p>NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a3d8d54c05080fddb16df4176527bafa8" name="ab99c7fed050816eae0fa0315562e0412a3d8d54c05080fddb16df4176527bafa8"></a>NEOLED_CTRL_PRSC2&#160;</td><td class="fielddoc"><p>NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a3bb5d0d1f78cebccbc8620a0194f43b8" name="ab99c7fed050816eae0fa0315562e0412a3bb5d0d1f78cebccbc8620a0194f43b8"></a>NEOLED_CTRL_BUFS_0&#160;</td><td class="fielddoc"><p>NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412aed0a878e73ad501bed3bbe6905974368" name="ab99c7fed050816eae0fa0315562e0412aed0a878e73ad501bed3bbe6905974368"></a>NEOLED_CTRL_BUFS_1&#160;</td><td class="fielddoc"><p>NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412ae7b9d45c4ef69ca15fa13aa107e68156" name="ab99c7fed050816eae0fa0315562e0412ae7b9d45c4ef69ca15fa13aa107e68156"></a>NEOLED_CTRL_BUFS_2&#160;</td><td class="fielddoc"><p>NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412ac1922a5311e91a74710eddbf86ccc1c1" name="ab99c7fed050816eae0fa0315562e0412ac1922a5311e91a74710eddbf86ccc1c1"></a>NEOLED_CTRL_BUFS_3&#160;</td><td class="fielddoc"><p>NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a44d8f064decabc690ed1f092be2b049b" name="ab99c7fed050816eae0fa0315562e0412a44d8f064decabc690ed1f092be2b049b"></a>NEOLED_CTRL_T_TOT_0&#160;</td><td class="fielddoc"><p>NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412addf4d6d1fd09f145d8aa497c4a7479c2" name="ab99c7fed050816eae0fa0315562e0412addf4d6d1fd09f145d8aa497c4a7479c2"></a>NEOLED_CTRL_T_TOT_1&#160;</td><td class="fielddoc"><p>NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a42d09d42d39fc0eb2697853c99f4d5b0" name="ab99c7fed050816eae0fa0315562e0412a42d09d42d39fc0eb2697853c99f4d5b0"></a>NEOLED_CTRL_T_TOT_2&#160;</td><td class="fielddoc"><p>NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412acbcd3c046b528e1900e86428da231df2" name="ab99c7fed050816eae0fa0315562e0412acbcd3c046b528e1900e86428da231df2"></a>NEOLED_CTRL_T_TOT_3&#160;</td><td class="fielddoc"><p>NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a3f1a0ad71d9fd892829ec0246be343b3" name="ab99c7fed050816eae0fa0315562e0412a3f1a0ad71d9fd892829ec0246be343b3"></a>NEOLED_CTRL_T_TOT_4&#160;</td><td class="fielddoc"><p>NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a7285e332ec7c2b3aeb34290e3e60ded7" name="ab99c7fed050816eae0fa0315562e0412a7285e332ec7c2b3aeb34290e3e60ded7"></a>NEOLED_CTRL_T_ZERO_H_0&#160;</td><td class="fielddoc"><p>NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a1ef56b35c966786c42f2a2f800e30eae" name="ab99c7fed050816eae0fa0315562e0412a1ef56b35c966786c42f2a2f800e30eae"></a>NEOLED_CTRL_T_ZERO_H_1&#160;</td><td class="fielddoc"><p>NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a9d9411382d943c1659b6b761c462319b" name="ab99c7fed050816eae0fa0315562e0412a9d9411382d943c1659b6b761c462319b"></a>NEOLED_CTRL_T_ZERO_H_2&#160;</td><td class="fielddoc"><p>NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412abf2ea111a4ff34b6cb4dd987c5692f5c" name="ab99c7fed050816eae0fa0315562e0412abf2ea111a4ff34b6cb4dd987c5692f5c"></a>NEOLED_CTRL_T_ZERO_H_3&#160;</td><td class="fielddoc"><p>NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a0d5d01b8d30119bb86c1d079f7d5a9ad" name="ab99c7fed050816eae0fa0315562e0412a0d5d01b8d30119bb86c1d079f7d5a9ad"></a>NEOLED_CTRL_T_ZERO_H_4&#160;</td><td class="fielddoc"><p>NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a770df505d47353f6c9289059c416d9c8" name="ab99c7fed050816eae0fa0315562e0412a770df505d47353f6c9289059c416d9c8"></a>NEOLED_CTRL_T_ONE_H_0&#160;</td><td class="fielddoc"><p>NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412aea15666ad4bb9eb1eba5dc9ed96114a6" name="ab99c7fed050816eae0fa0315562e0412aea15666ad4bb9eb1eba5dc9ed96114a6"></a>NEOLED_CTRL_T_ONE_H_1&#160;</td><td class="fielddoc"><p>NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a4d362af8c630823b5104401a9c7d734e" name="ab99c7fed050816eae0fa0315562e0412a4d362af8c630823b5104401a9c7d734e"></a>NEOLED_CTRL_T_ONE_H_2&#160;</td><td class="fielddoc"><p>NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a369f36e73783c2923d07ca333081a4a6" name="ab99c7fed050816eae0fa0315562e0412a369f36e73783c2923d07ca333081a4a6"></a>NEOLED_CTRL_T_ONE_H_3&#160;</td><td class="fielddoc"><p>NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a0c15850d0ab005b075f1a317646e18b1" name="ab99c7fed050816eae0fa0315562e0412a0c15850d0ab005b075f1a317646e18b1"></a>NEOLED_CTRL_T_ONE_H_4&#160;</td><td class="fielddoc"><p>NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a37421074b86a260b276534b7c4949339" name="ab99c7fed050816eae0fa0315562e0412a37421074b86a260b276534b7c4949339"></a>NEOLED_CTRL_IRQ_CONF&#160;</td><td class="fielddoc"><p>NEOLED control register(27) (r/w): TX FIFO interrupt: 1=IRQ if FIFO is empty, 1=IRQ if FIFO is less than half-full </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a23937f0a728da197590e1d383507cb23" name="ab99c7fed050816eae0fa0315562e0412a23937f0a728da197590e1d383507cb23"></a>NEOLED_CTRL_TX_EMPTY&#160;</td><td class="fielddoc"><p>NEOLED control register(28) (r/-): TX FIFO is empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a16c09df2784cfb6fafffaeaf245f1b73" name="ab99c7fed050816eae0fa0315562e0412a16c09df2784cfb6fafffaeaf245f1b73"></a>NEOLED_CTRL_TX_HALF&#160;</td><td class="fielddoc"><p>NEOLED control register(29) (r/-): TX FIFO is at least half-full </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412acfac5269688b2a03794dc17b11f1b983" name="ab99c7fed050816eae0fa0315562e0412acfac5269688b2a03794dc17b11f1b983"></a>NEOLED_CTRL_TX_FULL&#160;</td><td class="fielddoc"><p>NEOLED control register(30) (r/-): TX FIFO is full </p> +</td></tr> +<tr><td class="fieldname"><a id="ab99c7fed050816eae0fa0315562e0412a55da98b018c7cc32cd1e80087ed9018e" name="ab99c7fed050816eae0fa0315562e0412a55da98b018c7cc32cd1e80087ed9018e"></a>NEOLED_CTRL_TX_BUSY&#160;</td><td class="fielddoc"><p>NEOLED control register(31) (r/-): busy flag </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a57398d92fb4fc735b33e89271726e1d6" name="a57398d92fb4fc735b33e89271726e1d6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a57398d92fb4fc735b33e89271726e1d6">&#9670;&#160;</a></span>neorv32_neoled_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_neoled_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if NEOLED unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if NEOLED was not synthesized, 1 if NEOLED is available. </dd></dl> + +</div> +</div> +<a id="a8daaa97a85e0eb94d4a38eb2119ea183" name="a8daaa97a85e0eb94d4a38eb2119ea183"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8daaa97a85e0eb94d4a38eb2119ea183">&#9670;&#160;</a></span>neorv32_neoled_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable NEOLED controller. </p> + +</div> +</div> +<a id="a8181d5c1d15b7b5eecdc018341ac14fa" name="a8181d5c1d15b7b5eecdc018341ac14fa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8181d5c1d15b7b5eecdc018341ac14fa">&#9670;&#160;</a></span>neorv32_neoled_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable NEOLED controller. </p> + +</div> +</div> +<a id="a81c2c49198531fb6551eb288e29c084e" name="a81c2c49198531fb6551eb288e29c084e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a81c2c49198531fb6551eb288e29c084e">&#9670;&#160;</a></span>neorv32_neoled_get_buffer_size()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_neoled_get_buffer_size </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get NEOLED hardware buffer size.</p> +<dl class="section return"><dt>Returns</dt><dd>Number of entries in NEOLED TX buffer. </dd></dl> + +</div> +</div> +<a id="a484fcc6797b6d9cef86192e9593ec33d" name="a484fcc6797b6d9cef86192e9593ec33d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a484fcc6797b6d9cef86192e9593ec33d">&#9670;&#160;</a></span>neorv32_neoled_set_mode()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_set_mode </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>mode</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set NEOLED mode (24-bit RGB / 32-bit RGBW).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>0 = 24-bit mode (RGB), 1 = 32-bit mode (RGBW) </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac6e94602453779a2791bd0734465f5a3" name="ac6e94602453779a2791bd0734465f5a3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac6e94602453779a2791bd0734465f5a3">&#9670;&#160;</a></span>neorv32_neoled_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>t_total</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>t_high_zero</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>t_high_one</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>irq_mode</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable and configure NEOLED controller. The NEOLED control register bits are listed in <a class="el" href="#ab99c7fed050816eae0fa0315562e0412">NEORV32_NEOLED_CTRL_enum</a>. This function performs a "raw" configuration (just configuring the according control register bit).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Clock prescaler select (0..7). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">t_total</td><td>Number of pre-scaled clock ticks for total bit period (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">t_high_zero</td><td>Number of pre-scaled clock ticks to generate high-time for sending a '0' (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">t_high_one</td><td>Number of pre-scaled clock ticks to generate high-time for sending a '1' (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mode</td><td>Interrupt condition (1=IRQ if FIFO is empty, 1=IRQ if FIFO is less than half-full). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="adade69c7368c28180b9992d5f0ab6031" name="adade69c7368c28180b9992d5f0ab6031"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adade69c7368c28180b9992d5f0ab6031">&#9670;&#160;</a></span>neorv32_neoled_setup_ws2812()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_setup_ws2812 </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>irq_mode</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure NEOLED controller for using WS2812 LEDs (NeoPixel-compatible). This function computes all the required timings and finally calls <a class="el" href="neorv32__neoled_8c.html#ac6e94602453779a2791bd0734465f5a3">neorv32_neoled_setup</a>.</p> +<dl class="section note"><dt>Note</dt><dd>WS2812 timing: T_period = 1.2us, T_high_zero = 0.4us, T_high_one = 0.8us. Change the constants if required. </dd> +<dd> +This function uses the SYSINFO_CLK value (from the SYSINFO HW module) to do the timing computations.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mode</td><td>Interrupt condition (1=IRQ if FIFO is empty, 1=IRQ if FIFO is less than half-full). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a5aa9eb4dd3655fa08e1b61eb0f36589c" name="a5aa9eb4dd3655fa08e1b61eb0f36589c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5aa9eb4dd3655fa08e1b61eb0f36589c">&#9670;&#160;</a></span>neorv32_neoled_strobe_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_strobe_blocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send strobe command ("RESET") - blocking. </p> + +</div> +</div> +<a id="abf7882b949373df0774fc9cc20c2bd2e" name="abf7882b949373df0774fc9cc20c2bd2e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abf7882b949373df0774fc9cc20c2bd2e">&#9670;&#160;</a></span>neorv32_neoled_strobe_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_strobe_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send strobe command ("RESET") - non-blocking. </p> + +</div> +</div> +<a id="a3ee5b3602da3ae982628e2802587e451" name="a3ee5b3602da3ae982628e2802587e451"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3ee5b3602da3ae982628e2802587e451">&#9670;&#160;</a></span>neorv32_neoled_write_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_write_blocking </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send single RGB(W) data word to NEOLED module (blocking).</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking as it polls the NEOLED FIFO full flag.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>LSB-aligned 24-bit RGB or 32-bit RGBW data </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ad2a318bd59be12de34797ced0f7743c6" name="ad2a318bd59be12de34797ced0f7743c6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad2a318bd59be12de34797ced0f7743c6">&#9670;&#160;</a></span>neorv32_neoled_write_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_neoled_write_nonblocking </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Send single RGB(W) data word to NEOLED module (non-blocking).</p> +<dl class="section warning"><dt>Warning</dt><dd>This function uses NO busy/flag checks at all!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>LSB-aligned 24-bit RGB or 32-bit RGBW data </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr 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class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_neoled.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__neoled_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_neoled_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_neoled_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__neoled__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__neoled__t.html#adfe7618c002ff88dd22e65fcedfd6139"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__neoled__t.html#adfe7618c002ff88dd22e65fcedfd6139">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__neoled__t.html#a995fb1d63a9dfb3f20d715932781c1de"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__neoled__t.html#a995fb1d63a9dfb3f20d715932781c1de">DATA</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__neoled__t.html">neorv32_neoled_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#a3ccc1097bc70f92235d693b612fa994a"> 35</a></span><span class="preprocessor">#define NEORV32_NEOLED ((neorv32_neoled_t*) (NEORV32_NEOLED_BASE))</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="foldopen" id="foldopen00038" data-start="{" data-end="};"> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412"> 38</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412">NEORV32_NEOLED_CTRL_enum</a> {</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412af97ab77b33a250d87025c3dd3a21fea7"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412af97ab77b33a250d87025c3dd3a21fea7">NEOLED_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412abf6779cbeae87ab55efc9573932fc865"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412abf6779cbeae87ab55efc9573932fc865">NEOLED_CTRL_MODE</a> = 1, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a436ad310b025bd3000af37986c193de5"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a436ad310b025bd3000af37986c193de5">NEOLED_CTRL_STROBE</a> = 2, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a142ed3fd65e01f853666a1169f920ad0"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a142ed3fd65e01f853666a1169f920ad0">NEOLED_CTRL_PRSC0</a> = 3, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0f4178d81ec6fe9a8b0e30230d318a91"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0f4178d81ec6fe9a8b0e30230d318a91">NEOLED_CTRL_PRSC1</a> = 4, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3d8d54c05080fddb16df4176527bafa8"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3d8d54c05080fddb16df4176527bafa8">NEOLED_CTRL_PRSC2</a> = 5, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3bb5d0d1f78cebccbc8620a0194f43b8"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3bb5d0d1f78cebccbc8620a0194f43b8">NEOLED_CTRL_BUFS_0</a> = 6, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412aed0a878e73ad501bed3bbe6905974368"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412aed0a878e73ad501bed3bbe6905974368">NEOLED_CTRL_BUFS_1</a> = 7, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412ae7b9d45c4ef69ca15fa13aa107e68156"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412ae7b9d45c4ef69ca15fa13aa107e68156">NEOLED_CTRL_BUFS_2</a> = 8, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412ac1922a5311e91a74710eddbf86ccc1c1"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412ac1922a5311e91a74710eddbf86ccc1c1">NEOLED_CTRL_BUFS_3</a> = 9, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a44d8f064decabc690ed1f092be2b049b"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a44d8f064decabc690ed1f092be2b049b">NEOLED_CTRL_T_TOT_0</a> = 10, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412addf4d6d1fd09f145d8aa497c4a7479c2"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412addf4d6d1fd09f145d8aa497c4a7479c2">NEOLED_CTRL_T_TOT_1</a> = 11, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a42d09d42d39fc0eb2697853c99f4d5b0"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a42d09d42d39fc0eb2697853c99f4d5b0">NEOLED_CTRL_T_TOT_2</a> = 12, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412acbcd3c046b528e1900e86428da231df2"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412acbcd3c046b528e1900e86428da231df2">NEOLED_CTRL_T_TOT_3</a> = 13, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3f1a0ad71d9fd892829ec0246be343b3"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3f1a0ad71d9fd892829ec0246be343b3">NEOLED_CTRL_T_TOT_4</a> = 14, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a7285e332ec7c2b3aeb34290e3e60ded7"> 57</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a7285e332ec7c2b3aeb34290e3e60ded7">NEOLED_CTRL_T_ZERO_H_0</a> = 15, </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a1ef56b35c966786c42f2a2f800e30eae"> 58</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a1ef56b35c966786c42f2a2f800e30eae">NEOLED_CTRL_T_ZERO_H_1</a> = 16, </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a9d9411382d943c1659b6b761c462319b"> 59</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a9d9411382d943c1659b6b761c462319b">NEOLED_CTRL_T_ZERO_H_2</a> = 17, </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412abf2ea111a4ff34b6cb4dd987c5692f5c"> 60</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412abf2ea111a4ff34b6cb4dd987c5692f5c">NEOLED_CTRL_T_ZERO_H_3</a> = 18, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0d5d01b8d30119bb86c1d079f7d5a9ad"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0d5d01b8d30119bb86c1d079f7d5a9ad">NEOLED_CTRL_T_ZERO_H_4</a> = 19, </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a770df505d47353f6c9289059c416d9c8"> 63</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a770df505d47353f6c9289059c416d9c8">NEOLED_CTRL_T_ONE_H_0</a> = 20, </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412aea15666ad4bb9eb1eba5dc9ed96114a6"> 64</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412aea15666ad4bb9eb1eba5dc9ed96114a6">NEOLED_CTRL_T_ONE_H_1</a> = 21, </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a4d362af8c630823b5104401a9c7d734e"> 65</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a4d362af8c630823b5104401a9c7d734e">NEOLED_CTRL_T_ONE_H_2</a> = 22, </div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a369f36e73783c2923d07ca333081a4a6"> 66</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a369f36e73783c2923d07ca333081a4a6">NEOLED_CTRL_T_ONE_H_3</a> = 23, </div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0c15850d0ab005b075f1a317646e18b1"> 67</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0c15850d0ab005b075f1a317646e18b1">NEOLED_CTRL_T_ONE_H_4</a> = 24, </div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a37421074b86a260b276534b7c4949339"> 69</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a37421074b86a260b276534b7c4949339">NEOLED_CTRL_IRQ_CONF</a> = 27, </div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a23937f0a728da197590e1d383507cb23"> 70</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a23937f0a728da197590e1d383507cb23">NEOLED_CTRL_TX_EMPTY</a> = 28, </div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a16c09df2784cfb6fafffaeaf245f1b73"> 71</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a16c09df2784cfb6fafffaeaf245f1b73">NEOLED_CTRL_TX_HALF</a> = 29, </div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412acfac5269688b2a03794dc17b11f1b983"> 72</a></span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412acfac5269688b2a03794dc17b11f1b983">NEOLED_CTRL_TX_FULL</a> = 30, </div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span> <a class="code hl_enumvalue" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a55da98b018c7cc32cd1e80087ed9018e">NEOLED_CTRL_TX_BUSY</a> = 31 </div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a55da98b018c7cc32cd1e80087ed9018e"> 74</a></span>};</div> +</div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__neoled_8h.html#a57398d92fb4fc735b33e89271726e1d6">neorv32_neoled_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__neoled_8h.html#ac6e94602453779a2791bd0734465f5a3">neorv32_neoled_setup</a>(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one, <span class="keywordtype">int</span> irq_mode);</div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__neoled_8h.html#adade69c7368c28180b9992d5f0ab6031">neorv32_neoled_setup_ws2812</a>(<span class="keywordtype">int</span> irq_mode);</div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__neoled_8h.html#a484fcc6797b6d9cef86192e9593ec33d">neorv32_neoled_set_mode</a>(uint32_t mode);</div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__neoled_8h.html#a5aa9eb4dd3655fa08e1b61eb0f36589c">neorv32_neoled_strobe_blocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__neoled_8h.html#abf7882b949373df0774fc9cc20c2bd2e">neorv32_neoled_strobe_nonblocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__neoled_8h.html#a8181d5c1d15b7b5eecdc018341ac14fa">neorv32_neoled_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__neoled_8h.html#a8daaa97a85e0eb94d4a38eb2119ea183">neorv32_neoled_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__neoled_8h.html#a3ee5b3602da3ae982628e2802587e451">neorv32_neoled_write_blocking</a>(uint32_t data);</div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span>uint32_t <a class="code hl_function" href="neorv32__neoled_8h.html#a81c2c49198531fb6551eb288e29c084e">neorv32_neoled_get_buffer_size</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00102" data-start="{" data-end="}"> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"><a class="line" href="neorv32__neoled_8h.html#ad2a318bd59be12de34797ced0f7743c6"> 102</a></span><span class="keyword">inline</span> <span class="keywordtype">void</span> __attribute__ ((always_inline)) <a class="code hl_function" href="neorv32__neoled_8h.html#ad2a318bd59be12de34797ced0f7743c6">neorv32_neoled_write_nonblocking</a>(uint32_t data) {</div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span> </div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span> <a class="code hl_define" href="neorv32__neoled_8h.html#a3ccc1097bc70f92235d693b612fa994a">NEORV32_NEOLED</a>-&gt;DATA = data; <span class="comment">// send new LED data</span></div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span>}</div> +</div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span> </div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_neoled_h</span></div> +<div class="ttc" id="aneorv32__neoled_8h_html_a3ccc1097bc70f92235d693b612fa994a"><div class="ttname"><a href="neorv32__neoled_8h.html#a3ccc1097bc70f92235d693b612fa994a">NEORV32_NEOLED</a></div><div class="ttdeci">#define NEORV32_NEOLED</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:35</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_a3ee5b3602da3ae982628e2802587e451"><div class="ttname"><a href="neorv32__neoled_8h.html#a3ee5b3602da3ae982628e2802587e451">neorv32_neoled_write_blocking</a></div><div class="ttdeci">void neorv32_neoled_write_blocking(uint32_t data)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:193</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_a484fcc6797b6d9cef86192e9593ec33d"><div class="ttname"><a href="neorv32__neoled_8h.html#a484fcc6797b6d9cef86192e9593ec33d">neorv32_neoled_set_mode</a></div><div class="ttdeci">void neorv32_neoled_set_mode(uint32_t mode)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:130</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_a57398d92fb4fc735b33e89271726e1d6"><div class="ttname"><a href="neorv32__neoled_8h.html#a57398d92fb4fc735b33e89271726e1d6">neorv32_neoled_available</a></div><div class="ttdeci">int neorv32_neoled_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:26</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_a5aa9eb4dd3655fa08e1b61eb0f36589c"><div class="ttname"><a href="neorv32__neoled_8h.html#a5aa9eb4dd3655fa08e1b61eb0f36589c">neorv32_neoled_strobe_blocking</a></div><div class="ttdeci">void neorv32_neoled_strobe_blocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:142</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_a8181d5c1d15b7b5eecdc018341ac14fa"><div class="ttname"><a href="neorv32__neoled_8h.html#a8181d5c1d15b7b5eecdc018341ac14fa">neorv32_neoled_enable</a></div><div class="ttdeci">void neorv32_neoled_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:171</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_a81c2c49198531fb6551eb288e29c084e"><div class="ttname"><a href="neorv32__neoled_8h.html#a81c2c49198531fb6551eb288e29c084e">neorv32_neoled_get_buffer_size</a></div><div class="ttdeci">uint32_t neorv32_neoled_get_buffer_size(void)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:210</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_a8daaa97a85e0eb94d4a38eb2119ea183"><div class="ttname"><a href="neorv32__neoled_8h.html#a8daaa97a85e0eb94d4a38eb2119ea183">neorv32_neoled_disable</a></div><div class="ttdeci">void neorv32_neoled_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:180</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412">NEORV32_NEOLED_CTRL_enum</a></div><div class="ttdeci">NEORV32_NEOLED_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:38</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a0c15850d0ab005b075f1a317646e18b1"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0c15850d0ab005b075f1a317646e18b1">NEOLED_CTRL_T_ONE_H_4</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ONE_H_4</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:67</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a0d5d01b8d30119bb86c1d079f7d5a9ad"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0d5d01b8d30119bb86c1d079f7d5a9ad">NEOLED_CTRL_T_ZERO_H_4</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ZERO_H_4</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:61</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a0f4178d81ec6fe9a8b0e30230d318a91"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a0f4178d81ec6fe9a8b0e30230d318a91">NEOLED_CTRL_PRSC1</a></div><div class="ttdeci">@ NEOLED_CTRL_PRSC1</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:43</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a142ed3fd65e01f853666a1169f920ad0"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a142ed3fd65e01f853666a1169f920ad0">NEOLED_CTRL_PRSC0</a></div><div class="ttdeci">@ NEOLED_CTRL_PRSC0</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:42</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a16c09df2784cfb6fafffaeaf245f1b73"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a16c09df2784cfb6fafffaeaf245f1b73">NEOLED_CTRL_TX_HALF</a></div><div class="ttdeci">@ NEOLED_CTRL_TX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:71</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a1ef56b35c966786c42f2a2f800e30eae"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a1ef56b35c966786c42f2a2f800e30eae">NEOLED_CTRL_T_ZERO_H_1</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ZERO_H_1</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:58</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a23937f0a728da197590e1d383507cb23"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a23937f0a728da197590e1d383507cb23">NEOLED_CTRL_TX_EMPTY</a></div><div class="ttdeci">@ NEOLED_CTRL_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:70</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a369f36e73783c2923d07ca333081a4a6"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a369f36e73783c2923d07ca333081a4a6">NEOLED_CTRL_T_ONE_H_3</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ONE_H_3</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:66</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a37421074b86a260b276534b7c4949339"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a37421074b86a260b276534b7c4949339">NEOLED_CTRL_IRQ_CONF</a></div><div class="ttdeci">@ NEOLED_CTRL_IRQ_CONF</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:69</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a3bb5d0d1f78cebccbc8620a0194f43b8"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3bb5d0d1f78cebccbc8620a0194f43b8">NEOLED_CTRL_BUFS_0</a></div><div class="ttdeci">@ NEOLED_CTRL_BUFS_0</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:46</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a3d8d54c05080fddb16df4176527bafa8"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3d8d54c05080fddb16df4176527bafa8">NEOLED_CTRL_PRSC2</a></div><div class="ttdeci">@ NEOLED_CTRL_PRSC2</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:44</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a3f1a0ad71d9fd892829ec0246be343b3"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a3f1a0ad71d9fd892829ec0246be343b3">NEOLED_CTRL_T_TOT_4</a></div><div class="ttdeci">@ NEOLED_CTRL_T_TOT_4</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:55</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a42d09d42d39fc0eb2697853c99f4d5b0"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a42d09d42d39fc0eb2697853c99f4d5b0">NEOLED_CTRL_T_TOT_2</a></div><div class="ttdeci">@ NEOLED_CTRL_T_TOT_2</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:53</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a436ad310b025bd3000af37986c193de5"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a436ad310b025bd3000af37986c193de5">NEOLED_CTRL_STROBE</a></div><div class="ttdeci">@ NEOLED_CTRL_STROBE</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:41</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a44d8f064decabc690ed1f092be2b049b"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a44d8f064decabc690ed1f092be2b049b">NEOLED_CTRL_T_TOT_0</a></div><div class="ttdeci">@ NEOLED_CTRL_T_TOT_0</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:51</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a4d362af8c630823b5104401a9c7d734e"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a4d362af8c630823b5104401a9c7d734e">NEOLED_CTRL_T_ONE_H_2</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ONE_H_2</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:65</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a55da98b018c7cc32cd1e80087ed9018e"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a55da98b018c7cc32cd1e80087ed9018e">NEOLED_CTRL_TX_BUSY</a></div><div class="ttdeci">@ NEOLED_CTRL_TX_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:73</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a7285e332ec7c2b3aeb34290e3e60ded7"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a7285e332ec7c2b3aeb34290e3e60ded7">NEOLED_CTRL_T_ZERO_H_0</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ZERO_H_0</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:57</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a770df505d47353f6c9289059c416d9c8"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a770df505d47353f6c9289059c416d9c8">NEOLED_CTRL_T_ONE_H_0</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ONE_H_0</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:63</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412a9d9411382d943c1659b6b761c462319b"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412a9d9411382d943c1659b6b761c462319b">NEOLED_CTRL_T_ZERO_H_2</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ZERO_H_2</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:59</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412abf2ea111a4ff34b6cb4dd987c5692f5c"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412abf2ea111a4ff34b6cb4dd987c5692f5c">NEOLED_CTRL_T_ZERO_H_3</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ZERO_H_3</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:60</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412abf6779cbeae87ab55efc9573932fc865"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412abf6779cbeae87ab55efc9573932fc865">NEOLED_CTRL_MODE</a></div><div class="ttdeci">@ NEOLED_CTRL_MODE</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:40</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412ac1922a5311e91a74710eddbf86ccc1c1"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412ac1922a5311e91a74710eddbf86ccc1c1">NEOLED_CTRL_BUFS_3</a></div><div class="ttdeci">@ NEOLED_CTRL_BUFS_3</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:49</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412acbcd3c046b528e1900e86428da231df2"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412acbcd3c046b528e1900e86428da231df2">NEOLED_CTRL_T_TOT_3</a></div><div class="ttdeci">@ NEOLED_CTRL_T_TOT_3</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:54</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412acfac5269688b2a03794dc17b11f1b983"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412acfac5269688b2a03794dc17b11f1b983">NEOLED_CTRL_TX_FULL</a></div><div class="ttdeci">@ NEOLED_CTRL_TX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:72</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412addf4d6d1fd09f145d8aa497c4a7479c2"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412addf4d6d1fd09f145d8aa497c4a7479c2">NEOLED_CTRL_T_TOT_1</a></div><div class="ttdeci">@ NEOLED_CTRL_T_TOT_1</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:52</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412ae7b9d45c4ef69ca15fa13aa107e68156"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412ae7b9d45c4ef69ca15fa13aa107e68156">NEOLED_CTRL_BUFS_2</a></div><div class="ttdeci">@ NEOLED_CTRL_BUFS_2</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:48</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412aea15666ad4bb9eb1eba5dc9ed96114a6"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412aea15666ad4bb9eb1eba5dc9ed96114a6">NEOLED_CTRL_T_ONE_H_1</a></div><div class="ttdeci">@ NEOLED_CTRL_T_ONE_H_1</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:64</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412aed0a878e73ad501bed3bbe6905974368"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412aed0a878e73ad501bed3bbe6905974368">NEOLED_CTRL_BUFS_1</a></div><div class="ttdeci">@ NEOLED_CTRL_BUFS_1</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:47</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ab99c7fed050816eae0fa0315562e0412af97ab77b33a250d87025c3dd3a21fea7"><div class="ttname"><a href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412af97ab77b33a250d87025c3dd3a21fea7">NEOLED_CTRL_EN</a></div><div class="ttdeci">@ NEOLED_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:39</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_abf7882b949373df0774fc9cc20c2bd2e"><div class="ttname"><a href="neorv32__neoled_8h.html#abf7882b949373df0774fc9cc20c2bd2e">neorv32_neoled_strobe_nonblocking</a></div><div class="ttdeci">void neorv32_neoled_strobe_nonblocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:157</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ac6e94602453779a2791bd0734465f5a3"><div class="ttname"><a href="neorv32__neoled_8h.html#ac6e94602453779a2791bd0734465f5a3">neorv32_neoled_setup</a></div><div class="ttdeci">void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one, int irq_mode)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:47</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_ad2a318bd59be12de34797ced0f7743c6"><div class="ttname"><a href="neorv32__neoled_8h.html#ad2a318bd59be12de34797ced0f7743c6">neorv32_neoled_write_nonblocking</a></div><div class="ttdeci">void neorv32_neoled_write_nonblocking(uint32_t data)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:102</div></div> +<div class="ttc" id="aneorv32__neoled_8h_html_adade69c7368c28180b9992d5f0ab6031"><div class="ttname"><a href="neorv32__neoled_8h.html#adade69c7368c28180b9992d5f0ab6031">neorv32_neoled_setup_ws2812</a></div><div class="ttdeci">void neorv32_neoled_setup_ws2812(int irq_mode)</div><div class="ttdef"><b>Definition</b> neorv32_neoled.c:71</div></div> +<div class="ttc" id="astructneorv32__neoled__t_html"><div class="ttname"><a href="structneorv32__neoled__t.html">neorv32_neoled_t</a></div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:29</div></div> +<div class="ttc" id="astructneorv32__neoled__t_html_a995fb1d63a9dfb3f20d715932781c1de"><div class="ttname"><a href="structneorv32__neoled__t.html#a995fb1d63a9dfb3f20d715932781c1de">neorv32_neoled_t::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:31</div></div> +<div class="ttc" id="astructneorv32__neoled__t_html_adfe7618c002ff88dd22e65fcedfd6139"><div class="ttname"><a href="structneorv32__neoled__t.html#adfe7618c002ff88dd22e65fcedfd6139">neorv32_neoled_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_neoled.h:30</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__newlib_8c.html b/sw/neorv32__newlib_8c.html new file mode 100644 index 000000000..69126f8a9 --- /dev/null +++ b/sw/neorv32__newlib_8c.html @@ -0,0 +1,167 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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class="title">neorv32_newlib.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>NEORV32-specific Newlib system calls. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;newlib.h&gt;</code><br /> +<code>#include &lt;sys/stat.h&gt;</code><br /> +<code>#include &lt;sys/timeb.h&gt;</code><br /> +<code>#include &lt;sys/times.h&gt;</code><br /> +<code>#include &lt;sys/time.h&gt;</code><br /> +<code>#include &lt;time.h&gt;</code><br /> +<code>#include &lt;unistd.h&gt;</code><br /> +<code>#include &lt;errno.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a38f8394eee3a086b87ff6d431e1e5343" id="r_a38f8394eee3a086b87ff6d431e1e5343"><td class="memItemLeft" align="right" valign="top"><a id="a38f8394eee3a086b87ff6d431e1e5343" name="a38f8394eee3a086b87ff6d431e1e5343"></a> +void *&#160;</td><td class="memItemRight" valign="bottom"><b>_sbrk</b> (int incr)</td></tr> +<tr class="separator:a38f8394eee3a086b87ff6d431e1e5343"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5aab5e2acfd600e3667dc915a2bbc7cb" id="r_a5aab5e2acfd600e3667dc915a2bbc7cb"><td class="memItemLeft" align="right" valign="top"><a id="a5aab5e2acfd600e3667dc915a2bbc7cb" name="a5aab5e2acfd600e3667dc915a2bbc7cb"></a> +int&#160;</td><td class="memItemRight" valign="bottom"><b>_close</b> (int file)</td></tr> +<tr class="separator:a5aab5e2acfd600e3667dc915a2bbc7cb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a41eef54307912a82d20e71c3d47315aa" id="r_a41eef54307912a82d20e71c3d47315aa"><td class="memItemLeft" align="right" valign="top"><a id="a41eef54307912a82d20e71c3d47315aa" name="a41eef54307912a82d20e71c3d47315aa"></a> +int&#160;</td><td class="memItemRight" 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class="memItemLeft" align="right" valign="top"><a id="a4f9bf1e1602f2828e0a54e70c3b2dccb" name="a4f9bf1e1602f2828e0a54e70c3b2dccb"></a> +int&#160;</td><td class="memItemRight" valign="bottom"><b>_read</b> (int file, char *ptr, int len)</td></tr> +<tr class="separator:a4f9bf1e1602f2828e0a54e70c3b2dccb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adb34f735d9a9fc1e9d1acc68a6c05d8c" id="r_adb34f735d9a9fc1e9d1acc68a6c05d8c"><td class="memItemLeft" align="right" valign="top"><a id="adb34f735d9a9fc1e9d1acc68a6c05d8c" name="adb34f735d9a9fc1e9d1acc68a6c05d8c"></a> +int&#160;</td><td class="memItemRight" valign="bottom"><b>_gettimeofday</b> (struct timeval *tp, void *tzp)</td></tr> +<tr class="separator:adb34f735d9a9fc1e9d1acc68a6c05d8c"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:ad65a8842cc674e3ddf69355898c0ecbf" id="r_ad65a8842cc674e3ddf69355898c0ecbf"><td class="memItemLeft" align="right" valign="top"><a id="ad65a8842cc674e3ddf69355898c0ecbf" name="ad65a8842cc674e3ddf69355898c0ecbf"></a> +int&#160;</td><td class="memItemRight" valign="bottom"><b>errno</b></td></tr> +<tr class="separator:ad65a8842cc674e3ddf69355898c0ecbf"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>NEORV32-specific Newlib system calls. </p> +<dl class="section note"><dt>Note</dt><dd>Original source file: <a href="https://github.com/openhwgroup/cv32e40p/blob/master/example_tb/core/custom/syscalls.c">https://github.com/openhwgroup/cv32e40p/blob/master/example_tb/core/custom/syscalls.c</a> </dd> +<dd> +More information was derived from: <a href="https://interrupt.memfault.com/blog/boostrapping-libc-with-newlib#implementing-newlib">https://interrupt.memfault.com/blog/boostrapping-libc-with-newlib#implementing-newlib</a></dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__onewire_8c.html b/sw/neorv32__onewire_8c.html new file mode 100644 index 000000000..2871f6da3 --- /dev/null +++ b/sw/neorv32__onewire_8c.html @@ -0,0 +1,552 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>1-Wire Interface Controller (ONEWIRE) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a865e5c381fd3c27c6981a589a5124d1e" id="r_a865e5c381fd3c27c6981a589a5124d1e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a865e5c381fd3c27c6981a589a5124d1e">neorv32_onewire_available</a> (void)</td></tr> +<tr class="separator:a865e5c381fd3c27c6981a589a5124d1e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a224005037387484dfa510a1355a62828" id="r_a224005037387484dfa510a1355a62828"><td class="memItemLeft" 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href="#a7510e65a26aeefb40e994fd00667537e">neorv32_onewire_read_byte_blocking</a> (void)</td></tr> +<tr class="separator:a7510e65a26aeefb40e994fd00667537e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac78557c77482b59394677f42fda4fdf1" id="r_ac78557c77482b59394677f42fda4fdf1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac78557c77482b59394677f42fda4fdf1">neorv32_onewire_write_byte_blocking</a> (uint8_t byte)</td></tr> +<tr class="separator:ac78557c77482b59394677f42fda4fdf1"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>1-Wire Interface Controller (ONEWIRE) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the ONEWIRE unit was synthesized (IO_ONEWIRE_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a865e5c381fd3c27c6981a589a5124d1e" name="a865e5c381fd3c27c6981a589a5124d1e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a865e5c381fd3c27c6981a589a5124d1e">&#9670;&#160;</a></span>neorv32_onewire_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if ONEWIRE controller was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if ONEWIRE was not synthesized, 1 if ONEWIRE is available. </dd></dl> + +</div> +</div> +<a id="a01b6236b89c045ddbd58398361c6ee0a" name="a01b6236b89c045ddbd58398361c6ee0a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a01b6236b89c045ddbd58398361c6ee0a">&#9670;&#160;</a></span>neorv32_onewire_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_busy </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if ONEWIRE module is busy.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if not busy, 1 if busy. </dd></dl> + +</div> +</div> +<a id="a7e329eeb1cd98301a53b271a6a102385" name="a7e329eeb1cd98301a53b271a6a102385"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7e329eeb1cd98301a53b271a6a102385">&#9670;&#160;</a></span>neorv32_onewire_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable ONEWIRE controller. </p> + +</div> +</div> +<a id="ae6fe766e7decf18869cfb86bba741ca4" name="ae6fe766e7decf18869cfb86bba741ca4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae6fe766e7decf18869cfb86bba741ca4">&#9670;&#160;</a></span>neorv32_onewire_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable ONEWIRE controller. </p> + +</div> +</div> +<a id="aace8398062b759256a516e6245aced83" name="aace8398062b759256a516e6245aced83"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aace8398062b759256a516e6245aced83">&#9670;&#160;</a></span>neorv32_onewire_read_bit()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_read_bit </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate single-bit read.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd></dl> + +</div> +</div> +<a id="ace8b7cf697b068b6b51676d84dec5960" name="ace8b7cf697b068b6b51676d84dec5960"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ace8b7cf697b068b6b51676d84dec5960">&#9670;&#160;</a></span>neorv32_onewire_read_bit_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_onewire_read_bit_blocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read single bit.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Read bit in bit 0. </dd></dl> + +</div> +</div> +<a id="aa4a19d2d8dc3b3401307615aec201190" name="aa4a19d2d8dc3b3401307615aec201190"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa4a19d2d8dc3b3401307615aec201190">&#9670;&#160;</a></span>neorv32_onewire_read_bit_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_onewire_read_bit_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get bit from previous single-bit read operation</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Read bit in bit 0. </dd></dl> + +</div> +</div> +<a id="a01ddba7a9148be542b5c52e39e6f46d6" name="a01ddba7a9148be542b5c52e39e6f46d6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a01ddba7a9148be542b5c52e39e6f46d6">&#9670;&#160;</a></span>neorv32_onewire_read_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_read_byte </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate read byte.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd></dl> + +</div> +</div> +<a id="a7510e65a26aeefb40e994fd00667537e" name="a7510e65a26aeefb40e994fd00667537e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7510e65a26aeefb40e994fd00667537e">&#9670;&#160;</a></span>neorv32_onewire_read_byte_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_onewire_read_byte_blocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read byte.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Read byte. </dd></dl> + +</div> +</div> +<a id="a4c7eec15c095c97c939163f631f51dab" name="a4c7eec15c095c97c939163f631f51dab"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4c7eec15c095c97c939163f631f51dab">&#9670;&#160;</a></span>neorv32_onewire_read_byte_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_onewire_read_byte_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get data from previous read byte operation.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Read byte. </dd></dl> + +</div> +</div> +<a id="a3072f7167831edc95dee44ecfef6a0d4" name="a3072f7167831edc95dee44ecfef6a0d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3072f7167831edc95dee44ecfef6a0d4">&#9670;&#160;</a></span>neorv32_onewire_reset()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_reset </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate reset pulse.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd></dl> + +</div> +</div> +<a id="af8ca6be495176797b7da3857e2f794f9" name="af8ca6be495176797b7da3857e2f794f9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af8ca6be495176797b7da3857e2f794f9">&#9670;&#160;</a></span>neorv32_onewire_reset_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_reset_blocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate reset pulse and check if any bus device is present.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if at lest one device is present, -1 otherwise </dd></dl> + +</div> +</div> +<a id="a43eb8a08eeaa83e3d7e9aa5058a4269f" name="a43eb8a08eeaa83e3d7e9aa5058a4269f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a43eb8a08eeaa83e3d7e9aa5058a4269f">&#9670;&#160;</a></span>neorv32_onewire_reset_get_presence()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_reset_get_presence </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get bus presence (after RESET).</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if at lest one device is present, -1 otherwise </dd></dl> + +</div> +</div> +<a id="a122531c7154126858c46d89e003d838d" name="a122531c7154126858c46d89e003d838d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a122531c7154126858c46d89e003d838d">&#9670;&#160;</a></span>neorv32_onewire_sense()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_sense </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get current bus state.</p> +<dl class="section return"><dt>Returns</dt><dd>1 if bus is high, 0 if bus is low. </dd></dl> + +</div> +</div> +<a id="a224005037387484dfa510a1355a62828" name="a224005037387484dfa510a1355a62828"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a224005037387484dfa510a1355a62828">&#9670;&#160;</a></span>neorv32_onewire_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>t_base</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, configure and enable ONEWIRE interface controller.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">t_base</td><td>Base tick time in ns. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if configuration failed, otherwise the actual t_base time in ns is returned. </dd></dl> + +</div> +</div> +<a id="a49d0a2a386f129fd2f4fed880bba31d4" name="a49d0a2a386f129fd2f4fed880bba31d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a49d0a2a386f129fd2f4fed880bba31d4">&#9670;&#160;</a></span>neorv32_onewire_write_bit()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_write_bit </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>bit</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate single-bit write.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">bit</td><td>Bit to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a6f7b6690a2437e0b574a8a9a23dc0eaa" name="a6f7b6690a2437e0b574a8a9a23dc0eaa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6f7b6690a2437e0b574a8a9a23dc0eaa">&#9670;&#160;</a></span>neorv32_onewire_write_bit_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_write_bit_blocking </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>bit</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write single bit.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">bit</td><td>Bit to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a23b96b68c3214b188525eb102cafb620" name="a23b96b68c3214b188525eb102cafb620"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a23b96b68c3214b188525eb102cafb620">&#9670;&#160;</a></span>neorv32_onewire_write_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_write_byte </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>byte</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate write byte.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Byte to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac78557c77482b59394677f42fda4fdf1" name="ac78557c77482b59394677f42fda4fdf1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac78557c77482b59394677f42fda4fdf1">&#9670;&#160;</a></span>neorv32_onewire_write_byte_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_write_byte_blocking </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>byte</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write byte.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Byte to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" 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href="structneorv32__onewire__t.html">neorv32_onewire_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:a865e5c381fd3c27c6981a589a5124d1e" id="r_a865e5c381fd3c27c6981a589a5124d1e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a865e5c381fd3c27c6981a589a5124d1e">neorv32_onewire_available</a> (void)</td></tr> +<tr class="separator:a865e5c381fd3c27c6981a589a5124d1e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a224005037387484dfa510a1355a62828" id="r_a224005037387484dfa510a1355a62828"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" 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id="r_a3072f7167831edc95dee44ecfef6a0d4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3072f7167831edc95dee44ecfef6a0d4">neorv32_onewire_reset</a> (void)</td></tr> +<tr class="separator:a3072f7167831edc95dee44ecfef6a0d4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a43eb8a08eeaa83e3d7e9aa5058a4269f" id="r_a43eb8a08eeaa83e3d7e9aa5058a4269f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a43eb8a08eeaa83e3d7e9aa5058a4269f">neorv32_onewire_reset_get_presence</a> (void)</td></tr> +<tr class="separator:a43eb8a08eeaa83e3d7e9aa5058a4269f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aace8398062b759256a516e6245aced83" id="r_aace8398062b759256a516e6245aced83"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a23b96b68c3214b188525eb102cafb620">neorv32_onewire_write_byte</a> (uint8_t byte)</td></tr> +<tr class="separator:a23b96b68c3214b188525eb102cafb620"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af8ca6be495176797b7da3857e2f794f9" id="r_af8ca6be495176797b7da3857e2f794f9"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af8ca6be495176797b7da3857e2f794f9">neorv32_onewire_reset_blocking</a> (void)</td></tr> +<tr class="separator:af8ca6be495176797b7da3857e2f794f9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ace8b7cf697b068b6b51676d84dec5960" id="r_ace8b7cf697b068b6b51676d84dec5960"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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class="separator:a7510e65a26aeefb40e994fd00667537e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac78557c77482b59394677f42fda4fdf1" id="r_ac78557c77482b59394677f42fda4fdf1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac78557c77482b59394677f42fda4fdf1">neorv32_onewire_write_byte_blocking</a> (uint8_t byte)</td></tr> +<tr class="separator:ac78557c77482b59394677f42fda4fdf1"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: 1-Wire Interface Controller (ONEWIRE)</h2></td></tr> +<tr class="memitem:a6f119e35d7ac01f110987508ff3becc9" id="r_a6f119e35d7ac01f110987508ff3becc9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6f119e35d7ac01f110987508ff3becc9">NEORV32_ONEWIRE</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__onewire__t.html">neorv32_onewire_t</a>*) (<a class="el" href="neorv32_8h.html#a8d0b612e52b77395a05d4f18af6fcf00">NEORV32_ONEWIRE_BASE</a>))</td></tr> +<tr class="separator:a6f119e35d7ac01f110987508ff3becc9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ade1a01f533843880868ec7496d116831" id="r_ade1a01f533843880868ec7496d116831"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ade1a01f533843880868ec7496d116831">NEORV32_ONEWIRE_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ade1a01f533843880868ec7496d116831ab87882c202f80185278c69e482f147da">ONEWIRE_CTRL_EN</a> = 0 +, <a class="el" href="#ade1a01f533843880868ec7496d116831abfed6417c3abd7ef94cd18a3b32c4393">ONEWIRE_CTRL_PRSC0</a> = 1 +, <a class="el" href="#ade1a01f533843880868ec7496d116831aee1e24261e263c70bf2e36dcafc9dc74">ONEWIRE_CTRL_PRSC1</a> = 2 +, <a class="el" href="#ade1a01f533843880868ec7496d116831acdfca08f34d7379aaf8505ba3425c6f5">ONEWIRE_CTRL_CLKDIV0</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#ade1a01f533843880868ec7496d116831afa1476a5e04eb4eabf4d7a595eca2df9">ONEWIRE_CTRL_CLKDIV1</a> = 4 +, <a class="el" href="#ade1a01f533843880868ec7496d116831aec9f056072e1db747e74a5c695d2a1df">ONEWIRE_CTRL_CLKDIV2</a> = 5 +, <a class="el" href="#ade1a01f533843880868ec7496d116831ab8600bd09d74e39869259881b84ebfbf">ONEWIRE_CTRL_CLKDIV3</a> = 6 +, <a class="el" href="#ade1a01f533843880868ec7496d116831a32af8c86e7166e02e801727bd261c179">ONEWIRE_CTRL_CLKDIV4</a> = 7 +, <br /> +&#160;&#160;<a class="el" href="#ade1a01f533843880868ec7496d116831a789d65fd9b0ab17bffd0d6de9d2e132a">ONEWIRE_CTRL_CLKDIV5</a> = 8 +, <a class="el" href="#ade1a01f533843880868ec7496d116831a27f040454bebc6218b490f7160ea2312">ONEWIRE_CTRL_CLKDIV6</a> = 9 +, <a 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colspan="2">&#160;</td></tr> +<tr class="memitem:ae770490afa8662fb8577065531d51368" id="r_ae770490afa8662fb8577065531d51368"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae770490afa8662fb8577065531d51368">NEORV32_ONEWIRE_DATA_enum</a> { <a class="el" href="#ae770490afa8662fb8577065531d51368a6ad35475e3f80a8c68ce0caa9c3754a5">ONEWIRE_DATA_LSB</a> = 0 +, <a class="el" href="#ae770490afa8662fb8577065531d51368af967429634efb019ada46bf75f373aa3">ONEWIRE_DATA_MSB</a> = 7 + }</td></tr> +<tr class="separator:ae770490afa8662fb8577065531d51368"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>1-Wire Interface Controller (ONEWIRE) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the ONEWIRE unit was synthesized (IO_ONEWIRE_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a6f119e35d7ac01f110987508ff3becc9" name="a6f119e35d7ac01f110987508ff3becc9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6f119e35d7ac01f110987508ff3becc9">&#9670;&#160;</a></span>NEORV32_ONEWIRE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_ONEWIRE&#160;&#160;&#160;((<a class="el" href="structneorv32__onewire__t.html">neorv32_onewire_t</a>*) (<a class="el" href="neorv32_8h.html#a8d0b612e52b77395a05d4f18af6fcf00">NEORV32_ONEWIRE_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>ONEWIRE module hardware access (<a class="el" href="structneorv32__onewire__t.html">neorv32_onewire_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="ade1a01f533843880868ec7496d116831" name="ade1a01f533843880868ec7496d116831"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ade1a01f533843880868ec7496d116831">&#9670;&#160;</a></span>NEORV32_ONEWIRE_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ade1a01f533843880868ec7496d116831">NEORV32_ONEWIRE_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>ONEWIRE control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831ab87882c202f80185278c69e482f147da" name="ade1a01f533843880868ec7496d116831ab87882c202f80185278c69e482f147da"></a>ONEWIRE_CTRL_EN&#160;</td><td class="fielddoc"><p>ONEWIRE control register(0) (r/w): ONEWIRE controller enable </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831abfed6417c3abd7ef94cd18a3b32c4393" name="ade1a01f533843880868ec7496d116831abfed6417c3abd7ef94cd18a3b32c4393"></a>ONEWIRE_CTRL_PRSC0&#160;</td><td class="fielddoc"><p>ONEWIRE control register(1) (r/w): Clock prescaler select bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831aee1e24261e263c70bf2e36dcafc9dc74" name="ade1a01f533843880868ec7496d116831aee1e24261e263c70bf2e36dcafc9dc74"></a>ONEWIRE_CTRL_PRSC1&#160;</td><td class="fielddoc"><p>ONEWIRE control register(2) (r/w): Clock prescaler select bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831acdfca08f34d7379aaf8505ba3425c6f5" name="ade1a01f533843880868ec7496d116831acdfca08f34d7379aaf8505ba3425c6f5"></a>ONEWIRE_CTRL_CLKDIV0&#160;</td><td class="fielddoc"><p>ONEWIRE control register(3) (r/w): Clock divider bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831afa1476a5e04eb4eabf4d7a595eca2df9" name="ade1a01f533843880868ec7496d116831afa1476a5e04eb4eabf4d7a595eca2df9"></a>ONEWIRE_CTRL_CLKDIV1&#160;</td><td class="fielddoc"><p>ONEWIRE control register(4) (r/w): Clock divider bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831aec9f056072e1db747e74a5c695d2a1df" name="ade1a01f533843880868ec7496d116831aec9f056072e1db747e74a5c695d2a1df"></a>ONEWIRE_CTRL_CLKDIV2&#160;</td><td class="fielddoc"><p>ONEWIRE control register(5) (r/w): Clock divider bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831ab8600bd09d74e39869259881b84ebfbf" name="ade1a01f533843880868ec7496d116831ab8600bd09d74e39869259881b84ebfbf"></a>ONEWIRE_CTRL_CLKDIV3&#160;</td><td class="fielddoc"><p>ONEWIRE control register(6) (r/w): Clock divider bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831a32af8c86e7166e02e801727bd261c179" name="ade1a01f533843880868ec7496d116831a32af8c86e7166e02e801727bd261c179"></a>ONEWIRE_CTRL_CLKDIV4&#160;</td><td class="fielddoc"><p>ONEWIRE control register(7) (r/w): Clock divider bit 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831a789d65fd9b0ab17bffd0d6de9d2e132a" name="ade1a01f533843880868ec7496d116831a789d65fd9b0ab17bffd0d6de9d2e132a"></a>ONEWIRE_CTRL_CLKDIV5&#160;</td><td class="fielddoc"><p>ONEWIRE control register(8) (r/w): Clock divider bit 5 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831a27f040454bebc6218b490f7160ea2312" name="ade1a01f533843880868ec7496d116831a27f040454bebc6218b490f7160ea2312"></a>ONEWIRE_CTRL_CLKDIV6&#160;</td><td class="fielddoc"><p>ONEWIRE control register(9) (r/w): Clock divider bit 6 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831a8b19096f72ef96a7597fda9be625ed40" name="ade1a01f533843880868ec7496d116831a8b19096f72ef96a7597fda9be625ed40"></a>ONEWIRE_CTRL_CLKDIV7&#160;</td><td class="fielddoc"><p>ONEWIRE control register(10) (r/w): Clock divider bit 7 </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831a98624ec944e0413a208cdf54bbbf4c75" name="ade1a01f533843880868ec7496d116831a98624ec944e0413a208cdf54bbbf4c75"></a>ONEWIRE_CTRL_TRIG_RST&#160;</td><td class="fielddoc"><p>ONEWIRE control register(11) (-/w): Trigger reset pulse, auto-clears </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831a7ecbccef9e77e68caf22ed2c416e1f77" name="ade1a01f533843880868ec7496d116831a7ecbccef9e77e68caf22ed2c416e1f77"></a>ONEWIRE_CTRL_TRIG_BIT&#160;</td><td class="fielddoc"><p>ONEWIRE control register(12) (-/w): Trigger single-bit transmission, auto-clears </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831acfd8a56f668ca55dbbaa1714b1235dfe" name="ade1a01f533843880868ec7496d116831acfd8a56f668ca55dbbaa1714b1235dfe"></a>ONEWIRE_CTRL_TRIG_BYTE&#160;</td><td class="fielddoc"><p>ONEWIRE control register(13) (-/w): Trigger full-byte transmission, auto-clears </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831af992c94d0b9a7b7b92a5a23366b9a8c6" name="ade1a01f533843880868ec7496d116831af992c94d0b9a7b7b92a5a23366b9a8c6"></a>ONEWIRE_CTRL_SENSE&#160;</td><td class="fielddoc"><p>ONEWIRE control register(29) (r/-): Current state of the bus line </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831a92e1ff9fa10319d64c8d2c6a6d61b37e" name="ade1a01f533843880868ec7496d116831a92e1ff9fa10319d64c8d2c6a6d61b37e"></a>ONEWIRE_CTRL_PRESENCE&#160;</td><td class="fielddoc"><p>ONEWIRE control register(30) (r/-): Bus presence detected </p> +</td></tr> +<tr><td class="fieldname"><a id="ade1a01f533843880868ec7496d116831aac8933755e80d72e1e9c293198d831b9" name="ade1a01f533843880868ec7496d116831aac8933755e80d72e1e9c293198d831b9"></a>ONEWIRE_CTRL_BUSY&#160;</td><td class="fielddoc"><p>ONEWIRE control register(31) (r/-): Operation in progress when set </p> +</td></tr> +</table> + +</div> +</div> +<a id="ae770490afa8662fb8577065531d51368" name="ae770490afa8662fb8577065531d51368"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae770490afa8662fb8577065531d51368">&#9670;&#160;</a></span>NEORV32_ONEWIRE_DATA_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ae770490afa8662fb8577065531d51368">NEORV32_ONEWIRE_DATA_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>ONEWIRE receive/transmit data register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ae770490afa8662fb8577065531d51368a6ad35475e3f80a8c68ce0caa9c3754a5" name="ae770490afa8662fb8577065531d51368a6ad35475e3f80a8c68ce0caa9c3754a5"></a>ONEWIRE_DATA_LSB&#160;</td><td class="fielddoc"><p>ONEWIRE data register(0) (r/w): Receive/transmit data (8-bit) LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="ae770490afa8662fb8577065531d51368af967429634efb019ada46bf75f373aa3" name="ae770490afa8662fb8577065531d51368af967429634efb019ada46bf75f373aa3"></a>ONEWIRE_DATA_MSB&#160;</td><td class="fielddoc"><p>ONEWIRE data register(7) (r/w): Receive/transmit data (8-bit) MSB </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a865e5c381fd3c27c6981a589a5124d1e" name="a865e5c381fd3c27c6981a589a5124d1e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a865e5c381fd3c27c6981a589a5124d1e">&#9670;&#160;</a></span>neorv32_onewire_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if ONEWIRE controller was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if ONEWIRE was not synthesized, 1 if ONEWIRE is available. </dd></dl> + +</div> +</div> +<a id="a01b6236b89c045ddbd58398361c6ee0a" name="a01b6236b89c045ddbd58398361c6ee0a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a01b6236b89c045ddbd58398361c6ee0a">&#9670;&#160;</a></span>neorv32_onewire_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_busy </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if ONEWIRE module is busy.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if not busy, 1 if busy. </dd></dl> + +</div> +</div> +<a id="a7e329eeb1cd98301a53b271a6a102385" name="a7e329eeb1cd98301a53b271a6a102385"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7e329eeb1cd98301a53b271a6a102385">&#9670;&#160;</a></span>neorv32_onewire_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable ONEWIRE controller. </p> + +</div> +</div> +<a id="ae6fe766e7decf18869cfb86bba741ca4" name="ae6fe766e7decf18869cfb86bba741ca4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae6fe766e7decf18869cfb86bba741ca4">&#9670;&#160;</a></span>neorv32_onewire_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable ONEWIRE controller. </p> + +</div> +</div> +<a id="aace8398062b759256a516e6245aced83" name="aace8398062b759256a516e6245aced83"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aace8398062b759256a516e6245aced83">&#9670;&#160;</a></span>neorv32_onewire_read_bit()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_read_bit </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate single-bit read.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd></dl> + +</div> +</div> +<a id="ace8b7cf697b068b6b51676d84dec5960" name="ace8b7cf697b068b6b51676d84dec5960"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ace8b7cf697b068b6b51676d84dec5960">&#9670;&#160;</a></span>neorv32_onewire_read_bit_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_onewire_read_bit_blocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read single bit.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Read bit in bit 0. </dd></dl> + +</div> +</div> +<a id="aa4a19d2d8dc3b3401307615aec201190" name="aa4a19d2d8dc3b3401307615aec201190"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa4a19d2d8dc3b3401307615aec201190">&#9670;&#160;</a></span>neorv32_onewire_read_bit_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_onewire_read_bit_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get bit from previous single-bit read operation</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Read bit in bit 0. </dd></dl> + +</div> +</div> +<a id="a01ddba7a9148be542b5c52e39e6f46d6" name="a01ddba7a9148be542b5c52e39e6f46d6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a01ddba7a9148be542b5c52e39e6f46d6">&#9670;&#160;</a></span>neorv32_onewire_read_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_read_byte </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate read byte.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd></dl> + +</div> +</div> +<a id="a7510e65a26aeefb40e994fd00667537e" name="a7510e65a26aeefb40e994fd00667537e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7510e65a26aeefb40e994fd00667537e">&#9670;&#160;</a></span>neorv32_onewire_read_byte_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_onewire_read_byte_blocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Read byte.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Read byte. </dd></dl> + +</div> +</div> +<a id="a4c7eec15c095c97c939163f631f51dab" name="a4c7eec15c095c97c939163f631f51dab"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4c7eec15c095c97c939163f631f51dab">&#9670;&#160;</a></span>neorv32_onewire_read_byte_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_onewire_read_byte_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get data from previous read byte operation.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Read byte. </dd></dl> + +</div> +</div> +<a id="a3072f7167831edc95dee44ecfef6a0d4" name="a3072f7167831edc95dee44ecfef6a0d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3072f7167831edc95dee44ecfef6a0d4">&#9670;&#160;</a></span>neorv32_onewire_reset()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_reset </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate reset pulse.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd></dl> + +</div> +</div> +<a id="af8ca6be495176797b7da3857e2f794f9" name="af8ca6be495176797b7da3857e2f794f9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af8ca6be495176797b7da3857e2f794f9">&#9670;&#160;</a></span>neorv32_onewire_reset_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_reset_blocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate reset pulse and check if any bus device is present.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if at lest one device is present, -1 otherwise </dd></dl> + +</div> +</div> +<a id="a43eb8a08eeaa83e3d7e9aa5058a4269f" name="a43eb8a08eeaa83e3d7e9aa5058a4269f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a43eb8a08eeaa83e3d7e9aa5058a4269f">&#9670;&#160;</a></span>neorv32_onewire_reset_get_presence()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_reset_get_presence </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get bus presence (after RESET).</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if at lest one device is present, -1 otherwise </dd></dl> + +</div> +</div> +<a id="a122531c7154126858c46d89e003d838d" name="a122531c7154126858c46d89e003d838d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a122531c7154126858c46d89e003d838d">&#9670;&#160;</a></span>neorv32_onewire_sense()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_sense </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get current bus state.</p> +<dl class="section return"><dt>Returns</dt><dd>1 if bus is high, 0 if bus is low. </dd></dl> + +</div> +</div> +<a id="a224005037387484dfa510a1355a62828" name="a224005037387484dfa510a1355a62828"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a224005037387484dfa510a1355a62828">&#9670;&#160;</a></span>neorv32_onewire_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_onewire_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>t_base</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, configure and enable ONEWIRE interface controller.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">t_base</td><td>Base tick time in ns. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if configuration failed, otherwise the actual t_base time in ns is returned. </dd></dl> + +</div> +</div> +<a id="a49d0a2a386f129fd2f4fed880bba31d4" name="a49d0a2a386f129fd2f4fed880bba31d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a49d0a2a386f129fd2f4fed880bba31d4">&#9670;&#160;</a></span>neorv32_onewire_write_bit()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_write_bit </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>bit</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate single-bit write.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">bit</td><td>Bit to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a6f7b6690a2437e0b574a8a9a23dc0eaa" name="a6f7b6690a2437e0b574a8a9a23dc0eaa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6f7b6690a2437e0b574a8a9a23dc0eaa">&#9670;&#160;</a></span>neorv32_onewire_write_bit_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_write_bit_blocking </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>bit</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write single bit.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">bit</td><td>Bit to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a23b96b68c3214b188525eb102cafb620" name="a23b96b68c3214b188525eb102cafb620"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a23b96b68c3214b188525eb102cafb620">&#9670;&#160;</a></span>neorv32_onewire_write_byte()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_write_byte </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>byte</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initiate write byte.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Byte to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac78557c77482b59394677f42fda4fdf1" name="ac78557c77482b59394677f42fda4fdf1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac78557c77482b59394677f42fda4fdf1">&#9670;&#160;</a></span>neorv32_onewire_write_byte_blocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_onewire_write_byte_blocking </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>byte</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Write byte.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function is blocking!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">byte</td><td>Byte to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" 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href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_onewire.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__onewire_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_onewire_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_onewire_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__onewire__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__onewire__t.html#a310df3bab43e4438417b2ff948f4712a"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__onewire__t.html#a310df3bab43e4438417b2ff948f4712a">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__onewire__t.html#a2c04aa736b901940ed65b96202c8af7a"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__onewire__t.html#a2c04aa736b901940ed65b96202c8af7a">DATA</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__onewire__t.html">neorv32_onewire_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#a6f119e35d7ac01f110987508ff3becc9"> 35</a></span><span class="preprocessor">#define NEORV32_ONEWIRE ((neorv32_onewire_t*) (NEORV32_ONEWIRE_BASE))</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="foldopen" id="foldopen00038" data-start="{" data-end="};"> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831"> 38</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831">NEORV32_ONEWIRE_CTRL_enum</a> {</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831ab87882c202f80185278c69e482f147da"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831ab87882c202f80185278c69e482f147da">ONEWIRE_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831abfed6417c3abd7ef94cd18a3b32c4393"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831abfed6417c3abd7ef94cd18a3b32c4393">ONEWIRE_CTRL_PRSC0</a> = 1, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aee1e24261e263c70bf2e36dcafc9dc74"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aee1e24261e263c70bf2e36dcafc9dc74">ONEWIRE_CTRL_PRSC1</a> = 2, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831acdfca08f34d7379aaf8505ba3425c6f5"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831acdfca08f34d7379aaf8505ba3425c6f5">ONEWIRE_CTRL_CLKDIV0</a> = 3, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831afa1476a5e04eb4eabf4d7a595eca2df9"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831afa1476a5e04eb4eabf4d7a595eca2df9">ONEWIRE_CTRL_CLKDIV1</a> = 4, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aec9f056072e1db747e74a5c695d2a1df"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aec9f056072e1db747e74a5c695d2a1df">ONEWIRE_CTRL_CLKDIV2</a> = 5, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831ab8600bd09d74e39869259881b84ebfbf"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831ab8600bd09d74e39869259881b84ebfbf">ONEWIRE_CTRL_CLKDIV3</a> = 6, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a32af8c86e7166e02e801727bd261c179"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a32af8c86e7166e02e801727bd261c179">ONEWIRE_CTRL_CLKDIV4</a> = 7, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a789d65fd9b0ab17bffd0d6de9d2e132a"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a789d65fd9b0ab17bffd0d6de9d2e132a">ONEWIRE_CTRL_CLKDIV5</a> = 8, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a27f040454bebc6218b490f7160ea2312"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a27f040454bebc6218b490f7160ea2312">ONEWIRE_CTRL_CLKDIV6</a> = 9, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a8b19096f72ef96a7597fda9be625ed40"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a8b19096f72ef96a7597fda9be625ed40">ONEWIRE_CTRL_CLKDIV7</a> = 10, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a98624ec944e0413a208cdf54bbbf4c75"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a98624ec944e0413a208cdf54bbbf4c75">ONEWIRE_CTRL_TRIG_RST</a> = 11, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a7ecbccef9e77e68caf22ed2c416e1f77"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a7ecbccef9e77e68caf22ed2c416e1f77">ONEWIRE_CTRL_TRIG_BIT</a> = 12, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831acfd8a56f668ca55dbbaa1714b1235dfe"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831acfd8a56f668ca55dbbaa1714b1235dfe">ONEWIRE_CTRL_TRIG_BYTE</a> = 13, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831af992c94d0b9a7b7b92a5a23366b9a8c6"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831af992c94d0b9a7b7b92a5a23366b9a8c6">ONEWIRE_CTRL_SENSE</a> = 29, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a92e1ff9fa10319d64c8d2c6a6d61b37e"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a92e1ff9fa10319d64c8d2c6a6d61b37e">ONEWIRE_CTRL_PRESENCE</a> = 30, </div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aac8933755e80d72e1e9c293198d831b9"> 56</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aac8933755e80d72e1e9c293198d831b9">ONEWIRE_CTRL_BUSY</a> = 31, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span>};</div> +</div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span> </div> +<div class="foldopen" id="foldopen00060" data-start="{" data-end="};"> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368"> 60</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368">NEORV32_ONEWIRE_DATA_enum</a> {</div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368a6ad35475e3f80a8c68ce0caa9c3754a5"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368a6ad35475e3f80a8c68ce0caa9c3754a5">ONEWIRE_DATA_LSB</a> = 0, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> <a class="code hl_enumvalue" href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368af967429634efb019ada46bf75f373aa3">ONEWIRE_DATA_MSB</a> = 7 </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368af967429634efb019ada46bf75f373aa3"> 63</a></span>};</div> +</div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a865e5c381fd3c27c6981a589a5124d1e">neorv32_onewire_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a224005037387484dfa510a1355a62828">neorv32_onewire_setup</a>(uint32_t t_base);</div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#ae6fe766e7decf18869cfb86bba741ca4">neorv32_onewire_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a7e329eeb1cd98301a53b271a6a102385">neorv32_onewire_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a122531c7154126858c46d89e003d838d">neorv32_onewire_sense</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span> </div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a01b6236b89c045ddbd58398361c6ee0a">neorv32_onewire_busy</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a3072f7167831edc95dee44ecfef6a0d4">neorv32_onewire_reset</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a43eb8a08eeaa83e3d7e9aa5058a4269f">neorv32_onewire_reset_get_presence</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#aace8398062b759256a516e6245aced83">neorv32_onewire_read_bit</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span>uint8_t <a class="code hl_function" href="neorv32__onewire_8h.html#aa4a19d2d8dc3b3401307615aec201190">neorv32_onewire_read_bit_get</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a49d0a2a386f129fd2f4fed880bba31d4">neorv32_onewire_write_bit</a>(uint8_t bit);</div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a01ddba7a9148be542b5c52e39e6f46d6">neorv32_onewire_read_byte</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span>uint8_t <a class="code hl_function" href="neorv32__onewire_8h.html#a4c7eec15c095c97c939163f631f51dab">neorv32_onewire_read_byte_get</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a23b96b68c3214b188525eb102cafb620">neorv32_onewire_write_byte</a>(uint8_t <span class="keywordtype">byte</span>);</div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span> </div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__onewire_8h.html#af8ca6be495176797b7da3857e2f794f9">neorv32_onewire_reset_blocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span>uint8_t <a class="code hl_function" href="neorv32__onewire_8h.html#ace8b7cf697b068b6b51676d84dec5960">neorv32_onewire_read_bit_blocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#a6f7b6690a2437e0b574a8a9a23dc0eaa">neorv32_onewire_write_bit_blocking</a>(uint8_t bit);</div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span>uint8_t <a class="code hl_function" href="neorv32__onewire_8h.html#a7510e65a26aeefb40e994fd00667537e">neorv32_onewire_read_byte_blocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__onewire_8h.html#ac78557c77482b59394677f42fda4fdf1">neorv32_onewire_write_byte_blocking</a>(uint8_t <span class="keywordtype">byte</span>);</div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_onewire_h</span></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a01b6236b89c045ddbd58398361c6ee0a"><div class="ttname"><a href="neorv32__onewire_8h.html#a01b6236b89c045ddbd58398361c6ee0a">neorv32_onewire_busy</a></div><div class="ttdeci">int neorv32_onewire_busy(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:130</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a01ddba7a9148be542b5c52e39e6f46d6"><div class="ttname"><a href="neorv32__onewire_8h.html#a01ddba7a9148be542b5c52e39e6f46d6">neorv32_onewire_read_byte</a></div><div class="ttdeci">void neorv32_onewire_read_byte(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:234</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a122531c7154126858c46d89e003d838d"><div class="ttname"><a href="neorv32__onewire_8h.html#a122531c7154126858c46d89e003d838d">neorv32_onewire_sense</a></div><div class="ttdeci">int neorv32_onewire_sense(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:107</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a224005037387484dfa510a1355a62828"><div class="ttname"><a href="neorv32__onewire_8h.html#a224005037387484dfa510a1355a62828">neorv32_onewire_setup</a></div><div class="ttdeci">int neorv32_onewire_setup(uint32_t t_base)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:43</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a23b96b68c3214b188525eb102cafb620"><div class="ttname"><a href="neorv32__onewire_8h.html#a23b96b68c3214b188525eb102cafb620">neorv32_onewire_write_byte</a></div><div class="ttdeci">void neorv32_onewire_write_byte(uint8_t byte)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:265</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a3072f7167831edc95dee44ecfef6a0d4"><div class="ttname"><a href="neorv32__onewire_8h.html#a3072f7167831edc95dee44ecfef6a0d4">neorv32_onewire_reset</a></div><div class="ttdeci">void neorv32_onewire_reset(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:147</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a43eb8a08eeaa83e3d7e9aa5058a4269f"><div class="ttname"><a href="neorv32__onewire_8h.html#a43eb8a08eeaa83e3d7e9aa5058a4269f">neorv32_onewire_reset_get_presence</a></div><div class="ttdeci">int neorv32_onewire_reset_get_presence(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:161</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a49d0a2a386f129fd2f4fed880bba31d4"><div class="ttname"><a href="neorv32__onewire_8h.html#a49d0a2a386f129fd2f4fed880bba31d4">neorv32_onewire_write_bit</a></div><div class="ttdeci">void neorv32_onewire_write_bit(uint8_t bit)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:214</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a4c7eec15c095c97c939163f631f51dab"><div class="ttname"><a href="neorv32__onewire_8h.html#a4c7eec15c095c97c939163f631f51dab">neorv32_onewire_read_byte_get</a></div><div class="ttdeci">uint8_t neorv32_onewire_read_byte_get(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:251</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a6f7b6690a2437e0b574a8a9a23dc0eaa"><div class="ttname"><a href="neorv32__onewire_8h.html#a6f7b6690a2437e0b574a8a9a23dc0eaa">neorv32_onewire_write_bit_blocking</a></div><div class="ttdeci">void neorv32_onewire_write_bit_blocking(uint8_t bit)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:327</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a7510e65a26aeefb40e994fd00667537e"><div class="ttname"><a href="neorv32__onewire_8h.html#a7510e65a26aeefb40e994fd00667537e">neorv32_onewire_read_byte_blocking</a></div><div class="ttdeci">uint8_t neorv32_onewire_read_byte_blocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:344</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a7e329eeb1cd98301a53b271a6a102385"><div class="ttname"><a href="neorv32__onewire_8h.html#a7e329eeb1cd98301a53b271a6a102385">neorv32_onewire_disable</a></div><div class="ttdeci">void neorv32_onewire_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:96</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_a865e5c381fd3c27c6981a589a5124d1e"><div class="ttname"><a href="neorv32__onewire_8h.html#a865e5c381fd3c27c6981a589a5124d1e">neorv32_onewire_available</a></div><div class="ttdeci">int neorv32_onewire_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:26</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_aa4a19d2d8dc3b3401307615aec201190"><div class="ttname"><a href="neorv32__onewire_8h.html#aa4a19d2d8dc3b3401307615aec201190">neorv32_onewire_read_bit_get</a></div><div class="ttdeci">uint8_t neorv32_onewire_read_bit_get(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:195</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_aace8398062b759256a516e6245aced83"><div class="ttname"><a href="neorv32__onewire_8h.html#aace8398062b759256a516e6245aced83">neorv32_onewire_read_bit</a></div><div class="ttdeci">void neorv32_onewire_read_bit(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:178</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ac78557c77482b59394677f42fda4fdf1"><div class="ttname"><a href="neorv32__onewire_8h.html#ac78557c77482b59394677f42fda4fdf1">neorv32_onewire_write_byte_blocking</a></div><div class="ttdeci">void neorv32_onewire_write_byte_blocking(uint8_t byte)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:364</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ace8b7cf697b068b6b51676d84dec5960"><div class="ttname"><a href="neorv32__onewire_8h.html#ace8b7cf697b068b6b51676d84dec5960">neorv32_onewire_read_bit_blocking</a></div><div class="ttdeci">uint8_t neorv32_onewire_read_bit_blocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:307</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831">NEORV32_ONEWIRE_CTRL_enum</a></div><div class="ttdeci">NEORV32_ONEWIRE_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:38</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831a27f040454bebc6218b490f7160ea2312"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a27f040454bebc6218b490f7160ea2312">ONEWIRE_CTRL_CLKDIV6</a></div><div class="ttdeci">@ ONEWIRE_CTRL_CLKDIV6</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:48</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831a32af8c86e7166e02e801727bd261c179"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a32af8c86e7166e02e801727bd261c179">ONEWIRE_CTRL_CLKDIV4</a></div><div class="ttdeci">@ ONEWIRE_CTRL_CLKDIV4</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:46</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831a789d65fd9b0ab17bffd0d6de9d2e132a"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a789d65fd9b0ab17bffd0d6de9d2e132a">ONEWIRE_CTRL_CLKDIV5</a></div><div class="ttdeci">@ ONEWIRE_CTRL_CLKDIV5</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:47</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831a7ecbccef9e77e68caf22ed2c416e1f77"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a7ecbccef9e77e68caf22ed2c416e1f77">ONEWIRE_CTRL_TRIG_BIT</a></div><div class="ttdeci">@ ONEWIRE_CTRL_TRIG_BIT</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:51</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831a8b19096f72ef96a7597fda9be625ed40"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a8b19096f72ef96a7597fda9be625ed40">ONEWIRE_CTRL_CLKDIV7</a></div><div class="ttdeci">@ ONEWIRE_CTRL_CLKDIV7</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:49</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831a92e1ff9fa10319d64c8d2c6a6d61b37e"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a92e1ff9fa10319d64c8d2c6a6d61b37e">ONEWIRE_CTRL_PRESENCE</a></div><div class="ttdeci">@ ONEWIRE_CTRL_PRESENCE</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:55</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831a98624ec944e0413a208cdf54bbbf4c75"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831a98624ec944e0413a208cdf54bbbf4c75">ONEWIRE_CTRL_TRIG_RST</a></div><div class="ttdeci">@ ONEWIRE_CTRL_TRIG_RST</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:50</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831aac8933755e80d72e1e9c293198d831b9"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aac8933755e80d72e1e9c293198d831b9">ONEWIRE_CTRL_BUSY</a></div><div class="ttdeci">@ ONEWIRE_CTRL_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:56</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831ab8600bd09d74e39869259881b84ebfbf"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831ab8600bd09d74e39869259881b84ebfbf">ONEWIRE_CTRL_CLKDIV3</a></div><div class="ttdeci">@ ONEWIRE_CTRL_CLKDIV3</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:45</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831ab87882c202f80185278c69e482f147da"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831ab87882c202f80185278c69e482f147da">ONEWIRE_CTRL_EN</a></div><div class="ttdeci">@ ONEWIRE_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:39</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831abfed6417c3abd7ef94cd18a3b32c4393"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831abfed6417c3abd7ef94cd18a3b32c4393">ONEWIRE_CTRL_PRSC0</a></div><div class="ttdeci">@ ONEWIRE_CTRL_PRSC0</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:40</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831acdfca08f34d7379aaf8505ba3425c6f5"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831acdfca08f34d7379aaf8505ba3425c6f5">ONEWIRE_CTRL_CLKDIV0</a></div><div class="ttdeci">@ ONEWIRE_CTRL_CLKDIV0</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:42</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831acfd8a56f668ca55dbbaa1714b1235dfe"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831acfd8a56f668ca55dbbaa1714b1235dfe">ONEWIRE_CTRL_TRIG_BYTE</a></div><div class="ttdeci">@ ONEWIRE_CTRL_TRIG_BYTE</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:52</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831aec9f056072e1db747e74a5c695d2a1df"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aec9f056072e1db747e74a5c695d2a1df">ONEWIRE_CTRL_CLKDIV2</a></div><div class="ttdeci">@ ONEWIRE_CTRL_CLKDIV2</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:44</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831aee1e24261e263c70bf2e36dcafc9dc74"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831aee1e24261e263c70bf2e36dcafc9dc74">ONEWIRE_CTRL_PRSC1</a></div><div class="ttdeci">@ ONEWIRE_CTRL_PRSC1</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:41</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831af992c94d0b9a7b7b92a5a23366b9a8c6"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831af992c94d0b9a7b7b92a5a23366b9a8c6">ONEWIRE_CTRL_SENSE</a></div><div class="ttdeci">@ ONEWIRE_CTRL_SENSE</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:54</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ade1a01f533843880868ec7496d116831afa1476a5e04eb4eabf4d7a595eca2df9"><div class="ttname"><a href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831afa1476a5e04eb4eabf4d7a595eca2df9">ONEWIRE_CTRL_CLKDIV1</a></div><div class="ttdeci">@ ONEWIRE_CTRL_CLKDIV1</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:43</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ae6fe766e7decf18869cfb86bba741ca4"><div class="ttname"><a href="neorv32__onewire_8h.html#ae6fe766e7decf18869cfb86bba741ca4">neorv32_onewire_enable</a></div><div class="ttdeci">void neorv32_onewire_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:87</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ae770490afa8662fb8577065531d51368"><div class="ttname"><a href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368">NEORV32_ONEWIRE_DATA_enum</a></div><div class="ttdeci">NEORV32_ONEWIRE_DATA_enum</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:60</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ae770490afa8662fb8577065531d51368a6ad35475e3f80a8c68ce0caa9c3754a5"><div class="ttname"><a href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368a6ad35475e3f80a8c68ce0caa9c3754a5">ONEWIRE_DATA_LSB</a></div><div class="ttdeci">@ ONEWIRE_DATA_LSB</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:61</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_ae770490afa8662fb8577065531d51368af967429634efb019ada46bf75f373aa3"><div class="ttname"><a href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368af967429634efb019ada46bf75f373aa3">ONEWIRE_DATA_MSB</a></div><div class="ttdeci">@ ONEWIRE_DATA_MSB</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:62</div></div> +<div class="ttc" id="aneorv32__onewire_8h_html_af8ca6be495176797b7da3857e2f794f9"><div class="ttname"><a href="neorv32__onewire_8h.html#af8ca6be495176797b7da3857e2f794f9">neorv32_onewire_reset_blocking</a></div><div class="ttdeci">int neorv32_onewire_reset_blocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:287</div></div> +<div class="ttc" id="astructneorv32__onewire__t_html"><div class="ttname"><a href="structneorv32__onewire__t.html">neorv32_onewire_t</a></div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:29</div></div> +<div class="ttc" id="astructneorv32__onewire__t_html_a2c04aa736b901940ed65b96202c8af7a"><div class="ttname"><a href="structneorv32__onewire__t.html#a2c04aa736b901940ed65b96202c8af7a">neorv32_onewire_t::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:31</div></div> +<div class="ttc" id="astructneorv32__onewire__t_html_a310df3bab43e4438417b2ff948f4712a"><div class="ttname"><a href="structneorv32__onewire__t.html#a310df3bab43e4438417b2ff948f4712a">neorv32_onewire_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_onewire.h:30</div></div> +</div><!-- fragment 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_pwm.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Pulse-Width Modulation Controller (PWM) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:afb12c860b2f7fa6cd1e069ea540da41c" id="r_afb12c860b2f7fa6cd1e069ea540da41c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afb12c860b2f7fa6cd1e069ea540da41c">neorv32_pwm_available</a> (void)</td></tr> +<tr class="separator:afb12c860b2f7fa6cd1e069ea540da41c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a43d8a47dc79ebac24c8a7d2d8247d2a5" id="r_a43d8a47dc79ebac24c8a7d2d8247d2a5"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a43d8a47dc79ebac24c8a7d2d8247d2a5">neorv32_pmw_get_num_channels</a> (void)</td></tr> +<tr class="separator:a43d8a47dc79ebac24c8a7d2d8247d2a5"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af00e67388ef9186e051e518883ad9a40" id="r_af00e67388ef9186e051e518883ad9a40"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af00e67388ef9186e051e518883ad9a40">neorv32_pwm_ch_enable</a> (int channel)</td></tr> +<tr class="separator:af00e67388ef9186e051e518883ad9a40"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7bc39afa807b7c2e06d6fd8b4dc7506c" id="r_a7bc39afa807b7c2e06d6fd8b4dc7506c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7bc39afa807b7c2e06d6fd8b4dc7506c">neorv32_pwm_ch_disable</a> (int channel)</td></tr> +<tr class="separator:a7bc39afa807b7c2e06d6fd8b4dc7506c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a784672443179a7c1e604f23854e001f4" id="r_a784672443179a7c1e604f23854e001f4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a784672443179a7c1e604f23854e001f4">neorv32_pwm_ch_set_clock</a> (int channel, int prsc, int cdiv)</td></tr> +<tr class="separator:a784672443179a7c1e604f23854e001f4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a518bad33405039fadd668d16276acb14" id="r_a518bad33405039fadd668d16276acb14"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a518bad33405039fadd668d16276acb14">neorv32_pwm_ch_set_duty</a> (int channel, int duty)</td></tr> +<tr class="separator:a518bad33405039fadd668d16276acb14"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Pulse-Width Modulation Controller (PWM) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the PWM unit was synthesized (IO_PWM_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a43d8a47dc79ebac24c8a7d2d8247d2a5" name="a43d8a47dc79ebac24c8a7d2d8247d2a5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a43d8a47dc79ebac24c8a7d2d8247d2a5">&#9670;&#160;</a></span>neorv32_pmw_get_num_channels()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_pmw_get_num_channels </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get number of implemented PWM channels. </p><dl class="section warning"><dt>Warning</dt><dd>This function will override all channel configuration registers.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Number of implemented PWM channels. </dd></dl> + +</div> +</div> +<a id="afb12c860b2f7fa6cd1e069ea540da41c" name="afb12c860b2f7fa6cd1e069ea540da41c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afb12c860b2f7fa6cd1e069ea540da41c">&#9670;&#160;</a></span>neorv32_pwm_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_pwm_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if PWM unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if PWM was not synthesized, 1 if PWM is available. </dd></dl> + +</div> +</div> +<a id="a7bc39afa807b7c2e06d6fd8b4dc7506c" name="a7bc39afa807b7c2e06d6fd8b4dc7506c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7bc39afa807b7c2e06d6fd8b4dc7506c">&#9670;&#160;</a></span>neorv32_pwm_ch_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_pwm_ch_disable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable PWM channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>Channel select (0..15). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="af00e67388ef9186e051e518883ad9a40" name="af00e67388ef9186e051e518883ad9a40"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af00e67388ef9186e051e518883ad9a40">&#9670;&#160;</a></span>neorv32_pwm_ch_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_pwm_ch_enable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable PWM channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>Channel select (0..15). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a784672443179a7c1e604f23854e001f4" name="a784672443179a7c1e604f23854e001f4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a784672443179a7c1e604f23854e001f4">&#9670;&#160;</a></span>neorv32_pwm_ch_set_clock()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_pwm_ch_set_clock </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cdiv</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set PWM channel's clock configuration.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>Channel select (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Coarse clock prescaler select (3-bit, LSB-aligned). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cdiv</td><td>Fine clock divider value (10-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a518bad33405039fadd668d16276acb14" name="a518bad33405039fadd668d16276acb14"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a518bad33405039fadd668d16276acb14">&#9670;&#160;</a></span>neorv32_pwm_ch_set_duty()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_pwm_ch_set_duty </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>duty</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set PWM channel's duty cycle.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>Channel select (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">duty</td><td>Duty cycle (8-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__pwm_8h.html b/sw/neorv32__pwm_8h.html new file mode 100644 index 000000000..bfd9fec58 --- /dev/null +++ b/sw/neorv32__pwm_8h.html @@ -0,0 +1,352 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 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driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__pwm_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__pwm__t.html">neorv32_pwm_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:afb12c860b2f7fa6cd1e069ea540da41c" id="r_afb12c860b2f7fa6cd1e069ea540da41c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afb12c860b2f7fa6cd1e069ea540da41c">neorv32_pwm_available</a> (void)</td></tr> +<tr class="separator:afb12c860b2f7fa6cd1e069ea540da41c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a43d8a47dc79ebac24c8a7d2d8247d2a5" id="r_a43d8a47dc79ebac24c8a7d2d8247d2a5"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a43d8a47dc79ebac24c8a7d2d8247d2a5">neorv32_pmw_get_num_channels</a> (void)</td></tr> +<tr class="separator:a43d8a47dc79ebac24c8a7d2d8247d2a5"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af00e67388ef9186e051e518883ad9a40" id="r_af00e67388ef9186e051e518883ad9a40"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af00e67388ef9186e051e518883ad9a40">neorv32_pwm_ch_enable</a> (int channel)</td></tr> +<tr class="separator:af00e67388ef9186e051e518883ad9a40"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7bc39afa807b7c2e06d6fd8b4dc7506c" id="r_a7bc39afa807b7c2e06d6fd8b4dc7506c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7bc39afa807b7c2e06d6fd8b4dc7506c">neorv32_pwm_ch_disable</a> (int channel)</td></tr> +<tr class="separator:a7bc39afa807b7c2e06d6fd8b4dc7506c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a784672443179a7c1e604f23854e001f4" id="r_a784672443179a7c1e604f23854e001f4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a784672443179a7c1e604f23854e001f4">neorv32_pwm_ch_set_clock</a> (int channel, int prsc, int cdiv)</td></tr> +<tr class="separator:a784672443179a7c1e604f23854e001f4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a518bad33405039fadd668d16276acb14" id="r_a518bad33405039fadd668d16276acb14"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a518bad33405039fadd668d16276acb14">neorv32_pwm_ch_set_duty</a> (int channel, int duty)</td></tr> +<tr class="separator:a518bad33405039fadd668d16276acb14"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Pulse Width Modulation Controller (PWM)</h2></td></tr> +<tr class="memitem:ad4cb534c29e26fa56c10bef7afab8f51" id="r_ad4cb534c29e26fa56c10bef7afab8f51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad4cb534c29e26fa56c10bef7afab8f51">NEORV32_PWM</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__pwm__t.html">neorv32_pwm_t</a>*) (<a class="el" href="neorv32_8h.html#afef7a6b121a788560b29e2ee2a58c725">NEORV32_PWM_BASE</a>))</td></tr> +<tr class="separator:ad4cb534c29e26fa56c10bef7afab8f51"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acbcb6d5d80029fb404efcd7123ff5175" id="r_acbcb6d5d80029fb404efcd7123ff5175"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175">CHANNEL_CFG_enum</a> { <br /> +&#160;&#160;<a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175a9aa8249716b15c92368c93b36bf7db43">PWM_CFG_DUTY_LSB</a> = 0 +, <a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175af5d9dcb5740c39cfe8f9bfb5c1b66341">PWM_CFG_DUTY_MSB</a> = 7 +, <a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175acc7e31e4b3f0e7ab0a0306a107109b4f">PWM_CFG_CDIV_LSB</a> = 8 +, <a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175a6f741e102b7e15e946714360e81f4bb2">PWM_CFG_CDIV_MSB</a> = 17 +, <br /> +&#160;&#160;<a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175aefe2211fe39acffb40ca738639b3d5f5">PWM_CFG_PRSC_LSB</a> = 28 +, <a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175aa100b419699cd3c6787a9168a3ffec3d">PWM_CFG_PRSC_MSB</a> = 30 +, <a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175a2b766bfa9653705025b745e0809c432a">PWM_CFG_EN</a> = 31 +<br /> + }</td></tr> +<tr class="separator:acbcb6d5d80029fb404efcd7123ff5175"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Pulse-Width Modulation Controller (PWM) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the PWM unit was synthesized (IO_PWM_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad4cb534c29e26fa56c10bef7afab8f51" name="ad4cb534c29e26fa56c10bef7afab8f51"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad4cb534c29e26fa56c10bef7afab8f51">&#9670;&#160;</a></span>NEORV32_PWM</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_PWM&#160;&#160;&#160;((<a class="el" href="structneorv32__pwm__t.html">neorv32_pwm_t</a>*) (<a class="el" href="neorv32_8h.html#afef7a6b121a788560b29e2ee2a58c725">NEORV32_PWM_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>PWM module hardware access (<a class="el" href="structneorv32__pwm__t.html">neorv32_pwm_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="acbcb6d5d80029fb404efcd7123ff5175" name="acbcb6d5d80029fb404efcd7123ff5175"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acbcb6d5d80029fb404efcd7123ff5175">&#9670;&#160;</a></span>CHANNEL_CFG_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#acbcb6d5d80029fb404efcd7123ff5175">CHANNEL_CFG_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>PWM channel configuration bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="acbcb6d5d80029fb404efcd7123ff5175a9aa8249716b15c92368c93b36bf7db43" name="acbcb6d5d80029fb404efcd7123ff5175a9aa8249716b15c92368c93b36bf7db43"></a>PWM_CFG_DUTY_LSB&#160;</td><td class="fielddoc"><p>PWM configuration register(0) (r/w): Duty cycle (8-bit), LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="acbcb6d5d80029fb404efcd7123ff5175af5d9dcb5740c39cfe8f9bfb5c1b66341" name="acbcb6d5d80029fb404efcd7123ff5175af5d9dcb5740c39cfe8f9bfb5c1b66341"></a>PWM_CFG_DUTY_MSB&#160;</td><td class="fielddoc"><p>PWM configuration register(7) (r/w): Duty cycle (8-bit), MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="acbcb6d5d80029fb404efcd7123ff5175acc7e31e4b3f0e7ab0a0306a107109b4f" name="acbcb6d5d80029fb404efcd7123ff5175acc7e31e4b3f0e7ab0a0306a107109b4f"></a>PWM_CFG_CDIV_LSB&#160;</td><td class="fielddoc"><p>PWM configuration register(8) (r/w): Clock divider (10-bit), LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="acbcb6d5d80029fb404efcd7123ff5175a6f741e102b7e15e946714360e81f4bb2" name="acbcb6d5d80029fb404efcd7123ff5175a6f741e102b7e15e946714360e81f4bb2"></a>PWM_CFG_CDIV_MSB&#160;</td><td class="fielddoc"><p>PWM configuration register(17) (r/w): Clock divider (10-bit), MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="acbcb6d5d80029fb404efcd7123ff5175aefe2211fe39acffb40ca738639b3d5f5" name="acbcb6d5d80029fb404efcd7123ff5175aefe2211fe39acffb40ca738639b3d5f5"></a>PWM_CFG_PRSC_LSB&#160;</td><td class="fielddoc"><p>PWM configuration register(28) (r/w): Clock prescaler select (3-bit), LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="acbcb6d5d80029fb404efcd7123ff5175aa100b419699cd3c6787a9168a3ffec3d" name="acbcb6d5d80029fb404efcd7123ff5175aa100b419699cd3c6787a9168a3ffec3d"></a>PWM_CFG_PRSC_MSB&#160;</td><td class="fielddoc"><p>PWM configuration register(30) (r/w): Clock prescaler select (3-bit), MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="acbcb6d5d80029fb404efcd7123ff5175a2b766bfa9653705025b745e0809c432a" name="acbcb6d5d80029fb404efcd7123ff5175a2b766bfa9653705025b745e0809c432a"></a>PWM_CFG_EN&#160;</td><td class="fielddoc"><p>PWM configuration register(31) (r/w): channel enable </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a43d8a47dc79ebac24c8a7d2d8247d2a5" name="a43d8a47dc79ebac24c8a7d2d8247d2a5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a43d8a47dc79ebac24c8a7d2d8247d2a5">&#9670;&#160;</a></span>neorv32_pmw_get_num_channels()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_pmw_get_num_channels </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get number of implemented PWM channels. </p><dl class="section warning"><dt>Warning</dt><dd>This function will override all channel configuration registers.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Number of implemented PWM channels. </dd></dl> + +</div> +</div> +<a id="afb12c860b2f7fa6cd1e069ea540da41c" name="afb12c860b2f7fa6cd1e069ea540da41c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afb12c860b2f7fa6cd1e069ea540da41c">&#9670;&#160;</a></span>neorv32_pwm_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_pwm_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if PWM unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if PWM was not synthesized, 1 if PWM is available. </dd></dl> + +</div> +</div> +<a id="a7bc39afa807b7c2e06d6fd8b4dc7506c" name="a7bc39afa807b7c2e06d6fd8b4dc7506c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7bc39afa807b7c2e06d6fd8b4dc7506c">&#9670;&#160;</a></span>neorv32_pwm_ch_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_pwm_ch_disable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable PWM channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>Channel select (0..15). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="af00e67388ef9186e051e518883ad9a40" name="af00e67388ef9186e051e518883ad9a40"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af00e67388ef9186e051e518883ad9a40">&#9670;&#160;</a></span>neorv32_pwm_ch_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_pwm_ch_enable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable PWM channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>Channel select (0..15). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a784672443179a7c1e604f23854e001f4" name="a784672443179a7c1e604f23854e001f4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a784672443179a7c1e604f23854e001f4">&#9670;&#160;</a></span>neorv32_pwm_ch_set_clock()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_pwm_ch_set_clock </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cdiv</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set PWM channel's clock configuration.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>Channel select (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Coarse clock prescaler select (3-bit, LSB-aligned). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cdiv</td><td>Fine clock divider value (10-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a518bad33405039fadd668d16276acb14" name="a518bad33405039fadd668d16276acb14"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a518bad33405039fadd668d16276acb14">&#9670;&#160;</a></span>neorv32_pwm_ch_set_duty()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_pwm_ch_set_duty </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>duty</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set PWM channel's duty cycle.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>Channel select (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">duty</td><td>Duty cycle (8-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__pwm_8h_source.html b/sw/neorv32__pwm_8h_source.html new file mode 100644 index 000000000..2d9e8023d --- /dev/null +++ b/sw/neorv32__pwm_8h_source.html @@ -0,0 +1,160 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_pwm.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_pwm_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_pwm_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__pwm__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__pwm__t.html#a5df0cf6c7c250365db3ada8db7cc19e9"> 30</a></span> uint32_t CHANNEL_CFG[16]; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span>} <a class="code hl_struct" href="structneorv32__pwm__t.html">neorv32_pwm_t</a>;</div> +</div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#ad4cb534c29e26fa56c10bef7afab8f51"> 34</a></span><span class="preprocessor">#define NEORV32_PWM ((neorv32_pwm_t*) (NEORV32_PWM_BASE))</span></div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div> +<div class="foldopen" id="foldopen00037" data-start="{" data-end="};"> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175"> 37</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175">CHANNEL_CFG_enum</a> {</div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a9aa8249716b15c92368c93b36bf7db43"> 38</a></span> <a class="code hl_enumvalue" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a9aa8249716b15c92368c93b36bf7db43">PWM_CFG_DUTY_LSB</a> = 0, </div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175af5d9dcb5740c39cfe8f9bfb5c1b66341"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175af5d9dcb5740c39cfe8f9bfb5c1b66341">PWM_CFG_DUTY_MSB</a> = 7, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175acc7e31e4b3f0e7ab0a0306a107109b4f"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175acc7e31e4b3f0e7ab0a0306a107109b4f">PWM_CFG_CDIV_LSB</a> = 8, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a6f741e102b7e15e946714360e81f4bb2"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a6f741e102b7e15e946714360e81f4bb2">PWM_CFG_CDIV_MSB</a> = 17, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175aefe2211fe39acffb40ca738639b3d5f5"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175aefe2211fe39acffb40ca738639b3d5f5">PWM_CFG_PRSC_LSB</a> = 28, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175aa100b419699cd3c6787a9168a3ffec3d"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175aa100b419699cd3c6787a9168a3ffec3d">PWM_CFG_PRSC_MSB</a> = 30, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span> <a class="code hl_enumvalue" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a2b766bfa9653705025b745e0809c432a">PWM_CFG_EN</a> = 31 </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a2b766bfa9653705025b745e0809c432a"> 46</a></span>};</div> +</div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__pwm_8h.html#afb12c860b2f7fa6cd1e069ea540da41c">neorv32_pwm_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__pwm_8h.html#a43d8a47dc79ebac24c8a7d2d8247d2a5">neorv32_pmw_get_num_channels</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__pwm_8h.html#af00e67388ef9186e051e518883ad9a40">neorv32_pwm_ch_enable</a>(<span class="keywordtype">int</span> channel);</div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__pwm_8h.html#a7bc39afa807b7c2e06d6fd8b4dc7506c">neorv32_pwm_ch_disable</a>(<span class="keywordtype">int</span> channel);</div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__pwm_8h.html#a784672443179a7c1e604f23854e001f4">neorv32_pwm_ch_set_clock</a>(<span class="keywordtype">int</span> channel, <span class="keywordtype">int</span> prsc, <span class="keywordtype">int</span> cdiv);</div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__pwm_8h.html#a518bad33405039fadd668d16276acb14">neorv32_pwm_ch_set_duty</a>(<span class="keywordtype">int</span> channel, <span class="keywordtype">int</span> duty);</div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_pwm_h</span></div> +<div class="ttc" id="aneorv32__pwm_8h_html_a43d8a47dc79ebac24c8a7d2d8247d2a5"><div class="ttname"><a href="neorv32__pwm_8h.html#a43d8a47dc79ebac24c8a7d2d8247d2a5">neorv32_pmw_get_num_channels</a></div><div class="ttdeci">int neorv32_pmw_get_num_channels(void)</div><div class="ttdef"><b>Definition</b> neorv32_pwm.c:43</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_a518bad33405039fadd668d16276acb14"><div class="ttname"><a href="neorv32__pwm_8h.html#a518bad33405039fadd668d16276acb14">neorv32_pwm_ch_set_duty</a></div><div class="ttdeci">void neorv32_pwm_ch_set_duty(int channel, int duty)</div><div class="ttdef"><b>Definition</b> neorv32_pwm.c:108</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_a784672443179a7c1e604f23854e001f4"><div class="ttname"><a href="neorv32__pwm_8h.html#a784672443179a7c1e604f23854e001f4">neorv32_pwm_ch_set_clock</a></div><div class="ttdeci">void neorv32_pwm_ch_set_clock(int channel, int prsc, int cdiv)</div><div class="ttdef"><b>Definition</b> neorv32_pwm.c:90</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_a7bc39afa807b7c2e06d6fd8b4dc7506c"><div class="ttname"><a href="neorv32__pwm_8h.html#a7bc39afa807b7c2e06d6fd8b4dc7506c">neorv32_pwm_ch_disable</a></div><div class="ttdeci">void neorv32_pwm_ch_disable(int channel)</div><div class="ttdef"><b>Definition</b> neorv32_pwm.c:75</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_acbcb6d5d80029fb404efcd7123ff5175"><div class="ttname"><a href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175">CHANNEL_CFG_enum</a></div><div class="ttdeci">CHANNEL_CFG_enum</div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:37</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_acbcb6d5d80029fb404efcd7123ff5175a2b766bfa9653705025b745e0809c432a"><div class="ttname"><a href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a2b766bfa9653705025b745e0809c432a">PWM_CFG_EN</a></div><div class="ttdeci">@ PWM_CFG_EN</div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:45</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_acbcb6d5d80029fb404efcd7123ff5175a6f741e102b7e15e946714360e81f4bb2"><div class="ttname"><a href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a6f741e102b7e15e946714360e81f4bb2">PWM_CFG_CDIV_MSB</a></div><div class="ttdeci">@ PWM_CFG_CDIV_MSB</div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:41</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_acbcb6d5d80029fb404efcd7123ff5175a9aa8249716b15c92368c93b36bf7db43"><div class="ttname"><a href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175a9aa8249716b15c92368c93b36bf7db43">PWM_CFG_DUTY_LSB</a></div><div class="ttdeci">@ PWM_CFG_DUTY_LSB</div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:38</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_acbcb6d5d80029fb404efcd7123ff5175aa100b419699cd3c6787a9168a3ffec3d"><div class="ttname"><a href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175aa100b419699cd3c6787a9168a3ffec3d">PWM_CFG_PRSC_MSB</a></div><div class="ttdeci">@ PWM_CFG_PRSC_MSB</div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:44</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_acbcb6d5d80029fb404efcd7123ff5175acc7e31e4b3f0e7ab0a0306a107109b4f"><div class="ttname"><a href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175acc7e31e4b3f0e7ab0a0306a107109b4f">PWM_CFG_CDIV_LSB</a></div><div class="ttdeci">@ PWM_CFG_CDIV_LSB</div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:40</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_acbcb6d5d80029fb404efcd7123ff5175aefe2211fe39acffb40ca738639b3d5f5"><div class="ttname"><a href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175aefe2211fe39acffb40ca738639b3d5f5">PWM_CFG_PRSC_LSB</a></div><div class="ttdeci">@ PWM_CFG_PRSC_LSB</div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:43</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_acbcb6d5d80029fb404efcd7123ff5175af5d9dcb5740c39cfe8f9bfb5c1b66341"><div class="ttname"><a href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175af5d9dcb5740c39cfe8f9bfb5c1b66341">PWM_CFG_DUTY_MSB</a></div><div class="ttdeci">@ PWM_CFG_DUTY_MSB</div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:39</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_af00e67388ef9186e051e518883ad9a40"><div class="ttname"><a href="neorv32__pwm_8h.html#af00e67388ef9186e051e518883ad9a40">neorv32_pwm_ch_enable</a></div><div class="ttdeci">void neorv32_pwm_ch_enable(int channel)</div><div class="ttdef"><b>Definition</b> neorv32_pwm.c:62</div></div> +<div class="ttc" id="aneorv32__pwm_8h_html_afb12c860b2f7fa6cd1e069ea540da41c"><div class="ttname"><a href="neorv32__pwm_8h.html#afb12c860b2f7fa6cd1e069ea540da41c">neorv32_pwm_available</a></div><div class="ttdeci">int neorv32_pwm_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_pwm.c:26</div></div> +<div class="ttc" id="astructneorv32__pwm__t_html"><div class="ttname"><a href="structneorv32__pwm__t.html">neorv32_pwm_t</a></div><div class="ttdef"><b>Definition</b> neorv32_pwm.h:29</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__rte_8c.html b/sw/neorv32__rte_8c.html new file mode 100644 index 000000000..36d8014f3 --- /dev/null +++ b/sw/neorv32__rte_8c.html @@ -0,0 +1,468 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> 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class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a53f1e006f0bf61deb7ad018f35228873" id="r_a53f1e006f0bf61deb7ad018f35228873"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a53f1e006f0bf61deb7ad018f35228873">__neorv32_rte_core</a> (void)</td></tr> +<tr class="separator:a53f1e006f0bf61deb7ad018f35228873"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a01bf6c01f5a8cda2132b9ac98824edc1" id="r_a01bf6c01f5a8cda2132b9ac98824edc1"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a01bf6c01f5a8cda2132b9ac98824edc1">__neorv32_rte_print_hex_word</a> (uint32_t num)</td></tr> +<tr class="separator:a01bf6c01f5a8cda2132b9ac98824edc1"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a343e1913bdc37db9b168fb4def0e6170" id="r_a343e1913bdc37db9b168fb4def0e6170"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a343e1913bdc37db9b168fb4def0e6170">neorv32_rte_setup</a> (void)</td></tr> +<tr class="separator:a343e1913bdc37db9b168fb4def0e6170"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2cf31cfa569a03a20d554b6400c4c5e2" id="r_a2cf31cfa569a03a20d554b6400c4c5e2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2cf31cfa569a03a20d554b6400c4c5e2">neorv32_rte_handler_install</a> (int id, void(*handler)(void))</td></tr> +<tr class="separator:a2cf31cfa569a03a20d554b6400c4c5e2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a10fde6229bf391e46148405616404a65" id="r_a10fde6229bf391e46148405616404a65"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a10fde6229bf391e46148405616404a65">neorv32_rte_handler_uninstall</a> (int id)</td></tr> +<tr class="separator:a10fde6229bf391e46148405616404a65"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a65e71acc8916b42b59dc2cf6bba30ba3" id="r_a65e71acc8916b42b59dc2cf6bba30ba3"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a65e71acc8916b42b59dc2cf6bba30ba3">neorv32_rte_context_get</a> (int x)</td></tr> +<tr class="separator:a65e71acc8916b42b59dc2cf6bba30ba3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae13a9c1fd59ad71afb0d47cf9a0b303e" id="r_ae13a9c1fd59ad71afb0d47cf9a0b303e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae13a9c1fd59ad71afb0d47cf9a0b303e">neorv32_rte_context_put</a> (int x, uint32_t data)</td></tr> +<tr class="separator:ae13a9c1fd59ad71afb0d47cf9a0b303e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a65422bb44f1e7bc011e9bfc5d8451ebe" id="r_a65422bb44f1e7bc011e9bfc5d8451ebe"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a65422bb44f1e7bc011e9bfc5d8451ebe">neorv32_rte_debug_handler</a> (void)</td></tr> +<tr class="separator:a65422bb44f1e7bc011e9bfc5d8451ebe"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a05e8304963e402d228a76aff1868771c" id="r_a05e8304963e402d228a76aff1868771c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a05e8304963e402d228a76aff1868771c">neorv32_rte_print_hw_config</a> (void)</td></tr> +<tr class="separator:a05e8304963e402d228a76aff1868771c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aad6f5256a265807c4cde163bcba8dae9" id="r_aad6f5256a265807c4cde163bcba8dae9"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aad6f5256a265807c4cde163bcba8dae9">neorv32_rte_print_hw_version</a> (void)</td></tr> +<tr class="separator:aad6f5256a265807c4cde163bcba8dae9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa442c0e39f9156a131c3432fda587692" id="r_aa442c0e39f9156a131c3432fda587692"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa442c0e39f9156a131c3432fda587692">neorv32_rte_print_about</a> (void)</td></tr> +<tr class="separator:aa442c0e39f9156a131c3432fda587692"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a16df1b48f2e1258a51d3bb7f49531cf3" id="r_a16df1b48f2e1258a51d3bb7f49531cf3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a16df1b48f2e1258a51d3bb7f49531cf3">neorv32_rte_print_logo</a> (void)</td></tr> +<tr class="separator:a16df1b48f2e1258a51d3bb7f49531cf3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acd96aa73eebe6d4bbc9aabe1230cbabc" id="r_acd96aa73eebe6d4bbc9aabe1230cbabc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acd96aa73eebe6d4bbc9aabe1230cbabc">neorv32_rte_print_license</a> (void)</td></tr> +<tr class="separator:acd96aa73eebe6d4bbc9aabe1230cbabc"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a2c8272b4628edddb943bcfad829b561a" id="r_a2c8272b4628edddb943bcfad829b561a"><td class="memItemLeft" align="right" valign="top">static uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2c8272b4628edddb943bcfad829b561a">__neorv32_rte_vector_lut</a> [<a class="el" href="neorv32__rte_8h.html#ad14a1ca41df1e9300bfd01aef07dce59">NEORV32_RTE_NUM_TRAPS</a>]</td></tr> +<tr class="separator:a2c8272b4628edddb943bcfad829b561a"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>NEORV32 Runtime Environment. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a53f1e006f0bf61deb7ad018f35228873" name="a53f1e006f0bf61deb7ad018f35228873"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a53f1e006f0bf61deb7ad018f35228873">&#9670;&#160;</a></span>__neorv32_rte_core()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">static void __neorv32_rte_core </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">static</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): This is the core of the NEORV32 RTE (first-level trap handler, executed in machine mode). </p> + +</div> +</div> +<a id="a01bf6c01f5a8cda2132b9ac98824edc1" name="a01bf6c01f5a8cda2132b9ac98824edc1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a01bf6c01f5a8cda2132b9ac98824edc1">&#9670;&#160;</a></span>__neorv32_rte_print_hex_word()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void __neorv32_rte_print_hex_word </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>num</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">static</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Private function to print 32-bit number as 8-digit hexadecimal value (with "0x" suffix).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Number to print as hexadecimal via UART0. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a65e71acc8916b42b59dc2cf6bba30ba3" name="a65e71acc8916b42b59dc2cf6bba30ba3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a65e71acc8916b42b59dc2cf6bba30ba3">&#9670;&#160;</a></span>neorv32_rte_context_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_rte_context_get </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>x</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Read register from application context (on stack).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">x</td><td>Register number (0..31, corresponds to register x0..x31). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Content of register x. </dd></dl> + +</div> +</div> +<a id="ae13a9c1fd59ad71afb0d47cf9a0b303e" name="ae13a9c1fd59ad71afb0d47cf9a0b303e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae13a9c1fd59ad71afb0d47cf9a0b303e">&#9670;&#160;</a></span>neorv32_rte_context_put()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_context_put </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>x</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>data</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Write register to application context (on stack).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">x</td><td>Register number (0..31, corresponds to register x0..x31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>Data to be written to register x. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a65422bb44f1e7bc011e9bfc5d8451ebe" name="a65422bb44f1e7bc011e9bfc5d8451ebe"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a65422bb44f1e7bc011e9bfc5d8451ebe">&#9670;&#160;</a></span>neorv32_rte_debug_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_debug_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Debug trap handler, printing information via UART0. </p> + +</div> +</div> +<a id="a2cf31cfa569a03a20d554b6400c4c5e2" name="a2cf31cfa569a03a20d554b6400c4c5e2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2cf31cfa569a03a20d554b6400c4c5e2">&#9670;&#160;</a></span>neorv32_rte_handler_install()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_rte_handler_install </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>id</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">void(*</td> <td class="paramname"><span class="paramname"><em>handler&#160;</em></span>)(void)&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Install trap handler function (second-level trap handler).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>Identifier (type) of the targeted trap. See <a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">handler</td><td>The actual handler function for the specified trap (function MUST be of type "void function(void);"). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if success, -1 if error (invalid id or targeted trap not supported). </dd></dl> + +</div> +</div> +<a id="a10fde6229bf391e46148405616404a65" name="a10fde6229bf391e46148405616404a65"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a10fde6229bf391e46148405616404a65">&#9670;&#160;</a></span>neorv32_rte_handler_uninstall()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_rte_handler_uninstall </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>id</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Uninstall trap handler function from NEORV32 runtime environment, which was previously installed via neorv32_rte_handler_install(uint8_t id, void (*handler)(void)).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>Identifier (type) of the targeted trap. See <a class="el" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if success, -1 if error (invalid id or targeted trap not supported). </dd></dl> + +</div> +</div> +<a id="aa442c0e39f9156a131c3432fda587692" name="aa442c0e39f9156a131c3432fda587692"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa442c0e39f9156a131c3432fda587692">&#9670;&#160;</a></span>neorv32_rte_print_about()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_about </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print project info via UART0. </p> + +</div> +</div> +<a id="a05e8304963e402d228a76aff1868771c" name="a05e8304963e402d228a76aff1868771c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a05e8304963e402d228a76aff1868771c">&#9670;&#160;</a></span>neorv32_rte_print_hw_config()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_hw_config </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print hardware configuration information via UART0.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function overrides several CSR, CNT and HPM CSRs! </dd></dl> + +</div> +</div> +<a id="aad6f5256a265807c4cde163bcba8dae9" name="aad6f5256a265807c4cde163bcba8dae9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aad6f5256a265807c4cde163bcba8dae9">&#9670;&#160;</a></span>neorv32_rte_print_hw_version()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_hw_version </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print the processor version in human-readable format via UART0. </p> + +</div> +</div> +<a id="acd96aa73eebe6d4bbc9aabe1230cbabc" name="acd96aa73eebe6d4bbc9aabe1230cbabc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acd96aa73eebe6d4bbc9aabe1230cbabc">&#9670;&#160;</a></span>neorv32_rte_print_license()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_license </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print project license via UART0. </p> + +</div> +</div> +<a id="a16df1b48f2e1258a51d3bb7f49531cf3" name="a16df1b48f2e1258a51d3bb7f49531cf3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a16df1b48f2e1258a51d3bb7f49531cf3">&#9670;&#160;</a></span>neorv32_rte_print_logo()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_logo </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print project logo via UART0. </p> + +</div> +</div> +<a id="a343e1913bdc37db9b168fb4def0e6170" name="a343e1913bdc37db9b168fb4def0e6170"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a343e1913bdc37db9b168fb4def0e6170">&#9670;&#160;</a></span>neorv32_rte_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_setup </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Setup RTE.</p> +<dl class="section note"><dt>Note</dt><dd>This function installs a debug handler for ALL trap sources, which gives detailed information about the trap. Actual handlers can be installed afterwards via neorv32_rte_handler_install(uint8_t id, void (*handler)(void)). </dd></dl> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a id="a2c8272b4628edddb943bcfad829b561a" name="a2c8272b4628edddb943bcfad829b561a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2c8272b4628edddb943bcfad829b561a">&#9670;&#160;</a></span>__neorv32_rte_vector_lut</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __neorv32_rte_vector_lut[<a class="el" href="neorv32__rte_8h.html#ad14a1ca41df1e9300bfd01aef07dce59">NEORV32_RTE_NUM_TRAPS</a>]</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">static</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): The &gt;private&lt; trap vector look-up table of the NEORV32 RTE. </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__rte_8h.html b/sw/neorv32__rte_8h.html new file mode 100644 index 000000000..d42e20947 --- /dev/null +++ b/sw/neorv32__rte_8h.html @@ -0,0 +1,520 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#define-members">Macros</a> &#124; +<a href="#enum-members">Enumerations</a> </div> + <div class="headertitle"><div class="title">neorv32_rte.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>NEORV32 Runtime Environment. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__rte_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:ad14a1ca41df1e9300bfd01aef07dce59" id="r_ad14a1ca41df1e9300bfd01aef07dce59"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad14a1ca41df1e9300bfd01aef07dce59">NEORV32_RTE_NUM_TRAPS</a>&#160;&#160;&#160;29</td></tr> +<tr class="separator:ad14a1ca41df1e9300bfd01aef07dce59"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a> +Enumerations</h2></td></tr> +<tr class="memitem:ad28f86ab02d89ade2f0bc12e0a8ca70a" id="r_ad28f86ab02d89ade2f0bc12e0a8ca70a"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aa931a4f314b04233924b01e8245153be4">RTE_TRAP_I_ACCESS</a> = 0 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aa48f4d253b260784a1ffaaded508166e2">RTE_TRAP_I_ILLEGAL</a> = 1 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aaf647ff8d55d021379202879627c91d81">RTE_TRAP_I_MISALIGNED</a> = 2 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aa463611404367b5910c42dd31c0a218a2">RTE_TRAP_BREAKPOINT</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aa8e2cc9a533ebbc0e1d29c3ec8afbe61f">RTE_TRAP_L_MISALIGNED</a> = 4 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aa97047b024b72807a0b312979c9359dab">RTE_TRAP_L_ACCESS</a> = 5 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aa85934b3fd8b5268340f84810b3f67232">RTE_TRAP_S_MISALIGNED</a> = 6 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aaa9b8334712ecad0500c7610a25741ec7">RTE_TRAP_S_ACCESS</a> = 7 +, <br /> +&#160;&#160;<a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aa155f84a52bace69f81a99de59701decc">RTE_TRAP_UENV_CALL</a> = 8 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aaea6027bf0354c3120fa61c8094dd7a1d">RTE_TRAP_MENV_CALL</a> = 9 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aadddffa9acdfcce80dd68ad4b26725174">RTE_TRAP_MSI</a> = 10 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aacf17d4b2454c43a1cb544e532d247fff">RTE_TRAP_MTI</a> = 11 +, <br /> +&#160;&#160;<a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aad2a55d5586d33497fd21b1da8aa98fff">RTE_TRAP_MEI</a> = 12 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aab36a403cd7b833439ce7f9a708c33922">RTE_TRAP_FIRQ_0</a> = 13 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aab199b53a1458017fa5278e0aeecf41fd">RTE_TRAP_FIRQ_1</a> = 14 +, <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70aa29ffa3108fadc78bf375773c3232c489">RTE_TRAP_FIRQ_2</a> = 15 +, <br /> +&#160;&#160;<a class="el" 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class="memitem:a343e1913bdc37db9b168fb4def0e6170" id="r_a343e1913bdc37db9b168fb4def0e6170"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a343e1913bdc37db9b168fb4def0e6170">neorv32_rte_setup</a> (void)</td></tr> +<tr class="separator:a343e1913bdc37db9b168fb4def0e6170"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2cf31cfa569a03a20d554b6400c4c5e2" id="r_a2cf31cfa569a03a20d554b6400c4c5e2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2cf31cfa569a03a20d554b6400c4c5e2">neorv32_rte_handler_install</a> (int id, void(*handler)(void))</td></tr> +<tr class="separator:a2cf31cfa569a03a20d554b6400c4c5e2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a10fde6229bf391e46148405616404a65" id="r_a10fde6229bf391e46148405616404a65"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a10fde6229bf391e46148405616404a65">neorv32_rte_handler_uninstall</a> (int id)</td></tr> +<tr class="separator:a10fde6229bf391e46148405616404a65"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a65422bb44f1e7bc011e9bfc5d8451ebe" id="r_a65422bb44f1e7bc011e9bfc5d8451ebe"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a65422bb44f1e7bc011e9bfc5d8451ebe">neorv32_rte_debug_handler</a> (void)</td></tr> +<tr class="separator:a65422bb44f1e7bc011e9bfc5d8451ebe"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a65e71acc8916b42b59dc2cf6bba30ba3" id="r_a65e71acc8916b42b59dc2cf6bba30ba3"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a65e71acc8916b42b59dc2cf6bba30ba3">neorv32_rte_context_get</a> (int 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class="memItemRight" valign="bottom"><a class="el" href="#a16df1b48f2e1258a51d3bb7f49531cf3">neorv32_rte_print_logo</a> (void)</td></tr> +<tr class="separator:a16df1b48f2e1258a51d3bb7f49531cf3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acd96aa73eebe6d4bbc9aabe1230cbabc" id="r_acd96aa73eebe6d4bbc9aabe1230cbabc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acd96aa73eebe6d4bbc9aabe1230cbabc">neorv32_rte_print_license</a> (void)</td></tr> +<tr class="separator:acd96aa73eebe6d4bbc9aabe1230cbabc"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>NEORV32 Runtime Environment. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ad14a1ca41df1e9300bfd01aef07dce59" name="ad14a1ca41df1e9300bfd01aef07dce59"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad14a1ca41df1e9300bfd01aef07dce59">&#9670;&#160;</a></span>NEORV32_RTE_NUM_TRAPS</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_RTE_NUM_TRAPS&#160;&#160;&#160;29</td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment: Number of available traps. </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="ad28f86ab02d89ade2f0bc12e0a8ca70a" name="ad28f86ab02d89ade2f0bc12e0a8ca70a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad28f86ab02d89ade2f0bc12e0a8ca70a">&#9670;&#160;</a></span>NEORV32_RTE_TRAP_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a 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name="ad28f86ab02d89ade2f0bc12e0a8ca70aaf647ff8d55d021379202879627c91d81"></a>RTE_TRAP_I_MISALIGNED&#160;</td><td class="fielddoc"><p>Instruction address misaligned </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa463611404367b5910c42dd31c0a218a2" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa463611404367b5910c42dd31c0a218a2"></a>RTE_TRAP_BREAKPOINT&#160;</td><td class="fielddoc"><p>Breakpoint (EBREAK instruction) </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa8e2cc9a533ebbc0e1d29c3ec8afbe61f" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa8e2cc9a533ebbc0e1d29c3ec8afbe61f"></a>RTE_TRAP_L_MISALIGNED&#160;</td><td class="fielddoc"><p>Load address misaligned </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa97047b024b72807a0b312979c9359dab" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa97047b024b72807a0b312979c9359dab"></a>RTE_TRAP_L_ACCESS&#160;</td><td class="fielddoc"><p>Load access fault </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa85934b3fd8b5268340f84810b3f67232" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa85934b3fd8b5268340f84810b3f67232"></a>RTE_TRAP_S_MISALIGNED&#160;</td><td class="fielddoc"><p>Store address misaligned </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aaa9b8334712ecad0500c7610a25741ec7" name="ad28f86ab02d89ade2f0bc12e0a8ca70aaa9b8334712ecad0500c7610a25741ec7"></a>RTE_TRAP_S_ACCESS&#160;</td><td class="fielddoc"><p>Store access fault </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa155f84a52bace69f81a99de59701decc" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa155f84a52bace69f81a99de59701decc"></a>RTE_TRAP_UENV_CALL&#160;</td><td class="fielddoc"><p>Environment call from user mode (ECALL instruction) </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aaea6027bf0354c3120fa61c8094dd7a1d" name="ad28f86ab02d89ade2f0bc12e0a8ca70aaea6027bf0354c3120fa61c8094dd7a1d"></a>RTE_TRAP_MENV_CALL&#160;</td><td class="fielddoc"><p>Environment call from machine mode (ECALL instruction) </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aadddffa9acdfcce80dd68ad4b26725174" name="ad28f86ab02d89ade2f0bc12e0a8ca70aadddffa9acdfcce80dd68ad4b26725174"></a>RTE_TRAP_MSI&#160;</td><td class="fielddoc"><p>Machine software interrupt </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aacf17d4b2454c43a1cb544e532d247fff" name="ad28f86ab02d89ade2f0bc12e0a8ca70aacf17d4b2454c43a1cb544e532d247fff"></a>RTE_TRAP_MTI&#160;</td><td class="fielddoc"><p>Machine timer interrupt </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aad2a55d5586d33497fd21b1da8aa98fff" name="ad28f86ab02d89ade2f0bc12e0a8ca70aad2a55d5586d33497fd21b1da8aa98fff"></a>RTE_TRAP_MEI&#160;</td><td class="fielddoc"><p>Machine external interrupt </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aab36a403cd7b833439ce7f9a708c33922" name="ad28f86ab02d89ade2f0bc12e0a8ca70aab36a403cd7b833439ce7f9a708c33922"></a>RTE_TRAP_FIRQ_0&#160;</td><td class="fielddoc"><p>Fast interrupt channel 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aab199b53a1458017fa5278e0aeecf41fd" name="ad28f86ab02d89ade2f0bc12e0a8ca70aab199b53a1458017fa5278e0aeecf41fd"></a>RTE_TRAP_FIRQ_1&#160;</td><td class="fielddoc"><p>Fast interrupt channel 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa29ffa3108fadc78bf375773c3232c489" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa29ffa3108fadc78bf375773c3232c489"></a>RTE_TRAP_FIRQ_2&#160;</td><td class="fielddoc"><p>Fast interrupt channel 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa4a74188fd87ea17a594ac6fe8ddf71be" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa4a74188fd87ea17a594ac6fe8ddf71be"></a>RTE_TRAP_FIRQ_3&#160;</td><td class="fielddoc"><p>Fast interrupt channel 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa8b39868bf91da54f9ec492918e0c01ff" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa8b39868bf91da54f9ec492918e0c01ff"></a>RTE_TRAP_FIRQ_4&#160;</td><td class="fielddoc"><p>Fast interrupt channel 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa01f562418ddbbb6b84be168673deeea9" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa01f562418ddbbb6b84be168673deeea9"></a>RTE_TRAP_FIRQ_5&#160;</td><td class="fielddoc"><p>Fast interrupt channel 5 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aac9fb28ea8bafff182f12c29d2fad6998" name="ad28f86ab02d89ade2f0bc12e0a8ca70aac9fb28ea8bafff182f12c29d2fad6998"></a>RTE_TRAP_FIRQ_6&#160;</td><td class="fielddoc"><p>Fast interrupt channel 6 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa73bb84f7b6c7528bec552ac1d3e9ccdb" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa73bb84f7b6c7528bec552ac1d3e9ccdb"></a>RTE_TRAP_FIRQ_7&#160;</td><td class="fielddoc"><p>Fast interrupt channel 7 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa3edbf47bd9a278e100bb808c8bb68308" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa3edbf47bd9a278e100bb808c8bb68308"></a>RTE_TRAP_FIRQ_8&#160;</td><td class="fielddoc"><p>Fast interrupt channel 8 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa2cd04189d91465dad2bc2a8852406b76" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa2cd04189d91465dad2bc2a8852406b76"></a>RTE_TRAP_FIRQ_9&#160;</td><td class="fielddoc"><p>Fast interrupt channel 9 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aadebcc4d91aea1364b1481111f1060c52" name="ad28f86ab02d89ade2f0bc12e0a8ca70aadebcc4d91aea1364b1481111f1060c52"></a>RTE_TRAP_FIRQ_10&#160;</td><td class="fielddoc"><p>Fast interrupt channel 10 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aab49ff0110481f22da22a085d2633a0e0" name="ad28f86ab02d89ade2f0bc12e0a8ca70aab49ff0110481f22da22a085d2633a0e0"></a>RTE_TRAP_FIRQ_11&#160;</td><td class="fielddoc"><p>Fast interrupt channel 11 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aaecea4f1d524a33d02324382357b2bcb9" name="ad28f86ab02d89ade2f0bc12e0a8ca70aaecea4f1d524a33d02324382357b2bcb9"></a>RTE_TRAP_FIRQ_12&#160;</td><td class="fielddoc"><p>Fast interrupt channel 12 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa609613cf25bb8f2d0e323089d6798220" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa609613cf25bb8f2d0e323089d6798220"></a>RTE_TRAP_FIRQ_13&#160;</td><td class="fielddoc"><p>Fast interrupt channel 13 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aaadd66d9b9c33a6869fa3c30e1e434313" name="ad28f86ab02d89ade2f0bc12e0a8ca70aaadd66d9b9c33a6869fa3c30e1e434313"></a>RTE_TRAP_FIRQ_14&#160;</td><td class="fielddoc"><p>Fast interrupt channel 14 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad28f86ab02d89ade2f0bc12e0a8ca70aa1d18312227bfd5332ebcc1f74c979dbe" name="ad28f86ab02d89ade2f0bc12e0a8ca70aa1d18312227bfd5332ebcc1f74c979dbe"></a>RTE_TRAP_FIRQ_15&#160;</td><td class="fielddoc"><p>Fast interrupt channel 15 </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a65e71acc8916b42b59dc2cf6bba30ba3" name="a65e71acc8916b42b59dc2cf6bba30ba3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a65e71acc8916b42b59dc2cf6bba30ba3">&#9670;&#160;</a></span>neorv32_rte_context_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_rte_context_get </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>x</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Read register from application context (on stack).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">x</td><td>Register number (0..31, corresponds to register x0..x31). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Content of register x. </dd></dl> + +</div> +</div> +<a id="ae13a9c1fd59ad71afb0d47cf9a0b303e" name="ae13a9c1fd59ad71afb0d47cf9a0b303e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae13a9c1fd59ad71afb0d47cf9a0b303e">&#9670;&#160;</a></span>neorv32_rte_context_put()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_context_put </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>x</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>data</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Write register to application context (on stack).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">x</td><td>Register number (0..31, corresponds to register x0..x31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>Data to be written to register x. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a65422bb44f1e7bc011e9bfc5d8451ebe" name="a65422bb44f1e7bc011e9bfc5d8451ebe"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a65422bb44f1e7bc011e9bfc5d8451ebe">&#9670;&#160;</a></span>neorv32_rte_debug_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_debug_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Debug trap handler, printing information via UART0. </p> + +</div> +</div> +<a id="a2cf31cfa569a03a20d554b6400c4c5e2" name="a2cf31cfa569a03a20d554b6400c4c5e2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2cf31cfa569a03a20d554b6400c4c5e2">&#9670;&#160;</a></span>neorv32_rte_handler_install()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_rte_handler_install </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>id</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">void(*</td> <td class="paramname"><span class="paramname"><em>handler&#160;</em></span>)(void)&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Install trap handler function (second-level trap handler).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>Identifier (type) of the targeted trap. See <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">handler</td><td>The actual handler function for the specified trap (function MUST be of type "void function(void);"). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if success, -1 if error (invalid id or targeted trap not supported). </dd></dl> + +</div> +</div> +<a id="a10fde6229bf391e46148405616404a65" name="a10fde6229bf391e46148405616404a65"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a10fde6229bf391e46148405616404a65">&#9670;&#160;</a></span>neorv32_rte_handler_uninstall()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_rte_handler_uninstall </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>id</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Uninstall trap handler function from NEORV32 runtime environment, which was previously installed via neorv32_rte_handler_install(uint8_t id, void (*handler)(void)).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>Identifier (type) of the targeted trap. See <a class="el" href="#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if success, -1 if error (invalid id or targeted trap not supported). </dd></dl> + +</div> +</div> +<a id="aa442c0e39f9156a131c3432fda587692" name="aa442c0e39f9156a131c3432fda587692"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa442c0e39f9156a131c3432fda587692">&#9670;&#160;</a></span>neorv32_rte_print_about()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_about </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print project info via UART0. </p> + +</div> +</div> +<a id="a05e8304963e402d228a76aff1868771c" name="a05e8304963e402d228a76aff1868771c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a05e8304963e402d228a76aff1868771c">&#9670;&#160;</a></span>neorv32_rte_print_hw_config()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_hw_config </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print hardware configuration information via UART0.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function overrides several CSR, CNT and HPM CSRs! </dd></dl> + +</div> +</div> +<a id="aad6f5256a265807c4cde163bcba8dae9" name="aad6f5256a265807c4cde163bcba8dae9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aad6f5256a265807c4cde163bcba8dae9">&#9670;&#160;</a></span>neorv32_rte_print_hw_version()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_hw_version </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print the processor version in human-readable format via UART0. </p> + +</div> +</div> +<a id="acd96aa73eebe6d4bbc9aabe1230cbabc" name="acd96aa73eebe6d4bbc9aabe1230cbabc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acd96aa73eebe6d4bbc9aabe1230cbabc">&#9670;&#160;</a></span>neorv32_rte_print_license()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_license </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print project license via UART0. </p> + +</div> +</div> +<a id="a16df1b48f2e1258a51d3bb7f49531cf3" name="a16df1b48f2e1258a51d3bb7f49531cf3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a16df1b48f2e1258a51d3bb7f49531cf3">&#9670;&#160;</a></span>neorv32_rte_print_logo()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_print_logo </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Print project logo via UART0. </p> + +</div> +</div> +<a id="a343e1913bdc37db9b168fb4def0e6170" name="a343e1913bdc37db9b168fb4def0e6170"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a343e1913bdc37db9b168fb4def0e6170">&#9670;&#160;</a></span>neorv32_rte_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_rte_setup </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32 runtime environment (RTE): Setup RTE.</p> +<dl class="section note"><dt>Note</dt><dd>This function installs a debug handler for ALL trap sources, which gives detailed information about the trap. Actual handlers can be installed afterwards via neorv32_rte_handler_install(uint8_t id, void (*handler)(void)). </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__rte_8h_source.html b/sw/neorv32__rte_8h_source.html new file mode 100644 index 000000000..735d26cd5 --- /dev/null +++ b/sw/neorv32__rte_8h_source.html @@ -0,0 +1,212 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_rte.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_rte_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_rte_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad14a1ca41df1e9300bfd01aef07dce59"> 25</a></span><span class="preprocessor">#define NEORV32_RTE_NUM_TRAPS 29</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span> </div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span> </div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00031" data-start="{" data-end="};"> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a"> 31</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a> {</div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa931a4f314b04233924b01e8245153be4"> 32</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa931a4f314b04233924b01e8245153be4">RTE_TRAP_I_ACCESS</a> = 0, </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa48f4d253b260784a1ffaaded508166e2"> 33</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa48f4d253b260784a1ffaaded508166e2">RTE_TRAP_I_ILLEGAL</a> = 1, </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaf647ff8d55d021379202879627c91d81"> 34</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaf647ff8d55d021379202879627c91d81">RTE_TRAP_I_MISALIGNED</a> = 2, </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa463611404367b5910c42dd31c0a218a2"> 35</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa463611404367b5910c42dd31c0a218a2">RTE_TRAP_BREAKPOINT</a> = 3, </div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa8e2cc9a533ebbc0e1d29c3ec8afbe61f"> 36</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa8e2cc9a533ebbc0e1d29c3ec8afbe61f">RTE_TRAP_L_MISALIGNED</a> = 4, </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa97047b024b72807a0b312979c9359dab"> 37</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa97047b024b72807a0b312979c9359dab">RTE_TRAP_L_ACCESS</a> = 5, </div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa85934b3fd8b5268340f84810b3f67232"> 38</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa85934b3fd8b5268340f84810b3f67232">RTE_TRAP_S_MISALIGNED</a> = 6, </div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaa9b8334712ecad0500c7610a25741ec7"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaa9b8334712ecad0500c7610a25741ec7">RTE_TRAP_S_ACCESS</a> = 7, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa155f84a52bace69f81a99de59701decc"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa155f84a52bace69f81a99de59701decc">RTE_TRAP_UENV_CALL</a> = 8, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaea6027bf0354c3120fa61c8094dd7a1d"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaea6027bf0354c3120fa61c8094dd7a1d">RTE_TRAP_MENV_CALL</a> = 9, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aadddffa9acdfcce80dd68ad4b26725174"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aadddffa9acdfcce80dd68ad4b26725174">RTE_TRAP_MSI</a> = 10, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aacf17d4b2454c43a1cb544e532d247fff"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aacf17d4b2454c43a1cb544e532d247fff">RTE_TRAP_MTI</a> = 11, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aad2a55d5586d33497fd21b1da8aa98fff"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aad2a55d5586d33497fd21b1da8aa98fff">RTE_TRAP_MEI</a> = 12, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab36a403cd7b833439ce7f9a708c33922"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab36a403cd7b833439ce7f9a708c33922">RTE_TRAP_FIRQ_0</a> = 13, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab199b53a1458017fa5278e0aeecf41fd"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab199b53a1458017fa5278e0aeecf41fd">RTE_TRAP_FIRQ_1</a> = 14, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa29ffa3108fadc78bf375773c3232c489"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa29ffa3108fadc78bf375773c3232c489">RTE_TRAP_FIRQ_2</a> = 15, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa4a74188fd87ea17a594ac6fe8ddf71be"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa4a74188fd87ea17a594ac6fe8ddf71be">RTE_TRAP_FIRQ_3</a> = 16, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa8b39868bf91da54f9ec492918e0c01ff"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa8b39868bf91da54f9ec492918e0c01ff">RTE_TRAP_FIRQ_4</a> = 17, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa01f562418ddbbb6b84be168673deeea9"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa01f562418ddbbb6b84be168673deeea9">RTE_TRAP_FIRQ_5</a> = 18, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aac9fb28ea8bafff182f12c29d2fad6998"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aac9fb28ea8bafff182f12c29d2fad6998">RTE_TRAP_FIRQ_6</a> = 19, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa73bb84f7b6c7528bec552ac1d3e9ccdb"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa73bb84f7b6c7528bec552ac1d3e9ccdb">RTE_TRAP_FIRQ_7</a> = 20, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa3edbf47bd9a278e100bb808c8bb68308"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa3edbf47bd9a278e100bb808c8bb68308">RTE_TRAP_FIRQ_8</a> = 21, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa2cd04189d91465dad2bc2a8852406b76"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa2cd04189d91465dad2bc2a8852406b76">RTE_TRAP_FIRQ_9</a> = 22, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aadebcc4d91aea1364b1481111f1060c52"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aadebcc4d91aea1364b1481111f1060c52">RTE_TRAP_FIRQ_10</a> = 23, </div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab49ff0110481f22da22a085d2633a0e0"> 56</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab49ff0110481f22da22a085d2633a0e0">RTE_TRAP_FIRQ_11</a> = 24, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaecea4f1d524a33d02324382357b2bcb9"> 57</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaecea4f1d524a33d02324382357b2bcb9">RTE_TRAP_FIRQ_12</a> = 25, </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa609613cf25bb8f2d0e323089d6798220"> 58</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa609613cf25bb8f2d0e323089d6798220">RTE_TRAP_FIRQ_13</a> = 26, </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaadd66d9b9c33a6869fa3c30e1e434313"> 59</a></span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaadd66d9b9c33a6869fa3c30e1e434313">RTE_TRAP_FIRQ_14</a> = 27, </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span> <a class="code hl_enumvalue" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa1d18312227bfd5332ebcc1f74c979dbe">RTE_TRAP_FIRQ_15</a> = 28 </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa1d18312227bfd5332ebcc1f74c979dbe"> 61</a></span>};</div> +</div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span> </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__rte_8h.html#a343e1913bdc37db9b168fb4def0e6170">neorv32_rte_setup</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__rte_8h.html#a2cf31cfa569a03a20d554b6400c4c5e2">neorv32_rte_handler_install</a>(<span class="keywordtype">int</span> <span class="keywordtype">id</span>, <span class="keywordtype">void</span> (*handler)(<span class="keywordtype">void</span>));</div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__rte_8h.html#a10fde6229bf391e46148405616404a65">neorv32_rte_handler_uninstall</a>(<span class="keywordtype">int</span> <span class="keywordtype">id</span>);</div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__rte_8h.html#a65422bb44f1e7bc011e9bfc5d8451ebe">neorv32_rte_debug_handler</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span>uint32_t <a class="code hl_function" href="neorv32__rte_8h.html#a65e71acc8916b42b59dc2cf6bba30ba3">neorv32_rte_context_get</a>(<span class="keywordtype">int</span> x);</div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__rte_8h.html#ae13a9c1fd59ad71afb0d47cf9a0b303e">neorv32_rte_context_put</a>(<span class="keywordtype">int</span> x, uint32_t data);</div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span> </div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__rte_8h.html#a05e8304963e402d228a76aff1868771c">neorv32_rte_print_hw_config</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__rte_8h.html#aad6f5256a265807c4cde163bcba8dae9">neorv32_rte_print_hw_version</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__rte_8h.html#aa442c0e39f9156a131c3432fda587692">neorv32_rte_print_about</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__rte_8h.html#a16df1b48f2e1258a51d3bb7f49531cf3">neorv32_rte_print_logo</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__rte_8h.html#acd96aa73eebe6d4bbc9aabe1230cbabc">neorv32_rte_print_license</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_rte_h</span></div> +<div class="ttc" id="aneorv32__rte_8h_html_a05e8304963e402d228a76aff1868771c"><div class="ttname"><a href="neorv32__rte_8h.html#a05e8304963e402d228a76aff1868771c">neorv32_rte_print_hw_config</a></div><div class="ttdeci">void neorv32_rte_print_hw_config(void)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:387</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_a10fde6229bf391e46148405616404a65"><div class="ttname"><a href="neorv32__rte_8h.html#a10fde6229bf391e46148405616404a65">neorv32_rte_handler_uninstall</a></div><div class="ttdeci">int neorv32_rte_handler_uninstall(int id)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:85</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_a16df1b48f2e1258a51d3bb7f49531cf3"><div class="ttname"><a href="neorv32__rte_8h.html#a16df1b48f2e1258a51d3bb7f49531cf3">neorv32_rte_print_logo</a></div><div class="ttdeci">void neorv32_rte_print_logo(void)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:726</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_a2cf31cfa569a03a20d554b6400c4c5e2"><div class="ttname"><a href="neorv32__rte_8h.html#a2cf31cfa569a03a20d554b6400c4c5e2">neorv32_rte_handler_install</a></div><div class="ttdeci">int neorv32_rte_handler_install(int id, void(*handler)(void))</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:65</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_a343e1913bdc37db9b168fb4def0e6170"><div class="ttname"><a href="neorv32__rte_8h.html#a343e1913bdc37db9b168fb4def0e6170">neorv32_rte_setup</a></div><div class="ttdeci">void neorv32_rte_setup(void)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:38</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_a65422bb44f1e7bc011e9bfc5d8451ebe"><div class="ttname"><a href="neorv32__rte_8h.html#a65422bb44f1e7bc011e9bfc5d8451ebe">neorv32_rte_debug_handler</a></div><div class="ttdeci">void neorv32_rte_debug_handler(void)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:297</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_a65e71acc8916b42b59dc2cf6bba30ba3"><div class="ttname"><a href="neorv32__rte_8h.html#a65e71acc8916b42b59dc2cf6bba30ba3">neorv32_rte_context_get</a></div><div class="ttdeci">uint32_t neorv32_rte_context_get(int x)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:260</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_aa442c0e39f9156a131c3432fda587692"><div class="ttname"><a href="neorv32__rte_8h.html#aa442c0e39f9156a131c3432fda587692">neorv32_rte_print_about</a></div><div class="ttdeci">void neorv32_rte_print_about(void)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:711</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_aad6f5256a265807c4cde163bcba8dae9"><div class="ttname"><a href="neorv32__rte_8h.html#aad6f5256a265807c4cde163bcba8dae9">neorv32_rte_print_hw_version</a></div><div class="ttdeci">void neorv32_rte_print_hw_version(void)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:678</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_acd96aa73eebe6d4bbc9aabe1230cbabc"><div class="ttname"><a href="neorv32__rte_8h.html#acd96aa73eebe6d4bbc9aabe1230cbabc">neorv32_rte_print_license</a></div><div class="ttdeci">void neorv32_rte_print_license(void)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:768</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70a"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70a">NEORV32_RTE_TRAP_enum</a></div><div class="ttdeci">NEORV32_RTE_TRAP_enum</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:31</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa01f562418ddbbb6b84be168673deeea9"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa01f562418ddbbb6b84be168673deeea9">RTE_TRAP_FIRQ_5</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_5</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:50</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa155f84a52bace69f81a99de59701decc"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa155f84a52bace69f81a99de59701decc">RTE_TRAP_UENV_CALL</a></div><div class="ttdeci">@ RTE_TRAP_UENV_CALL</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:40</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa1d18312227bfd5332ebcc1f74c979dbe"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa1d18312227bfd5332ebcc1f74c979dbe">RTE_TRAP_FIRQ_15</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_15</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:60</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa29ffa3108fadc78bf375773c3232c489"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa29ffa3108fadc78bf375773c3232c489">RTE_TRAP_FIRQ_2</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_2</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:47</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa2cd04189d91465dad2bc2a8852406b76"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa2cd04189d91465dad2bc2a8852406b76">RTE_TRAP_FIRQ_9</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_9</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:54</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa3edbf47bd9a278e100bb808c8bb68308"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa3edbf47bd9a278e100bb808c8bb68308">RTE_TRAP_FIRQ_8</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_8</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:53</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa463611404367b5910c42dd31c0a218a2"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa463611404367b5910c42dd31c0a218a2">RTE_TRAP_BREAKPOINT</a></div><div class="ttdeci">@ RTE_TRAP_BREAKPOINT</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:35</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa48f4d253b260784a1ffaaded508166e2"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa48f4d253b260784a1ffaaded508166e2">RTE_TRAP_I_ILLEGAL</a></div><div class="ttdeci">@ RTE_TRAP_I_ILLEGAL</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:33</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa4a74188fd87ea17a594ac6fe8ddf71be"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa4a74188fd87ea17a594ac6fe8ddf71be">RTE_TRAP_FIRQ_3</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_3</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:48</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa609613cf25bb8f2d0e323089d6798220"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa609613cf25bb8f2d0e323089d6798220">RTE_TRAP_FIRQ_13</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_13</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:58</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa73bb84f7b6c7528bec552ac1d3e9ccdb"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa73bb84f7b6c7528bec552ac1d3e9ccdb">RTE_TRAP_FIRQ_7</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_7</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:52</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa85934b3fd8b5268340f84810b3f67232"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa85934b3fd8b5268340f84810b3f67232">RTE_TRAP_S_MISALIGNED</a></div><div class="ttdeci">@ RTE_TRAP_S_MISALIGNED</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:38</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa8b39868bf91da54f9ec492918e0c01ff"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa8b39868bf91da54f9ec492918e0c01ff">RTE_TRAP_FIRQ_4</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_4</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:49</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa8e2cc9a533ebbc0e1d29c3ec8afbe61f"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa8e2cc9a533ebbc0e1d29c3ec8afbe61f">RTE_TRAP_L_MISALIGNED</a></div><div class="ttdeci">@ RTE_TRAP_L_MISALIGNED</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:36</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa931a4f314b04233924b01e8245153be4"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa931a4f314b04233924b01e8245153be4">RTE_TRAP_I_ACCESS</a></div><div class="ttdeci">@ RTE_TRAP_I_ACCESS</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:32</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aa97047b024b72807a0b312979c9359dab"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aa97047b024b72807a0b312979c9359dab">RTE_TRAP_L_ACCESS</a></div><div class="ttdeci">@ RTE_TRAP_L_ACCESS</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:37</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aaa9b8334712ecad0500c7610a25741ec7"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaa9b8334712ecad0500c7610a25741ec7">RTE_TRAP_S_ACCESS</a></div><div class="ttdeci">@ RTE_TRAP_S_ACCESS</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:39</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aaadd66d9b9c33a6869fa3c30e1e434313"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaadd66d9b9c33a6869fa3c30e1e434313">RTE_TRAP_FIRQ_14</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_14</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:59</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aab199b53a1458017fa5278e0aeecf41fd"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab199b53a1458017fa5278e0aeecf41fd">RTE_TRAP_FIRQ_1</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_1</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:46</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aab36a403cd7b833439ce7f9a708c33922"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab36a403cd7b833439ce7f9a708c33922">RTE_TRAP_FIRQ_0</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_0</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:45</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aab49ff0110481f22da22a085d2633a0e0"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aab49ff0110481f22da22a085d2633a0e0">RTE_TRAP_FIRQ_11</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_11</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:56</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aac9fb28ea8bafff182f12c29d2fad6998"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aac9fb28ea8bafff182f12c29d2fad6998">RTE_TRAP_FIRQ_6</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_6</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:51</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aacf17d4b2454c43a1cb544e532d247fff"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aacf17d4b2454c43a1cb544e532d247fff">RTE_TRAP_MTI</a></div><div class="ttdeci">@ RTE_TRAP_MTI</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:43</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aad2a55d5586d33497fd21b1da8aa98fff"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aad2a55d5586d33497fd21b1da8aa98fff">RTE_TRAP_MEI</a></div><div class="ttdeci">@ RTE_TRAP_MEI</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:44</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aadddffa9acdfcce80dd68ad4b26725174"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aadddffa9acdfcce80dd68ad4b26725174">RTE_TRAP_MSI</a></div><div class="ttdeci">@ RTE_TRAP_MSI</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:42</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aadebcc4d91aea1364b1481111f1060c52"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aadebcc4d91aea1364b1481111f1060c52">RTE_TRAP_FIRQ_10</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_10</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:55</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aaea6027bf0354c3120fa61c8094dd7a1d"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaea6027bf0354c3120fa61c8094dd7a1d">RTE_TRAP_MENV_CALL</a></div><div class="ttdeci">@ RTE_TRAP_MENV_CALL</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:41</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aaecea4f1d524a33d02324382357b2bcb9"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaecea4f1d524a33d02324382357b2bcb9">RTE_TRAP_FIRQ_12</a></div><div class="ttdeci">@ RTE_TRAP_FIRQ_12</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:57</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ad28f86ab02d89ade2f0bc12e0a8ca70aaf647ff8d55d021379202879627c91d81"><div class="ttname"><a href="neorv32__rte_8h.html#ad28f86ab02d89ade2f0bc12e0a8ca70aaf647ff8d55d021379202879627c91d81">RTE_TRAP_I_MISALIGNED</a></div><div class="ttdeci">@ RTE_TRAP_I_MISALIGNED</div><div class="ttdef"><b>Definition</b> neorv32_rte.h:34</div></div> +<div class="ttc" id="aneorv32__rte_8h_html_ae13a9c1fd59ad71afb0d47cf9a0b303e"><div class="ttname"><a href="neorv32__rte_8h.html#ae13a9c1fd59ad71afb0d47cf9a0b303e">neorv32_rte_context_put</a></div><div class="ttdeci">void neorv32_rte_context_put(int x, uint32_t data)</div><div class="ttdef"><b>Definition</b> neorv32_rte.c:280</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__sdi_8c.html b/sw/neorv32__sdi_8c.html new file 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href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_sdi.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Serial data interface controller (SDI) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a51412722efdb18cd09667622b215e825" id="r_a51412722efdb18cd09667622b215e825"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a51412722efdb18cd09667622b215e825">neorv32_sdi_available</a> (void)</td></tr> +<tr class="separator:a51412722efdb18cd09667622b215e825"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a3246118dc0d7e1f61bc2485bbab44149" id="r_a3246118dc0d7e1f61bc2485bbab44149"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3246118dc0d7e1f61bc2485bbab44149">neorv32_sdi_setup</a> (uint32_t irq_mask)</td></tr> +<tr class="separator:a3246118dc0d7e1f61bc2485bbab44149"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8bd54bca8aea6147651c8115ee616f54" id="r_a8bd54bca8aea6147651c8115ee616f54"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8bd54bca8aea6147651c8115ee616f54">neorv32_sdi_disable</a> (void)</td></tr> +<tr class="separator:a8bd54bca8aea6147651c8115ee616f54"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5d68b9b1642baf3519076e55a22a8f61" id="r_a5d68b9b1642baf3519076e55a22a8f61"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5d68b9b1642baf3519076e55a22a8f61">neorv32_sdi_enable</a> (void)</td></tr> +<tr class="separator:a5d68b9b1642baf3519076e55a22a8f61"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7390faeb01b4de3dd5ac18335736b90c" id="r_a7390faeb01b4de3dd5ac18335736b90c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7390faeb01b4de3dd5ac18335736b90c">neorv32_sdi_get_fifo_depth</a> (void)</td></tr> +<tr class="separator:a7390faeb01b4de3dd5ac18335736b90c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac7a262d16c42bbac27723ff779545569" id="r_ac7a262d16c42bbac27723ff779545569"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac7a262d16c42bbac27723ff779545569">neorv32_sdi_put</a> (uint8_t data)</td></tr> +<tr class="separator:ac7a262d16c42bbac27723ff779545569"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4d54ce22ec97eb83da118439576e3277" id="r_a4d54ce22ec97eb83da118439576e3277"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4d54ce22ec97eb83da118439576e3277">neorv32_sdi_get</a> (uint8_t *data)</td></tr> +<tr class="separator:a4d54ce22ec97eb83da118439576e3277"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2636cf1959ce1f3eb4b77c00ca2e2707" id="r_a2636cf1959ce1f3eb4b77c00ca2e2707"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2636cf1959ce1f3eb4b77c00ca2e2707">neorv32_sdi_check_cs</a> (void)</td></tr> +<tr class="separator:a2636cf1959ce1f3eb4b77c00ca2e2707"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Serial data interface controller (SDI) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the SDI unit was synthesized (IO_SDI_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a51412722efdb18cd09667622b215e825" name="a51412722efdb18cd09667622b215e825"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a51412722efdb18cd09667622b215e825">&#9670;&#160;</a></span>neorv32_sdi_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if SDI unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if SDI was not synthesized, 1 if SPI is available. </dd></dl> + +</div> +</div> +<a id="a2636cf1959ce1f3eb4b77c00ca2e2707" name="a2636cf1959ce1f3eb4b77c00ca2e2707"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2636cf1959ce1f3eb4b77c00ca2e2707">&#9670;&#160;</a></span>neorv32_sdi_check_cs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_check_cs </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get status of chip-select line.</p> +<dl class="section return"><dt>Returns</dt><dd>1 if chip-select line is enabled/active (driven low), 0 otherwise. </dd></dl> + +</div> +</div> +<a id="a8bd54bca8aea6147651c8115ee616f54" name="a8bd54bca8aea6147651c8115ee616f54"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8bd54bca8aea6147651c8115ee616f54">&#9670;&#160;</a></span>neorv32_sdi_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_sdi_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable SDI controller. </p> + +</div> +</div> +<a id="a5d68b9b1642baf3519076e55a22a8f61" name="a5d68b9b1642baf3519076e55a22a8f61"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5d68b9b1642baf3519076e55a22a8f61">&#9670;&#160;</a></span>neorv32_sdi_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_sdi_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable SDI controller. </p> + +</div> +</div> +<a id="a4d54ce22ec97eb83da118439576e3277" name="a4d54ce22ec97eb83da118439576e3277"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4d54ce22ec97eb83da118439576e3277">&#9670;&#160;</a></span>neorv32_sdi_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_get </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get data from SDI input FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">Pointer</td><td>fro data byte read from RX FIFO. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>-1 if RX FIFO is empty, 0 if success. </dd></dl> + +</div> +</div> +<a id="a7390faeb01b4de3dd5ac18335736b90c" name="a7390faeb01b4de3dd5ac18335736b90c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7390faeb01b4de3dd5ac18335736b90c">&#9670;&#160;</a></span>neorv32_sdi_get_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_get_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get SDI FIFO depth.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries), 1 if no FIFO implemented </dd></dl> + +</div> +</div> +<a id="ac7a262d16c42bbac27723ff779545569" name="ac7a262d16c42bbac27723ff779545569"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac7a262d16c42bbac27723ff779545569">&#9670;&#160;</a></span>neorv32_sdi_put()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_put </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Push data to SDI output FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>Byte to push into TX FIFO. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>-1 if TX FIFO is full, 0 if success. </dd></dl> + +</div> +</div> +<a id="a3246118dc0d7e1f61bc2485bbab44149" name="a3246118dc0d7e1f61bc2485bbab44149"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3246118dc0d7e1f61bc2485bbab44149">&#9670;&#160;</a></span>neorv32_sdi_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_sdi_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>irq_mask</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, enable and configure SDI controller. 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Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Serial data interface controller (SPPI) HW driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__sdi_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__sdi__t.html">neorv32_sdi_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:a51412722efdb18cd09667622b215e825" id="r_a51412722efdb18cd09667622b215e825"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a51412722efdb18cd09667622b215e825">neorv32_sdi_available</a> (void)</td></tr> +<tr class="separator:a51412722efdb18cd09667622b215e825"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a3246118dc0d7e1f61bc2485bbab44149" id="r_a3246118dc0d7e1f61bc2485bbab44149"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3246118dc0d7e1f61bc2485bbab44149">neorv32_sdi_setup</a> (uint32_t irq_mask)</td></tr> +<tr class="separator:a3246118dc0d7e1f61bc2485bbab44149"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8bd54bca8aea6147651c8115ee616f54" id="r_a8bd54bca8aea6147651c8115ee616f54"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8bd54bca8aea6147651c8115ee616f54">neorv32_sdi_disable</a> (void)</td></tr> +<tr class="separator:a8bd54bca8aea6147651c8115ee616f54"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5d68b9b1642baf3519076e55a22a8f61" id="r_a5d68b9b1642baf3519076e55a22a8f61"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5d68b9b1642baf3519076e55a22a8f61">neorv32_sdi_enable</a> (void)</td></tr> +<tr class="separator:a5d68b9b1642baf3519076e55a22a8f61"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7390faeb01b4de3dd5ac18335736b90c" id="r_a7390faeb01b4de3dd5ac18335736b90c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7390faeb01b4de3dd5ac18335736b90c">neorv32_sdi_get_fifo_depth</a> (void)</td></tr> +<tr class="separator:a7390faeb01b4de3dd5ac18335736b90c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac7a262d16c42bbac27723ff779545569" id="r_ac7a262d16c42bbac27723ff779545569"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac7a262d16c42bbac27723ff779545569">neorv32_sdi_put</a> (uint8_t data)</td></tr> +<tr class="separator:ac7a262d16c42bbac27723ff779545569"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4d54ce22ec97eb83da118439576e3277" id="r_a4d54ce22ec97eb83da118439576e3277"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4d54ce22ec97eb83da118439576e3277">neorv32_sdi_get</a> (uint8_t *data)</td></tr> +<tr class="separator:a4d54ce22ec97eb83da118439576e3277"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2636cf1959ce1f3eb4b77c00ca2e2707" id="r_a2636cf1959ce1f3eb4b77c00ca2e2707"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2636cf1959ce1f3eb4b77c00ca2e2707">neorv32_sdi_check_cs</a> (void)</td></tr> +<tr class="separator:a2636cf1959ce1f3eb4b77c00ca2e2707"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Serial Data Interface (SDI)</h2></td></tr> +<tr class="memitem:afd0921633d6523d9b7235055e9bbf928" id="r_afd0921633d6523d9b7235055e9bbf928"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afd0921633d6523d9b7235055e9bbf928">NEORV32_SDI</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__sdi__t.html">neorv32_sdi_t</a>*) (<a class="el" href="neorv32_8h.html#a9b316ec038bd94ada42c9dab57a0a3cb">NEORV32_SDI_BASE</a>))</td></tr> +<tr class="separator:afd0921633d6523d9b7235055e9bbf928"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abad9f422cbdff1b73100e98f7ab20ec6" id="r_abad9f422cbdff1b73100e98f7ab20ec6"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6">NEORV32_SDI_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6af6016d120844c2d8d8da4fccc09f9809">SDI_CTRL_EN</a> = 0 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6a840c74518f55028608e2353ec6ce58c4">SDI_CTRL_FIFO_LSB</a> = 4 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6ab3b57f906bd3fc16242fa06601ce1716">SDI_CTRL_FIFO_MSB</a> = 7 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6a2a611e339fd9ae7854931743802ff5c0">SDI_CTRL_IRQ_RX_AVAIL</a> = 15 +, <br /> +&#160;&#160;<a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6af1e2abec3b3bc2ff9ecb2698d933a281">SDI_CTRL_IRQ_RX_HALF</a> = 16 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6a051d69f43c2b0f15c5e9e9252c906c9d">SDI_CTRL_IRQ_RX_FULL</a> = 17 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6a5df074faedb03cf3cc0cfa90eaccd210">SDI_CTRL_IRQ_TX_EMPTY</a> = 18 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6a762237a6107ee690276c36108fa1c1ed">SDI_CTRL_IRQ_TX_NHALF</a> = 19 +, <br /> +&#160;&#160;<a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6ae15186a46909f1a957269b21af6a14a0">SDI_CTRL_RX_AVAIL</a> = 23 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6ac9381cffb4da427baf31cdbbeae5e1f4">SDI_CTRL_RX_HALF</a> = 24 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6a45ade3854c01dc1b14a80e3fea29417a">SDI_CTRL_RX_FULL</a> = 25 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6aa9b89463a37e3a9c554195c2f87fb8d8">SDI_CTRL_TX_EMPTY</a> = 26 +, <br /> +&#160;&#160;<a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6aeac16a67f250cce5ea420790e80b8bb9">SDI_CTRL_TX_NHALF</a> = 27 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6adb5c4613ce0a6178a01599cf8fd6984a">SDI_CTRL_TX_FULL</a> = 28 +, <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6ad288a52f2bdaa1ea6ddbadf7f32a3a63">SDI_CTRL_CS_ACTIVE</a> = 31 +<br /> + }</td></tr> +<tr class="separator:abad9f422cbdff1b73100e98f7ab20ec6"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Serial data interface controller (SPPI) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the SDI unit was synthesized (IO_SDI_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="afd0921633d6523d9b7235055e9bbf928" name="afd0921633d6523d9b7235055e9bbf928"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afd0921633d6523d9b7235055e9bbf928">&#9670;&#160;</a></span>NEORV32_SDI</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_SDI&#160;&#160;&#160;((<a class="el" href="structneorv32__sdi__t.html">neorv32_sdi_t</a>*) (<a class="el" href="neorv32_8h.html#a9b316ec038bd94ada42c9dab57a0a3cb">NEORV32_SDI_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>SDI module hardware access (<a class="el" href="structneorv32__sdi__t.html">neorv32_sdi_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="abad9f422cbdff1b73100e98f7ab20ec6" name="abad9f422cbdff1b73100e98f7ab20ec6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abad9f422cbdff1b73100e98f7ab20ec6">&#9670;&#160;</a></span>NEORV32_SDI_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6">NEORV32_SDI_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SDI control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6af6016d120844c2d8d8da4fccc09f9809" name="abad9f422cbdff1b73100e98f7ab20ec6af6016d120844c2d8d8da4fccc09f9809"></a>SDI_CTRL_EN&#160;</td><td class="fielddoc"><p>SDI control register(0) (r/w): SID module enable </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6a840c74518f55028608e2353ec6ce58c4" name="abad9f422cbdff1b73100e98f7ab20ec6a840c74518f55028608e2353ec6ce58c4"></a>SDI_CTRL_FIFO_LSB&#160;</td><td class="fielddoc"><p>SDI control register(4) (r/-): log2 of SDI FIFO size, LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6ab3b57f906bd3fc16242fa06601ce1716" name="abad9f422cbdff1b73100e98f7ab20ec6ab3b57f906bd3fc16242fa06601ce1716"></a>SDI_CTRL_FIFO_MSB&#160;</td><td class="fielddoc"><p>SDI control register(7) (r/-): log2 of SDI FIFO size, MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6a2a611e339fd9ae7854931743802ff5c0" name="abad9f422cbdff1b73100e98f7ab20ec6a2a611e339fd9ae7854931743802ff5c0"></a>SDI_CTRL_IRQ_RX_AVAIL&#160;</td><td class="fielddoc"><p>SDI control register(15) (r/w): IRQ when RX FIFO not empty </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6af1e2abec3b3bc2ff9ecb2698d933a281" name="abad9f422cbdff1b73100e98f7ab20ec6af1e2abec3b3bc2ff9ecb2698d933a281"></a>SDI_CTRL_IRQ_RX_HALF&#160;</td><td class="fielddoc"><p>SDI control register(16) (r/w): IRQ when RX FIFO at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6a051d69f43c2b0f15c5e9e9252c906c9d" name="abad9f422cbdff1b73100e98f7ab20ec6a051d69f43c2b0f15c5e9e9252c906c9d"></a>SDI_CTRL_IRQ_RX_FULL&#160;</td><td class="fielddoc"><p>SDI control register(17) (r/w): IRQ when RX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6a5df074faedb03cf3cc0cfa90eaccd210" name="abad9f422cbdff1b73100e98f7ab20ec6a5df074faedb03cf3cc0cfa90eaccd210"></a>SDI_CTRL_IRQ_TX_EMPTY&#160;</td><td class="fielddoc"><p>SDI control register(18) (r/w): IRQ when TX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6a762237a6107ee690276c36108fa1c1ed" name="abad9f422cbdff1b73100e98f7ab20ec6a762237a6107ee690276c36108fa1c1ed"></a>SDI_CTRL_IRQ_TX_NHALF&#160;</td><td class="fielddoc"><p>SDI control register(19) (r/w): IRQ when TX FIFO not at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6ae15186a46909f1a957269b21af6a14a0" name="abad9f422cbdff1b73100e98f7ab20ec6ae15186a46909f1a957269b21af6a14a0"></a>SDI_CTRL_RX_AVAIL&#160;</td><td class="fielddoc"><p>SDI control register(23) (r/-): RX FIFO not empty </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6ac9381cffb4da427baf31cdbbeae5e1f4" name="abad9f422cbdff1b73100e98f7ab20ec6ac9381cffb4da427baf31cdbbeae5e1f4"></a>SDI_CTRL_RX_HALF&#160;</td><td class="fielddoc"><p>SDI control register(24) (r/-): RX FIFO at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6a45ade3854c01dc1b14a80e3fea29417a" name="abad9f422cbdff1b73100e98f7ab20ec6a45ade3854c01dc1b14a80e3fea29417a"></a>SDI_CTRL_RX_FULL&#160;</td><td class="fielddoc"><p>SDI control register(25) (r/-): RX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6aa9b89463a37e3a9c554195c2f87fb8d8" name="abad9f422cbdff1b73100e98f7ab20ec6aa9b89463a37e3a9c554195c2f87fb8d8"></a>SDI_CTRL_TX_EMPTY&#160;</td><td class="fielddoc"><p>SDI control register(26) (r/-): TX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6aeac16a67f250cce5ea420790e80b8bb9" name="abad9f422cbdff1b73100e98f7ab20ec6aeac16a67f250cce5ea420790e80b8bb9"></a>SDI_CTRL_TX_NHALF&#160;</td><td class="fielddoc"><p>SDI control register(27) (r/-): TX FIFO not at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6adb5c4613ce0a6178a01599cf8fd6984a" name="abad9f422cbdff1b73100e98f7ab20ec6adb5c4613ce0a6178a01599cf8fd6984a"></a>SDI_CTRL_TX_FULL&#160;</td><td class="fielddoc"><p>SDI control register(28) (r/-): TX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="abad9f422cbdff1b73100e98f7ab20ec6ad288a52f2bdaa1ea6ddbadf7f32a3a63" name="abad9f422cbdff1b73100e98f7ab20ec6ad288a52f2bdaa1ea6ddbadf7f32a3a63"></a>SDI_CTRL_CS_ACTIVE&#160;</td><td class="fielddoc"><p>SDI control register(31) (r/-): Chip-select is active when set </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a51412722efdb18cd09667622b215e825" name="a51412722efdb18cd09667622b215e825"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a51412722efdb18cd09667622b215e825">&#9670;&#160;</a></span>neorv32_sdi_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if SDI unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if SDI was not synthesized, 1 if SPI is available. </dd></dl> + +</div> +</div> +<a id="a2636cf1959ce1f3eb4b77c00ca2e2707" name="a2636cf1959ce1f3eb4b77c00ca2e2707"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2636cf1959ce1f3eb4b77c00ca2e2707">&#9670;&#160;</a></span>neorv32_sdi_check_cs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_check_cs </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get status of chip-select line.</p> +<dl class="section return"><dt>Returns</dt><dd>1 if chip-select line is enabled/active (driven low), 0 otherwise. </dd></dl> + +</div> +</div> +<a id="a8bd54bca8aea6147651c8115ee616f54" name="a8bd54bca8aea6147651c8115ee616f54"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8bd54bca8aea6147651c8115ee616f54">&#9670;&#160;</a></span>neorv32_sdi_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_sdi_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable SDI controller. </p> + +</div> +</div> +<a id="a5d68b9b1642baf3519076e55a22a8f61" name="a5d68b9b1642baf3519076e55a22a8f61"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5d68b9b1642baf3519076e55a22a8f61">&#9670;&#160;</a></span>neorv32_sdi_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_sdi_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable SDI controller. </p> + +</div> +</div> +<a id="a4d54ce22ec97eb83da118439576e3277" name="a4d54ce22ec97eb83da118439576e3277"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4d54ce22ec97eb83da118439576e3277">&#9670;&#160;</a></span>neorv32_sdi_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_get </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get data from SDI input FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">Pointer</td><td>fro data byte read from RX FIFO. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>-1 if RX FIFO is empty, 0 if success. </dd></dl> + +</div> +</div> +<a id="a7390faeb01b4de3dd5ac18335736b90c" name="a7390faeb01b4de3dd5ac18335736b90c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7390faeb01b4de3dd5ac18335736b90c">&#9670;&#160;</a></span>neorv32_sdi_get_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_get_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get SDI FIFO depth.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries), 1 if no FIFO implemented </dd></dl> + +</div> +</div> +<a id="ac7a262d16c42bbac27723ff779545569" name="ac7a262d16c42bbac27723ff779545569"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac7a262d16c42bbac27723ff779545569">&#9670;&#160;</a></span>neorv32_sdi_put()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_sdi_put </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Push data to SDI output FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>Byte to push into TX FIFO. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>-1 if TX FIFO is full, 0 if success. </dd></dl> + +</div> +</div> +<a id="a3246118dc0d7e1f61bc2485bbab44149" name="a3246118dc0d7e1f61bc2485bbab44149"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3246118dc0d7e1f61bc2485bbab44149">&#9670;&#160;</a></span>neorv32_sdi_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_sdi_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>irq_mask</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, enable and configure SDI controller. The SDI control register bits are listed in <a class="el" href="#abad9f422cbdff1b73100e98f7ab20ec6">NEORV32_SDI_CTRL_enum</a>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mask</td><td>Interrupt configuration mask (CTRL's irq_* bits). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__sdi_8h_source.html b/sw/neorv32__sdi_8h_source.html new file mode 100644 index 000000000..e2eb64065 --- /dev/null +++ b/sw/neorv32__sdi_8h_source.html @@ -0,0 +1,183 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_sdi.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_sdi_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_sdi_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__sdi__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__sdi__t.html#af494f25cbcd8478cf384eb868e447303"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__sdi__t.html#af494f25cbcd8478cf384eb868e447303">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__sdi__t.html#a3ea6903c0924d0a1b633b6a2b0ae44f1"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__sdi__t.html#a3ea6903c0924d0a1b633b6a2b0ae44f1">DATA</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__sdi__t.html">neorv32_sdi_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#afd0921633d6523d9b7235055e9bbf928"> 35</a></span><span class="preprocessor">#define NEORV32_SDI ((neorv32_sdi_t*) (NEORV32_SDI_BASE))</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="foldopen" id="foldopen00038" data-start="{" data-end="};"> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6"> 38</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6">NEORV32_SDI_CTRL_enum</a> {</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6af6016d120844c2d8d8da4fccc09f9809"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6af6016d120844c2d8d8da4fccc09f9809">SDI_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a840c74518f55028608e2353ec6ce58c4"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a840c74518f55028608e2353ec6ce58c4">SDI_CTRL_FIFO_LSB</a> = 4, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ab3b57f906bd3fc16242fa06601ce1716"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ab3b57f906bd3fc16242fa06601ce1716">SDI_CTRL_FIFO_MSB</a> = 7, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a2a611e339fd9ae7854931743802ff5c0"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a2a611e339fd9ae7854931743802ff5c0">SDI_CTRL_IRQ_RX_AVAIL</a> = 15, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6af1e2abec3b3bc2ff9ecb2698d933a281"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6af1e2abec3b3bc2ff9ecb2698d933a281">SDI_CTRL_IRQ_RX_HALF</a> = 16, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a051d69f43c2b0f15c5e9e9252c906c9d"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a051d69f43c2b0f15c5e9e9252c906c9d">SDI_CTRL_IRQ_RX_FULL</a> = 17, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a5df074faedb03cf3cc0cfa90eaccd210"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a5df074faedb03cf3cc0cfa90eaccd210">SDI_CTRL_IRQ_TX_EMPTY</a> = 18, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a762237a6107ee690276c36108fa1c1ed"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a762237a6107ee690276c36108fa1c1ed">SDI_CTRL_IRQ_TX_NHALF</a> = 19, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ae15186a46909f1a957269b21af6a14a0"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ae15186a46909f1a957269b21af6a14a0">SDI_CTRL_RX_AVAIL</a> = 23, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ac9381cffb4da427baf31cdbbeae5e1f4"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ac9381cffb4da427baf31cdbbeae5e1f4">SDI_CTRL_RX_HALF</a> = 24, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a45ade3854c01dc1b14a80e3fea29417a"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a45ade3854c01dc1b14a80e3fea29417a">SDI_CTRL_RX_FULL</a> = 25, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6aa9b89463a37e3a9c554195c2f87fb8d8"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6aa9b89463a37e3a9c554195c2f87fb8d8">SDI_CTRL_TX_EMPTY</a> = 26, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6aeac16a67f250cce5ea420790e80b8bb9"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6aeac16a67f250cce5ea420790e80b8bb9">SDI_CTRL_TX_NHALF</a> = 27, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6adb5c4613ce0a6178a01599cf8fd6984a"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6adb5c4613ce0a6178a01599cf8fd6984a">SDI_CTRL_TX_FULL</a> = 28, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span> <a class="code hl_enumvalue" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ad288a52f2bdaa1ea6ddbadf7f32a3a63">SDI_CTRL_CS_ACTIVE</a> = 31 </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ad288a52f2bdaa1ea6ddbadf7f32a3a63"> 58</a></span>};</div> +</div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__sdi_8h.html#a51412722efdb18cd09667622b215e825">neorv32_sdi_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__sdi_8h.html#a3246118dc0d7e1f61bc2485bbab44149">neorv32_sdi_setup</a>(uint32_t irq_mask);</div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__sdi_8h.html#a8bd54bca8aea6147651c8115ee616f54">neorv32_sdi_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__sdi_8h.html#a5d68b9b1642baf3519076e55a22a8f61">neorv32_sdi_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__sdi_8h.html#a7390faeb01b4de3dd5ac18335736b90c">neorv32_sdi_get_fifo_depth</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__sdi_8h.html#ac7a262d16c42bbac27723ff779545569">neorv32_sdi_put</a>(uint8_t data);</div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__sdi_8h.html#a4d54ce22ec97eb83da118439576e3277">neorv32_sdi_get</a>(uint8_t* data);</div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__sdi_8h.html#a2636cf1959ce1f3eb4b77c00ca2e2707">neorv32_sdi_check_cs</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_sdi_h</span></div> +<div class="ttc" id="aneorv32__sdi_8h_html_a2636cf1959ce1f3eb4b77c00ca2e2707"><div class="ttname"><a href="neorv32__sdi_8h.html#a2636cf1959ce1f3eb4b77c00ca2e2707">neorv32_sdi_check_cs</a></div><div class="ttdeci">int neorv32_sdi_check_cs(void)</div><div class="ttdef"><b>Definition</b> neorv32_sdi.c:126</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_a3246118dc0d7e1f61bc2485bbab44149"><div class="ttname"><a href="neorv32__sdi_8h.html#a3246118dc0d7e1f61bc2485bbab44149">neorv32_sdi_setup</a></div><div class="ttdeci">void neorv32_sdi_setup(uint32_t irq_mask)</div><div class="ttdef"><b>Definition</b> neorv32_sdi.c:43</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_a4d54ce22ec97eb83da118439576e3277"><div class="ttname"><a href="neorv32__sdi_8h.html#a4d54ce22ec97eb83da118439576e3277">neorv32_sdi_get</a></div><div class="ttdeci">int neorv32_sdi_get(uint8_t *data)</div><div class="ttdef"><b>Definition</b> neorv32_sdi.c:109</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_a51412722efdb18cd09667622b215e825"><div class="ttname"><a href="neorv32__sdi_8h.html#a51412722efdb18cd09667622b215e825">neorv32_sdi_available</a></div><div class="ttdeci">int neorv32_sdi_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_sdi.c:26</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_a5d68b9b1642baf3519076e55a22a8f61"><div class="ttname"><a href="neorv32__sdi_8h.html#a5d68b9b1642baf3519076e55a22a8f61">neorv32_sdi_enable</a></div><div class="ttdeci">void neorv32_sdi_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_sdi.c:67</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_a7390faeb01b4de3dd5ac18335736b90c"><div class="ttname"><a href="neorv32__sdi_8h.html#a7390faeb01b4de3dd5ac18335736b90c">neorv32_sdi_get_fifo_depth</a></div><div class="ttdeci">int neorv32_sdi_get_fifo_depth(void)</div><div class="ttdef"><b>Definition</b> neorv32_sdi.c:78</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_a8bd54bca8aea6147651c8115ee616f54"><div class="ttname"><a href="neorv32__sdi_8h.html#a8bd54bca8aea6147651c8115ee616f54">neorv32_sdi_disable</a></div><div class="ttdeci">void neorv32_sdi_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_sdi.c:58</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6">NEORV32_SDI_CTRL_enum</a></div><div class="ttdeci">NEORV32_SDI_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:38</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6a051d69f43c2b0f15c5e9e9252c906c9d"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a051d69f43c2b0f15c5e9e9252c906c9d">SDI_CTRL_IRQ_RX_FULL</a></div><div class="ttdeci">@ SDI_CTRL_IRQ_RX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:46</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6a2a611e339fd9ae7854931743802ff5c0"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a2a611e339fd9ae7854931743802ff5c0">SDI_CTRL_IRQ_RX_AVAIL</a></div><div class="ttdeci">@ SDI_CTRL_IRQ_RX_AVAIL</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:44</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6a45ade3854c01dc1b14a80e3fea29417a"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a45ade3854c01dc1b14a80e3fea29417a">SDI_CTRL_RX_FULL</a></div><div class="ttdeci">@ SDI_CTRL_RX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:52</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6a5df074faedb03cf3cc0cfa90eaccd210"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a5df074faedb03cf3cc0cfa90eaccd210">SDI_CTRL_IRQ_TX_EMPTY</a></div><div class="ttdeci">@ SDI_CTRL_IRQ_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:47</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6a762237a6107ee690276c36108fa1c1ed"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a762237a6107ee690276c36108fa1c1ed">SDI_CTRL_IRQ_TX_NHALF</a></div><div class="ttdeci">@ SDI_CTRL_IRQ_TX_NHALF</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:48</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6a840c74518f55028608e2353ec6ce58c4"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6a840c74518f55028608e2353ec6ce58c4">SDI_CTRL_FIFO_LSB</a></div><div class="ttdeci">@ SDI_CTRL_FIFO_LSB</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:41</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6aa9b89463a37e3a9c554195c2f87fb8d8"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6aa9b89463a37e3a9c554195c2f87fb8d8">SDI_CTRL_TX_EMPTY</a></div><div class="ttdeci">@ SDI_CTRL_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:53</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6ab3b57f906bd3fc16242fa06601ce1716"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ab3b57f906bd3fc16242fa06601ce1716">SDI_CTRL_FIFO_MSB</a></div><div class="ttdeci">@ SDI_CTRL_FIFO_MSB</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:42</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6ac9381cffb4da427baf31cdbbeae5e1f4"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ac9381cffb4da427baf31cdbbeae5e1f4">SDI_CTRL_RX_HALF</a></div><div class="ttdeci">@ SDI_CTRL_RX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:51</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6ad288a52f2bdaa1ea6ddbadf7f32a3a63"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ad288a52f2bdaa1ea6ddbadf7f32a3a63">SDI_CTRL_CS_ACTIVE</a></div><div class="ttdeci">@ SDI_CTRL_CS_ACTIVE</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:57</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6adb5c4613ce0a6178a01599cf8fd6984a"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6adb5c4613ce0a6178a01599cf8fd6984a">SDI_CTRL_TX_FULL</a></div><div class="ttdeci">@ SDI_CTRL_TX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:55</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6ae15186a46909f1a957269b21af6a14a0"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6ae15186a46909f1a957269b21af6a14a0">SDI_CTRL_RX_AVAIL</a></div><div class="ttdeci">@ SDI_CTRL_RX_AVAIL</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:50</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6aeac16a67f250cce5ea420790e80b8bb9"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6aeac16a67f250cce5ea420790e80b8bb9">SDI_CTRL_TX_NHALF</a></div><div class="ttdeci">@ SDI_CTRL_TX_NHALF</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:54</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6af1e2abec3b3bc2ff9ecb2698d933a281"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6af1e2abec3b3bc2ff9ecb2698d933a281">SDI_CTRL_IRQ_RX_HALF</a></div><div class="ttdeci">@ SDI_CTRL_IRQ_RX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:45</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_abad9f422cbdff1b73100e98f7ab20ec6af6016d120844c2d8d8da4fccc09f9809"><div class="ttname"><a href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6af6016d120844c2d8d8da4fccc09f9809">SDI_CTRL_EN</a></div><div class="ttdeci">@ SDI_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:39</div></div> +<div class="ttc" id="aneorv32__sdi_8h_html_ac7a262d16c42bbac27723ff779545569"><div class="ttname"><a href="neorv32__sdi_8h.html#ac7a262d16c42bbac27723ff779545569">neorv32_sdi_put</a></div><div class="ttdeci">int neorv32_sdi_put(uint8_t data)</div><div class="ttdef"><b>Definition</b> neorv32_sdi.c:91</div></div> +<div class="ttc" id="astructneorv32__sdi__t_html"><div class="ttname"><a href="structneorv32__sdi__t.html">neorv32_sdi_t</a></div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:29</div></div> +<div class="ttc" id="astructneorv32__sdi__t_html_a3ea6903c0924d0a1b633b6a2b0ae44f1"><div class="ttname"><a href="structneorv32__sdi__t.html#a3ea6903c0924d0a1b633b6a2b0ae44f1">neorv32_sdi_t::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:31</div></div> +<div class="ttc" id="astructneorv32__sdi__t_html_af494f25cbcd8478cf384eb868e447303"><div class="ttname"><a href="structneorv32__sdi__t.html#af494f25cbcd8478cf384eb868e447303">neorv32_sdi_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_sdi.h:30</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__slink_8c.html b/sw/neorv32__slink_8c.html new file mode 100644 index 000000000..bb426f9be --- /dev/null +++ b/sw/neorv32__slink_8c.html @@ -0,0 +1,485 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Stream Link Interface HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:aaf0f7bc96b797e819ccaae94292d9ddb" id="r_aaf0f7bc96b797e819ccaae94292d9ddb"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aaf0f7bc96b797e819ccaae94292d9ddb">neorv32_slink_available</a> (void)</td></tr> +<tr class="separator:aaf0f7bc96b797e819ccaae94292d9ddb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8f0b4a768f53a72a5c16034e160ce321" id="r_a8f0b4a768f53a72a5c16034e160ce321"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8f0b4a768f53a72a5c16034e160ce321">neorv32_slink_setup</a> (uint32_t rx_irq, uint32_t tx_irq)</td></tr> +<tr class="separator:a8f0b4a768f53a72a5c16034e160ce321"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad149fea81e6d28f77450b8ba50cf706e" id="r_ad149fea81e6d28f77450b8ba50cf706e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad149fea81e6d28f77450b8ba50cf706e">neorv32_slink_rx_clear</a> (void)</td></tr> +<tr class="separator:ad149fea81e6d28f77450b8ba50cf706e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac7484e9e3848f94efe016dd064f6a57f" id="r_ac7484e9e3848f94efe016dd064f6a57f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac7484e9e3848f94efe016dd064f6a57f">neorv32_slink_tx_clear</a> (void)</td></tr> +<tr class="separator:ac7484e9e3848f94efe016dd064f6a57f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a575c7663ca0bd07c95b1d45152a3ddf8" id="r_a575c7663ca0bd07c95b1d45152a3ddf8"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a575c7663ca0bd07c95b1d45152a3ddf8">neorv32_slink_get_rx_fifo_depth</a> (void)</td></tr> +<tr class="separator:a575c7663ca0bd07c95b1d45152a3ddf8"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aaf0d0d1b890353d4f3bf49450ec2fad2" id="r_aaf0d0d1b890353d4f3bf49450ec2fad2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aaf0d0d1b890353d4f3bf49450ec2fad2">neorv32_slink_get_tx_fifo_depth</a> (void)</td></tr> +<tr class="separator:aaf0d0d1b890353d4f3bf49450ec2fad2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ace319592c12dc6a0fe1b7dd66bdf9284" id="r_ace319592c12dc6a0fe1b7dd66bdf9284"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ace319592c12dc6a0fe1b7dd66bdf9284">neorv32_slink_get</a> (void)</td></tr> +<tr class="separator:ace319592c12dc6a0fe1b7dd66bdf9284"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a3e02c558548c1c6178c49adee9a007f7" id="r_a3e02c558548c1c6178c49adee9a007f7"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3e02c558548c1c6178c49adee9a007f7">neorv32_slink_check_last</a> (void)</td></tr> +<tr class="separator:a3e02c558548c1c6178c49adee9a007f7"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad857d7e78ca2b5eb0d0a4f2c515fe7bc" id="r_ad857d7e78ca2b5eb0d0a4f2c515fe7bc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad857d7e78ca2b5eb0d0a4f2c515fe7bc">neorv32_slink_set_dst</a> (uint32_t dst)</td></tr> +<tr class="separator:ad857d7e78ca2b5eb0d0a4f2c515fe7bc"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1a9269f42552a849450aecd99f7ec7a0" id="r_a1a9269f42552a849450aecd99f7ec7a0"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1a9269f42552a849450aecd99f7ec7a0">neorv32_slink_get_src</a> (void)</td></tr> +<tr class="separator:a1a9269f42552a849450aecd99f7ec7a0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aaa9fdb9cbfa7888e92790ab65431d21d" id="r_aaa9fdb9cbfa7888e92790ab65431d21d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aaa9fdb9cbfa7888e92790ab65431d21d">neorv32_slink_put</a> (uint32_t tx_data)</td></tr> +<tr class="separator:aaa9fdb9cbfa7888e92790ab65431d21d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2136bc0b12ee2e6703e84a6417a1e8eb" id="r_a2136bc0b12ee2e6703e84a6417a1e8eb"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2136bc0b12ee2e6703e84a6417a1e8eb">neorv32_slink_put_last</a> (uint32_t tx_data)</td></tr> +<tr class="separator:a2136bc0b12ee2e6703e84a6417a1e8eb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad57fc0941fe32e8bf423ce3e57e2c10a" id="r_ad57fc0941fe32e8bf423ce3e57e2c10a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad57fc0941fe32e8bf423ce3e57e2c10a">neorv32_slink_rx_status</a> (void)</td></tr> +<tr class="separator:ad57fc0941fe32e8bf423ce3e57e2c10a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad0252e7ae915e5840cd17e8c52e94a1c" id="r_ad0252e7ae915e5840cd17e8c52e94a1c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad0252e7ae915e5840cd17e8c52e94a1c">neorv32_slink_tx_status</a> (void)</td></tr> +<tr class="separator:ad0252e7ae915e5840cd17e8c52e94a1c"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Stream Link Interface HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the SLINK unit was synthesized (IO_SLINK_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="aaf0f7bc96b797e819ccaae94292d9ddb" name="aaf0f7bc96b797e819ccaae94292d9ddb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaf0f7bc96b797e819ccaae94292d9ddb">&#9670;&#160;</a></span>neorv32_slink_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_slink_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if stream link interface was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if SLINK was not synthesized, 1 if SLINK is available. </dd></dl> + +</div> +</div> +<a id="a3e02c558548c1c6178c49adee9a007f7" name="a3e02c558548c1c6178c49adee9a007f7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3e02c558548c1c6178c49adee9a007f7">&#9670;&#160;</a></span>neorv32_slink_check_last()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_check_last </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Check if last RX word has "end-of-stream" delimiter.</p> +<dl class="section note"><dt>Note</dt><dd>This needs has to be called AFTER reading the actual data word using <a class="el" href="#ace319592c12dc6a0fe1b7dd66bdf9284">neorv32_slink_get(void)</a>.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if not end of stream, !=0 if end of stream. </dd></dl> + +</div> +</div> +<a id="ace319592c12dc6a0fe1b7dd66bdf9284" name="ace319592c12dc6a0fe1b7dd66bdf9284"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ace319592c12dc6a0fe1b7dd66bdf9284">&#9670;&#160;</a></span>neorv32_slink_get()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Read data from RX link (non-blocking)</p> +<dl class="section return"><dt>Returns</dt><dd>Data received from link. </dd></dl> + +</div> +</div> +<a id="a575c7663ca0bd07c95b1d45152a3ddf8" name="a575c7663ca0bd07c95b1d45152a3ddf8"></a> +<h2 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+ <td class="memname">uint32_t neorv32_slink_get_src </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Get RX link routing source</p> +<dl class="section note"><dt>Note</dt><dd>This needs has to be called AFTER reading the actual data word using <a class="el" href="#ace319592c12dc6a0fe1b7dd66bdf9284">neorv32_slink_get(void)</a>.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>4-bit source routing ID. </dd></dl> + +</div> +</div> +<a id="aaf0d0d1b890353d4f3bf49450ec2fad2" name="aaf0d0d1b890353d4f3bf49450ec2fad2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaf0d0d1b890353d4f3bf49450ec2fad2">&#9670;&#160;</a></span>neorv32_slink_get_tx_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_slink_get_tx_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get FIFO depth of TX link.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth of TX link (1..32768). </dd></dl> + +</div> +</div> +<a id="aaa9fdb9cbfa7888e92790ab65431d21d" name="aaa9fdb9cbfa7888e92790ab65431d21d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaa9fdb9cbfa7888e92790ab65431d21d">&#9670;&#160;</a></span>neorv32_slink_put()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_put </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>tx_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Write data to TX link (non-blocking)</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">tx_data</td><td>Data to send to link. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a2136bc0b12ee2e6703e84a6417a1e8eb" name="a2136bc0b12ee2e6703e84a6417a1e8eb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2136bc0b12ee2e6703e84a6417a1e8eb">&#9670;&#160;</a></span>neorv32_slink_put_last()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_put_last </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td 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class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear RX FIFO. </p> + +</div> +</div> +<a id="ad57fc0941fe32e8bf423ce3e57e2c10a" name="ad57fc0941fe32e8bf423ce3e57e2c10a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad57fc0941fe32e8bf423ce3e57e2c10a">&#9670;&#160;</a></span>neorv32_slink_rx_status()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_slink_rx_status </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get RX link FIFO status.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO status <a class="el" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bf">NEORV32_SLINK_STATUS_enum</a>. </dd></dl> + +</div> +</div> +<a id="ad857d7e78ca2b5eb0d0a4f2c515fe7bc" name="ad857d7e78ca2b5eb0d0a4f2c515fe7bc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad857d7e78ca2b5eb0d0a4f2c515fe7bc">&#9670;&#160;</a></span>neorv32_slink_set_dst()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_set_dst </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>dst</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Set TX link routing destination</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">dst</td><td>Routing destination ID (4-bit, LSB-aligned). </td></tr> + </table> + </dd> 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href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a>). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">tx_irq</td><td>Configure TX interrupt conditions (<a class="el" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a>). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac7484e9e3848f94efe016dd064f6a57f" name="ac7484e9e3848f94efe016dd064f6a57f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac7484e9e3848f94efe016dd064f6a57f">&#9670;&#160;</a></span>neorv32_slink_tx_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_tx_clear </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear TX FIFO. </p> + +</div> +</div> +<a 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href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#nested-classes">Data Structures</a> </div> + <div class="headertitle"><div class="title">neorv32_slink.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Stream Link Interface HW driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__slink_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" 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id="r_ad0252e7ae915e5840cd17e8c52e94a1c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad0252e7ae915e5840cd17e8c52e94a1c">neorv32_slink_tx_status</a> (void)</td></tr> +<tr class="separator:ad0252e7ae915e5840cd17e8c52e94a1c"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Stream Link Interface (SLINK)</h2></td></tr> +<tr class="memitem:a6380d894432de119a20993096db534df" id="r_a6380d894432de119a20993096db534df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6380d894432de119a20993096db534df">NEORV32_SLINK</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__slink__t.html">neorv32_slink_t</a>*) (<a class="el" href="neorv32_8h.html#ab5e6dc57886cd5ed98b86f22fc37d7cc">NEORV32_SLINK_BASE</a>))</td></tr> +<tr class="separator:a6380d894432de119a20993096db534df"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac0385a56c38315d492b3414d98235ef1" id="r_ac0385a56c38315d492b3414d98235ef1"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ac0385a56c38315d492b3414d98235ef1a739187f413b7436dc4037187e4a9e86a">SLINK_CTRL_EN</a> = 0 +, <a class="el" href="#ac0385a56c38315d492b3414d98235ef1a156fa3209b2652af6b58b0fdfc6cab1b">SLINK_CTRL_RX_CLR</a> = 1 +, <a class="el" href="#ac0385a56c38315d492b3414d98235ef1ad366597a44d3dff7dbab4cde72bed82f">SLINK_CTRL_TX_CLR</a> = 2 +, <a class="el" href="#ac0385a56c38315d492b3414d98235ef1a624723683d247668ef44137393e576aa">SLINK_CTRL_RX_LAST</a> = 4 +, <br /> +&#160;&#160;<a class="el" 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+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Stream Link Interface HW driver header file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a6380d894432de119a20993096db534df" name="a6380d894432de119a20993096db534df"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6380d894432de119a20993096db534df">&#9670;&#160;</a></span>NEORV32_SLINK</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_SLINK&#160;&#160;&#160;((<a class="el" href="structneorv32__slink__t.html">neorv32_slink_t</a>*) (<a class="el" href="neorv32_8h.html#ab5e6dc57886cd5ed98b86f22fc37d7cc">NEORV32_SLINK_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>SLINK module hardware access (<a class="el" href="structneorv32__slink__t.html">neorv32_slink_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="ac0385a56c38315d492b3414d98235ef1" name="ac0385a56c38315d492b3414d98235ef1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac0385a56c38315d492b3414d98235ef1">&#9670;&#160;</a></span>NEORV32_SLINK_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SLINK control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a739187f413b7436dc4037187e4a9e86a" name="ac0385a56c38315d492b3414d98235ef1a739187f413b7436dc4037187e4a9e86a"></a>SLINK_CTRL_EN&#160;</td><td class="fielddoc"><p>SLINK control register(0) (r/w): SLINK unit enable </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a156fa3209b2652af6b58b0fdfc6cab1b" name="ac0385a56c38315d492b3414d98235ef1a156fa3209b2652af6b58b0fdfc6cab1b"></a>SLINK_CTRL_RX_CLR&#160;</td><td class="fielddoc"><p>SLINK control register(1) (-/w): Clear RX FIFO, auto-clears </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1ad366597a44d3dff7dbab4cde72bed82f" name="ac0385a56c38315d492b3414d98235ef1ad366597a44d3dff7dbab4cde72bed82f"></a>SLINK_CTRL_TX_CLR&#160;</td><td class="fielddoc"><p>SLINK control register(2) (-/w): Clear TX FIFO, auto-clears </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a624723683d247668ef44137393e576aa" name="ac0385a56c38315d492b3414d98235ef1a624723683d247668ef44137393e576aa"></a>SLINK_CTRL_RX_LAST&#160;</td><td class="fielddoc"><p>SLINK control register(4) (r/-): RX end-of-stream delimiter </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1ae78f82e54bd9d737bbcbc5c7af0e9d4b" name="ac0385a56c38315d492b3414d98235ef1ae78f82e54bd9d737bbcbc5c7af0e9d4b"></a>SLINK_CTRL_RX_EMPTY&#160;</td><td class="fielddoc"><p>SLINK control register(8) (r/-): RX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1af695158b9cf5466d87c207f9bd0a688e" name="ac0385a56c38315d492b3414d98235ef1af695158b9cf5466d87c207f9bd0a688e"></a>SLINK_CTRL_RX_HALF&#160;</td><td class="fielddoc"><p>SLINK control register(9) (r/-): RX FIFO at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1aa7521fbe691fef233c0dff4053e4493e" name="ac0385a56c38315d492b3414d98235ef1aa7521fbe691fef233c0dff4053e4493e"></a>SLINK_CTRL_RX_FULL&#160;</td><td class="fielddoc"><p>SLINK control register(10) (r/-): RX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a308cf7829ecca32f7a3da1bd74339854" name="ac0385a56c38315d492b3414d98235ef1a308cf7829ecca32f7a3da1bd74339854"></a>SLINK_CTRL_TX_EMPTY&#160;</td><td class="fielddoc"><p>SLINK control register(11) (r/-): TX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a530b8b76301f36fbda134b330447de78" name="ac0385a56c38315d492b3414d98235ef1a530b8b76301f36fbda134b330447de78"></a>SLINK_CTRL_TX_HALF&#160;</td><td class="fielddoc"><p>SLINK control register(12) (r/-): TX FIFO at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1af94314ed65c6a8d9c364d99d7ae960ee" name="ac0385a56c38315d492b3414d98235ef1af94314ed65c6a8d9c364d99d7ae960ee"></a>SLINK_CTRL_TX_FULL&#160;</td><td class="fielddoc"><p>SLINK control register(13) (r/-): TX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a5452eab0fe12d174ec804c4c72060854" name="ac0385a56c38315d492b3414d98235ef1a5452eab0fe12d174ec804c4c72060854"></a>SLINK_CTRL_IRQ_RX_NEMPTY&#160;</td><td class="fielddoc"><p>SLINK control register(16) (r/w): RX interrupt if RX FIFO not empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1afa9353cd824d1b2833930ce9e922e392" name="ac0385a56c38315d492b3414d98235ef1afa9353cd824d1b2833930ce9e922e392"></a>SLINK_CTRL_IRQ_RX_HALF&#160;</td><td class="fielddoc"><p>SLINK control register(17) (r/w): RX interrupt if RX FIFO at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1ac8a688706aee72d2027e022b64664309" name="ac0385a56c38315d492b3414d98235ef1ac8a688706aee72d2027e022b64664309"></a>SLINK_CTRL_IRQ_RX_FULL&#160;</td><td class="fielddoc"><p>SLINK control register(18) (r/w): RX interrupt if RX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1ae06ad5f627f8902e2368e0daff6cfa88" name="ac0385a56c38315d492b3414d98235ef1ae06ad5f627f8902e2368e0daff6cfa88"></a>SLINK_CTRL_IRQ_TX_EMPTY&#160;</td><td class="fielddoc"><p>SLINK control register(19) (r/w): TX interrupt if TX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a7bf757dbfb1fdaddceaed3a3887003cf" name="ac0385a56c38315d492b3414d98235ef1a7bf757dbfb1fdaddceaed3a3887003cf"></a>SLINK_CTRL_IRQ_TX_NHALF&#160;</td><td class="fielddoc"><p>SLINK control register(20) (r/w): TX interrupt if TX FIFO not at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a8f994f256f57c006c88b9e38df3f54fa" name="ac0385a56c38315d492b3414d98235ef1a8f994f256f57c006c88b9e38df3f54fa"></a>SLINK_CTRL_IRQ_TX_NFULL&#160;</td><td class="fielddoc"><p>SLINK control register(21) (r/w): TX interrupt if TX FIFO not full </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a9c68af961c1147846929ca55e9e4e88c" name="ac0385a56c38315d492b3414d98235ef1a9c68af961c1147846929ca55e9e4e88c"></a>SLINK_CTRL_RX_FIFO_LSB&#160;</td><td class="fielddoc"><p>SLINK control register(24) (r/-): log2(RX FIFO size) LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1a945e2b7eda65dc13ca38eb21c9c4f657" name="ac0385a56c38315d492b3414d98235ef1a945e2b7eda65dc13ca38eb21c9c4f657"></a>SLINK_CTRL_RX_FIFO_MSB&#160;</td><td class="fielddoc"><p>SLINK control register(27) (r/-): log2(RX FIFO size) MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1aba613343fc17715fc1bb07729588a12d" name="ac0385a56c38315d492b3414d98235ef1aba613343fc17715fc1bb07729588a12d"></a>SLINK_CTRL_TX_FIFO_LSB&#160;</td><td class="fielddoc"><p>SLINK control register(28) (r/-): log2(TX FIFO size) LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="ac0385a56c38315d492b3414d98235ef1af27a9e6e50b169d3f5efd0a08ba4a943" name="ac0385a56c38315d492b3414d98235ef1af27a9e6e50b169d3f5efd0a08ba4a943"></a>SLINK_CTRL_TX_FIFO_MSB&#160;</td><td class="fielddoc"><p>SLINK control register(31) (r/-): log2(TX FIFO size) MSB </p> +</td></tr> +</table> + +</div> +</div> +<a id="ac3e5e02fd89a357135adca6d28cd0e45" name="ac3e5e02fd89a357135adca6d28cd0e45"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac3e5e02fd89a357135adca6d28cd0e45">&#9670;&#160;</a></span>NEORV32_SLINK_ROUTE_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ac3e5e02fd89a357135adca6d28cd0e45">NEORV32_SLINK_ROUTE_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>ROUTE register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ac3e5e02fd89a357135adca6d28cd0e45a9a2311357bd87c85a5cc45f08b0d8f80" name="ac3e5e02fd89a357135adca6d28cd0e45a9a2311357bd87c85a5cc45f08b0d8f80"></a>SLINK_ROUTE_DST_LSB&#160;</td><td class="fielddoc"><p>SLINK routing register(0) (r/w): Destination routing information LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="ac3e5e02fd89a357135adca6d28cd0e45a7e8da208ecaf142107587033e2d63ec1" name="ac3e5e02fd89a357135adca6d28cd0e45a7e8da208ecaf142107587033e2d63ec1"></a>SLINK_ROUTE_DST_MSB&#160;</td><td class="fielddoc"><p>SLINK routing register(3) (r/w): Destination routing information MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="ac3e5e02fd89a357135adca6d28cd0e45a69942c3a7b7b0550634f4016e639b0c2" name="ac3e5e02fd89a357135adca6d28cd0e45a69942c3a7b7b0550634f4016e639b0c2"></a>SLINK_ROUTE_SRC_LSB&#160;</td><td class="fielddoc"><p>SLINK routing register(4) (r/-): Source routing information LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="ac3e5e02fd89a357135adca6d28cd0e45a7b7b0b9bd4fe448cae97a3a21460f983" name="ac3e5e02fd89a357135adca6d28cd0e45a7b7b0b9bd4fe448cae97a3a21460f983"></a>SLINK_ROUTE_SRC_MSB&#160;</td><td class="fielddoc"><p>SLINK routing register(7) (r/-): Source routing information MSB </p> +</td></tr> +</table> + +</div> +</div> +<a id="a84f7fe82f188bd4e68f41549587822bf" name="a84f7fe82f188bd4e68f41549587822bf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a84f7fe82f188bd4e68f41549587822bf">&#9670;&#160;</a></span>NEORV32_SLINK_STATUS_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a84f7fe82f188bd4e68f41549587822bf">NEORV32_SLINK_STATUS_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SLINK module hardware access (<a class="el" href="structneorv32__slink__t.html">neorv32_slink_t</a>) </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a84f7fe82f188bd4e68f41549587822bfa9f24886f55b7f78ae8909ea8a573058c" name="a84f7fe82f188bd4e68f41549587822bfa9f24886f55b7f78ae8909ea8a573058c"></a>SLINK_FIFO_EMPTY&#160;</td><td class="fielddoc"><p>FIFO is empty </p> +</td></tr> +<tr><td class="fieldname"><a id="a84f7fe82f188bd4e68f41549587822bfadc37988b8aee38e85626064b2c3704f9" name="a84f7fe82f188bd4e68f41549587822bfadc37988b8aee38e85626064b2c3704f9"></a>SLINK_FIFO_HALF&#160;</td><td class="fielddoc"><p>FIFO is at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="a84f7fe82f188bd4e68f41549587822bfa2f96e61f0e07ef4ecd40f14e69b69211" name="a84f7fe82f188bd4e68f41549587822bfa2f96e61f0e07ef4ecd40f14e69b69211"></a>SLINK_FIFO_FULL&#160;</td><td class="fielddoc"><p>FIFO is full </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="aaf0f7bc96b797e819ccaae94292d9ddb" name="aaf0f7bc96b797e819ccaae94292d9ddb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaf0f7bc96b797e819ccaae94292d9ddb">&#9670;&#160;</a></span>neorv32_slink_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_slink_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if stream link interface was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if SLINK was not synthesized, 1 if SLINK is available. </dd></dl> + +</div> +</div> +<a id="a3e02c558548c1c6178c49adee9a007f7" name="a3e02c558548c1c6178c49adee9a007f7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3e02c558548c1c6178c49adee9a007f7">&#9670;&#160;</a></span>neorv32_slink_check_last()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_check_last </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Check if last RX word has "end-of-stream" delimiter.</p> +<dl class="section note"><dt>Note</dt><dd>This needs has to be called AFTER reading the actual data word using <a class="el" href="neorv32__slink_8c.html#ace319592c12dc6a0fe1b7dd66bdf9284">neorv32_slink_get(void)</a>.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if not end of stream, !=0 if end of stream. </dd></dl> + +</div> +</div> +<a id="ace319592c12dc6a0fe1b7dd66bdf9284" name="ace319592c12dc6a0fe1b7dd66bdf9284"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ace319592c12dc6a0fe1b7dd66bdf9284">&#9670;&#160;</a></span>neorv32_slink_get()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_get </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Read data from RX link (non-blocking)</p> +<dl class="section return"><dt>Returns</dt><dd>Data received from link. </dd></dl> + +</div> +</div> +<a id="a575c7663ca0bd07c95b1d45152a3ddf8" name="a575c7663ca0bd07c95b1d45152a3ddf8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a575c7663ca0bd07c95b1d45152a3ddf8">&#9670;&#160;</a></span>neorv32_slink_get_rx_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_slink_get_rx_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get FIFO depth of RX link.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth of RX link (1..32768). </dd></dl> + +</div> +</div> +<a id="a1a9269f42552a849450aecd99f7ec7a0" name="a1a9269f42552a849450aecd99f7ec7a0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1a9269f42552a849450aecd99f7ec7a0">&#9670;&#160;</a></span>neorv32_slink_get_src()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_get_src </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Get RX link routing source</p> +<dl class="section note"><dt>Note</dt><dd>This needs has to be called AFTER reading the actual data word using <a class="el" href="neorv32__slink_8c.html#ace319592c12dc6a0fe1b7dd66bdf9284">neorv32_slink_get(void)</a>.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>4-bit source routing ID. </dd></dl> + +</div> +</div> +<a id="aaf0d0d1b890353d4f3bf49450ec2fad2" name="aaf0d0d1b890353d4f3bf49450ec2fad2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaf0d0d1b890353d4f3bf49450ec2fad2">&#9670;&#160;</a></span>neorv32_slink_get_tx_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_slink_get_tx_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get FIFO depth of TX link.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth of TX link (1..32768). </dd></dl> + +</div> +</div> +<a id="aaa9fdb9cbfa7888e92790ab65431d21d" name="aaa9fdb9cbfa7888e92790ab65431d21d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaa9fdb9cbfa7888e92790ab65431d21d">&#9670;&#160;</a></span>neorv32_slink_put()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_put </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>tx_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Write data to TX link (non-blocking)</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">tx_data</td><td>Data to send to link. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a2136bc0b12ee2e6703e84a6417a1e8eb" name="a2136bc0b12ee2e6703e84a6417a1e8eb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2136bc0b12ee2e6703e84a6417a1e8eb">&#9670;&#160;</a></span>neorv32_slink_put_last()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_put_last </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>tx_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Write data to TX link (non-blocking) and set "last" (end-of-stream) delimiter.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">tx_data</td><td>Data to send to link. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ad149fea81e6d28f77450b8ba50cf706e" name="ad149fea81e6d28f77450b8ba50cf706e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad149fea81e6d28f77450b8ba50cf706e">&#9670;&#160;</a></span>neorv32_slink_rx_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_rx_clear </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear RX FIFO. </p> + +</div> +</div> +<a id="ad57fc0941fe32e8bf423ce3e57e2c10a" name="ad57fc0941fe32e8bf423ce3e57e2c10a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad57fc0941fe32e8bf423ce3e57e2c10a">&#9670;&#160;</a></span>neorv32_slink_rx_status()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_slink_rx_status </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get RX link FIFO status.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO status <a class="el" href="#a84f7fe82f188bd4e68f41549587822bf">NEORV32_SLINK_STATUS_enum</a>. </dd></dl> + +</div> +</div> +<a id="ad857d7e78ca2b5eb0d0a4f2c515fe7bc" name="ad857d7e78ca2b5eb0d0a4f2c515fe7bc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad857d7e78ca2b5eb0d0a4f2c515fe7bc">&#9670;&#160;</a></span>neorv32_slink_set_dst()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_set_dst </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>dst</em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">inline</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>Set TX link routing destination</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">dst</td><td>Routing destination ID (4-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a8f0b4a768f53a72a5c16034e160ce321" name="a8f0b4a768f53a72a5c16034e160ce321"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8f0b4a768f53a72a5c16034e160ce321">&#9670;&#160;</a></span>neorv32_slink_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>rx_irq</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>tx_irq</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, enable and configure SLINK.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">rx_irq</td><td>Configure RX interrupt conditions (<a class="el" href="#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a>). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">tx_irq</td><td>Configure TX interrupt conditions (<a class="el" href="#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a>). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac7484e9e3848f94efe016dd064f6a57f" name="ac7484e9e3848f94efe016dd064f6a57f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac7484e9e3848f94efe016dd064f6a57f">&#9670;&#160;</a></span>neorv32_slink_tx_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_slink_tx_clear </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear TX FIFO. </p> + +</div> +</div> +<a id="ad0252e7ae915e5840cd17e8c52e94a1c" name="ad0252e7ae915e5840cd17e8c52e94a1c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad0252e7ae915e5840cd17e8c52e94a1c">&#9670;&#160;</a></span>neorv32_slink_tx_status()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_slink_tx_status </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get TX link FIFO status.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO status <a class="el" href="#a84f7fe82f188bd4e68f41549587822bf">NEORV32_SLINK_STATUS_enum</a>. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__slink_8h_source.html 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+</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_slink.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__slink_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_slink_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_slink_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00027" data-start="{" data-end="};"> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"><a class="line" href="structneorv32__slink__t.html"> 27</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"><a class="line" href="structneorv32__slink__t.html#a39ece6aeeea6982002e164902a1e784f"> 28</a></span> uint32_t <a class="code hl_variable" href="structneorv32__slink__t.html#a39ece6aeeea6982002e164902a1e784f">CTRL</a>; </div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__slink__t.html#a0b2417a1a587da45909ce2a948f90e22"> 29</a></span> uint32_t <a class="code hl_variable" href="structneorv32__slink__t.html#a0b2417a1a587da45909ce2a948f90e22">ROUTE</a>; </div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__slink__t.html#a8af7d4ea9787cf94c599c82133c6aa74"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__slink__t.html#a8af7d4ea9787cf94c599c82133c6aa74">DATA</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__slink__t.html#ada8f10141d2161b83a5a367722ed6a77"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__slink__t.html#ada8f10141d2161b83a5a367722ed6a77">DATA_LAST</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__slink__t.html">neorv32_slink_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#a6380d894432de119a20993096db534df"> 35</a></span><span class="preprocessor">#define NEORV32_SLINK ((neorv32_slink_t*) (NEORV32_SLINK_BASE))</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="foldopen" id="foldopen00038" data-start="{" data-end="};"> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1"> 38</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a> {</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a739187f413b7436dc4037187e4a9e86a"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a739187f413b7436dc4037187e4a9e86a">SLINK_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a156fa3209b2652af6b58b0fdfc6cab1b"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a156fa3209b2652af6b58b0fdfc6cab1b">SLINK_CTRL_RX_CLR</a> = 1, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ad366597a44d3dff7dbab4cde72bed82f"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ad366597a44d3dff7dbab4cde72bed82f">SLINK_CTRL_TX_CLR</a> = 2, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a624723683d247668ef44137393e576aa"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a624723683d247668ef44137393e576aa">SLINK_CTRL_RX_LAST</a> = 4, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ae78f82e54bd9d737bbcbc5c7af0e9d4b"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ae78f82e54bd9d737bbcbc5c7af0e9d4b">SLINK_CTRL_RX_EMPTY</a> = 8, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af695158b9cf5466d87c207f9bd0a688e"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af695158b9cf5466d87c207f9bd0a688e">SLINK_CTRL_RX_HALF</a> = 9, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1aa7521fbe691fef233c0dff4053e4493e"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1aa7521fbe691fef233c0dff4053e4493e">SLINK_CTRL_RX_FULL</a> = 10, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a308cf7829ecca32f7a3da1bd74339854"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a308cf7829ecca32f7a3da1bd74339854">SLINK_CTRL_TX_EMPTY</a> = 11, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a530b8b76301f36fbda134b330447de78"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a530b8b76301f36fbda134b330447de78">SLINK_CTRL_TX_HALF</a> = 12, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af94314ed65c6a8d9c364d99d7ae960ee"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af94314ed65c6a8d9c364d99d7ae960ee">SLINK_CTRL_TX_FULL</a> = 13, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a5452eab0fe12d174ec804c4c72060854"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a5452eab0fe12d174ec804c4c72060854">SLINK_CTRL_IRQ_RX_NEMPTY</a> = 16, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1afa9353cd824d1b2833930ce9e922e392"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1afa9353cd824d1b2833930ce9e922e392">SLINK_CTRL_IRQ_RX_HALF</a> = 17, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ac8a688706aee72d2027e022b64664309"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ac8a688706aee72d2027e022b64664309">SLINK_CTRL_IRQ_RX_FULL</a> = 18, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ae06ad5f627f8902e2368e0daff6cfa88"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ae06ad5f627f8902e2368e0daff6cfa88">SLINK_CTRL_IRQ_TX_EMPTY</a> = 19, </div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a7bf757dbfb1fdaddceaed3a3887003cf"> 56</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a7bf757dbfb1fdaddceaed3a3887003cf">SLINK_CTRL_IRQ_TX_NHALF</a> = 20, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a8f994f256f57c006c88b9e38df3f54fa"> 57</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a8f994f256f57c006c88b9e38df3f54fa">SLINK_CTRL_IRQ_TX_NFULL</a> = 21, </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a9c68af961c1147846929ca55e9e4e88c"> 59</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a9c68af961c1147846929ca55e9e4e88c">SLINK_CTRL_RX_FIFO_LSB</a> = 24, </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a945e2b7eda65dc13ca38eb21c9c4f657"> 60</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a945e2b7eda65dc13ca38eb21c9c4f657">SLINK_CTRL_RX_FIFO_MSB</a> = 27, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1aba613343fc17715fc1bb07729588a12d"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1aba613343fc17715fc1bb07729588a12d">SLINK_CTRL_TX_FIFO_LSB</a> = 28, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af27a9e6e50b169d3f5efd0a08ba4a943">SLINK_CTRL_TX_FIFO_MSB</a> = 31 </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af27a9e6e50b169d3f5efd0a08ba4a943"> 63</a></span>};</div> +</div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span> </div> +<div class="foldopen" id="foldopen00066" data-start="{" data-end="};"> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45"> 66</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45">NEORV32_SLINK_ROUTE_enum</a> {</div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a9a2311357bd87c85a5cc45f08b0d8f80"> 67</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a9a2311357bd87c85a5cc45f08b0d8f80">SLINK_ROUTE_DST_LSB</a> = 0, </div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a7e8da208ecaf142107587033e2d63ec1"> 68</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a7e8da208ecaf142107587033e2d63ec1">SLINK_ROUTE_DST_MSB</a> = 3, </div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a69942c3a7b7b0550634f4016e639b0c2"> 69</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a69942c3a7b7b0550634f4016e639b0c2">SLINK_ROUTE_SRC_LSB</a> = 4, </div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a7b7b0b9bd4fe448cae97a3a21460f983">SLINK_ROUTE_SRC_MSB</a> = 7 </div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a7b7b0b9bd4fe448cae97a3a21460f983"> 71</a></span>};</div> +</div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span> </div> +<div class="foldopen" id="foldopen00073" data-start="{" data-end="};"> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bf"> 73</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bf">NEORV32_SLINK_STATUS_enum</a> {</div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfa9f24886f55b7f78ae8909ea8a573058c"> 74</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfa9f24886f55b7f78ae8909ea8a573058c">SLINK_FIFO_EMPTY</a> = 0, </div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfadc37988b8aee38e85626064b2c3704f9"> 75</a></span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfadc37988b8aee38e85626064b2c3704f9">SLINK_FIFO_HALF</a> = 1, </div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span> <a class="code hl_enumvalue" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfa2f96e61f0e07ef4ecd40f14e69b69211">SLINK_FIFO_FULL</a> = 2 </div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"><a class="line" href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfa2f96e61f0e07ef4ecd40f14e69b69211"> 77</a></span>};</div> +</div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__slink_8h.html#aaf0f7bc96b797e819ccaae94292d9ddb">neorv32_slink_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__slink_8h.html#a8f0b4a768f53a72a5c16034e160ce321">neorv32_slink_setup</a>(uint32_t rx_irq, uint32_t tx_irq);</div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__slink_8h.html#ad149fea81e6d28f77450b8ba50cf706e">neorv32_slink_rx_clear</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__slink_8h.html#ac7484e9e3848f94efe016dd064f6a57f">neorv32_slink_tx_clear</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__slink_8h.html#a575c7663ca0bd07c95b1d45152a3ddf8">neorv32_slink_get_rx_fifo_depth</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__slink_8h.html#aaf0d0d1b890353d4f3bf49450ec2fad2">neorv32_slink_get_tx_fifo_depth</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span>uint32_t <a class="code hl_function" href="neorv32__slink_8h.html#ace319592c12dc6a0fe1b7dd66bdf9284">neorv32_slink_get</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span>uint32_t <a class="code hl_function" href="neorv32__slink_8h.html#a3e02c558548c1c6178c49adee9a007f7">neorv32_slink_check_last</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__slink_8h.html#ad857d7e78ca2b5eb0d0a4f2c515fe7bc">neorv32_slink_set_dst</a>(uint32_t dst);</div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span>uint32_t <a class="code hl_function" href="neorv32__slink_8h.html#a1a9269f42552a849450aecd99f7ec7a0">neorv32_slink_get_src</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__slink_8h.html#aaa9fdb9cbfa7888e92790ab65431d21d">neorv32_slink_put</a>(uint32_t tx_data);</div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__slink_8h.html#a2136bc0b12ee2e6703e84a6417a1e8eb">neorv32_slink_put_last</a>(uint32_t tx_data);</div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__slink_8h.html#ad57fc0941fe32e8bf423ce3e57e2c10a">neorv32_slink_rx_status</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__slink_8h.html#ad0252e7ae915e5840cd17e8c52e94a1c">neorv32_slink_tx_status</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_slink_h</span></div> +<div class="ttc" id="aneorv32__slink_8h_html_a1a9269f42552a849450aecd99f7ec7a0"><div class="ttname"><a href="neorv32__slink_8h.html#a1a9269f42552a849450aecd99f7ec7a0">neorv32_slink_get_src</a></div><div class="ttdeci">uint32_t neorv32_slink_get_src(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:148</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_a2136bc0b12ee2e6703e84a6417a1e8eb"><div class="ttname"><a href="neorv32__slink_8h.html#a2136bc0b12ee2e6703e84a6417a1e8eb">neorv32_slink_put_last</a></div><div class="ttdeci">void neorv32_slink_put_last(uint32_t tx_data)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:171</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_a3e02c558548c1c6178c49adee9a007f7"><div class="ttname"><a href="neorv32__slink_8h.html#a3e02c558548c1c6178c49adee9a007f7">neorv32_slink_check_last</a></div><div class="ttdeci">uint32_t neorv32_slink_check_last(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:123</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_a575c7663ca0bd07c95b1d45152a3ddf8"><div class="ttname"><a href="neorv32__slink_8h.html#a575c7663ca0bd07c95b1d45152a3ddf8">neorv32_slink_get_rx_fifo_depth</a></div><div class="ttdeci">int neorv32_slink_get_rx_fifo_depth(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:85</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_a84f7fe82f188bd4e68f41549587822bf"><div class="ttname"><a href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bf">NEORV32_SLINK_STATUS_enum</a></div><div class="ttdeci">NEORV32_SLINK_STATUS_enum</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:73</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_a84f7fe82f188bd4e68f41549587822bfa2f96e61f0e07ef4ecd40f14e69b69211"><div class="ttname"><a href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfa2f96e61f0e07ef4ecd40f14e69b69211">SLINK_FIFO_FULL</a></div><div class="ttdeci">@ SLINK_FIFO_FULL</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:76</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_a84f7fe82f188bd4e68f41549587822bfa9f24886f55b7f78ae8909ea8a573058c"><div class="ttname"><a href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfa9f24886f55b7f78ae8909ea8a573058c">SLINK_FIFO_EMPTY</a></div><div class="ttdeci">@ SLINK_FIFO_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:74</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_a84f7fe82f188bd4e68f41549587822bfadc37988b8aee38e85626064b2c3704f9"><div class="ttname"><a href="neorv32__slink_8h.html#a84f7fe82f188bd4e68f41549587822bfadc37988b8aee38e85626064b2c3704f9">SLINK_FIFO_HALF</a></div><div class="ttdeci">@ SLINK_FIFO_HALF</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:75</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_a8f0b4a768f53a72a5c16034e160ce321"><div class="ttname"><a href="neorv32__slink_8h.html#a8f0b4a768f53a72a5c16034e160ce321">neorv32_slink_setup</a></div><div class="ttdeci">void neorv32_slink_setup(uint32_t rx_irq, uint32_t tx_irq)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:43</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_aaa9fdb9cbfa7888e92790ab65431d21d"><div class="ttname"><a href="neorv32__slink_8h.html#aaa9fdb9cbfa7888e92790ab65431d21d">neorv32_slink_put</a></div><div class="ttdeci">void neorv32_slink_put(uint32_t tx_data)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:159</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_aaf0d0d1b890353d4f3bf49450ec2fad2"><div class="ttname"><a href="neorv32__slink_8h.html#aaf0d0d1b890353d4f3bf49450ec2fad2">neorv32_slink_get_tx_fifo_depth</a></div><div class="ttdeci">int neorv32_slink_get_tx_fifo_depth(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:97</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_aaf0f7bc96b797e819ccaae94292d9ddb"><div class="ttname"><a href="neorv32__slink_8h.html#aaf0f7bc96b797e819ccaae94292d9ddb">neorv32_slink_available</a></div><div class="ttdeci">int neorv32_slink_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:26</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a></div><div class="ttdeci">NEORV32_SLINK_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:38</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a156fa3209b2652af6b58b0fdfc6cab1b"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a156fa3209b2652af6b58b0fdfc6cab1b">SLINK_CTRL_RX_CLR</a></div><div class="ttdeci">@ SLINK_CTRL_RX_CLR</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:40</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a308cf7829ecca32f7a3da1bd74339854"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a308cf7829ecca32f7a3da1bd74339854">SLINK_CTRL_TX_EMPTY</a></div><div class="ttdeci">@ SLINK_CTRL_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:48</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a530b8b76301f36fbda134b330447de78"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a530b8b76301f36fbda134b330447de78">SLINK_CTRL_TX_HALF</a></div><div class="ttdeci">@ SLINK_CTRL_TX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:49</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a5452eab0fe12d174ec804c4c72060854"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a5452eab0fe12d174ec804c4c72060854">SLINK_CTRL_IRQ_RX_NEMPTY</a></div><div class="ttdeci">@ SLINK_CTRL_IRQ_RX_NEMPTY</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:52</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a624723683d247668ef44137393e576aa"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a624723683d247668ef44137393e576aa">SLINK_CTRL_RX_LAST</a></div><div class="ttdeci">@ SLINK_CTRL_RX_LAST</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:43</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a739187f413b7436dc4037187e4a9e86a"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a739187f413b7436dc4037187e4a9e86a">SLINK_CTRL_EN</a></div><div class="ttdeci">@ SLINK_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:39</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a7bf757dbfb1fdaddceaed3a3887003cf"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a7bf757dbfb1fdaddceaed3a3887003cf">SLINK_CTRL_IRQ_TX_NHALF</a></div><div class="ttdeci">@ SLINK_CTRL_IRQ_TX_NHALF</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:56</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a8f994f256f57c006c88b9e38df3f54fa"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a8f994f256f57c006c88b9e38df3f54fa">SLINK_CTRL_IRQ_TX_NFULL</a></div><div class="ttdeci">@ SLINK_CTRL_IRQ_TX_NFULL</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:57</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a945e2b7eda65dc13ca38eb21c9c4f657"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a945e2b7eda65dc13ca38eb21c9c4f657">SLINK_CTRL_RX_FIFO_MSB</a></div><div class="ttdeci">@ SLINK_CTRL_RX_FIFO_MSB</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:60</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1a9c68af961c1147846929ca55e9e4e88c"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1a9c68af961c1147846929ca55e9e4e88c">SLINK_CTRL_RX_FIFO_LSB</a></div><div class="ttdeci">@ SLINK_CTRL_RX_FIFO_LSB</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:59</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1aa7521fbe691fef233c0dff4053e4493e"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1aa7521fbe691fef233c0dff4053e4493e">SLINK_CTRL_RX_FULL</a></div><div class="ttdeci">@ SLINK_CTRL_RX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:47</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1aba613343fc17715fc1bb07729588a12d"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1aba613343fc17715fc1bb07729588a12d">SLINK_CTRL_TX_FIFO_LSB</a></div><div class="ttdeci">@ SLINK_CTRL_TX_FIFO_LSB</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:61</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1ac8a688706aee72d2027e022b64664309"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ac8a688706aee72d2027e022b64664309">SLINK_CTRL_IRQ_RX_FULL</a></div><div class="ttdeci">@ SLINK_CTRL_IRQ_RX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:54</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1ad366597a44d3dff7dbab4cde72bed82f"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ad366597a44d3dff7dbab4cde72bed82f">SLINK_CTRL_TX_CLR</a></div><div class="ttdeci">@ SLINK_CTRL_TX_CLR</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:41</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1ae06ad5f627f8902e2368e0daff6cfa88"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ae06ad5f627f8902e2368e0daff6cfa88">SLINK_CTRL_IRQ_TX_EMPTY</a></div><div class="ttdeci">@ SLINK_CTRL_IRQ_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:55</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1ae78f82e54bd9d737bbcbc5c7af0e9d4b"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1ae78f82e54bd9d737bbcbc5c7af0e9d4b">SLINK_CTRL_RX_EMPTY</a></div><div class="ttdeci">@ SLINK_CTRL_RX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:45</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1af27a9e6e50b169d3f5efd0a08ba4a943"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af27a9e6e50b169d3f5efd0a08ba4a943">SLINK_CTRL_TX_FIFO_MSB</a></div><div class="ttdeci">@ SLINK_CTRL_TX_FIFO_MSB</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:62</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1af695158b9cf5466d87c207f9bd0a688e"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af695158b9cf5466d87c207f9bd0a688e">SLINK_CTRL_RX_HALF</a></div><div class="ttdeci">@ SLINK_CTRL_RX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:46</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1af94314ed65c6a8d9c364d99d7ae960ee"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1af94314ed65c6a8d9c364d99d7ae960ee">SLINK_CTRL_TX_FULL</a></div><div class="ttdeci">@ SLINK_CTRL_TX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:50</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac0385a56c38315d492b3414d98235ef1afa9353cd824d1b2833930ce9e922e392"><div class="ttname"><a href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1afa9353cd824d1b2833930ce9e922e392">SLINK_CTRL_IRQ_RX_HALF</a></div><div class="ttdeci">@ SLINK_CTRL_IRQ_RX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:53</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac3e5e02fd89a357135adca6d28cd0e45"><div class="ttname"><a href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45">NEORV32_SLINK_ROUTE_enum</a></div><div class="ttdeci">NEORV32_SLINK_ROUTE_enum</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:66</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac3e5e02fd89a357135adca6d28cd0e45a69942c3a7b7b0550634f4016e639b0c2"><div class="ttname"><a href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a69942c3a7b7b0550634f4016e639b0c2">SLINK_ROUTE_SRC_LSB</a></div><div class="ttdeci">@ SLINK_ROUTE_SRC_LSB</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:69</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac3e5e02fd89a357135adca6d28cd0e45a7b7b0b9bd4fe448cae97a3a21460f983"><div class="ttname"><a href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a7b7b0b9bd4fe448cae97a3a21460f983">SLINK_ROUTE_SRC_MSB</a></div><div class="ttdeci">@ SLINK_ROUTE_SRC_MSB</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:70</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac3e5e02fd89a357135adca6d28cd0e45a7e8da208ecaf142107587033e2d63ec1"><div class="ttname"><a href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a7e8da208ecaf142107587033e2d63ec1">SLINK_ROUTE_DST_MSB</a></div><div class="ttdeci">@ SLINK_ROUTE_DST_MSB</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:68</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac3e5e02fd89a357135adca6d28cd0e45a9a2311357bd87c85a5cc45f08b0d8f80"><div class="ttname"><a href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45a9a2311357bd87c85a5cc45f08b0d8f80">SLINK_ROUTE_DST_LSB</a></div><div class="ttdeci">@ SLINK_ROUTE_DST_LSB</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:67</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ac7484e9e3848f94efe016dd064f6a57f"><div class="ttname"><a href="neorv32__slink_8h.html#ac7484e9e3848f94efe016dd064f6a57f">neorv32_slink_tx_clear</a></div><div class="ttdeci">void neorv32_slink_tx_clear(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:74</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ace319592c12dc6a0fe1b7dd66bdf9284"><div class="ttname"><a href="neorv32__slink_8h.html#ace319592c12dc6a0fe1b7dd66bdf9284">neorv32_slink_get</a></div><div class="ttdeci">uint32_t neorv32_slink_get(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:109</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ad0252e7ae915e5840cd17e8c52e94a1c"><div class="ttname"><a href="neorv32__slink_8h.html#ad0252e7ae915e5840cd17e8c52e94a1c">neorv32_slink_tx_status</a></div><div class="ttdeci">int neorv32_slink_tx_status(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:206</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ad149fea81e6d28f77450b8ba50cf706e"><div class="ttname"><a href="neorv32__slink_8h.html#ad149fea81e6d28f77450b8ba50cf706e">neorv32_slink_rx_clear</a></div><div class="ttdeci">void neorv32_slink_rx_clear(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:65</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ad57fc0941fe32e8bf423ce3e57e2c10a"><div class="ttname"><a href="neorv32__slink_8h.html#ad57fc0941fe32e8bf423ce3e57e2c10a">neorv32_slink_rx_status</a></div><div class="ttdeci">int neorv32_slink_rx_status(void)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:182</div></div> +<div class="ttc" id="aneorv32__slink_8h_html_ad857d7e78ca2b5eb0d0a4f2c515fe7bc"><div class="ttname"><a href="neorv32__slink_8h.html#ad857d7e78ca2b5eb0d0a4f2c515fe7bc">neorv32_slink_set_dst</a></div><div class="ttdeci">void neorv32_slink_set_dst(uint32_t dst)</div><div class="ttdef"><b>Definition</b> neorv32_slink.c:134</div></div> +<div class="ttc" id="astructneorv32__slink__t_html"><div class="ttname"><a href="structneorv32__slink__t.html">neorv32_slink_t</a></div><div class="ttdef"><b>Definition</b> neorv32_slink.h:27</div></div> +<div class="ttc" id="astructneorv32__slink__t_html_a0b2417a1a587da45909ce2a948f90e22"><div class="ttname"><a href="structneorv32__slink__t.html#a0b2417a1a587da45909ce2a948f90e22">neorv32_slink_t::ROUTE</a></div><div class="ttdeci">uint32_t ROUTE</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:29</div></div> +<div class="ttc" id="astructneorv32__slink__t_html_a39ece6aeeea6982002e164902a1e784f"><div class="ttname"><a href="structneorv32__slink__t.html#a39ece6aeeea6982002e164902a1e784f">neorv32_slink_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:28</div></div> +<div class="ttc" id="astructneorv32__slink__t_html_a8af7d4ea9787cf94c599c82133c6aa74"><div class="ttname"><a href="structneorv32__slink__t.html#a8af7d4ea9787cf94c599c82133c6aa74">neorv32_slink_t::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition</b> neorv32_slink.h:30</div></div> +<div class="ttc" id="astructneorv32__slink__t_html_ada8f10141d2161b83a5a367722ed6a77"><div class="ttname"><a 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href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a7266ee439d0ec11c5cedd4bf1a258272" id="r_a7266ee439d0ec11c5cedd4bf1a258272"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7266ee439d0ec11c5cedd4bf1a258272">neorv32_spi_available</a> (void)</td></tr> +<tr class="separator:a7266ee439d0ec11c5cedd4bf1a258272"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7d8124d986b69210081df6f1aa653552" id="r_a7d8124d986b69210081df6f1aa653552"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7d8124d986b69210081df6f1aa653552">neorv32_spi_setup</a> (int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t 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class="memitem:a01c6b63d7349447e2277f2649c3c89f2" id="r_a01c6b63d7349447e2277f2649c3c89f2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a01c6b63d7349447e2277f2649c3c89f2">neorv32_spi_get_clock_speed</a> (void)</td></tr> +<tr class="separator:a01c6b63d7349447e2277f2649c3c89f2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a817dd9a38bfceb2048e40874a83ba169" id="r_a817dd9a38bfceb2048e40874a83ba169"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a817dd9a38bfceb2048e40874a83ba169">neorv32_spi_disable</a> (void)</td></tr> +<tr class="separator:a817dd9a38bfceb2048e40874a83ba169"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8fa25d144ccb20a2faf0450c8dddd16e" id="r_a8fa25d144ccb20a2faf0450c8dddd16e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8fa25d144ccb20a2faf0450c8dddd16e">neorv32_spi_enable</a> (void)</td></tr> +<tr class="separator:a8fa25d144ccb20a2faf0450c8dddd16e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae1c4da7e4dc2e42b04d7187f684f142c" id="r_ae1c4da7e4dc2e42b04d7187f684f142c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae1c4da7e4dc2e42b04d7187f684f142c">neorv32_spi_get_fifo_depth</a> (void)</td></tr> +<tr class="separator:ae1c4da7e4dc2e42b04d7187f684f142c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a737961d040ac09567350f89034f9e122" id="r_a737961d040ac09567350f89034f9e122"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a737961d040ac09567350f89034f9e122">neorv32_spi_cs_en</a> (int cs)</td></tr> +<tr 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id="r_aec8583e988789e846d21c2a35e6b06e7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aec8583e988789e846d21c2a35e6b06e7">neorv32_spi_put_nonblocking</a> (uint8_t tx_data)</td></tr> +<tr class="separator:aec8583e988789e846d21c2a35e6b06e7"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aad66fa8f8d1a92d4f355de7579bfbfd2" id="r_aad66fa8f8d1a92d4f355de7579bfbfd2"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aad66fa8f8d1a92d4f355de7579bfbfd2">neorv32_spi_get_nonblocking</a> (void)</td></tr> +<tr class="separator:aad66fa8f8d1a92d4f355de7579bfbfd2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a97b5536347a27b053f071ba49071ba6f" id="r_a97b5536347a27b053f071ba49071ba6f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" 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class="separator:a82bb4d4c222b2bdc57e917c348481501"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a332c7a1be511812ac0a2b102c165398a" id="r_a332c7a1be511812ac0a2b102c165398a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a332c7a1be511812ac0a2b102c165398a">neorv32_spi_busy</a> (void)</td></tr> +<tr class="separator:a332c7a1be511812ac0a2b102c165398a"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Serial peripheral interface controller (SPI) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a7266ee439d0ec11c5cedd4bf1a258272" name="a7266ee439d0ec11c5cedd4bf1a258272"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7266ee439d0ec11c5cedd4bf1a258272">&#9670;&#160;</a></span>neorv32_spi_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if SPI unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if SPI was not synthesized, 1 if SPI is available. </dd></dl> + +</div> +</div> +<a id="a332c7a1be511812ac0a2b102c165398a" name="a332c7a1be511812ac0a2b102c165398a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a332c7a1be511812ac0a2b102c165398a">&#9670;&#160;</a></span>neorv32_spi_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_busy </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if SPI transceiver is busy or TX FIFO not empty.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if idle, 1 if busy </dd></dl> + +</div> +</div> +<a id="a82bb4d4c222b2bdc57e917c348481501" name="a82bb4d4c222b2bdc57e917c348481501"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a82bb4d4c222b2bdc57e917c348481501">&#9670;&#160;</a></span>neorv32_spi_check_cs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_check_cs </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if any chip-select line is active.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if no CS lines are active, 1 if at least one CS line is active. </dd></dl> + +</div> +</div> +<a id="aa10ec90ccba6325eeeebb8f6f298d30c" name="aa10ec90ccba6325eeeebb8f6f298d30c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa10ec90ccba6325eeeebb8f6f298d30c">&#9670;&#160;</a></span>neorv32_spi_cs_dis()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_cs_dis </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Deactivate currently active SPI chip select signal.</p> +<dl class="section note"><dt>Note</dt><dd>The SPI chip select output lines are HIGH when deactivated. </dd> +<dd> +This function is blocking. </dd></dl> + +</div> +</div> +<a id="ad8dd1b5a85a9daef4c8c21c9990884c1" name="ad8dd1b5a85a9daef4c8c21c9990884c1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad8dd1b5a85a9daef4c8c21c9990884c1">&#9670;&#160;</a></span>neorv32_spi_cs_dis_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_cs_dis_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Deactivate currently active SPI chip select signal (non-blocking).</p> +<dl class="section note"><dt>Note</dt><dd>The SPI chip select output lines are HIGH when deactivated. </dd></dl> + +</div> +</div> +<a id="a737961d040ac09567350f89034f9e122" name="a737961d040ac09567350f89034f9e122"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a737961d040ac09567350f89034f9e122">&#9670;&#160;</a></span>neorv32_spi_cs_en()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_cs_en </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cs</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Activate single SPI chip select signal.</p> +<dl class="section note"><dt>Note</dt><dd>The SPI chip select output lines are LOW when activated. </dd> +<dd> +This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">cs</td><td>Chip select line to activate (0..7). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a97b5536347a27b053f071ba49071ba6f" name="a97b5536347a27b053f071ba49071ba6f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a97b5536347a27b053f071ba49071ba6f">&#9670;&#160;</a></span>neorv32_spi_cs_en_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_cs_en_nonblocking </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cs</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Activate single SPI chip select signal (non-blocking).</p> +<dl class="section note"><dt>Note</dt><dd>The SPI chip select output lines are LOW when activated.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">cs</td><td>Chip select line to activate (0..7). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a817dd9a38bfceb2048e40874a83ba169" name="a817dd9a38bfceb2048e40874a83ba169"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a817dd9a38bfceb2048e40874a83ba169">&#9670;&#160;</a></span>neorv32_spi_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable SPI controller. </p> + +</div> +</div> +<a id="a8fa25d144ccb20a2faf0450c8dddd16e" name="a8fa25d144ccb20a2faf0450c8dddd16e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8fa25d144ccb20a2faf0450c8dddd16e">&#9670;&#160;</a></span>neorv32_spi_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable SPI controller. </p> + +</div> +</div> +<a id="a01c6b63d7349447e2277f2649c3c89f2" name="a01c6b63d7349447e2277f2649c3c89f2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a01c6b63d7349447e2277f2649c3c89f2">&#9670;&#160;</a></span>neorv32_spi_get_clock_speed()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_spi_get_clock_speed </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get configured clock speed in Hz.</p> +<dl class="section return"><dt>Returns</dt><dd>Actual configured SPI clock speed in Hz. </dd></dl> + +</div> +</div> +<a id="ae1c4da7e4dc2e42b04d7187f684f142c" name="ae1c4da7e4dc2e42b04d7187f684f142c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae1c4da7e4dc2e42b04d7187f684f142c">&#9670;&#160;</a></span>neorv32_spi_get_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_get_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get SPI FIFO depth.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries), zero if no FIFO implemented </dd></dl> + +</div> +</div> +<a id="aad66fa8f8d1a92d4f355de7579bfbfd2" name="aad66fa8f8d1a92d4f355de7579bfbfd2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aad66fa8f8d1a92d4f355de7579bfbfd2">&#9670;&#160;</a></span>neorv32_spi_get_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_spi_get_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get SPI RX data (non-blocking).</p> +<dl class="section return"><dt>Returns</dt><dd>Receive data (8-bit, LSB-aligned). </dd></dl> + +</div> +</div> +<a id="a67e9717635e272bc0e04408135a2f04d" name="a67e9717635e272bc0e04408135a2f04d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a67e9717635e272bc0e04408135a2f04d">&#9670;&#160;</a></span>neorv32_spi_highspeed_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_highspeed_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable high-speed mode. </p> + +</div> +</div> +<a id="acf131faa3ad970c19a3cd8a47cb54f65" name="acf131faa3ad970c19a3cd8a47cb54f65"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acf131faa3ad970c19a3cd8a47cb54f65">&#9670;&#160;</a></span>neorv32_spi_highspeed_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_highspeed_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable high-speed mode. </p> + +</div> +</div> +<a id="aec8583e988789e846d21c2a35e6b06e7" name="aec8583e988789e846d21c2a35e6b06e7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aec8583e988789e846d21c2a35e6b06e7">&#9670;&#160;</a></span>neorv32_spi_put_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_put_nonblocking </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>tx_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Put SPI TX data (non-blocking).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">tx_data</td><td>Transmit data (8-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a7d8124d986b69210081df6f1aa653552" name="a7d8124d986b69210081df6f1aa653552"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7d8124d986b69210081df6f1aa653552">&#9670;&#160;</a></span>neorv32_spi_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_setup </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cdiv</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>clk_phase</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>clk_polarity</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>irq_mask</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable and configure SPI controller. The SPI control register bits are listed in <a class="el" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3b">NEORV32_SPI_CTRL_enum</a>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Clock prescaler select (0..7). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. @prama[in] cdiv Clock divider (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">clk_phase</td><td>Clock phase (0=sample on rising edge, 1=sample on falling edge). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">clk_polarity</td><td>Clock polarity (when idle). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mask</td><td>Interrupt configuration mask (CTRL's irq_* bits). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a7af79950eefc26e67a89bde02f255532" name="a7af79950eefc26e67a89bde02f255532"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7af79950eefc26e67a89bde02f255532">&#9670;&#160;</a></span>neorv32_spi_trans()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_spi_trans </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>tx_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Perform a single SPI data transfer.</p> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">tx_data</td><td>Transmit data (8-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Receive data (8-bit, LSB-aligned). </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__spi_8h.html b/sw/neorv32__spi_8h.html new file mode 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href="#nested-classes">Data Structures</a> </div> + <div class="headertitle"><div class="title">neorv32_spi.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Serial peripheral interface controller (SPI) HW driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__spi_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__spi__t.html">neorv32_spi_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:a7266ee439d0ec11c5cedd4bf1a258272" id="r_a7266ee439d0ec11c5cedd4bf1a258272"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7266ee439d0ec11c5cedd4bf1a258272">neorv32_spi_available</a> (void)</td></tr> +<tr class="separator:a7266ee439d0ec11c5cedd4bf1a258272"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7d8124d986b69210081df6f1aa653552" id="r_a7d8124d986b69210081df6f1aa653552"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7d8124d986b69210081df6f1aa653552">neorv32_spi_setup</a> (int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t irq_mask)</td></tr> +<tr class="separator:a7d8124d986b69210081df6f1aa653552"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acf131faa3ad970c19a3cd8a47cb54f65" id="r_acf131faa3ad970c19a3cd8a47cb54f65"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acf131faa3ad970c19a3cd8a47cb54f65">neorv32_spi_highspeed_enable</a> (void)</td></tr> +<tr class="separator:acf131faa3ad970c19a3cd8a47cb54f65"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a67e9717635e272bc0e04408135a2f04d" id="r_a67e9717635e272bc0e04408135a2f04d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a67e9717635e272bc0e04408135a2f04d">neorv32_spi_highspeed_disable</a> (void)</td></tr> +<tr class="separator:a67e9717635e272bc0e04408135a2f04d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a01c6b63d7349447e2277f2649c3c89f2" id="r_a01c6b63d7349447e2277f2649c3c89f2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a01c6b63d7349447e2277f2649c3c89f2">neorv32_spi_get_clock_speed</a> (void)</td></tr> +<tr class="separator:a01c6b63d7349447e2277f2649c3c89f2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a817dd9a38bfceb2048e40874a83ba169" id="r_a817dd9a38bfceb2048e40874a83ba169"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a817dd9a38bfceb2048e40874a83ba169">neorv32_spi_disable</a> (void)</td></tr> +<tr class="separator:a817dd9a38bfceb2048e40874a83ba169"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8fa25d144ccb20a2faf0450c8dddd16e" id="r_a8fa25d144ccb20a2faf0450c8dddd16e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8fa25d144ccb20a2faf0450c8dddd16e">neorv32_spi_enable</a> (void)</td></tr> +<tr class="separator:a8fa25d144ccb20a2faf0450c8dddd16e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae1c4da7e4dc2e42b04d7187f684f142c" id="r_ae1c4da7e4dc2e42b04d7187f684f142c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae1c4da7e4dc2e42b04d7187f684f142c">neorv32_spi_get_fifo_depth</a> (void)</td></tr> +<tr class="separator:ae1c4da7e4dc2e42b04d7187f684f142c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a737961d040ac09567350f89034f9e122" id="r_a737961d040ac09567350f89034f9e122"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a737961d040ac09567350f89034f9e122">neorv32_spi_cs_en</a> (int cs)</td></tr> +<tr class="separator:a737961d040ac09567350f89034f9e122"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa10ec90ccba6325eeeebb8f6f298d30c" id="r_aa10ec90ccba6325eeeebb8f6f298d30c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa10ec90ccba6325eeeebb8f6f298d30c">neorv32_spi_cs_dis</a> (void)</td></tr> +<tr class="separator:aa10ec90ccba6325eeeebb8f6f298d30c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7af79950eefc26e67a89bde02f255532" id="r_a7af79950eefc26e67a89bde02f255532"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7af79950eefc26e67a89bde02f255532">neorv32_spi_trans</a> (uint8_t tx_data)</td></tr> +<tr class="separator:a7af79950eefc26e67a89bde02f255532"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aec8583e988789e846d21c2a35e6b06e7" id="r_aec8583e988789e846d21c2a35e6b06e7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aec8583e988789e846d21c2a35e6b06e7">neorv32_spi_put_nonblocking</a> (uint8_t tx_data)</td></tr> +<tr class="separator:aec8583e988789e846d21c2a35e6b06e7"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aad66fa8f8d1a92d4f355de7579bfbfd2" id="r_aad66fa8f8d1a92d4f355de7579bfbfd2"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aad66fa8f8d1a92d4f355de7579bfbfd2">neorv32_spi_get_nonblocking</a> (void)</td></tr> +<tr class="separator:aad66fa8f8d1a92d4f355de7579bfbfd2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a97b5536347a27b053f071ba49071ba6f" id="r_a97b5536347a27b053f071ba49071ba6f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a97b5536347a27b053f071ba49071ba6f">neorv32_spi_cs_en_nonblocking</a> (int cs)</td></tr> +<tr class="separator:a97b5536347a27b053f071ba49071ba6f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad8dd1b5a85a9daef4c8c21c9990884c1" id="r_ad8dd1b5a85a9daef4c8c21c9990884c1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad8dd1b5a85a9daef4c8c21c9990884c1">neorv32_spi_cs_dis_nonblocking</a> (void)</td></tr> +<tr class="separator:ad8dd1b5a85a9daef4c8c21c9990884c1"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a82bb4d4c222b2bdc57e917c348481501" id="r_a82bb4d4c222b2bdc57e917c348481501"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a82bb4d4c222b2bdc57e917c348481501">neorv32_spi_check_cs</a> (void)</td></tr> +<tr class="separator:a82bb4d4c222b2bdc57e917c348481501"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a332c7a1be511812ac0a2b102c165398a" id="r_a332c7a1be511812ac0a2b102c165398a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a332c7a1be511812ac0a2b102c165398a">neorv32_spi_busy</a> (void)</td></tr> +<tr class="separator:a332c7a1be511812ac0a2b102c165398a"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Serial Peripheral Interface Controller (SPI)</h2></td></tr> +<tr class="memitem:a5f3afc4e268670c54d90df67fa38ca22" id="r_a5f3afc4e268670c54d90df67fa38ca22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5f3afc4e268670c54d90df67fa38ca22">NEORV32_SPI</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__spi__t.html">neorv32_spi_t</a>*) (<a class="el" href="neorv32_8h.html#aa466dc5eace7351bd438606f0f7475a7">NEORV32_SPI_BASE</a>))</td></tr> +<tr class="separator:a5f3afc4e268670c54d90df67fa38ca22"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae269b2f5b2afd46ae16801762ade2c3b" id="r_ae269b2f5b2afd46ae16801762ade2c3b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3b">NEORV32_SPI_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba647a6357971f94b79b7672785c06a4ea">SPI_CTRL_EN</a> = 0 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba4d787c993152a9417fcd50f76820c7b0">SPI_CTRL_CPHA</a> = 1 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba7661acb97cc8c6dd7f333be4f4a2d315">SPI_CTRL_CPOL</a> = 2 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3babc927c4ea78433de697a9fe96f47248e">SPI_CTRL_PRSC0</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba49c38a34b95c034249a094fbc93e0a61">SPI_CTRL_PRSC1</a> = 4 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba7a5244e443e1fe4ff6b7a2176f90ae7a">SPI_CTRL_PRSC2</a> = 5 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3bae6db5cfa843a58d7c09783e7f29fa49f">SPI_CTRL_CDIV0</a> = 6 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba0b9ca202963b68b999f94baab50fbc48">SPI_CTRL_CDIV1</a> = 7 +, <br /> +&#160;&#160;<a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba97aaa7a4ffcc6d17a00c4f992e517c46">SPI_CTRL_CDIV2</a> = 8 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba85164e4e00b5ccd34158f98f691bca29">SPI_CTRL_CDIV3</a> = 9 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3bac38b12af6b8fb6bf2fc6f6ff6baee91e">SPI_CTRL_HIGHSPEED</a> = 10 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba115b097b76b3b99716f54a63c6ce5633">SPI_CTRL_RX_AVAIL</a> = 16 +, <br /> +&#160;&#160;<a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba487b87333d33db0a05cd2a229225ffc6">SPI_CTRL_TX_EMPTY</a> = 17 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba5efcaded20b93d2bffeaa4ea813f73b4">SPI_CTRL_TX_NHALF</a> = 18 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba96860d260b31ee4c232b6b0eb45f7905">SPI_CTRL_TX_FULL</a> = 19 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba2cd2350ffc819b7198d1833b525c5ca0">SPI_CTRL_IRQ_RX_AVAIL</a> = 20 +, <br /> +&#160;&#160;<a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3bafcdc17528f9f4521c02ec5c473b44622">SPI_CTRL_IRQ_TX_EMPTY</a> = 21 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba8c18d975418ad444255f80317448d26b">SPI_CTRL_IRQ_TX_HALF</a> = 22 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba3f80e9c6ef6445ad769038c955c171a2">SPI_CTRL_IRQ_IDLE</a> = 23 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba12f67abd206066651c1d62fc29fafcdb">SPI_CTRL_FIFO_LSB</a> = 24 +, <br /> +&#160;&#160;<a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba8c0426f70974f0ab129481f2db7cf0ed">SPI_CTRL_FIFO_MSB</a> = 27 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba5e12c05349444d3d1defff49dec00580">SPI_CS_ACTIVE</a> = 30 +, <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3ba7957cf1cf3997cd059ed81cba73a688c">SPI_CTRL_BUSY</a> = 31 +<br /> + }</td></tr> +<tr class="separator:ae269b2f5b2afd46ae16801762ade2c3b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aab478c23898c0b06cee53a1cbda38bf8" id="r_aab478c23898c0b06cee53a1cbda38bf8"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aab478c23898c0b06cee53a1cbda38bf8">NEORV32_SPI_DATA_enum</a> { <a class="el" href="#aab478c23898c0b06cee53a1cbda38bf8ae3c36a644c05cea0fccaefb9da90a1b4">SPI_DATA_LSB</a> = 0 +, <a class="el" href="#aab478c23898c0b06cee53a1cbda38bf8a0167ec9c252ee0228ab9d21f4acba600">SPI_DATA_MSB</a> = 1 +, <a class="el" href="#aab478c23898c0b06cee53a1cbda38bf8a5673b6a3382dc5452e3cfcd4e8f3c8a2">SPI_DATA_CSEN</a> = 3 +, <a class="el" href="#aab478c23898c0b06cee53a1cbda38bf8a8b565083f989905b8335d9d22a14c4b6">SPI_DATA_CMD</a> = 31 + }</td></tr> +<tr class="separator:aab478c23898c0b06cee53a1cbda38bf8"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Serial peripheral interface controller (SPI) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a5f3afc4e268670c54d90df67fa38ca22" name="a5f3afc4e268670c54d90df67fa38ca22"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5f3afc4e268670c54d90df67fa38ca22">&#9670;&#160;</a></span>NEORV32_SPI</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_SPI&#160;&#160;&#160;((<a class="el" href="structneorv32__spi__t.html">neorv32_spi_t</a>*) (<a class="el" href="neorv32_8h.html#aa466dc5eace7351bd438606f0f7475a7">NEORV32_SPI_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI module hardware access (<a class="el" href="structneorv32__spi__t.html">neorv32_spi_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="ae269b2f5b2afd46ae16801762ade2c3b" name="ae269b2f5b2afd46ae16801762ade2c3b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae269b2f5b2afd46ae16801762ade2c3b">&#9670;&#160;</a></span>NEORV32_SPI_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3b">NEORV32_SPI_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba647a6357971f94b79b7672785c06a4ea" name="ae269b2f5b2afd46ae16801762ade2c3ba647a6357971f94b79b7672785c06a4ea"></a>SPI_CTRL_EN&#160;</td><td class="fielddoc"><p>SPI control register(0) (r/w): SPI unit enable </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba4d787c993152a9417fcd50f76820c7b0" name="ae269b2f5b2afd46ae16801762ade2c3ba4d787c993152a9417fcd50f76820c7b0"></a>SPI_CTRL_CPHA&#160;</td><td class="fielddoc"><p>SPI control register(1) (r/w): Clock phase </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba7661acb97cc8c6dd7f333be4f4a2d315" name="ae269b2f5b2afd46ae16801762ade2c3ba7661acb97cc8c6dd7f333be4f4a2d315"></a>SPI_CTRL_CPOL&#160;</td><td class="fielddoc"><p>SPI control register(2) (r/w): Clock polarity </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3babc927c4ea78433de697a9fe96f47248e" name="ae269b2f5b2afd46ae16801762ade2c3babc927c4ea78433de697a9fe96f47248e"></a>SPI_CTRL_PRSC0&#160;</td><td class="fielddoc"><p>SPI control register(3) (r/w): Clock prescaler select bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba49c38a34b95c034249a094fbc93e0a61" name="ae269b2f5b2afd46ae16801762ade2c3ba49c38a34b95c034249a094fbc93e0a61"></a>SPI_CTRL_PRSC1&#160;</td><td class="fielddoc"><p>SPI control register(4) (r/w): Clock prescaler select bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba7a5244e443e1fe4ff6b7a2176f90ae7a" name="ae269b2f5b2afd46ae16801762ade2c3ba7a5244e443e1fe4ff6b7a2176f90ae7a"></a>SPI_CTRL_PRSC2&#160;</td><td class="fielddoc"><p>SPI control register(5) (r/w): Clock prescaler select bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3bae6db5cfa843a58d7c09783e7f29fa49f" name="ae269b2f5b2afd46ae16801762ade2c3bae6db5cfa843a58d7c09783e7f29fa49f"></a>SPI_CTRL_CDIV0&#160;</td><td class="fielddoc"><p>SPI control register(6) (r/w): Clock divider bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba0b9ca202963b68b999f94baab50fbc48" name="ae269b2f5b2afd46ae16801762ade2c3ba0b9ca202963b68b999f94baab50fbc48"></a>SPI_CTRL_CDIV1&#160;</td><td class="fielddoc"><p>SPI control register(7) (r/w): Clock divider bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba97aaa7a4ffcc6d17a00c4f992e517c46" name="ae269b2f5b2afd46ae16801762ade2c3ba97aaa7a4ffcc6d17a00c4f992e517c46"></a>SPI_CTRL_CDIV2&#160;</td><td class="fielddoc"><p>SPI control register(8) (r/w): Clock divider bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba85164e4e00b5ccd34158f98f691bca29" name="ae269b2f5b2afd46ae16801762ade2c3ba85164e4e00b5ccd34158f98f691bca29"></a>SPI_CTRL_CDIV3&#160;</td><td class="fielddoc"><p>SPI control register(9) (r/w): Clock divider bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3bac38b12af6b8fb6bf2fc6f6ff6baee91e" name="ae269b2f5b2afd46ae16801762ade2c3bac38b12af6b8fb6bf2fc6f6ff6baee91e"></a>SPI_CTRL_HIGHSPEED&#160;</td><td class="fielddoc"><p>SPI control register(10) (r/w): High-speed mode </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba115b097b76b3b99716f54a63c6ce5633" name="ae269b2f5b2afd46ae16801762ade2c3ba115b097b76b3b99716f54a63c6ce5633"></a>SPI_CTRL_RX_AVAIL&#160;</td><td class="fielddoc"><p>SPI control register(16) (r/-): RX FIFO data available (RX FIFO not empty) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba487b87333d33db0a05cd2a229225ffc6" name="ae269b2f5b2afd46ae16801762ade2c3ba487b87333d33db0a05cd2a229225ffc6"></a>SPI_CTRL_TX_EMPTY&#160;</td><td class="fielddoc"><p>SPI control register(17) (r/-): TX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba5efcaded20b93d2bffeaa4ea813f73b4" name="ae269b2f5b2afd46ae16801762ade2c3ba5efcaded20b93d2bffeaa4ea813f73b4"></a>SPI_CTRL_TX_NHALF&#160;</td><td class="fielddoc"><p>SPI control register(18) (r/-): TX FIFO not at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba96860d260b31ee4c232b6b0eb45f7905" name="ae269b2f5b2afd46ae16801762ade2c3ba96860d260b31ee4c232b6b0eb45f7905"></a>SPI_CTRL_TX_FULL&#160;</td><td class="fielddoc"><p>SPI control register(19) (r/-): TX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba2cd2350ffc819b7198d1833b525c5ca0" name="ae269b2f5b2afd46ae16801762ade2c3ba2cd2350ffc819b7198d1833b525c5ca0"></a>SPI_CTRL_IRQ_RX_AVAIL&#160;</td><td class="fielddoc"><p>SPI control register(20) (r/w): Fire IRQ if RX FIFO data available (RX FIFO not empty) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3bafcdc17528f9f4521c02ec5c473b44622" name="ae269b2f5b2afd46ae16801762ade2c3bafcdc17528f9f4521c02ec5c473b44622"></a>SPI_CTRL_IRQ_TX_EMPTY&#160;</td><td class="fielddoc"><p>SPI control register(21) (r/w): Fire IRQ if TX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba8c18d975418ad444255f80317448d26b" name="ae269b2f5b2afd46ae16801762ade2c3ba8c18d975418ad444255f80317448d26b"></a>SPI_CTRL_IRQ_TX_HALF&#160;</td><td class="fielddoc"><p>SPI control register(22) (r/w): Fire IRQ if TX FIFO not at least half full </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba3f80e9c6ef6445ad769038c955c171a2" name="ae269b2f5b2afd46ae16801762ade2c3ba3f80e9c6ef6445ad769038c955c171a2"></a>SPI_CTRL_IRQ_IDLE&#160;</td><td class="fielddoc"><p>SPI control register(23) (r/w): Fire IRQ if TX FIFO is empty and SPI bus engine is idle </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba12f67abd206066651c1d62fc29fafcdb" name="ae269b2f5b2afd46ae16801762ade2c3ba12f67abd206066651c1d62fc29fafcdb"></a>SPI_CTRL_FIFO_LSB&#160;</td><td class="fielddoc"><p>SPI control register(24) (r/-): log2(FIFO size), lsb </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba8c0426f70974f0ab129481f2db7cf0ed" name="ae269b2f5b2afd46ae16801762ade2c3ba8c0426f70974f0ab129481f2db7cf0ed"></a>SPI_CTRL_FIFO_MSB&#160;</td><td class="fielddoc"><p>SPI control register(27) (r/-): log2(FIFO size), msb </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba5e12c05349444d3d1defff49dec00580" name="ae269b2f5b2afd46ae16801762ade2c3ba5e12c05349444d3d1defff49dec00580"></a>SPI_CS_ACTIVE&#160;</td><td class="fielddoc"><p>SPI control register(30) (r/-): At least one CS line is active when set </p> +</td></tr> +<tr><td class="fieldname"><a id="ae269b2f5b2afd46ae16801762ade2c3ba7957cf1cf3997cd059ed81cba73a688c" name="ae269b2f5b2afd46ae16801762ade2c3ba7957cf1cf3997cd059ed81cba73a688c"></a>SPI_CTRL_BUSY&#160;</td><td class="fielddoc"><p>SPI control register(31) (r/-): SPI busy flag </p> +</td></tr> +</table> + +</div> +</div> +<a id="aab478c23898c0b06cee53a1cbda38bf8" name="aab478c23898c0b06cee53a1cbda38bf8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aab478c23898c0b06cee53a1cbda38bf8">&#9670;&#160;</a></span>NEORV32_SPI_DATA_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#aab478c23898c0b06cee53a1cbda38bf8">NEORV32_SPI_DATA_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI data register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="aab478c23898c0b06cee53a1cbda38bf8ae3c36a644c05cea0fccaefb9da90a1b4" name="aab478c23898c0b06cee53a1cbda38bf8ae3c36a644c05cea0fccaefb9da90a1b4"></a>SPI_DATA_LSB&#160;</td><td class="fielddoc"><p>SPI data register(0) (r/w): Data byte LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="aab478c23898c0b06cee53a1cbda38bf8a0167ec9c252ee0228ab9d21f4acba600" name="aab478c23898c0b06cee53a1cbda38bf8a0167ec9c252ee0228ab9d21f4acba600"></a>SPI_DATA_MSB&#160;</td><td class="fielddoc"><p>SPI data register(1) (r/w): Data byte LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="aab478c23898c0b06cee53a1cbda38bf8a5673b6a3382dc5452e3cfcd4e8f3c8a2" name="aab478c23898c0b06cee53a1cbda38bf8a5673b6a3382dc5452e3cfcd4e8f3c8a2"></a>SPI_DATA_CSEN&#160;</td><td class="fielddoc"><p>SPI data register(3) (-/w): Chip select enable (command-mode only) </p> +</td></tr> +<tr><td class="fieldname"><a id="aab478c23898c0b06cee53a1cbda38bf8a8b565083f989905b8335d9d22a14c4b6" name="aab478c23898c0b06cee53a1cbda38bf8a8b565083f989905b8335d9d22a14c4b6"></a>SPI_DATA_CMD&#160;</td><td class="fielddoc"><p>SPI data register(31) (-/w): Command (=1) / data (=0) select </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a7266ee439d0ec11c5cedd4bf1a258272" name="a7266ee439d0ec11c5cedd4bf1a258272"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7266ee439d0ec11c5cedd4bf1a258272">&#9670;&#160;</a></span>neorv32_spi_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if SPI unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if SPI was not synthesized, 1 if SPI is available. </dd></dl> + +</div> +</div> +<a id="a332c7a1be511812ac0a2b102c165398a" name="a332c7a1be511812ac0a2b102c165398a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a332c7a1be511812ac0a2b102c165398a">&#9670;&#160;</a></span>neorv32_spi_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_busy </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if SPI transceiver is busy or TX FIFO not empty.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if idle, 1 if busy </dd></dl> + +</div> +</div> +<a id="a82bb4d4c222b2bdc57e917c348481501" name="a82bb4d4c222b2bdc57e917c348481501"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a82bb4d4c222b2bdc57e917c348481501">&#9670;&#160;</a></span>neorv32_spi_check_cs()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_check_cs </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if any chip-select line is active.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if no CS lines are active, 1 if at least one CS line is active. </dd></dl> + +</div> +</div> +<a id="aa10ec90ccba6325eeeebb8f6f298d30c" name="aa10ec90ccba6325eeeebb8f6f298d30c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa10ec90ccba6325eeeebb8f6f298d30c">&#9670;&#160;</a></span>neorv32_spi_cs_dis()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_cs_dis </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Deactivate currently active SPI chip select signal.</p> +<dl class="section note"><dt>Note</dt><dd>The SPI chip select output lines are HIGH when deactivated. </dd> +<dd> +This function is blocking. </dd></dl> + +</div> +</div> +<a id="ad8dd1b5a85a9daef4c8c21c9990884c1" name="ad8dd1b5a85a9daef4c8c21c9990884c1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad8dd1b5a85a9daef4c8c21c9990884c1">&#9670;&#160;</a></span>neorv32_spi_cs_dis_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_cs_dis_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Deactivate currently active SPI chip select signal (non-blocking).</p> +<dl class="section note"><dt>Note</dt><dd>The SPI chip select output lines are HIGH when deactivated. </dd></dl> + +</div> +</div> +<a id="a737961d040ac09567350f89034f9e122" name="a737961d040ac09567350f89034f9e122"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a737961d040ac09567350f89034f9e122">&#9670;&#160;</a></span>neorv32_spi_cs_en()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_cs_en </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cs</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Activate single SPI chip select signal.</p> +<dl class="section note"><dt>Note</dt><dd>The SPI chip select output lines are LOW when activated. </dd> +<dd> +This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">cs</td><td>Chip select line to activate (0..7). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a97b5536347a27b053f071ba49071ba6f" name="a97b5536347a27b053f071ba49071ba6f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a97b5536347a27b053f071ba49071ba6f">&#9670;&#160;</a></span>neorv32_spi_cs_en_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_cs_en_nonblocking </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cs</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Activate single SPI chip select signal (non-blocking).</p> +<dl class="section note"><dt>Note</dt><dd>The SPI chip select output lines are LOW when activated.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">cs</td><td>Chip select line to activate (0..7). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a817dd9a38bfceb2048e40874a83ba169" name="a817dd9a38bfceb2048e40874a83ba169"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a817dd9a38bfceb2048e40874a83ba169">&#9670;&#160;</a></span>neorv32_spi_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable SPI controller. </p> + +</div> +</div> +<a id="a8fa25d144ccb20a2faf0450c8dddd16e" name="a8fa25d144ccb20a2faf0450c8dddd16e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8fa25d144ccb20a2faf0450c8dddd16e">&#9670;&#160;</a></span>neorv32_spi_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable SPI controller. </p> + +</div> +</div> +<a id="a01c6b63d7349447e2277f2649c3c89f2" name="a01c6b63d7349447e2277f2649c3c89f2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a01c6b63d7349447e2277f2649c3c89f2">&#9670;&#160;</a></span>neorv32_spi_get_clock_speed()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_spi_get_clock_speed </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get configured clock speed in Hz.</p> +<dl class="section return"><dt>Returns</dt><dd>Actual configured SPI clock speed in Hz. </dd></dl> + +</div> +</div> +<a id="ae1c4da7e4dc2e42b04d7187f684f142c" name="ae1c4da7e4dc2e42b04d7187f684f142c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae1c4da7e4dc2e42b04d7187f684f142c">&#9670;&#160;</a></span>neorv32_spi_get_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_get_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get SPI FIFO depth.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries), zero if no FIFO implemented </dd></dl> + +</div> +</div> +<a id="aad66fa8f8d1a92d4f355de7579bfbfd2" name="aad66fa8f8d1a92d4f355de7579bfbfd2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aad66fa8f8d1a92d4f355de7579bfbfd2">&#9670;&#160;</a></span>neorv32_spi_get_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_spi_get_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get SPI RX data (non-blocking).</p> +<dl class="section return"><dt>Returns</dt><dd>Receive data (8-bit, LSB-aligned). </dd></dl> + +</div> +</div> +<a id="a67e9717635e272bc0e04408135a2f04d" name="a67e9717635e272bc0e04408135a2f04d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a67e9717635e272bc0e04408135a2f04d">&#9670;&#160;</a></span>neorv32_spi_highspeed_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_highspeed_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable high-speed mode. </p> + +</div> +</div> +<a id="acf131faa3ad970c19a3cd8a47cb54f65" name="acf131faa3ad970c19a3cd8a47cb54f65"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acf131faa3ad970c19a3cd8a47cb54f65">&#9670;&#160;</a></span>neorv32_spi_highspeed_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_highspeed_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable high-speed mode. </p> + +</div> +</div> +<a id="aec8583e988789e846d21c2a35e6b06e7" name="aec8583e988789e846d21c2a35e6b06e7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aec8583e988789e846d21c2a35e6b06e7">&#9670;&#160;</a></span>neorv32_spi_put_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_put_nonblocking </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>tx_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Put SPI TX data (non-blocking).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">tx_data</td><td>Transmit data (8-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a7d8124d986b69210081df6f1aa653552" name="a7d8124d986b69210081df6f1aa653552"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7d8124d986b69210081df6f1aa653552">&#9670;&#160;</a></span>neorv32_spi_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_setup </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cdiv</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>clk_phase</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>clk_polarity</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>irq_mask</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable and configure SPI controller. The SPI control register bits are listed in <a class="el" href="#ae269b2f5b2afd46ae16801762ade2c3b">NEORV32_SPI_CTRL_enum</a>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Clock prescaler select (0..7). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. @prama[in] cdiv Clock divider (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">clk_phase</td><td>Clock phase (0=sample on rising edge, 1=sample on falling edge). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">clk_polarity</td><td>Clock polarity (when idle). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mask</td><td>Interrupt configuration mask (CTRL's irq_* bits). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a7af79950eefc26e67a89bde02f255532" name="a7af79950eefc26e67a89bde02f255532"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7af79950eefc26e67a89bde02f255532">&#9670;&#160;</a></span>neorv32_spi_trans()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t neorv32_spi_trans </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>tx_data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Perform a single SPI data transfer.</p> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">tx_data</td><td>Transmit data (8-bit, LSB-aligned). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Receive data (8-bit, LSB-aligned). </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__spi_8h_source.html b/sw/neorv32__spi_8h_source.html new file mode 100644 index 000000000..099922941 --- /dev/null +++ b/sw/neorv32__spi_8h_source.html @@ -0,0 +1,231 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_spi.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_spi_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_spi_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__spi__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__spi__t.html#a34fa748f0e3ceb75822c0a5553bd0420"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__spi__t.html#a34fa748f0e3ceb75822c0a5553bd0420">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__spi__t.html#a3901bad351213e34820197a33d589f1e"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__spi__t.html#a3901bad351213e34820197a33d589f1e">DATA</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__spi__t.html">neorv32_spi_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#a5f3afc4e268670c54d90df67fa38ca22"> 35</a></span><span class="preprocessor">#define NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE))</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="foldopen" id="foldopen00038" data-start="{" data-end="};"> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3b"> 38</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3b">NEORV32_SPI_CTRL_enum</a> {</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba647a6357971f94b79b7672785c06a4ea"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba647a6357971f94b79b7672785c06a4ea">SPI_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba4d787c993152a9417fcd50f76820c7b0"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba4d787c993152a9417fcd50f76820c7b0">SPI_CTRL_CPHA</a> = 1, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7661acb97cc8c6dd7f333be4f4a2d315"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7661acb97cc8c6dd7f333be4f4a2d315">SPI_CTRL_CPOL</a> = 2, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3babc927c4ea78433de697a9fe96f47248e"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3babc927c4ea78433de697a9fe96f47248e">SPI_CTRL_PRSC0</a> = 3, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba49c38a34b95c034249a094fbc93e0a61"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba49c38a34b95c034249a094fbc93e0a61">SPI_CTRL_PRSC1</a> = 4, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7a5244e443e1fe4ff6b7a2176f90ae7a"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7a5244e443e1fe4ff6b7a2176f90ae7a">SPI_CTRL_PRSC2</a> = 5, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bae6db5cfa843a58d7c09783e7f29fa49f"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bae6db5cfa843a58d7c09783e7f29fa49f">SPI_CTRL_CDIV0</a> = 6, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba0b9ca202963b68b999f94baab50fbc48"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba0b9ca202963b68b999f94baab50fbc48">SPI_CTRL_CDIV1</a> = 7, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba97aaa7a4ffcc6d17a00c4f992e517c46"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba97aaa7a4ffcc6d17a00c4f992e517c46">SPI_CTRL_CDIV2</a> = 8, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba85164e4e00b5ccd34158f98f691bca29"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba85164e4e00b5ccd34158f98f691bca29">SPI_CTRL_CDIV3</a> = 9, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bac38b12af6b8fb6bf2fc6f6ff6baee91e"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bac38b12af6b8fb6bf2fc6f6ff6baee91e">SPI_CTRL_HIGHSPEED</a> = 10, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba115b097b76b3b99716f54a63c6ce5633"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba115b097b76b3b99716f54a63c6ce5633">SPI_CTRL_RX_AVAIL</a> = 16, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba487b87333d33db0a05cd2a229225ffc6"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba487b87333d33db0a05cd2a229225ffc6">SPI_CTRL_TX_EMPTY</a> = 17, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba5efcaded20b93d2bffeaa4ea813f73b4"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba5efcaded20b93d2bffeaa4ea813f73b4">SPI_CTRL_TX_NHALF</a> = 18, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba96860d260b31ee4c232b6b0eb45f7905"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba96860d260b31ee4c232b6b0eb45f7905">SPI_CTRL_TX_FULL</a> = 19, </div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba2cd2350ffc819b7198d1833b525c5ca0"> 56</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba2cd2350ffc819b7198d1833b525c5ca0">SPI_CTRL_IRQ_RX_AVAIL</a> = 20, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bafcdc17528f9f4521c02ec5c473b44622"> 57</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bafcdc17528f9f4521c02ec5c473b44622">SPI_CTRL_IRQ_TX_EMPTY</a> = 21, </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba8c18d975418ad444255f80317448d26b"> 58</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba8c18d975418ad444255f80317448d26b">SPI_CTRL_IRQ_TX_HALF</a> = 22, </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba3f80e9c6ef6445ad769038c955c171a2"> 59</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba3f80e9c6ef6445ad769038c955c171a2">SPI_CTRL_IRQ_IDLE</a> = 23, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba12f67abd206066651c1d62fc29fafcdb"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba12f67abd206066651c1d62fc29fafcdb">SPI_CTRL_FIFO_LSB</a> = 24, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba8c0426f70974f0ab129481f2db7cf0ed"> 62</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba8c0426f70974f0ab129481f2db7cf0ed">SPI_CTRL_FIFO_MSB</a> = 27, </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba5e12c05349444d3d1defff49dec00580"> 64</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba5e12c05349444d3d1defff49dec00580">SPI_CS_ACTIVE</a> = 30, </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7957cf1cf3997cd059ed81cba73a688c">SPI_CTRL_BUSY</a> = 31 </div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7957cf1cf3997cd059ed81cba73a688c"> 66</a></span>};</div> +</div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span> </div> +<div class="foldopen" id="foldopen00069" data-start="{" data-end="};"> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8"> 69</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8">NEORV32_SPI_DATA_enum</a> {</div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8ae3c36a644c05cea0fccaefb9da90a1b4"> 70</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8ae3c36a644c05cea0fccaefb9da90a1b4">SPI_DATA_LSB</a> = 0, </div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a0167ec9c252ee0228ab9d21f4acba600"> 71</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a0167ec9c252ee0228ab9d21f4acba600">SPI_DATA_MSB</a> = 1, </div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a5673b6a3382dc5452e3cfcd4e8f3c8a2"> 72</a></span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a5673b6a3382dc5452e3cfcd4e8f3c8a2">SPI_DATA_CSEN</a> = 3, </div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span> <a class="code hl_enumvalue" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a8b565083f989905b8335d9d22a14c4b6">SPI_DATA_CMD</a> = 31 </div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"><a class="line" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a8b565083f989905b8335d9d22a14c4b6"> 74</a></span>};</div> +</div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__spi_8h.html#a7266ee439d0ec11c5cedd4bf1a258272">neorv32_spi_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#a7d8124d986b69210081df6f1aa653552">neorv32_spi_setup</a>(<span class="keywordtype">int</span> prsc, <span class="keywordtype">int</span> cdiv, <span class="keywordtype">int</span> clk_phase, <span class="keywordtype">int</span> clk_polarity, uint32_t irq_mask);</div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#acf131faa3ad970c19a3cd8a47cb54f65">neorv32_spi_highspeed_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#a67e9717635e272bc0e04408135a2f04d">neorv32_spi_highspeed_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span>uint32_t <a class="code hl_function" href="neorv32__spi_8h.html#a01c6b63d7349447e2277f2649c3c89f2">neorv32_spi_get_clock_speed</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#a817dd9a38bfceb2048e40874a83ba169">neorv32_spi_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#a8fa25d144ccb20a2faf0450c8dddd16e">neorv32_spi_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__spi_8h.html#ae1c4da7e4dc2e42b04d7187f684f142c">neorv32_spi_get_fifo_depth</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#a737961d040ac09567350f89034f9e122">neorv32_spi_cs_en</a>(<span class="keywordtype">int</span> cs);</div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#aa10ec90ccba6325eeeebb8f6f298d30c">neorv32_spi_cs_dis</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span>uint8_t <a class="code hl_function" href="neorv32__spi_8h.html#a7af79950eefc26e67a89bde02f255532">neorv32_spi_trans</a>(uint8_t tx_data);</div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#aec8583e988789e846d21c2a35e6b06e7">neorv32_spi_put_nonblocking</a>(uint8_t tx_data);</div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span>uint8_t <a class="code hl_function" href="neorv32__spi_8h.html#aad66fa8f8d1a92d4f355de7579bfbfd2">neorv32_spi_get_nonblocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#a97b5536347a27b053f071ba49071ba6f">neorv32_spi_cs_en_nonblocking</a>(<span class="keywordtype">int</span> cs);</div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi_8h.html#ad8dd1b5a85a9daef4c8c21c9990884c1">neorv32_spi_cs_dis_nonblocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__spi_8h.html#a82bb4d4c222b2bdc57e917c348481501">neorv32_spi_check_cs</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__spi_8h.html#a332c7a1be511812ac0a2b102c165398a">neorv32_spi_busy</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_spi_h</span></div> +<div class="ttc" id="aneorv32__spi_8h_html_a01c6b63d7349447e2277f2649c3c89f2"><div class="ttname"><a href="neorv32__spi_8h.html#a01c6b63d7349447e2277f2649c3c89f2">neorv32_spi_get_clock_speed</a></div><div class="ttdeci">uint32_t neorv32_spi_get_clock_speed(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:85</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a332c7a1be511812ac0a2b102c165398a"><div class="ttname"><a href="neorv32__spi_8h.html#a332c7a1be511812ac0a2b102c165398a">neorv32_spi_busy</a></div><div class="ttdeci">int neorv32_spi_busy(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:247</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a67e9717635e272bc0e04408135a2f04d"><div class="ttname"><a href="neorv32__spi_8h.html#a67e9717635e272bc0e04408135a2f04d">neorv32_spi_highspeed_disable</a></div><div class="ttdeci">void neorv32_spi_highspeed_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:74</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a7266ee439d0ec11c5cedd4bf1a258272"><div class="ttname"><a href="neorv32__spi_8h.html#a7266ee439d0ec11c5cedd4bf1a258272">neorv32_spi_available</a></div><div class="ttdeci">int neorv32_spi_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:26</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a737961d040ac09567350f89034f9e122"><div class="ttname"><a href="neorv32__spi_8h.html#a737961d040ac09567350f89034f9e122">neorv32_spi_cs_en</a></div><div class="ttdeci">void neorv32_spi_cs_en(int cs)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:144</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a7af79950eefc26e67a89bde02f255532"><div class="ttname"><a href="neorv32__spi_8h.html#a7af79950eefc26e67a89bde02f255532">neorv32_spi_trans</a></div><div class="ttdeci">uint8_t neorv32_spi_trans(uint8_t tx_data)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:172</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a7d8124d986b69210081df6f1aa653552"><div class="ttname"><a href="neorv32__spi_8h.html#a7d8124d986b69210081df6f1aa653552">neorv32_spi_setup</a></div><div class="ttdeci">void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t irq_mask)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:46</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a817dd9a38bfceb2048e40874a83ba169"><div class="ttname"><a href="neorv32__spi_8h.html#a817dd9a38bfceb2048e40874a83ba169">neorv32_spi_disable</a></div><div class="ttdeci">void neorv32_spi_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:109</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a82bb4d4c222b2bdc57e917c348481501"><div class="ttname"><a href="neorv32__spi_8h.html#a82bb4d4c222b2bdc57e917c348481501">neorv32_spi_check_cs</a></div><div class="ttdeci">int neorv32_spi_check_cs(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:231</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a8fa25d144ccb20a2faf0450c8dddd16e"><div class="ttname"><a href="neorv32__spi_8h.html#a8fa25d144ccb20a2faf0450c8dddd16e">neorv32_spi_enable</a></div><div class="ttdeci">void neorv32_spi_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:118</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_a97b5536347a27b053f071ba49071ba6f"><div class="ttname"><a href="neorv32__spi_8h.html#a97b5536347a27b053f071ba49071ba6f">neorv32_spi_cs_en_nonblocking</a></div><div class="ttdeci">void neorv32_spi_cs_en_nonblocking(int cs)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:209</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_aa10ec90ccba6325eeeebb8f6f298d30c"><div class="ttname"><a href="neorv32__spi_8h.html#aa10ec90ccba6325eeeebb8f6f298d30c">neorv32_spi_cs_dis</a></div><div class="ttdeci">void neorv32_spi_cs_dis(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:157</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_aab478c23898c0b06cee53a1cbda38bf8"><div class="ttname"><a href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8">NEORV32_SPI_DATA_enum</a></div><div class="ttdeci">NEORV32_SPI_DATA_enum</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:69</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_aab478c23898c0b06cee53a1cbda38bf8a0167ec9c252ee0228ab9d21f4acba600"><div class="ttname"><a href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a0167ec9c252ee0228ab9d21f4acba600">SPI_DATA_MSB</a></div><div class="ttdeci">@ SPI_DATA_MSB</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:71</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_aab478c23898c0b06cee53a1cbda38bf8a5673b6a3382dc5452e3cfcd4e8f3c8a2"><div class="ttname"><a href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a5673b6a3382dc5452e3cfcd4e8f3c8a2">SPI_DATA_CSEN</a></div><div class="ttdeci">@ SPI_DATA_CSEN</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:72</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_aab478c23898c0b06cee53a1cbda38bf8a8b565083f989905b8335d9d22a14c4b6"><div class="ttname"><a href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8a8b565083f989905b8335d9d22a14c4b6">SPI_DATA_CMD</a></div><div class="ttdeci">@ SPI_DATA_CMD</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:73</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_aab478c23898c0b06cee53a1cbda38bf8ae3c36a644c05cea0fccaefb9da90a1b4"><div class="ttname"><a href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8ae3c36a644c05cea0fccaefb9da90a1b4">SPI_DATA_LSB</a></div><div class="ttdeci">@ SPI_DATA_LSB</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:70</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_aad66fa8f8d1a92d4f355de7579bfbfd2"><div class="ttname"><a href="neorv32__spi_8h.html#aad66fa8f8d1a92d4f355de7579bfbfd2">neorv32_spi_get_nonblocking</a></div><div class="ttdeci">uint8_t neorv32_spi_get_nonblocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:196</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_acf131faa3ad970c19a3cd8a47cb54f65"><div class="ttname"><a href="neorv32__spi_8h.html#acf131faa3ad970c19a3cd8a47cb54f65">neorv32_spi_highspeed_enable</a></div><div class="ttdeci">void neorv32_spi_highspeed_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:65</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ad8dd1b5a85a9daef4c8c21c9990884c1"><div class="ttname"><a href="neorv32__spi_8h.html#ad8dd1b5a85a9daef4c8c21c9990884c1">neorv32_spi_cs_dis_nonblocking</a></div><div class="ttdeci">void neorv32_spi_cs_dis_nonblocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:220</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae1c4da7e4dc2e42b04d7187f684f142c"><div class="ttname"><a href="neorv32__spi_8h.html#ae1c4da7e4dc2e42b04d7187f684f142c">neorv32_spi_get_fifo_depth</a></div><div class="ttdeci">int neorv32_spi_get_fifo_depth(void)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:129</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3b"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3b">NEORV32_SPI_CTRL_enum</a></div><div class="ttdeci">NEORV32_SPI_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:38</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba0b9ca202963b68b999f94baab50fbc48"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba0b9ca202963b68b999f94baab50fbc48">SPI_CTRL_CDIV1</a></div><div class="ttdeci">@ SPI_CTRL_CDIV1</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:46</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba115b097b76b3b99716f54a63c6ce5633"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba115b097b76b3b99716f54a63c6ce5633">SPI_CTRL_RX_AVAIL</a></div><div class="ttdeci">@ SPI_CTRL_RX_AVAIL</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:51</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba12f67abd206066651c1d62fc29fafcdb"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba12f67abd206066651c1d62fc29fafcdb">SPI_CTRL_FIFO_LSB</a></div><div class="ttdeci">@ SPI_CTRL_FIFO_LSB</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:61</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba2cd2350ffc819b7198d1833b525c5ca0"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba2cd2350ffc819b7198d1833b525c5ca0">SPI_CTRL_IRQ_RX_AVAIL</a></div><div class="ttdeci">@ SPI_CTRL_IRQ_RX_AVAIL</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:56</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba3f80e9c6ef6445ad769038c955c171a2"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba3f80e9c6ef6445ad769038c955c171a2">SPI_CTRL_IRQ_IDLE</a></div><div class="ttdeci">@ SPI_CTRL_IRQ_IDLE</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:59</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba487b87333d33db0a05cd2a229225ffc6"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba487b87333d33db0a05cd2a229225ffc6">SPI_CTRL_TX_EMPTY</a></div><div class="ttdeci">@ SPI_CTRL_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:52</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba49c38a34b95c034249a094fbc93e0a61"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba49c38a34b95c034249a094fbc93e0a61">SPI_CTRL_PRSC1</a></div><div class="ttdeci">@ SPI_CTRL_PRSC1</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:43</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba4d787c993152a9417fcd50f76820c7b0"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba4d787c993152a9417fcd50f76820c7b0">SPI_CTRL_CPHA</a></div><div class="ttdeci">@ SPI_CTRL_CPHA</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:40</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba5e12c05349444d3d1defff49dec00580"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba5e12c05349444d3d1defff49dec00580">SPI_CS_ACTIVE</a></div><div class="ttdeci">@ SPI_CS_ACTIVE</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:64</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba5efcaded20b93d2bffeaa4ea813f73b4"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba5efcaded20b93d2bffeaa4ea813f73b4">SPI_CTRL_TX_NHALF</a></div><div class="ttdeci">@ SPI_CTRL_TX_NHALF</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:53</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba647a6357971f94b79b7672785c06a4ea"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba647a6357971f94b79b7672785c06a4ea">SPI_CTRL_EN</a></div><div class="ttdeci">@ SPI_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:39</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba7661acb97cc8c6dd7f333be4f4a2d315"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7661acb97cc8c6dd7f333be4f4a2d315">SPI_CTRL_CPOL</a></div><div class="ttdeci">@ SPI_CTRL_CPOL</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:41</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba7957cf1cf3997cd059ed81cba73a688c"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7957cf1cf3997cd059ed81cba73a688c">SPI_CTRL_BUSY</a></div><div class="ttdeci">@ SPI_CTRL_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:65</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba7a5244e443e1fe4ff6b7a2176f90ae7a"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba7a5244e443e1fe4ff6b7a2176f90ae7a">SPI_CTRL_PRSC2</a></div><div class="ttdeci">@ SPI_CTRL_PRSC2</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:44</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba85164e4e00b5ccd34158f98f691bca29"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba85164e4e00b5ccd34158f98f691bca29">SPI_CTRL_CDIV3</a></div><div class="ttdeci">@ SPI_CTRL_CDIV3</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:48</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba8c0426f70974f0ab129481f2db7cf0ed"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba8c0426f70974f0ab129481f2db7cf0ed">SPI_CTRL_FIFO_MSB</a></div><div class="ttdeci">@ SPI_CTRL_FIFO_MSB</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:62</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba8c18d975418ad444255f80317448d26b"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba8c18d975418ad444255f80317448d26b">SPI_CTRL_IRQ_TX_HALF</a></div><div class="ttdeci">@ SPI_CTRL_IRQ_TX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:58</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba96860d260b31ee4c232b6b0eb45f7905"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba96860d260b31ee4c232b6b0eb45f7905">SPI_CTRL_TX_FULL</a></div><div class="ttdeci">@ SPI_CTRL_TX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:54</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3ba97aaa7a4ffcc6d17a00c4f992e517c46"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3ba97aaa7a4ffcc6d17a00c4f992e517c46">SPI_CTRL_CDIV2</a></div><div class="ttdeci">@ SPI_CTRL_CDIV2</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:47</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3babc927c4ea78433de697a9fe96f47248e"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3babc927c4ea78433de697a9fe96f47248e">SPI_CTRL_PRSC0</a></div><div class="ttdeci">@ SPI_CTRL_PRSC0</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:42</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3bac38b12af6b8fb6bf2fc6f6ff6baee91e"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bac38b12af6b8fb6bf2fc6f6ff6baee91e">SPI_CTRL_HIGHSPEED</a></div><div class="ttdeci">@ SPI_CTRL_HIGHSPEED</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:49</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3bae6db5cfa843a58d7c09783e7f29fa49f"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bae6db5cfa843a58d7c09783e7f29fa49f">SPI_CTRL_CDIV0</a></div><div class="ttdeci">@ SPI_CTRL_CDIV0</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:45</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_ae269b2f5b2afd46ae16801762ade2c3bafcdc17528f9f4521c02ec5c473b44622"><div class="ttname"><a href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3bafcdc17528f9f4521c02ec5c473b44622">SPI_CTRL_IRQ_TX_EMPTY</a></div><div class="ttdeci">@ SPI_CTRL_IRQ_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:57</div></div> +<div class="ttc" id="aneorv32__spi_8h_html_aec8583e988789e846d21c2a35e6b06e7"><div class="ttname"><a href="neorv32__spi_8h.html#aec8583e988789e846d21c2a35e6b06e7">neorv32_spi_put_nonblocking</a></div><div class="ttdeci">void neorv32_spi_put_nonblocking(uint8_t tx_data)</div><div class="ttdef"><b>Definition</b> neorv32_spi.c:185</div></div> +<div class="ttc" id="astructneorv32__spi__t_html"><div class="ttname"><a href="structneorv32__spi__t.html">neorv32_spi_t</a></div><div class="ttdef"><b>Definition</b> neorv32_spi.h:29</div></div> +<div class="ttc" id="astructneorv32__spi__t_html_a34fa748f0e3ceb75822c0a5553bd0420"><div class="ttname"><a href="structneorv32__spi__t.html#a34fa748f0e3ceb75822c0a5553bd0420">neorv32_spi_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:30</div></div> +<div class="ttc" id="astructneorv32__spi__t_html_a3901bad351213e34820197a33d589f1e"><div class="ttname"><a href="structneorv32__spi__t.html#a3901bad351213e34820197a33d589f1e">neorv32_spi_t::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition</b> neorv32_spi.h:31</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__spi__irq_8c.html b/sw/neorv32__spi__irq_8c.html new file mode 100644 index 000000000..0f7335fe1 --- /dev/null +++ b/sw/neorv32__spi__irq_8c.html @@ -0,0 +1,257 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_spi_irq/drv/neorv32_spi_irq.c File Reference</title> +<link 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Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* 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href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_f0f9b27afba2e8cc2da6e5fddcc1a8c9.html">example</a></li><li class="navelem"><a class="el" href="dir_8f848e36ac87ced1c361afcc0549ca32.html">demo_spi_irq</a></li><li class="navelem"><a class="el" href="dir_9d04cdc586d6978be343bda7adcdc371.html">drv</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_spi_irq.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Addition to <a class="el" href="neorv32__spi_8c.html" title="Serial peripheral interface controller (SPI) HW driver source file.">neorv32_spi.c</a>, which provides an IRQ driven data flow. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &quot;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&quot;</code><br /> +<code>#include &quot;<a class="el" href="neorv32__spi__irq_8h_source.html">neorv32_spi_irq.h</a>&quot;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a4aa4746fd210ecc0c3614089a6951ddf" id="r_a4aa4746fd210ecc0c3614089a6951ddf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4aa4746fd210ecc0c3614089a6951ddf">neorv32_spi_init</a> (<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self)</td></tr> +<tr class="separator:a4aa4746fd210ecc0c3614089a6951ddf"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa641816bb302df497664aa21ea69ed16" id="r_aa641816bb302df497664aa21ea69ed16"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa641816bb302df497664aa21ea69ed16">neorv32_spi_isr</a> (<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self)</td></tr> +<tr class="separator:aa641816bb302df497664aa21ea69ed16"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1f44ed849415d8e1d659c0485762c485" id="r_a1f44ed849415d8e1d659c0485762c485"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1f44ed849415d8e1d659c0485762c485">neorv32_spi_rw</a> (<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self, uint8_t csn, void *spi, uint32_t len)</td></tr> +<tr class="separator:a1f44ed849415d8e1d659c0485762c485"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1863e19932bc6a79f2ca27d23eb74ef5" id="r_a1863e19932bc6a79f2ca27d23eb74ef5"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1863e19932bc6a79f2ca27d23eb74ef5">neorv32_spi_rw_busy</a> (<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self)</td></tr> +<tr class="separator:a1863e19932bc6a79f2ca27d23eb74ef5"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Addition to <a class="el" href="neorv32__spi_8c.html" title="Serial peripheral interface controller (SPI) HW driver source file.">neorv32_spi.c</a>, which provides an IRQ driven data flow. </p> +<dl class="section author"><dt>Author</dt><dd>Andreas Kaeberlein </dd></dl> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true). </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a4aa4746fd210ecc0c3614089a6951ddf" name="a4aa4746fd210ecc0c3614089a6951ddf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4aa4746fd210ecc0c3614089a6951ddf">&#9670;&#160;</a></span>neorv32_spi_init()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_init </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *</td> <td class="paramname"><span class="paramname"><em>self</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initializes SPI flow control handle. The data structure elements are listed in <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*self</td><td>SPI driver common data handle. See <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aa641816bb302df497664aa21ea69ed16" name="aa641816bb302df497664aa21ea69ed16"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa641816bb302df497664aa21ea69ed16">&#9670;&#160;</a></span>neorv32_spi_isr()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_isr </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *</td> <td class="paramname"><span class="paramname"><em>self</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI interrupt service routine. The data structure elements are listed in <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*self</td><td>SPI driver common data handle. See <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a1f44ed849415d8e1d659c0485762c485" name="a1f44ed849415d8e1d659c0485762c485"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1f44ed849415d8e1d659c0485762c485">&#9670;&#160;</a></span>neorv32_spi_rw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_rw </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *</td> <td class="paramname"><span class="paramname"><em>self</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>csn</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">void *</td> <td class="paramname"><span class="paramname"><em>spi</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>len</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Starts ISR driven read/write SPI transfer.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*self</td><td>SPI driver common data handle. See <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">csn</td><td>Used chip select index for transfer. </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*spi</td><td>write/read data buffer for SPI. Before transmission contents the write data and after the read data. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">len</td><td>number of bytes to transfer. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>int status of function. </dd></dl> +<dl class="retval"><dt>Return values</dt><dd> + <table class="retval"> + <tr><td class="paramname">0</td><td>new transfer started. </td></tr> + <tr><td class="paramname">1</td><td>transfer active, refused request. </td></tr> + <tr><td class="paramname">2</td><td>unsupported data size, only 1/2/4 allowed. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a1863e19932bc6a79f2ca27d23eb74ef5" name="a1863e19932bc6a79f2ca27d23eb74ef5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1863e19932bc6a79f2ca27d23eb74ef5">&#9670;&#160;</a></span>neorv32_spi_rw_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_rw_busy </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *</td> <td class="paramname"><span class="paramname"><em>self</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if transfer is active. see <a class="el" href="#a1f44ed849415d8e1d659c0485762c485">neorv32_spi_rw</a></p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*self</td><td>SPI driver common data handle. See <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>int status of function. </dd></dl> +<dl class="retval"><dt>Return values</dt><dd> + <table class="retval"> + <tr><td class="paramname">0</td><td>idle. </td></tr> + <tr><td class="paramname">1</td><td>busy. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__spi__irq_8h.html b/sw/neorv32__spi__irq_8h.html new file mode 100644 index 000000000..63eceb0c4 --- /dev/null +++ b/sw/neorv32__spi__irq_8h.html @@ -0,0 +1,301 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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href="#nested-classes">Data Structures</a> &#124; +<a href="#define-members">Macros</a> &#124; +<a href="#typedef-members">Typedefs</a> &#124; +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_spi_irq.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Addition to <a class="el" href="neorv32__spi_8h.html" title="Serial peripheral interface controller (SPI) HW driver header file.">neorv32_spi.h</a>, which provides an IRQ driven data flow. +<a href="#details">More...</a></p> + +<p><a href="neorv32__spi__irq_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:ac6afabdc09a49a433ee19d8a9486056d" id="r_ac6afabdc09a49a433ee19d8a9486056d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac6afabdc09a49a433ee19d8a9486056d">min</a>(a, b)</td></tr> +<tr class="separator:ac6afabdc09a49a433ee19d8a9486056d"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="typedef-members" name="typedef-members"></a> +Typedefs</h2></td></tr> +<tr class="memitem:a1bff352570118788aafc29fcc41c27f9" id="r_a1bff352570118788aafc29fcc41c27f9"><td class="memItemLeft" align="right" valign="top"><a id="a1bff352570118788aafc29fcc41c27f9" name="a1bff352570118788aafc29fcc41c27f9"></a> +typedef struct t_neorv32_spi&#160;</td><td class="memItemRight" valign="bottom"><b>t_neorv32_spi</b></td></tr> +<tr class="separator:a1bff352570118788aafc29fcc41c27f9"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a4aa4746fd210ecc0c3614089a6951ddf" id="r_a4aa4746fd210ecc0c3614089a6951ddf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4aa4746fd210ecc0c3614089a6951ddf">neorv32_spi_init</a> (<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self)</td></tr> +<tr class="separator:a4aa4746fd210ecc0c3614089a6951ddf"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa641816bb302df497664aa21ea69ed16" id="r_aa641816bb302df497664aa21ea69ed16"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa641816bb302df497664aa21ea69ed16">neorv32_spi_isr</a> (<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self)</td></tr> +<tr class="separator:aa641816bb302df497664aa21ea69ed16"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1f44ed849415d8e1d659c0485762c485" id="r_a1f44ed849415d8e1d659c0485762c485"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1f44ed849415d8e1d659c0485762c485">neorv32_spi_rw</a> (<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self, uint8_t csn, void *spi, uint32_t len)</td></tr> +<tr class="separator:a1f44ed849415d8e1d659c0485762c485"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1863e19932bc6a79f2ca27d23eb74ef5" id="r_a1863e19932bc6a79f2ca27d23eb74ef5"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1863e19932bc6a79f2ca27d23eb74ef5">neorv32_spi_rw_busy</a> (<a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self)</td></tr> +<tr class="separator:a1863e19932bc6a79f2ca27d23eb74ef5"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Addition to <a class="el" href="neorv32__spi_8h.html" title="Serial peripheral interface controller (SPI) HW driver header file.">neorv32_spi.h</a>, which provides an IRQ driven data flow. </p> +<dl class="section author"><dt>Author</dt><dd>Andreas Kaeberlein </dd></dl> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true). </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="ac6afabdc09a49a433ee19d8a9486056d" name="ac6afabdc09a49a433ee19d8a9486056d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac6afabdc09a49a433ee19d8a9486056d">&#9670;&#160;</a></span>min</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define min</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>a</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>b</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"> ({ __typeof__ (a) _a = (a); \</div> +<div class="line"> __typeof__ (b) _b = (b); \</div> +<div class="line"> _a &lt; _b ? _a : _b; })</div> +</div><!-- fragment --> +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a4aa4746fd210ecc0c3614089a6951ddf" name="a4aa4746fd210ecc0c3614089a6951ddf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4aa4746fd210ecc0c3614089a6951ddf">&#9670;&#160;</a></span>neorv32_spi_init()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_init </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *</td> <td class="paramname"><span class="paramname"><em>self</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initializes SPI flow control handle. The data structure elements are listed in <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*self</td><td>SPI driver common data handle. See <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aa641816bb302df497664aa21ea69ed16" name="aa641816bb302df497664aa21ea69ed16"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa641816bb302df497664aa21ea69ed16">&#9670;&#160;</a></span>neorv32_spi_isr()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_spi_isr </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *</td> <td class="paramname"><span class="paramname"><em>self</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI interrupt service routine. The data structure elements are listed in <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*self</td><td>SPI driver common data handle. See <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a1f44ed849415d8e1d659c0485762c485" name="a1f44ed849415d8e1d659c0485762c485"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1f44ed849415d8e1d659c0485762c485">&#9670;&#160;</a></span>neorv32_spi_rw()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_rw </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *</td> <td class="paramname"><span class="paramname"><em>self</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>csn</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">void *</td> <td class="paramname"><span class="paramname"><em>spi</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>len</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Starts ISR driven read/write SPI transfer.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*self</td><td>SPI driver common data handle. See <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">csn</td><td>Used chip select index for transfer. </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*spi</td><td>write/read data buffer for SPI. Before transmission contents the write data and after the read data. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">len</td><td>number of bytes to transfer. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>int status of function. </dd></dl> +<dl class="retval"><dt>Return values</dt><dd> + <table class="retval"> + <tr><td class="paramname">0</td><td>new transfer started. </td></tr> + <tr><td class="paramname">1</td><td>transfer active, refused request. </td></tr> + <tr><td class="paramname">2</td><td>unsupported data size, only 1/2/4 allowed. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a1863e19932bc6a79f2ca27d23eb74ef5" name="a1863e19932bc6a79f2ca27d23eb74ef5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1863e19932bc6a79f2ca27d23eb74ef5">&#9670;&#160;</a></span>neorv32_spi_rw_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_spi_rw_busy </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a> *</td> <td class="paramname"><span class="paramname"><em>self</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if transfer is active. see <a class="el" href="neorv32__spi__irq_8c.html#a1f44ed849415d8e1d659c0485762c485">neorv32_spi_rw</a></p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">*self</td><td>SPI driver common data handle. See <a class="el" href="structt__neorv32__spi.html">t_neorv32_spi</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>int status of function. </dd></dl> +<dl class="retval"><dt>Return values</dt><dd> + <table class="retval"> + <tr><td class="paramname">0</td><td>idle. </td></tr> + <tr><td class="paramname">1</td><td>busy. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__spi__irq_8h_source.html b/sw/neorv32__spi__irq_8h_source.html new file mode 100644 index 000000000..a99ff9971 --- /dev/null +++ b/sw/neorv32__spi__irq_8h_source.html @@ -0,0 +1,183 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_spi_irq/drv/neorv32_spi_irq.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. #</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="comment">// # Redistribution and use in source and binary forms, with or without modification, are #</span></div> +<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="comment">// # permitted provided that the following conditions are met: #</span></div> +<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="comment">// # 1. Redistributions of source code must retain the above copyright notice, this list of #</span></div> +<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="comment">// # conditions and the following disclaimer. #</span></div> +<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span><span class="comment">// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #</span></div> +<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="comment">// # conditions and the following disclaimer in the documentation and/or other materials #</span></div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="comment">// # provided with the distribution. #</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="comment">// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="comment">// # endorse or promote products derived from this software without specific prior written #</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="comment">// # permission. #</span></div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="comment">// # #</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS &quot;AS IS&quot; AND ANY EXPRESS #</span></div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span><span class="comment">// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #</span></div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #</span></div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span><span class="comment">// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #</span></div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span><span class="comment">// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #</span></div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span><span class="comment">// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #</span></div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span><span class="comment">// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #</span></div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span><span class="comment">// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #</span></div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span><span class="comment">// # OF THE POSSIBILITY OF SUCH DAMAGE. #</span></div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span><span class="comment">// # ********************************************************************************************* #</span></div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span><span class="comment">// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #</span></div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span><span class="comment">// #################################################################################################</span></div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="preprocessor">#ifndef neorv32_spi_irq_h</span></div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span><span class="preprocessor">#define neorv32_spi_irq_h</span></div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span><span class="comment">// MIN macro</span></div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="comment">// https://stackoverflow.com/questions/3437404/min-and-max-in-c</span></div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span><span class="preprocessor">#define min(a,b) \</span></div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span><span class="preprocessor"> ({ __typeof__ (a) _a = (a); \</span></div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span><span class="preprocessor"> __typeof__ (b) _b = (b); \</span></div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="preprocessor"> _a &lt; _b ? _a : _b; })</span></div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span> </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span><span class="comment">// data handle for ISR</span></div> +<div class="foldopen" id="foldopen00055" data-start="{" data-end="};"> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="structt__neorv32__spi.html"> 55</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structt__neorv32__spi.html">t_neorv32_spi</a></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span>{</div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="structt__neorv32__spi.html#a487a6510820871ff8d0da7699463f6d9"> 57</a></span> uint8_t* <a class="code hl_variable" href="structt__neorv32__spi.html#a487a6510820871ff8d0da7699463f6d9">ptrSpiBuf</a>; </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="structt__neorv32__spi.html#a435c266758a440d32de4344472e3514a"> 58</a></span> uint8_t <a class="code hl_variable" href="structt__neorv32__spi.html#a435c266758a440d32de4344472e3514a">uint8Csn</a>; </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="structt__neorv32__spi.html#a71fb3f91af197e1abdbe97d62130ad0f"> 59</a></span> uint16_t <a class="code hl_variable" href="structt__neorv32__spi.html#a71fb3f91af197e1abdbe97d62130ad0f">uint16Fifo</a>; </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="structt__neorv32__spi.html#aa4d96f72e57fb6930ab43de6fb0a85ae"> 60</a></span> uint32_t <a class="code hl_variable" href="structt__neorv32__spi.html#aa4d96f72e57fb6930ab43de6fb0a85ae">uint32Total</a>; </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="structt__neorv32__spi.html#aa89b7a769e54e331798e4d68d02a7b43"> 61</a></span> <span class="keyword">volatile</span> uint32_t <a class="code hl_variable" href="structt__neorv32__spi.html#aa89b7a769e54e331798e4d68d02a7b43">uint32Write</a>; </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="structt__neorv32__spi.html#a5750a54f8312ec2fed349eb9fbeff323"> 62</a></span> <span class="keyword">volatile</span> uint32_t <a class="code hl_variable" href="structt__neorv32__spi.html#a5750a54f8312ec2fed349eb9fbeff323">uint32Read</a>; </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="structt__neorv32__spi.html#a8ed31f9393bee5b963e08582b6c517ed"> 63</a></span> <span class="keyword">volatile</span> uint8_t <a class="code hl_variable" href="structt__neorv32__spi.html#a8ed31f9393bee5b963e08582b6c517ed">uint8IsBusy</a>; </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span>} <a class="code hl_struct" href="structt__neorv32__spi.html">t_neorv32_spi</a>;</div> +</div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span> </div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span> </div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="comment">// prototypes</span></div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi__irq_8h.html#a4aa4746fd210ecc0c3614089a6951ddf">neorv32_spi_init</a>(<a class="code hl_struct" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self);</div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__spi__irq_8h.html#aa641816bb302df497664aa21ea69ed16">neorv32_spi_isr</a>(<a class="code hl_struct" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self);</div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__spi__irq_8h.html#a1f44ed849415d8e1d659c0485762c485">neorv32_spi_rw</a>(<a class="code hl_struct" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self, uint8_t csn, <span class="keywordtype">void</span> *spi, uint32_t len);</div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__spi__irq_8h.html#a1863e19932bc6a79f2ca27d23eb74ef5">neorv32_spi_rw_busy</a>(<a class="code hl_struct" href="structt__neorv32__spi.html">t_neorv32_spi</a> *self);</div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span> </div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_spi_irq_h</span></div> +<div class="ttc" id="aneorv32__spi__irq_8h_html_a1863e19932bc6a79f2ca27d23eb74ef5"><div class="ttname"><a href="neorv32__spi__irq_8h.html#a1863e19932bc6a79f2ca27d23eb74ef5">neorv32_spi_rw_busy</a></div><div class="ttdeci">int neorv32_spi_rw_busy(t_neorv32_spi *self)</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.c:139</div></div> +<div class="ttc" id="aneorv32__spi__irq_8h_html_a1f44ed849415d8e1d659c0485762c485"><div class="ttname"><a href="neorv32__spi__irq_8h.html#a1f44ed849415d8e1d659c0485762c485">neorv32_spi_rw</a></div><div class="ttdeci">int neorv32_spi_rw(t_neorv32_spi *self, uint8_t csn, void *spi, uint32_t len)</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.c:109</div></div> +<div class="ttc" id="aneorv32__spi__irq_8h_html_a4aa4746fd210ecc0c3614089a6951ddf"><div class="ttname"><a href="neorv32__spi__irq_8h.html#a4aa4746fd210ecc0c3614089a6951ddf">neorv32_spi_init</a></div><div class="ttdeci">void neorv32_spi_init(t_neorv32_spi *self)</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.c:53</div></div> +<div class="ttc" id="aneorv32__spi__irq_8h_html_aa641816bb302df497664aa21ea69ed16"><div class="ttname"><a href="neorv32__spi__irq_8h.html#aa641816bb302df497664aa21ea69ed16">neorv32_spi_isr</a></div><div class="ttdeci">void neorv32_spi_isr(t_neorv32_spi *self)</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.c:69</div></div> +<div class="ttc" id="astructt__neorv32__spi_html"><div class="ttname"><a href="structt__neorv32__spi.html">t_neorv32_spi</a></div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.h:56</div></div> +<div class="ttc" id="astructt__neorv32__spi_html_a435c266758a440d32de4344472e3514a"><div class="ttname"><a href="structt__neorv32__spi.html#a435c266758a440d32de4344472e3514a">t_neorv32_spi::uint8Csn</a></div><div class="ttdeci">uint8_t uint8Csn</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.h:58</div></div> +<div class="ttc" id="astructt__neorv32__spi_html_a487a6510820871ff8d0da7699463f6d9"><div class="ttname"><a href="structt__neorv32__spi.html#a487a6510820871ff8d0da7699463f6d9">t_neorv32_spi::ptrSpiBuf</a></div><div class="ttdeci">uint8_t * ptrSpiBuf</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.h:57</div></div> +<div class="ttc" id="astructt__neorv32__spi_html_a5750a54f8312ec2fed349eb9fbeff323"><div class="ttname"><a href="structt__neorv32__spi.html#a5750a54f8312ec2fed349eb9fbeff323">t_neorv32_spi::uint32Read</a></div><div class="ttdeci">volatile uint32_t uint32Read</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.h:62</div></div> +<div class="ttc" id="astructt__neorv32__spi_html_a71fb3f91af197e1abdbe97d62130ad0f"><div class="ttname"><a href="structt__neorv32__spi.html#a71fb3f91af197e1abdbe97d62130ad0f">t_neorv32_spi::uint16Fifo</a></div><div class="ttdeci">uint16_t uint16Fifo</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.h:59</div></div> +<div class="ttc" id="astructt__neorv32__spi_html_a8ed31f9393bee5b963e08582b6c517ed"><div class="ttname"><a href="structt__neorv32__spi.html#a8ed31f9393bee5b963e08582b6c517ed">t_neorv32_spi::uint8IsBusy</a></div><div class="ttdeci">volatile uint8_t uint8IsBusy</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.h:63</div></div> +<div class="ttc" id="astructt__neorv32__spi_html_aa4d96f72e57fb6930ab43de6fb0a85ae"><div class="ttname"><a href="structt__neorv32__spi.html#aa4d96f72e57fb6930ab43de6fb0a85ae">t_neorv32_spi::uint32Total</a></div><div class="ttdeci">uint32_t uint32Total</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.h:60</div></div> +<div class="ttc" id="astructt__neorv32__spi_html_aa89b7a769e54e331798e4d68d02a7b43"><div class="ttname"><a href="structt__neorv32__spi.html#aa89b7a769e54e331798e4d68d02a7b43">t_neorv32_spi::uint32Write</a></div><div class="ttdeci">volatile uint32_t uint32Write</div><div class="ttdef"><b>Definition</b> neorv32_spi_irq.h:61</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" 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valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a098105f8a133087f286c7010c5dec8dd">neorv32_sysinfo_get_clk</a> (void)</td></tr> +<tr class="separator:a098105f8a133087f286c7010c5dec8dd"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9b1ca94e298533641547ee448e1c52b3" id="r_a9b1ca94e298533641547ee448e1c52b3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9b1ca94e298533641547ee448e1c52b3">neorv32_sysinfo_set_clk</a> (uint32_t clock)</td></tr> +<tr class="separator:a9b1ca94e298533641547ee448e1c52b3"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>System Information Memory (SYSINFO) HW driver source file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a098105f8a133087f286c7010c5dec8dd" name="a098105f8a133087f286c7010c5dec8dd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a098105f8a133087f286c7010c5dec8dd">&#9670;&#160;</a></span>neorv32_sysinfo_get_clk()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_sysinfo_get_clk </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get current processor clock frequency.</p> +<dl class="section return"><dt>Returns</dt><dd>Clock frequency in Hz. </dd></dl> + +</div> +</div> +<a id="a9b1ca94e298533641547ee448e1c52b3" name="a9b1ca94e298533641547ee448e1c52b3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9b1ca94e298533641547ee448e1c52b3">&#9670;&#160;</a></span>neorv32_sysinfo_set_clk()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_sysinfo_set_clk </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>clock</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set processor clock frequency.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">clock</td><td>Clock frequency in Hz. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 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href="structneorv32__sysinfo__t.html">neorv32_sysinfo_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:a098105f8a133087f286c7010c5dec8dd" id="r_a098105f8a133087f286c7010c5dec8dd"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a098105f8a133087f286c7010c5dec8dd">neorv32_sysinfo_get_clk</a> (void)</td></tr> +<tr class="separator:a098105f8a133087f286c7010c5dec8dd"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9b1ca94e298533641547ee448e1c52b3" id="r_a9b1ca94e298533641547ee448e1c52b3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9b1ca94e298533641547ee448e1c52b3">neorv32_sysinfo_set_clk</a> (uint32_t clock)</td></tr> +<tr class="separator:a9b1ca94e298533641547ee448e1c52b3"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: System Configuration Information Memory (SYSINFO)</h2></td></tr> +<tr class="memitem:a140e23434ef7e85b2b38d8ae9695227b" id="r_a140e23434ef7e85b2b38d8ae9695227b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a140e23434ef7e85b2b38d8ae9695227b">NEORV32_SYSINFO</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__sysinfo__t.html">neorv32_sysinfo_t</a>*) (<a class="el" href="neorv32_8h.html#a5aa936f38782232c7ed3eab1283ee536">NEORV32_SYSINFO_BASE</a>))</td></tr> +<tr class="separator:a140e23434ef7e85b2b38d8ae9695227b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aebaa5f3f231003a05c899cc1491b8c5f" id="r_aebaa5f3f231003a05c899cc1491b8c5f"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aebaa5f3f231003a05c899cc1491b8c5f">NEORV32_SYSINFO_MEM_enum</a> { <a class="el" href="#aebaa5f3f231003a05c899cc1491b8c5fa807d9e70e78e2ba3d5bfb902cc1cdc53">SYSINFO_MEM_IMEM</a> = 0 +, <a class="el" href="#aebaa5f3f231003a05c899cc1491b8c5fa8a46c064e5a1339978a5fb1f41301894">SYSINFO_MEM_DMEM</a> = 1 + }</td></tr> +<tr class="separator:aebaa5f3f231003a05c899cc1491b8c5f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae41ebd5785b09640a00df194b1a0fa08" id="r_ae41ebd5785b09640a00df194b1a0fa08"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08">NEORV32_SYSINFO_SOC_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a6899a935ae8c4aef08d828f250342e9a">SYSINFO_SOC_BOOTLOADER</a> = 0 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08add6721803c9d79f1e50248927ba30e16">SYSINFO_SOC_XBUS</a> = 1 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a1c2fbb0cc03a1df2e5e8a472f3f1ca57">SYSINFO_SOC_MEM_INT_IMEM</a> = 2 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a58ff6e112c09f798be014fdf84385135">SYSINFO_SOC_MEM_INT_DMEM</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a3e50b1c24eec0f1811d5630e6dd33e93">SYSINFO_SOC_OCD</a> = 4 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a124c4c2b101008b0e3f1d82efec11c26">SYSINFO_SOC_ICACHE</a> = 5 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a9823c2c0945997ed0d7e5eb473d81e41">SYSINFO_SOC_DCACHE</a> = 6 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a3d50c94d151d39d8229109e8b12812bf">SYSINFO_SOC_CLOCK_GATING</a> = 7 +, <br /> +&#160;&#160;<a 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+&#160;&#160;<a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a179401244ac42bc4aac3108ca9bbb9c3">SYSINFO_SOC_IO_TWI</a> = 19 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a8dc202143c3b13850bccf16380466399">SYSINFO_SOC_IO_PWM</a> = 20 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08afc964f39427cbc4090a960967eada7be">SYSINFO_SOC_IO_WDT</a> = 21 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08ae725c2452eeb33e3230dcfb3450598e6">SYSINFO_SOC_IO_CFS</a> = 22 +, <br /> +&#160;&#160;<a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a44892276837b2b1bbe6ef9faa715ad5d">SYSINFO_SOC_IO_TRNG</a> = 23 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a84088f6664a3dc19041dfad5b551ced9">SYSINFO_SOC_IO_SDI</a> = 24 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a52b0ca1ef2af5e9c9a0250440b2de9e5">SYSINFO_SOC_IO_UART1</a> = 25 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a164c5c9dc702b4b5fc71110fc047c7f1">SYSINFO_SOC_IO_NEOLED</a> = 26 +, <br /> +&#160;&#160;<a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08ad1b8d38e3715485242756cd37b7c1fe9">SYSINFO_SOC_IO_XIRQ</a> = 27 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a4aea6c006f9c999720b1dd6166a01afe">SYSINFO_SOC_IO_GPTMR</a> = 28 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08a26b25f1b47f62e98ff0920544f56b57e">SYSINFO_SOC_IO_SLINK</a> = 29 +, <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08aa8ec3b39b36f13ee4f97a72700e881a8">SYSINFO_SOC_IO_ONEWIRE</a> = 30 +, <br /> +&#160;&#160;<a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08ab89821e2c61ccb9db6324ee503f9dfa6">SYSINFO_SOC_IO_CRC</a> = 31 +<br /> + }</td></tr> +<tr class="separator:ae41ebd5785b09640a00df194b1a0fa08"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a50ee5bda9789b5cffae281db5d10a1ea" id="r_a50ee5bda9789b5cffae281db5d10a1ea"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a50ee5bda9789b5cffae281db5d10a1ea">NEORV32_SYSINFO_CACHE_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa1bdccae04b3bd84988297c16ffbefaf2">SYSINFO_CACHE_INST_BLOCK_SIZE_0</a> = 0 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaaf4a91f729e16adc72c2419d9ad3807e5">SYSINFO_CACHE_INST_BLOCK_SIZE_3</a> = 3 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaabd13283ebd48dee48aee2cff3a560fe9">SYSINFO_CACHE_INST_NUM_BLOCKS_0</a> = 4 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa02f235d7d2fc30c4ae3a383a631d9060">SYSINFO_CACHE_INST_NUM_BLOCKS_3</a> = 7 +, <br /> +&#160;&#160;<a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa8a2c7079b44f4255196de49d6d59afdb">SYSINFO_CACHE_DATA_BLOCK_SIZE_0</a> = 8 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaaaec544d85ce3296ca9e97e833e20936e">SYSINFO_CACHE_DATA_BLOCK_SIZE_3</a> = 11 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaabb743d3ca41bf44aa6ff188ec898cfb8">SYSINFO_CACHE_DATA_NUM_BLOCKS_0</a> = 12 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa5778928b290b3b1cba42412de4dabf96">SYSINFO_CACHE_DATA_NUM_BLOCKS_3</a> = 15 +, <br /> +&#160;&#160;<a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaaea0a88adaa9d0b5e1f4e5cca630ed6f8">SYSINFO_CACHE_XIP_BLOCK_SIZE_0</a> = 16 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa44d4d12c0395e924b8bf7dc40059bfba">SYSINFO_CACHE_XIP_BLOCK_SIZE_3</a> = 19 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa90ae265a72ea53d99b474798e721c317">SYSINFO_CACHE_XIP_NUM_BLOCKS_0</a> = 20 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaaf88eacb3ed63d5a048a554927812460b">SYSINFO_CACHE_XIP_NUM_BLOCKS_3</a> = 23 +, <br /> +&#160;&#160;<a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa3f6e68cdf6bb641902a9a6d32c1f9d9e">SYSINFO_CACHE_XBUS_BLOCK_SIZE_0</a> = 24 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa908c60a836b03129098cb70fe2a860a1">SYSINFO_CACHE_XBUS_BLOCK_SIZE_3</a> = 27 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaa73553a14d3425498be9d3802ca5f1459">SYSINFO_CACHE_XBUS_NUM_BLOCKS_0</a> = 28 +, <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1eaade7f119164ff2c3800b4464a65ca247b">SYSINFO_CACHE_XBUS_NUM_BLOCKS_3</a> = 31 +<br /> + }</td></tr> +<tr class="separator:a50ee5bda9789b5cffae281db5d10a1ea"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>System Information Memory (SYSINFO) HW driver header file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a140e23434ef7e85b2b38d8ae9695227b" name="a140e23434ef7e85b2b38d8ae9695227b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a140e23434ef7e85b2b38d8ae9695227b">&#9670;&#160;</a></span>NEORV32_SYSINFO</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_SYSINFO&#160;&#160;&#160;((<a class="el" href="structneorv32__sysinfo__t.html">neorv32_sysinfo_t</a>*) (<a class="el" href="neorv32_8h.html#a5aa936f38782232c7ed3eab1283ee536">NEORV32_SYSINFO_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>SYSINFO module hardware access (<a class="el" href="structneorv32__sysinfo__t.html">neorv32_sysinfo_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a50ee5bda9789b5cffae281db5d10a1ea" name="a50ee5bda9789b5cffae281db5d10a1ea"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a50ee5bda9789b5cffae281db5d10a1ea">&#9670;&#160;</a></span>NEORV32_SYSINFO_CACHE_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a50ee5bda9789b5cffae281db5d10a1ea">NEORV32_SYSINFO_CACHE_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32_SYSINFO.CACHE (r/-): Cache configuration </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa1bdccae04b3bd84988297c16ffbefaf2" name="a50ee5bda9789b5cffae281db5d10a1eaa1bdccae04b3bd84988297c16ffbefaf2"></a>SYSINFO_CACHE_INST_BLOCK_SIZE_0&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaaf4a91f729e16adc72c2419d9ad3807e5" name="a50ee5bda9789b5cffae281db5d10a1eaaf4a91f729e16adc72c2419d9ad3807e5"></a>SYSINFO_CACHE_INST_BLOCK_SIZE_3&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (3) (r/-): i-cache: log2(Block size in bytes), bit 3 (via ICACHE_BLOCK_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaabd13283ebd48dee48aee2cff3a560fe9" name="a50ee5bda9789b5cffae281db5d10a1eaabd13283ebd48dee48aee2cff3a560fe9"></a>SYSINFO_CACHE_INST_NUM_BLOCKS_0&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (4) (r/-): i-cache: log2(Number of cache blocks), bit 0 (via ICACHE_NUM_BLOCKS generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa02f235d7d2fc30c4ae3a383a631d9060" name="a50ee5bda9789b5cffae281db5d10a1eaa02f235d7d2fc30c4ae3a383a631d9060"></a>SYSINFO_CACHE_INST_NUM_BLOCKS_3&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (7) (r/-): i-cache: log2(Number of cache blocks), bit 3 (via ICACHE_NUM_BLOCKS generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa8a2c7079b44f4255196de49d6d59afdb" name="a50ee5bda9789b5cffae281db5d10a1eaa8a2c7079b44f4255196de49d6d59afdb"></a>SYSINFO_CACHE_DATA_BLOCK_SIZE_0&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (8) (r/-): d-cache: log2(Block size in bytes), bit 0 (via DCACHE_BLOCK_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaaaec544d85ce3296ca9e97e833e20936e" name="a50ee5bda9789b5cffae281db5d10a1eaaaec544d85ce3296ca9e97e833e20936e"></a>SYSINFO_CACHE_DATA_BLOCK_SIZE_3&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (11) (r/-): d-cache: log2(Block size in bytes), bit 3 (via DCACHE_BLOCK_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaabb743d3ca41bf44aa6ff188ec898cfb8" name="a50ee5bda9789b5cffae281db5d10a1eaabb743d3ca41bf44aa6ff188ec898cfb8"></a>SYSINFO_CACHE_DATA_NUM_BLOCKS_0&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (12) (r/-): d-cache: log2(Number of cache blocks), bit 0 (via DCACHE_NUM_BLOCKS generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa5778928b290b3b1cba42412de4dabf96" name="a50ee5bda9789b5cffae281db5d10a1eaa5778928b290b3b1cba42412de4dabf96"></a>SYSINFO_CACHE_DATA_NUM_BLOCKS_3&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (15) (r/-): d-cache: log2(Number of cache blocks), bit 3 (via DCACHE_NUM_BLOCKS generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaaea0a88adaa9d0b5e1f4e5cca630ed6f8" name="a50ee5bda9789b5cffae281db5d10a1eaaea0a88adaa9d0b5e1f4e5cca630ed6f8"></a>SYSINFO_CACHE_XIP_BLOCK_SIZE_0&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (16) (r/-): xip-cache: log2(Block size in bytes), bit 0 (via XIP_CACHE_BLOCK_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa44d4d12c0395e924b8bf7dc40059bfba" name="a50ee5bda9789b5cffae281db5d10a1eaa44d4d12c0395e924b8bf7dc40059bfba"></a>SYSINFO_CACHE_XIP_BLOCK_SIZE_3&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (19) (r/-): xip-cache: log2(Block size in bytes), bit 3 (via XIP_CACHE_BLOCK_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa90ae265a72ea53d99b474798e721c317" name="a50ee5bda9789b5cffae281db5d10a1eaa90ae265a72ea53d99b474798e721c317"></a>SYSINFO_CACHE_XIP_NUM_BLOCKS_0&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (20) (r/-): xip-cache: log2(Number of cache blocks), bit 0 (via XIP_CACHE_NUM_BLOCKS generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaaf88eacb3ed63d5a048a554927812460b" name="a50ee5bda9789b5cffae281db5d10a1eaaf88eacb3ed63d5a048a554927812460b"></a>SYSINFO_CACHE_XIP_NUM_BLOCKS_3&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (23) (r/-): xip-cache: log2(Number of cache blocks), bit 3 (via XIP_CACHE_NUM_BLOCKS generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa3f6e68cdf6bb641902a9a6d32c1f9d9e" name="a50ee5bda9789b5cffae281db5d10a1eaa3f6e68cdf6bb641902a9a6d32c1f9d9e"></a>SYSINFO_CACHE_XBUS_BLOCK_SIZE_0&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (24) (r/-): xbus-cache: log2(Block size in bytes), bit 0 (via XBUS_CACHE_BLOCK_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa908c60a836b03129098cb70fe2a860a1" name="a50ee5bda9789b5cffae281db5d10a1eaa908c60a836b03129098cb70fe2a860a1"></a>SYSINFO_CACHE_XBUS_BLOCK_SIZE_3&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (27) (r/-): xbus-cache: log2(Block size in bytes), bit 3 (via XBUS_CACHE_BLOCK_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaa73553a14d3425498be9d3802ca5f1459" name="a50ee5bda9789b5cffae281db5d10a1eaa73553a14d3425498be9d3802ca5f1459"></a>SYSINFO_CACHE_XBUS_NUM_BLOCKS_0&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (28) (r/-): xbus-cache: log2(Number of cache blocks), bit 0 (via XBUS_CACHE_NUM_BLOCKS generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="a50ee5bda9789b5cffae281db5d10a1eaade7f119164ff2c3800b4464a65ca247b" name="a50ee5bda9789b5cffae281db5d10a1eaade7f119164ff2c3800b4464a65ca247b"></a>SYSINFO_CACHE_XBUS_NUM_BLOCKS_3&#160;</td><td class="fielddoc"><p>SYSINFO_CACHE (31) (r/-): xbus-cache: log2(Number of cache blocks), bit 3 (via XBUS_CACHE_NUM_BLOCKS generic) </p> +</td></tr> +</table> + +</div> +</div> +<a id="aebaa5f3f231003a05c899cc1491b8c5f" name="aebaa5f3f231003a05c899cc1491b8c5f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aebaa5f3f231003a05c899cc1491b8c5f">&#9670;&#160;</a></span>NEORV32_SYSINFO_MEM_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#aebaa5f3f231003a05c899cc1491b8c5f">NEORV32_SYSINFO_MEM_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32_SYSINFO.MEM (r/-): Memory configuration (sizes) </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="aebaa5f3f231003a05c899cc1491b8c5fa807d9e70e78e2ba3d5bfb902cc1cdc53" name="aebaa5f3f231003a05c899cc1491b8c5fa807d9e70e78e2ba3d5bfb902cc1cdc53"></a>SYSINFO_MEM_IMEM&#160;</td><td class="fielddoc"><p>SYSINFO_MEM byte 0 (r/-): log2(internal IMEM size in bytes) (via MEM_INT_IMEM_SIZE generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="aebaa5f3f231003a05c899cc1491b8c5fa8a46c064e5a1339978a5fb1f41301894" name="aebaa5f3f231003a05c899cc1491b8c5fa8a46c064e5a1339978a5fb1f41301894"></a>SYSINFO_MEM_DMEM&#160;</td><td class="fielddoc"><p>SYSINFO_MEM byte 1 (r/-): log2(internal DMEM size in bytes) (via MEM_INT_DMEM_SIZE generic) </p> +</td></tr> +</table> + +</div> +</div> +<a id="ae41ebd5785b09640a00df194b1a0fa08" name="ae41ebd5785b09640a00df194b1a0fa08"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae41ebd5785b09640a00df194b1a0fa08">&#9670;&#160;</a></span>NEORV32_SYSINFO_SOC_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ae41ebd5785b09640a00df194b1a0fa08">NEORV32_SYSINFO_SOC_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a6899a935ae8c4aef08d828f250342e9a" name="ae41ebd5785b09640a00df194b1a0fa08a6899a935ae8c4aef08d828f250342e9a"></a>SYSINFO_SOC_BOOTLOADER&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08add6721803c9d79f1e50248927ba30e16" name="ae41ebd5785b09640a00df194b1a0fa08add6721803c9d79f1e50248927ba30e16"></a>SYSINFO_SOC_XBUS&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (1) (r/-): External bus interface implemented when 1 (via XBUS_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a1c2fbb0cc03a1df2e5e8a472f3f1ca57" name="ae41ebd5785b09640a00df194b1a0fa08a1c2fbb0cc03a1df2e5e8a472f3f1ca57"></a>SYSINFO_SOC_MEM_INT_IMEM&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a58ff6e112c09f798be014fdf84385135" name="ae41ebd5785b09640a00df194b1a0fa08a58ff6e112c09f798be014fdf84385135"></a>SYSINFO_SOC_MEM_INT_DMEM&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a3e50b1c24eec0f1811d5630e6dd33e93" name="ae41ebd5785b09640a00df194b1a0fa08a3e50b1c24eec0f1811d5630e6dd33e93"></a>SYSINFO_SOC_OCD&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (4) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a124c4c2b101008b0e3f1d82efec11c26" name="ae41ebd5785b09640a00df194b1a0fa08a124c4c2b101008b0e3f1d82efec11c26"></a>SYSINFO_SOC_ICACHE&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a9823c2c0945997ed0d7e5eb473d81e41" name="ae41ebd5785b09640a00df194b1a0fa08a9823c2c0945997ed0d7e5eb473d81e41"></a>SYSINFO_SOC_DCACHE&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (6) (r/-): Processor-internal instruction cache implemented when 1 (via DCACHE_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a3d50c94d151d39d8229109e8b12812bf" name="ae41ebd5785b09640a00df194b1a0fa08a3d50c94d151d39d8229109e8b12812bf"></a>SYSINFO_SOC_CLOCK_GATING&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (7) (r/-): Clock gating implemented when 1 (via CLOCK_GATING_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a579f26ab04d4fd9af8e419df465695ca" name="ae41ebd5785b09640a00df194b1a0fa08a579f26ab04d4fd9af8e419df465695ca"></a>SYSINFO_SOC_XBUS_CACHE&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (8) (r/-): External bus cache implemented when 1 (via XBUS_CACHE_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a516a2e254ae63e017caefbeed20f54e9" name="ae41ebd5785b09640a00df194b1a0fa08a516a2e254ae63e017caefbeed20f54e9"></a>SYSINFO_SOC_XIP&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (9) (r/-): Execute in-place module implemented when 1 (via XIP_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08ac943fc33a2c1c25c3ab075228b87c0ef" name="ae41ebd5785b09640a00df194b1a0fa08ac943fc33a2c1c25c3ab075228b87c0ef"></a>SYSINFO_SOC_XIP_CACHE&#160;</td><td class="fielddoc"><p>SYSINFO_S C (10) (r/-): Execute in-place cache implemented when 1 (via XIP_CACHE_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a24658727efef9747414b5da8f26de66d" name="ae41ebd5785b09640a00df194b1a0fa08a24658727efef9747414b5da8f26de66d"></a>SYSINFO_SOC_IO_DMA&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (14) (r/-): Direct memory access controller implemented when 1 (via IO_DMA_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a62a2337b33a2f65b6efd5c91e699c2d1" name="ae41ebd5785b09640a00df194b1a0fa08a62a2337b33a2f65b6efd5c91e699c2d1"></a>SYSINFO_SOC_IO_GPIO&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (15) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a5458b7ad729818c2f42e20c61fcffe2d" name="ae41ebd5785b09640a00df194b1a0fa08a5458b7ad729818c2f42e20c61fcffe2d"></a>SYSINFO_SOC_IO_MTIME&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (16) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a244710794e00c93e91a7f13d533cb139" name="ae41ebd5785b09640a00df194b1a0fa08a244710794e00c93e91a7f13d533cb139"></a>SYSINFO_SOC_IO_UART0&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (17) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a4cf4b1a83a4b52efbf26eace21f5ab20" name="ae41ebd5785b09640a00df194b1a0fa08a4cf4b1a83a4b52efbf26eace21f5ab20"></a>SYSINFO_SOC_IO_SPI&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (18) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a179401244ac42bc4aac3108ca9bbb9c3" name="ae41ebd5785b09640a00df194b1a0fa08a179401244ac42bc4aac3108ca9bbb9c3"></a>SYSINFO_SOC_IO_TWI&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (19) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a8dc202143c3b13850bccf16380466399" name="ae41ebd5785b09640a00df194b1a0fa08a8dc202143c3b13850bccf16380466399"></a>SYSINFO_SOC_IO_PWM&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (20) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08afc964f39427cbc4090a960967eada7be" name="ae41ebd5785b09640a00df194b1a0fa08afc964f39427cbc4090a960967eada7be"></a>SYSINFO_SOC_IO_WDT&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (21) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08ae725c2452eeb33e3230dcfb3450598e6" name="ae41ebd5785b09640a00df194b1a0fa08ae725c2452eeb33e3230dcfb3450598e6"></a>SYSINFO_SOC_IO_CFS&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (22) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a44892276837b2b1bbe6ef9faa715ad5d" name="ae41ebd5785b09640a00df194b1a0fa08a44892276837b2b1bbe6ef9faa715ad5d"></a>SYSINFO_SOC_IO_TRNG&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (23) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a84088f6664a3dc19041dfad5b551ced9" name="ae41ebd5785b09640a00df194b1a0fa08a84088f6664a3dc19041dfad5b551ced9"></a>SYSINFO_SOC_IO_SDI&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (24) (r/-): Serial data interface implemented when 1 (via IO_SDI_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a52b0ca1ef2af5e9c9a0250440b2de9e5" name="ae41ebd5785b09640a00df194b1a0fa08a52b0ca1ef2af5e9c9a0250440b2de9e5"></a>SYSINFO_SOC_IO_UART1&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (25) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a164c5c9dc702b4b5fc71110fc047c7f1" name="ae41ebd5785b09640a00df194b1a0fa08a164c5c9dc702b4b5fc71110fc047c7f1"></a>SYSINFO_SOC_IO_NEOLED&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (26) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08ad1b8d38e3715485242756cd37b7c1fe9" name="ae41ebd5785b09640a00df194b1a0fa08ad1b8d38e3715485242756cd37b7c1fe9"></a>SYSINFO_SOC_IO_XIRQ&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (27) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a4aea6c006f9c999720b1dd6166a01afe" name="ae41ebd5785b09640a00df194b1a0fa08a4aea6c006f9c999720b1dd6166a01afe"></a>SYSINFO_SOC_IO_GPTMR&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (28) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08a26b25f1b47f62e98ff0920544f56b57e" name="ae41ebd5785b09640a00df194b1a0fa08a26b25f1b47f62e98ff0920544f56b57e"></a>SYSINFO_SOC_IO_SLINK&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (29) (r/-): Stream link interface implemented when 1 (via IO_SLINK_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08aa8ec3b39b36f13ee4f97a72700e881a8" name="ae41ebd5785b09640a00df194b1a0fa08aa8ec3b39b36f13ee4f97a72700e881a8"></a>SYSINFO_SOC_IO_ONEWIRE&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (30) (r/-): 1-wire interface controller implemented when 1 (via IO_ONEWIRE_EN generic) </p> +</td></tr> +<tr><td class="fieldname"><a id="ae41ebd5785b09640a00df194b1a0fa08ab89821e2c61ccb9db6324ee503f9dfa6" name="ae41ebd5785b09640a00df194b1a0fa08ab89821e2c61ccb9db6324ee503f9dfa6"></a>SYSINFO_SOC_IO_CRC&#160;</td><td class="fielddoc"><p>SYSINFO_SOC (31) (r/-): Cyclic redundancy check unit implemented when 1 (via IO_CRC_EN generic) </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a098105f8a133087f286c7010c5dec8dd" name="a098105f8a133087f286c7010c5dec8dd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a098105f8a133087f286c7010c5dec8dd">&#9670;&#160;</a></span>neorv32_sysinfo_get_clk()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_sysinfo_get_clk </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get current processor clock frequency.</p> +<dl class="section return"><dt>Returns</dt><dd>Clock frequency in Hz. </dd></dl> + +</div> +</div> +<a id="a9b1ca94e298533641547ee448e1c52b3" name="a9b1ca94e298533641547ee448e1c52b3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9b1ca94e298533641547ee448e1c52b3">&#9670;&#160;</a></span>neorv32_sysinfo_set_clk()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_sysinfo_set_clk </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>clock</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set processor clock frequency.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">clock</td><td>Clock frequency in Hz. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__sysinfo_8h_source.html b/sw/neorv32__sysinfo_8h_source.html new file mode 100644 index 000000000..dd58a5459 --- /dev/null +++ b/sw/neorv32__sysinfo_8h_source.html @@ -0,0 +1,250 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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href="neorv32__sysinfo_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_sysinfo_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_sysinfo_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00027" data-start="{" data-end="};"> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"><a class="line" href="structneorv32__sysinfo__t.html"> 27</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"><a class="line" href="structneorv32__sysinfo__t.html#a3f8ce96050fc0a680afa9b7fdf7cb35c"> 28</a></span> uint32_t <a class="code hl_variable" href="structneorv32__sysinfo__t.html#a3f8ce96050fc0a680afa9b7fdf7cb35c">CLK</a>; </div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__sysinfo__t.html#a51eee92b1824c1b19eb0a83a0a9c7d4c"> 29</a></span> <span class="keyword">const</span> uint8_t MEM[4]; </div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__sysinfo__t.html#ac43abe3b416da3a2895d1d06537a14c3"> 30</a></span> <span class="keyword">const</span> uint32_t <a class="code hl_variable" href="structneorv32__sysinfo__t.html#ac43abe3b416da3a2895d1d06537a14c3">SOC</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__sysinfo__t.html#ada99a36ccda38b254d5b6a84883101f6"> 31</a></span> <span class="keyword">const</span> uint32_t <a class="code hl_variable" href="structneorv32__sysinfo__t.html#ada99a36ccda38b254d5b6a84883101f6">CACHE</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__sysinfo__t.html">neorv32_sysinfo_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a140e23434ef7e85b2b38d8ae9695227b"> 35</a></span><span class="preprocessor">#define NEORV32_SYSINFO ((neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE))</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="foldopen" id="foldopen00038" data-start="{" data-end="};"> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5f"> 38</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5f">NEORV32_SYSINFO_MEM_enum</a> {</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5fa807d9e70e78e2ba3d5bfb902cc1cdc53"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5fa807d9e70e78e2ba3d5bfb902cc1cdc53">SYSINFO_MEM_IMEM</a> = 0, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5fa8a46c064e5a1339978a5fb1f41301894">SYSINFO_MEM_DMEM</a> = 1 </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5fa8a46c064e5a1339978a5fb1f41301894"> 41</a></span>};</div> +</div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> </div> +<div class="foldopen" id="foldopen00044" data-start="{" data-end="};"> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08"> 44</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08">NEORV32_SYSINFO_SOC_enum</a> {</div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a6899a935ae8c4aef08d828f250342e9a"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a6899a935ae8c4aef08d828f250342e9a">SYSINFO_SOC_BOOTLOADER</a> = 0, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08add6721803c9d79f1e50248927ba30e16"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08add6721803c9d79f1e50248927ba30e16">SYSINFO_SOC_XBUS</a> = 1, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a1c2fbb0cc03a1df2e5e8a472f3f1ca57"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a1c2fbb0cc03a1df2e5e8a472f3f1ca57">SYSINFO_SOC_MEM_INT_IMEM</a> = 2, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a58ff6e112c09f798be014fdf84385135"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a58ff6e112c09f798be014fdf84385135">SYSINFO_SOC_MEM_INT_DMEM</a> = 3, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a3e50b1c24eec0f1811d5630e6dd33e93"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a3e50b1c24eec0f1811d5630e6dd33e93">SYSINFO_SOC_OCD</a> = 4, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a124c4c2b101008b0e3f1d82efec11c26"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a124c4c2b101008b0e3f1d82efec11c26">SYSINFO_SOC_ICACHE</a> = 5, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a9823c2c0945997ed0d7e5eb473d81e41"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a9823c2c0945997ed0d7e5eb473d81e41">SYSINFO_SOC_DCACHE</a> = 6, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a3d50c94d151d39d8229109e8b12812bf"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a3d50c94d151d39d8229109e8b12812bf">SYSINFO_SOC_CLOCK_GATING</a> = 7, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a579f26ab04d4fd9af8e419df465695ca"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a579f26ab04d4fd9af8e419df465695ca">SYSINFO_SOC_XBUS_CACHE</a> = 8, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a516a2e254ae63e017caefbeed20f54e9"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a516a2e254ae63e017caefbeed20f54e9">SYSINFO_SOC_XIP</a> = 9, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ac943fc33a2c1c25c3ab075228b87c0ef"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ac943fc33a2c1c25c3ab075228b87c0ef">SYSINFO_SOC_XIP_CACHE</a> = 10, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a24658727efef9747414b5da8f26de66d"> 57</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a24658727efef9747414b5da8f26de66d">SYSINFO_SOC_IO_DMA</a> = 14, </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a62a2337b33a2f65b6efd5c91e699c2d1"> 58</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a62a2337b33a2f65b6efd5c91e699c2d1">SYSINFO_SOC_IO_GPIO</a> = 15, </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a5458b7ad729818c2f42e20c61fcffe2d"> 59</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a5458b7ad729818c2f42e20c61fcffe2d">SYSINFO_SOC_IO_MTIME</a> = 16, </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a244710794e00c93e91a7f13d533cb139"> 60</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a244710794e00c93e91a7f13d533cb139">SYSINFO_SOC_IO_UART0</a> = 17, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a4cf4b1a83a4b52efbf26eace21f5ab20"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a4cf4b1a83a4b52efbf26eace21f5ab20">SYSINFO_SOC_IO_SPI</a> = 18, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a179401244ac42bc4aac3108ca9bbb9c3"> 62</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a179401244ac42bc4aac3108ca9bbb9c3">SYSINFO_SOC_IO_TWI</a> = 19, </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a8dc202143c3b13850bccf16380466399"> 63</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a8dc202143c3b13850bccf16380466399">SYSINFO_SOC_IO_PWM</a> = 20, </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08afc964f39427cbc4090a960967eada7be"> 64</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08afc964f39427cbc4090a960967eada7be">SYSINFO_SOC_IO_WDT</a> = 21, </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ae725c2452eeb33e3230dcfb3450598e6"> 65</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ae725c2452eeb33e3230dcfb3450598e6">SYSINFO_SOC_IO_CFS</a> = 22, </div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a44892276837b2b1bbe6ef9faa715ad5d"> 66</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a44892276837b2b1bbe6ef9faa715ad5d">SYSINFO_SOC_IO_TRNG</a> = 23, </div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a84088f6664a3dc19041dfad5b551ced9"> 67</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a84088f6664a3dc19041dfad5b551ced9">SYSINFO_SOC_IO_SDI</a> = 24, </div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a52b0ca1ef2af5e9c9a0250440b2de9e5"> 68</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a52b0ca1ef2af5e9c9a0250440b2de9e5">SYSINFO_SOC_IO_UART1</a> = 25, </div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a164c5c9dc702b4b5fc71110fc047c7f1"> 69</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a164c5c9dc702b4b5fc71110fc047c7f1">SYSINFO_SOC_IO_NEOLED</a> = 26, </div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ad1b8d38e3715485242756cd37b7c1fe9"> 70</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ad1b8d38e3715485242756cd37b7c1fe9">SYSINFO_SOC_IO_XIRQ</a> = 27, </div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a4aea6c006f9c999720b1dd6166a01afe"> 71</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a4aea6c006f9c999720b1dd6166a01afe">SYSINFO_SOC_IO_GPTMR</a> = 28, </div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a26b25f1b47f62e98ff0920544f56b57e"> 72</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a26b25f1b47f62e98ff0920544f56b57e">SYSINFO_SOC_IO_SLINK</a> = 29, </div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08aa8ec3b39b36f13ee4f97a72700e881a8"> 73</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08aa8ec3b39b36f13ee4f97a72700e881a8">SYSINFO_SOC_IO_ONEWIRE</a> = 30, </div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ab89821e2c61ccb9db6324ee503f9dfa6">SYSINFO_SOC_IO_CRC</a> = 31 </div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ab89821e2c61ccb9db6324ee503f9dfa6"> 75</a></span>};</div> +</div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span> </div> +<div class="foldopen" id="foldopen00078" data-start="{" data-end="};"> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1ea"> 78</a></span> <span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1ea">NEORV32_SYSINFO_CACHE_enum</a> {</div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa1bdccae04b3bd84988297c16ffbefaf2"> 79</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa1bdccae04b3bd84988297c16ffbefaf2">SYSINFO_CACHE_INST_BLOCK_SIZE_0</a> = 0, </div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaf4a91f729e16adc72c2419d9ad3807e5"> 80</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaf4a91f729e16adc72c2419d9ad3807e5">SYSINFO_CACHE_INST_BLOCK_SIZE_3</a> = 3, </div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaabd13283ebd48dee48aee2cff3a560fe9"> 81</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaabd13283ebd48dee48aee2cff3a560fe9">SYSINFO_CACHE_INST_NUM_BLOCKS_0</a> = 4, </div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa02f235d7d2fc30c4ae3a383a631d9060"> 82</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa02f235d7d2fc30c4ae3a383a631d9060">SYSINFO_CACHE_INST_NUM_BLOCKS_3</a> = 7, </div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa8a2c7079b44f4255196de49d6d59afdb"> 84</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa8a2c7079b44f4255196de49d6d59afdb">SYSINFO_CACHE_DATA_BLOCK_SIZE_0</a> = 8, </div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaaec544d85ce3296ca9e97e833e20936e"> 85</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaaec544d85ce3296ca9e97e833e20936e">SYSINFO_CACHE_DATA_BLOCK_SIZE_3</a> = 11, </div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaabb743d3ca41bf44aa6ff188ec898cfb8"> 86</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaabb743d3ca41bf44aa6ff188ec898cfb8">SYSINFO_CACHE_DATA_NUM_BLOCKS_0</a> = 12, </div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa5778928b290b3b1cba42412de4dabf96"> 87</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa5778928b290b3b1cba42412de4dabf96">SYSINFO_CACHE_DATA_NUM_BLOCKS_3</a> = 15, </div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaea0a88adaa9d0b5e1f4e5cca630ed6f8"> 89</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaea0a88adaa9d0b5e1f4e5cca630ed6f8">SYSINFO_CACHE_XIP_BLOCK_SIZE_0</a> = 16, </div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa44d4d12c0395e924b8bf7dc40059bfba"> 90</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa44d4d12c0395e924b8bf7dc40059bfba">SYSINFO_CACHE_XIP_BLOCK_SIZE_3</a> = 19, </div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa90ae265a72ea53d99b474798e721c317"> 91</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa90ae265a72ea53d99b474798e721c317">SYSINFO_CACHE_XIP_NUM_BLOCKS_0</a> = 20, </div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaf88eacb3ed63d5a048a554927812460b"> 92</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaf88eacb3ed63d5a048a554927812460b">SYSINFO_CACHE_XIP_NUM_BLOCKS_3</a> = 23, </div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa3f6e68cdf6bb641902a9a6d32c1f9d9e"> 94</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa3f6e68cdf6bb641902a9a6d32c1f9d9e">SYSINFO_CACHE_XBUS_BLOCK_SIZE_0</a> = 24, </div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa908c60a836b03129098cb70fe2a860a1"> 95</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa908c60a836b03129098cb70fe2a860a1">SYSINFO_CACHE_XBUS_BLOCK_SIZE_3</a> = 27, </div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa73553a14d3425498be9d3802ca5f1459"> 96</a></span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa73553a14d3425498be9d3802ca5f1459">SYSINFO_CACHE_XBUS_NUM_BLOCKS_0</a> = 28, </div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> <a class="code hl_enumvalue" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaade7f119164ff2c3800b4464a65ca247b">SYSINFO_CACHE_XBUS_NUM_BLOCKS_3</a> = 31 </div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"><a class="line" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaade7f119164ff2c3800b4464a65ca247b"> 98</a></span>};</div> +</div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span>uint32_t <a class="code hl_function" href="neorv32__sysinfo_8h.html#a098105f8a133087f286c7010c5dec8dd">neorv32_sysinfo_get_clk</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__sysinfo_8h.html#a9b1ca94e298533641547ee448e1c52b3">neorv32_sysinfo_set_clk</a>(uint32_t clock);</div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_sysinfo_h</span></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a098105f8a133087f286c7010c5dec8dd"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a098105f8a133087f286c7010c5dec8dd">neorv32_sysinfo_get_clk</a></div><div class="ttdeci">uint32_t neorv32_sysinfo_get_clk(void)</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.c:24</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1ea"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1ea">NEORV32_SYSINFO_CACHE_enum</a></div><div class="ttdeci">NEORV32_SYSINFO_CACHE_enum</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:78</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa02f235d7d2fc30c4ae3a383a631d9060"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa02f235d7d2fc30c4ae3a383a631d9060">SYSINFO_CACHE_INST_NUM_BLOCKS_3</a></div><div class="ttdeci">@ SYSINFO_CACHE_INST_NUM_BLOCKS_3</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:82</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa1bdccae04b3bd84988297c16ffbefaf2"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa1bdccae04b3bd84988297c16ffbefaf2">SYSINFO_CACHE_INST_BLOCK_SIZE_0</a></div><div class="ttdeci">@ SYSINFO_CACHE_INST_BLOCK_SIZE_0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:79</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa3f6e68cdf6bb641902a9a6d32c1f9d9e"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa3f6e68cdf6bb641902a9a6d32c1f9d9e">SYSINFO_CACHE_XBUS_BLOCK_SIZE_0</a></div><div class="ttdeci">@ SYSINFO_CACHE_XBUS_BLOCK_SIZE_0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:94</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa44d4d12c0395e924b8bf7dc40059bfba"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa44d4d12c0395e924b8bf7dc40059bfba">SYSINFO_CACHE_XIP_BLOCK_SIZE_3</a></div><div class="ttdeci">@ SYSINFO_CACHE_XIP_BLOCK_SIZE_3</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:90</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa5778928b290b3b1cba42412de4dabf96"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa5778928b290b3b1cba42412de4dabf96">SYSINFO_CACHE_DATA_NUM_BLOCKS_3</a></div><div class="ttdeci">@ SYSINFO_CACHE_DATA_NUM_BLOCKS_3</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:87</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa73553a14d3425498be9d3802ca5f1459"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa73553a14d3425498be9d3802ca5f1459">SYSINFO_CACHE_XBUS_NUM_BLOCKS_0</a></div><div class="ttdeci">@ SYSINFO_CACHE_XBUS_NUM_BLOCKS_0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:96</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa8a2c7079b44f4255196de49d6d59afdb"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa8a2c7079b44f4255196de49d6d59afdb">SYSINFO_CACHE_DATA_BLOCK_SIZE_0</a></div><div class="ttdeci">@ SYSINFO_CACHE_DATA_BLOCK_SIZE_0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:84</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa908c60a836b03129098cb70fe2a860a1"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa908c60a836b03129098cb70fe2a860a1">SYSINFO_CACHE_XBUS_BLOCK_SIZE_3</a></div><div class="ttdeci">@ SYSINFO_CACHE_XBUS_BLOCK_SIZE_3</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:95</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaa90ae265a72ea53d99b474798e721c317"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaa90ae265a72ea53d99b474798e721c317">SYSINFO_CACHE_XIP_NUM_BLOCKS_0</a></div><div class="ttdeci">@ SYSINFO_CACHE_XIP_NUM_BLOCKS_0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:91</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaaaec544d85ce3296ca9e97e833e20936e"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaaec544d85ce3296ca9e97e833e20936e">SYSINFO_CACHE_DATA_BLOCK_SIZE_3</a></div><div class="ttdeci">@ SYSINFO_CACHE_DATA_BLOCK_SIZE_3</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:85</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaabb743d3ca41bf44aa6ff188ec898cfb8"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaabb743d3ca41bf44aa6ff188ec898cfb8">SYSINFO_CACHE_DATA_NUM_BLOCKS_0</a></div><div class="ttdeci">@ SYSINFO_CACHE_DATA_NUM_BLOCKS_0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:86</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaabd13283ebd48dee48aee2cff3a560fe9"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaabd13283ebd48dee48aee2cff3a560fe9">SYSINFO_CACHE_INST_NUM_BLOCKS_0</a></div><div class="ttdeci">@ SYSINFO_CACHE_INST_NUM_BLOCKS_0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:81</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaade7f119164ff2c3800b4464a65ca247b"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaade7f119164ff2c3800b4464a65ca247b">SYSINFO_CACHE_XBUS_NUM_BLOCKS_3</a></div><div class="ttdeci">@ SYSINFO_CACHE_XBUS_NUM_BLOCKS_3</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:97</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaaea0a88adaa9d0b5e1f4e5cca630ed6f8"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaea0a88adaa9d0b5e1f4e5cca630ed6f8">SYSINFO_CACHE_XIP_BLOCK_SIZE_0</a></div><div class="ttdeci">@ SYSINFO_CACHE_XIP_BLOCK_SIZE_0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:89</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaaf4a91f729e16adc72c2419d9ad3807e5"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaf4a91f729e16adc72c2419d9ad3807e5">SYSINFO_CACHE_INST_BLOCK_SIZE_3</a></div><div class="ttdeci">@ SYSINFO_CACHE_INST_BLOCK_SIZE_3</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:80</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a50ee5bda9789b5cffae281db5d10a1eaaf88eacb3ed63d5a048a554927812460b"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1eaaf88eacb3ed63d5a048a554927812460b">SYSINFO_CACHE_XIP_NUM_BLOCKS_3</a></div><div class="ttdeci">@ SYSINFO_CACHE_XIP_NUM_BLOCKS_3</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:92</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_a9b1ca94e298533641547ee448e1c52b3"><div class="ttname"><a href="neorv32__sysinfo_8h.html#a9b1ca94e298533641547ee448e1c52b3">neorv32_sysinfo_set_clk</a></div><div class="ttdeci">void neorv32_sysinfo_set_clk(uint32_t clock)</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.c:35</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08">NEORV32_SYSINFO_SOC_enum</a></div><div class="ttdeci">NEORV32_SYSINFO_SOC_enum</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:44</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a124c4c2b101008b0e3f1d82efec11c26"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a124c4c2b101008b0e3f1d82efec11c26">SYSINFO_SOC_ICACHE</a></div><div class="ttdeci">@ SYSINFO_SOC_ICACHE</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:50</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a164c5c9dc702b4b5fc71110fc047c7f1"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a164c5c9dc702b4b5fc71110fc047c7f1">SYSINFO_SOC_IO_NEOLED</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_NEOLED</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:69</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a179401244ac42bc4aac3108ca9bbb9c3"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a179401244ac42bc4aac3108ca9bbb9c3">SYSINFO_SOC_IO_TWI</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_TWI</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:62</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a1c2fbb0cc03a1df2e5e8a472f3f1ca57"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a1c2fbb0cc03a1df2e5e8a472f3f1ca57">SYSINFO_SOC_MEM_INT_IMEM</a></div><div class="ttdeci">@ SYSINFO_SOC_MEM_INT_IMEM</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:47</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a244710794e00c93e91a7f13d533cb139"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a244710794e00c93e91a7f13d533cb139">SYSINFO_SOC_IO_UART0</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_UART0</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:60</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a24658727efef9747414b5da8f26de66d"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a24658727efef9747414b5da8f26de66d">SYSINFO_SOC_IO_DMA</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_DMA</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:57</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a26b25f1b47f62e98ff0920544f56b57e"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a26b25f1b47f62e98ff0920544f56b57e">SYSINFO_SOC_IO_SLINK</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_SLINK</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:72</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a3d50c94d151d39d8229109e8b12812bf"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a3d50c94d151d39d8229109e8b12812bf">SYSINFO_SOC_CLOCK_GATING</a></div><div class="ttdeci">@ SYSINFO_SOC_CLOCK_GATING</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:52</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a3e50b1c24eec0f1811d5630e6dd33e93"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a3e50b1c24eec0f1811d5630e6dd33e93">SYSINFO_SOC_OCD</a></div><div class="ttdeci">@ SYSINFO_SOC_OCD</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:49</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a44892276837b2b1bbe6ef9faa715ad5d"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a44892276837b2b1bbe6ef9faa715ad5d">SYSINFO_SOC_IO_TRNG</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_TRNG</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:66</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a4aea6c006f9c999720b1dd6166a01afe"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a4aea6c006f9c999720b1dd6166a01afe">SYSINFO_SOC_IO_GPTMR</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_GPTMR</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:71</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a4cf4b1a83a4b52efbf26eace21f5ab20"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a4cf4b1a83a4b52efbf26eace21f5ab20">SYSINFO_SOC_IO_SPI</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_SPI</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:61</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a516a2e254ae63e017caefbeed20f54e9"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a516a2e254ae63e017caefbeed20f54e9">SYSINFO_SOC_XIP</a></div><div class="ttdeci">@ SYSINFO_SOC_XIP</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:54</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a52b0ca1ef2af5e9c9a0250440b2de9e5"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a52b0ca1ef2af5e9c9a0250440b2de9e5">SYSINFO_SOC_IO_UART1</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_UART1</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:68</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a5458b7ad729818c2f42e20c61fcffe2d"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a5458b7ad729818c2f42e20c61fcffe2d">SYSINFO_SOC_IO_MTIME</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_MTIME</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:59</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a579f26ab04d4fd9af8e419df465695ca"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a579f26ab04d4fd9af8e419df465695ca">SYSINFO_SOC_XBUS_CACHE</a></div><div class="ttdeci">@ SYSINFO_SOC_XBUS_CACHE</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:53</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a58ff6e112c09f798be014fdf84385135"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a58ff6e112c09f798be014fdf84385135">SYSINFO_SOC_MEM_INT_DMEM</a></div><div class="ttdeci">@ SYSINFO_SOC_MEM_INT_DMEM</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:48</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a62a2337b33a2f65b6efd5c91e699c2d1"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a62a2337b33a2f65b6efd5c91e699c2d1">SYSINFO_SOC_IO_GPIO</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_GPIO</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:58</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a6899a935ae8c4aef08d828f250342e9a"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a6899a935ae8c4aef08d828f250342e9a">SYSINFO_SOC_BOOTLOADER</a></div><div class="ttdeci">@ SYSINFO_SOC_BOOTLOADER</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:45</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a84088f6664a3dc19041dfad5b551ced9"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a84088f6664a3dc19041dfad5b551ced9">SYSINFO_SOC_IO_SDI</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_SDI</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:67</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a8dc202143c3b13850bccf16380466399"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a8dc202143c3b13850bccf16380466399">SYSINFO_SOC_IO_PWM</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_PWM</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:63</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08a9823c2c0945997ed0d7e5eb473d81e41"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08a9823c2c0945997ed0d7e5eb473d81e41">SYSINFO_SOC_DCACHE</a></div><div class="ttdeci">@ SYSINFO_SOC_DCACHE</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:51</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08aa8ec3b39b36f13ee4f97a72700e881a8"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08aa8ec3b39b36f13ee4f97a72700e881a8">SYSINFO_SOC_IO_ONEWIRE</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_ONEWIRE</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:73</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08ab89821e2c61ccb9db6324ee503f9dfa6"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ab89821e2c61ccb9db6324ee503f9dfa6">SYSINFO_SOC_IO_CRC</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_CRC</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:74</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08ac943fc33a2c1c25c3ab075228b87c0ef"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ac943fc33a2c1c25c3ab075228b87c0ef">SYSINFO_SOC_XIP_CACHE</a></div><div class="ttdeci">@ SYSINFO_SOC_XIP_CACHE</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:55</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08ad1b8d38e3715485242756cd37b7c1fe9"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ad1b8d38e3715485242756cd37b7c1fe9">SYSINFO_SOC_IO_XIRQ</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_XIRQ</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:70</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08add6721803c9d79f1e50248927ba30e16"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08add6721803c9d79f1e50248927ba30e16">SYSINFO_SOC_XBUS</a></div><div class="ttdeci">@ SYSINFO_SOC_XBUS</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:46</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08ae725c2452eeb33e3230dcfb3450598e6"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08ae725c2452eeb33e3230dcfb3450598e6">SYSINFO_SOC_IO_CFS</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_CFS</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:65</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_ae41ebd5785b09640a00df194b1a0fa08afc964f39427cbc4090a960967eada7be"><div class="ttname"><a href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08afc964f39427cbc4090a960967eada7be">SYSINFO_SOC_IO_WDT</a></div><div class="ttdeci">@ SYSINFO_SOC_IO_WDT</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:64</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_aebaa5f3f231003a05c899cc1491b8c5f"><div class="ttname"><a href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5f">NEORV32_SYSINFO_MEM_enum</a></div><div class="ttdeci">NEORV32_SYSINFO_MEM_enum</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:38</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_aebaa5f3f231003a05c899cc1491b8c5fa807d9e70e78e2ba3d5bfb902cc1cdc53"><div class="ttname"><a href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5fa807d9e70e78e2ba3d5bfb902cc1cdc53">SYSINFO_MEM_IMEM</a></div><div class="ttdeci">@ SYSINFO_MEM_IMEM</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:39</div></div> +<div class="ttc" id="aneorv32__sysinfo_8h_html_aebaa5f3f231003a05c899cc1491b8c5fa8a46c064e5a1339978a5fb1f41301894"><div class="ttname"><a href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5fa8a46c064e5a1339978a5fb1f41301894">SYSINFO_MEM_DMEM</a></div><div class="ttdeci">@ SYSINFO_MEM_DMEM</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:40</div></div> +<div class="ttc" id="astructneorv32__sysinfo__t_html"><div class="ttname"><a href="structneorv32__sysinfo__t.html">neorv32_sysinfo_t</a></div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:27</div></div> +<div class="ttc" id="astructneorv32__sysinfo__t_html_a3f8ce96050fc0a680afa9b7fdf7cb35c"><div class="ttname"><a href="structneorv32__sysinfo__t.html#a3f8ce96050fc0a680afa9b7fdf7cb35c">neorv32_sysinfo_t::CLK</a></div><div class="ttdeci">uint32_t CLK</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:28</div></div> +<div class="ttc" id="astructneorv32__sysinfo__t_html_ac43abe3b416da3a2895d1d06537a14c3"><div class="ttname"><a href="structneorv32__sysinfo__t.html#ac43abe3b416da3a2895d1d06537a14c3">neorv32_sysinfo_t::SOC</a></div><div class="ttdeci">const uint32_t SOC</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:30</div></div> +<div class="ttc" id="astructneorv32__sysinfo__t_html_ada99a36ccda38b254d5b6a84883101f6"><div class="ttname"><a href="structneorv32__sysinfo__t.html#ada99a36ccda38b254d5b6a84883101f6">neorv32_sysinfo_t::CACHE</a></div><div class="ttdeci">const uint32_t CACHE</div><div class="ttdef"><b>Definition</b> neorv32_sysinfo.h:31</div></div> +</div><!-- fragment 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_trng.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>True Random Number Generator (TRNG) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:af0c4139ff68763623b3d658a8dd8b5ce" id="r_af0c4139ff68763623b3d658a8dd8b5ce"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af0c4139ff68763623b3d658a8dd8b5ce">neorv32_trng_available</a> (void)</td></tr> +<tr class="separator:af0c4139ff68763623b3d658a8dd8b5ce"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8b8a1771e37a152792264561b93228fa" id="r_a8b8a1771e37a152792264561b93228fa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8b8a1771e37a152792264561b93228fa">neorv32_trng_enable</a> (int irq_sel)</td></tr> +<tr class="separator:a8b8a1771e37a152792264561b93228fa"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae838bc980e28c300dc2c9c3f34a46bb8" id="r_ae838bc980e28c300dc2c9c3f34a46bb8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae838bc980e28c300dc2c9c3f34a46bb8">neorv32_trng_disable</a> (void)</td></tr> +<tr class="separator:ae838bc980e28c300dc2c9c3f34a46bb8"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a87cfe338e2ff559f96c73f729465f967" id="r_a87cfe338e2ff559f96c73f729465f967"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a87cfe338e2ff559f96c73f729465f967">neorv32_trng_fifo_clear</a> (void)</td></tr> +<tr class="separator:a87cfe338e2ff559f96c73f729465f967"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad24e44372f4fd1ed29a6967dccab4fb0" id="r_ad24e44372f4fd1ed29a6967dccab4fb0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad24e44372f4fd1ed29a6967dccab4fb0">neorv32_trng_get_fifo_depth</a> (void)</td></tr> +<tr class="separator:ad24e44372f4fd1ed29a6967dccab4fb0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9148bcb6a7c448c364e78fa98aac6985" id="r_a9148bcb6a7c448c364e78fa98aac6985"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9148bcb6a7c448c364e78fa98aac6985">neorv32_trng_get</a> (uint8_t *data)</td></tr> +<tr class="separator:a9148bcb6a7c448c364e78fa98aac6985"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aba36f08dd88f2f3e58353ae72eaa14f7" id="r_aba36f08dd88f2f3e58353ae72eaa14f7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aba36f08dd88f2f3e58353ae72eaa14f7">neorv32_trng_check_sim_mode</a> (void)</td></tr> +<tr class="separator:aba36f08dd88f2f3e58353ae72eaa14f7"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>True Random Number Generator (TRNG) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the TRNG unit was synthesized (IO_TRNG_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="af0c4139ff68763623b3d658a8dd8b5ce" name="af0c4139ff68763623b3d658a8dd8b5ce"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af0c4139ff68763623b3d658a8dd8b5ce">&#9670;&#160;</a></span>neorv32_trng_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_trng_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if TRNG unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if TRNG was not synthesized, 1 if TRNG is available. </dd></dl> + +</div> +</div> +<a id="aba36f08dd88f2f3e58353ae72eaa14f7" name="aba36f08dd88f2f3e58353ae72eaa14f7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aba36f08dd88f2f3e58353ae72eaa14f7">&#9670;&#160;</a></span>neorv32_trng_check_sim_mode()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_trng_check_sim_mode </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if TRNG is implemented using SIMULATION mode.</p> +<dl class="section warning"><dt>Warning</dt><dd>In simulation mode the physical entropy source is replaced by a PRNG (LFSR) with very bad random quality.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Simulation mode active when not zero. </dd></dl> + +</div> +</div> +<a id="ae838bc980e28c300dc2c9c3f34a46bb8" name="ae838bc980e28c300dc2c9c3f34a46bb8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae838bc980e28c300dc2c9c3f34a46bb8">&#9670;&#160;</a></span>neorv32_trng_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_trng_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset and disable TRNG. </p> + +</div> +</div> +<a id="a8b8a1771e37a152792264561b93228fa" name="a8b8a1771e37a152792264561b93228fa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8b8a1771e37a152792264561b93228fa">&#9670;&#160;</a></span>neorv32_trng_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_trng_enable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>irq_sel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, configure and enable TRNG.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_sel</td><td>Interrupt trigger select (0 = data available, 1 = FIFO full). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a87cfe338e2ff559f96c73f729465f967" name="a87cfe338e2ff559f96c73f729465f967"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a87cfe338e2ff559f96c73f729465f967">&#9670;&#160;</a></span>neorv32_trng_fifo_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_trng_fifo_clear </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Flush TRNG random data FIFO. </p> + +</div> +</div> +<a id="a9148bcb6a7c448c364e78fa98aac6985" name="a9148bcb6a7c448c364e78fa98aac6985"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9148bcb6a7c448c364e78fa98aac6985">&#9670;&#160;</a></span>neorv32_trng_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_trng_get </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get random data byte from TRNG.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">data</td><td>uint8_t pointer for storing random data byte. Will be set to zero if no valid data available. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Data is valid when 0 and invalid otherwise. </dd></dl> + +</div> +</div> +<a id="ad24e44372f4fd1ed29a6967dccab4fb0" name="ad24e44372f4fd1ed29a6967dccab4fb0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad24e44372f4fd1ed29a6967dccab4fb0">&#9670;&#160;</a></span>neorv32_trng_get_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_trng_get_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get TRNG FIFO depth.</p> +<dl class="section return"><dt>Returns</dt><dd>TRNG FIFO size (number of entries). </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address 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class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__trng__t.html">neorv32_trng_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:af0c4139ff68763623b3d658a8dd8b5ce" id="r_af0c4139ff68763623b3d658a8dd8b5ce"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af0c4139ff68763623b3d658a8dd8b5ce">neorv32_trng_available</a> (void)</td></tr> +<tr class="separator:af0c4139ff68763623b3d658a8dd8b5ce"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8b8a1771e37a152792264561b93228fa" id="r_a8b8a1771e37a152792264561b93228fa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8b8a1771e37a152792264561b93228fa">neorv32_trng_enable</a> (int irq_sel)</td></tr> +<tr class="separator:a8b8a1771e37a152792264561b93228fa"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae838bc980e28c300dc2c9c3f34a46bb8" id="r_ae838bc980e28c300dc2c9c3f34a46bb8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae838bc980e28c300dc2c9c3f34a46bb8">neorv32_trng_disable</a> (void)</td></tr> +<tr class="separator:ae838bc980e28c300dc2c9c3f34a46bb8"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a87cfe338e2ff559f96c73f729465f967" id="r_a87cfe338e2ff559f96c73f729465f967"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a87cfe338e2ff559f96c73f729465f967">neorv32_trng_fifo_clear</a> (void)</td></tr> +<tr class="separator:a87cfe338e2ff559f96c73f729465f967"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad24e44372f4fd1ed29a6967dccab4fb0" id="r_ad24e44372f4fd1ed29a6967dccab4fb0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad24e44372f4fd1ed29a6967dccab4fb0">neorv32_trng_get_fifo_depth</a> (void)</td></tr> +<tr class="separator:ad24e44372f4fd1ed29a6967dccab4fb0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9148bcb6a7c448c364e78fa98aac6985" id="r_a9148bcb6a7c448c364e78fa98aac6985"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9148bcb6a7c448c364e78fa98aac6985">neorv32_trng_get</a> (uint8_t *data)</td></tr> +<tr class="separator:a9148bcb6a7c448c364e78fa98aac6985"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aba36f08dd88f2f3e58353ae72eaa14f7" id="r_aba36f08dd88f2f3e58353ae72eaa14f7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aba36f08dd88f2f3e58353ae72eaa14f7">neorv32_trng_check_sim_mode</a> (void)</td></tr> +<tr class="separator:aba36f08dd88f2f3e58353ae72eaa14f7"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: True Random Number Generator (TRNG)</h2></td></tr> +<tr class="memitem:a9794ff3746eb5321ad9c2bf522ea26dd" id="r_a9794ff3746eb5321ad9c2bf522ea26dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9794ff3746eb5321ad9c2bf522ea26dd">NEORV32_TRNG</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__trng__t.html">neorv32_trng_t</a>*) (<a class="el" href="neorv32_8h.html#ab4846cd153e8a23deec45d81cc8372a2">NEORV32_TRNG_BASE</a>))</td></tr> +<tr class="separator:a9794ff3746eb5321ad9c2bf522ea26dd"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1440e1355bf5bff17760992adc156b1a" id="r_a1440e1355bf5bff17760992adc156b1a"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1440e1355bf5bff17760992adc156b1a">NEORV32_TRNG_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a1440e1355bf5bff17760992adc156b1aa50bb6e10e245a977dcf29a7a138776c6">TRNG_CTRL_DATA_LSB</a> = 0 +, <a class="el" href="#a1440e1355bf5bff17760992adc156b1aa95620874acc9393a05d670824c0bbed2">TRNG_CTRL_DATA_MSB</a> = 7 +, <a class="el" href="#a1440e1355bf5bff17760992adc156b1aa8c0325eede4ffec4530cfd5dc700dc52">TRNG_CTRL_FIFO_LSB</a> = 16 +, <a class="el" href="#a1440e1355bf5bff17760992adc156b1aa919c3105723e4fe46e341c63cbf276f5">TRNG_CTRL_FIFO_MSB</a> = 19 +, <br /> +&#160;&#160;<a class="el" href="#a1440e1355bf5bff17760992adc156b1aa968a770fe6b172183dd97818e09c63da">TRNG_CTRL_IRQ_SEL</a> = 27 +, <a class="el" href="#a1440e1355bf5bff17760992adc156b1aabf1bb7bc3b44394c85709edd1c9f03ac">TRNG_CTRL_FIFO_CLR</a> = 28 +, <a class="el" href="#a1440e1355bf5bff17760992adc156b1aaa6990058793ac7d96250693f935837c5">TRNG_CTRL_SIM_MODE</a> = 29 +, <a class="el" href="#a1440e1355bf5bff17760992adc156b1aa0bdf0194eefe95884c5c5853a2f7670d">TRNG_CTRL_EN</a> = 30 +, <br /> +&#160;&#160;<a class="el" href="#a1440e1355bf5bff17760992adc156b1aa2e0079358668db409fb763eaccb93da9">TRNG_CTRL_VALID</a> = 31 +<br /> + }</td></tr> +<tr class="separator:a1440e1355bf5bff17760992adc156b1a"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>True Random Number Generator (TRNG) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the TRNG unit was synthesized (IO_TRNG_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a9794ff3746eb5321ad9c2bf522ea26dd" name="a9794ff3746eb5321ad9c2bf522ea26dd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9794ff3746eb5321ad9c2bf522ea26dd">&#9670;&#160;</a></span>NEORV32_TRNG</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_TRNG&#160;&#160;&#160;((<a class="el" href="structneorv32__trng__t.html">neorv32_trng_t</a>*) (<a class="el" href="neorv32_8h.html#ab4846cd153e8a23deec45d81cc8372a2">NEORV32_TRNG_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>TRNG module hardware access (<a class="el" href="structneorv32__trng__t.html">neorv32_trng_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a1440e1355bf5bff17760992adc156b1a" name="a1440e1355bf5bff17760992adc156b1a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1440e1355bf5bff17760992adc156b1a">&#9670;&#160;</a></span>NEORV32_TRNG_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a1440e1355bf5bff17760992adc156b1a">NEORV32_TRNG_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>TRNG control/data register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aa50bb6e10e245a977dcf29a7a138776c6" name="a1440e1355bf5bff17760992adc156b1aa50bb6e10e245a977dcf29a7a138776c6"></a>TRNG_CTRL_DATA_LSB&#160;</td><td class="fielddoc"><p>TRNG data/control register(0) (r/-): Random data byte LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aa95620874acc9393a05d670824c0bbed2" name="a1440e1355bf5bff17760992adc156b1aa95620874acc9393a05d670824c0bbed2"></a>TRNG_CTRL_DATA_MSB&#160;</td><td class="fielddoc"><p>TRNG data/control register(7) (r/-): Random data byte MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aa8c0325eede4ffec4530cfd5dc700dc52" name="a1440e1355bf5bff17760992adc156b1aa8c0325eede4ffec4530cfd5dc700dc52"></a>TRNG_CTRL_FIFO_LSB&#160;</td><td class="fielddoc"><p>TRNG data/control register(16) (r/-): log2(FIFO size), LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aa919c3105723e4fe46e341c63cbf276f5" name="a1440e1355bf5bff17760992adc156b1aa919c3105723e4fe46e341c63cbf276f5"></a>TRNG_CTRL_FIFO_MSB&#160;</td><td class="fielddoc"><p>TRNG data/control register(19) (r/-): log2(FIFO size), MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aa968a770fe6b172183dd97818e09c63da" name="a1440e1355bf5bff17760992adc156b1aa968a770fe6b172183dd97818e09c63da"></a>TRNG_CTRL_IRQ_SEL&#160;</td><td class="fielddoc"><p>TRNG data/control register(27) (r/w): Interrupt trigger select (0 = data available, 1 = FIFO full) </p> +</td></tr> +<tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aabf1bb7bc3b44394c85709edd1c9f03ac" name="a1440e1355bf5bff17760992adc156b1aabf1bb7bc3b44394c85709edd1c9f03ac"></a>TRNG_CTRL_FIFO_CLR&#160;</td><td class="fielddoc"><p>TRNG data/control register(28) (-/w): Clear data FIFO (auto clears) </p> +</td></tr> +<tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aaa6990058793ac7d96250693f935837c5" name="a1440e1355bf5bff17760992adc156b1aaa6990058793ac7d96250693f935837c5"></a>TRNG_CTRL_SIM_MODE&#160;</td><td class="fielddoc"><p>TRNG data/control register(29) (r/-): PRNG mode (simulation mode) </p> +</td></tr> +<tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aa0bdf0194eefe95884c5c5853a2f7670d" name="a1440e1355bf5bff17760992adc156b1aa0bdf0194eefe95884c5c5853a2f7670d"></a>TRNG_CTRL_EN&#160;</td><td class="fielddoc"><p>TRNG data/control register(30) (r/w): TRNG enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a1440e1355bf5bff17760992adc156b1aa2e0079358668db409fb763eaccb93da9" name="a1440e1355bf5bff17760992adc156b1aa2e0079358668db409fb763eaccb93da9"></a>TRNG_CTRL_VALID&#160;</td><td class="fielddoc"><p>TRNG data/control register(31) (r/-): Random data output valid </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="af0c4139ff68763623b3d658a8dd8b5ce" name="af0c4139ff68763623b3d658a8dd8b5ce"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af0c4139ff68763623b3d658a8dd8b5ce">&#9670;&#160;</a></span>neorv32_trng_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_trng_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if TRNG unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if TRNG was not synthesized, 1 if TRNG is available. </dd></dl> + +</div> +</div> +<a id="aba36f08dd88f2f3e58353ae72eaa14f7" name="aba36f08dd88f2f3e58353ae72eaa14f7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aba36f08dd88f2f3e58353ae72eaa14f7">&#9670;&#160;</a></span>neorv32_trng_check_sim_mode()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_trng_check_sim_mode </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if TRNG is implemented using SIMULATION mode.</p> +<dl class="section warning"><dt>Warning</dt><dd>In simulation mode the physical entropy source is replaced by a PRNG (LFSR) with very bad random quality.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>Simulation mode active when not zero. </dd></dl> + +</div> +</div> +<a id="ae838bc980e28c300dc2c9c3f34a46bb8" name="ae838bc980e28c300dc2c9c3f34a46bb8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae838bc980e28c300dc2c9c3f34a46bb8">&#9670;&#160;</a></span>neorv32_trng_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_trng_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset and disable TRNG. </p> + +</div> +</div> +<a id="a8b8a1771e37a152792264561b93228fa" name="a8b8a1771e37a152792264561b93228fa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8b8a1771e37a152792264561b93228fa">&#9670;&#160;</a></span>neorv32_trng_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_trng_enable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>irq_sel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, configure and enable TRNG.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_sel</td><td>Interrupt trigger select (0 = data available, 1 = FIFO full). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a87cfe338e2ff559f96c73f729465f967" name="a87cfe338e2ff559f96c73f729465f967"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a87cfe338e2ff559f96c73f729465f967">&#9670;&#160;</a></span>neorv32_trng_fifo_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_trng_fifo_clear </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Flush TRNG random data FIFO. </p> + +</div> +</div> +<a id="a9148bcb6a7c448c364e78fa98aac6985" name="a9148bcb6a7c448c364e78fa98aac6985"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9148bcb6a7c448c364e78fa98aac6985">&#9670;&#160;</a></span>neorv32_trng_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_trng_get </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get random data byte from TRNG.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">data</td><td>uint8_t pointer for storing random data byte. Will be set to zero if no valid data available. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Data is valid when 0 and invalid otherwise. </dd></dl> + +</div> +</div> +<a id="ad24e44372f4fd1ed29a6967dccab4fb0" name="ad24e44372f4fd1ed29a6967dccab4fb0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad24e44372f4fd1ed29a6967dccab4fb0">&#9670;&#160;</a></span>neorv32_trng_get_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_trng_get_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get TRNG FIFO depth.</p> +<dl class="section return"><dt>Returns</dt><dd>TRNG FIFO size (number of entries). </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__trng_8h_source.html b/sw/neorv32__trng_8h_source.html new file mode 100644 index 000000000..31090710f --- /dev/null +++ b/sw/neorv32__trng_8h_source.html @@ -0,0 +1,167 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_trng.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_trng_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_trng_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__trng__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__trng__t.html#ae2ff37ce30fb85ef59d9012534bc7e67"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__trng__t.html#ae2ff37ce30fb85ef59d9012534bc7e67">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span>} <a class="code hl_struct" href="structneorv32__trng__t.html">neorv32_trng_t</a>;</div> +</div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a9794ff3746eb5321ad9c2bf522ea26dd"> 34</a></span><span class="preprocessor">#define NEORV32_TRNG ((neorv32_trng_t*) (NEORV32_TRNG_BASE))</span></div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div> +<div class="foldopen" id="foldopen00037" data-start="{" data-end="};"> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1a"> 37</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1a">NEORV32_TRNG_CTRL_enum</a> {</div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa50bb6e10e245a977dcf29a7a138776c6"> 38</a></span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa50bb6e10e245a977dcf29a7a138776c6">TRNG_CTRL_DATA_LSB</a> = 0, </div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa95620874acc9393a05d670824c0bbed2"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa95620874acc9393a05d670824c0bbed2">TRNG_CTRL_DATA_MSB</a> = 7, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa8c0325eede4ffec4530cfd5dc700dc52"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa8c0325eede4ffec4530cfd5dc700dc52">TRNG_CTRL_FIFO_LSB</a> = 16, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa919c3105723e4fe46e341c63cbf276f5"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa919c3105723e4fe46e341c63cbf276f5">TRNG_CTRL_FIFO_MSB</a> = 19, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa968a770fe6b172183dd97818e09c63da"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa968a770fe6b172183dd97818e09c63da">TRNG_CTRL_IRQ_SEL</a> = 27, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aabf1bb7bc3b44394c85709edd1c9f03ac"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aabf1bb7bc3b44394c85709edd1c9f03ac">TRNG_CTRL_FIFO_CLR</a> = 28, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aaa6990058793ac7d96250693f935837c5"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aaa6990058793ac7d96250693f935837c5">TRNG_CTRL_SIM_MODE</a> = 29, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa0bdf0194eefe95884c5c5853a2f7670d"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa0bdf0194eefe95884c5c5853a2f7670d">TRNG_CTRL_EN</a> = 30, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> <a class="code hl_enumvalue" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa2e0079358668db409fb763eaccb93da9">TRNG_CTRL_VALID</a> = 31 </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa2e0079358668db409fb763eaccb93da9"> 49</a></span>};</div> +</div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__trng_8h.html#af0c4139ff68763623b3d658a8dd8b5ce">neorv32_trng_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__trng_8h.html#a8b8a1771e37a152792264561b93228fa">neorv32_trng_enable</a>(<span class="keywordtype">int</span> irq_sel);</div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__trng_8h.html#ae838bc980e28c300dc2c9c3f34a46bb8">neorv32_trng_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__trng_8h.html#a87cfe338e2ff559f96c73f729465f967">neorv32_trng_fifo_clear</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__trng_8h.html#ad24e44372f4fd1ed29a6967dccab4fb0">neorv32_trng_get_fifo_depth</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__trng_8h.html#a9148bcb6a7c448c364e78fa98aac6985">neorv32_trng_get</a>(uint8_t *data);</div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__trng_8h.html#aba36f08dd88f2f3e58353ae72eaa14f7">neorv32_trng_check_sim_mode</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_trng_h</span></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1a"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1a">NEORV32_TRNG_CTRL_enum</a></div><div class="ttdeci">NEORV32_TRNG_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:37</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aa0bdf0194eefe95884c5c5853a2f7670d"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa0bdf0194eefe95884c5c5853a2f7670d">TRNG_CTRL_EN</a></div><div class="ttdeci">@ TRNG_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:47</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aa2e0079358668db409fb763eaccb93da9"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa2e0079358668db409fb763eaccb93da9">TRNG_CTRL_VALID</a></div><div class="ttdeci">@ TRNG_CTRL_VALID</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:48</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aa50bb6e10e245a977dcf29a7a138776c6"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa50bb6e10e245a977dcf29a7a138776c6">TRNG_CTRL_DATA_LSB</a></div><div class="ttdeci">@ TRNG_CTRL_DATA_LSB</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:38</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aa8c0325eede4ffec4530cfd5dc700dc52"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa8c0325eede4ffec4530cfd5dc700dc52">TRNG_CTRL_FIFO_LSB</a></div><div class="ttdeci">@ TRNG_CTRL_FIFO_LSB</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:41</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aa919c3105723e4fe46e341c63cbf276f5"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa919c3105723e4fe46e341c63cbf276f5">TRNG_CTRL_FIFO_MSB</a></div><div class="ttdeci">@ TRNG_CTRL_FIFO_MSB</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:42</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aa95620874acc9393a05d670824c0bbed2"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa95620874acc9393a05d670824c0bbed2">TRNG_CTRL_DATA_MSB</a></div><div class="ttdeci">@ TRNG_CTRL_DATA_MSB</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:39</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aa968a770fe6b172183dd97818e09c63da"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aa968a770fe6b172183dd97818e09c63da">TRNG_CTRL_IRQ_SEL</a></div><div class="ttdeci">@ TRNG_CTRL_IRQ_SEL</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:44</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aaa6990058793ac7d96250693f935837c5"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aaa6990058793ac7d96250693f935837c5">TRNG_CTRL_SIM_MODE</a></div><div class="ttdeci">@ TRNG_CTRL_SIM_MODE</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:46</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a1440e1355bf5bff17760992adc156b1aabf1bb7bc3b44394c85709edd1c9f03ac"><div class="ttname"><a href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1aabf1bb7bc3b44394c85709edd1c9f03ac">TRNG_CTRL_FIFO_CLR</a></div><div class="ttdeci">@ TRNG_CTRL_FIFO_CLR</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:45</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a87cfe338e2ff559f96c73f729465f967"><div class="ttname"><a href="neorv32__trng_8h.html#a87cfe338e2ff559f96c73f729465f967">neorv32_trng_fifo_clear</a></div><div class="ttdeci">void neorv32_trng_fifo_clear(void)</div><div class="ttdef"><b>Definition</b> neorv32_trng.c:72</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a8b8a1771e37a152792264561b93228fa"><div class="ttname"><a href="neorv32__trng_8h.html#a8b8a1771e37a152792264561b93228fa">neorv32_trng_enable</a></div><div class="ttdeci">void neorv32_trng_enable(int irq_sel)</div><div class="ttdef"><b>Definition</b> neorv32_trng.c:42</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_a9148bcb6a7c448c364e78fa98aac6985"><div class="ttname"><a href="neorv32__trng_8h.html#a9148bcb6a7c448c364e78fa98aac6985">neorv32_trng_get</a></div><div class="ttdeci">int neorv32_trng_get(uint8_t *data)</div><div class="ttdef"><b>Definition</b> neorv32_trng.c:96</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_aba36f08dd88f2f3e58353ae72eaa14f7"><div class="ttname"><a href="neorv32__trng_8h.html#aba36f08dd88f2f3e58353ae72eaa14f7">neorv32_trng_check_sim_mode</a></div><div class="ttdeci">int neorv32_trng_check_sim_mode(void)</div><div class="ttdef"><b>Definition</b> neorv32_trng.c:117</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_ad24e44372f4fd1ed29a6967dccab4fb0"><div class="ttname"><a href="neorv32__trng_8h.html#ad24e44372f4fd1ed29a6967dccab4fb0">neorv32_trng_get_fifo_depth</a></div><div class="ttdeci">int neorv32_trng_get_fifo_depth(void)</div><div class="ttdef"><b>Definition</b> neorv32_trng.c:83</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_ae838bc980e28c300dc2c9c3f34a46bb8"><div class="ttname"><a href="neorv32__trng_8h.html#ae838bc980e28c300dc2c9c3f34a46bb8">neorv32_trng_disable</a></div><div class="ttdeci">void neorv32_trng_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_trng.c:63</div></div> +<div class="ttc" id="aneorv32__trng_8h_html_af0c4139ff68763623b3d658a8dd8b5ce"><div class="ttname"><a href="neorv32__trng_8h.html#af0c4139ff68763623b3d658a8dd8b5ce">neorv32_trng_available</a></div><div class="ttdeci">int neorv32_trng_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_trng.c:26</div></div> +<div class="ttc" id="astructneorv32__trng__t_html"><div class="ttname"><a href="structneorv32__trng__t.html">neorv32_trng_t</a></div><div class="ttdef"><b>Definition</b> neorv32_trng.h:29</div></div> +<div class="ttc" id="astructneorv32__trng__t_html_ae2ff37ce30fb85ef59d9012534bc7e67"><div class="ttname"><a href="structneorv32__trng__t.html#ae2ff37ce30fb85ef59d9012534bc7e67">neorv32_trng_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_trng.h:30</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" 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href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_twi.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Two-Wire Interface Controller (TWI) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:aa2e01ebbc0c82d65ed4ded351f4d8711" id="r_aa2e01ebbc0c82d65ed4ded351f4d8711"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa2e01ebbc0c82d65ed4ded351f4d8711">neorv32_twi_available</a> (void)</td></tr> +<tr class="separator:aa2e01ebbc0c82d65ed4ded351f4d8711"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7ea6f3509a7cf622234d4b83e33afbe3" id="r_a7ea6f3509a7cf622234d4b83e33afbe3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7ea6f3509a7cf622234d4b83e33afbe3">neorv32_twi_setup</a> (int prsc, int cdiv, int clkstr)</td></tr> +<tr class="separator:a7ea6f3509a7cf622234d4b83e33afbe3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2c8f3bc55f4a9a8bdcb111759cf56ae2" id="r_a2c8f3bc55f4a9a8bdcb111759cf56ae2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2c8f3bc55f4a9a8bdcb111759cf56ae2">neorv32_twi_get_fifo_depth</a> (void)</td></tr> +<tr class="separator:a2c8f3bc55f4a9a8bdcb111759cf56ae2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae5f31e737c7a6c3c86070ff34cb0d861" id="r_ae5f31e737c7a6c3c86070ff34cb0d861"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae5f31e737c7a6c3c86070ff34cb0d861">neorv32_twi_disable</a> (void)</td></tr> +<tr class="separator:ae5f31e737c7a6c3c86070ff34cb0d861"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a22717887cffff1e6830756bc73140e7b" id="r_a22717887cffff1e6830756bc73140e7b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a22717887cffff1e6830756bc73140e7b">neorv32_twi_enable</a> (void)</td></tr> +<tr class="separator:a22717887cffff1e6830756bc73140e7b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4fff1ddade320f6cc568c6266f2c2acd" id="r_a4fff1ddade320f6cc568c6266f2c2acd"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4fff1ddade320f6cc568c6266f2c2acd">neorv32_twi_busy</a> (void)</td></tr> +<tr class="separator:a4fff1ddade320f6cc568c6266f2c2acd"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7735376d26560866b153ed205dfcb2ba" id="r_a7735376d26560866b153ed205dfcb2ba"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7735376d26560866b153ed205dfcb2ba">neorv32_twi_get</a> (uint8_t *data)</td></tr> +<tr class="separator:a7735376d26560866b153ed205dfcb2ba"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac7020f3379602f11c47ca16f1bd82f2e" id="r_ac7020f3379602f11c47ca16f1bd82f2e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac7020f3379602f11c47ca16f1bd82f2e">neorv32_twi_trans</a> (uint8_t *data, int mack)</td></tr> +<tr class="separator:ac7020f3379602f11c47ca16f1bd82f2e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad352447adcccccabd4e20577b34fbece" id="r_ad352447adcccccabd4e20577b34fbece"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad352447adcccccabd4e20577b34fbece">neorv32_twi_generate_stop</a> (void)</td></tr> +<tr class="separator:ad352447adcccccabd4e20577b34fbece"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a633d460e4735eb369d74a834b03c8b78" id="r_a633d460e4735eb369d74a834b03c8b78"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a633d460e4735eb369d74a834b03c8b78">neorv32_twi_generate_start</a> (void)</td></tr> +<tr class="separator:a633d460e4735eb369d74a834b03c8b78"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a28fc44cce5d28f6e8c32268b239b07d5" id="r_a28fc44cce5d28f6e8c32268b239b07d5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a28fc44cce5d28f6e8c32268b239b07d5">neorv32_twi_send_nonblocking</a> (uint8_t data, int mack)</td></tr> +<tr class="separator:a28fc44cce5d28f6e8c32268b239b07d5"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa22430aab0a38d88cbd2c4220c573da0" id="r_aa22430aab0a38d88cbd2c4220c573da0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa22430aab0a38d88cbd2c4220c573da0">neorv32_twi_generate_stop_nonblocking</a> (void)</td></tr> +<tr class="separator:aa22430aab0a38d88cbd2c4220c573da0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adbf2eaed0c76221da5c3091665fc885e" id="r_adbf2eaed0c76221da5c3091665fc885e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adbf2eaed0c76221da5c3091665fc885e">neorv32_twi_generate_start_nonblocking</a> (void)</td></tr> +<tr class="separator:adbf2eaed0c76221da5c3091665fc885e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Two-Wire Interface Controller (TWI) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the TWI unit was synthesized (IO_TWI_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="aa2e01ebbc0c82d65ed4ded351f4d8711" name="aa2e01ebbc0c82d65ed4ded351f4d8711"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa2e01ebbc0c82d65ed4ded351f4d8711">&#9670;&#160;</a></span>neorv32_twi_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if TWI unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if TWI was not synthesized, 1 if TWI is available. </dd></dl> + +</div> +</div> +<a id="a4fff1ddade320f6cc568c6266f2c2acd" name="a4fff1ddade320f6cc568c6266f2c2acd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4fff1ddade320f6cc568c6266f2c2acd">&#9670;&#160;</a></span>neorv32_twi_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_busy </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if TWI is busy (TWI bus engine busy or TX FIFO not empty).</p> +<dl class="section return"><dt>Returns</dt><dd>0 if idle, 1 if busy </dd></dl> + +</div> +</div> +<a id="ae5f31e737c7a6c3c86070ff34cb0d861" name="ae5f31e737c7a6c3c86070ff34cb0d861"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae5f31e737c7a6c3c86070ff34cb0d861">&#9670;&#160;</a></span>neorv32_twi_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable TWI controller. </p> + +</div> +</div> +<a id="a22717887cffff1e6830756bc73140e7b" name="a22717887cffff1e6830756bc73140e7b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a22717887cffff1e6830756bc73140e7b">&#9670;&#160;</a></span>neorv32_twi_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable TWI controller. </p> + +</div> +</div> +<a id="a633d460e4735eb369d74a834b03c8b78" name="a633d460e4735eb369d74a834b03c8b78"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a633d460e4735eb369d74a834b03c8b78">&#9670;&#160;</a></span>neorv32_twi_generate_start()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_generate_start </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate START (or REPEATED-START) condition.</p> +<dl class="section note"><dt>Note</dt><dd>Blocking function. </dd></dl> + +</div> +</div> +<a id="adbf2eaed0c76221da5c3091665fc885e" name="adbf2eaed0c76221da5c3091665fc885e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adbf2eaed0c76221da5c3091665fc885e">&#9670;&#160;</a></span>neorv32_twi_generate_start_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_generate_start_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate START (or REPEATED-START) condition.</p> +<dl class="section note"><dt>Note</dt><dd>Non-blocking function; does not check the TX FIFO. </dd></dl> + +</div> +</div> +<a id="ad352447adcccccabd4e20577b34fbece" name="ad352447adcccccabd4e20577b34fbece"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad352447adcccccabd4e20577b34fbece">&#9670;&#160;</a></span>neorv32_twi_generate_stop()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_generate_stop </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate STOP condition.</p> +<dl class="section note"><dt>Note</dt><dd>Blocking function. </dd></dl> + +</div> +</div> +<a id="aa22430aab0a38d88cbd2c4220c573da0" name="aa22430aab0a38d88cbd2c4220c573da0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa22430aab0a38d88cbd2c4220c573da0">&#9670;&#160;</a></span>neorv32_twi_generate_stop_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_generate_stop_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate STOP condition.</p> +<dl class="section note"><dt>Note</dt><dd>Non-blocking function; does not check the TX FIFO. </dd></dl> + +</div> +</div> +<a id="a7735376d26560866b153ed205dfcb2ba" name="a7735376d26560866b153ed205dfcb2ba"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7735376d26560866b153ed205dfcb2ba">&#9670;&#160;</a></span>neorv32_twi_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_get </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get received data + ACK/NACH from RX FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">data</td><td>Pointer for returned data (uint8_t). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>RX FIFO access status (-1 = no data available, 0 = ACK received, 1 = NACK received). </dd></dl> + +</div> +</div> +<a id="a2c8f3bc55f4a9a8bdcb111759cf56ae2" name="a2c8f3bc55f4a9a8bdcb111759cf56ae2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2c8f3bc55f4a9a8bdcb111759cf56ae2">&#9670;&#160;</a></span>neorv32_twi_get_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_get_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get TWI FIFO depth.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries), zero if no FIFO implemented </dd></dl> + +</div> +</div> +<a id="a28fc44cce5d28f6e8c32268b239b07d5" name="a28fc44cce5d28f6e8c32268b239b07d5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a28fc44cce5d28f6e8c32268b239b07d5">&#9670;&#160;</a></span>neorv32_twi_send_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_send_nonblocking </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>data</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>mack</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send data byte (RX can be read via <a class="el" href="#a7735376d26560866b153ed205dfcb2ba">neorv32_twi_get()</a>).</p> +<dl class="section note"><dt>Note</dt><dd>Non-blocking function; does not check the TX FIFO.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>Data byte to be send. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">mack</td><td>Generate ACK by host controller when set. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a7ea6f3509a7cf622234d4b83e33afbe3" name="a7ea6f3509a7cf622234d4b83e33afbe3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7ea6f3509a7cf622234d4b83e33afbe3">&#9670;&#160;</a></span>neorv32_twi_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_setup </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cdiv</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>clkstr</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable and configure TWI controller. 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See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cdiv</td><td>Clock divider (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">clkstr</td><td>Enable (allow) clock stretching. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac7020f3379602f11c47ca16f1bd82f2e" name="ac7020f3379602f11c47ca16f1bd82f2e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac7020f3379602f11c47ca16f1bd82f2e">&#9670;&#160;</a></span>neorv32_twi_trans()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_trans </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>data</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>mack</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>TWI transfer: send data byte and also receive data byte.</p> +<dl class="section note"><dt>Note</dt><dd>Blocking function.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">data</td><td>Pointer for TX/RX data (uint8_t). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">mack</td><td>Generate ACK by host controller when set. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0: ACK received, 1: NACK received. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> 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+</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#nested-classes">Data Structures</a> </div> + <div class="headertitle"><div class="title">neorv32_twi.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Two-Wire Interface Controller (TWI) HW driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +</div> +<p><a href="neorv32__twi_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__twi__t.html">neorv32_twi_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">TWI commands</div></td></tr> +<tr class="memitem:a62866821d0aa4500114ce2a7295ffb73" id="r_a62866821d0aa4500114ce2a7295ffb73"><td class="memItemLeft" align="right" valign="top"><a id="a62866821d0aa4500114ce2a7295ffb73" name="a62866821d0aa4500114ce2a7295ffb73"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>TWI_CMD_NOP</b>&#160;&#160;&#160;(0b00)</td></tr> +<tr class="separator:a62866821d0aa4500114ce2a7295ffb73"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad55273f04f6b92146f0a1c3e8e6abe5e" id="r_ad55273f04f6b92146f0a1c3e8e6abe5e"><td class="memItemLeft" align="right" valign="top"><a id="ad55273f04f6b92146f0a1c3e8e6abe5e" name="ad55273f04f6b92146f0a1c3e8e6abe5e"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>TWI_CMD_START</b>&#160;&#160;&#160;(0b01)</td></tr> +<tr class="separator:ad55273f04f6b92146f0a1c3e8e6abe5e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8b6b6c0bbeee2df9d3e246c4e49c2bd9" id="r_a8b6b6c0bbeee2df9d3e246c4e49c2bd9"><td class="memItemLeft" align="right" valign="top"><a id="a8b6b6c0bbeee2df9d3e246c4e49c2bd9" name="a8b6b6c0bbeee2df9d3e246c4e49c2bd9"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>TWI_CMD_STOP</b>&#160;&#160;&#160;(0b10)</td></tr> +<tr class="separator:a8b6b6c0bbeee2df9d3e246c4e49c2bd9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9770d78d5fa52d94606b1dfb6cefc144" id="r_a9770d78d5fa52d94606b1dfb6cefc144"><td class="memItemLeft" align="right" valign="top"><a id="a9770d78d5fa52d94606b1dfb6cefc144" name="a9770d78d5fa52d94606b1dfb6cefc144"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>TWI_CMD_RTX</b>&#160;&#160;&#160;(0b11)</td></tr> +<tr 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class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a22717887cffff1e6830756bc73140e7b" id="r_a22717887cffff1e6830756bc73140e7b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a22717887cffff1e6830756bc73140e7b">neorv32_twi_enable</a> (void)</td></tr> +<tr class="separator:a22717887cffff1e6830756bc73140e7b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a4fff1ddade320f6cc568c6266f2c2acd" id="r_a4fff1ddade320f6cc568c6266f2c2acd"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4fff1ddade320f6cc568c6266f2c2acd">neorv32_twi_busy</a> (void)</td></tr> +<tr class="separator:a4fff1ddade320f6cc568c6266f2c2acd"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a7735376d26560866b153ed205dfcb2ba" id="r_a7735376d26560866b153ed205dfcb2ba"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7735376d26560866b153ed205dfcb2ba">neorv32_twi_get</a> (uint8_t *data)</td></tr> +<tr class="separator:a7735376d26560866b153ed205dfcb2ba"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac7020f3379602f11c47ca16f1bd82f2e" id="r_ac7020f3379602f11c47ca16f1bd82f2e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac7020f3379602f11c47ca16f1bd82f2e">neorv32_twi_trans</a> (uint8_t *data, int mack)</td></tr> +<tr class="separator:ac7020f3379602f11c47ca16f1bd82f2e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad352447adcccccabd4e20577b34fbece" id="r_ad352447adcccccabd4e20577b34fbece"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad352447adcccccabd4e20577b34fbece">neorv32_twi_generate_stop</a> (void)</td></tr> +<tr class="separator:ad352447adcccccabd4e20577b34fbece"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a633d460e4735eb369d74a834b03c8b78" id="r_a633d460e4735eb369d74a834b03c8b78"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a633d460e4735eb369d74a834b03c8b78">neorv32_twi_generate_start</a> (void)</td></tr> +<tr class="separator:a633d460e4735eb369d74a834b03c8b78"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a28fc44cce5d28f6e8c32268b239b07d5" id="r_a28fc44cce5d28f6e8c32268b239b07d5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a28fc44cce5d28f6e8c32268b239b07d5">neorv32_twi_send_nonblocking</a> (uint8_t data, int mack)</td></tr> +<tr class="separator:a28fc44cce5d28f6e8c32268b239b07d5"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa22430aab0a38d88cbd2c4220c573da0" id="r_aa22430aab0a38d88cbd2c4220c573da0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa22430aab0a38d88cbd2c4220c573da0">neorv32_twi_generate_stop_nonblocking</a> (void)</td></tr> +<tr class="separator:aa22430aab0a38d88cbd2c4220c573da0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adbf2eaed0c76221da5c3091665fc885e" id="r_adbf2eaed0c76221da5c3091665fc885e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adbf2eaed0c76221da5c3091665fc885e">neorv32_twi_generate_start_nonblocking</a> (void)</td></tr> +<tr class="separator:adbf2eaed0c76221da5c3091665fc885e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Two-Wire Interface Controller (TWI)</h2></td></tr> +<tr class="memitem:a2769c2fe5e0de01b12fe4a5fad029768" id="r_a2769c2fe5e0de01b12fe4a5fad029768"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2769c2fe5e0de01b12fe4a5fad029768">NEORV32_TWI</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__twi__t.html">neorv32_twi_t</a>*) (<a class="el" href="neorv32_8h.html#a4a741408a4bb0938e03b99555306db9c">NEORV32_TWI_BASE</a>))</td></tr> +<tr class="separator:a2769c2fe5e0de01b12fe4a5fad029768"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a71ef393d3b34d2dd0698590994b7dafa" id="r_a71ef393d3b34d2dd0698590994b7dafa"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a71ef393d3b34d2dd0698590994b7dafa">NEORV32_TWI_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a71ef393d3b34d2dd0698590994b7dafaa43381fe5ab9fe64ebdf76638eba5a694">TWI_CTRL_EN</a> = 0 +, <a class="el" href="#a71ef393d3b34d2dd0698590994b7dafaa9033ac6cc891bff0da52449aa4b6a8d9">TWI_CTRL_PRSC0</a> = 1 +, <a class="el" href="#a71ef393d3b34d2dd0698590994b7dafaa8b666cd2e40ca9ba3f9a635f0ed107df">TWI_CTRL_PRSC1</a> = 2 +, <a class="el" href="#a71ef393d3b34d2dd0698590994b7dafaa4d55ed983ca2f94fa9deac196d949b31">TWI_CTRL_PRSC2</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#a71ef393d3b34d2dd0698590994b7dafaa75d3a61b5e642e5d5c1f699c35c26b31">TWI_CTRL_CDIV0</a> = 4 +, <a class="el" href="#a71ef393d3b34d2dd0698590994b7dafaa4473769463a0c7e4b58ed0b983610674">TWI_CTRL_CDIV1</a> = 5 +, <a class="el" href="#a71ef393d3b34d2dd0698590994b7dafaaa6db454861ad5be70846ed4f9eb2ea12">TWI_CTRL_CDIV2</a> = 6 +, <a class="el" href="#a71ef393d3b34d2dd0698590994b7dafaa99e2153a53cc1f9d7cc83d52c698cbcc">TWI_CTRL_CDIV3</a> = 7 +, <br /> +&#160;&#160;<a class="el" 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&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3421852c63baca60fe58c990b1c653d8">NEORV32_TWI_DCMD_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a3421852c63baca60fe58c990b1c653d8adf6176c87655bbbb5c7cea9dea29ce56">TWI_DCMD_LSB</a> = 0 +, <a class="el" href="#a3421852c63baca60fe58c990b1c653d8ab7f53f7cef06031c1a34db04c602a50d">TWI_DCMD_MSB</a> = 7 +, <a class="el" href="#a3421852c63baca60fe58c990b1c653d8af64359afd3627db0a79733d00128f3a5">TWI_DCMD_ACK</a> = 8 +, <a class="el" href="#a3421852c63baca60fe58c990b1c653d8ab2e20f7f5a5b131c31772341caa97e5e">TWI_DCMD_CMD_LO</a> = 9 +, <br /> +&#160;&#160;<a class="el" href="#a3421852c63baca60fe58c990b1c653d8accd7e8be435db3055c27f0a6d5e0201e">TWI_DCMD_CMD_HI</a> = 10 +<br /> + }</td></tr> +<tr class="separator:a3421852c63baca60fe58c990b1c653d8"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Two-Wire Interface Controller (TWI) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the TWI unit was synthesized (IO_TWI_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a2769c2fe5e0de01b12fe4a5fad029768" name="a2769c2fe5e0de01b12fe4a5fad029768"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2769c2fe5e0de01b12fe4a5fad029768">&#9670;&#160;</a></span>NEORV32_TWI</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_TWI&#160;&#160;&#160;((<a class="el" href="structneorv32__twi__t.html">neorv32_twi_t</a>*) (<a class="el" href="neorv32_8h.html#a4a741408a4bb0938e03b99555306db9c">NEORV32_TWI_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>TWI module hardware access (<a class="el" href="structneorv32__twi__t.html">neorv32_twi_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a71ef393d3b34d2dd0698590994b7dafa" name="a71ef393d3b34d2dd0698590994b7dafa"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a71ef393d3b34d2dd0698590994b7dafa">&#9670;&#160;</a></span>NEORV32_TWI_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a71ef393d3b34d2dd0698590994b7dafa">NEORV32_TWI_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>TWI control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa43381fe5ab9fe64ebdf76638eba5a694" name="a71ef393d3b34d2dd0698590994b7dafaa43381fe5ab9fe64ebdf76638eba5a694"></a>TWI_CTRL_EN&#160;</td><td class="fielddoc"><p>TWI control register(0) (r/w): TWI enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa9033ac6cc891bff0da52449aa4b6a8d9" name="a71ef393d3b34d2dd0698590994b7dafaa9033ac6cc891bff0da52449aa4b6a8d9"></a>TWI_CTRL_PRSC0&#160;</td><td class="fielddoc"><p>TWI control register(1) (r/w): Clock prescaler select bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa8b666cd2e40ca9ba3f9a635f0ed107df" name="a71ef393d3b34d2dd0698590994b7dafaa8b666cd2e40ca9ba3f9a635f0ed107df"></a>TWI_CTRL_PRSC1&#160;</td><td class="fielddoc"><p>TWI control register(2) (r/w): Clock prescaler select bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa4d55ed983ca2f94fa9deac196d949b31" name="a71ef393d3b34d2dd0698590994b7dafaa4d55ed983ca2f94fa9deac196d949b31"></a>TWI_CTRL_PRSC2&#160;</td><td class="fielddoc"><p>TWI control register(3) (r/w): Clock prescaler select bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa75d3a61b5e642e5d5c1f699c35c26b31" name="a71ef393d3b34d2dd0698590994b7dafaa75d3a61b5e642e5d5c1f699c35c26b31"></a>TWI_CTRL_CDIV0&#160;</td><td class="fielddoc"><p>TWI control register(4) (r/w): Clock divider bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa4473769463a0c7e4b58ed0b983610674" name="a71ef393d3b34d2dd0698590994b7dafaa4473769463a0c7e4b58ed0b983610674"></a>TWI_CTRL_CDIV1&#160;</td><td class="fielddoc"><p>TWI control register(5) (r/w): Clock divider bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaaa6db454861ad5be70846ed4f9eb2ea12" name="a71ef393d3b34d2dd0698590994b7dafaaa6db454861ad5be70846ed4f9eb2ea12"></a>TWI_CTRL_CDIV2&#160;</td><td class="fielddoc"><p>TWI control register(6) (r/w): Clock divider bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa99e2153a53cc1f9d7cc83d52c698cbcc" name="a71ef393d3b34d2dd0698590994b7dafaa99e2153a53cc1f9d7cc83d52c698cbcc"></a>TWI_CTRL_CDIV3&#160;</td><td class="fielddoc"><p>TWI control register(7) (r/w): Clock divider bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaac62d6e3c47a8195a6a9ccc79129bfe48" name="a71ef393d3b34d2dd0698590994b7dafaac62d6e3c47a8195a6a9ccc79129bfe48"></a>TWI_CTRL_CLKSTR&#160;</td><td class="fielddoc"><p>TWI control register(8) (r/w): Enable/allow clock stretching </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa74126d424719b1db61f5e1ab567489fb" name="a71ef393d3b34d2dd0698590994b7dafaa74126d424719b1db61f5e1ab567489fb"></a>TWI_CTRL_FIFO_LSB&#160;</td><td class="fielddoc"><p>SPI control register(15) (r/-): log2(FIFO size), lsb </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa183f5b9c3993d04cc9aea2a79e9a4f75" name="a71ef393d3b34d2dd0698590994b7dafaa183f5b9c3993d04cc9aea2a79e9a4f75"></a>TWI_CTRL_FIFO_MSB&#160;</td><td class="fielddoc"><p>SPI control register(18) (r/-): log2(FIFO size), msb </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaaa0597dc9dea3f6f7a2f19dbcc7a2dabb" name="a71ef393d3b34d2dd0698590994b7dafaaa0597dc9dea3f6f7a2f19dbcc7a2dabb"></a>TWI_CTRL_TX_FULL&#160;</td><td class="fielddoc"><p>TWI control register(29) (r/-): TX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaad2798dfabf3a72e6138135e983734671" name="a71ef393d3b34d2dd0698590994b7dafaad2798dfabf3a72e6138135e983734671"></a>TWI_CTRL_RX_AVAIL&#160;</td><td class="fielddoc"><p>TWI control register(30) (r/-): RX FIFO data available </p> +</td></tr> +<tr><td class="fieldname"><a id="a71ef393d3b34d2dd0698590994b7dafaa443a2a65ee810f428d40a4f8474d8e6d" name="a71ef393d3b34d2dd0698590994b7dafaa443a2a65ee810f428d40a4f8474d8e6d"></a>TWI_CTRL_BUSY&#160;</td><td class="fielddoc"><p>TWI control register(31) (r/-): Bus engine busy or TX FIFO not empty </p> +</td></tr> +</table> + +</div> +</div> +<a id="a3421852c63baca60fe58c990b1c653d8" name="a3421852c63baca60fe58c990b1c653d8"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3421852c63baca60fe58c990b1c653d8">&#9670;&#160;</a></span>NEORV32_TWI_DCMD_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a3421852c63baca60fe58c990b1c653d8">NEORV32_TWI_DCMD_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>TWI command/data register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a3421852c63baca60fe58c990b1c653d8adf6176c87655bbbb5c7cea9dea29ce56" name="a3421852c63baca60fe58c990b1c653d8adf6176c87655bbbb5c7cea9dea29ce56"></a>TWI_DCMD_LSB&#160;</td><td class="fielddoc"><p>TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a3421852c63baca60fe58c990b1c653d8ab7f53f7cef06031c1a34db04c602a50d" name="a3421852c63baca60fe58c990b1c653d8ab7f53f7cef06031c1a34db04c602a50d"></a>TWI_DCMD_MSB&#160;</td><td class="fielddoc"><p>TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a3421852c63baca60fe58c990b1c653d8af64359afd3627db0a79733d00128f3a5" name="a3421852c63baca60fe58c990b1c653d8af64359afd3627db0a79733d00128f3a5"></a>TWI_DCMD_ACK&#160;</td><td class="fielddoc"><p>TWI data register(8) (r/w): RX = ACK/NACK, TX = MACK </p> +</td></tr> +<tr><td class="fieldname"><a id="a3421852c63baca60fe58c990b1c653d8ab2e20f7f5a5b131c31772341caa97e5e" name="a3421852c63baca60fe58c990b1c653d8ab2e20f7f5a5b131c31772341caa97e5e"></a>TWI_DCMD_CMD_LO&#160;</td><td class="fielddoc"><p>TWI data register(9) (r/w): CMD lsb </p> +</td></tr> +<tr><td class="fieldname"><a id="a3421852c63baca60fe58c990b1c653d8accd7e8be435db3055c27f0a6d5e0201e" name="a3421852c63baca60fe58c990b1c653d8accd7e8be435db3055c27f0a6d5e0201e"></a>TWI_DCMD_CMD_HI&#160;</td><td class="fielddoc"><p>TWI data register(10) (r/w): CMD msb </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="aa2e01ebbc0c82d65ed4ded351f4d8711" name="aa2e01ebbc0c82d65ed4ded351f4d8711"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa2e01ebbc0c82d65ed4ded351f4d8711">&#9670;&#160;</a></span>neorv32_twi_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if TWI unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if TWI was not synthesized, 1 if TWI is available. </dd></dl> + +</div> +</div> +<a id="a4fff1ddade320f6cc568c6266f2c2acd" name="a4fff1ddade320f6cc568c6266f2c2acd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4fff1ddade320f6cc568c6266f2c2acd">&#9670;&#160;</a></span>neorv32_twi_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_busy </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if TWI is busy (TWI bus engine busy or TX FIFO not empty).</p> +<dl class="section return"><dt>Returns</dt><dd>0 if idle, 1 if busy </dd></dl> + +</div> +</div> +<a id="ae5f31e737c7a6c3c86070ff34cb0d861" name="ae5f31e737c7a6c3c86070ff34cb0d861"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae5f31e737c7a6c3c86070ff34cb0d861">&#9670;&#160;</a></span>neorv32_twi_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable TWI controller. </p> + +</div> +</div> +<a id="a22717887cffff1e6830756bc73140e7b" name="a22717887cffff1e6830756bc73140e7b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a22717887cffff1e6830756bc73140e7b">&#9670;&#160;</a></span>neorv32_twi_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable TWI controller. </p> + +</div> +</div> +<a id="a633d460e4735eb369d74a834b03c8b78" name="a633d460e4735eb369d74a834b03c8b78"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a633d460e4735eb369d74a834b03c8b78">&#9670;&#160;</a></span>neorv32_twi_generate_start()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_generate_start </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate START (or REPEATED-START) condition.</p> +<dl class="section note"><dt>Note</dt><dd>Blocking function. </dd></dl> + +</div> +</div> +<a id="adbf2eaed0c76221da5c3091665fc885e" name="adbf2eaed0c76221da5c3091665fc885e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adbf2eaed0c76221da5c3091665fc885e">&#9670;&#160;</a></span>neorv32_twi_generate_start_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_generate_start_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate START (or REPEATED-START) condition.</p> +<dl class="section note"><dt>Note</dt><dd>Non-blocking function; does not check the TX FIFO. </dd></dl> + +</div> +</div> +<a id="ad352447adcccccabd4e20577b34fbece" name="ad352447adcccccabd4e20577b34fbece"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad352447adcccccabd4e20577b34fbece">&#9670;&#160;</a></span>neorv32_twi_generate_stop()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_generate_stop </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate STOP condition.</p> +<dl class="section note"><dt>Note</dt><dd>Blocking function. </dd></dl> + +</div> +</div> +<a id="aa22430aab0a38d88cbd2c4220c573da0" name="aa22430aab0a38d88cbd2c4220c573da0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa22430aab0a38d88cbd2c4220c573da0">&#9670;&#160;</a></span>neorv32_twi_generate_stop_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_generate_stop_nonblocking </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Generate STOP condition.</p> +<dl class="section note"><dt>Note</dt><dd>Non-blocking function; does not check the TX FIFO. </dd></dl> + +</div> +</div> +<a id="a7735376d26560866b153ed205dfcb2ba" name="a7735376d26560866b153ed205dfcb2ba"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7735376d26560866b153ed205dfcb2ba">&#9670;&#160;</a></span>neorv32_twi_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_get </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>data</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get received data + ACK/NACH from RX FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">data</td><td>Pointer for returned data (uint8_t). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>RX FIFO access status (-1 = no data available, 0 = ACK received, 1 = NACK received). </dd></dl> + +</div> +</div> +<a id="a2c8f3bc55f4a9a8bdcb111759cf56ae2" name="a2c8f3bc55f4a9a8bdcb111759cf56ae2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2c8f3bc55f4a9a8bdcb111759cf56ae2">&#9670;&#160;</a></span>neorv32_twi_get_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_get_fifo_depth </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get TWI FIFO depth.</p> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries), zero if no FIFO implemented </dd></dl> + +</div> +</div> +<a id="a28fc44cce5d28f6e8c32268b239b07d5" name="a28fc44cce5d28f6e8c32268b239b07d5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a28fc44cce5d28f6e8c32268b239b07d5">&#9670;&#160;</a></span>neorv32_twi_send_nonblocking()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_send_nonblocking </td> + <td>(</td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>data</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>mack</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send data byte (RX can be read via <a class="el" href="neorv32__twi_8c.html#a7735376d26560866b153ed205dfcb2ba">neorv32_twi_get()</a>).</p> +<dl class="section note"><dt>Note</dt><dd>Non-blocking function; does not check the TX FIFO.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">data</td><td>Data byte to be send. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">mack</td><td>Generate ACK by host controller when set. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a7ea6f3509a7cf622234d4b83e33afbe3" name="a7ea6f3509a7cf622234d4b83e33afbe3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7ea6f3509a7cf622234d4b83e33afbe3">&#9670;&#160;</a></span>neorv32_twi_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_twi_setup </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cdiv</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>clkstr</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable and configure TWI controller. The TWI control register bits are listed in <a class="el" href="#a71ef393d3b34d2dd0698590994b7dafa">NEORV32_TWI_CTRL_enum</a>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>Clock prescaler select (0..7). See <a class="el" href="neorv32_8h.html#a10022df4c223533b04d5aebe222e8b73">NEORV32_CLOCK_PRSC_enum</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cdiv</td><td>Clock divider (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">clkstr</td><td>Enable (allow) clock stretching. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac7020f3379602f11c47ca16f1bd82f2e" name="ac7020f3379602f11c47ca16f1bd82f2e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac7020f3379602f11c47ca16f1bd82f2e">&#9670;&#160;</a></span>neorv32_twi_trans()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_twi_trans </td> + <td>(</td> + <td class="paramtype">uint8_t *</td> <td class="paramname"><span class="paramname"><em>data</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>mack</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>TWI transfer: send data byte and also receive data byte.</p> +<dl class="section note"><dt>Note</dt><dd>Blocking function.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">data</td><td>Pointer for TX/RX data (uint8_t). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">mack</td><td>Generate ACK by host controller when set. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0: ACK received, 1: NACK received. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__twi_8h_source.html b/sw/neorv32__twi_8h_source.html new file mode 100644 index 000000000..be1ff67cf --- /dev/null +++ b/sw/neorv32__twi_8h_source.html @@ -0,0 +1,215 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_twi.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_twi_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_twi_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__twi__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__twi__t.html#a148a1c681a2632881b25ee41652b5304"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__twi__t.html#a148a1c681a2632881b25ee41652b5304">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__twi__t.html#ae311e0827bdb178c6dd8c4535b80d5cb"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__twi__t.html#ae311e0827bdb178c6dd8c4535b80d5cb">DCMD</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__twi__t.html">neorv32_twi_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a2769c2fe5e0de01b12fe4a5fad029768"> 35</a></span><span class="preprocessor">#define NEORV32_TWI ((neorv32_twi_t*) (NEORV32_TWI_BASE))</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="foldopen" id="foldopen00038" data-start="{" data-end="};"> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafa"> 38</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafa">NEORV32_TWI_CTRL_enum</a> {</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa43381fe5ab9fe64ebdf76638eba5a694"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa43381fe5ab9fe64ebdf76638eba5a694">TWI_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa9033ac6cc891bff0da52449aa4b6a8d9"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa9033ac6cc891bff0da52449aa4b6a8d9">TWI_CTRL_PRSC0</a> = 1, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa8b666cd2e40ca9ba3f9a635f0ed107df"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa8b666cd2e40ca9ba3f9a635f0ed107df">TWI_CTRL_PRSC1</a> = 2, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa4d55ed983ca2f94fa9deac196d949b31"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa4d55ed983ca2f94fa9deac196d949b31">TWI_CTRL_PRSC2</a> = 3, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa75d3a61b5e642e5d5c1f699c35c26b31"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa75d3a61b5e642e5d5c1f699c35c26b31">TWI_CTRL_CDIV0</a> = 4, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa4473769463a0c7e4b58ed0b983610674"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa4473769463a0c7e4b58ed0b983610674">TWI_CTRL_CDIV1</a> = 5, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaaa6db454861ad5be70846ed4f9eb2ea12"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaaa6db454861ad5be70846ed4f9eb2ea12">TWI_CTRL_CDIV2</a> = 6, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa99e2153a53cc1f9d7cc83d52c698cbcc"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa99e2153a53cc1f9d7cc83d52c698cbcc">TWI_CTRL_CDIV3</a> = 7, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaac62d6e3c47a8195a6a9ccc79129bfe48"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaac62d6e3c47a8195a6a9ccc79129bfe48">TWI_CTRL_CLKSTR</a> = 8, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa74126d424719b1db61f5e1ab567489fb"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa74126d424719b1db61f5e1ab567489fb">TWI_CTRL_FIFO_LSB</a> = 15, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa183f5b9c3993d04cc9aea2a79e9a4f75"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa183f5b9c3993d04cc9aea2a79e9a4f75">TWI_CTRL_FIFO_MSB</a> = 18, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaaa0597dc9dea3f6f7a2f19dbcc7a2dabb"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaaa0597dc9dea3f6f7a2f19dbcc7a2dabb">TWI_CTRL_TX_FULL</a> = 29, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaad2798dfabf3a72e6138135e983734671"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaad2798dfabf3a72e6138135e983734671">TWI_CTRL_RX_AVAIL</a> = 30, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa443a2a65ee810f428d40a4f8474d8e6d">TWI_CTRL_BUSY</a> = 31 </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa443a2a65ee810f428d40a4f8474d8e6d"> 55</a></span>};</div> +</div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> </div> +<div class="foldopen" id="foldopen00058" data-start="{" data-end="};"> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8"> 58</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8">NEORV32_TWI_DCMD_enum</a> {</div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8adf6176c87655bbbb5c7cea9dea29ce56"> 59</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8adf6176c87655bbbb5c7cea9dea29ce56">TWI_DCMD_LSB</a> = 0, </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8ab7f53f7cef06031c1a34db04c602a50d"> 60</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8ab7f53f7cef06031c1a34db04c602a50d">TWI_DCMD_MSB</a> = 7, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8af64359afd3627db0a79733d00128f3a5"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8af64359afd3627db0a79733d00128f3a5">TWI_DCMD_ACK</a> = 8, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8ab2e20f7f5a5b131c31772341caa97e5e"> 62</a></span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8ab2e20f7f5a5b131c31772341caa97e5e">TWI_DCMD_CMD_LO</a> = 9, </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span> <a class="code hl_enumvalue" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8accd7e8be435db3055c27f0a6d5e0201e">TWI_DCMD_CMD_HI</a> = 10 </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8accd7e8be435db3055c27f0a6d5e0201e"> 64</a></span>};</div> +</div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="preprocessor">#define TWI_CMD_NOP (0b00) </span><span class="comment">// no operation</span></div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="preprocessor">#define TWI_CMD_START (0b01) </span><span class="comment">// generate start condition</span></div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="preprocessor">#define TWI_CMD_STOP (0b10) </span><span class="comment">// generate stop condition</span></div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="preprocessor">#define TWI_CMD_RTX (0b11) </span><span class="comment">// transmit+receive data byte</span></div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="comment">/**********************************************************************/</span><span class="preprocessor"></span></div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__twi_8h.html#aa2e01ebbc0c82d65ed4ded351f4d8711">neorv32_twi_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__twi_8h.html#a7ea6f3509a7cf622234d4b83e33afbe3">neorv32_twi_setup</a>(<span class="keywordtype">int</span> prsc, <span class="keywordtype">int</span> cdiv, <span class="keywordtype">int</span> clkstr);</div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__twi_8h.html#a2c8f3bc55f4a9a8bdcb111759cf56ae2">neorv32_twi_get_fifo_depth</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__twi_8h.html#ae5f31e737c7a6c3c86070ff34cb0d861">neorv32_twi_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__twi_8h.html#a22717887cffff1e6830756bc73140e7b">neorv32_twi_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span> </div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__twi_8h.html#a4fff1ddade320f6cc568c6266f2c2acd">neorv32_twi_busy</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__twi_8h.html#a7735376d26560866b153ed205dfcb2ba">neorv32_twi_get</a>(uint8_t *data);</div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span> </div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__twi_8h.html#ac7020f3379602f11c47ca16f1bd82f2e">neorv32_twi_trans</a>(uint8_t *data, <span class="keywordtype">int</span> mack);</div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__twi_8h.html#ad352447adcccccabd4e20577b34fbece">neorv32_twi_generate_stop</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__twi_8h.html#a633d460e4735eb369d74a834b03c8b78">neorv32_twi_generate_start</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span> </div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__twi_8h.html#a28fc44cce5d28f6e8c32268b239b07d5">neorv32_twi_send_nonblocking</a>(uint8_t data, <span class="keywordtype">int</span> mack);</div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__twi_8h.html#aa22430aab0a38d88cbd2c4220c573da0">neorv32_twi_generate_stop_nonblocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__twi_8h.html#adbf2eaed0c76221da5c3091665fc885e">neorv32_twi_generate_start_nonblocking</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_twi_h</span></div> +<div class="ttc" id="aneorv32__twi_8h_html_a22717887cffff1e6830756bc73140e7b"><div class="ttname"><a href="neorv32__twi_8h.html#a22717887cffff1e6830756bc73140e7b">neorv32_twi_enable</a></div><div class="ttdeci">void neorv32_twi_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:81</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a28fc44cce5d28f6e8c32268b239b07d5"><div class="ttname"><a href="neorv32__twi_8h.html#a28fc44cce5d28f6e8c32268b239b07d5">neorv32_twi_send_nonblocking</a></div><div class="ttdeci">void neorv32_twi_send_nonblocking(uint8_t data, int mack)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:182</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a2c8f3bc55f4a9a8bdcb111759cf56ae2"><div class="ttname"><a href="neorv32__twi_8h.html#a2c8f3bc55f4a9a8bdcb111759cf56ae2">neorv32_twi_get_fifo_depth</a></div><div class="ttdeci">int neorv32_twi_get_fifo_depth(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:62</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a3421852c63baca60fe58c990b1c653d8"><div class="ttname"><a href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8">NEORV32_TWI_DCMD_enum</a></div><div class="ttdeci">NEORV32_TWI_DCMD_enum</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:58</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a3421852c63baca60fe58c990b1c653d8ab2e20f7f5a5b131c31772341caa97e5e"><div class="ttname"><a href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8ab2e20f7f5a5b131c31772341caa97e5e">TWI_DCMD_CMD_LO</a></div><div class="ttdeci">@ TWI_DCMD_CMD_LO</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:62</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a3421852c63baca60fe58c990b1c653d8ab7f53f7cef06031c1a34db04c602a50d"><div class="ttname"><a href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8ab7f53f7cef06031c1a34db04c602a50d">TWI_DCMD_MSB</a></div><div class="ttdeci">@ TWI_DCMD_MSB</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:60</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a3421852c63baca60fe58c990b1c653d8accd7e8be435db3055c27f0a6d5e0201e"><div class="ttname"><a href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8accd7e8be435db3055c27f0a6d5e0201e">TWI_DCMD_CMD_HI</a></div><div class="ttdeci">@ TWI_DCMD_CMD_HI</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:63</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a3421852c63baca60fe58c990b1c653d8adf6176c87655bbbb5c7cea9dea29ce56"><div class="ttname"><a href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8adf6176c87655bbbb5c7cea9dea29ce56">TWI_DCMD_LSB</a></div><div class="ttdeci">@ TWI_DCMD_LSB</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:59</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a3421852c63baca60fe58c990b1c653d8af64359afd3627db0a79733d00128f3a5"><div class="ttname"><a href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8af64359afd3627db0a79733d00128f3a5">TWI_DCMD_ACK</a></div><div class="ttdeci">@ TWI_DCMD_ACK</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:61</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a4fff1ddade320f6cc568c6266f2c2acd"><div class="ttname"><a href="neorv32__twi_8h.html#a4fff1ddade320f6cc568c6266f2c2acd">neorv32_twi_busy</a></div><div class="ttdeci">int neorv32_twi_busy(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:92</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a633d460e4735eb369d74a834b03c8b78"><div class="ttname"><a href="neorv32__twi_8h.html#a633d460e4735eb369d74a834b03c8b78">neorv32_twi_generate_start</a></div><div class="ttdeci">void neorv32_twi_generate_start(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:166</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafa"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafa">NEORV32_TWI_CTRL_enum</a></div><div class="ttdeci">NEORV32_TWI_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:38</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa183f5b9c3993d04cc9aea2a79e9a4f75"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa183f5b9c3993d04cc9aea2a79e9a4f75">TWI_CTRL_FIFO_MSB</a></div><div class="ttdeci">@ TWI_CTRL_FIFO_MSB</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:50</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa43381fe5ab9fe64ebdf76638eba5a694"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa43381fe5ab9fe64ebdf76638eba5a694">TWI_CTRL_EN</a></div><div class="ttdeci">@ TWI_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:39</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa443a2a65ee810f428d40a4f8474d8e6d"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa443a2a65ee810f428d40a4f8474d8e6d">TWI_CTRL_BUSY</a></div><div class="ttdeci">@ TWI_CTRL_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:54</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa4473769463a0c7e4b58ed0b983610674"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa4473769463a0c7e4b58ed0b983610674">TWI_CTRL_CDIV1</a></div><div class="ttdeci">@ TWI_CTRL_CDIV1</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:44</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa4d55ed983ca2f94fa9deac196d949b31"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa4d55ed983ca2f94fa9deac196d949b31">TWI_CTRL_PRSC2</a></div><div class="ttdeci">@ TWI_CTRL_PRSC2</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:42</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa74126d424719b1db61f5e1ab567489fb"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa74126d424719b1db61f5e1ab567489fb">TWI_CTRL_FIFO_LSB</a></div><div class="ttdeci">@ TWI_CTRL_FIFO_LSB</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:49</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa75d3a61b5e642e5d5c1f699c35c26b31"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa75d3a61b5e642e5d5c1f699c35c26b31">TWI_CTRL_CDIV0</a></div><div class="ttdeci">@ TWI_CTRL_CDIV0</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:43</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa8b666cd2e40ca9ba3f9a635f0ed107df"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa8b666cd2e40ca9ba3f9a635f0ed107df">TWI_CTRL_PRSC1</a></div><div class="ttdeci">@ TWI_CTRL_PRSC1</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:41</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa9033ac6cc891bff0da52449aa4b6a8d9"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa9033ac6cc891bff0da52449aa4b6a8d9">TWI_CTRL_PRSC0</a></div><div class="ttdeci">@ TWI_CTRL_PRSC0</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:40</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaa99e2153a53cc1f9d7cc83d52c698cbcc"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaa99e2153a53cc1f9d7cc83d52c698cbcc">TWI_CTRL_CDIV3</a></div><div class="ttdeci">@ TWI_CTRL_CDIV3</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:46</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaaa0597dc9dea3f6f7a2f19dbcc7a2dabb"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaaa0597dc9dea3f6f7a2f19dbcc7a2dabb">TWI_CTRL_TX_FULL</a></div><div class="ttdeci">@ TWI_CTRL_TX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:52</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaaa6db454861ad5be70846ed4f9eb2ea12"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaaa6db454861ad5be70846ed4f9eb2ea12">TWI_CTRL_CDIV2</a></div><div class="ttdeci">@ TWI_CTRL_CDIV2</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:45</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaac62d6e3c47a8195a6a9ccc79129bfe48"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaac62d6e3c47a8195a6a9ccc79129bfe48">TWI_CTRL_CLKSTR</a></div><div class="ttdeci">@ TWI_CTRL_CLKSTR</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:47</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a71ef393d3b34d2dd0698590994b7dafaad2798dfabf3a72e6138135e983734671"><div class="ttname"><a href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafaad2798dfabf3a72e6138135e983734671">TWI_CTRL_RX_AVAIL</a></div><div class="ttdeci">@ TWI_CTRL_RX_AVAIL</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:53</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a7735376d26560866b153ed205dfcb2ba"><div class="ttname"><a href="neorv32__twi_8h.html#a7735376d26560866b153ed205dfcb2ba">neorv32_twi_get</a></div><div class="ttdeci">int neorv32_twi_get(uint8_t *data)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:109</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_a7ea6f3509a7cf622234d4b83e33afbe3"><div class="ttname"><a href="neorv32__twi_8h.html#a7ea6f3509a7cf622234d4b83e33afbe3">neorv32_twi_setup</a></div><div class="ttdeci">void neorv32_twi_setup(int prsc, int cdiv, int clkstr)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:44</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_aa22430aab0a38d88cbd2c4220c573da0"><div class="ttname"><a href="neorv32__twi_8h.html#aa22430aab0a38d88cbd2c4220c573da0">neorv32_twi_generate_stop_nonblocking</a></div><div class="ttdeci">void neorv32_twi_generate_stop_nonblocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:196</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_aa2e01ebbc0c82d65ed4ded351f4d8711"><div class="ttname"><a href="neorv32__twi_8h.html#aa2e01ebbc0c82d65ed4ded351f4d8711">neorv32_twi_available</a></div><div class="ttdeci">int neorv32_twi_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:26</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_ac7020f3379602f11c47ca16f1bd82f2e"><div class="ttname"><a href="neorv32__twi_8h.html#ac7020f3379602f11c47ca16f1bd82f2e">neorv32_twi_trans</a></div><div class="ttdeci">int neorv32_twi_trans(uint8_t *data, int mack)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:130</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_ad352447adcccccabd4e20577b34fbece"><div class="ttname"><a href="neorv32__twi_8h.html#ad352447adcccccabd4e20577b34fbece">neorv32_twi_generate_stop</a></div><div class="ttdeci">void neorv32_twi_generate_stop(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:153</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_adbf2eaed0c76221da5c3091665fc885e"><div class="ttname"><a href="neorv32__twi_8h.html#adbf2eaed0c76221da5c3091665fc885e">neorv32_twi_generate_start_nonblocking</a></div><div class="ttdeci">void neorv32_twi_generate_start_nonblocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:207</div></div> +<div class="ttc" id="aneorv32__twi_8h_html_ae5f31e737c7a6c3c86070ff34cb0d861"><div class="ttname"><a href="neorv32__twi_8h.html#ae5f31e737c7a6c3c86070ff34cb0d861">neorv32_twi_disable</a></div><div class="ttdeci">void neorv32_twi_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_twi.c:72</div></div> +<div class="ttc" id="astructneorv32__twi__t_html"><div class="ttname"><a href="structneorv32__twi__t.html">neorv32_twi_t</a></div><div class="ttdef"><b>Definition</b> neorv32_twi.h:29</div></div> +<div class="ttc" id="astructneorv32__twi__t_html_a148a1c681a2632881b25ee41652b5304"><div class="ttname"><a href="structneorv32__twi__t.html#a148a1c681a2632881b25ee41652b5304">neorv32_twi_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:30</div></div> +<div class="ttc" id="astructneorv32__twi__t_html_ae311e0827bdb178c6dd8c4535b80d5cb"><div class="ttname"><a href="structneorv32__twi__t.html#ae311e0827bdb178c6dd8c4535b80d5cb">neorv32_twi_t::DCMD</a></div><div class="ttdeci">uint32_t DCMD</div><div class="ttdef"><b>Definition</b> neorv32_twi.h:31</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" 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href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_uart.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Universal asynchronous receiver/transmitter (UART0/UART1) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +<code>#include &lt;stdarg.h&gt;</code><br /> +<code>#include &lt;ctype.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:abef6415b0391dc055713404312196682" id="r_abef6415b0391dc055713404312196682"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abef6415b0391dc055713404312196682">neorv32_uart_available</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:abef6415b0391dc055713404312196682"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9cdec36f2723c5373664022d1b68b841" id="r_a9cdec36f2723c5373664022d1b68b841"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9cdec36f2723c5373664022d1b68b841">neorv32_uart_setup</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, uint32_t baudrate, uint32_t irq_mask)</td></tr> +<tr class="separator:a9cdec36f2723c5373664022d1b68b841"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af85fb929c912d3edef3d86ffa833982a" id="r_af85fb929c912d3edef3d86ffa833982a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af85fb929c912d3edef3d86ffa833982a">neorv32_uart_get_rx_fifo_depth</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:af85fb929c912d3edef3d86ffa833982a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a031e3e27c8783c299623468020a22b0e" id="r_a031e3e27c8783c299623468020a22b0e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a031e3e27c8783c299623468020a22b0e">neorv32_uart_get_tx_fifo_depth</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:a031e3e27c8783c299623468020a22b0e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afa0533e81d53057c36f4997a2dbbe2bc" id="r_afa0533e81d53057c36f4997a2dbbe2bc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afa0533e81d53057c36f4997a2dbbe2bc">neorv32_uart_enable</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:afa0533e81d53057c36f4997a2dbbe2bc"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae18804ccd29ec2fd1cc06e9ce985b704" id="r_ae18804ccd29ec2fd1cc06e9ce985b704"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae18804ccd29ec2fd1cc06e9ce985b704">neorv32_uart_disable</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:ae18804ccd29ec2fd1cc06e9ce985b704"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a734b610f4cd1b474d7763f9700a715ec" id="r_a734b610f4cd1b474d7763f9700a715ec"><td class="memItemLeft" align="right" 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valign="bottom"><a class="el" href="#aa490df3a9bb2aa3215fa6fad34ffe7d1">neorv32_uart_char_received_get</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:aa490df3a9bb2aa3215fa6fad34ffe7d1"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a45a07d5e71677162baaa1025759c67a2" id="r_a45a07d5e71677162baaa1025759c67a2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a45a07d5e71677162baaa1025759c67a2">neorv32_uart_puts</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, const char *s)</td></tr> +<tr class="separator:a45a07d5e71677162baaa1025759c67a2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8714cdb1c04d94bec322c6215ea10238" id="r_a8714cdb1c04d94bec322c6215ea10238"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8714cdb1c04d94bec322c6215ea10238">neorv32_uart_vprintf</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, const char *format, va_list args)</td></tr> +<tr class="separator:a8714cdb1c04d94bec322c6215ea10238"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ab8c1f9f451def9126ab2749d7bbe50d9" id="r_ab8c1f9f451def9126ab2749d7bbe50d9"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab8c1f9f451def9126ab2749d7bbe50d9">neorv32_uart_printf</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, const char *format,...)</td></tr> +<tr class="separator:ab8c1f9f451def9126ab2749d7bbe50d9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac429964878bd6deab61d9ed8659bca75" id="r_ac429964878bd6deab61d9ed8659bca75"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac429964878bd6deab61d9ed8659bca75">neorv32_uart_scan</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, char *buffer, int max_size, int echo)</td></tr> +<tr class="separator:ac429964878bd6deab61d9ed8659bca75"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Universal asynchronous receiver/transmitter (UART0/UART1) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the UART0/UART1 unit was synthesized.</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="abef6415b0391dc055713404312196682" name="abef6415b0391dc055713404312196682"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abef6415b0391dc055713404312196682">&#9670;&#160;</a></span>neorv32_uart_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_available </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if UART unit was synthesized.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">Hardware</td><td>handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if UART0/1 was not synthesized, 1 if UART0/1 is available. </dd></dl> + +</div> +</div> +<a id="adedb0e07efb232717534017167a5be98" name="adedb0e07efb232717534017167a5be98"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adedb0e07efb232717534017167a5be98">&#9670;&#160;</a></span>neorv32_uart_char_received()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_char_received </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if UART has received a char.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd> +<dd> +Use neorv32_uart_char_received_get(void) to get the char.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>1 when a char has been received, 0 otherwise. </dd></dl> + +</div> +</div> +<a id="aa490df3a9bb2aa3215fa6fad34ffe7d1" name="aa490df3a9bb2aa3215fa6fad34ffe7d1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa490df3a9bb2aa3215fa6fad34ffe7d1">&#9670;&#160;</a></span>neorv32_uart_char_received_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">char neorv32_uart_char_received_get </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get a received char from UART.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd> +<dd> +Should only be used in combination with neorv32_uart_char_received(void).</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Received char. </dd></dl> + +</div> +</div> +<a id="ae18804ccd29ec2fd1cc06e9ce985b704" name="ae18804ccd29ec2fd1cc06e9ce985b704"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae18804ccd29ec2fd1cc06e9ce985b704">&#9670;&#160;</a></span>neorv32_uart_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_disable </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="afa0533e81d53057c36f4997a2dbbe2bc" name="afa0533e81d53057c36f4997a2dbbe2bc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afa0533e81d53057c36f4997a2dbbe2bc">&#9670;&#160;</a></span>neorv32_uart_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_enable </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="af85fb929c912d3edef3d86ffa833982a" name="af85fb929c912d3edef3d86ffa833982a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af85fb929c912d3edef3d86ffa833982a">&#9670;&#160;</a></span>neorv32_uart_get_rx_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_get_rx_fifo_depth </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get UART RX FIFO depth.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries) </dd></dl> + +</div> +</div> +<a id="a031e3e27c8783c299623468020a22b0e" name="a031e3e27c8783c299623468020a22b0e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a031e3e27c8783c299623468020a22b0e">&#9670;&#160;</a></span>neorv32_uart_get_tx_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_get_tx_fifo_depth </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get UART TX FIFO depth.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries) </dd></dl> + +</div> +</div> +<a id="a2efd432f63b8d36d44263d0b1f39a6dc" name="a2efd432f63b8d36d44263d0b1f39a6dc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2efd432f63b8d36d44263d0b1f39a6dc">&#9670;&#160;</a></span>neorv32_uart_getc()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">char neorv32_uart_getc </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get char from UART.</p> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Received char. </dd></dl> + +</div> +</div> +<a id="ab8c1f9f451def9126ab2749d7bbe50d9" name="ab8c1f9f451def9126ab2749d7bbe50d9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab8c1f9f451def9126ab2749d7bbe50d9">&#9670;&#160;</a></span>neorv32_uart_printf()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_printf </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const char *</td> <td class="paramname"><span class="paramname"><em>format</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>...</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Custom version of 'printf' printing to UART.</p> +<dl class="section warning"><dt>Warning</dt><dd>: This functions only provides a minimal subset of the 'printf' formating features! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">format</td><td>Pointer to format string. See neorv32_uart_vprintf. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a9bc7bb94a50b74e1145b78eec6094129" name="a9bc7bb94a50b74e1145b78eec6094129"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9bc7bb94a50b74e1145b78eec6094129">&#9670;&#160;</a></span>neorv32_uart_putc()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_putc </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">char</td> <td class="paramname"><span class="paramname"><em>c</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send single char via UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">c</td><td>Char to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a45a07d5e71677162baaa1025759c67a2" name="a45a07d5e71677162baaa1025759c67a2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a45a07d5e71677162baaa1025759c67a2">&#9670;&#160;</a></span>neorv32_uart_puts()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_puts </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const char *</td> <td class="paramname"><span class="paramname"><em>s</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print string (zero-terminated) via UART. Print full line break "\r\n" for every '<br /> +'.</p> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">s</td><td>Pointer to string. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a7b2f924ef4554b1fa90433c38d97558d" name="a7b2f924ef4554b1fa90433c38d97558d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7b2f924ef4554b1fa90433c38d97558d">&#9670;&#160;</a></span>neorv32_uart_rtscts_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_rtscts_disable </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable RTS/CTS hardware flow-control.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a734b610f4cd1b474d7763f9700a715ec" name="a734b610f4cd1b474d7763f9700a715ec"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a734b610f4cd1b474d7763f9700a715ec">&#9670;&#160;</a></span>neorv32_uart_rtscts_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_rtscts_enable </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable RTS/CTS hardware flow-control.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="afe0de59c14faff1e0c890d5465be25f0" name="afe0de59c14faff1e0c890d5465be25f0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afe0de59c14faff1e0c890d5465be25f0">&#9670;&#160;</a></span>neorv32_uart_rx_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_rx_clear </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear RX FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac429964878bd6deab61d9ed8659bca75" name="ac429964878bd6deab61d9ed8659bca75"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac429964878bd6deab61d9ed8659bca75">&#9670;&#160;</a></span>neorv32_uart_scan()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_scan </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">char *</td> <td class="paramname"><span class="paramname"><em>buffer</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>max_size</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>echo</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Simplified custom version of 'scanf' reading from UART.</p> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">buffer</td><td>Pointer to array of chars to store string. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">max_size</td><td>Maximum number of chars to sample (including zero-termination). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">echo</td><td>Echo UART input when 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Number of chars read. </dd></dl> + +</div> +</div> +<a id="a9cdec36f2723c5373664022d1b68b841" name="a9cdec36f2723c5373664022d1b68b841"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9cdec36f2723c5373664022d1b68b841">&#9670;&#160;</a></span>neorv32_uart_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_setup </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>baudrate</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>irq_mask</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, configure and enable UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">baudrate</td><td>Targeted BAUD rate (e.g. 19200). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mask</td><td>Interrupt configuration mask (CTRL's irq_* bits). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aa7bef48a58e044c246b8c4ad32864502" name="aa7bef48a58e044c246b8c4ad32864502"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa7bef48a58e044c246b8c4ad32864502">&#9670;&#160;</a></span>neorv32_uart_tx_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_tx_busy </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if UART TX is busy (transmitter busy or data left in TX buffer).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if idle, 1 if busy </dd></dl> + +</div> +</div> +<a id="a27971954262a2fd1f21d3bf1ba27e87c" name="a27971954262a2fd1f21d3bf1ba27e87c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a27971954262a2fd1f21d3bf1ba27e87c">&#9670;&#160;</a></span>neorv32_uart_tx_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_tx_clear </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear TX FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a8714cdb1c04d94bec322c6215ea10238" name="a8714cdb1c04d94bec322c6215ea10238"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8714cdb1c04d94bec322c6215ea10238">&#9670;&#160;</a></span>neorv32_uart_vprintf()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_vprintf </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const char *</td> <td class="paramname"><span class="paramname"><em>format</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">va_list</td> <td class="paramname"><span class="paramname"><em>args</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Custom version of 'vprintf' printing to UART.</p> +<dl class="section warning"><dt>Warning</dt><dd>: This functions only provides a minimal subset of the 'vprintf' formating features! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">format</td><td>Pointer to format string. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">args</td><td>A value identifying a variable arguments list. </td></tr> + </table> + </dd> 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#nested-classes">Data Structures</a> </div> + <div class="headertitle"><div class="title">neorv32_uart.h File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;stdint.h&gt;</code><br /> +<code>#include &lt;stdarg.h&gt;</code><br /> +</div> +<p><a href="neorv32__uart_8h_source.html">Go to the source code of this file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">UART wrappers for easy access</div></td></tr> +<tr class="memitem:a652d93c0e3c6d7e5dc7c25c2465070e5" id="r_a652d93c0e3c6d7e5dc7c25c2465070e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a652d93c0e3c6d7e5dc7c25c2465070e5">neorv32_uart0_available</a>()</td></tr> +<tr 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valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa8cd95c962154cf55fb4b9d5008c858f">neorv32_uart0_scan</a>(buffer, max_size, echo)</td></tr> +<tr class="separator:aa8cd95c962154cf55fb4b9d5008c858f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a969f991e166e72a32aaee174ddef5962" id="r_a969f991e166e72a32aaee174ddef5962"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a969f991e166e72a32aaee174ddef5962">neorv32_uart1_available</a>()</td></tr> +<tr class="separator:a969f991e166e72a32aaee174ddef5962"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8a00c086c47e0cffbc586155228060df" id="r_a8a00c086c47e0cffbc586155228060df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8a00c086c47e0cffbc586155228060df">neorv32_uart1_get_rx_fifo_depth</a>()</td></tr> +<tr class="separator:a8a00c086c47e0cffbc586155228060df"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a27f16aaf0b15f5417c335804cfebbe54" id="r_a27f16aaf0b15f5417c335804cfebbe54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a27f16aaf0b15f5417c335804cfebbe54">neorv32_uart1_get_tx_fifo_depth</a>()</td></tr> +<tr class="separator:a27f16aaf0b15f5417c335804cfebbe54"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5d94cc37807bdac20fcd782df138d480" id="r_a5d94cc37807bdac20fcd782df138d480"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5d94cc37807bdac20fcd782df138d480">neorv32_uart1_setup</a>(baudrate, irq_mask)</td></tr> +<tr class="separator:a5d94cc37807bdac20fcd782df138d480"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a244073e58d04a364446f50e4708f3b36" id="r_a244073e58d04a364446f50e4708f3b36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a244073e58d04a364446f50e4708f3b36">neorv32_uart1_disable</a>()</td></tr> +<tr class="separator:a244073e58d04a364446f50e4708f3b36"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad36be396ae9e9ea21cf4a5f3247d7a8d" id="r_ad36be396ae9e9ea21cf4a5f3247d7a8d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad36be396ae9e9ea21cf4a5f3247d7a8d">neorv32_uart1_enable</a>()</td></tr> +<tr class="separator:ad36be396ae9e9ea21cf4a5f3247d7a8d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a49c5158b6fa31f1c59660ed8744f2a3a" id="r_a49c5158b6fa31f1c59660ed8744f2a3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a49c5158b6fa31f1c59660ed8744f2a3a">neorv32_uart1_rtscts_disable</a>()</td></tr> +<tr class="separator:a49c5158b6fa31f1c59660ed8744f2a3a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a64979d4d47678ca3e81a3b1d2eab52e7" id="r_a64979d4d47678ca3e81a3b1d2eab52e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a64979d4d47678ca3e81a3b1d2eab52e7">neorv32_uart1_rtscts_enable</a>()</td></tr> +<tr class="separator:a64979d4d47678ca3e81a3b1d2eab52e7"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acb41a23b9a1cbc4032d89455461c32be" id="r_acb41a23b9a1cbc4032d89455461c32be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:abef6415b0391dc055713404312196682" id="r_abef6415b0391dc055713404312196682"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abef6415b0391dc055713404312196682">neorv32_uart_available</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:abef6415b0391dc055713404312196682"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af85fb929c912d3edef3d86ffa833982a" id="r_af85fb929c912d3edef3d86ffa833982a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af85fb929c912d3edef3d86ffa833982a">neorv32_uart_get_rx_fifo_depth</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:af85fb929c912d3edef3d86ffa833982a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a031e3e27c8783c299623468020a22b0e" id="r_a031e3e27c8783c299623468020a22b0e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a031e3e27c8783c299623468020a22b0e">neorv32_uart_get_tx_fifo_depth</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx)</td></tr> +<tr class="separator:a031e3e27c8783c299623468020a22b0e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9cdec36f2723c5373664022d1b68b841" id="r_a9cdec36f2723c5373664022d1b68b841"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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class="el" href="#ab8c1f9f451def9126ab2749d7bbe50d9">neorv32_uart_printf</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, const char *format,...)</td></tr> +<tr class="separator:ab8c1f9f451def9126ab2749d7bbe50d9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac429964878bd6deab61d9ed8659bca75" id="r_ac429964878bd6deab61d9ed8659bca75"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac429964878bd6deab61d9ed8659bca75">neorv32_uart_scan</a> (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, char *buffer, int max_size, int echo)</td></tr> +<tr class="separator:ac429964878bd6deab61d9ed8659bca75"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)</h2></td></tr> +<tr class="memitem:a4c880a6b27e46f459e750425258b1bdb" id="r_a4c880a6b27e46f459e750425258b1bdb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>*) (<a class="el" href="neorv32_8h.html#a000b37f710043fe21e49b2fdbc039d94">NEORV32_UART0_BASE</a>))</td></tr> +<tr class="separator:a4c880a6b27e46f459e750425258b1bdb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa2a9ded4523f001bf69935c80247fa2d" id="r_aa2a9ded4523f001bf69935c80247fa2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>*) (<a class="el" href="neorv32_8h.html#a26a1defe18ce222b8b4ed1c760344700">NEORV32_UART1_BASE</a>))</td></tr> +<tr class="separator:aa2a9ded4523f001bf69935c80247fa2d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad9f75f453beca1619344bb4213352afc" id="r_ad9f75f453beca1619344bb4213352afc"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad9f75f453beca1619344bb4213352afc">NEORV32_UART_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#ad9f75f453beca1619344bb4213352afca38f6c0e5991f8f80159a388c1080f7c2">UART_CTRL_EN</a> = 0 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca42ed376220259ab22c6f837d08273ef1">UART_CTRL_SIM_MODE</a> = 1 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afcacab78fcd440167c5a2c0f5d300c8f07c">UART_CTRL_HWFC_EN</a> = 2 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca1ddbca448bb30c77c42499fff1312183">UART_CTRL_PRSC0</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#ad9f75f453beca1619344bb4213352afca9c1d8e8763a653339210ff4e6e3067d2">UART_CTRL_PRSC1</a> = 4 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca8afd60e4bd3854fab623b91fa4f33f70">UART_CTRL_PRSC2</a> = 5 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afcad38432e7e050276d4667daf92c1e3fd5">UART_CTRL_BAUD0</a> = 6 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca1e702002402897eca82bf398504bc439">UART_CTRL_BAUD1</a> = 7 +, <br /> +&#160;&#160;<a class="el" href="#ad9f75f453beca1619344bb4213352afca36266026e11f22aca1584bd81cd38cd6">UART_CTRL_BAUD2</a> = 8 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca58190cd41c2ce69512bea10740d35276">UART_CTRL_BAUD3</a> = 9 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca81ea805f01b93a59664823b940c7a424">UART_CTRL_BAUD4</a> = 10 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca5da1d6007af0265fe48ace8469e07833">UART_CTRL_BAUD5</a> = 11 +, <br /> +&#160;&#160;<a class="el" href="#ad9f75f453beca1619344bb4213352afca9ac3c1e23d684cb2f67060d6ebe1fa63">UART_CTRL_BAUD6</a> = 12 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca9c12648f7f058f444db434cd8a8d854e">UART_CTRL_BAUD7</a> = 13 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca09c311eb1f6b38500e6fcbb6ad9dd9ff">UART_CTRL_BAUD8</a> = 14 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca697321bddeaa2cac1ea034c418be540e">UART_CTRL_BAUD9</a> = 15 +, <br /> +&#160;&#160;<a class="el" href="#ad9f75f453beca1619344bb4213352afca2015dd85e361aa0476e847953b62baff">UART_CTRL_RX_NEMPTY</a> = 16 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca3fc934d0ce6b36e3e131c6682db22247">UART_CTRL_RX_HALF</a> = 17 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca47c44fa21e51401621c28019025c1166">UART_CTRL_RX_FULL</a> = 18 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afcac5c044233b6c4162cf862f3d9831ef46">UART_CTRL_TX_EMPTY</a> = 19 +, <br /> +&#160;&#160;<a class="el" href="#ad9f75f453beca1619344bb4213352afca5b0e40ab30bdb198f496d09e89d2d0d9">UART_CTRL_TX_NHALF</a> = 20 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca36b4195e5d1f12e1fd1a0d30cad0e411">UART_CTRL_TX_FULL</a> = 21 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca569ea830518914c5330fa14680b02851">UART_CTRL_IRQ_RX_NEMPTY</a> = 22 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afcaa219ea3ed5b21f5023bbc5ffa5c5f175">UART_CTRL_IRQ_RX_HALF</a> = 23 +, <br /> +&#160;&#160;<a class="el" href="#ad9f75f453beca1619344bb4213352afcae5f01868b170d71a5f3064023c96a82a">UART_CTRL_IRQ_RX_FULL</a> = 24 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca15b9fca73877aad446a8cd338e228e2c">UART_CTRL_IRQ_TX_EMPTY</a> = 25 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca726b73ef9c44ccc1a45a4230a8bda9d1">UART_CTRL_IRQ_TX_NHALF</a> = 26 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afcaefbef37247d88a7e38e1c53b8a33ed33">UART_CTRL_RX_CLR</a> = 28 +, <br /> +&#160;&#160;<a class="el" href="#ad9f75f453beca1619344bb4213352afca408412a32673cc7f6ea70682e3e61431">UART_CTRL_TX_CLR</a> = 29 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca81a52e0b81018f2cf43e64d74caba632">UART_CTRL_RX_OVER</a> = 30 +, <a class="el" href="#ad9f75f453beca1619344bb4213352afca0eb636d8b7961d7073c5c7341b5bbe25">UART_CTRL_TX_BUSY</a> = 31 +<br /> + }</td></tr> +<tr class="separator:ad9f75f453beca1619344bb4213352afc"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:adcf35350a9ea18a59c32c35f528643f2" id="r_adcf35350a9ea18a59c32c35f528643f2"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adcf35350a9ea18a59c32c35f528643f2">NEORV32_UART_DATA_enum</a> { <br /> +&#160;&#160;<a class="el" href="#adcf35350a9ea18a59c32c35f528643f2ae70e9f6cd69af724932e79ea7e7f7195">UART_DATA_RTX_LSB</a> = 0 +, <a class="el" href="#adcf35350a9ea18a59c32c35f528643f2a19926d013ca202645d38f2c704782ebb">UART_DATA_RTX_MSB</a> = 7 +, <a class="el" href="#adcf35350a9ea18a59c32c35f528643f2a43b296e86d1f2ec7400d57655c3180ef">UART_DATA_RX_FIFO_SIZE_LSB</a> = 8 +, <a class="el" href="#adcf35350a9ea18a59c32c35f528643f2a81a82ac0dc5c8c8d7af21553288e3225">UART_DATA_RX_FIFO_SIZE_MSB</a> = 11 +, <br /> +&#160;&#160;<a class="el" href="#adcf35350a9ea18a59c32c35f528643f2a6d718ad0bb82a5cb053c117cd2d6ca8e">UART_DATA_TX_FIFO_SIZE_LSB</a> = 12 +, <a class="el" href="#adcf35350a9ea18a59c32c35f528643f2ada92cbbe278e3e0592eba58c97699529">UART_DATA_TX_FIFO_SIZE_MSB</a> = 15 +<br /> + }</td></tr> +<tr class="separator:adcf35350a9ea18a59c32c35f528643f2"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a4c880a6b27e46f459e750425258b1bdb" name="a4c880a6b27e46f459e750425258b1bdb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4c880a6b27e46f459e750425258b1bdb">&#9670;&#160;</a></span>NEORV32_UART0</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_UART0&#160;&#160;&#160;((<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>*) (<a class="el" href="neorv32_8h.html#a000b37f710043fe21e49b2fdbc039d94">NEORV32_UART0_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART0 module hardware access (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>) </p> + +</div> +</div> +<a id="a652d93c0e3c6d7e5dc7c25c2465070e5" name="a652d93c0e3c6d7e5dc7c25c2465070e5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a652d93c0e3c6d7e5dc7c25c2465070e5">&#9670;&#160;</a></span>neorv32_uart0_available</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_available</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#abef6415b0391dc055713404312196682">neorv32_uart_available</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a4c880a6b27e46f459e750425258b1bdb"><div class="ttname"><a href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a></div><div class="ttdeci">#define NEORV32_UART0</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:34</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_abef6415b0391dc055713404312196682"><div class="ttname"><a href="#abef6415b0391dc055713404312196682">neorv32_uart_available</a></div><div class="ttdeci">int neorv32_uart_available(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:30</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="aa29a2aeeee4faeb35b19165a9af31ac7" name="aa29a2aeeee4faeb35b19165a9af31ac7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa29a2aeeee4faeb35b19165a9af31ac7">&#9670;&#160;</a></span>neorv32_uart0_char_received</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_char_received</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#adedb0e07efb232717534017167a5be98">neorv32_uart_char_received</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_adedb0e07efb232717534017167a5be98"><div class="ttname"><a href="#adedb0e07efb232717534017167a5be98">neorv32_uart_char_received</a></div><div class="ttdeci">int neorv32_uart_char_received(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:255</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a68aee77039a3c7450ec78e0f868889f1" name="a68aee77039a3c7450ec78e0f868889f1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a68aee77039a3c7450ec78e0f868889f1">&#9670;&#160;</a></span>neorv32_uart0_char_received_get</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_char_received_get</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#aa490df3a9bb2aa3215fa6fad34ffe7d1">neorv32_uart_char_received_get</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_aa490df3a9bb2aa3215fa6fad34ffe7d1"><div class="ttname"><a href="#aa490df3a9bb2aa3215fa6fad34ffe7d1">neorv32_uart_char_received_get</a></div><div class="ttdeci">char neorv32_uart_char_received_get(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:275</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="af99ce6ccc40fec039264da66e8f67ba7" name="af99ce6ccc40fec039264da66e8f67ba7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af99ce6ccc40fec039264da66e8f67ba7">&#9670;&#160;</a></span>neorv32_uart0_disable</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_disable</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#ae18804ccd29ec2fd1cc06e9ce985b704">neorv32_uart_disable</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_ae18804ccd29ec2fd1cc06e9ce985b704"><div class="ttname"><a href="#ae18804ccd29ec2fd1cc06e9ce985b704">neorv32_uart_disable</a></div><div class="ttdeci">void neorv32_uart_disable(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:147</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a4cc0ea2ee22b379fc9a7f45e30bc118f" name="a4cc0ea2ee22b379fc9a7f45e30bc118f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4cc0ea2ee22b379fc9a7f45e30bc118f">&#9670;&#160;</a></span>neorv32_uart0_enable</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_enable</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#afa0533e81d53057c36f4997a2dbbe2bc">neorv32_uart_enable</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_afa0533e81d53057c36f4997a2dbbe2bc"><div class="ttname"><a href="#afa0533e81d53057c36f4997a2dbbe2bc">neorv32_uart_enable</a></div><div class="ttdeci">void neorv32_uart_enable(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:136</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="aa5c803f757ecc14cdfdad521d4bf7c18" name="aa5c803f757ecc14cdfdad521d4bf7c18"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa5c803f757ecc14cdfdad521d4bf7c18">&#9670;&#160;</a></span>neorv32_uart0_get_rx_fifo_depth</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_get_rx_fifo_depth</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#af85fb929c912d3edef3d86ffa833982a">neorv32_uart_get_rx_fifo_depth</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_af85fb929c912d3edef3d86ffa833982a"><div class="ttname"><a href="#af85fb929c912d3edef3d86ffa833982a">neorv32_uart_get_rx_fifo_depth</a></div><div class="ttdeci">int neorv32_uart_get_rx_fifo_depth(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:110</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="af6068949ae9ed923eac69350347273dc" name="af6068949ae9ed923eac69350347273dc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af6068949ae9ed923eac69350347273dc">&#9670;&#160;</a></span>neorv32_uart0_get_tx_fifo_depth</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_get_tx_fifo_depth</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a031e3e27c8783c299623468020a22b0e">neorv32_uart_get_tx_fifo_depth</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a031e3e27c8783c299623468020a22b0e"><div class="ttname"><a href="#a031e3e27c8783c299623468020a22b0e">neorv32_uart_get_tx_fifo_depth</a></div><div class="ttdeci">int neorv32_uart_get_tx_fifo_depth(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:124</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a248d40034ce64ca3325c00b9ae0c5208" name="a248d40034ce64ca3325c00b9ae0c5208"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a248d40034ce64ca3325c00b9ae0c5208">&#9670;&#160;</a></span>neorv32_uart0_getc</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_getc</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a2efd432f63b8d36d44263d0b1f39a6dc">neorv32_uart_getc</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a2efd432f63b8d36d44263d0b1f39a6dc"><div class="ttname"><a href="#a2efd432f63b8d36d44263d0b1f39a6dc">neorv32_uart_getc</a></div><div class="ttdeci">char neorv32_uart_getc(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:236</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a6927bfe22016655a19b906d867006896" name="a6927bfe22016655a19b906d867006896"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6927bfe22016655a19b906d867006896">&#9670;&#160;</a></span>neorv32_uart0_printf</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_printf</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em></em></span>...</td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#ab8c1f9f451def9126ab2749d7bbe50d9">neorv32_uart_printf</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>, __VA_ARGS__)</div> +<div class="ttc" id="aneorv32__uart_8h_html_ab8c1f9f451def9126ab2749d7bbe50d9"><div class="ttname"><a href="#ab8c1f9f451def9126ab2749d7bbe50d9">neorv32_uart_printf</a></div><div class="ttdeci">void neorv32_uart_printf(neorv32_uart_t *UARTx, const char *format,...)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:386</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a2dc207fedc80aa9021a4e5b7abd667a7" name="a2dc207fedc80aa9021a4e5b7abd667a7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2dc207fedc80aa9021a4e5b7abd667a7">&#9670;&#160;</a></span>neorv32_uart0_putc</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_putc</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>c</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a9bc7bb94a50b74e1145b78eec6094129">neorv32_uart_putc</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>, c)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a9bc7bb94a50b74e1145b78eec6094129"><div class="ttname"><a href="#a9bc7bb94a50b74e1145b78eec6094129">neorv32_uart_putc</a></div><div class="ttdeci">void neorv32_uart_putc(neorv32_uart_t *UARTx, char c)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:181</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="adc688c900d03a0538dbd6461c56f00cd" name="adc688c900d03a0538dbd6461c56f00cd"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adc688c900d03a0538dbd6461c56f00cd">&#9670;&#160;</a></span>neorv32_uart0_puts</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_puts</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>s</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a45a07d5e71677162baaa1025759c67a2">neorv32_uart_puts</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>, s)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a45a07d5e71677162baaa1025759c67a2"><div class="ttname"><a href="#a45a07d5e71677162baaa1025759c67a2">neorv32_uart_puts</a></div><div class="ttdeci">void neorv32_uart_puts(neorv32_uart_t *UARTx, const char *s)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:289</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a3cdd0db72d7cffe25c9f2f90a39fc2f7" name="a3cdd0db72d7cffe25c9f2f90a39fc2f7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3cdd0db72d7cffe25c9f2f90a39fc2f7">&#9670;&#160;</a></span>neorv32_uart0_rtscts_disable</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_rtscts_disable</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a7b2f924ef4554b1fa90433c38d97558d">neorv32_uart_rtscts_disable</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a7b2f924ef4554b1fa90433c38d97558d"><div class="ttname"><a href="#a7b2f924ef4554b1fa90433c38d97558d">neorv32_uart_rtscts_disable</a></div><div class="ttdeci">void neorv32_uart_rtscts_disable(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:169</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a53734cc693bdfa11458a62df5b609264" name="a53734cc693bdfa11458a62df5b609264"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a53734cc693bdfa11458a62df5b609264">&#9670;&#160;</a></span>neorv32_uart0_rtscts_enable</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_rtscts_enable</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a734b610f4cd1b474d7763f9700a715ec">neorv32_uart_rtscts_enable</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a734b610f4cd1b474d7763f9700a715ec"><div class="ttname"><a href="#a734b610f4cd1b474d7763f9700a715ec">neorv32_uart_rtscts_enable</a></div><div class="ttdeci">void neorv32_uart_rtscts_enable(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:158</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="ab576f613cf952dadb8c1a352d8bdf4b5" name="ab576f613cf952dadb8c1a352d8bdf4b5"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab576f613cf952dadb8c1a352d8bdf4b5">&#9670;&#160;</a></span>neorv32_uart0_rx_clear</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_rx_clear</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#afe0de59c14faff1e0c890d5465be25f0">neorv32_uart_rx_clear</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_afe0de59c14faff1e0c890d5465be25f0"><div class="ttname"><a href="#afe0de59c14faff1e0c890d5465be25f0">neorv32_uart_rx_clear</a></div><div class="ttdeci">void neorv32_uart_rx_clear(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:194</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="aa8cd95c962154cf55fb4b9d5008c858f" name="aa8cd95c962154cf55fb4b9d5008c858f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa8cd95c962154cf55fb4b9d5008c858f">&#9670;&#160;</a></span>neorv32_uart0_scan</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_scan</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>buffer</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>max_size</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>echo</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#ac429964878bd6deab61d9ed8659bca75">neorv32_uart_scan</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>, buffer, max_size, echo)</div> +<div class="ttc" id="aneorv32__uart_8h_html_ac429964878bd6deab61d9ed8659bca75"><div class="ttname"><a href="#ac429964878bd6deab61d9ed8659bca75">neorv32_uart_scan</a></div><div class="ttdeci">int neorv32_uart_scan(neorv32_uart_t *UARTx, char *buffer, int max_size, int echo)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:406</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a27e92f501ceda8e34652781901e6db33" name="a27e92f501ceda8e34652781901e6db33"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a27e92f501ceda8e34652781901e6db33">&#9670;&#160;</a></span>neorv32_uart0_setup</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_setup</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>baudrate</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>irq_mask</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a9cdec36f2723c5373664022d1b68b841">neorv32_uart_setup</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>, baudrate, irq_mask)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a9cdec36f2723c5373664022d1b68b841"><div class="ttname"><a href="#a9cdec36f2723c5373664022d1b68b841">neorv32_uart_setup</a></div><div class="ttdeci">void neorv32_uart_setup(neorv32_uart_t *UARTx, uint32_t baudrate, uint32_t irq_mask)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:51</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a80c68d3af417085da2d18a82081124ba" name="a80c68d3af417085da2d18a82081124ba"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a80c68d3af417085da2d18a82081124ba">&#9670;&#160;</a></span>neorv32_uart0_tx_busy</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_tx_busy</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#aa7bef48a58e044c246b8c4ad32864502">neorv32_uart_tx_busy</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_aa7bef48a58e044c246b8c4ad32864502"><div class="ttname"><a href="#aa7bef48a58e044c246b8c4ad32864502">neorv32_uart_tx_busy</a></div><div class="ttdeci">int neorv32_uart_tx_busy(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:217</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="af4fd1601d10c6eeca0f4e8b6fe076a7f" name="af4fd1601d10c6eeca0f4e8b6fe076a7f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af4fd1601d10c6eeca0f4e8b6fe076a7f">&#9670;&#160;</a></span>neorv32_uart0_tx_clear</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart0_tx_clear</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a27971954262a2fd1f21d3bf1ba27e87c">neorv32_uart_tx_clear</a>(<a class="code hl_define" href="#a4c880a6b27e46f459e750425258b1bdb">NEORV32_UART0</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_a27971954262a2fd1f21d3bf1ba27e87c"><div class="ttname"><a href="#a27971954262a2fd1f21d3bf1ba27e87c">neorv32_uart_tx_clear</a></div><div class="ttdeci">void neorv32_uart_tx_clear(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:205</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="aa2a9ded4523f001bf69935c80247fa2d" name="aa2a9ded4523f001bf69935c80247fa2d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa2a9ded4523f001bf69935c80247fa2d">&#9670;&#160;</a></span>NEORV32_UART1</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_UART1&#160;&#160;&#160;((<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>*) (<a class="el" href="neorv32_8h.html#a26a1defe18ce222b8b4ed1c760344700">NEORV32_UART1_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART1 module hardware access (<a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>) </p> + +</div> +</div> +<a id="a969f991e166e72a32aaee174ddef5962" name="a969f991e166e72a32aaee174ddef5962"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a969f991e166e72a32aaee174ddef5962">&#9670;&#160;</a></span>neorv32_uart1_available</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_available</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#abef6415b0391dc055713404312196682">neorv32_uart_available</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +<div class="ttc" id="aneorv32__uart_8h_html_aa2a9ded4523f001bf69935c80247fa2d"><div class="ttname"><a href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a></div><div class="ttdeci">#define NEORV32_UART1</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:37</div></div> +</div><!-- fragment --> +</div> +</div> +<a id="a8b862c864010a574b856a7f5d3f6020b" name="a8b862c864010a574b856a7f5d3f6020b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8b862c864010a574b856a7f5d3f6020b">&#9670;&#160;</a></span>neorv32_uart1_char_received</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_char_received</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#adedb0e07efb232717534017167a5be98">neorv32_uart_char_received</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a25006186655175f0bbfe739750ebcec6" name="a25006186655175f0bbfe739750ebcec6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a25006186655175f0bbfe739750ebcec6">&#9670;&#160;</a></span>neorv32_uart1_char_received_get</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_char_received_get</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#aa490df3a9bb2aa3215fa6fad34ffe7d1">neorv32_uart_char_received_get</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a244073e58d04a364446f50e4708f3b36" name="a244073e58d04a364446f50e4708f3b36"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a244073e58d04a364446f50e4708f3b36">&#9670;&#160;</a></span>neorv32_uart1_disable</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_disable</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#ae18804ccd29ec2fd1cc06e9ce985b704">neorv32_uart_disable</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="ad36be396ae9e9ea21cf4a5f3247d7a8d" name="ad36be396ae9e9ea21cf4a5f3247d7a8d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad36be396ae9e9ea21cf4a5f3247d7a8d">&#9670;&#160;</a></span>neorv32_uart1_enable</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_enable</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#afa0533e81d53057c36f4997a2dbbe2bc">neorv32_uart_enable</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a8a00c086c47e0cffbc586155228060df" name="a8a00c086c47e0cffbc586155228060df"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8a00c086c47e0cffbc586155228060df">&#9670;&#160;</a></span>neorv32_uart1_get_rx_fifo_depth</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_get_rx_fifo_depth</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#af85fb929c912d3edef3d86ffa833982a">neorv32_uart_get_rx_fifo_depth</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a27f16aaf0b15f5417c335804cfebbe54" name="a27f16aaf0b15f5417c335804cfebbe54"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a27f16aaf0b15f5417c335804cfebbe54">&#9670;&#160;</a></span>neorv32_uart1_get_tx_fifo_depth</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_get_tx_fifo_depth</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a031e3e27c8783c299623468020a22b0e">neorv32_uart_get_tx_fifo_depth</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a1d8a289bcd2d4c33769dcc670678a573" name="a1d8a289bcd2d4c33769dcc670678a573"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1d8a289bcd2d4c33769dcc670678a573">&#9670;&#160;</a></span>neorv32_uart1_getc</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_getc</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a2efd432f63b8d36d44263d0b1f39a6dc">neorv32_uart_getc</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a5992006547f020a7ba5ab914266358c6" name="a5992006547f020a7ba5ab914266358c6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5992006547f020a7ba5ab914266358c6">&#9670;&#160;</a></span>neorv32_uart1_printf</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_printf</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em></em></span>...</td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#ab8c1f9f451def9126ab2749d7bbe50d9">neorv32_uart_printf</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>, __VA_ARGS__)</div> +</div><!-- fragment --> +</div> +</div> +<a id="acb41a23b9a1cbc4032d89455461c32be" name="acb41a23b9a1cbc4032d89455461c32be"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acb41a23b9a1cbc4032d89455461c32be">&#9670;&#160;</a></span>neorv32_uart1_putc</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_putc</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>c</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a9bc7bb94a50b74e1145b78eec6094129">neorv32_uart_putc</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>, c)</div> +</div><!-- fragment --> +</div> +</div> +<a id="aa44dc625701ebbffe94508aa2e23dedf" name="aa44dc625701ebbffe94508aa2e23dedf"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa44dc625701ebbffe94508aa2e23dedf">&#9670;&#160;</a></span>neorv32_uart1_puts</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_puts</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>s</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a45a07d5e71677162baaa1025759c67a2">neorv32_uart_puts</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>, s)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a49c5158b6fa31f1c59660ed8744f2a3a" name="a49c5158b6fa31f1c59660ed8744f2a3a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a49c5158b6fa31f1c59660ed8744f2a3a">&#9670;&#160;</a></span>neorv32_uart1_rtscts_disable</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_rtscts_disable</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a7b2f924ef4554b1fa90433c38d97558d">neorv32_uart_rtscts_disable</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a64979d4d47678ca3e81a3b1d2eab52e7" name="a64979d4d47678ca3e81a3b1d2eab52e7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a64979d4d47678ca3e81a3b1d2eab52e7">&#9670;&#160;</a></span>neorv32_uart1_rtscts_enable</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_rtscts_enable</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a734b610f4cd1b474d7763f9700a715ec">neorv32_uart_rtscts_enable</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a43be76025c2b90c3868315eacb0ee865" name="a43be76025c2b90c3868315eacb0ee865"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a43be76025c2b90c3868315eacb0ee865">&#9670;&#160;</a></span>neorv32_uart1_rx_clear</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_rx_clear</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#afe0de59c14faff1e0c890d5465be25f0">neorv32_uart_rx_clear</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a22a000e915c62c5d7da0af8ca4922710" name="a22a000e915c62c5d7da0af8ca4922710"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a22a000e915c62c5d7da0af8ca4922710">&#9670;&#160;</a></span>neorv32_uart1_scan</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_scan</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>buffer</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>max_size</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>echo</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#ac429964878bd6deab61d9ed8659bca75">neorv32_uart_scan</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>, buffer, max_size, echo)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a5d94cc37807bdac20fcd782df138d480" name="a5d94cc37807bdac20fcd782df138d480"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5d94cc37807bdac20fcd782df138d480">&#9670;&#160;</a></span>neorv32_uart1_setup</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_setup</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>baudrate</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>irq_mask</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a9cdec36f2723c5373664022d1b68b841">neorv32_uart_setup</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>, baudrate, irq_mask)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a4fbbc6737f0d5e44eb775f5f6d724b02" name="a4fbbc6737f0d5e44eb775f5f6d724b02"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4fbbc6737f0d5e44eb775f5f6d724b02">&#9670;&#160;</a></span>neorv32_uart1_tx_busy</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_tx_busy</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#aa7bef48a58e044c246b8c4ad32864502">neorv32_uart_tx_busy</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<a id="a4705c6caea4b5064f51d37b40a156080" name="a4705c6caea4b5064f51d37b40a156080"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a4705c6caea4b5064f51d37b40a156080">&#9670;&#160;</a></span>neorv32_uart1_tx_clear</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define neorv32_uart1_tx_clear</td> + <td>(</td> + <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line"><a class="code hl_function" href="#a27971954262a2fd1f21d3bf1ba27e87c">neorv32_uart_tx_clear</a>(<a class="code hl_define" href="#aa2a9ded4523f001bf69935c80247fa2d">NEORV32_UART1</a>)</div> +</div><!-- fragment --> +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="ad9f75f453beca1619344bb4213352afc" name="ad9f75f453beca1619344bb4213352afc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad9f75f453beca1619344bb4213352afc">&#9670;&#160;</a></span>NEORV32_UART_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#ad9f75f453beca1619344bb4213352afc">NEORV32_UART_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca38f6c0e5991f8f80159a388c1080f7c2" name="ad9f75f453beca1619344bb4213352afca38f6c0e5991f8f80159a388c1080f7c2"></a>UART_CTRL_EN&#160;</td><td class="fielddoc"><p>UART control register(0) (r/w): UART global enable </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca42ed376220259ab22c6f837d08273ef1" name="ad9f75f453beca1619344bb4213352afca42ed376220259ab22c6f837d08273ef1"></a>UART_CTRL_SIM_MODE&#160;</td><td class="fielddoc"><p>UART control register(1) (r/w): Simulation output override enable </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afcacab78fcd440167c5a2c0f5d300c8f07c" name="ad9f75f453beca1619344bb4213352afcacab78fcd440167c5a2c0f5d300c8f07c"></a>UART_CTRL_HWFC_EN&#160;</td><td class="fielddoc"><p>UART control register(2) (r/w): Enable RTS/CTS hardware flow-control </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca1ddbca448bb30c77c42499fff1312183" name="ad9f75f453beca1619344bb4213352afca1ddbca448bb30c77c42499fff1312183"></a>UART_CTRL_PRSC0&#160;</td><td class="fielddoc"><p>UART control register(3) (r/w): clock prescaler select bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca9c1d8e8763a653339210ff4e6e3067d2" name="ad9f75f453beca1619344bb4213352afca9c1d8e8763a653339210ff4e6e3067d2"></a>UART_CTRL_PRSC1&#160;</td><td class="fielddoc"><p>UART control register(4) (r/w): clock prescaler select bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca8afd60e4bd3854fab623b91fa4f33f70" name="ad9f75f453beca1619344bb4213352afca8afd60e4bd3854fab623b91fa4f33f70"></a>UART_CTRL_PRSC2&#160;</td><td class="fielddoc"><p>UART control register(5) (r/w): clock prescaler select bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afcad38432e7e050276d4667daf92c1e3fd5" name="ad9f75f453beca1619344bb4213352afcad38432e7e050276d4667daf92c1e3fd5"></a>UART_CTRL_BAUD0&#160;</td><td class="fielddoc"><p>UART control register(6) (r/w): BAUD rate divisor, bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca1e702002402897eca82bf398504bc439" name="ad9f75f453beca1619344bb4213352afca1e702002402897eca82bf398504bc439"></a>UART_CTRL_BAUD1&#160;</td><td class="fielddoc"><p>UART control register(7) (r/w): BAUD rate divisor, bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca36266026e11f22aca1584bd81cd38cd6" name="ad9f75f453beca1619344bb4213352afca36266026e11f22aca1584bd81cd38cd6"></a>UART_CTRL_BAUD2&#160;</td><td class="fielddoc"><p>UART control register(8) (r/w): BAUD rate divisor, bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca58190cd41c2ce69512bea10740d35276" name="ad9f75f453beca1619344bb4213352afca58190cd41c2ce69512bea10740d35276"></a>UART_CTRL_BAUD3&#160;</td><td class="fielddoc"><p>UART control register(9) (r/w): BAUD rate divisor, bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca81ea805f01b93a59664823b940c7a424" name="ad9f75f453beca1619344bb4213352afca81ea805f01b93a59664823b940c7a424"></a>UART_CTRL_BAUD4&#160;</td><td class="fielddoc"><p>UART control register(10) (r/w): BAUD rate divisor, bit 4 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca5da1d6007af0265fe48ace8469e07833" name="ad9f75f453beca1619344bb4213352afca5da1d6007af0265fe48ace8469e07833"></a>UART_CTRL_BAUD5&#160;</td><td class="fielddoc"><p>UART control register(11) (r/w): BAUD rate divisor, bit 5 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca9ac3c1e23d684cb2f67060d6ebe1fa63" name="ad9f75f453beca1619344bb4213352afca9ac3c1e23d684cb2f67060d6ebe1fa63"></a>UART_CTRL_BAUD6&#160;</td><td class="fielddoc"><p>UART control register(12) (r/w): BAUD rate divisor, bit 6 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca9c12648f7f058f444db434cd8a8d854e" name="ad9f75f453beca1619344bb4213352afca9c12648f7f058f444db434cd8a8d854e"></a>UART_CTRL_BAUD7&#160;</td><td class="fielddoc"><p>UART control register(13) (r/w): BAUD rate divisor, bit 7 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca09c311eb1f6b38500e6fcbb6ad9dd9ff" name="ad9f75f453beca1619344bb4213352afca09c311eb1f6b38500e6fcbb6ad9dd9ff"></a>UART_CTRL_BAUD8&#160;</td><td class="fielddoc"><p>UART control register(14) (r/w): BAUD rate divisor, bit 8 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca697321bddeaa2cac1ea034c418be540e" name="ad9f75f453beca1619344bb4213352afca697321bddeaa2cac1ea034c418be540e"></a>UART_CTRL_BAUD9&#160;</td><td class="fielddoc"><p>UART control register(15) (r/w): BAUD rate divisor, bit 9 </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca2015dd85e361aa0476e847953b62baff" name="ad9f75f453beca1619344bb4213352afca2015dd85e361aa0476e847953b62baff"></a>UART_CTRL_RX_NEMPTY&#160;</td><td class="fielddoc"><p>UART control register(16) (r/-): RX FIFO not empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca3fc934d0ce6b36e3e131c6682db22247" name="ad9f75f453beca1619344bb4213352afca3fc934d0ce6b36e3e131c6682db22247"></a>UART_CTRL_RX_HALF&#160;</td><td class="fielddoc"><p>UART control register(17) (r/-): RX FIFO at least half-full </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca47c44fa21e51401621c28019025c1166" name="ad9f75f453beca1619344bb4213352afca47c44fa21e51401621c28019025c1166"></a>UART_CTRL_RX_FULL&#160;</td><td class="fielddoc"><p>UART control register(18) (r/-): RX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afcac5c044233b6c4162cf862f3d9831ef46" name="ad9f75f453beca1619344bb4213352afcac5c044233b6c4162cf862f3d9831ef46"></a>UART_CTRL_TX_EMPTY&#160;</td><td class="fielddoc"><p>UART control register(19) (r/-): TX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca5b0e40ab30bdb198f496d09e89d2d0d9" name="ad9f75f453beca1619344bb4213352afca5b0e40ab30bdb198f496d09e89d2d0d9"></a>UART_CTRL_TX_NHALF&#160;</td><td class="fielddoc"><p>UART control register(20) (r/-): TX FIFO not at least half-full </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca36b4195e5d1f12e1fd1a0d30cad0e411" name="ad9f75f453beca1619344bb4213352afca36b4195e5d1f12e1fd1a0d30cad0e411"></a>UART_CTRL_TX_FULL&#160;</td><td class="fielddoc"><p>UART control register(21) (r/-): TX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca569ea830518914c5330fa14680b02851" name="ad9f75f453beca1619344bb4213352afca569ea830518914c5330fa14680b02851"></a>UART_CTRL_IRQ_RX_NEMPTY&#160;</td><td class="fielddoc"><p>UART control register(22) (r/w): Fire IRQ if RX FIFO not empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afcaa219ea3ed5b21f5023bbc5ffa5c5f175" name="ad9f75f453beca1619344bb4213352afcaa219ea3ed5b21f5023bbc5ffa5c5f175"></a>UART_CTRL_IRQ_RX_HALF&#160;</td><td class="fielddoc"><p>UART control register(23) (r/w): Fire IRQ if RX FIFO at least half-full </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afcae5f01868b170d71a5f3064023c96a82a" name="ad9f75f453beca1619344bb4213352afcae5f01868b170d71a5f3064023c96a82a"></a>UART_CTRL_IRQ_RX_FULL&#160;</td><td class="fielddoc"><p>UART control register(24) (r/w): Fire IRQ if RX FIFO full </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca15b9fca73877aad446a8cd338e228e2c" name="ad9f75f453beca1619344bb4213352afca15b9fca73877aad446a8cd338e228e2c"></a>UART_CTRL_IRQ_TX_EMPTY&#160;</td><td class="fielddoc"><p>UART control register(25) (r/w): Fire IRQ if TX FIFO empty </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca726b73ef9c44ccc1a45a4230a8bda9d1" name="ad9f75f453beca1619344bb4213352afca726b73ef9c44ccc1a45a4230a8bda9d1"></a>UART_CTRL_IRQ_TX_NHALF&#160;</td><td class="fielddoc"><p>UART control register(26) (r/w): Fire IRQ if TX FIFO not at least half-full </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afcaefbef37247d88a7e38e1c53b8a33ed33" name="ad9f75f453beca1619344bb4213352afcaefbef37247d88a7e38e1c53b8a33ed33"></a>UART_CTRL_RX_CLR&#160;</td><td class="fielddoc"><p>UART control register(28) (r/w): Clear RX FIFO, flag auto-clears </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca408412a32673cc7f6ea70682e3e61431" name="ad9f75f453beca1619344bb4213352afca408412a32673cc7f6ea70682e3e61431"></a>UART_CTRL_TX_CLR&#160;</td><td class="fielddoc"><p>UART control register(29) (r/w): Clear TX FIFO, flag auto-clears </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca81a52e0b81018f2cf43e64d74caba632" name="ad9f75f453beca1619344bb4213352afca81a52e0b81018f2cf43e64d74caba632"></a>UART_CTRL_RX_OVER&#160;</td><td class="fielddoc"><p>UART control register(30) (r/-): RX FIFO overflow </p> +</td></tr> +<tr><td class="fieldname"><a id="ad9f75f453beca1619344bb4213352afca0eb636d8b7961d7073c5c7341b5bbe25" name="ad9f75f453beca1619344bb4213352afca0eb636d8b7961d7073c5c7341b5bbe25"></a>UART_CTRL_TX_BUSY&#160;</td><td class="fielddoc"><p>UART control register(31) (r/-): Transmitter busy or TX FIFO not empty </p> +</td></tr> +</table> + +</div> +</div> +<a id="adcf35350a9ea18a59c32c35f528643f2" name="adcf35350a9ea18a59c32c35f528643f2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adcf35350a9ea18a59c32c35f528643f2">&#9670;&#160;</a></span>NEORV32_UART_DATA_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#adcf35350a9ea18a59c32c35f528643f2">NEORV32_UART_DATA_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>UART data register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="adcf35350a9ea18a59c32c35f528643f2ae70e9f6cd69af724932e79ea7e7f7195" name="adcf35350a9ea18a59c32c35f528643f2ae70e9f6cd69af724932e79ea7e7f7195"></a>UART_DATA_RTX_LSB&#160;</td><td class="fielddoc"><p>UART data register(0) (r/w): UART receive/transmit data, LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="adcf35350a9ea18a59c32c35f528643f2a19926d013ca202645d38f2c704782ebb" name="adcf35350a9ea18a59c32c35f528643f2a19926d013ca202645d38f2c704782ebb"></a>UART_DATA_RTX_MSB&#160;</td><td class="fielddoc"><p>UART data register(7) (r/w): UART receive/transmit data, MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="adcf35350a9ea18a59c32c35f528643f2a43b296e86d1f2ec7400d57655c3180ef" name="adcf35350a9ea18a59c32c35f528643f2a43b296e86d1f2ec7400d57655c3180ef"></a>UART_DATA_RX_FIFO_SIZE_LSB&#160;</td><td class="fielddoc"><p>UART data register(8) (r/-): log2(RX FIFO size), LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="adcf35350a9ea18a59c32c35f528643f2a81a82ac0dc5c8c8d7af21553288e3225" name="adcf35350a9ea18a59c32c35f528643f2a81a82ac0dc5c8c8d7af21553288e3225"></a>UART_DATA_RX_FIFO_SIZE_MSB&#160;</td><td class="fielddoc"><p>UART data register(11) (r/-): log2(RX FIFO size), MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="adcf35350a9ea18a59c32c35f528643f2a6d718ad0bb82a5cb053c117cd2d6ca8e" name="adcf35350a9ea18a59c32c35f528643f2a6d718ad0bb82a5cb053c117cd2d6ca8e"></a>UART_DATA_TX_FIFO_SIZE_LSB&#160;</td><td class="fielddoc"><p>UART data register(12) (r/-): log2(RX FIFO size), LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="adcf35350a9ea18a59c32c35f528643f2ada92cbbe278e3e0592eba58c97699529" name="adcf35350a9ea18a59c32c35f528643f2ada92cbbe278e3e0592eba58c97699529"></a>UART_DATA_TX_FIFO_SIZE_MSB&#160;</td><td class="fielddoc"><p>UART data register(15) (r/-): log2(RX FIFO size), MSB </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="abef6415b0391dc055713404312196682" name="abef6415b0391dc055713404312196682"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abef6415b0391dc055713404312196682">&#9670;&#160;</a></span>neorv32_uart_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_available </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if UART unit was synthesized.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">Hardware</td><td>handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if UART0/1 was not synthesized, 1 if UART0/1 is available. </dd></dl> + +</div> +</div> +<a id="adedb0e07efb232717534017167a5be98" name="adedb0e07efb232717534017167a5be98"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adedb0e07efb232717534017167a5be98">&#9670;&#160;</a></span>neorv32_uart_char_received()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_char_received </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if UART has received a char.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd> +<dd> +Use neorv32_uart_char_received_get(void) to get the char.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>1 when a char has been received, 0 otherwise. </dd></dl> + +</div> +</div> +<a id="aa490df3a9bb2aa3215fa6fad34ffe7d1" name="aa490df3a9bb2aa3215fa6fad34ffe7d1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa490df3a9bb2aa3215fa6fad34ffe7d1">&#9670;&#160;</a></span>neorv32_uart_char_received_get()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">char neorv32_uart_char_received_get </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get a received char from UART.</p> +<dl class="section note"><dt>Note</dt><dd>This function is non-blocking. </dd> +<dd> +Should only be used in combination with neorv32_uart_char_received(void).</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Received char. </dd></dl> + +</div> +</div> +<a id="ae18804ccd29ec2fd1cc06e9ce985b704" name="ae18804ccd29ec2fd1cc06e9ce985b704"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae18804ccd29ec2fd1cc06e9ce985b704">&#9670;&#160;</a></span>neorv32_uart_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_disable </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="afa0533e81d53057c36f4997a2dbbe2bc" name="afa0533e81d53057c36f4997a2dbbe2bc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afa0533e81d53057c36f4997a2dbbe2bc">&#9670;&#160;</a></span>neorv32_uart_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_enable </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="af85fb929c912d3edef3d86ffa833982a" name="af85fb929c912d3edef3d86ffa833982a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af85fb929c912d3edef3d86ffa833982a">&#9670;&#160;</a></span>neorv32_uart_get_rx_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_get_rx_fifo_depth </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get UART RX FIFO depth.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries) </dd></dl> + +</div> +</div> +<a id="a031e3e27c8783c299623468020a22b0e" name="a031e3e27c8783c299623468020a22b0e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a031e3e27c8783c299623468020a22b0e">&#9670;&#160;</a></span>neorv32_uart_get_tx_fifo_depth()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_get_tx_fifo_depth </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get UART TX FIFO depth.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>FIFO depth (number of entries) </dd></dl> + +</div> +</div> +<a id="a2efd432f63b8d36d44263d0b1f39a6dc" name="a2efd432f63b8d36d44263d0b1f39a6dc"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2efd432f63b8d36d44263d0b1f39a6dc">&#9670;&#160;</a></span>neorv32_uart_getc()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">char neorv32_uart_getc </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get char from UART.</p> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Received char. </dd></dl> + +</div> +</div> +<a id="ab8c1f9f451def9126ab2749d7bbe50d9" name="ab8c1f9f451def9126ab2749d7bbe50d9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab8c1f9f451def9126ab2749d7bbe50d9">&#9670;&#160;</a></span>neorv32_uart_printf()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_printf </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const char *</td> <td class="paramname"><span class="paramname"><em>format</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em>...</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Custom version of 'printf' printing to UART.</p> +<dl class="section warning"><dt>Warning</dt><dd>: This functions only provides a minimal subset of the 'printf' formating features! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">format</td><td>Pointer to format string. See neorv32_uart_vprintf. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a9bc7bb94a50b74e1145b78eec6094129" name="a9bc7bb94a50b74e1145b78eec6094129"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9bc7bb94a50b74e1145b78eec6094129">&#9670;&#160;</a></span>neorv32_uart_putc()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_putc </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">char</td> <td class="paramname"><span class="paramname"><em>c</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send single char via UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">c</td><td>Char to be send. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a45a07d5e71677162baaa1025759c67a2" name="a45a07d5e71677162baaa1025759c67a2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a45a07d5e71677162baaa1025759c67a2">&#9670;&#160;</a></span>neorv32_uart_puts()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_puts </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const char *</td> <td class="paramname"><span class="paramname"><em>s</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Print string (zero-terminated) via UART. Print full line break "\r\n" for every '<br /> +'.</p> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">s</td><td>Pointer to string. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a7b2f924ef4554b1fa90433c38d97558d" name="a7b2f924ef4554b1fa90433c38d97558d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7b2f924ef4554b1fa90433c38d97558d">&#9670;&#160;</a></span>neorv32_uart_rtscts_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_rtscts_disable </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable RTS/CTS hardware flow-control.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a734b610f4cd1b474d7763f9700a715ec" name="a734b610f4cd1b474d7763f9700a715ec"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a734b610f4cd1b474d7763f9700a715ec">&#9670;&#160;</a></span>neorv32_uart_rtscts_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_rtscts_enable </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable RTS/CTS hardware flow-control.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="afe0de59c14faff1e0c890d5465be25f0" name="afe0de59c14faff1e0c890d5465be25f0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afe0de59c14faff1e0c890d5465be25f0">&#9670;&#160;</a></span>neorv32_uart_rx_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_rx_clear </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear RX FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="ac429964878bd6deab61d9ed8659bca75" name="ac429964878bd6deab61d9ed8659bca75"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac429964878bd6deab61d9ed8659bca75">&#9670;&#160;</a></span>neorv32_uart_scan()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_scan </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">char *</td> <td class="paramname"><span class="paramname"><em>buffer</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>max_size</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>echo</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Simplified custom version of 'scanf' reading from UART.</p> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">buffer</td><td>Pointer to array of chars to store string. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">max_size</td><td>Maximum number of chars to sample (including zero-termination). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">echo</td><td>Echo UART input when 1. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Number of chars read. </dd></dl> + +</div> +</div> +<a id="a9cdec36f2723c5373664022d1b68b841" name="a9cdec36f2723c5373664022d1b68b841"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9cdec36f2723c5373664022d1b68b841">&#9670;&#160;</a></span>neorv32_uart_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_setup </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>baudrate</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>irq_mask</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset, configure and enable UART.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">baudrate</td><td>Targeted BAUD rate (e.g. 19200). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">irq_mask</td><td>Interrupt configuration mask (CTRL's irq_* bits). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="aa7bef48a58e044c246b8c4ad32864502" name="aa7bef48a58e044c246b8c4ad32864502"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa7bef48a58e044c246b8c4ad32864502">&#9670;&#160;</a></span>neorv32_uart_tx_busy()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_uart_tx_busy </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if UART TX is busy (transmitter busy or data left in TX buffer).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if idle, 1 if busy </dd></dl> + +</div> +</div> +<a id="a27971954262a2fd1f21d3bf1ba27e87c" name="a27971954262a2fd1f21d3bf1ba27e87c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a27971954262a2fd1f21d3bf1ba27e87c">&#9670;&#160;</a></span>neorv32_uart_tx_clear()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_tx_clear </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear TX FIFO.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a8714cdb1c04d94bec322c6215ea10238" name="a8714cdb1c04d94bec322c6215ea10238"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8714cdb1c04d94bec322c6215ea10238">&#9670;&#160;</a></span>neorv32_uart_vprintf()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_uart_vprintf </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a> *</td> <td class="paramname"><span class="paramname"><em>UARTx</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const char *</td> <td class="paramname"><span class="paramname"><em>format</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">va_list</td> <td class="paramname"><span class="paramname"><em>args</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Custom version of 'vprintf' printing to UART.</p> +<dl class="section warning"><dt>Warning</dt><dd>: This functions only provides a minimal subset of the 'vprintf' formating features! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in,out]</td><td class="paramname">UARTx</td><td>Hardware handle to UART register struct, <a class="el" href="structneorv32__uart__t.html">neorv32_uart_t</a>. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">format</td><td>Pointer to format string. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">args</td><td>A value identifying a variable arguments list. </td></tr> + </table> + </dd> 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+<div id="nav-path" class="navpath"> + <ul> +<li class="navelem"><a class="el" href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_752b1e5d3973bf735fa78bf6b4727df9.html">include</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"><div class="title">neorv32_uart.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__uart_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_uart_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_uart_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="preprocessor">#include &lt;stdarg.h&gt;</span></div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00028" data-start="{" data-end="};"> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"><a class="line" href="structneorv32__uart__t.html"> 28</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__uart__t.html#a0a6227aeea38335d2b9a9da46b35451b"> 29</a></span> uint32_t <a class="code hl_variable" href="structneorv32__uart__t.html#a0a6227aeea38335d2b9a9da46b35451b">CTRL</a>; </div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__uart__t.html#a38eec82aae9ed522a0d2afb9a9560036"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__uart__t.html#a38eec82aae9ed522a0d2afb9a9560036">DATA</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span>} <a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a>;</div> +</div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#a4c880a6b27e46f459e750425258b1bdb"> 34</a></span><span class="preprocessor">#define NEORV32_UART0 ((neorv32_uart_t*) (NEORV32_UART0_BASE))</span></div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#aa2a9ded4523f001bf69935c80247fa2d"> 37</a></span><span class="preprocessor">#define NEORV32_UART1 ((neorv32_uart_t*) (NEORV32_UART1_BASE))</span></div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> </div> +<div class="foldopen" id="foldopen00040" data-start="{" data-end="};"> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afc"> 40</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afc">NEORV32_UART_CTRL_enum</a> {</div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca38f6c0e5991f8f80159a388c1080f7c2"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca38f6c0e5991f8f80159a388c1080f7c2">UART_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca42ed376220259ab22c6f837d08273ef1"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca42ed376220259ab22c6f837d08273ef1">UART_CTRL_SIM_MODE</a> = 1, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcacab78fcd440167c5a2c0f5d300c8f07c"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcacab78fcd440167c5a2c0f5d300c8f07c">UART_CTRL_HWFC_EN</a> = 2, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca1ddbca448bb30c77c42499fff1312183"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca1ddbca448bb30c77c42499fff1312183">UART_CTRL_PRSC0</a> = 3, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9c1d8e8763a653339210ff4e6e3067d2"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9c1d8e8763a653339210ff4e6e3067d2">UART_CTRL_PRSC1</a> = 4, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca8afd60e4bd3854fab623b91fa4f33f70"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca8afd60e4bd3854fab623b91fa4f33f70">UART_CTRL_PRSC2</a> = 5, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcad38432e7e050276d4667daf92c1e3fd5"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcad38432e7e050276d4667daf92c1e3fd5">UART_CTRL_BAUD0</a> = 6, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca1e702002402897eca82bf398504bc439"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca1e702002402897eca82bf398504bc439">UART_CTRL_BAUD1</a> = 7, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca36266026e11f22aca1584bd81cd38cd6"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca36266026e11f22aca1584bd81cd38cd6">UART_CTRL_BAUD2</a> = 8, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca58190cd41c2ce69512bea10740d35276"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca58190cd41c2ce69512bea10740d35276">UART_CTRL_BAUD3</a> = 9, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca81ea805f01b93a59664823b940c7a424"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca81ea805f01b93a59664823b940c7a424">UART_CTRL_BAUD4</a> = 10, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca5da1d6007af0265fe48ace8469e07833"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca5da1d6007af0265fe48ace8469e07833">UART_CTRL_BAUD5</a> = 11, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9ac3c1e23d684cb2f67060d6ebe1fa63"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9ac3c1e23d684cb2f67060d6ebe1fa63">UART_CTRL_BAUD6</a> = 12, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9c12648f7f058f444db434cd8a8d854e"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9c12648f7f058f444db434cd8a8d854e">UART_CTRL_BAUD7</a> = 13, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca09c311eb1f6b38500e6fcbb6ad9dd9ff"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca09c311eb1f6b38500e6fcbb6ad9dd9ff">UART_CTRL_BAUD8</a> = 14, </div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca697321bddeaa2cac1ea034c418be540e"> 56</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca697321bddeaa2cac1ea034c418be540e">UART_CTRL_BAUD9</a> = 15, </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca2015dd85e361aa0476e847953b62baff"> 58</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca2015dd85e361aa0476e847953b62baff">UART_CTRL_RX_NEMPTY</a> = 16, </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca3fc934d0ce6b36e3e131c6682db22247"> 59</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca3fc934d0ce6b36e3e131c6682db22247">UART_CTRL_RX_HALF</a> = 17, </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca47c44fa21e51401621c28019025c1166"> 60</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca47c44fa21e51401621c28019025c1166">UART_CTRL_RX_FULL</a> = 18, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcac5c044233b6c4162cf862f3d9831ef46"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcac5c044233b6c4162cf862f3d9831ef46">UART_CTRL_TX_EMPTY</a> = 19, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca5b0e40ab30bdb198f496d09e89d2d0d9"> 62</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca5b0e40ab30bdb198f496d09e89d2d0d9">UART_CTRL_TX_NHALF</a> = 20, </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca36b4195e5d1f12e1fd1a0d30cad0e411"> 63</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca36b4195e5d1f12e1fd1a0d30cad0e411">UART_CTRL_TX_FULL</a> = 21, </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca569ea830518914c5330fa14680b02851"> 65</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca569ea830518914c5330fa14680b02851">UART_CTRL_IRQ_RX_NEMPTY</a> = 22, </div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcaa219ea3ed5b21f5023bbc5ffa5c5f175"> 66</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcaa219ea3ed5b21f5023bbc5ffa5c5f175">UART_CTRL_IRQ_RX_HALF</a> = 23, </div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcae5f01868b170d71a5f3064023c96a82a"> 67</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcae5f01868b170d71a5f3064023c96a82a">UART_CTRL_IRQ_RX_FULL</a> = 24, </div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca15b9fca73877aad446a8cd338e228e2c"> 68</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca15b9fca73877aad446a8cd338e228e2c">UART_CTRL_IRQ_TX_EMPTY</a> = 25, </div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca726b73ef9c44ccc1a45a4230a8bda9d1"> 69</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca726b73ef9c44ccc1a45a4230a8bda9d1">UART_CTRL_IRQ_TX_NHALF</a> = 26, </div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcaefbef37247d88a7e38e1c53b8a33ed33"> 71</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcaefbef37247d88a7e38e1c53b8a33ed33">UART_CTRL_RX_CLR</a> = 28, </div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca408412a32673cc7f6ea70682e3e61431"> 72</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca408412a32673cc7f6ea70682e3e61431">UART_CTRL_TX_CLR</a> = 29, </div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca81a52e0b81018f2cf43e64d74caba632"> 73</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca81a52e0b81018f2cf43e64d74caba632">UART_CTRL_RX_OVER</a> = 30, </div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca0eb636d8b7961d7073c5c7341b5bbe25">UART_CTRL_TX_BUSY</a> = 31 </div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca0eb636d8b7961d7073c5c7341b5bbe25"> 75</a></span>};</div> +</div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span> </div> +<div class="foldopen" id="foldopen00078" data-start="{" data-end="};"> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2"> 78</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2">NEORV32_UART_DATA_enum</a> {</div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2ae70e9f6cd69af724932e79ea7e7f7195"> 79</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2ae70e9f6cd69af724932e79ea7e7f7195">UART_DATA_RTX_LSB</a> = 0, </div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a19926d013ca202645d38f2c704782ebb"> 80</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a19926d013ca202645d38f2c704782ebb">UART_DATA_RTX_MSB</a> = 7, </div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a43b296e86d1f2ec7400d57655c3180ef"> 82</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a43b296e86d1f2ec7400d57655c3180ef">UART_DATA_RX_FIFO_SIZE_LSB</a> = 8, </div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a81a82ac0dc5c8c8d7af21553288e3225"> 83</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a81a82ac0dc5c8c8d7af21553288e3225">UART_DATA_RX_FIFO_SIZE_MSB</a> = 11, </div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a6d718ad0bb82a5cb053c117cd2d6ca8e"> 85</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a6d718ad0bb82a5cb053c117cd2d6ca8e">UART_DATA_TX_FIFO_SIZE_LSB</a> = 12, </div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"><a class="line" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2ada92cbbe278e3e0592eba58c97699529"> 86</a></span> <a class="code hl_enumvalue" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2ada92cbbe278e3e0592eba58c97699529">UART_DATA_TX_FIFO_SIZE_MSB</a> = 15, </div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span>};</div> +</div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__uart_8h.html#abef6415b0391dc055713404312196682">neorv32_uart_available</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__uart_8h.html#af85fb929c912d3edef3d86ffa833982a">neorv32_uart_get_rx_fifo_depth</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__uart_8h.html#a031e3e27c8783c299623468020a22b0e">neorv32_uart_get_tx_fifo_depth</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#a9cdec36f2723c5373664022d1b68b841">neorv32_uart_setup</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, uint32_t baudrate, uint32_t irq_mask);</div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#afa0533e81d53057c36f4997a2dbbe2bc">neorv32_uart_enable</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#ae18804ccd29ec2fd1cc06e9ce985b704">neorv32_uart_disable</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#a734b610f4cd1b474d7763f9700a715ec">neorv32_uart_rtscts_enable</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#a7b2f924ef4554b1fa90433c38d97558d">neorv32_uart_rtscts_disable</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#a9bc7bb94a50b74e1145b78eec6094129">neorv32_uart_putc</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, <span class="keywordtype">char</span> c);</div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#afe0de59c14faff1e0c890d5465be25f0">neorv32_uart_rx_clear</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#a27971954262a2fd1f21d3bf1ba27e87c">neorv32_uart_tx_clear</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__uart_8h.html#aa7bef48a58e044c246b8c4ad32864502">neorv32_uart_tx_busy</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span><span class="keywordtype">char</span> <a class="code hl_function" href="neorv32__uart_8h.html#a2efd432f63b8d36d44263d0b1f39a6dc">neorv32_uart_getc</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__uart_8h.html#adedb0e07efb232717534017167a5be98">neorv32_uart_char_received</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span><span class="keywordtype">char</span> <a class="code hl_function" href="neorv32__uart_8h.html#aa490df3a9bb2aa3215fa6fad34ffe7d1">neorv32_uart_char_received_get</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx);</div> +<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#a45a07d5e71677162baaa1025759c67a2">neorv32_uart_puts</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, <span class="keyword">const</span> <span class="keywordtype">char</span> *s);</div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#a8714cdb1c04d94bec322c6215ea10238">neorv32_uart_vprintf</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, <span class="keyword">const</span> <span class="keywordtype">char</span> *format, va_list args);</div> +<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__uart_8h.html#ab8c1f9f451def9126ab2749d7bbe50d9">neorv32_uart_printf</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, <span class="keyword">const</span> <span class="keywordtype">char</span> *format, ...);</div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__uart_8h.html#ac429964878bd6deab61d9ed8659bca75">neorv32_uart_scan</a>(<a class="code hl_struct" href="structneorv32__uart__t.html">neorv32_uart_t</a> *UARTx, <span class="keywordtype">char</span> *buffer, <span class="keywordtype">int</span> max_size, <span class="keywordtype">int</span> echo);</div> +<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span><span class="preprocessor">#define neorv32_uart0_available() neorv32_uart_available(NEORV32_UART0)</span></div> +<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span><span class="preprocessor">#define neorv32_uart0_get_rx_fifo_depth() neorv32_uart_get_rx_fifo_depth(NEORV32_UART0)</span></div> +<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span><span class="preprocessor">#define neorv32_uart0_get_tx_fifo_depth() neorv32_uart_get_tx_fifo_depth(NEORV32_UART0)</span></div> +<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span><span class="preprocessor">#define neorv32_uart0_setup(baudrate, irq_mask) neorv32_uart_setup(NEORV32_UART0, baudrate, irq_mask)</span></div> +<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span><span class="preprocessor">#define neorv32_uart0_disable() neorv32_uart_disable(NEORV32_UART0)</span></div> +<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span><span class="preprocessor">#define neorv32_uart0_enable() neorv32_uart_enable(NEORV32_UART0)</span></div> +<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"> 127</span><span class="preprocessor">#define neorv32_uart0_rtscts_disable() neorv32_uart_rtscts_disable(NEORV32_UART0)</span></div> +<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"> 128</span><span class="preprocessor">#define neorv32_uart0_rtscts_enable() neorv32_uart_rtscts_enable(NEORV32_UART0)</span></div> +<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span><span class="preprocessor">#define neorv32_uart0_putc(c) neorv32_uart_putc(NEORV32_UART0, c)</span></div> +<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span><span class="preprocessor">#define neorv32_uart0_rx_clear() neorv32_uart_rx_clear(NEORV32_UART0)</span></div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span><span class="preprocessor">#define neorv32_uart0_tx_clear() neorv32_uart_tx_clear(NEORV32_UART0)</span></div> +<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span><span class="preprocessor">#define neorv32_uart0_tx_busy() neorv32_uart_tx_busy(NEORV32_UART0)</span></div> +<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span><span class="preprocessor">#define neorv32_uart0_getc() neorv32_uart_getc(NEORV32_UART0)</span></div> +<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"> 134</span><span class="preprocessor">#define neorv32_uart0_char_received() neorv32_uart_char_received(NEORV32_UART0)</span></div> +<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"> 135</span><span class="preprocessor">#define neorv32_uart0_char_received_get() neorv32_uart_char_received_get(NEORV32_UART0)</span></div> +<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"> 136</span><span class="preprocessor">#define neorv32_uart0_puts(s) neorv32_uart_puts(NEORV32_UART0, s)</span></div> +<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"> 137</span><span class="preprocessor">#define neorv32_uart0_printf(...) neorv32_uart_printf(NEORV32_UART0, __VA_ARGS__)</span></div> +<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"> 138</span><span class="preprocessor">#define neorv32_uart0_scan(buffer, max_size, echo) neorv32_uart_scan(NEORV32_UART0, buffer, max_size, echo)</span></div> +<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"> 139</span> </div> +<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span><span class="preprocessor">#define neorv32_uart1_available() neorv32_uart_available(NEORV32_UART1)</span></div> +<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span><span class="preprocessor">#define neorv32_uart1_get_rx_fifo_depth() neorv32_uart_get_rx_fifo_depth(NEORV32_UART1)</span></div> +<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span><span class="preprocessor">#define neorv32_uart1_get_tx_fifo_depth() neorv32_uart_get_tx_fifo_depth(NEORV32_UART1)</span></div> +<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"> 143</span><span class="preprocessor">#define neorv32_uart1_setup(baudrate, irq_mask) neorv32_uart_setup(NEORV32_UART1, baudrate, irq_mask)</span></div> +<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span><span class="preprocessor">#define neorv32_uart1_disable() neorv32_uart_disable(NEORV32_UART1)</span></div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span><span class="preprocessor">#define neorv32_uart1_enable() neorv32_uart_enable(NEORV32_UART1)</span></div> +<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span><span class="preprocessor">#define neorv32_uart1_rtscts_disable() neorv32_uart_rtscts_disable(NEORV32_UART1)</span></div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span><span class="preprocessor">#define neorv32_uart1_rtscts_enable() neorv32_uart_rtscts_enable(NEORV32_UART1)</span></div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span><span class="preprocessor">#define neorv32_uart1_putc(c) neorv32_uart_putc(NEORV32_UART1, c)</span></div> +<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span><span class="preprocessor">#define neorv32_uart1_rx_clear() neorv32_uart_rx_clear(NEORV32_UART1)</span></div> +<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span><span class="preprocessor">#define neorv32_uart1_tx_clear() neorv32_uart_tx_clear(NEORV32_UART1)</span></div> +<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span><span class="preprocessor">#define neorv32_uart1_tx_busy() neorv32_uart_tx_busy(NEORV32_UART1)</span></div> +<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span><span class="preprocessor">#define neorv32_uart1_getc() neorv32_uart_getc(NEORV32_UART1)</span></div> +<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span><span class="preprocessor">#define neorv32_uart1_char_received() neorv32_uart_char_received(NEORV32_UART1)</span></div> +<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"> 154</span><span class="preprocessor">#define neorv32_uart1_char_received_get() neorv32_uart_char_received_get(NEORV32_UART1)</span></div> +<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span><span class="preprocessor">#define neorv32_uart1_puts(s) neorv32_uart_puts(NEORV32_UART1, s)</span></div> +<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span><span class="preprocessor">#define neorv32_uart1_printf(...) neorv32_uart_printf(NEORV32_UART1, __VA_ARGS__)</span></div> +<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span><span class="preprocessor">#define neorv32_uart1_scan(buffer, max_size, echo) neorv32_uart_scan(NEORV32_UART1, buffer, max_size, echo)</span></div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_uart_h</span></div> +<div class="ttc" id="aneorv32__uart_8h_html_a031e3e27c8783c299623468020a22b0e"><div class="ttname"><a href="neorv32__uart_8h.html#a031e3e27c8783c299623468020a22b0e">neorv32_uart_get_tx_fifo_depth</a></div><div class="ttdeci">int neorv32_uart_get_tx_fifo_depth(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:124</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_a27971954262a2fd1f21d3bf1ba27e87c"><div class="ttname"><a href="neorv32__uart_8h.html#a27971954262a2fd1f21d3bf1ba27e87c">neorv32_uart_tx_clear</a></div><div class="ttdeci">void neorv32_uart_tx_clear(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:205</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_a2efd432f63b8d36d44263d0b1f39a6dc"><div class="ttname"><a href="neorv32__uart_8h.html#a2efd432f63b8d36d44263d0b1f39a6dc">neorv32_uart_getc</a></div><div class="ttdeci">char neorv32_uart_getc(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:236</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_a45a07d5e71677162baaa1025759c67a2"><div class="ttname"><a href="neorv32__uart_8h.html#a45a07d5e71677162baaa1025759c67a2">neorv32_uart_puts</a></div><div class="ttdeci">void neorv32_uart_puts(neorv32_uart_t *UARTx, const char *s)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:289</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_a734b610f4cd1b474d7763f9700a715ec"><div class="ttname"><a href="neorv32__uart_8h.html#a734b610f4cd1b474d7763f9700a715ec">neorv32_uart_rtscts_enable</a></div><div class="ttdeci">void neorv32_uart_rtscts_enable(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:158</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_a7b2f924ef4554b1fa90433c38d97558d"><div class="ttname"><a href="neorv32__uart_8h.html#a7b2f924ef4554b1fa90433c38d97558d">neorv32_uart_rtscts_disable</a></div><div class="ttdeci">void neorv32_uart_rtscts_disable(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:169</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_a8714cdb1c04d94bec322c6215ea10238"><div class="ttname"><a href="neorv32__uart_8h.html#a8714cdb1c04d94bec322c6215ea10238">neorv32_uart_vprintf</a></div><div class="ttdeci">void neorv32_uart_vprintf(neorv32_uart_t *UARTx, const char *format, va_list args)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:311</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_a9bc7bb94a50b74e1145b78eec6094129"><div class="ttname"><a href="neorv32__uart_8h.html#a9bc7bb94a50b74e1145b78eec6094129">neorv32_uart_putc</a></div><div class="ttdeci">void neorv32_uart_putc(neorv32_uart_t *UARTx, char c)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:181</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_a9cdec36f2723c5373664022d1b68b841"><div class="ttname"><a href="neorv32__uart_8h.html#a9cdec36f2723c5373664022d1b68b841">neorv32_uart_setup</a></div><div class="ttdeci">void neorv32_uart_setup(neorv32_uart_t *UARTx, uint32_t baudrate, uint32_t irq_mask)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:51</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_aa490df3a9bb2aa3215fa6fad34ffe7d1"><div class="ttname"><a href="neorv32__uart_8h.html#aa490df3a9bb2aa3215fa6fad34ffe7d1">neorv32_uart_char_received_get</a></div><div class="ttdeci">char neorv32_uart_char_received_get(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:275</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_aa7bef48a58e044c246b8c4ad32864502"><div class="ttname"><a href="neorv32__uart_8h.html#aa7bef48a58e044c246b8c4ad32864502">neorv32_uart_tx_busy</a></div><div class="ttdeci">int neorv32_uart_tx_busy(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:217</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ab8c1f9f451def9126ab2749d7bbe50d9"><div class="ttname"><a href="neorv32__uart_8h.html#ab8c1f9f451def9126ab2749d7bbe50d9">neorv32_uart_printf</a></div><div class="ttdeci">void neorv32_uart_printf(neorv32_uart_t *UARTx, const char *format,...)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:386</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_abef6415b0391dc055713404312196682"><div class="ttname"><a href="neorv32__uart_8h.html#abef6415b0391dc055713404312196682">neorv32_uart_available</a></div><div class="ttdeci">int neorv32_uart_available(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:30</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ac429964878bd6deab61d9ed8659bca75"><div class="ttname"><a href="neorv32__uart_8h.html#ac429964878bd6deab61d9ed8659bca75">neorv32_uart_scan</a></div><div class="ttdeci">int neorv32_uart_scan(neorv32_uart_t *UARTx, char *buffer, int max_size, int echo)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:406</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afc"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afc">NEORV32_UART_CTRL_enum</a></div><div class="ttdeci">NEORV32_UART_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:40</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca09c311eb1f6b38500e6fcbb6ad9dd9ff"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca09c311eb1f6b38500e6fcbb6ad9dd9ff">UART_CTRL_BAUD8</a></div><div class="ttdeci">@ UART_CTRL_BAUD8</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:55</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca0eb636d8b7961d7073c5c7341b5bbe25"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca0eb636d8b7961d7073c5c7341b5bbe25">UART_CTRL_TX_BUSY</a></div><div class="ttdeci">@ UART_CTRL_TX_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:74</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca15b9fca73877aad446a8cd338e228e2c"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca15b9fca73877aad446a8cd338e228e2c">UART_CTRL_IRQ_TX_EMPTY</a></div><div class="ttdeci">@ UART_CTRL_IRQ_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:68</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca1ddbca448bb30c77c42499fff1312183"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca1ddbca448bb30c77c42499fff1312183">UART_CTRL_PRSC0</a></div><div class="ttdeci">@ UART_CTRL_PRSC0</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:44</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca1e702002402897eca82bf398504bc439"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca1e702002402897eca82bf398504bc439">UART_CTRL_BAUD1</a></div><div class="ttdeci">@ UART_CTRL_BAUD1</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:48</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca2015dd85e361aa0476e847953b62baff"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca2015dd85e361aa0476e847953b62baff">UART_CTRL_RX_NEMPTY</a></div><div class="ttdeci">@ UART_CTRL_RX_NEMPTY</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:58</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca36266026e11f22aca1584bd81cd38cd6"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca36266026e11f22aca1584bd81cd38cd6">UART_CTRL_BAUD2</a></div><div class="ttdeci">@ UART_CTRL_BAUD2</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:49</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca36b4195e5d1f12e1fd1a0d30cad0e411"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca36b4195e5d1f12e1fd1a0d30cad0e411">UART_CTRL_TX_FULL</a></div><div class="ttdeci">@ UART_CTRL_TX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:63</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca38f6c0e5991f8f80159a388c1080f7c2"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca38f6c0e5991f8f80159a388c1080f7c2">UART_CTRL_EN</a></div><div class="ttdeci">@ UART_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:41</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca3fc934d0ce6b36e3e131c6682db22247"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca3fc934d0ce6b36e3e131c6682db22247">UART_CTRL_RX_HALF</a></div><div class="ttdeci">@ UART_CTRL_RX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:59</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca408412a32673cc7f6ea70682e3e61431"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca408412a32673cc7f6ea70682e3e61431">UART_CTRL_TX_CLR</a></div><div class="ttdeci">@ UART_CTRL_TX_CLR</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:72</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca42ed376220259ab22c6f837d08273ef1"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca42ed376220259ab22c6f837d08273ef1">UART_CTRL_SIM_MODE</a></div><div class="ttdeci">@ UART_CTRL_SIM_MODE</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:42</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca47c44fa21e51401621c28019025c1166"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca47c44fa21e51401621c28019025c1166">UART_CTRL_RX_FULL</a></div><div class="ttdeci">@ UART_CTRL_RX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:60</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca569ea830518914c5330fa14680b02851"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca569ea830518914c5330fa14680b02851">UART_CTRL_IRQ_RX_NEMPTY</a></div><div class="ttdeci">@ UART_CTRL_IRQ_RX_NEMPTY</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:65</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca58190cd41c2ce69512bea10740d35276"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca58190cd41c2ce69512bea10740d35276">UART_CTRL_BAUD3</a></div><div class="ttdeci">@ UART_CTRL_BAUD3</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:50</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca5b0e40ab30bdb198f496d09e89d2d0d9"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca5b0e40ab30bdb198f496d09e89d2d0d9">UART_CTRL_TX_NHALF</a></div><div class="ttdeci">@ UART_CTRL_TX_NHALF</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:62</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca5da1d6007af0265fe48ace8469e07833"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca5da1d6007af0265fe48ace8469e07833">UART_CTRL_BAUD5</a></div><div class="ttdeci">@ UART_CTRL_BAUD5</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:52</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca697321bddeaa2cac1ea034c418be540e"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca697321bddeaa2cac1ea034c418be540e">UART_CTRL_BAUD9</a></div><div class="ttdeci">@ UART_CTRL_BAUD9</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:56</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca726b73ef9c44ccc1a45a4230a8bda9d1"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca726b73ef9c44ccc1a45a4230a8bda9d1">UART_CTRL_IRQ_TX_NHALF</a></div><div class="ttdeci">@ UART_CTRL_IRQ_TX_NHALF</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:69</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca81a52e0b81018f2cf43e64d74caba632"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca81a52e0b81018f2cf43e64d74caba632">UART_CTRL_RX_OVER</a></div><div class="ttdeci">@ UART_CTRL_RX_OVER</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:73</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca81ea805f01b93a59664823b940c7a424"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca81ea805f01b93a59664823b940c7a424">UART_CTRL_BAUD4</a></div><div class="ttdeci">@ UART_CTRL_BAUD4</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:51</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca8afd60e4bd3854fab623b91fa4f33f70"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca8afd60e4bd3854fab623b91fa4f33f70">UART_CTRL_PRSC2</a></div><div class="ttdeci">@ UART_CTRL_PRSC2</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:46</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca9ac3c1e23d684cb2f67060d6ebe1fa63"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9ac3c1e23d684cb2f67060d6ebe1fa63">UART_CTRL_BAUD6</a></div><div class="ttdeci">@ UART_CTRL_BAUD6</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:53</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca9c12648f7f058f444db434cd8a8d854e"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9c12648f7f058f444db434cd8a8d854e">UART_CTRL_BAUD7</a></div><div class="ttdeci">@ UART_CTRL_BAUD7</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:54</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afca9c1d8e8763a653339210ff4e6e3067d2"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afca9c1d8e8763a653339210ff4e6e3067d2">UART_CTRL_PRSC1</a></div><div class="ttdeci">@ UART_CTRL_PRSC1</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:45</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afcaa219ea3ed5b21f5023bbc5ffa5c5f175"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcaa219ea3ed5b21f5023bbc5ffa5c5f175">UART_CTRL_IRQ_RX_HALF</a></div><div class="ttdeci">@ UART_CTRL_IRQ_RX_HALF</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:66</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afcac5c044233b6c4162cf862f3d9831ef46"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcac5c044233b6c4162cf862f3d9831ef46">UART_CTRL_TX_EMPTY</a></div><div class="ttdeci">@ UART_CTRL_TX_EMPTY</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:61</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afcacab78fcd440167c5a2c0f5d300c8f07c"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcacab78fcd440167c5a2c0f5d300c8f07c">UART_CTRL_HWFC_EN</a></div><div class="ttdeci">@ UART_CTRL_HWFC_EN</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:43</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afcad38432e7e050276d4667daf92c1e3fd5"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcad38432e7e050276d4667daf92c1e3fd5">UART_CTRL_BAUD0</a></div><div class="ttdeci">@ UART_CTRL_BAUD0</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:47</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afcae5f01868b170d71a5f3064023c96a82a"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcae5f01868b170d71a5f3064023c96a82a">UART_CTRL_IRQ_RX_FULL</a></div><div class="ttdeci">@ UART_CTRL_IRQ_RX_FULL</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:67</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ad9f75f453beca1619344bb4213352afcaefbef37247d88a7e38e1c53b8a33ed33"><div class="ttname"><a href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afcaefbef37247d88a7e38e1c53b8a33ed33">UART_CTRL_RX_CLR</a></div><div class="ttdeci">@ UART_CTRL_RX_CLR</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:71</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_adcf35350a9ea18a59c32c35f528643f2"><div class="ttname"><a href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2">NEORV32_UART_DATA_enum</a></div><div class="ttdeci">NEORV32_UART_DATA_enum</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:78</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_adcf35350a9ea18a59c32c35f528643f2a19926d013ca202645d38f2c704782ebb"><div class="ttname"><a href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a19926d013ca202645d38f2c704782ebb">UART_DATA_RTX_MSB</a></div><div class="ttdeci">@ UART_DATA_RTX_MSB</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:80</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_adcf35350a9ea18a59c32c35f528643f2a43b296e86d1f2ec7400d57655c3180ef"><div class="ttname"><a href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a43b296e86d1f2ec7400d57655c3180ef">UART_DATA_RX_FIFO_SIZE_LSB</a></div><div class="ttdeci">@ UART_DATA_RX_FIFO_SIZE_LSB</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:82</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_adcf35350a9ea18a59c32c35f528643f2a6d718ad0bb82a5cb053c117cd2d6ca8e"><div class="ttname"><a href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a6d718ad0bb82a5cb053c117cd2d6ca8e">UART_DATA_TX_FIFO_SIZE_LSB</a></div><div class="ttdeci">@ UART_DATA_TX_FIFO_SIZE_LSB</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:85</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_adcf35350a9ea18a59c32c35f528643f2a81a82ac0dc5c8c8d7af21553288e3225"><div class="ttname"><a href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2a81a82ac0dc5c8c8d7af21553288e3225">UART_DATA_RX_FIFO_SIZE_MSB</a></div><div class="ttdeci">@ UART_DATA_RX_FIFO_SIZE_MSB</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:83</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_adcf35350a9ea18a59c32c35f528643f2ada92cbbe278e3e0592eba58c97699529"><div class="ttname"><a href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2ada92cbbe278e3e0592eba58c97699529">UART_DATA_TX_FIFO_SIZE_MSB</a></div><div class="ttdeci">@ UART_DATA_TX_FIFO_SIZE_MSB</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:86</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_adcf35350a9ea18a59c32c35f528643f2ae70e9f6cd69af724932e79ea7e7f7195"><div class="ttname"><a href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2ae70e9f6cd69af724932e79ea7e7f7195">UART_DATA_RTX_LSB</a></div><div class="ttdeci">@ UART_DATA_RTX_LSB</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:79</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_adedb0e07efb232717534017167a5be98"><div class="ttname"><a href="neorv32__uart_8h.html#adedb0e07efb232717534017167a5be98">neorv32_uart_char_received</a></div><div class="ttdeci">int neorv32_uart_char_received(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:255</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_ae18804ccd29ec2fd1cc06e9ce985b704"><div class="ttname"><a href="neorv32__uart_8h.html#ae18804ccd29ec2fd1cc06e9ce985b704">neorv32_uart_disable</a></div><div class="ttdeci">void neorv32_uart_disable(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:147</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_af85fb929c912d3edef3d86ffa833982a"><div class="ttname"><a href="neorv32__uart_8h.html#af85fb929c912d3edef3d86ffa833982a">neorv32_uart_get_rx_fifo_depth</a></div><div class="ttdeci">int neorv32_uart_get_rx_fifo_depth(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:110</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_afa0533e81d53057c36f4997a2dbbe2bc"><div class="ttname"><a href="neorv32__uart_8h.html#afa0533e81d53057c36f4997a2dbbe2bc">neorv32_uart_enable</a></div><div class="ttdeci">void neorv32_uart_enable(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:136</div></div> +<div class="ttc" id="aneorv32__uart_8h_html_afe0de59c14faff1e0c890d5465be25f0"><div class="ttname"><a href="neorv32__uart_8h.html#afe0de59c14faff1e0c890d5465be25f0">neorv32_uart_rx_clear</a></div><div class="ttdeci">void neorv32_uart_rx_clear(neorv32_uart_t *UARTx)</div><div class="ttdef"><b>Definition</b> neorv32_uart.c:194</div></div> +<div class="ttc" id="astructneorv32__uart__t_html"><div class="ttname"><a href="structneorv32__uart__t.html">neorv32_uart_t</a></div><div class="ttdef"><b>Definition</b> neorv32_uart.h:28</div></div> +<div class="ttc" id="astructneorv32__uart__t_html_a0a6227aeea38335d2b9a9da46b35451b"><div class="ttname"><a href="structneorv32__uart__t.html#a0a6227aeea38335d2b9a9da46b35451b">neorv32_uart_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:29</div></div> +<div class="ttc" id="astructneorv32__uart__t_html_a38eec82aae9ed522a0d2afb9a9560036"><div class="ttname"><a href="structneorv32__uart__t.html#a38eec82aae9ed522a0d2afb9a9560036">neorv32_uart_t::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition</b> neorv32_uart.h:30</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated 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id="r_a459a918c5a86c0167e8c748352d39827"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a459a918c5a86c0167e8c748352d39827">neorv32_wdt_available</a> (void)</td></tr> +<tr class="separator:a459a918c5a86c0167e8c748352d39827"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2aa72608191d34ef41c5f545988ff400" id="r_a2aa72608191d34ef41c5f545988ff400"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2aa72608191d34ef41c5f545988ff400">neorv32_wdt_setup</a> (uint32_t timeout, int lock, int debug_en, int sleep_en, int strict)</td></tr> +<tr class="separator:a2aa72608191d34ef41c5f545988ff400"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aba52520582392a671e2b717715a330b2" id="r_aba52520582392a671e2b717715a330b2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aba52520582392a671e2b717715a330b2">neorv32_wdt_disable</a> (void)</td></tr> +<tr class="separator:aba52520582392a671e2b717715a330b2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae4e86c42ed45eefdec43d9ece08b98a4" id="r_ae4e86c42ed45eefdec43d9ece08b98a4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae4e86c42ed45eefdec43d9ece08b98a4">neorv32_wdt_feed</a> (uint32_t password)</td></tr> +<tr class="separator:ae4e86c42ed45eefdec43d9ece08b98a4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a80fa8d178d18c9b02d32d93e815b532e" id="r_a80fa8d178d18c9b02d32d93e815b532e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a80fa8d178d18c9b02d32d93e815b532e">neorv32_wdt_get_cause</a> (void)</td></tr> +<tr class="separator:a80fa8d178d18c9b02d32d93e815b532e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Direct Memory Access Controller (DMA) HW driver source file. </p> +<p>Watchdog Timer (WDT) HW driver source file.</p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the DMA controller was synthesized (IO_DMA_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a></dd></dl> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the WDT unit was synthesized (IO_WDT_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a459a918c5a86c0167e8c748352d39827" name="a459a918c5a86c0167e8c748352d39827"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a459a918c5a86c0167e8c748352d39827">&#9670;&#160;</a></span>neorv32_wdt_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_wdt_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if WDT unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if WDT was not synthesized, 1 if WDT is available. </dd></dl> + +</div> +</div> +<a id="aba52520582392a671e2b717715a330b2" name="aba52520582392a671e2b717715a330b2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aba52520582392a671e2b717715a330b2">&#9670;&#160;</a></span>neorv32_wdt_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_wdt_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable watchdog timer.</p> +<dl class="section return"><dt>Returns</dt><dd>Returns 0 if WDT is really deactivated, -1 otherwise. </dd></dl> + +</div> +</div> +<a id="ae4e86c42ed45eefdec43d9ece08b98a4" name="ae4e86c42ed45eefdec43d9ece08b98a4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae4e86c42ed45eefdec43d9ece08b98a4">&#9670;&#160;</a></span>neorv32_wdt_feed()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_wdt_feed </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>password</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Feed watchdog (reset timeout counter).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">password</td><td>Password for WDT reset. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a80fa8d178d18c9b02d32d93e815b532e" name="a80fa8d178d18c9b02d32d93e815b532e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a80fa8d178d18c9b02d32d93e815b532e">&#9670;&#160;</a></span>neorv32_wdt_get_cause()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_wdt_get_cause </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get cause of last system reset.</p> +<dl class="section return"><dt>Returns</dt><dd>Cause of last reset (<a class="el" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049">NEORV32_WDT_RCAUSE_enum</a>). </dd></dl> + +</div> +</div> +<a id="a2aa72608191d34ef41c5f545988ff400" name="a2aa72608191d34ef41c5f545988ff400"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2aa72608191d34ef41c5f545988ff400">&#9670;&#160;</a></span>neorv32_wdt_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_wdt_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>timeout</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>lock</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>debug_en</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>sleep_en</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>strict</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure and enable watchdog timer. The WDT control register bits are listed in <a class="el" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23e">NEORV32_WDT_CTRL_enum</a>.</p> +<dl class="section warning"><dt>Warning</dt><dd>Once the lock bit is set it can only be removed by a hardware reset!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">timeout</td><td>24-bit timeout value. A WDT IRQ is triggered when the internal counter reaches 'timeout/2'. A system hardware reset is triggered when the internal counter reaches 'timeout'. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">lock</td><td>Control register will be locked when 1 (until next reset). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">debug_en</td><td>Allow watchdog to continue operation even when CPU is in debug mode. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">sleep_en</td><td>Allow watchdog to continue operation even when CPU is in sleep mode. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">strict</td><td>Force hardware reset if reset password is incorrect or if trying to alter a locked configuration. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" 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valign="bottom"><a class="el" href="structneorv32__wdt__t.html">neorv32_wdt_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:af2a2bd9c74bdba1b46bd92025bd00ab6" id="r_af2a2bd9c74bdba1b46bd92025bd00ab6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af2a2bd9c74bdba1b46bd92025bd00ab6">WDT_PASSWORD</a>&#160;&#160;&#160;(0x709D1AB3)</td></tr> +<tr class="separator:af2a2bd9c74bdba1b46bd92025bd00ab6"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a> +Enumerations</h2></td></tr> +<tr class="memitem:a70098b4ee893774864536fb4100ff049" id="r_a70098b4ee893774864536fb4100ff049"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a70098b4ee893774864536fb4100ff049">NEORV32_WDT_RCAUSE_enum</a> { <a class="el" href="#a70098b4ee893774864536fb4100ff049ac5fc25cdc29c248b1a570b6095ddded0">WDT_RCAUSE_EXT</a> = 0b00 +, <a class="el" href="#a70098b4ee893774864536fb4100ff049a764a7797f17d82f619a6d30c0878bf1e">WDT_RCAUSE_OCD</a> = 0b01 +, <a class="el" href="#a70098b4ee893774864536fb4100ff049a7273d24bb65d3f40c1d289ce5cbc1a40">WDT_RCAUSE_TMO</a> = 0b10 +, <a class="el" href="#a70098b4ee893774864536fb4100ff049a10999a782ffc2c26f601615f76121376">WDT_RCAUSE_ACC</a> = 0b11 + }</td></tr> +<tr class="separator:a70098b4ee893774864536fb4100ff049"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:a459a918c5a86c0167e8c748352d39827" id="r_a459a918c5a86c0167e8c748352d39827"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a459a918c5a86c0167e8c748352d39827">neorv32_wdt_available</a> (void)</td></tr> +<tr class="separator:a459a918c5a86c0167e8c748352d39827"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2aa72608191d34ef41c5f545988ff400" id="r_a2aa72608191d34ef41c5f545988ff400"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2aa72608191d34ef41c5f545988ff400">neorv32_wdt_setup</a> (uint32_t timeout, int lock, int debug_en, int sleep_en, int strict)</td></tr> +<tr class="separator:a2aa72608191d34ef41c5f545988ff400"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aba52520582392a671e2b717715a330b2" id="r_aba52520582392a671e2b717715a330b2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aba52520582392a671e2b717715a330b2">neorv32_wdt_disable</a> (void)</td></tr> +<tr class="separator:aba52520582392a671e2b717715a330b2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae4e86c42ed45eefdec43d9ece08b98a4" id="r_ae4e86c42ed45eefdec43d9ece08b98a4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae4e86c42ed45eefdec43d9ece08b98a4">neorv32_wdt_feed</a> (uint32_t password)</td></tr> +<tr class="separator:ae4e86c42ed45eefdec43d9ece08b98a4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a80fa8d178d18c9b02d32d93e815b532e" id="r_a80fa8d178d18c9b02d32d93e815b532e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a80fa8d178d18c9b02d32d93e815b532e">neorv32_wdt_get_cause</a> (void)</td></tr> +<tr class="separator:a80fa8d178d18c9b02d32d93e815b532e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Watchdog Timer (WDT)</h2></td></tr> +<tr class="memitem:a78615b08cd799063011606d084fef46c" id="r_a78615b08cd799063011606d084fef46c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a78615b08cd799063011606d084fef46c">NEORV32_WDT</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__wdt__t.html">neorv32_wdt_t</a>*) (<a class="el" href="neorv32_8h.html#a3012986cdd5748ee96bcc74cd7108dea">NEORV32_WDT_BASE</a>))</td></tr> +<tr class="separator:a78615b08cd799063011606d084fef46c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0a4cb24fd818277c5bb9b10ff519f23e" id="r_a0a4cb24fd818277c5bb9b10ff519f23e"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23e">NEORV32_WDT_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23ea0e078b41b69bd6089acceb592e14553f">WDT_CTRL_EN</a> = 0 +, <a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23eadc44267502fceb8e7311dfa502fe54d3">WDT_CTRL_LOCK</a> = 1 +, <a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23ea4b0d994fe5ff8d8004c7f25b621fb3a9">WDT_CTRL_DBEN</a> = 2 +, <a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23ea7b7ea5bd390ecbb5ee0d9542ef124148">WDT_CTRL_SEN</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23ea28dd25b66c4a50d0ea47a16c460031ac">WDT_CTRL_STRICT</a> = 4 +, <a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23ea0e7d3e97517f97042ce5606dd5247779">WDT_CTRL_RCAUSE_LO</a> = 5 +, <a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23ea6012d63ea4734fc8a063c9edc6785abd">WDT_CTRL_RCAUSE_HI</a> = 6 +, <a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23ea45df3c9100beb420add34bf71a0e8609">WDT_CTRL_TIMEOUT_LSB</a> = 8 +, <br /> +&#160;&#160;<a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23ea25dea2104b29a3c20dcc3782c2d43dc7">WDT_CTRL_TIMEOUT_MSB</a> = 31 +<br /> + }</td></tr> +<tr class="separator:a0a4cb24fd818277c5bb9b10ff519f23e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Watchdog Timer (WDT) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the WDT unit was synthesized (IO_WDT_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a78615b08cd799063011606d084fef46c" name="a78615b08cd799063011606d084fef46c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a78615b08cd799063011606d084fef46c">&#9670;&#160;</a></span>NEORV32_WDT</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_WDT&#160;&#160;&#160;((<a class="el" href="structneorv32__wdt__t.html">neorv32_wdt_t</a>*) (<a class="el" href="neorv32_8h.html#a3012986cdd5748ee96bcc74cd7108dea">NEORV32_WDT_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>WDT module hardware access (<a class="el" href="structneorv32__wdt__t.html">neorv32_wdt_t</a>) </p> + +</div> +</div> +<a id="af2a2bd9c74bdba1b46bd92025bd00ab6" name="af2a2bd9c74bdba1b46bd92025bd00ab6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af2a2bd9c74bdba1b46bd92025bd00ab6">&#9670;&#160;</a></span>WDT_PASSWORD</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define WDT_PASSWORD&#160;&#160;&#160;(0x709D1AB3)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset Password </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a0a4cb24fd818277c5bb9b10ff519f23e" name="a0a4cb24fd818277c5bb9b10ff519f23e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0a4cb24fd818277c5bb9b10ff519f23e">&#9670;&#160;</a></span>NEORV32_WDT_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23e">NEORV32_WDT_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>WDT control register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23ea0e078b41b69bd6089acceb592e14553f" name="a0a4cb24fd818277c5bb9b10ff519f23ea0e078b41b69bd6089acceb592e14553f"></a>WDT_CTRL_EN&#160;</td><td class="fielddoc"><p>WDT control register(0) (r/w): Watchdog enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23eadc44267502fceb8e7311dfa502fe54d3" name="a0a4cb24fd818277c5bb9b10ff519f23eadc44267502fceb8e7311dfa502fe54d3"></a>WDT_CTRL_LOCK&#160;</td><td class="fielddoc"><p>WDT control register(1) (r/w): Lock write access to control register, clears on reset only </p> +</td></tr> +<tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23ea4b0d994fe5ff8d8004c7f25b621fb3a9" name="a0a4cb24fd818277c5bb9b10ff519f23ea4b0d994fe5ff8d8004c7f25b621fb3a9"></a>WDT_CTRL_DBEN&#160;</td><td class="fielddoc"><p>WDT control register(2) (r/w): Allow WDT to continue operation even when CPU is in debug mode </p> +</td></tr> +<tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23ea7b7ea5bd390ecbb5ee0d9542ef124148" name="a0a4cb24fd818277c5bb9b10ff519f23ea7b7ea5bd390ecbb5ee0d9542ef124148"></a>WDT_CTRL_SEN&#160;</td><td class="fielddoc"><p>WDT control register(3) (r/w): Allow WDT to continue operation even when CPU is in sleep mode </p> +</td></tr> +<tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23ea28dd25b66c4a50d0ea47a16c460031ac" name="a0a4cb24fd818277c5bb9b10ff519f23ea28dd25b66c4a50d0ea47a16c460031ac"></a>WDT_CTRL_STRICT&#160;</td><td class="fielddoc"><p>WDT control register(4) (r/w): Force hardware reset if reset password is incorrect or if write attempt to locked CTRL register </p> +</td></tr> +<tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23ea0e7d3e97517f97042ce5606dd5247779" name="a0a4cb24fd818277c5bb9b10ff519f23ea0e7d3e97517f97042ce5606dd5247779"></a>WDT_CTRL_RCAUSE_LO&#160;</td><td class="fielddoc"><p>WDT control register(5) (r/-): Cause of last system reset - low </p> +</td></tr> +<tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23ea6012d63ea4734fc8a063c9edc6785abd" name="a0a4cb24fd818277c5bb9b10ff519f23ea6012d63ea4734fc8a063c9edc6785abd"></a>WDT_CTRL_RCAUSE_HI&#160;</td><td class="fielddoc"><p>WDT control register(5) (r/-): Cause of last system reset - high </p> +</td></tr> +<tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23ea45df3c9100beb420add34bf71a0e8609" name="a0a4cb24fd818277c5bb9b10ff519f23ea45df3c9100beb420add34bf71a0e8609"></a>WDT_CTRL_TIMEOUT_LSB&#160;</td><td class="fielddoc"><p>WDT control register(8) (r/w): Timeout value, LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a0a4cb24fd818277c5bb9b10ff519f23ea25dea2104b29a3c20dcc3782c2d43dc7" name="a0a4cb24fd818277c5bb9b10ff519f23ea25dea2104b29a3c20dcc3782c2d43dc7"></a>WDT_CTRL_TIMEOUT_MSB&#160;</td><td class="fielddoc"><p>WDT control register(31) (r/w): Timeout value, MSB </p> +</td></tr> +</table> + +</div> +</div> +<a id="a70098b4ee893774864536fb4100ff049" name="a70098b4ee893774864536fb4100ff049"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a70098b4ee893774864536fb4100ff049">&#9670;&#160;</a></span>NEORV32_WDT_RCAUSE_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a70098b4ee893774864536fb4100ff049">NEORV32_WDT_RCAUSE_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reset Cause </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a70098b4ee893774864536fb4100ff049ac5fc25cdc29c248b1a570b6095ddded0" name="a70098b4ee893774864536fb4100ff049ac5fc25cdc29c248b1a570b6095ddded0"></a>WDT_RCAUSE_EXT&#160;</td><td class="fielddoc"><p>Reset caused by external signal/pin </p> +</td></tr> +<tr><td class="fieldname"><a id="a70098b4ee893774864536fb4100ff049a764a7797f17d82f619a6d30c0878bf1e" name="a70098b4ee893774864536fb4100ff049a764a7797f17d82f619a6d30c0878bf1e"></a>WDT_RCAUSE_OCD&#160;</td><td class="fielddoc"><p>Reset caused by on-chip debugger </p> +</td></tr> +<tr><td class="fieldname"><a id="a70098b4ee893774864536fb4100ff049a7273d24bb65d3f40c1d289ce5cbc1a40" name="a70098b4ee893774864536fb4100ff049a7273d24bb65d3f40c1d289ce5cbc1a40"></a>WDT_RCAUSE_TMO&#160;</td><td class="fielddoc"><p>Reset caused by watchdog timer timeout </p> +</td></tr> +<tr><td class="fieldname"><a id="a70098b4ee893774864536fb4100ff049a10999a782ffc2c26f601615f76121376" name="a70098b4ee893774864536fb4100ff049a10999a782ffc2c26f601615f76121376"></a>WDT_RCAUSE_ACC&#160;</td><td class="fielddoc"><p>Reset caused by watchdog timer invalid access </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a459a918c5a86c0167e8c748352d39827" name="a459a918c5a86c0167e8c748352d39827"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a459a918c5a86c0167e8c748352d39827">&#9670;&#160;</a></span>neorv32_wdt_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_wdt_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if WDT unit was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if WDT was not synthesized, 1 if WDT is available. </dd></dl> + +</div> +</div> +<a id="aba52520582392a671e2b717715a330b2" name="aba52520582392a671e2b717715a330b2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aba52520582392a671e2b717715a330b2">&#9670;&#160;</a></span>neorv32_wdt_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_wdt_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable watchdog timer.</p> +<dl class="section return"><dt>Returns</dt><dd>Returns 0 if WDT is really deactivated, -1 otherwise. </dd></dl> + +</div> +</div> +<a id="ae4e86c42ed45eefdec43d9ece08b98a4" name="ae4e86c42ed45eefdec43d9ece08b98a4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae4e86c42ed45eefdec43d9ece08b98a4">&#9670;&#160;</a></span>neorv32_wdt_feed()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_wdt_feed </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>password</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Feed watchdog (reset timeout counter).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">password</td><td>Password for WDT reset. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a80fa8d178d18c9b02d32d93e815b532e" name="a80fa8d178d18c9b02d32d93e815b532e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a80fa8d178d18c9b02d32d93e815b532e">&#9670;&#160;</a></span>neorv32_wdt_get_cause()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_wdt_get_cause </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get cause of last system reset.</p> +<dl class="section return"><dt>Returns</dt><dd>Cause of last reset (<a class="el" href="#a70098b4ee893774864536fb4100ff049">NEORV32_WDT_RCAUSE_enum</a>). </dd></dl> + +</div> +</div> +<a id="a2aa72608191d34ef41c5f545988ff400" name="a2aa72608191d34ef41c5f545988ff400"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2aa72608191d34ef41c5f545988ff400">&#9670;&#160;</a></span>neorv32_wdt_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_wdt_setup </td> + <td>(</td> + <td class="paramtype">uint32_t</td> <td class="paramname"><span class="paramname"><em>timeout</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>lock</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>debug_en</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>sleep_en</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>strict</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure and enable watchdog timer. The WDT control register bits are listed in <a class="el" href="#a0a4cb24fd818277c5bb9b10ff519f23e">NEORV32_WDT_CTRL_enum</a>.</p> +<dl class="section warning"><dt>Warning</dt><dd>Once the lock bit is set it can only be removed by a hardware reset!</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">timeout</td><td>24-bit timeout value. A WDT IRQ is triggered when the internal counter reaches 'timeout/2'. A system hardware reset is triggered when the internal counter reaches 'timeout'. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">lock</td><td>Control register will be locked when 1 (until next reset). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">debug_en</td><td>Allow watchdog to continue operation even when CPU is in debug mode. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">sleep_en</td><td>Allow watchdog to continue operation even when CPU is in sleep mode. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">strict</td><td>Force hardware reset if reset password is incorrect or if trying to alter a locked configuration. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__wdt_8h_source.html b/sw/neorv32__wdt_8h_source.html new file mode 100644 index 000000000..a3f4268df --- /dev/null +++ b/sw/neorv32__wdt_8h_source.html @@ -0,0 +1,185 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/lib/include/neorv32_wdt.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_wdt_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_wdt_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__wdt__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__wdt__t.html#a6ae41e28d08b0f06118c499f52b56f41"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__wdt__t.html#a6ae41e28d08b0f06118c499f52b56f41">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__wdt__t.html#a0a273e8ca2bd92547bf7727ec65a9449"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__wdt__t.html#a0a273e8ca2bd92547bf7727ec65a9449">RESET</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span>} <a class="code hl_struct" href="structneorv32__wdt__t.html">neorv32_wdt_t</a>;</div> +</div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a78615b08cd799063011606d084fef46c"> 35</a></span><span class="preprocessor">#define NEORV32_WDT ((neorv32_wdt_t*) (NEORV32_WDT_BASE))</span></div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> </div> +<div class="foldopen" id="foldopen00038" data-start="{" data-end="};"> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23e"> 38</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23e">NEORV32_WDT_CTRL_enum</a> {</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea0e078b41b69bd6089acceb592e14553f"> 39</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea0e078b41b69bd6089acceb592e14553f">WDT_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23eadc44267502fceb8e7311dfa502fe54d3"> 40</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23eadc44267502fceb8e7311dfa502fe54d3">WDT_CTRL_LOCK</a> = 1, </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea4b0d994fe5ff8d8004c7f25b621fb3a9"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea4b0d994fe5ff8d8004c7f25b621fb3a9">WDT_CTRL_DBEN</a> = 2, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea7b7ea5bd390ecbb5ee0d9542ef124148"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea7b7ea5bd390ecbb5ee0d9542ef124148">WDT_CTRL_SEN</a> = 3, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea28dd25b66c4a50d0ea47a16c460031ac"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea28dd25b66c4a50d0ea47a16c460031ac">WDT_CTRL_STRICT</a> = 4, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea0e7d3e97517f97042ce5606dd5247779"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea0e7d3e97517f97042ce5606dd5247779">WDT_CTRL_RCAUSE_LO</a> = 5, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea6012d63ea4734fc8a063c9edc6785abd"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea6012d63ea4734fc8a063c9edc6785abd">WDT_CTRL_RCAUSE_HI</a> = 6, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea45df3c9100beb420add34bf71a0e8609"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea45df3c9100beb420add34bf71a0e8609">WDT_CTRL_TIMEOUT_LSB</a> = 8, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea25dea2104b29a3c20dcc3782c2d43dc7">WDT_CTRL_TIMEOUT_MSB</a> = 31 </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea25dea2104b29a3c20dcc3782c2d43dc7"> 49</a></span>};</div> +</div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#af2a2bd9c74bdba1b46bd92025bd00ab6"> 56</a></span><span class="preprocessor">#define WDT_PASSWORD (0x709D1AB3)</span></div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span> </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span> </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00062" data-start="{" data-end="};"> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049"> 62</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049">NEORV32_WDT_RCAUSE_enum</a> {</div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049ac5fc25cdc29c248b1a570b6095ddded0"> 63</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049ac5fc25cdc29c248b1a570b6095ddded0">WDT_RCAUSE_EXT</a> = 0b00, </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a764a7797f17d82f619a6d30c0878bf1e"> 64</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a764a7797f17d82f619a6d30c0878bf1e">WDT_RCAUSE_OCD</a> = 0b01, </div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a7273d24bb65d3f40c1d289ce5cbc1a40"> 65</a></span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a7273d24bb65d3f40c1d289ce5cbc1a40">WDT_RCAUSE_TMO</a> = 0b10, </div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span> <a class="code hl_enumvalue" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a10999a782ffc2c26f601615f76121376">WDT_RCAUSE_ACC</a> = 0b11 </div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"><a class="line" href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a10999a782ffc2c26f601615f76121376"> 67</a></span>};</div> +</div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span> </div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span> </div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__wdt_8h.html#a459a918c5a86c0167e8c748352d39827">neorv32_wdt_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__wdt_8h.html#a2aa72608191d34ef41c5f545988ff400">neorv32_wdt_setup</a>(uint32_t timeout, <span class="keywordtype">int</span> lock, <span class="keywordtype">int</span> debug_en, <span class="keywordtype">int</span> sleep_en, <span class="keywordtype">int</span> strict);</div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__wdt_8h.html#aba52520582392a671e2b717715a330b2">neorv32_wdt_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__wdt_8h.html#ae4e86c42ed45eefdec43d9ece08b98a4">neorv32_wdt_feed</a>(uint32_t password);</div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__wdt_8h.html#a80fa8d178d18c9b02d32d93e815b532e">neorv32_wdt_get_cause</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_wdt_h</span></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23e"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23e">NEORV32_WDT_CTRL_enum</a></div><div class="ttdeci">NEORV32_WDT_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:38</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23ea0e078b41b69bd6089acceb592e14553f"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea0e078b41b69bd6089acceb592e14553f">WDT_CTRL_EN</a></div><div class="ttdeci">@ WDT_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:39</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23ea0e7d3e97517f97042ce5606dd5247779"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea0e7d3e97517f97042ce5606dd5247779">WDT_CTRL_RCAUSE_LO</a></div><div class="ttdeci">@ WDT_CTRL_RCAUSE_LO</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:44</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23ea25dea2104b29a3c20dcc3782c2d43dc7"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea25dea2104b29a3c20dcc3782c2d43dc7">WDT_CTRL_TIMEOUT_MSB</a></div><div class="ttdeci">@ WDT_CTRL_TIMEOUT_MSB</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:48</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23ea28dd25b66c4a50d0ea47a16c460031ac"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea28dd25b66c4a50d0ea47a16c460031ac">WDT_CTRL_STRICT</a></div><div class="ttdeci">@ WDT_CTRL_STRICT</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:43</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23ea45df3c9100beb420add34bf71a0e8609"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea45df3c9100beb420add34bf71a0e8609">WDT_CTRL_TIMEOUT_LSB</a></div><div class="ttdeci">@ WDT_CTRL_TIMEOUT_LSB</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:47</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23ea4b0d994fe5ff8d8004c7f25b621fb3a9"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea4b0d994fe5ff8d8004c7f25b621fb3a9">WDT_CTRL_DBEN</a></div><div class="ttdeci">@ WDT_CTRL_DBEN</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:41</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23ea6012d63ea4734fc8a063c9edc6785abd"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea6012d63ea4734fc8a063c9edc6785abd">WDT_CTRL_RCAUSE_HI</a></div><div class="ttdeci">@ WDT_CTRL_RCAUSE_HI</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:45</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23ea7b7ea5bd390ecbb5ee0d9542ef124148"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23ea7b7ea5bd390ecbb5ee0d9542ef124148">WDT_CTRL_SEN</a></div><div class="ttdeci">@ WDT_CTRL_SEN</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:42</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a0a4cb24fd818277c5bb9b10ff519f23eadc44267502fceb8e7311dfa502fe54d3"><div class="ttname"><a href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23eadc44267502fceb8e7311dfa502fe54d3">WDT_CTRL_LOCK</a></div><div class="ttdeci">@ WDT_CTRL_LOCK</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:40</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a2aa72608191d34ef41c5f545988ff400"><div class="ttname"><a href="neorv32__wdt_8h.html#a2aa72608191d34ef41c5f545988ff400">neorv32_wdt_setup</a></div><div class="ttdeci">void neorv32_wdt_setup(uint32_t timeout, int lock, int debug_en, int sleep_en, int strict)</div><div class="ttdef"><b>Definition</b> neorv32_wdt.c:49</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a459a918c5a86c0167e8c748352d39827"><div class="ttname"><a href="neorv32__wdt_8h.html#a459a918c5a86c0167e8c748352d39827">neorv32_wdt_available</a></div><div class="ttdeci">int neorv32_wdt_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_wdt.c:26</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a70098b4ee893774864536fb4100ff049"><div class="ttname"><a href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049">NEORV32_WDT_RCAUSE_enum</a></div><div class="ttdeci">NEORV32_WDT_RCAUSE_enum</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:62</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a70098b4ee893774864536fb4100ff049a10999a782ffc2c26f601615f76121376"><div class="ttname"><a href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a10999a782ffc2c26f601615f76121376">WDT_RCAUSE_ACC</a></div><div class="ttdeci">@ WDT_RCAUSE_ACC</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:66</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a70098b4ee893774864536fb4100ff049a7273d24bb65d3f40c1d289ce5cbc1a40"><div class="ttname"><a href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a7273d24bb65d3f40c1d289ce5cbc1a40">WDT_RCAUSE_TMO</a></div><div class="ttdeci">@ WDT_RCAUSE_TMO</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:65</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a70098b4ee893774864536fb4100ff049a764a7797f17d82f619a6d30c0878bf1e"><div class="ttname"><a href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049a764a7797f17d82f619a6d30c0878bf1e">WDT_RCAUSE_OCD</a></div><div class="ttdeci">@ WDT_RCAUSE_OCD</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:64</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a70098b4ee893774864536fb4100ff049ac5fc25cdc29c248b1a570b6095ddded0"><div class="ttname"><a href="neorv32__wdt_8h.html#a70098b4ee893774864536fb4100ff049ac5fc25cdc29c248b1a570b6095ddded0">WDT_RCAUSE_EXT</a></div><div class="ttdeci">@ WDT_RCAUSE_EXT</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:63</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_a80fa8d178d18c9b02d32d93e815b532e"><div class="ttname"><a href="neorv32__wdt_8h.html#a80fa8d178d18c9b02d32d93e815b532e">neorv32_wdt_get_cause</a></div><div class="ttdeci">int neorv32_wdt_get_cause(void)</div><div class="ttdef"><b>Definition</b> neorv32_wdt.c:106</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_aba52520582392a671e2b717715a330b2"><div class="ttname"><a href="neorv32__wdt_8h.html#aba52520582392a671e2b717715a330b2">neorv32_wdt_disable</a></div><div class="ttdeci">int neorv32_wdt_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_wdt.c:74</div></div> +<div class="ttc" id="aneorv32__wdt_8h_html_ae4e86c42ed45eefdec43d9ece08b98a4"><div class="ttname"><a href="neorv32__wdt_8h.html#ae4e86c42ed45eefdec43d9ece08b98a4">neorv32_wdt_feed</a></div><div class="ttdeci">void neorv32_wdt_feed(uint32_t password)</div><div class="ttdef"><b>Definition</b> neorv32_wdt.c:95</div></div> +<div class="ttc" id="astructneorv32__wdt__t_html"><div class="ttname"><a href="structneorv32__wdt__t.html">neorv32_wdt_t</a></div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:29</div></div> +<div class="ttc" id="astructneorv32__wdt__t_html_a0a273e8ca2bd92547bf7727ec65a9449"><div class="ttname"><a href="structneorv32__wdt__t.html#a0a273e8ca2bd92547bf7727ec65a9449">neorv32_wdt_t::RESET</a></div><div class="ttdeci">uint32_t RESET</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:31</div></div> +<div class="ttc" id="astructneorv32__wdt__t_html_a6ae41e28d08b0f06118c499f52b56f41"><div class="ttname"><a href="structneorv32__wdt__t.html#a6ae41e28d08b0f06118c499f52b56f41">neorv32_wdt_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_wdt.h:30</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address 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+ <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div 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href="dir_01fcd3835fb4e7d9331b722d86291b65.html">sw</a></li><li class="navelem"><a class="el" href="dir_7d04193005ada6f9450f847f4adb6b5b.html">lib</a></li><li class="navelem"><a class="el" href="dir_0c6ac14e2254a316d41123f98feeb67b.html">source</a></li> </ul> +</div> +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"><div class="title">neorv32_xip.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>Execute in place module (XIP) HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:afe2e5682a26cafdb0585d2233bccc7c6" id="r_afe2e5682a26cafdb0585d2233bccc7c6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afe2e5682a26cafdb0585d2233bccc7c6">neorv32_xip_available</a> (void)</td></tr> +<tr class="separator:afe2e5682a26cafdb0585d2233bccc7c6"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a549d68abdf5a3d7484abe6d5370bb999" id="r_a549d68abdf5a3d7484abe6d5370bb999"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a549d68abdf5a3d7484abe6d5370bb999">neorv32_xip_setup</a> (int prsc, int cdiv, int cpol, int cpha, uint8_t rd_cmd)</td></tr> +<tr class="separator:a549d68abdf5a3d7484abe6d5370bb999"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0ab2c36c973030a811e6d7abe0afc393" id="r_a0ab2c36c973030a811e6d7abe0afc393"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0ab2c36c973030a811e6d7abe0afc393">neorv32_xip_start</a> (int abytes)</td></tr> +<tr class="separator:a0ab2c36c973030a811e6d7abe0afc393"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6aef2ea29451ba2aa55160da777a5115" id="r_a6aef2ea29451ba2aa55160da777a5115"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6aef2ea29451ba2aa55160da777a5115">neorv32_xip_highspeed_enable</a> (void)</td></tr> +<tr class="separator:a6aef2ea29451ba2aa55160da777a5115"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad74f2842ed2251e3ae5c19e06dced0c3" id="r_ad74f2842ed2251e3ae5c19e06dced0c3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad74f2842ed2251e3ae5c19e06dced0c3">neorv32_xip_highspeed_disable</a> (void)</td></tr> +<tr class="separator:ad74f2842ed2251e3ae5c19e06dced0c3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a88f728101e82939bf7f8b9ab5a904706" id="r_a88f728101e82939bf7f8b9ab5a904706"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a88f728101e82939bf7f8b9ab5a904706">neorv32_xip_get_clock_speed</a> (void)</td></tr> +<tr class="separator:a88f728101e82939bf7f8b9ab5a904706"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a92f1446a3bb7fe6dee5dbed33882b223" id="r_a92f1446a3bb7fe6dee5dbed33882b223"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a92f1446a3bb7fe6dee5dbed33882b223">neorv32_xip_spi_trans</a> (int nbytes, uint64_t *rtx_data)</td></tr> +<tr class="separator:a92f1446a3bb7fe6dee5dbed33882b223"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Execute in place module (XIP) HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="afe2e5682a26cafdb0585d2233bccc7c6" name="afe2e5682a26cafdb0585d2233bccc7c6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afe2e5682a26cafdb0585d2233bccc7c6">&#9670;&#160;</a></span>neorv32_xip_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xip_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if XIP module was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if XIP was not synthesized, 1 if XIP is available. </dd></dl> + +</div> +</div> +<a id="a88f728101e82939bf7f8b9ab5a904706" name="a88f728101e82939bf7f8b9ab5a904706"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a88f728101e82939bf7f8b9ab5a904706">&#9670;&#160;</a></span>neorv32_xip_get_clock_speed()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_xip_get_clock_speed </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get configured clock speed in Hz.</p> +<dl class="section return"><dt>Returns</dt><dd>Actual configured XIP clock speed in Hz. </dd></dl> + +</div> +</div> +<a id="ad74f2842ed2251e3ae5c19e06dced0c3" name="ad74f2842ed2251e3ae5c19e06dced0c3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad74f2842ed2251e3ae5c19e06dced0c3">&#9670;&#160;</a></span>neorv32_xip_highspeed_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xip_highspeed_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable high-speed SPI mode. </p> + +</div> +</div> +<a id="a6aef2ea29451ba2aa55160da777a5115" name="a6aef2ea29451ba2aa55160da777a5115"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6aef2ea29451ba2aa55160da777a5115">&#9670;&#160;</a></span>neorv32_xip_highspeed_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xip_highspeed_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable high-speed SPI mode (running at half of the processor clock).</p> +<dl class="section note"><dt>Note</dt><dd>High-speed SPI mode ignores the programmed clock prescaler configuration. </dd></dl> + +</div> +</div> +<a id="a549d68abdf5a3d7484abe6d5370bb999" name="a549d68abdf5a3d7484abe6d5370bb999"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a549d68abdf5a3d7484abe6d5370bb999">&#9670;&#160;</a></span>neorv32_xip_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xip_setup </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cdiv</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cpol</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cpha</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>rd_cmd</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure XIP module: configure SPI/flash properties.</p> +<dl class="section warning"><dt>Warning</dt><dd>This will reset the XIP module overriding the CTRL register. </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function will also send 64 dummy clocks via the SPI port (with chip-select disabled).</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>SPI clock prescaler select (0..7). @prama[in] cdiv Clock divider (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cpol</td><td>SPI clock polarity (0/1). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cpha</td><td>SPI clock phase(0/1). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rd_cmd</td><td>SPI flash read byte command. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a92f1446a3bb7fe6dee5dbed33882b223" name="a92f1446a3bb7fe6dee5dbed33882b223"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a92f1446a3bb7fe6dee5dbed33882b223">&#9670;&#160;</a></span>neorv32_xip_spi_trans()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xip_spi_trans </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>nbytes</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint64_t *</td> <td class="paramname"><span class="paramname"><em>rtx_data</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Direct SPI access to the XIP flash.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function can only be used BEFORE the XIP-mode is activated! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">nbytes</td><td>Number of bytes to transfer (1..8). </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">rtx_data</td><td>Pointer to 64-bit TX/RX data (MSB-aligned for sending, LSB-aligned for receiving (only 32-bit)). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if valid transfer, 1 if transfer configuration error. </dd></dl> + +</div> +</div> +<a id="a0ab2c36c973030a811e6d7abe0afc393" name="a0ab2c36c973030a811e6d7abe0afc393"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0ab2c36c973030a811e6d7abe0afc393">&#9670;&#160;</a></span>neorv32_xip_start()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xip_start </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>abytes</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable XIP mode (to allow CPU to <em>transparently</em> fetch data &amp; instructions).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">abytes</td><td>Number of address bytes used to access the SPI flash (1,2,3,4). </td></tr> + </table> + </dd> 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file.</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structneorv32__xip__t.html">neorv32_xip_t</a></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:afe2e5682a26cafdb0585d2233bccc7c6" id="r_afe2e5682a26cafdb0585d2233bccc7c6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afe2e5682a26cafdb0585d2233bccc7c6">neorv32_xip_available</a> (void)</td></tr> +<tr class="separator:afe2e5682a26cafdb0585d2233bccc7c6"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a549d68abdf5a3d7484abe6d5370bb999" id="r_a549d68abdf5a3d7484abe6d5370bb999"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a549d68abdf5a3d7484abe6d5370bb999">neorv32_xip_setup</a> (int prsc, int cdiv, int cpol, int cpha, uint8_t rd_cmd)</td></tr> +<tr class="separator:a549d68abdf5a3d7484abe6d5370bb999"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0ab2c36c973030a811e6d7abe0afc393" id="r_a0ab2c36c973030a811e6d7abe0afc393"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0ab2c36c973030a811e6d7abe0afc393">neorv32_xip_start</a> (int abytes)</td></tr> +<tr class="separator:a0ab2c36c973030a811e6d7abe0afc393"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a6aef2ea29451ba2aa55160da777a5115" id="r_a6aef2ea29451ba2aa55160da777a5115"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6aef2ea29451ba2aa55160da777a5115">neorv32_xip_highspeed_enable</a> (void)</td></tr> +<tr class="separator:a6aef2ea29451ba2aa55160da777a5115"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad74f2842ed2251e3ae5c19e06dced0c3" id="r_ad74f2842ed2251e3ae5c19e06dced0c3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad74f2842ed2251e3ae5c19e06dced0c3">neorv32_xip_highspeed_disable</a> (void)</td></tr> +<tr class="separator:ad74f2842ed2251e3ae5c19e06dced0c3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a88f728101e82939bf7f8b9ab5a904706" id="r_a88f728101e82939bf7f8b9ab5a904706"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a88f728101e82939bf7f8b9ab5a904706">neorv32_xip_get_clock_speed</a> (void)</td></tr> +<tr class="separator:a88f728101e82939bf7f8b9ab5a904706"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a92f1446a3bb7fe6dee5dbed33882b223" id="r_a92f1446a3bb7fe6dee5dbed33882b223"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a92f1446a3bb7fe6dee5dbed33882b223">neorv32_xip_spi_trans</a> (int nbytes, uint64_t *rtx_data)</td></tr> +<tr class="separator:a92f1446a3bb7fe6dee5dbed33882b223"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader">IO Device: Execute In Place Module (XIP)</h2></td></tr> +<tr class="memitem:a3d6f138a347c16883b51069428eb7c1e" id="r_a3d6f138a347c16883b51069428eb7c1e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3d6f138a347c16883b51069428eb7c1e">NEORV32_XIP</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__xip__t.html">neorv32_xip_t</a>*) (<a class="el" href="neorv32_8h.html#ae0978315beac8399f96f520bda81c7fe">NEORV32_XIP_BASE</a>))</td></tr> +<tr class="separator:a3d6f138a347c16883b51069428eb7c1e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a72ed1ff87de1222cc3a13177c7483ceb" id="r_a72ed1ff87de1222cc3a13177c7483ceb"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceb">NEORV32_XIP_CTRL_enum</a> { <br /> +&#160;&#160;<a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba27658ce3cc81c9e258b73fb02d7f1045">XIP_CTRL_EN</a> = 0 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba67a0c0483eaf92e9cd03e9076be5b50d">XIP_CTRL_PRSC0</a> = 1 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483cebae47f2e1e8c023fd52e25a3dad5e332af">XIP_CTRL_PRSC1</a> = 2 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba896815c075a91a8291585eb61b6e0086">XIP_CTRL_PRSC2</a> = 3 +, <br /> +&#160;&#160;<a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba95ae19cf5d5140df397ead62f151247f">XIP_CTRL_CPOL</a> = 4 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483cebad31736f4a159745be94b487079c4c14d">XIP_CTRL_CPHA</a> = 5 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba23be66e49d28dd12c5321e576d2f0c7a">XIP_CTRL_SPI_NBYTES_LSB</a> = 6 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba5d13c4fe190fcd68dfcbbbe33d2e844c">XIP_CTRL_SPI_NBYTES_MSB</a> = 9 +, <br /> +&#160;&#160;<a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba3cbd45a66e05a4fcfc5ec810b8cee937">XIP_CTRL_XIP_EN</a> = 10 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba603f9d8d22ae2a6abc61b666bc88a4df">XIP_CTRL_XIP_ABYTES_LSB</a> = 11 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba5885ed5fcd2eed969bd921afe8dff4fc">XIP_CTRL_XIP_ABYTES_MSB</a> = 12 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba8287016f167727f147806aa11129e05b">XIP_CTRL_RD_CMD_LSB</a> = 13 +, <br /> +&#160;&#160;<a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba2c78cd2d32cfba4d89f7aab92f7939e7">XIP_CTRL_RD_CMD_MSB</a> = 20 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba5aadb2c374d34b878b56a660baec2080">XIP_CTRL_SPI_CSEN</a> = 21 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483cebaaeb104a59215667aabb5a751632ae781">XIP_CTRL_HIGHSPEED</a> = 22 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483cebaf9b56aa629973ce4a9c8ff61a2c90ba3">XIP_CTRL_CDIV0</a> = 23 +, <br /> +&#160;&#160;<a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba68775854b8f2cfa2f32d2eb82a714073">XIP_CTRL_CDIV1</a> = 24 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba43d7305e0e0398cb44c99e70dcd96445">XIP_CTRL_CDIV2</a> = 25 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba61ffffe9acda5c622b48b6360e357eef">XIP_CTRL_CDIV3</a> = 26 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba7ad9f81356d6923d524d1c9e39acdd2c">XIP_CTRL_BURST_EN</a> = 29 +, <br /> +&#160;&#160;<a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba76d2379d0e7ab09e7e686bc886888fa5">XIP_CTRL_PHY_BUSY</a> = 30 +, <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceba2c4a47f88d299782b8618b68fb87d59a">XIP_CTRL_XIP_BUSY</a> = 31 +<br /> + }</td></tr> +<tr class="separator:a72ed1ff87de1222cc3a13177c7483ceb"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Execute in place module (XIP) HW driver header file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a3d6f138a347c16883b51069428eb7c1e" name="a3d6f138a347c16883b51069428eb7c1e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3d6f138a347c16883b51069428eb7c1e">&#9670;&#160;</a></span>NEORV32_XIP</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_XIP&#160;&#160;&#160;((<a class="el" href="structneorv32__xip__t.html">neorv32_xip_t</a>*) (<a class="el" href="neorv32_8h.html#ae0978315beac8399f96f520bda81c7fe">NEORV32_XIP_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIP module hardware access (<a class="el" href="structneorv32__xip__t.html">neorv32_xip_t</a>) </p> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a id="a72ed1ff87de1222cc3a13177c7483ceb" name="a72ed1ff87de1222cc3a13177c7483ceb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a72ed1ff87de1222cc3a13177c7483ceb">&#9670;&#160;</a></span>NEORV32_XIP_CTRL_enum</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="#a72ed1ff87de1222cc3a13177c7483ceb">NEORV32_XIP_CTRL_enum</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIP control/data register bits </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba27658ce3cc81c9e258b73fb02d7f1045" name="a72ed1ff87de1222cc3a13177c7483ceba27658ce3cc81c9e258b73fb02d7f1045"></a>XIP_CTRL_EN&#160;</td><td class="fielddoc"><p>XIP control register( 0) (r/w): XIP module enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba67a0c0483eaf92e9cd03e9076be5b50d" name="a72ed1ff87de1222cc3a13177c7483ceba67a0c0483eaf92e9cd03e9076be5b50d"></a>XIP_CTRL_PRSC0&#160;</td><td class="fielddoc"><p>XIP control register( 1) (r/w): Clock prescaler select bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483cebae47f2e1e8c023fd52e25a3dad5e332af" name="a72ed1ff87de1222cc3a13177c7483cebae47f2e1e8c023fd52e25a3dad5e332af"></a>XIP_CTRL_PRSC1&#160;</td><td class="fielddoc"><p>XIP control register( 2) (r/w): Clock prescaler select bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba896815c075a91a8291585eb61b6e0086" name="a72ed1ff87de1222cc3a13177c7483ceba896815c075a91a8291585eb61b6e0086"></a>XIP_CTRL_PRSC2&#160;</td><td class="fielddoc"><p>XIP control register( 3) (r/w): Clock prescaler select bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba95ae19cf5d5140df397ead62f151247f" name="a72ed1ff87de1222cc3a13177c7483ceba95ae19cf5d5140df397ead62f151247f"></a>XIP_CTRL_CPOL&#160;</td><td class="fielddoc"><p>XIP control register( 4) (r/w): SPI (idle) clock polarity </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483cebad31736f4a159745be94b487079c4c14d" name="a72ed1ff87de1222cc3a13177c7483cebad31736f4a159745be94b487079c4c14d"></a>XIP_CTRL_CPHA&#160;</td><td class="fielddoc"><p>XIP control register( 5) (r/w): SPI clock phase </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba23be66e49d28dd12c5321e576d2f0c7a" name="a72ed1ff87de1222cc3a13177c7483ceba23be66e49d28dd12c5321e576d2f0c7a"></a>XIP_CTRL_SPI_NBYTES_LSB&#160;</td><td class="fielddoc"><p>XIP control register( 6) (r/w): Number of bytes in SPI transmission, LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba5d13c4fe190fcd68dfcbbbe33d2e844c" name="a72ed1ff87de1222cc3a13177c7483ceba5d13c4fe190fcd68dfcbbbe33d2e844c"></a>XIP_CTRL_SPI_NBYTES_MSB&#160;</td><td class="fielddoc"><p>XIP control register( 9) (r/w): Number of bytes in SPI transmission, MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba3cbd45a66e05a4fcfc5ec810b8cee937" name="a72ed1ff87de1222cc3a13177c7483ceba3cbd45a66e05a4fcfc5ec810b8cee937"></a>XIP_CTRL_XIP_EN&#160;</td><td class="fielddoc"><p>XIP control register(10) (r/w): XIP access enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba603f9d8d22ae2a6abc61b666bc88a4df" name="a72ed1ff87de1222cc3a13177c7483ceba603f9d8d22ae2a6abc61b666bc88a4df"></a>XIP_CTRL_XIP_ABYTES_LSB&#160;</td><td class="fielddoc"><p>XIP control register(11) (r/w): Number XIP address bytes (minus 1), LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba5885ed5fcd2eed969bd921afe8dff4fc" name="a72ed1ff87de1222cc3a13177c7483ceba5885ed5fcd2eed969bd921afe8dff4fc"></a>XIP_CTRL_XIP_ABYTES_MSB&#160;</td><td class="fielddoc"><p>XIP control register(12) (r/w): Number XIP address bytes (minus 1), MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba8287016f167727f147806aa11129e05b" name="a72ed1ff87de1222cc3a13177c7483ceba8287016f167727f147806aa11129e05b"></a>XIP_CTRL_RD_CMD_LSB&#160;</td><td class="fielddoc"><p>XIP control register(13) (r/w): SPI flash read command, LSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba2c78cd2d32cfba4d89f7aab92f7939e7" name="a72ed1ff87de1222cc3a13177c7483ceba2c78cd2d32cfba4d89f7aab92f7939e7"></a>XIP_CTRL_RD_CMD_MSB&#160;</td><td class="fielddoc"><p>XIP control register(20) (r/w): SPI flash read command, MSB </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba5aadb2c374d34b878b56a660baec2080" name="a72ed1ff87de1222cc3a13177c7483ceba5aadb2c374d34b878b56a660baec2080"></a>XIP_CTRL_SPI_CSEN&#160;</td><td class="fielddoc"><p>XIP control register(21) (r/w): SPI chip-select enable </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483cebaaeb104a59215667aabb5a751632ae781" name="a72ed1ff87de1222cc3a13177c7483cebaaeb104a59215667aabb5a751632ae781"></a>XIP_CTRL_HIGHSPEED&#160;</td><td class="fielddoc"><p>XIP control register(22) (r/w): SPI high-speed mode enable (ignoring XIP_CTRL_PRSC) </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483cebaf9b56aa629973ce4a9c8ff61a2c90ba3" name="a72ed1ff87de1222cc3a13177c7483cebaf9b56aa629973ce4a9c8ff61a2c90ba3"></a>XIP_CTRL_CDIV0&#160;</td><td class="fielddoc"><p>XIP control register(23) (r/w): Clock divider bit 0 </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba68775854b8f2cfa2f32d2eb82a714073" name="a72ed1ff87de1222cc3a13177c7483ceba68775854b8f2cfa2f32d2eb82a714073"></a>XIP_CTRL_CDIV1&#160;</td><td class="fielddoc"><p>XIP control register(24) (r/w): Clock divider bit 1 </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba43d7305e0e0398cb44c99e70dcd96445" name="a72ed1ff87de1222cc3a13177c7483ceba43d7305e0e0398cb44c99e70dcd96445"></a>XIP_CTRL_CDIV2&#160;</td><td class="fielddoc"><p>XIP control register(25) (r/w): Clock divider bit 2 </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba61ffffe9acda5c622b48b6360e357eef" name="a72ed1ff87de1222cc3a13177c7483ceba61ffffe9acda5c622b48b6360e357eef"></a>XIP_CTRL_CDIV3&#160;</td><td class="fielddoc"><p>XIP control register(26) (r/w): Clock divider bit 3 </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba7ad9f81356d6923d524d1c9e39acdd2c" name="a72ed1ff87de1222cc3a13177c7483ceba7ad9f81356d6923d524d1c9e39acdd2c"></a>XIP_CTRL_BURST_EN&#160;</td><td class="fielddoc"><p>XIP control register(29) (r/-): Burst mode enabled (set if XIP cache is implemented) </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba76d2379d0e7ab09e7e686bc886888fa5" name="a72ed1ff87de1222cc3a13177c7483ceba76d2379d0e7ab09e7e686bc886888fa5"></a>XIP_CTRL_PHY_BUSY&#160;</td><td class="fielddoc"><p>XIP control register(30) (r/-): SPI PHY is busy </p> +</td></tr> +<tr><td class="fieldname"><a id="a72ed1ff87de1222cc3a13177c7483ceba2c4a47f88d299782b8618b68fb87d59a" name="a72ed1ff87de1222cc3a13177c7483ceba2c4a47f88d299782b8618b68fb87d59a"></a>XIP_CTRL_XIP_BUSY&#160;</td><td class="fielddoc"><p>XIP control register(31) (r/-): XIP access in progress </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="afe2e5682a26cafdb0585d2233bccc7c6" name="afe2e5682a26cafdb0585d2233bccc7c6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#afe2e5682a26cafdb0585d2233bccc7c6">&#9670;&#160;</a></span>neorv32_xip_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xip_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if XIP module was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if XIP was not synthesized, 1 if XIP is available. </dd></dl> + +</div> +</div> +<a id="a88f728101e82939bf7f8b9ab5a904706" name="a88f728101e82939bf7f8b9ab5a904706"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a88f728101e82939bf7f8b9ab5a904706">&#9670;&#160;</a></span>neorv32_xip_get_clock_speed()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_xip_get_clock_speed </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get configured clock speed in Hz.</p> +<dl class="section return"><dt>Returns</dt><dd>Actual configured XIP clock speed in Hz. </dd></dl> + +</div> +</div> +<a id="ad74f2842ed2251e3ae5c19e06dced0c3" name="ad74f2842ed2251e3ae5c19e06dced0c3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad74f2842ed2251e3ae5c19e06dced0c3">&#9670;&#160;</a></span>neorv32_xip_highspeed_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xip_highspeed_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable high-speed SPI mode. </p> + +</div> +</div> +<a id="a6aef2ea29451ba2aa55160da777a5115" name="a6aef2ea29451ba2aa55160da777a5115"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6aef2ea29451ba2aa55160da777a5115">&#9670;&#160;</a></span>neorv32_xip_highspeed_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xip_highspeed_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable high-speed SPI mode (running at half of the processor clock).</p> +<dl class="section note"><dt>Note</dt><dd>High-speed SPI mode ignores the programmed clock prescaler configuration. </dd></dl> + +</div> +</div> +<a id="a549d68abdf5a3d7484abe6d5370bb999" name="a549d68abdf5a3d7484abe6d5370bb999"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a549d68abdf5a3d7484abe6d5370bb999">&#9670;&#160;</a></span>neorv32_xip_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xip_setup </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>prsc</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cdiv</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cpol</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>cpha</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t</td> <td class="paramname"><span class="paramname"><em>rd_cmd</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure XIP module: configure SPI/flash properties.</p> +<dl class="section warning"><dt>Warning</dt><dd>This will reset the XIP module overriding the CTRL register. </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function will also send 64 dummy clocks via the SPI port (with chip-select disabled).</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">prsc</td><td>SPI clock prescaler select (0..7). @prama[in] cdiv Clock divider (0..15). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cpol</td><td>SPI clock polarity (0/1). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">cpha</td><td>SPI clock phase(0/1). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">rd_cmd</td><td>SPI flash read byte command. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a92f1446a3bb7fe6dee5dbed33882b223" name="a92f1446a3bb7fe6dee5dbed33882b223"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a92f1446a3bb7fe6dee5dbed33882b223">&#9670;&#160;</a></span>neorv32_xip_spi_trans()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xip_spi_trans </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>nbytes</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint64_t *</td> <td class="paramname"><span class="paramname"><em>rtx_data</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Direct SPI access to the XIP flash.</p> +<dl class="section warning"><dt>Warning</dt><dd>This function can only be used BEFORE the XIP-mode is activated! </dd></dl> +<dl class="section note"><dt>Note</dt><dd>This function is blocking.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">nbytes</td><td>Number of bytes to transfer (1..8). </td></tr> + <tr><td class="paramdir">[in,out]</td><td class="paramname">rtx_data</td><td>Pointer to 64-bit TX/RX data (MSB-aligned for sending, LSB-aligned for receiving (only 32-bit)). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if valid transfer, 1 if transfer configuration error. </dd></dl> + +</div> +</div> +<a id="a0ab2c36c973030a811e6d7abe0afc393" name="a0ab2c36c973030a811e6d7abe0afc393"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0ab2c36c973030a811e6d7abe0afc393">&#9670;&#160;</a></span>neorv32_xip_start()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xip_start </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>abytes</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable XIP mode (to allow CPU to <em>transparently</em> fetch data &amp; instructions).</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">abytes</td><td>Number of address bytes used to access the SPI flash (1,2,3,4). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if XIP configuration is OK, -1 if configuration error. </dd></dl> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/neorv32__xip_8h_source.html b/sw/neorv32__xip_8h_source.html new file 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class="headertitle"><div class="title">neorv32_xip.h</div></div> +</div><!--header--> +<div class="contents"> +<a href="neorv32__xip_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="preprocessor">#ifndef neorv32_xip_h</span></div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#define neorv32_xip_h</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00029" data-start="{" data-end="};"> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__xip__t.html"> 29</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__xip__t.html#a7ead9d6a4f784d766a6b2755c6d35235"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__xip__t.html#a7ead9d6a4f784d766a6b2755c6d35235">CTRL</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__xip__t.html#aacb77d586c3caec518e8e0024cfe745c"> 31</a></span> <span class="keyword">const</span> uint32_t <a class="code hl_variable" href="structneorv32__xip__t.html#aacb77d586c3caec518e8e0024cfe745c">reserved</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"><a class="line" href="structneorv32__xip__t.html#ad64048bb3544e712b1c668c2ef343ccb"> 32</a></span> uint32_t <a class="code hl_variable" href="structneorv32__xip__t.html#ad64048bb3544e712b1c668c2ef343ccb">DATA_LO</a>; </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"><a class="line" href="structneorv32__xip__t.html#a516ab9c075ef6d1fb741e243db7703b2"> 33</a></span> uint32_t <a class="code hl_variable" href="structneorv32__xip__t.html#a516ab9c075ef6d1fb741e243db7703b2">DATA_HI</a>; </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span>} <a class="code hl_struct" href="structneorv32__xip__t.html">neorv32_xip_t</a>;</div> +</div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a3d6f138a347c16883b51069428eb7c1e"> 37</a></span><span class="preprocessor">#define NEORV32_XIP ((neorv32_xip_t*) (NEORV32_XIP_BASE))</span></div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> </div> +<div class="foldopen" id="foldopen00040" data-start="{" data-end="};"> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceb"> 40</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceb">NEORV32_XIP_CTRL_enum</a> {</div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba27658ce3cc81c9e258b73fb02d7f1045"> 41</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba27658ce3cc81c9e258b73fb02d7f1045">XIP_CTRL_EN</a> = 0, </div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba67a0c0483eaf92e9cd03e9076be5b50d"> 42</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba67a0c0483eaf92e9cd03e9076be5b50d">XIP_CTRL_PRSC0</a> = 1, </div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebae47f2e1e8c023fd52e25a3dad5e332af"> 43</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebae47f2e1e8c023fd52e25a3dad5e332af">XIP_CTRL_PRSC1</a> = 2, </div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba896815c075a91a8291585eb61b6e0086"> 44</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba896815c075a91a8291585eb61b6e0086">XIP_CTRL_PRSC2</a> = 3, </div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba95ae19cf5d5140df397ead62f151247f"> 45</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba95ae19cf5d5140df397ead62f151247f">XIP_CTRL_CPOL</a> = 4, </div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebad31736f4a159745be94b487079c4c14d"> 46</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebad31736f4a159745be94b487079c4c14d">XIP_CTRL_CPHA</a> = 5, </div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba23be66e49d28dd12c5321e576d2f0c7a"> 47</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba23be66e49d28dd12c5321e576d2f0c7a">XIP_CTRL_SPI_NBYTES_LSB</a> = 6, </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5d13c4fe190fcd68dfcbbbe33d2e844c"> 48</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5d13c4fe190fcd68dfcbbbe33d2e844c">XIP_CTRL_SPI_NBYTES_MSB</a> = 9, </div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba3cbd45a66e05a4fcfc5ec810b8cee937"> 49</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba3cbd45a66e05a4fcfc5ec810b8cee937">XIP_CTRL_XIP_EN</a> = 10, </div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba603f9d8d22ae2a6abc61b666bc88a4df"> 50</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba603f9d8d22ae2a6abc61b666bc88a4df">XIP_CTRL_XIP_ABYTES_LSB</a> = 11, </div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5885ed5fcd2eed969bd921afe8dff4fc"> 51</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5885ed5fcd2eed969bd921afe8dff4fc">XIP_CTRL_XIP_ABYTES_MSB</a> = 12, </div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba8287016f167727f147806aa11129e05b"> 52</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba8287016f167727f147806aa11129e05b">XIP_CTRL_RD_CMD_LSB</a> = 13, </div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba2c78cd2d32cfba4d89f7aab92f7939e7"> 53</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba2c78cd2d32cfba4d89f7aab92f7939e7">XIP_CTRL_RD_CMD_MSB</a> = 20, </div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5aadb2c374d34b878b56a660baec2080"> 54</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5aadb2c374d34b878b56a660baec2080">XIP_CTRL_SPI_CSEN</a> = 21, </div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebaaeb104a59215667aabb5a751632ae781"> 55</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebaaeb104a59215667aabb5a751632ae781">XIP_CTRL_HIGHSPEED</a> = 22, </div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebaf9b56aa629973ce4a9c8ff61a2c90ba3"> 56</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebaf9b56aa629973ce4a9c8ff61a2c90ba3">XIP_CTRL_CDIV0</a> = 23, </div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba68775854b8f2cfa2f32d2eb82a714073"> 57</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba68775854b8f2cfa2f32d2eb82a714073">XIP_CTRL_CDIV1</a> = 24, </div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba43d7305e0e0398cb44c99e70dcd96445"> 58</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba43d7305e0e0398cb44c99e70dcd96445">XIP_CTRL_CDIV2</a> = 25, </div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba61ffffe9acda5c622b48b6360e357eef"> 59</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba61ffffe9acda5c622b48b6360e357eef">XIP_CTRL_CDIV3</a> = 26, </div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba7ad9f81356d6923d524d1c9e39acdd2c"> 61</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba7ad9f81356d6923d524d1c9e39acdd2c">XIP_CTRL_BURST_EN</a> = 29, </div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba76d2379d0e7ab09e7e686bc886888fa5"> 62</a></span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba76d2379d0e7ab09e7e686bc886888fa5">XIP_CTRL_PHY_BUSY</a> = 30, </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span> <a class="code hl_enumvalue" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba2c4a47f88d299782b8618b68fb87d59a">XIP_CTRL_XIP_BUSY</a> = 31 </div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba2c4a47f88d299782b8618b68fb87d59a"> 64</a></span>};</div> +</div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__xip_8h.html#afe2e5682a26cafdb0585d2233bccc7c6">neorv32_xip_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xip_8h.html#a549d68abdf5a3d7484abe6d5370bb999">neorv32_xip_setup</a>(<span class="keywordtype">int</span> prsc, <span class="keywordtype">int</span> cdiv, <span class="keywordtype">int</span> cpol, <span class="keywordtype">int</span> cpha, uint8_t rd_cmd);</div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__xip_8h.html#a0ab2c36c973030a811e6d7abe0afc393">neorv32_xip_start</a>(<span class="keywordtype">int</span> abytes);</div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xip_8h.html#a6aef2ea29451ba2aa55160da777a5115">neorv32_xip_highspeed_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xip_8h.html#ad74f2842ed2251e3ae5c19e06dced0c3">neorv32_xip_highspeed_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span>uint32_t <a class="code hl_function" href="neorv32__xip_8h.html#a88f728101e82939bf7f8b9ab5a904706">neorv32_xip_get_clock_speed</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xip_8h.html#a92f1446a3bb7fe6dee5dbed33882b223">neorv32_xip_spi_trans</a>(<span class="keywordtype">int</span> nbytes, uint64_t *rtx_data);</div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_xip_h</span></div> +<div class="ttc" id="aneorv32__xip_8h_html_a0ab2c36c973030a811e6d7abe0afc393"><div class="ttname"><a href="neorv32__xip_8h.html#a0ab2c36c973030a811e6d7abe0afc393">neorv32_xip_start</a></div><div class="ttdeci">int neorv32_xip_start(int abytes)</div><div class="ttdef"><b>Definition</b> neorv32_xip.c:86</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a549d68abdf5a3d7484abe6d5370bb999"><div class="ttname"><a href="neorv32__xip_8h.html#a549d68abdf5a3d7484abe6d5370bb999">neorv32_xip_setup</a></div><div class="ttdeci">void neorv32_xip_setup(int prsc, int cdiv, int cpol, int cpha, uint8_t rd_cmd)</div><div class="ttdef"><b>Definition</b> neorv32_xip.c:49</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a6aef2ea29451ba2aa55160da777a5115"><div class="ttname"><a href="neorv32__xip_8h.html#a6aef2ea29451ba2aa55160da777a5115">neorv32_xip_highspeed_enable</a></div><div class="ttdeci">void neorv32_xip_highspeed_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_xip.c:116</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceb"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceb">NEORV32_XIP_CTRL_enum</a></div><div class="ttdeci">NEORV32_XIP_CTRL_enum</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:40</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba23be66e49d28dd12c5321e576d2f0c7a"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba23be66e49d28dd12c5321e576d2f0c7a">XIP_CTRL_SPI_NBYTES_LSB</a></div><div class="ttdeci">@ XIP_CTRL_SPI_NBYTES_LSB</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:47</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba27658ce3cc81c9e258b73fb02d7f1045"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba27658ce3cc81c9e258b73fb02d7f1045">XIP_CTRL_EN</a></div><div class="ttdeci">@ XIP_CTRL_EN</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:41</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba2c4a47f88d299782b8618b68fb87d59a"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba2c4a47f88d299782b8618b68fb87d59a">XIP_CTRL_XIP_BUSY</a></div><div class="ttdeci">@ XIP_CTRL_XIP_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:63</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba2c78cd2d32cfba4d89f7aab92f7939e7"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba2c78cd2d32cfba4d89f7aab92f7939e7">XIP_CTRL_RD_CMD_MSB</a></div><div class="ttdeci">@ XIP_CTRL_RD_CMD_MSB</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:53</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba3cbd45a66e05a4fcfc5ec810b8cee937"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba3cbd45a66e05a4fcfc5ec810b8cee937">XIP_CTRL_XIP_EN</a></div><div class="ttdeci">@ XIP_CTRL_XIP_EN</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:49</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba43d7305e0e0398cb44c99e70dcd96445"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba43d7305e0e0398cb44c99e70dcd96445">XIP_CTRL_CDIV2</a></div><div class="ttdeci">@ XIP_CTRL_CDIV2</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:58</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba5885ed5fcd2eed969bd921afe8dff4fc"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5885ed5fcd2eed969bd921afe8dff4fc">XIP_CTRL_XIP_ABYTES_MSB</a></div><div class="ttdeci">@ XIP_CTRL_XIP_ABYTES_MSB</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:51</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba5aadb2c374d34b878b56a660baec2080"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5aadb2c374d34b878b56a660baec2080">XIP_CTRL_SPI_CSEN</a></div><div class="ttdeci">@ XIP_CTRL_SPI_CSEN</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:54</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba5d13c4fe190fcd68dfcbbbe33d2e844c"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba5d13c4fe190fcd68dfcbbbe33d2e844c">XIP_CTRL_SPI_NBYTES_MSB</a></div><div class="ttdeci">@ XIP_CTRL_SPI_NBYTES_MSB</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:48</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba603f9d8d22ae2a6abc61b666bc88a4df"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba603f9d8d22ae2a6abc61b666bc88a4df">XIP_CTRL_XIP_ABYTES_LSB</a></div><div class="ttdeci">@ XIP_CTRL_XIP_ABYTES_LSB</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:50</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba61ffffe9acda5c622b48b6360e357eef"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba61ffffe9acda5c622b48b6360e357eef">XIP_CTRL_CDIV3</a></div><div class="ttdeci">@ XIP_CTRL_CDIV3</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:59</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba67a0c0483eaf92e9cd03e9076be5b50d"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba67a0c0483eaf92e9cd03e9076be5b50d">XIP_CTRL_PRSC0</a></div><div class="ttdeci">@ XIP_CTRL_PRSC0</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:42</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba68775854b8f2cfa2f32d2eb82a714073"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba68775854b8f2cfa2f32d2eb82a714073">XIP_CTRL_CDIV1</a></div><div class="ttdeci">@ XIP_CTRL_CDIV1</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:57</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba76d2379d0e7ab09e7e686bc886888fa5"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba76d2379d0e7ab09e7e686bc886888fa5">XIP_CTRL_PHY_BUSY</a></div><div class="ttdeci">@ XIP_CTRL_PHY_BUSY</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:62</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba7ad9f81356d6923d524d1c9e39acdd2c"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba7ad9f81356d6923d524d1c9e39acdd2c">XIP_CTRL_BURST_EN</a></div><div class="ttdeci">@ XIP_CTRL_BURST_EN</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:61</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba8287016f167727f147806aa11129e05b"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba8287016f167727f147806aa11129e05b">XIP_CTRL_RD_CMD_LSB</a></div><div class="ttdeci">@ XIP_CTRL_RD_CMD_LSB</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:52</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba896815c075a91a8291585eb61b6e0086"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba896815c075a91a8291585eb61b6e0086">XIP_CTRL_PRSC2</a></div><div class="ttdeci">@ XIP_CTRL_PRSC2</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:44</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483ceba95ae19cf5d5140df397ead62f151247f"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceba95ae19cf5d5140df397ead62f151247f">XIP_CTRL_CPOL</a></div><div class="ttdeci">@ XIP_CTRL_CPOL</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:45</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483cebaaeb104a59215667aabb5a751632ae781"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebaaeb104a59215667aabb5a751632ae781">XIP_CTRL_HIGHSPEED</a></div><div class="ttdeci">@ XIP_CTRL_HIGHSPEED</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:55</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483cebad31736f4a159745be94b487079c4c14d"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebad31736f4a159745be94b487079c4c14d">XIP_CTRL_CPHA</a></div><div class="ttdeci">@ XIP_CTRL_CPHA</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:46</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483cebae47f2e1e8c023fd52e25a3dad5e332af"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebae47f2e1e8c023fd52e25a3dad5e332af">XIP_CTRL_PRSC1</a></div><div class="ttdeci">@ XIP_CTRL_PRSC1</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:43</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a72ed1ff87de1222cc3a13177c7483cebaf9b56aa629973ce4a9c8ff61a2c90ba3"><div class="ttname"><a href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483cebaf9b56aa629973ce4a9c8ff61a2c90ba3">XIP_CTRL_CDIV0</a></div><div class="ttdeci">@ XIP_CTRL_CDIV0</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:56</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a88f728101e82939bf7f8b9ab5a904706"><div class="ttname"><a href="neorv32__xip_8h.html#a88f728101e82939bf7f8b9ab5a904706">neorv32_xip_get_clock_speed</a></div><div class="ttdeci">uint32_t neorv32_xip_get_clock_speed(void)</div><div class="ttdef"><b>Definition</b> neorv32_xip.c:136</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_a92f1446a3bb7fe6dee5dbed33882b223"><div class="ttname"><a href="neorv32__xip_8h.html#a92f1446a3bb7fe6dee5dbed33882b223">neorv32_xip_spi_trans</a></div><div class="ttdeci">void neorv32_xip_spi_trans(int nbytes, uint64_t *rtx_data)</div><div class="ttdef"><b>Definition</b> neorv32_xip.c:167</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_ad74f2842ed2251e3ae5c19e06dced0c3"><div class="ttname"><a href="neorv32__xip_8h.html#ad74f2842ed2251e3ae5c19e06dced0c3">neorv32_xip_highspeed_disable</a></div><div class="ttdeci">void neorv32_xip_highspeed_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_xip.c:125</div></div> +<div class="ttc" id="aneorv32__xip_8h_html_afe2e5682a26cafdb0585d2233bccc7c6"><div class="ttname"><a href="neorv32__xip_8h.html#afe2e5682a26cafdb0585d2233bccc7c6">neorv32_xip_available</a></div><div class="ttdeci">int neorv32_xip_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_xip.c:26</div></div> +<div class="ttc" id="astructneorv32__xip__t_html"><div class="ttname"><a href="structneorv32__xip__t.html">neorv32_xip_t</a></div><div class="ttdef"><b>Definition</b> neorv32_xip.h:29</div></div> +<div class="ttc" id="astructneorv32__xip__t_html_a516ab9c075ef6d1fb741e243db7703b2"><div class="ttname"><a href="structneorv32__xip__t.html#a516ab9c075ef6d1fb741e243db7703b2">neorv32_xip_t::DATA_HI</a></div><div class="ttdeci">uint32_t DATA_HI</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:33</div></div> +<div class="ttc" id="astructneorv32__xip__t_html_a7ead9d6a4f784d766a6b2755c6d35235"><div class="ttname"><a href="structneorv32__xip__t.html#a7ead9d6a4f784d766a6b2755c6d35235">neorv32_xip_t::CTRL</a></div><div class="ttdeci">uint32_t CTRL</div><div class="ttdef"><b>Definition</b> neorv32_xip.h:30</div></div> +<div class="ttc" id="astructneorv32__xip__t_html_aacb77d586c3caec518e8e0024cfe745c"><div class="ttname"><a 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href="#var-members">Variables</a> </div> + <div class="headertitle"><div class="title">neorv32_xirq.c File Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p>External Interrupt controller HW driver source file. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:a14661d628dd31e6bfce89376c6614627" id="r_a14661d628dd31e6bfce89376c6614627"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a14661d628dd31e6bfce89376c6614627">__neorv32_xirq_core</a> (void)</td></tr> +<tr class="separator:a14661d628dd31e6bfce89376c6614627"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae4d9362b23a1341c595a4cd239a87091" id="r_ae4d9362b23a1341c595a4cd239a87091"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae4d9362b23a1341c595a4cd239a87091">__neorv32_xirq_dummy_handler</a> (void)</td></tr> +<tr class="separator:ae4d9362b23a1341c595a4cd239a87091"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aaf30757d526030a8d81081915ab29a76" id="r_aaf30757d526030a8d81081915ab29a76"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aaf30757d526030a8d81081915ab29a76">neorv32_xirq_available</a> (void)</td></tr> +<tr class="separator:aaf30757d526030a8d81081915ab29a76"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9295997fce7114a8205325c4d75dd200" id="r_a9295997fce7114a8205325c4d75dd200"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9295997fce7114a8205325c4d75dd200">neorv32_xirq_setup</a> (void)</td></tr> +<tr class="separator:a9295997fce7114a8205325c4d75dd200"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a76468156ef52b371e06bc2ca8eddcd27" id="r_a76468156ef52b371e06bc2ca8eddcd27"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a76468156ef52b371e06bc2ca8eddcd27">neorv32_xirq_global_enable</a> (void)</td></tr> +<tr class="separator:a76468156ef52b371e06bc2ca8eddcd27"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac64d3ff5619968499bccebebe6a6cab3" id="r_ac64d3ff5619968499bccebebe6a6cab3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac64d3ff5619968499bccebebe6a6cab3">neorv32_xirq_global_disable</a> (void)</td></tr> +<tr class="separator:ac64d3ff5619968499bccebebe6a6cab3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a717a8e34908cc01345e68920e76f229c" id="r_a717a8e34908cc01345e68920e76f229c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a717a8e34908cc01345e68920e76f229c">neorv32_xirq_get_num</a> (void)</td></tr> +<tr class="separator:a717a8e34908cc01345e68920e76f229c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0d137f09d1e7dcd31c157b856033ac42" id="r_a0d137f09d1e7dcd31c157b856033ac42"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0d137f09d1e7dcd31c157b856033ac42">neorv32_xirq_setup_trigger</a> (int channel, int config)</td></tr> +<tr class="separator:a0d137f09d1e7dcd31c157b856033ac42"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a83ecaf568a6f6bcb1e1efdb1eef6df9c" id="r_a83ecaf568a6f6bcb1e1efdb1eef6df9c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a83ecaf568a6f6bcb1e1efdb1eef6df9c">neorv32_xirq_clear_pending</a> (int channel)</td></tr> +<tr class="separator:a83ecaf568a6f6bcb1e1efdb1eef6df9c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abe63c0968c94b472082c8156a1a7db5c" id="r_abe63c0968c94b472082c8156a1a7db5c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abe63c0968c94b472082c8156a1a7db5c">neorv32_xirq_channel_enable</a> (int channel)</td></tr> +<tr class="separator:abe63c0968c94b472082c8156a1a7db5c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae17509ad0c828aa9b36747b253cdbf0a" id="r_ae17509ad0c828aa9b36747b253cdbf0a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae17509ad0c828aa9b36747b253cdbf0a">neorv32_xirq_channel_disable</a> (int channel)</td></tr> +<tr class="separator:ae17509ad0c828aa9b36747b253cdbf0a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9129984f91c02afafaa072a5d86f9876" id="r_a9129984f91c02afafaa072a5d86f9876"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9129984f91c02afafaa072a5d86f9876">neorv32_xirq_install</a> (int channel, void(*handler)(void))</td></tr> +<tr class="separator:a9129984f91c02afafaa072a5d86f9876"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a49ae67d1d5066cd795149e96b81127f7" id="r_a49ae67d1d5066cd795149e96b81127f7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a49ae67d1d5066cd795149e96b81127f7">neorv32_xirq_uninstall</a> (int channel)</td></tr> +<tr class="separator:a49ae67d1d5066cd795149e96b81127f7"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="var-members" name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:a76d73c3bf372989703c685a9e8d229ac" id="r_a76d73c3bf372989703c685a9e8d229ac"><td class="memItemLeft" align="right" valign="top">static uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a76d73c3bf372989703c685a9e8d229ac">__neorv32_xirq_vector_lut</a> [32]</td></tr> +<tr class="separator:a76d73c3bf372989703c685a9e8d229ac"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>External Interrupt controller HW driver source file. </p> +<dl class="section note"><dt>Note</dt><dd>These functions should only be used if the XIRQ controller was synthesized.</dd></dl> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Function Documentation</h2> +<a id="a14661d628dd31e6bfce89376c6614627" name="a14661d628dd31e6bfce89376c6614627"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a14661d628dd31e6bfce89376c6614627">&#9670;&#160;</a></span>__neorv32_xirq_core()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">static void __neorv32_xirq_core </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">static</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>This is the actual second-level (F)IRQ handler for the XIRQ. It will call the previously installed handler if an XIRQ fires. </p> + +</div> +</div> +<a id="ae4d9362b23a1341c595a4cd239a87091" name="ae4d9362b23a1341c595a4cd239a87091"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae4d9362b23a1341c595a4cd239a87091">&#9670;&#160;</a></span>__neorv32_xirq_dummy_handler()</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">static void __neorv32_xirq_dummy_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">static</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>XIRQ dummy handler. </p> + +</div> +</div> +<a id="aaf30757d526030a8d81081915ab29a76" name="aaf30757d526030a8d81081915ab29a76"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaf30757d526030a8d81081915ab29a76">&#9670;&#160;</a></span>neorv32_xirq_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if external interrupt controller was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if XIRQ was not synthesized, 1 if EXTIRQ is available. </dd></dl> + +</div> +</div> +<a id="ae17509ad0c828aa9b36747b253cdbf0a" name="ae17509ad0c828aa9b36747b253cdbf0a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae17509ad0c828aa9b36747b253cdbf0a">&#9670;&#160;</a></span>neorv32_xirq_channel_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_channel_disable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable IRQ channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="abe63c0968c94b472082c8156a1a7db5c" name="abe63c0968c94b472082c8156a1a7db5c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abe63c0968c94b472082c8156a1a7db5c">&#9670;&#160;</a></span>neorv32_xirq_channel_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_channel_enable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable IRQ channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a83ecaf568a6f6bcb1e1efdb1eef6df9c" name="a83ecaf568a6f6bcb1e1efdb1eef6df9c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a83ecaf568a6f6bcb1e1efdb1eef6df9c">&#9670;&#160;</a></span>neorv32_xirq_clear_pending()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_clear_pending </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear pending interrupt.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a717a8e34908cc01345e68920e76f229c" name="a717a8e34908cc01345e68920e76f229c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a717a8e34908cc01345e68920e76f229c">&#9670;&#160;</a></span>neorv32_xirq_get_num()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_get_num </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get number of implemented XIRQ channels</p> +<dl class="section return"><dt>Returns</dt><dd>Number of implemented channels (0..32). </dd></dl> + +</div> +</div> +<a id="ac64d3ff5619968499bccebebe6a6cab3" name="ac64d3ff5619968499bccebebe6a6cab3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac64d3ff5619968499bccebebe6a6cab3">&#9670;&#160;</a></span>neorv32_xirq_global_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_global_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Globally disable XIRQ interrupts (via according FIRQ channel).</p> +<dl class="section note"><dt>Note</dt><dd>Triggered / triggering XIRQ will remain pending. </dd></dl> + +</div> +</div> +<a id="a76468156ef52b371e06bc2ca8eddcd27" name="a76468156ef52b371e06bc2ca8eddcd27"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a76468156ef52b371e06bc2ca8eddcd27">&#9670;&#160;</a></span>neorv32_xirq_global_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_global_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Globally enable XIRQ interrupts (via according FIRQ channel).</p> +<dl class="section note"><dt>Note</dt><dd>Triggered / triggering XIRQ will remain pending. </dd></dl> + +</div> +</div> +<a id="a9129984f91c02afafaa072a5d86f9876" name="a9129984f91c02afafaa072a5d86f9876"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9129984f91c02afafaa072a5d86f9876">&#9670;&#160;</a></span>neorv32_xirq_install()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_install </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">void(*</td> <td class="paramname"><span class="paramname"><em>handler&#160;</em></span>)(void)&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Install interrupt handler function for XIRQ channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">handler</td><td>The actual handler function for the specified interrupt (function MUST be of type "void function(void);"). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if success, 1 if error. </dd></dl> + +</div> +</div> +<a id="a9295997fce7114a8205325c4d75dd200" name="a9295997fce7114a8205325c4d75dd200"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9295997fce7114a8205325c4d75dd200">&#9670;&#160;</a></span>neorv32_xirq_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_setup </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initialize XIRQ controller.</p> +<dl class="section note"><dt>Note</dt><dd>All interrupt channels will be deactivated, all pending IRQs will be deleted and all handler addresses will be deleted.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if success, != 0 if error. </dd></dl> + +</div> +</div> +<a id="a0d137f09d1e7dcd31c157b856033ac42" name="a0d137f09d1e7dcd31c157b856033ac42"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0d137f09d1e7dcd31c157b856033ac42">&#9670;&#160;</a></span>neorv32_xirq_setup_trigger()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_setup_trigger </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>config</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure a channel's trigger type.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>Trigger type: 00 = low-level, 01 = high-level, 10 = falling-edge, 11 = rising-edge. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a49ae67d1d5066cd795149e96b81127f7" name="a49ae67d1d5066cd795149e96b81127f7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a49ae67d1d5066cd795149e96b81127f7">&#9670;&#160;</a></span>neorv32_xirq_uninstall()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_uninstall </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Uninstall interrupt handler function for XIRQ channel.</p> +<dl class="section note"><dt>Note</dt><dd>This will also deactivate the according XIRQ channel.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 if success, 1 if error. </dd></dl> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a id="a76d73c3bf372989703c685a9e8d229ac" name="a76d73c3bf372989703c685a9e8d229ac"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a76d73c3bf372989703c685a9e8d229ac">&#9670;&#160;</a></span>__neorv32_xirq_vector_lut</h2> + +<div class="memitem"> +<div class="memproto"> +<table class="mlabels"> + <tr> + <td class="mlabels-left"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __neorv32_xirq_vector_lut[32]</td> + </tr> + </table> + </td> + <td class="mlabels-right"> +<span class="mlabels"><span class="mlabel">static</span></span> </td> + </tr> +</table> +</div><div class="memdoc"> +<p>The &gt;private&lt; trap vector look-up table of the XIRQ. </p> + +</div> +</div> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> 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+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">IO Device: External Interrupt Controller (XIRQ)</div></td></tr> +<tr class="memitem:a0c0886139e9837867202e5f6a83307c4" id="r_a0c0886139e9837867202e5f6a83307c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0c0886139e9837867202e5f6a83307c4">NEORV32_XIRQ</a>&#160;&#160;&#160;((<a class="el" href="structneorv32__xirq__t.html">neorv32_xirq_t</a>*) (<a class="el" href="neorv32_8h.html#a942a897be2d4ae6820bee0f7bb3a0ff1">NEORV32_XIRQ_BASE</a>))</td></tr> +<tr class="separator:a0c0886139e9837867202e5f6a83307c4"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr><td colspan="2"><div class="groupHeader"></div></td></tr> +<tr class="memitem:a8bc89e6a47b4d0d95fb2afac4cdc9292" id="r_a8bc89e6a47b4d0d95fb2afac4cdc9292"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8bc89e6a47b4d0d95fb2afac4cdc9292">XIRQ_TRIGGER_LEVEL_LOW</a>&#160;&#160;&#160;(0b00)</td></tr> +<tr class="separator:a8bc89e6a47b4d0d95fb2afac4cdc9292"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9b10e89b2e257e1af410bff89f29911c" id="r_a9b10e89b2e257e1af410bff89f29911c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9b10e89b2e257e1af410bff89f29911c">XIRQ_TRIGGER_LEVEL_HIGH</a>&#160;&#160;&#160;(0b01)</td></tr> +<tr class="separator:a9b10e89b2e257e1af410bff89f29911c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a59316ffc7ee1aacf1d55d460bdca4d04" id="r_a59316ffc7ee1aacf1d55d460bdca4d04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a59316ffc7ee1aacf1d55d460bdca4d04">XIRQ_TRIGGER_EDGE_FALLING</a>&#160;&#160;&#160;(0b10)</td></tr> +<tr class="separator:a59316ffc7ee1aacf1d55d460bdca4d04"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ab7a05371e4dc3de3a9be11c59f5376ee" id="r_ab7a05371e4dc3de3a9be11c59f5376ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab7a05371e4dc3de3a9be11c59f5376ee">XIRQ_TRIGGER_EDGE_RISING</a>&#160;&#160;&#160;(0b11)</td></tr> +<tr class="separator:ab7a05371e4dc3de3a9be11c59f5376ee"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a> +Functions</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">Prototypes</div></td></tr> +<tr class="memitem:aaf30757d526030a8d81081915ab29a76" id="r_aaf30757d526030a8d81081915ab29a76"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aaf30757d526030a8d81081915ab29a76">neorv32_xirq_available</a> (void)</td></tr> +<tr class="separator:aaf30757d526030a8d81081915ab29a76"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9295997fce7114a8205325c4d75dd200" id="r_a9295997fce7114a8205325c4d75dd200"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9295997fce7114a8205325c4d75dd200">neorv32_xirq_setup</a> (void)</td></tr> +<tr class="separator:a9295997fce7114a8205325c4d75dd200"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a76468156ef52b371e06bc2ca8eddcd27" id="r_a76468156ef52b371e06bc2ca8eddcd27"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a76468156ef52b371e06bc2ca8eddcd27">neorv32_xirq_global_enable</a> (void)</td></tr> +<tr class="separator:a76468156ef52b371e06bc2ca8eddcd27"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac64d3ff5619968499bccebebe6a6cab3" id="r_ac64d3ff5619968499bccebebe6a6cab3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac64d3ff5619968499bccebebe6a6cab3">neorv32_xirq_global_disable</a> (void)</td></tr> +<tr class="separator:ac64d3ff5619968499bccebebe6a6cab3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a717a8e34908cc01345e68920e76f229c" id="r_a717a8e34908cc01345e68920e76f229c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" 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class="separator:a83ecaf568a6f6bcb1e1efdb1eef6df9c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abe63c0968c94b472082c8156a1a7db5c" id="r_abe63c0968c94b472082c8156a1a7db5c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abe63c0968c94b472082c8156a1a7db5c">neorv32_xirq_channel_enable</a> (int channel)</td></tr> +<tr class="separator:abe63c0968c94b472082c8156a1a7db5c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae17509ad0c828aa9b36747b253cdbf0a" id="r_ae17509ad0c828aa9b36747b253cdbf0a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae17509ad0c828aa9b36747b253cdbf0a">neorv32_xirq_channel_disable</a> (int channel)</td></tr> +<tr class="separator:ae17509ad0c828aa9b36747b253cdbf0a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9129984f91c02afafaa072a5d86f9876" id="r_a9129984f91c02afafaa072a5d86f9876"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9129984f91c02afafaa072a5d86f9876">neorv32_xirq_install</a> (int channel, void(*handler)(void))</td></tr> +<tr class="separator:a9129984f91c02afafaa072a5d86f9876"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a49ae67d1d5066cd795149e96b81127f7" id="r_a49ae67d1d5066cd795149e96b81127f7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a49ae67d1d5066cd795149e96b81127f7">neorv32_xirq_uninstall</a> (int channel)</td></tr> +<tr class="separator:a49ae67d1d5066cd795149e96b81127f7"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>External Interrupt controller HW driver header file. </p> +<dl class="section see"><dt>See also</dt><dd><a href="https://stnolting.github.io/neorv32/sw/files.html">https://stnolting.github.io/neorv32/sw/files.html</a> </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="a0c0886139e9837867202e5f6a83307c4" name="a0c0886139e9837867202e5f6a83307c4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0c0886139e9837867202e5f6a83307c4">&#9670;&#160;</a></span>NEORV32_XIRQ</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define NEORV32_XIRQ&#160;&#160;&#160;((<a class="el" href="structneorv32__xirq__t.html">neorv32_xirq_t</a>*) (<a class="el" href="neorv32_8h.html#a942a897be2d4ae6820bee0f7bb3a0ff1">NEORV32_XIRQ_BASE</a>))</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ module hardware access (<a class="el" href="structneorv32__xirq__t.html">neorv32_xirq_t</a>) </p> + +</div> +</div> +<a id="a59316ffc7ee1aacf1d55d460bdca4d04" name="a59316ffc7ee1aacf1d55d460bdca4d04"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a59316ffc7ee1aacf1d55d460bdca4d04">&#9670;&#160;</a></span>XIRQ_TRIGGER_EDGE_FALLING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIRQ_TRIGGER_EDGE_FALLING&#160;&#160;&#160;(0b10)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ trigger configuration </p> + +</div> +</div> +<a id="ab7a05371e4dc3de3a9be11c59f5376ee" name="ab7a05371e4dc3de3a9be11c59f5376ee"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ab7a05371e4dc3de3a9be11c59f5376ee">&#9670;&#160;</a></span>XIRQ_TRIGGER_EDGE_RISING</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIRQ_TRIGGER_EDGE_RISING&#160;&#160;&#160;(0b11)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ trigger configuration </p> + +</div> +</div> +<a id="a9b10e89b2e257e1af410bff89f29911c" name="a9b10e89b2e257e1af410bff89f29911c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9b10e89b2e257e1af410bff89f29911c">&#9670;&#160;</a></span>XIRQ_TRIGGER_LEVEL_HIGH</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIRQ_TRIGGER_LEVEL_HIGH&#160;&#160;&#160;(0b01)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ trigger configuration </p> + +</div> +</div> +<a id="a8bc89e6a47b4d0d95fb2afac4cdc9292" name="a8bc89e6a47b4d0d95fb2afac4cdc9292"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8bc89e6a47b4d0d95fb2afac4cdc9292">&#9670;&#160;</a></span>XIRQ_TRIGGER_LEVEL_LOW</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define XIRQ_TRIGGER_LEVEL_LOW&#160;&#160;&#160;(0b00)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>XIRQ trigger configuration </p> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="aaf30757d526030a8d81081915ab29a76" name="aaf30757d526030a8d81081915ab29a76"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aaf30757d526030a8d81081915ab29a76">&#9670;&#160;</a></span>neorv32_xirq_available()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_available </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Check if external interrupt controller was synthesized.</p> +<dl class="section return"><dt>Returns</dt><dd>0 if XIRQ was not synthesized, 1 if EXTIRQ is available. </dd></dl> + +</div> +</div> +<a id="ae17509ad0c828aa9b36747b253cdbf0a" name="ae17509ad0c828aa9b36747b253cdbf0a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae17509ad0c828aa9b36747b253cdbf0a">&#9670;&#160;</a></span>neorv32_xirq_channel_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_channel_disable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable IRQ channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="abe63c0968c94b472082c8156a1a7db5c" name="abe63c0968c94b472082c8156a1a7db5c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abe63c0968c94b472082c8156a1a7db5c">&#9670;&#160;</a></span>neorv32_xirq_channel_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_channel_enable </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable IRQ channel.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a83ecaf568a6f6bcb1e1efdb1eef6df9c" name="a83ecaf568a6f6bcb1e1efdb1eef6df9c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a83ecaf568a6f6bcb1e1efdb1eef6df9c">&#9670;&#160;</a></span>neorv32_xirq_clear_pending()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_clear_pending </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear pending interrupt.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a717a8e34908cc01345e68920e76f229c" name="a717a8e34908cc01345e68920e76f229c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a717a8e34908cc01345e68920e76f229c">&#9670;&#160;</a></span>neorv32_xirq_get_num()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_get_num </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Get number of implemented XIRQ channels</p> +<dl class="section return"><dt>Returns</dt><dd>Number of implemented channels (0..32). </dd></dl> + +</div> +</div> +<a id="ac64d3ff5619968499bccebebe6a6cab3" name="ac64d3ff5619968499bccebebe6a6cab3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac64d3ff5619968499bccebebe6a6cab3">&#9670;&#160;</a></span>neorv32_xirq_global_disable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_global_disable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Globally disable XIRQ interrupts (via according FIRQ channel).</p> +<dl class="section note"><dt>Note</dt><dd>Triggered / triggering XIRQ will remain pending. </dd></dl> + +</div> +</div> +<a id="a76468156ef52b371e06bc2ca8eddcd27" name="a76468156ef52b371e06bc2ca8eddcd27"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a76468156ef52b371e06bc2ca8eddcd27">&#9670;&#160;</a></span>neorv32_xirq_global_enable()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_global_enable </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Globally enable XIRQ interrupts (via according FIRQ channel).</p> +<dl class="section note"><dt>Note</dt><dd>Triggered / triggering XIRQ will remain pending. </dd></dl> + +</div> +</div> +<a id="a9129984f91c02afafaa072a5d86f9876" name="a9129984f91c02afafaa072a5d86f9876"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9129984f91c02afafaa072a5d86f9876">&#9670;&#160;</a></span>neorv32_xirq_install()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_install </td> + <td>(</td> + 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+<h2 class="memtitle"><span class="permalink"><a href="#a9295997fce7114a8205325c4d75dd200">&#9670;&#160;</a></span>neorv32_xirq_setup()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_setup </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initialize XIRQ controller.</p> +<dl class="section note"><dt>Note</dt><dd>All interrupt channels will be deactivated, all pending IRQs will be deleted and all handler addresses will be deleted.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if success, != 0 if error. </dd></dl> + +</div> +</div> +<a id="a0d137f09d1e7dcd31c157b856033ac42" name="a0d137f09d1e7dcd31c157b856033ac42"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0d137f09d1e7dcd31c157b856033ac42">&#9670;&#160;</a></span>neorv32_xirq_setup_trigger()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void neorv32_xirq_setup_trigger </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>config</em></span>&#160;)</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure a channel's trigger type.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>Trigger type: 00 = low-level, 01 = high-level, 10 = falling-edge, 11 = rising-edge. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a id="a49ae67d1d5066cd795149e96b81127f7" name="a49ae67d1d5066cd795149e96b81127f7"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a49ae67d1d5066cd795149e96b81127f7">&#9670;&#160;</a></span>neorv32_xirq_uninstall()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int neorv32_xirq_uninstall </td> + <td>(</td> + <td class="paramtype">int</td> <td class="paramname"><span class="paramname"><em>channel</em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Uninstall interrupt handler function for XIRQ channel.</p> +<dl class="section note"><dt>Note</dt><dd>This will also deactivate the according XIRQ channel.</dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>XIRQ interrupt channel (0..31). </td></tr> + </table> + </dd> +</dl> +<dl class="section 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name="l00002"></a><span class="lineno"> 2</span><span class="comment">// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// Copyright (c) NEORV32 contributors. //</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //</span></div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">// Licensed under the BSD-3-Clause license, see LICENSE for details. //</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">// SPDX-License-Identifier: BSD-3-Clause //</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment">// ================================================================================ //</span></div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="preprocessor">#ifndef neorv32_xirq_h</span></div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="preprocessor">#define neorv32_xirq_h</span></div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> </div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="preprocessor">#include &lt;stdint.h&gt;</span></div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> </div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="comment">/**********************************************************************/</span></div> +<div class="foldopen" id="foldopen00027" data-start="{" data-end="};"> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html"> 27</a></span><span class="keyword">typedef</span> <span class="keyword">volatile</span> <span class="keyword">struct </span>__attribute__((packed,aligned(4))) {</div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html#aef3c2b491207abd68bf6392f97096a74"> 28</a></span> uint32_t <a class="code hl_variable" href="structneorv32__xirq__t.html#aef3c2b491207abd68bf6392f97096a74">EIE</a>; </div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html#a788d8004f3b85fb66e947415d8fcc058"> 29</a></span> uint32_t <a class="code hl_variable" href="structneorv32__xirq__t.html#a788d8004f3b85fb66e947415d8fcc058">EIP</a>; </div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html#ae4f7f3f41210ff329b6f82d5dfada88a"> 30</a></span> uint32_t <a class="code hl_variable" href="structneorv32__xirq__t.html#ae4f7f3f41210ff329b6f82d5dfada88a">ESC</a>; </div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html#ab7117c210b5f0a8ebc369eeba6a4a5bc"> 31</a></span> uint32_t <a class="code hl_variable" href="structneorv32__xirq__t.html#ab7117c210b5f0a8ebc369eeba6a4a5bc">TTYP</a>; </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html#a5fe0036a2cada585228b60aaa780e92a"> 32</a></span> uint32_t <a class="code hl_variable" href="structneorv32__xirq__t.html#a5fe0036a2cada585228b60aaa780e92a">TPOL</a>; </div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html#a9be02c0398fab5763a3afbd7a018f092"> 33</a></span> <span class="keyword">const</span> uint32_t <a class="code hl_variable" href="structneorv32__xirq__t.html#a9be02c0398fab5763a3afbd7a018f092">reserved0</a>; </div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html#ac4c999cf3da75e39753619f917d9d654"> 34</a></span> <span class="keyword">const</span> uint32_t <a class="code hl_variable" href="structneorv32__xirq__t.html#ac4c999cf3da75e39753619f917d9d654">reserved1</a>; </div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="structneorv32__xirq__t.html#afba6ed500e1448719783923975b2dc64"> 35</a></span> <span class="keyword">const</span> uint32_t <a class="code hl_variable" href="structneorv32__xirq__t.html#afba6ed500e1448719783923975b2dc64">reserved2</a>; </div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span>} <a class="code hl_struct" href="structneorv32__xirq__t.html">neorv32_xirq_t</a>;</div> +</div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> </div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="neorv32__xirq_8h.html#a0c0886139e9837867202e5f6a83307c4"> 39</a></span><span class="preprocessor">#define NEORV32_XIRQ ((neorv32_xirq_t*) (NEORV32_XIRQ_BASE))</span></div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span><span class="comment">/**********************************************************************/</span></div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"><a class="line" href="neorv32__xirq_8h.html#a8bc89e6a47b4d0d95fb2afac4cdc9292"> 47</a></span><span class="preprocessor">#define XIRQ_TRIGGER_LEVEL_LOW (0b00) </span><span class="comment">// low-level</span></div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"><a class="line" href="neorv32__xirq_8h.html#a9b10e89b2e257e1af410bff89f29911c"> 48</a></span><span class="preprocessor">#define XIRQ_TRIGGER_LEVEL_HIGH (0b01) </span><span class="comment">// high-level</span></div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="neorv32__xirq_8h.html#a59316ffc7ee1aacf1d55d460bdca4d04"> 49</a></span><span class="preprocessor">#define XIRQ_TRIGGER_EDGE_FALLING (0b10) </span><span class="comment">// falling-edge</span></div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="neorv32__xirq_8h.html#ab7a05371e4dc3de3a9be11c59f5376ee"> 50</a></span><span class="preprocessor">#define XIRQ_TRIGGER_EDGE_RISING (0b11) </span><span class="comment">// rising-edge</span></div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span><span class="comment">/**********************************************************************/</span><span class="preprocessor"></span></div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__xirq_8h.html#aaf30757d526030a8d81081915ab29a76">neorv32_xirq_available</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__xirq_8h.html#a9295997fce7114a8205325c4d75dd200">neorv32_xirq_setup</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xirq_8h.html#a76468156ef52b371e06bc2ca8eddcd27">neorv32_xirq_global_enable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xirq_8h.html#ac64d3ff5619968499bccebebe6a6cab3">neorv32_xirq_global_disable</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__xirq_8h.html#a717a8e34908cc01345e68920e76f229c">neorv32_xirq_get_num</a>(<span class="keywordtype">void</span>);</div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xirq_8h.html#a0d137f09d1e7dcd31c157b856033ac42">neorv32_xirq_setup_trigger</a>(<span class="keywordtype">int</span> channel, <span class="keywordtype">int</span> config);</div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xirq_8h.html#a83ecaf568a6f6bcb1e1efdb1eef6df9c">neorv32_xirq_clear_pending</a>(<span class="keywordtype">int</span> channel);</div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xirq_8h.html#abe63c0968c94b472082c8156a1a7db5c">neorv32_xirq_channel_enable</a>(<span class="keywordtype">int</span> channel);</div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span><span class="keywordtype">void</span> <a class="code hl_function" href="neorv32__xirq_8h.html#ae17509ad0c828aa9b36747b253cdbf0a">neorv32_xirq_channel_disable</a>(<span class="keywordtype">int</span> channel);</div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__xirq_8h.html#a9129984f91c02afafaa072a5d86f9876">neorv32_xirq_install</a>(<span class="keywordtype">int</span> channel, <span class="keywordtype">void</span> (*handler)(<span class="keywordtype">void</span>));</div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="keywordtype">int</span> <a class="code hl_function" href="neorv32__xirq_8h.html#a49ae67d1d5066cd795149e96b81127f7">neorv32_xirq_uninstall</a>(<span class="keywordtype">int</span> channel);</div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="preprocessor">#endif </span><span class="comment">// neorv32_xirq_h</span></div> +<div class="ttc" id="aneorv32__xirq_8h_html_a0d137f09d1e7dcd31c157b856033ac42"><div class="ttname"><a href="neorv32__xirq_8h.html#a0d137f09d1e7dcd31c157b856033ac42">neorv32_xirq_setup_trigger</a></div><div class="ttdeci">void neorv32_xirq_setup_trigger(int channel, int config)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:157</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_a49ae67d1d5066cd795149e96b81127f7"><div class="ttname"><a href="neorv32__xirq_8h.html#a49ae67d1d5066cd795149e96b81127f7">neorv32_xirq_uninstall</a></div><div class="ttdeci">int neorv32_xirq_uninstall(int channel)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:242</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_a717a8e34908cc01345e68920e76f229c"><div class="ttname"><a href="neorv32__xirq_8h.html#a717a8e34908cc01345e68920e76f229c">neorv32_xirq_get_num</a></div><div class="ttdeci">int neorv32_xirq_get_num(void)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:126</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_a76468156ef52b371e06bc2ca8eddcd27"><div class="ttname"><a href="neorv32__xirq_8h.html#a76468156ef52b371e06bc2ca8eddcd27">neorv32_xirq_global_enable</a></div><div class="ttdeci">void neorv32_xirq_global_enable(void)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:102</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_a83ecaf568a6f6bcb1e1efdb1eef6df9c"><div class="ttname"><a href="neorv32__xirq_8h.html#a83ecaf568a6f6bcb1e1efdb1eef6df9c">neorv32_xirq_clear_pending</a></div><div class="ttdeci">void neorv32_xirq_clear_pending(int channel)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:185</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_a9129984f91c02afafaa072a5d86f9876"><div class="ttname"><a href="neorv32__xirq_8h.html#a9129984f91c02afafaa072a5d86f9876">neorv32_xirq_install</a></div><div class="ttdeci">int neorv32_xirq_install(int channel, void(*handler)(void))</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:223</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_a9295997fce7114a8205325c4d75dd200"><div class="ttname"><a href="neorv32__xirq_8h.html#a9295997fce7114a8205325c4d75dd200">neorv32_xirq_setup</a></div><div class="ttdeci">int neorv32_xirq_setup(void)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:81</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_aaf30757d526030a8d81081915ab29a76"><div class="ttname"><a href="neorv32__xirq_8h.html#aaf30757d526030a8d81081915ab29a76">neorv32_xirq_available</a></div><div class="ttdeci">int neorv32_xirq_available(void)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:62</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_abe63c0968c94b472082c8156a1a7db5c"><div class="ttname"><a href="neorv32__xirq_8h.html#abe63c0968c94b472082c8156a1a7db5c">neorv32_xirq_channel_enable</a></div><div class="ttdeci">void neorv32_xirq_channel_enable(int channel)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:197</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_ac64d3ff5619968499bccebebe6a6cab3"><div class="ttname"><a href="neorv32__xirq_8h.html#ac64d3ff5619968499bccebebe6a6cab3">neorv32_xirq_global_disable</a></div><div class="ttdeci">void neorv32_xirq_global_disable(void)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:114</div></div> +<div class="ttc" id="aneorv32__xirq_8h_html_ae17509ad0c828aa9b36747b253cdbf0a"><div class="ttname"><a href="neorv32__xirq_8h.html#ae17509ad0c828aa9b36747b253cdbf0a">neorv32_xirq_channel_disable</a></div><div class="ttdeci">void neorv32_xirq_channel_disable(int channel)</div><div class="ttdef"><b>Definition</b> neorv32_xirq.c:209</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html"><div class="ttname"><a href="structneorv32__xirq__t.html">neorv32_xirq_t</a></div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:27</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html_a5fe0036a2cada585228b60aaa780e92a"><div class="ttname"><a href="structneorv32__xirq__t.html#a5fe0036a2cada585228b60aaa780e92a">neorv32_xirq_t::TPOL</a></div><div class="ttdeci">uint32_t TPOL</div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:32</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html_a788d8004f3b85fb66e947415d8fcc058"><div class="ttname"><a href="structneorv32__xirq__t.html#a788d8004f3b85fb66e947415d8fcc058">neorv32_xirq_t::EIP</a></div><div class="ttdeci">uint32_t EIP</div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:29</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html_a9be02c0398fab5763a3afbd7a018f092"><div class="ttname"><a href="structneorv32__xirq__t.html#a9be02c0398fab5763a3afbd7a018f092">neorv32_xirq_t::reserved0</a></div><div class="ttdeci">const uint32_t reserved0</div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:33</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html_ab7117c210b5f0a8ebc369eeba6a4a5bc"><div class="ttname"><a href="structneorv32__xirq__t.html#ab7117c210b5f0a8ebc369eeba6a4a5bc">neorv32_xirq_t::TTYP</a></div><div class="ttdeci">uint32_t TTYP</div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:31</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html_ac4c999cf3da75e39753619f917d9d654"><div class="ttname"><a href="structneorv32__xirq__t.html#ac4c999cf3da75e39753619f917d9d654">neorv32_xirq_t::reserved1</a></div><div class="ttdeci">const uint32_t reserved1</div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:34</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html_ae4f7f3f41210ff329b6f82d5dfada88a"><div class="ttname"><a href="structneorv32__xirq__t.html#ae4f7f3f41210ff329b6f82d5dfada88a">neorv32_xirq_t::ESC</a></div><div class="ttdeci">uint32_t ESC</div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:30</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html_aef3c2b491207abd68bf6392f97096a74"><div class="ttname"><a href="structneorv32__xirq__t.html#aef3c2b491207abd68bf6392f97096a74">neorv32_xirq_t::EIE</a></div><div class="ttdeci">uint32_t EIE</div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:28</div></div> +<div class="ttc" id="astructneorv32__xirq__t_html_afba6ed500e1448719783923975b2dc64"><div class="ttname"><a href="structneorv32__xirq__t.html#afba6ed500e1448719783923975b2dc64">neorv32_xirq_t::reserved2</a></div><div class="ttdeci">const uint32_t reserved2</div><div class="ttdef"><b>Definition</b> neorv32_xirq.h:35</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a 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Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: sw/example/demo_onewire/onewire_aux.h Source File</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script 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class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// APPLICATION NOTE 187 &quot;1-Wire Search Algorithm&quot; by Maxim Integrated</span></div> +<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">// https://www.maximintegrated.com/en/design/technical-documents/app-notes/1/187.html</span></div> +<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">// modified for the NEORV32 Processor</span></div> +<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span> </div> +<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="preprocessor">#ifndef onewire_aux_h</span></div> +<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="preprocessor">#define onewire_aux_h</span></div> +<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span> </div> +<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="preprocessor">#include &lt;<a class="code" href="neorv32_8h.html">neorv32.h</a>&gt;</span></div> +<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span> </div> +<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span><span class="comment">// definitions</span></div> +<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="preprocessor">#define FALSE 0</span></div> +<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="preprocessor">#define TRUE 1</span></div> +<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span> </div> +<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span><span class="keyword">static</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> dscrc_table[] = {</div> +<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span> 0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,</div> +<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span> 157,195, 33,127,252,162, 64, 30, 95, 1,227,189, 62, 96,130,220,</div> +<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span> 35,125,159,193, 66, 28,254,160,225,191, 93, 3,128,222, 60, 98,</div> +<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span> 190,224, 2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,</div> +<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span> 70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89, 7,</div> +<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span> 219,133,103, 57,186,228, 6, 88, 25, 71,165,251,120, 38,196,154,</div> +<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> 101, 59,217,135, 4, 90,184,230,167,249, 27, 69,198,152,122, 36,</div> +<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> 248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91, 5,231,185,</div> +<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> 140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,</div> +<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span> 17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,</div> +<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span> 175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,</div> +<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span> 50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,</div> +<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span> 202,148,118, 40,171,245, 23, 73, 8, 86,180,234,105, 55,213,139,</div> +<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span> 87, 9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,</div> +<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span> 233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,</div> +<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span> 116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53};</div> +<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span> </div> +<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span><span class="comment">// method declarations</span></div> +<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span><span class="keywordtype">int</span> OWFirst();</div> +<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span><span class="keywordtype">int</span> OWNext();</div> +<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span><span class="keywordtype">int</span> OWVerify();</div> +<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span><span class="keywordtype">void</span> OWTargetSetup(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> family_code);</div> +<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span><span class="keywordtype">void</span> OWFamilySkipSetup();</div> +<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span><span class="keywordtype">int</span> OWSearch();</div> +<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span><span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> docrc8(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> value);</div> +<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> </div> +<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span><span class="comment">// global search state</span></div> +<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span><span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> ROM_NO[8];</div> +<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span><span class="keywordtype">int</span> LastDiscrepancy;</div> +<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="keywordtype">int</span> LastFamilyDiscrepancy;</div> +<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span><span class="keywordtype">int</span> LastDeviceFlag;</div> +<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span><span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> crc8;</div> +<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span> </div> +<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="comment">//--------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span><span class="comment">// Find the &#39;first&#39; devices on the 1-Wire bus</span></div> +<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span><span class="comment">// Return TRUE : device found, ROM number in ROM_NO buffer</span></div> +<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span><span class="comment">// FALSE : no device present</span></div> +<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="comment">//</span></div> +<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="keywordtype">int</span> OWFirst()</div> +<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span>{</div> +<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span> <span class="comment">// reset the search state</span></div> +<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> LastDiscrepancy = 0;</div> +<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span> LastDeviceFlag = FALSE;</div> +<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span> LastFamilyDiscrepancy = 0;</div> +<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> </div> +<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span> <span class="keywordflow">return</span> OWSearch();</div> +<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span>}</div> +<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> </div> +<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span><span class="comment">//--------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span><span class="comment">// Find the &#39;next&#39; devices on the 1-Wire bus</span></div> +<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span><span class="comment">// Return TRUE : device found, ROM number in ROM_NO buffer</span></div> +<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span><span class="comment">// FALSE : device not found, end of search</span></div> +<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="comment">//</span></div> +<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="keywordtype">int</span> OWNext()</div> +<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span>{</div> +<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span> <span class="comment">// leave the search state alone</span></div> +<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span> <span class="keywordflow">return</span> OWSearch();</div> +<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span>}</div> +<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span> </div> +<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="comment">//--------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="comment">// Perform the 1-Wire Search Algorithm on the 1-Wire bus using the existing</span></div> +<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span><span class="comment">// search state.</span></div> +<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="comment">// Return TRUE : device found, ROM number in ROM_NO buffer</span></div> +<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="comment">// FALSE : device not found, end of search</span></div> +<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span><span class="comment">//</span></div> +<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span><span class="keywordtype">int</span> OWSearch()</div> +<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span>{</div> +<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span> <span class="keywordtype">int</span> id_bit_number;</div> +<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span> <span class="keywordtype">int</span> last_zero, rom_byte_number, search_result;</div> +<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span> <span class="keywordtype">int</span> id_bit, cmp_id_bit;</div> +<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> rom_byte_mask, search_direction;</div> +<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span> </div> +<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span> <span class="comment">// initialize for search</span></div> +<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span> id_bit_number = 1;</div> +<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span> last_zero = 0;</div> +<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span> rom_byte_number = 0;</div> +<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span> rom_byte_mask = 1;</div> +<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span> search_result = 0;</div> +<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span> crc8 = 0;</div> +<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span> </div> +<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span> <span class="comment">// if the last call was not the last one</span></div> +<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span> <span class="keywordflow">if</span> (!LastDeviceFlag)</div> +<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> {</div> +<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> <span class="comment">// 1-Wire reset</span></div> +<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span> <span class="keywordflow">if</span> (<a class="code hl_function" href="neorv32__onewire_8c.html#af8ca6be495176797b7da3857e2f794f9">neorv32_onewire_reset_blocking</a>())</div> +<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span> {</div> +<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span> <span class="comment">// reset the search</span></div> +<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span> LastDiscrepancy = 0;</div> +<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span> LastDeviceFlag = FALSE;</div> +<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span> LastFamilyDiscrepancy = 0;</div> +<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span> <span class="keywordflow">return</span> FALSE;</div> +<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span> }</div> +<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span> </div> +<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span> <span class="comment">// issue the search command </span></div> +<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span> <a class="code hl_function" href="neorv32__onewire_8c.html#ac78557c77482b59394677f42fda4fdf1">neorv32_onewire_write_byte_blocking</a>(0xF0); </div> +<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span> </div> +<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span> <span class="comment">// loop to do the search</span></div> +<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span> <span class="keywordflow">do</span></div> +<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span> {</div> +<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span> <span class="comment">// read a bit and its complement</span></div> +<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span> id_bit = <a class="code hl_function" href="neorv32__onewire_8c.html#ace8b7cf697b068b6b51676d84dec5960">neorv32_onewire_read_bit_blocking</a>();</div> +<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span> cmp_id_bit = <a class="code hl_function" href="neorv32__onewire_8c.html#ace8b7cf697b068b6b51676d84dec5960">neorv32_onewire_read_bit_blocking</a>();</div> +<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span> </div> +<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span> <span class="comment">// check for no devices on 1-wire</span></div> +<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"> 119</span> <span class="keywordflow">if</span> ((id_bit == 1) &amp;&amp; (cmp_id_bit == 1))</div> +<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"> 120</span> <span class="keywordflow">break</span>;</div> +<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span> <span class="keywordflow">else</span></div> +<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span> {</div> +<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span> <span class="comment">// all devices coupled have 0 or 1</span></div> +<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span> <span class="keywordflow">if</span> (id_bit != cmp_id_bit)</div> +<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span> search_direction = id_bit; <span class="comment">// bit write value for search</span></div> +<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span> <span class="keywordflow">else</span></div> +<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"> 127</span> {</div> +<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"> 128</span> <span class="comment">// if this discrepancy if before the Last Discrepancy</span></div> +<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span> <span class="comment">// on a previous next then pick the same as last time</span></div> +<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span> <span class="keywordflow">if</span> (id_bit_number &lt; LastDiscrepancy)</div> +<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span> search_direction = ((ROM_NO[rom_byte_number] &amp; rom_byte_mask) &gt; 0);</div> +<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span> <span class="keywordflow">else</span></div> +<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span> <span class="comment">// if equal to last pick 1, if not then pick 0</span></div> +<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"> 134</span> search_direction = (id_bit_number == LastDiscrepancy);</div> +<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"> 135</span> </div> +<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"> 136</span> <span class="comment">// if 0 was picked then record its position in LastZero</span></div> +<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"> 137</span> <span class="keywordflow">if</span> (search_direction == 0)</div> +<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"> 138</span> {</div> +<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"> 139</span> last_zero = id_bit_number;</div> +<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span> </div> +<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span> <span class="comment">// check for Last discrepancy in family</span></div> +<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span> <span class="keywordflow">if</span> (last_zero &lt; 9)</div> +<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"> 143</span> LastFamilyDiscrepancy = last_zero;</div> +<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span> }</div> +<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span> }</div> +<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span> </div> +<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span> <span class="comment">// set or clear the bit in the ROM byte rom_byte_number</span></div> +<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span> <span class="comment">// with mask rom_byte_mask</span></div> +<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span> <span class="keywordflow">if</span> (search_direction == 1)</div> +<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span> ROM_NO[rom_byte_number] |= rom_byte_mask;</div> +<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span> <span class="keywordflow">else</span></div> +<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span> ROM_NO[rom_byte_number] &amp;= ~rom_byte_mask;</div> +<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span> </div> +<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"> 154</span> <span class="comment">// serial number search direction write bit</span></div> +<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span> <a class="code hl_function" href="neorv32__onewire_8c.html#a6f7b6690a2437e0b574a8a9a23dc0eaa">neorv32_onewire_write_bit_blocking</a>(search_direction);</div> +<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span> </div> +<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span> <span class="comment">// increment the byte counter id_bit_number</span></div> +<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"> 158</span> <span class="comment">// and shift the mask rom_byte_mask</span></div> +<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"> 159</span> id_bit_number++;</div> +<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span> rom_byte_mask &lt;&lt;= 1;</div> +<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span> </div> +<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span> <span class="comment">// if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask</span></div> +<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"> 163</span> <span class="keywordflow">if</span> (rom_byte_mask == 0)</div> +<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span> {</div> +<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span> docrc8(ROM_NO[rom_byte_number]); <span class="comment">// accumulate the CRC</span></div> +<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"> 166</span> rom_byte_number++;</div> +<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span> rom_byte_mask = 1;</div> +<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span> }</div> +<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"> 169</span> }</div> +<div class="line"><a id="l00170" name="l00170"></a><span class="lineno"> 170</span> }</div> +<div class="line"><a id="l00171" name="l00171"></a><span class="lineno"> 171</span> <span class="keywordflow">while</span>(rom_byte_number &lt; 8); <span class="comment">// loop until through all ROM bytes 0-7</span></div> +<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"> 172</span> </div> +<div class="line"><a id="l00173" name="l00173"></a><span class="lineno"> 173</span> <span class="comment">// if the search was successful then</span></div> +<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"> 174</span> <span class="keywordflow">if</span> (!((id_bit_number &lt; 65) || (crc8 != 0)))</div> +<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span> {</div> +<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span> <span class="comment">// search successful so set LastDiscrepancy,LastDeviceFlag,search_result</span></div> +<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span> LastDiscrepancy = last_zero;</div> +<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span> </div> +<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span> <span class="comment">// check for last device</span></div> +<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span> <span class="keywordflow">if</span> (LastDiscrepancy == 0)</div> +<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span> LastDeviceFlag = TRUE;</div> +<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"> 182</span> </div> +<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"> 183</span> search_result = TRUE;</div> +<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"> 184</span> }</div> +<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"> 185</span> }</div> +<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"> 186</span> </div> +<div class="line"><a id="l00187" name="l00187"></a><span class="lineno"> 187</span> <span class="comment">// if no device found then reset counters so next &#39;search&#39; will be like a first</span></div> +<div class="line"><a id="l00188" name="l00188"></a><span class="lineno"> 188</span> <span class="keywordflow">if</span> (!search_result || !ROM_NO[0])</div> +<div class="line"><a id="l00189" name="l00189"></a><span class="lineno"> 189</span> {</div> +<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"> 190</span> LastDiscrepancy = 0;</div> +<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span> LastDeviceFlag = FALSE;</div> +<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"> 192</span> LastFamilyDiscrepancy = 0;</div> +<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span> search_result = FALSE;</div> +<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span> }</div> +<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span> </div> +<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span> <span class="keywordflow">return</span> search_result;</div> +<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span>}</div> +<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span> </div> +<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span><span class="comment">//--------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"> 200</span><span class="comment">// Verify the device with the ROM number in ROM_NO buffer is present.</span></div> +<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"> 201</span><span class="comment">// Return TRUE : device verified present</span></div> +<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span><span class="comment">// FALSE : device not present</span></div> +<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span><span class="comment">//</span></div> +<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"> 204</span><span class="keywordtype">int</span> OWVerify()</div> +<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"> 205</span>{</div> +<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"> 206</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> rom_backup[8];</div> +<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"> 207</span> <span class="keywordtype">int</span> i,rslt,ld_backup,ldf_backup,lfd_backup;</div> +<div class="line"><a id="l00208" name="l00208"></a><span class="lineno"> 208</span> </div> +<div class="line"><a id="l00209" name="l00209"></a><span class="lineno"> 209</span> <span class="comment">// keep a backup copy of the current state</span></div> +<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"> 210</span> <span class="keywordflow">for</span> (i = 0; i &lt; 8; i++)</div> +<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"> 211</span> rom_backup[i] = ROM_NO[i];</div> +<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"> 212</span> ld_backup = LastDiscrepancy;</div> +<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"> 213</span> ldf_backup = LastDeviceFlag;</div> +<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"> 214</span> lfd_backup = LastFamilyDiscrepancy;</div> +<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"> 215</span> </div> +<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"> 216</span> <span class="comment">// set search to find the same device</span></div> +<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"> 217</span> LastDiscrepancy = 64;</div> +<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span> LastDeviceFlag = FALSE;</div> +<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"> 219</span> </div> +<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"> 220</span> <span class="keywordflow">if</span> (OWSearch())</div> +<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"> 221</span> {</div> +<div class="line"><a id="l00222" name="l00222"></a><span class="lineno"> 222</span> <span class="comment">// check if same device found</span></div> +<div class="line"><a id="l00223" name="l00223"></a><span class="lineno"> 223</span> rslt = TRUE;</div> +<div class="line"><a id="l00224" name="l00224"></a><span class="lineno"> 224</span> <span class="keywordflow">for</span> (i = 0; i &lt; 8; i++)</div> +<div class="line"><a id="l00225" name="l00225"></a><span class="lineno"> 225</span> {</div> +<div class="line"><a id="l00226" name="l00226"></a><span class="lineno"> 226</span> <span class="keywordflow">if</span> (rom_backup[i] != ROM_NO[i])</div> +<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"> 227</span> {</div> +<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span> rslt = FALSE;</div> +<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span> <span class="keywordflow">break</span>;</div> +<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span> }</div> +<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span> }</div> +<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span> }</div> +<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span> <span class="keywordflow">else</span></div> +<div class="line"><a id="l00234" name="l00234"></a><span class="lineno"> 234</span> rslt = FALSE;</div> +<div class="line"><a id="l00235" name="l00235"></a><span class="lineno"> 235</span> </div> +<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"> 236</span> <span class="comment">// restore the search state </span></div> +<div class="line"><a id="l00237" name="l00237"></a><span class="lineno"> 237</span> <span class="keywordflow">for</span> (i = 0; i &lt; 8; i++)</div> +<div class="line"><a id="l00238" name="l00238"></a><span class="lineno"> 238</span> ROM_NO[i] = rom_backup[i];</div> +<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"> 239</span> LastDiscrepancy = ld_backup;</div> +<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"> 240</span> LastDeviceFlag = ldf_backup;</div> +<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"> 241</span> LastFamilyDiscrepancy = lfd_backup;</div> +<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"> 242</span> </div> +<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"> 243</span> <span class="comment">// return the result of the verify</span></div> +<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"> 244</span> <span class="keywordflow">return</span> rslt;</div> +<div class="line"><a id="l00245" name="l00245"></a><span class="lineno"> 245</span>}</div> +<div class="line"><a id="l00246" name="l00246"></a><span class="lineno"> 246</span> </div> +<div class="line"><a id="l00247" name="l00247"></a><span class="lineno"> 247</span><span class="comment">//--------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00248" name="l00248"></a><span class="lineno"> 248</span><span class="comment">// Setup the search to find the device type &#39;family_code&#39; on the next call</span></div> +<div class="line"><a id="l00249" name="l00249"></a><span class="lineno"> 249</span><span class="comment">// to OWNext() if it is present.</span></div> +<div class="line"><a id="l00250" name="l00250"></a><span class="lineno"> 250</span><span class="comment">//</span></div> +<div class="line"><a id="l00251" name="l00251"></a><span class="lineno"> 251</span><span class="keywordtype">void</span> OWTargetSetup(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> family_code)</div> +<div class="line"><a id="l00252" name="l00252"></a><span class="lineno"> 252</span>{</div> +<div class="line"><a id="l00253" name="l00253"></a><span class="lineno"> 253</span> <span class="keywordtype">int</span> i;</div> +<div class="line"><a id="l00254" name="l00254"></a><span class="lineno"> 254</span> </div> +<div class="line"><a id="l00255" name="l00255"></a><span class="lineno"> 255</span> <span class="comment">// set the search state to find SearchFamily type devices</span></div> +<div class="line"><a id="l00256" name="l00256"></a><span class="lineno"> 256</span> ROM_NO[0] = family_code;</div> +<div class="line"><a id="l00257" name="l00257"></a><span class="lineno"> 257</span> <span class="keywordflow">for</span> (i = 1; i &lt; 8; i++)</div> +<div class="line"><a id="l00258" name="l00258"></a><span class="lineno"> 258</span> ROM_NO[i] = 0;</div> +<div class="line"><a id="l00259" name="l00259"></a><span class="lineno"> 259</span> LastDiscrepancy = 64;</div> +<div class="line"><a id="l00260" name="l00260"></a><span class="lineno"> 260</span> LastFamilyDiscrepancy = 0;</div> +<div class="line"><a id="l00261" name="l00261"></a><span class="lineno"> 261</span> LastDeviceFlag = FALSE;</div> +<div class="line"><a id="l00262" name="l00262"></a><span class="lineno"> 262</span>}</div> +<div class="line"><a id="l00263" name="l00263"></a><span class="lineno"> 263</span> </div> +<div class="line"><a id="l00264" name="l00264"></a><span class="lineno"> 264</span><span class="comment">//--------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00265" name="l00265"></a><span class="lineno"> 265</span><span class="comment">// Setup the search to skip the current device type on the next call</span></div> +<div class="line"><a id="l00266" name="l00266"></a><span class="lineno"> 266</span><span class="comment">// to OWNext().</span></div> +<div class="line"><a id="l00267" name="l00267"></a><span class="lineno"> 267</span><span class="comment">//</span></div> +<div class="line"><a id="l00268" name="l00268"></a><span class="lineno"> 268</span><span class="keywordtype">void</span> OWFamilySkipSetup()</div> +<div class="line"><a id="l00269" name="l00269"></a><span class="lineno"> 269</span>{</div> +<div class="line"><a id="l00270" name="l00270"></a><span class="lineno"> 270</span> <span class="comment">// set the Last discrepancy to last family discrepancy</span></div> +<div class="line"><a id="l00271" name="l00271"></a><span class="lineno"> 271</span> LastDiscrepancy = LastFamilyDiscrepancy;</div> +<div class="line"><a id="l00272" name="l00272"></a><span class="lineno"> 272</span> LastFamilyDiscrepancy = 0;</div> +<div class="line"><a id="l00273" name="l00273"></a><span class="lineno"> 273</span> </div> +<div class="line"><a id="l00274" name="l00274"></a><span class="lineno"> 274</span> <span class="comment">// check for end of list</span></div> +<div class="line"><a id="l00275" name="l00275"></a><span class="lineno"> 275</span> <span class="keywordflow">if</span> (LastDiscrepancy == 0)</div> +<div class="line"><a id="l00276" name="l00276"></a><span class="lineno"> 276</span> LastDeviceFlag = TRUE;</div> +<div class="line"><a id="l00277" name="l00277"></a><span class="lineno"> 277</span>}</div> +<div class="line"><a id="l00278" name="l00278"></a><span class="lineno"> 278</span> </div> +<div class="line"><a id="l00279" name="l00279"></a><span class="lineno"> 279</span><span class="comment">//--------------------------------------------------------------------------</span></div> +<div class="line"><a id="l00280" name="l00280"></a><span class="lineno"> 280</span><span class="comment">// Calculate the CRC8 of the byte value provided with the current </span></div> +<div class="line"><a id="l00281" name="l00281"></a><span class="lineno"> 281</span><span class="comment">// global &#39;crc8&#39; value. </span></div> +<div class="line"><a id="l00282" name="l00282"></a><span class="lineno"> 282</span><span class="comment">// Returns current global crc8 value</span></div> +<div class="line"><a id="l00283" name="l00283"></a><span class="lineno"> 283</span><span class="comment">//</span></div> +<div class="line"><a id="l00284" name="l00284"></a><span class="lineno"> 284</span><span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> docrc8(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> value)</div> +<div class="line"><a id="l00285" name="l00285"></a><span class="lineno"> 285</span>{</div> +<div class="line"><a id="l00286" name="l00286"></a><span class="lineno"> 286</span> <span class="comment">// See Application Note 27</span></div> +<div class="line"><a id="l00287" name="l00287"></a><span class="lineno"> 287</span> </div> +<div class="line"><a id="l00288" name="l00288"></a><span class="lineno"> 288</span> <span class="comment">// TEST BUILD</span></div> +<div class="line"><a id="l00289" name="l00289"></a><span class="lineno"> 289</span> crc8 = dscrc_table[crc8 ^ value];</div> +<div class="line"><a id="l00290" name="l00290"></a><span class="lineno"> 290</span> <span class="keywordflow">return</span> crc8;</div> +<div class="line"><a id="l00291" name="l00291"></a><span class="lineno"> 291</span>}</div> +<div class="line"><a id="l00292" name="l00292"></a><span class="lineno"> 292</span> </div> +<div class="line"><a id="l00293" name="l00293"></a><span class="lineno"> 293</span><span class="preprocessor">#endif </span><span class="comment">// onewire_aux_h</span></div> +<div class="ttc" id="aneorv32_8h_html"><div class="ttname"><a href="neorv32_8h.html">neorv32.h</a></div><div class="ttdoc">Main NEORV32 core library / driver / HAL include file.</div></div> +<div class="ttc" id="aneorv32__onewire_8c_html_a6f7b6690a2437e0b574a8a9a23dc0eaa"><div class="ttname"><a href="neorv32__onewire_8c.html#a6f7b6690a2437e0b574a8a9a23dc0eaa">neorv32_onewire_write_bit_blocking</a></div><div class="ttdeci">void neorv32_onewire_write_bit_blocking(uint8_t bit)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:327</div></div> +<div class="ttc" id="aneorv32__onewire_8c_html_ac78557c77482b59394677f42fda4fdf1"><div class="ttname"><a href="neorv32__onewire_8c.html#ac78557c77482b59394677f42fda4fdf1">neorv32_onewire_write_byte_blocking</a></div><div class="ttdeci">void neorv32_onewire_write_byte_blocking(uint8_t byte)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:364</div></div> +<div class="ttc" id="aneorv32__onewire_8c_html_ace8b7cf697b068b6b51676d84dec5960"><div class="ttname"><a href="neorv32__onewire_8c.html#ace8b7cf697b068b6b51676d84dec5960">neorv32_onewire_read_bit_blocking</a></div><div class="ttdeci">uint8_t neorv32_onewire_read_bit_blocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:307</div></div> +<div class="ttc" id="aneorv32__onewire_8c_html_af8ca6be495176797b7da3857e2f794f9"><div class="ttname"><a href="neorv32__onewire_8c.html#af8ca6be495176797b7da3857e2f794f9">neorv32_onewire_reset_blocking</a></div><div class="ttdeci">int neorv32_onewire_reset_blocking(void)</div><div class="ttdef"><b>Definition</b> neorv32_onewire.c:287</div></div> +</div><!-- fragment --></div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" 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+<p>CPU/Processor test/verification program. +<a href="#details">More...</a></p> +<div class="textblock"><code>#include &lt;<a class="el" href="neorv32_8h_source.html">neorv32.h</a>&gt;</code><br /> +<code>#include &lt;string.h&gt;</code><br /> +</div><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a> +Macros</h2></td></tr> +<tr><td colspan="2"><div class="groupHeader">User configuration</div></td></tr> +<tr class="memitem:ad4455691936f92fdd6c37566fc58ba1f" id="r_ad4455691936f92fdd6c37566fc58ba1f"><td class="memItemLeft" align="right" valign="top"><a id="ad4455691936f92fdd6c37566fc58ba1f" name="ad4455691936f92fdd6c37566fc58ba1f"></a> +#define&#160;</td><td class="memItemRight" valign="bottom"><b>BAUD_RATE</b>&#160;&#160;&#160;(19200)</td></tr> +<tr class="separator:ad4455691936f92fdd6c37566fc58ba1f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr 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id="a49b20a83a39c69f841db1ca6653a5d16" name="a49b20a83a39c69f841db1ca6653a5d16"></a> +volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>hw_brk_mscratch_ok</b> = 0</td></tr> +<tr class="separator:a49b20a83a39c69f841db1ca6653a5d16"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a264dc6692665c4813b594da243f3a7e2" id="r_a264dc6692665c4813b594da243f3a7e2"><td class="memItemLeft" align="right" valign="top"><a id="a264dc6692665c4813b594da243f3a7e2" name="a264dc6692665c4813b594da243f3a7e2"></a> +volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>dma_src</b></td></tr> +<tr class="separator:a264dc6692665c4813b594da243f3a7e2"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:acd15f2c828419bbdaf6acf27404df5a9" id="r_acd15f2c828419bbdaf6acf27404df5a9"><td class="memItemLeft" align="right" valign="top"><a id="acd15f2c828419bbdaf6acf27404df5a9" name="acd15f2c828419bbdaf6acf27404df5a9"></a> +volatile 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+</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>CPU/Processor test/verification program. </p> +<dl class="section author"><dt>Author</dt><dd>Stephan Nolting </dd></dl> +</div><h2 class="groupheader">Macro Definition Documentation</h2> +<a id="acaa90e675a32d0f349ece12c9437e98f" name="acaa90e675a32d0f349ece12c9437e98f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acaa90e675a32d0f349ece12c9437e98f">&#9670;&#160;</a></span>PRINT_CRITICAL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define PRINT_CRITICAL</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em></em></span>...</td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">neorv32_uart0_printf(__VA_ARGS__)</div> +</div><!-- fragment --> +</div> +</div> +<a id="acbfde3de517fdc818a720383ec516d5b" name="acbfde3de517fdc818a720383ec516d5b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acbfde3de517fdc818a720383ec516d5b">&#9670;&#160;</a></span>PRINT_STANDARD</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define PRINT_STANDARD</td> + <td>(</td> + <td class="paramtype"></td> <td class="paramname"><span class="paramname"><em></em></span>...</td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<b>Value:</b><div class="fragment"><div class="line">neorv32_uart0_printf(__VA_ARGS__)</div> +</div><!-- fragment --> +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a id="a9a64ce0ee69c4c32cecc8b2b2746604c" name="a9a64ce0ee69c4c32cecc8b2b2746604c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9a64ce0ee69c4c32cecc8b2b2746604c">&#9670;&#160;</a></span>global_trap_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void global_trap_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Trap handler for ALL exceptions/interrupts. </p> + +</div> +</div> +<a id="a31d9e432f6a368e6222f5e0907eeb6f4" name="a31d9e432f6a368e6222f5e0907eeb6f4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a31d9e432f6a368e6222f5e0907eeb6f4">&#9670;&#160;</a></span>hw_breakpoint_handler()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void hw_breakpoint_handler </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Hardware-breakpoint trap handler </p> + +</div> +</div> +<a id="ae66f6b31b5ad750f1fe042a706a4e3d4" name="ae66f6b31b5ad750f1fe042a706a4e3d4"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae66f6b31b5ad750f1fe042a706a4e3d4">&#9670;&#160;</a></span>main()</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int main </td> + <td>(</td> + <td class="paramtype">void</td> <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>High-level CPU/processor test program.</p> +<dl class="section warning"><dt>Warning</dt><dd>This test is intended for simulation only. </dd> +<dd> +This test requires all optional extensions/modules to be enabled.</dd></dl> +<dl class="section return"><dt>Returns</dt><dd>0 if execution was successful </dd></dl> + +</div> +</div> +<a id="a349743a03307abb5130a3e89d903971b" name="a349743a03307abb5130a3e89d903971b"></a> +<h2 class="memtitle"><span class="permalink"><a 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b/sw/resize.js @@ -0,0 +1,147 @@ +/* + @licstart The following is the entire license notice for the JavaScript code in this file. + + The MIT License (MIT) + + Copyright (C) 1997-2020 by Dimitri van Heesch + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software + and associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file + */ + +function initResizable(treeview) { + let sidenav,navtree,content,header,footer,barWidth=6; + const RESIZE_COOKIE_NAME = ''+'width'; + + function resizeWidth() { + const sidenavWidth = $(sidenav).outerWidth(); + content.css({marginLeft:parseInt(sidenavWidth)+"px"}); + if (typeof page_layout!=='undefined' && page_layout==1) { + footer.css({marginLeft:parseInt(sidenavWidth)+"px"}); + } + Cookie.writeSetting(RESIZE_COOKIE_NAME,sidenavWidth-barWidth); + } + + function restoreWidth(navWidth) { + content.css({marginLeft:parseInt(navWidth)+barWidth+"px"}); + if (typeof page_layout!=='undefined' && page_layout==1) { + footer.css({marginLeft:parseInt(navWidth)+barWidth+"px"}); + } + sidenav.css({width:navWidth + "px"}); + } + + function resizeHeight(treeview) { + const headerHeight = header.outerHeight(); + const windowHeight = $(window).height(); + let contentHeight; + if (treeview) + { + const footerHeight = footer.outerHeight(); + let navtreeHeight,sideNavHeight; + if (typeof page_layout==='undefined' || page_layout==0) { /* DISABLE_INDEX=NO */ + contentHeight = windowHeight - headerHeight - footerHeight; + navtreeHeight = contentHeight; + sideNavHeight = contentHeight; + } else if (page_layout==1) { /* DISABLE_INDEX=YES */ + contentHeight = windowHeight - footerHeight; + navtreeHeight = windowHeight - headerHeight; + sideNavHeight = windowHeight; + } + navtree.css({height:navtreeHeight + "px"}); + sidenav.css({height:sideNavHeight + "px"}); + } + else + { + contentHeight = windowHeight - headerHeight; + } + content.css({height:contentHeight + "px"}); + if (location.hash.slice(1)) { + (document.getElementById(location.hash.slice(1))||document.body).scrollIntoView(); + } + } + + function collapseExpand() { + let newWidth; + if (sidenav.width()>0) { + newWidth=0; + } else { + const width = Cookie.readSetting(RESIZE_COOKIE_NAME,250); + newWidth = (width>250 && width<$(window).width()) ? width : 250; + } + restoreWidth(newWidth); + const sidenavWidth = $(sidenav).outerWidth(); + Cookie.writeSetting(RESIZE_COOKIE_NAME,sidenavWidth-barWidth); + } + + header = $("#top"); + content = $("#doc-content"); + footer = $("#nav-path"); + sidenav = $("#side-nav"); + if (!treeview) { +// title = $("#titlearea"); +// titleH = $(title).height(); +// let animating = false; +// content.on("scroll", function() { +// slideOpts = { duration: 200, +// step: function() { +// contentHeight = $(window).height() - header.outerHeight(); +// content.css({ height : contentHeight + "px" }); +// }, +// done: function() { animating=false; } +// }; +// if (content.scrollTop()>titleH && title.css('display')!='none' && !animating) { +// title.slideUp(slideOpts); +// animating=true; +// } else if (content.scrollTop()<=titleH && title.css('display')=='none' && !animating) { +// title.slideDown(slideOpts); +// animating=true; +// } +// }); + } else { + navtree = $("#nav-tree"); + $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } }); + $(sidenav).resizable({ minWidth: 0 }); + } + $(window).resize(function() { resizeHeight(treeview); }); + if (treeview) + { + const device = navigator.userAgent.toLowerCase(); + const touch_device = device.match(/(iphone|ipod|ipad|android)/); + if (touch_device) { /* wider split bar for touch only devices */ + $(sidenav).css({ paddingRight:'20px' }); + $('.ui-resizable-e').css({ width:'20px' }); + $('#nav-sync').css({ right:'34px' }); + barWidth=20; + } + const width = Cookie.readSetting(RESIZE_COOKIE_NAME,250); + if (width) { restoreWidth(width); } else { resizeWidth(); } + } + resizeHeight(treeview); + const url = location.href; + const i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + const _preventDefault = function(evt) { evt.preventDefault(); }; + if (treeview) + { + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); + $(".ui-resizable-handle").dblclick(collapseExpand); + // workaround for firefox + $("body").css({overflow: "hidden"}); + } + $(window).on('load',function() { resizeHeight(treeview); }); +} +/* @license-end */ diff --git a/sw/search/all_0.js b/sw/search/all_0.js new file mode 100644 index 000000000..7b0e67ce9 --- /dev/null +++ b/sw/search/all_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['1_20overview_0',['1. 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@@ +/*---------------- Search Box positioning */ + +#main-menu > li:last-child { + /* This <li> object is the parent of the search bar */ + display: flex; + justify-content: center; + align-items: center; + height: 36px; + margin-right: 1em; +} + +/*---------------- Search box styling */ + +.SRPage * { + font-weight: normal; + line-height: normal; +} + +dark-mode-toggle { + margin-left: 5px; + display: flex; + float: right; +} + +#MSearchBox { + display: inline-block; + white-space : nowrap; + background: var(--search-background-color); + border-radius: 0.65em; + box-shadow: var(--search-box-shadow); + z-index: 102; +} + +#MSearchBox .left { + display: inline-block; + vertical-align: middle; + height: 1.4em; +} + +#MSearchSelect { + display: inline-block; + vertical-align: middle; + width: 20px; + height: 19px; + background-image: var(--search-magnification-select-image); + margin: 0 0 0 0.3em; + padding: 0; +} + +#MSearchSelectExt { + display: inline-block; + vertical-align: middle; + width: 10px; + height: 19px; + background-image: var(--search-magnification-image); + margin: 0 0 0 0.5em; + padding: 0; +} + + +#MSearchField { + display: inline-block; + vertical-align: middle; + width: 7.5em; + height: 19px; + margin: 0 0.15em; + padding: 0; + line-height: 1em; + border:none; + color: var(--search-foreground-color); + outline: none; + font-family: var(--font-family-search); + -webkit-border-radius: 0px; + border-radius: 0px; + background: none; +} + +@media(hover: none) { + /* to avoid zooming on iOS */ + #MSearchField { + font-size: 16px; + } +} + +#MSearchBox .right { + display: inline-block; + vertical-align: middle; + width: 1.4em; + height: 1.4em; +} + +#MSearchClose { + display: none; + font-size: inherit; + background : none; + border: none; + margin: 0; + padding: 0; + outline: none; + +} + +#MSearchCloseImg { + padding: 0.3em; + margin: 0; +} + +.MSearchBoxActive #MSearchField { + color: var(--search-active-color); +} + + + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid var(--search-filter-border-color); + background-color: var(--search-filter-background-color); + z-index: 10001; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt var(--font-family-search); + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: var(--font-family-monospace); + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: var(--search-filter-foreground-color); + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: var(--search-filter-foreground-color); + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: var(--search-filter-highlight-text-color); + background-color: var(--search-filter-highlight-bg-color); + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + /*width: 60ex;*/ + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid var(--search-results-border-color); + background-color: var(--search-results-background-color); + z-index:10000; + width: 300px; + height: 400px; + overflow: auto; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +div.SRPage { + margin: 5px 2px; + background-color: var(--search-results-background-color); +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: var(--search-results-foreground-color); + font-family: var(--font-family-search); + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: var(--search-results-foreground-color); + font-family: var(--font-family-search); + font-size: 8pt; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +span.SRScope { + padding-left: 4px; + font-family: var(--font-family-search); +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; + font-family: var(--font-family-search); +} + +.SRResult { + display: none; +} + +div.searchresults { + margin-left: 10px; + margin-right: 10px; +} + +/*---------------- External search page results */ + +.pages b { + color: white; + padding: 5px 5px 3px 5px; + background-image: var(--nav-gradient-active-image-parent); + background-repeat: repeat-x; + text-shadow: 0 1px 1px #000000; +} + +.pages { + line-height: 17px; + margin-left: 4px; + text-decoration: none; +} + +.hl { + font-weight: bold; +} + +#searchresults { + margin-bottom: 20px; +} + +.searchpages { + margin-top: 10px; +} + diff --git a/sw/search/search.js b/sw/search/search.js new file mode 100644 index 000000000..666af01e5 --- /dev/null +++ b/sw/search/search.js @@ -0,0 +1,694 @@ +/* + @licstart The following is the entire license notice for the JavaScript code in this file. + + The MIT License (MIT) + + Copyright (C) 1997-2020 by Dimitri van Heesch + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software + and associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + @licend The above is the entire license notice for the JavaScript code in this file + */ +const SEARCH_COOKIE_NAME = ''+'search_grp'; + +const searchResults = new SearchResults(); + +/* A class handling everything associated with the search panel. + + Parameters: + name - The name of the global variable that will be + storing this instance. Is needed to be able to set timeouts. + resultPath - path to use for external files +*/ +function SearchBox(name, resultsPath, extension) { + if (!name || !resultsPath) { alert("Missing parameters to SearchBox."); } + if (!extension || extension == "") { extension = ".html"; } + + function getXPos(item) { + let x = 0; + if (item.offsetWidth) { + while (item && item!=document.body) { + x += item.offsetLeft; + item = item.offsetParent; + } + } + return x; + } + + function getYPos(item) { + let y = 0; + if (item.offsetWidth) { + while (item && item!=document.body) { + y += item.offsetTop; + item = item.offsetParent; + } + } + return y; + } + + // ---------- Instance variables + this.name = name; + this.resultsPath = resultsPath; + this.keyTimeout = 0; + this.keyTimeoutLength = 500; + this.closeSelectionTimeout = 300; + this.lastSearchValue = ""; + this.lastResultsPage = ""; + this.hideTimeout = 0; + this.searchIndex = 0; + this.searchActive = false; + this.extension = extension; + + // ----------- DOM Elements + + this.DOMSearchField = () => document.getElementById("MSearchField"); + this.DOMSearchSelect = () => document.getElementById("MSearchSelect"); + this.DOMSearchSelectWindow = () => document.getElementById("MSearchSelectWindow"); + this.DOMPopupSearchResults = () => document.getElementById("MSearchResults"); + this.DOMPopupSearchResultsWindow = () => document.getElementById("MSearchResultsWindow"); + this.DOMSearchClose = () => document.getElementById("MSearchClose"); + this.DOMSearchBox = () => document.getElementById("MSearchBox"); + + // ------------ Event Handlers + + // Called when focus is added or removed from the search field. + this.OnSearchFieldFocus = function(isActive) { + this.Activate(isActive); + } + + this.OnSearchSelectShow = function() { + const searchSelectWindow = this.DOMSearchSelectWindow(); + const searchField = this.DOMSearchSelect(); + + const left = getXPos(searchField); + const top = getYPos(searchField) + searchField.offsetHeight; + + // show search selection popup + searchSelectWindow.style.display='block'; + searchSelectWindow.style.left = left + 'px'; + searchSelectWindow.style.top = top + 'px'; + + // stop selection hide timer + if (this.hideTimeout) { + clearTimeout(this.hideTimeout); + this.hideTimeout=0; + } + return false; // to avoid "image drag" default event + } + + this.OnSearchSelectHide = function() { + this.hideTimeout = setTimeout(this.CloseSelectionWindow.bind(this), + this.closeSelectionTimeout); + } + + // Called when the content of the search field is changed. + this.OnSearchFieldChange = function(evt) { + if (this.keyTimeout) { // kill running timer + clearTimeout(this.keyTimeout); + this.keyTimeout = 0; + } + + const e = evt ? evt : window.event; // for IE + if (e.keyCode==40 || e.keyCode==13) { + if (e.shiftKey==1) { + this.OnSearchSelectShow(); + const win=this.DOMSearchSelectWindow(); + for (let i=0;i<win.childNodes.length;i++) { + const child = win.childNodes[i]; // get span within a + if (child.className=='SelectItem') { + child.focus(); + return; + } + } + return; + } else { + const elem = searchResults.NavNext(0); + if (elem) elem.focus(); + } + } else if (e.keyCode==27) { // Escape out of the search field + e.stopPropagation(); + this.DOMSearchField().blur(); + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.lastSearchValue = ''; + this.Activate(false); + return; + } + + // strip whitespaces + const searchValue = this.DOMSearchField().value.replace(/ +/g, ""); + + if (searchValue != this.lastSearchValue) { // search value has changed + if (searchValue != "") { // non-empty search + // set timer for search update + this.keyTimeout = setTimeout(this.Search.bind(this), this.keyTimeoutLength); + } else { // empty search field + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.lastSearchValue = ''; + } + } + } + + this.SelectItemCount = function() { + let count=0; + const win=this.DOMSearchSelectWindow(); + for (let i=0;i<win.childNodes.length;i++) { + const child = win.childNodes[i]; // get span within a + if (child.className=='SelectItem') { + count++; + } + } + return count; + } + + this.GetSelectionIdByName = function(name) { + let j=0; + const win=this.DOMSearchSelectWindow(); + for (let i=0;i<win.childNodes.length;i++) { + const child = win.childNodes[i]; + if (child.className=='SelectItem') { + if (child.childNodes[1].nodeValue==name) { + return j; + } + j++; + } + } + return 0; + } + + this.SelectItemSet = function(id) { + let j=0; + const win=this.DOMSearchSelectWindow(); + for (let i=0;i<win.childNodes.length;i++) { + const child = win.childNodes[i]; // get span within a + if (child.className=='SelectItem') { + const node = child.firstChild; + if (j==id) { + node.innerHTML='&#8226;'; + Cookie.writeSetting(SEARCH_COOKIE_NAME, child.childNodes[1].nodeValue, 0) + } else { + node.innerHTML='&#160;'; + } + j++; + } + } + } + + // Called when an search filter selection is made. + // set item with index id as the active item + this.OnSelectItem = function(id) { + this.searchIndex = id; + this.SelectItemSet(id); + const searchValue = this.DOMSearchField().value.replace(/ +/g, ""); + if (searchValue!="" && this.searchActive) { // something was found -> do a search + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) { + const e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) { // Down + this.searchIndex++; + this.OnSelectItem(this.searchIndex); + } else if (e.keyCode==38 && this.searchIndex>0) { // Up + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } else if (e.keyCode==13 || e.keyCode==27) { + e.stopPropagation(); + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() { + this.keyTimeout = 0; + + // strip leading whitespace + const searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + const code = searchValue.toLowerCase().charCodeAt(0); + let idxChar = searchValue.substr(0, 1).toLowerCase(); + if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) { // surrogate pair + idxChar = searchValue.substr(0, 2); + } + + let jsFile; + let idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar); + if (idx!=-1) { + const hexCode=idx.toString(16); + jsFile = this.resultsPath + indexSectionNames[this.searchIndex] + '_' + hexCode + '.js'; + } + + const loadJS = function(url, impl, loc) { + const scriptTag = document.createElement('script'); + scriptTag.src = url; + scriptTag.onload = impl; + scriptTag.onreadystatechange = impl; + loc.appendChild(scriptTag); + } + + const domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + const domSearchBox = this.DOMSearchBox(); + const domPopupSearchResults = this.DOMPopupSearchResults(); + const domSearchClose = this.DOMSearchClose(); + const resultsPath = this.resultsPath; + + const handleResults = function() { + document.getElementById("Loading").style.display="none"; + if (typeof searchData !== 'undefined') { + createResults(resultsPath); + document.getElementById("NoMatches").style.display="none"; + } + + if (idx!=-1) { + searchResults.Search(searchValue); + } else { // no file with search results => force empty search results + searchResults.Search('===='); + } + + if (domPopupSearchResultsWindow.style.display!='block') { + domSearchClose.style.display = 'inline-block'; + let left = getXPos(domSearchBox) + 150; + let top = getYPos(domSearchBox) + 20; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + const maxWidth = document.body.clientWidth; + const maxHeight = document.body.clientHeight; + let width = 300; + if (left<10) left=10; + if (width+left+8>maxWidth) width=maxWidth-left-8; + let height = 400; + if (height+top+8>maxHeight) height=maxHeight-top-8; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResultsWindow.style.height = height + 'px'; + } + } + + if (jsFile) { + loadJS(jsFile, handleResults, this.DOMPopupSearchResultsWindow()); + } else { + handleResults(); + } + + this.lastSearchValue = searchValue; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) { + this.DOMSearchBox().className = 'MSearchBoxActive'; + this.searchActive = true; + } else if (!isActive) { // directly remove the panel + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + this.DOMSearchField().value = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults() { + + function convertToId(search) { + let result = ''; + for (let i=0;i<search.length;i++) { + const c = search.charAt(i); + const cn = c.charCodeAt(0); + if (c.match(/[a-z0-9\u0080-\uFFFF]/)) { + result+=c; + } else if (cn<16) { + result+="_0"+cn.toString(16); + } else { + result+="_"+cn.toString(16); + } + } + return result; + } + + // The number of matches from the last run of <Search()>. + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) { + const parentElement = document.getElementById(id); + let element = parentElement.firstChild; + + while (element && element!=parentElement) { + if (element.nodeName.toLowerCase() == 'div' && element.className == 'SRChildren') { + return element; + } + + if (element.nodeName.toLowerCase() == 'div' && element.hasChildNodes()) { + element = element.firstChild; + } else if (element.nextSibling) { + element = element.nextSibling; + } else { + do { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) { + const element = this.FindChildElement(id); + if (element) { + if (element.style.display == 'block') { + element.style.display = 'none'; + } else { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) { + if (!search) { // get search word from URL + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + const resultRows = document.getElementsByTagName("div"); + let matches = 0; + + let i = 0; + while (i < resultRows.length) { + const row = resultRows.item(i); + if (row.className == "SRResult") { + let rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) { + row.style.display = 'block'; + matches++; + } else { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) { // no results + document.getElementById("NoMatches").style.display='block'; + } else { // at least one result + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) { + let focusItem; + for (;;) { + const focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') { + break; + } else if (!focusItem) { // last element + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) { + let focusItem; + for (;;) { + const focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') { + break; + } else if (!focusItem) { // last element + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) { + if (e.type == "keydown") { + this.repeatOn = false; + this.lastKey = e.keyCode; + } else if (e.type == "keypress") { + if (!this.repeatOn) { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } else if (e.type == "keyup") { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) { + const e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) { // Up + const newIndex = itemIndex-1; + let focusItem = this.NavPrev(newIndex); + if (focusItem) { + let child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') { // children visible + let n=0; + let tmpElem; + for (;;) { // search for last child + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) { + focusItem = tmpElem; + } else { // found it! + break; + } + n++; + } + } + } + if (focusItem) { + focusItem.focus(); + } else { // return focus to search field + document.getElementById("MSearchField").focus(); + } + } else if (this.lastKey==40) { // Down + const newIndex = itemIndex+1; + let focusItem; + const item = document.getElementById('Item'+itemIndex); + const elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') { // children visible + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } else if (this.lastKey==39) { // Right + const item = document.getElementById('Item'+itemIndex); + const elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } else if (this.lastKey==37) { // Left + const item = document.getElementById('Item'+itemIndex); + const elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } else if (this.lastKey==27) { // Escape + e.stopPropagation(); + searchBox.CloseResultsWindow(); + document.getElementById("MSearchField").focus(); + } else if (this.lastKey==13) { // Enter + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) { + const e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) { // Up + if (childIndex>0) { + const newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } else { // already at first child, jump to parent + document.getElementById('Item'+itemIndex).focus(); + } + } else if (this.lastKey==40) { // Down + const newIndex = childIndex+1; + let elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) { // last child, jump to parent next parent + elem = this.NavNext(itemIndex+1); + } + if (elem) { + elem.focus(); + } + } else if (this.lastKey==27) { // Escape + e.stopPropagation(); + searchBox.CloseResultsWindow(); + document.getElementById("MSearchField").focus(); + } else if (this.lastKey==13) { // Enter + return true; + } + return false; + } +} + +function createResults(resultsPath) { + + function setKeyActions(elem,action) { + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); + } + + function setClassAttr(elem,attr) { + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); + } + + const results = document.getElementById("SRResults"); + results.innerHTML = ''; + searchData.forEach((elem,index) => { + const id = elem[0]; + const srResult = document.createElement('div'); + srResult.setAttribute('id','SR_'+id); + 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+<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_cfs_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__cfs_8h_source.html">neorv32_cfs.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a48d3e81b207f4dcce0b0cc901583dc4d" id="r_a48d3e81b207f4dcce0b0cc901583dc4d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a48d3e81b207f4dcce0b0cc901583dc4d">REG</a> [64]</td></tr> +<tr class="separator:a48d3e81b207f4dcce0b0cc901583dc4d"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>CFS module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a48d3e81b207f4dcce0b0cc901583dc4d" name="a48d3e81b207f4dcce0b0cc901583dc4d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a48d3e81b207f4dcce0b0cc901583dc4d">&#9670;&#160;</a></span>REG</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_cfs_t::REG[64]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4*0..4*63: CFS register 0..63, user-defined </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__cfs_8h_source.html">neorv32_cfs.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__crc__t.html b/sw/structneorv32__crc__t.html new file mode 100644 index 000000000..e4e096278 --- /dev/null +++ b/sw/structneorv32__crc__t.html @@ -0,0 +1,181 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: neorv32_crc_t Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_crc_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__crc_8h_source.html">neorv32_crc.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:ad720502701f16e6e952bbcaee980017c" id="r_ad720502701f16e6e952bbcaee980017c"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad720502701f16e6e952bbcaee980017c">MODE</a></td></tr> +<tr class="separator:ad720502701f16e6e952bbcaee980017c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9bbcab843ddba4f9772d07478947a661" id="r_a9bbcab843ddba4f9772d07478947a661"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9bbcab843ddba4f9772d07478947a661">POLY</a></td></tr> +<tr class="separator:a9bbcab843ddba4f9772d07478947a661"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a47f286612848f597859aaef0d2d5da4d" id="r_a47f286612848f597859aaef0d2d5da4d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a47f286612848f597859aaef0d2d5da4d">DATA</a></td></tr> +<tr class="separator:a47f286612848f597859aaef0d2d5da4d"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abf2b419f2aefdb6f2a6b81a02cb8612d" id="r_abf2b419f2aefdb6f2a6b81a02cb8612d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abf2b419f2aefdb6f2a6b81a02cb8612d">SREG</a></td></tr> +<tr class="separator:abf2b419f2aefdb6f2a6b81a02cb8612d"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>CRC module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a47f286612848f597859aaef0d2d5da4d" name="a47f286612848f597859aaef0d2d5da4d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a47f286612848f597859aaef0d2d5da4d">&#9670;&#160;</a></span>DATA</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_crc_t::DATA</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 8: data input register </p> + +</div> +</div> +<a id="ad720502701f16e6e952bbcaee980017c" name="ad720502701f16e6e952bbcaee980017c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad720502701f16e6e952bbcaee980017c">&#9670;&#160;</a></span>MODE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_crc_t::MODE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: mode register (<a class="el" href="neorv32__crc_8h.html#a1ae84a58f475bafc2fc3f2c690fd6447">NEORV32_CRC_MODE_enum</a>) </p> + +</div> +</div> +<a id="a9bbcab843ddba4f9772d07478947a661" name="a9bbcab843ddba4f9772d07478947a661"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a9bbcab843ddba4f9772d07478947a661">&#9670;&#160;</a></span>POLY</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_crc_t::POLY</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: polynomial register </p> + +</div> +</div> +<a id="abf2b419f2aefdb6f2a6b81a02cb8612d" name="abf2b419f2aefdb6f2a6b81a02cb8612d"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abf2b419f2aefdb6f2a6b81a02cb8612d">&#9670;&#160;</a></span>SREG</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_crc_t::SREG</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 12: CRC shift register </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__crc_8h_source.html">neorv32_crc.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__dma__t.html b/sw/structneorv32__dma__t.html new file mode 100644 index 000000000..677eec8ca --- /dev/null +++ b/sw/structneorv32__dma__t.html @@ -0,0 +1,181 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: neorv32_dma_t Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div 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init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_dma_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__dma_8h_source.html">neorv32_dma.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a8480d6ad3ba5063cdf21dca286711569" id="r_a8480d6ad3ba5063cdf21dca286711569"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8480d6ad3ba5063cdf21dca286711569">CTRL</a></td></tr> +<tr class="separator:a8480d6ad3ba5063cdf21dca286711569"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a3b214d1a373c7f15b374e113d7110b42" id="r_a3b214d1a373c7f15b374e113d7110b42"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3b214d1a373c7f15b374e113d7110b42">SRC_BASE</a></td></tr> +<tr class="separator:a3b214d1a373c7f15b374e113d7110b42"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aee8a6cf3cbd9fe3c5995f046ffb9a1c0" id="r_aee8a6cf3cbd9fe3c5995f046ffb9a1c0"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aee8a6cf3cbd9fe3c5995f046ffb9a1c0">DST_BASE</a></td></tr> +<tr class="separator:aee8a6cf3cbd9fe3c5995f046ffb9a1c0"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a70c28642195765409d97b941e98f47ca" id="r_a70c28642195765409d97b941e98f47ca"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a70c28642195765409d97b941e98f47ca">TTYPE</a></td></tr> +<tr class="separator:a70c28642195765409d97b941e98f47ca"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>DMA module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a8480d6ad3ba5063cdf21dca286711569" name="a8480d6ad3ba5063cdf21dca286711569"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8480d6ad3ba5063cdf21dca286711569">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_dma_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control and status register (<a class="el" href="neorv32__dma_8h.html#a6716eddb145b80ad38799da3b87cb2a4">NEORV32_DMA_CTRL_enum</a>) </p> + +</div> +</div> +<a id="aee8a6cf3cbd9fe3c5995f046ffb9a1c0" name="aee8a6cf3cbd9fe3c5995f046ffb9a1c0"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aee8a6cf3cbd9fe3c5995f046ffb9a1c0">&#9670;&#160;</a></span>DST_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_dma_t::DST_BASE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 8: destination base address register </p> + +</div> +</div> +<a id="a3b214d1a373c7f15b374e113d7110b42" name="a3b214d1a373c7f15b374e113d7110b42"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3b214d1a373c7f15b374e113d7110b42">&#9670;&#160;</a></span>SRC_BASE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_dma_t::SRC_BASE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: source base address register </p> + +</div> +</div> +<a id="a70c28642195765409d97b941e98f47ca" name="a70c28642195765409d97b941e98f47ca"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a70c28642195765409d97b941e98f47ca">&#9670;&#160;</a></span>TTYPE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_dma_t::TTYPE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 12: transfer type configuration register &amp; manual trigger (<a class="el" href="neorv32__dma_8h.html#a33187c5a074d62b46d2262e352edb8d9">NEORV32_DMA_TTYPE_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__dma_8h_source.html">neorv32_dma.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__gpio__t.html b/sw/structneorv32__gpio__t.html new file mode 100644 index 000000000..8a820825e --- /dev/null +++ b/sw/structneorv32__gpio__t.html @@ -0,0 +1,147 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: neorv32_gpio_t Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" 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magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_gpio_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__gpio_8h_source.html">neorv32_gpio.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a208ee622d43fee3574072f19a98c8808" id="r_a208ee622d43fee3574072f19a98c8808"><td class="memItemLeft" align="right" valign="top">const uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a208ee622d43fee3574072f19a98c8808">INPUT</a> [2]</td></tr> +<tr class="separator:a208ee622d43fee3574072f19a98c8808"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:abaf7de4f79adfc3debcde93fa4a921bb" id="r_abaf7de4f79adfc3debcde93fa4a921bb"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#abaf7de4f79adfc3debcde93fa4a921bb">OUTPUT</a> [2]</td></tr> +<tr class="separator:abaf7de4f79adfc3debcde93fa4a921bb"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>GPIO module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a208ee622d43fee3574072f19a98c8808" name="a208ee622d43fee3574072f19a98c8808"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a208ee622d43fee3574072f19a98c8808">&#9670;&#160;</a></span>INPUT</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const uint32_t neorv32_gpio_t::INPUT[2]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: parallel input port, read-only </p> + +</div> +</div> +<a id="abaf7de4f79adfc3debcde93fa4a921bb" name="abaf7de4f79adfc3debcde93fa4a921bb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#abaf7de4f79adfc3debcde93fa4a921bb">&#9670;&#160;</a></span>OUTPUT</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_gpio_t::OUTPUT[2]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 8: parallel output port </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__gpio_8h_source.html">neorv32_gpio.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__gptmr__t.html b/sw/structneorv32__gptmr__t.html new file mode 100644 index 000000000..acb8f5396 --- /dev/null +++ b/sw/structneorv32__gptmr__t.html @@ -0,0 +1,164 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" 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src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license 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searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_gptmr_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__gptmr_8h_source.html">neorv32_gptmr.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a3c477ccb24ed12122d9d90244431c7e9" id="r_a3c477ccb24ed12122d9d90244431c7e9"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3c477ccb24ed12122d9d90244431c7e9">CTRL</a></td></tr> +<tr class="separator:a3c477ccb24ed12122d9d90244431c7e9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a666ebcbea13dafcf1987629f3e0092ee" id="r_a666ebcbea13dafcf1987629f3e0092ee"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a666ebcbea13dafcf1987629f3e0092ee">THRES</a></td></tr> +<tr class="separator:a666ebcbea13dafcf1987629f3e0092ee"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1abc5bae1dffc64006e965d4570da479" id="r_a1abc5bae1dffc64006e965d4570da479"><td class="memItemLeft" align="right" valign="top">const uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1abc5bae1dffc64006e965d4570da479">COUNT</a></td></tr> +<tr class="separator:a1abc5bae1dffc64006e965d4570da479"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>GPTMR module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a1abc5bae1dffc64006e965d4570da479" name="a1abc5bae1dffc64006e965d4570da479"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1abc5bae1dffc64006e965d4570da479">&#9670;&#160;</a></span>COUNT</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const uint32_t neorv32_gptmr_t::COUNT</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 8: counter register, read-only </p> + +</div> +</div> +<a id="a3c477ccb24ed12122d9d90244431c7e9" name="a3c477ccb24ed12122d9d90244431c7e9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3c477ccb24ed12122d9d90244431c7e9">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_gptmr_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__gptmr_8h.html#a135b0750d4afed16e5867134e3843988">NEORV32_GPTMR_CTRL_enum</a>) </p> + +</div> +</div> +<a id="a666ebcbea13dafcf1987629f3e0092ee" name="a666ebcbea13dafcf1987629f3e0092ee"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a666ebcbea13dafcf1987629f3e0092ee">&#9670;&#160;</a></span>THRES</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_gptmr_t::THRES</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: threshold register </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__gptmr_8h_source.html">neorv32_gptmr.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__mtime__t.html b/sw/structneorv32__mtime__t.html new file mode 100644 index 000000000..477f5c196 --- /dev/null +++ b/sw/structneorv32__mtime__t.html @@ -0,0 +1,181 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta 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<tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_mtime_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__mtime_8h_source.html">neorv32_mtime.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:acccaa3dd87a57ebd5f7ae504771e904e" id="r_acccaa3dd87a57ebd5f7ae504771e904e"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acccaa3dd87a57ebd5f7ae504771e904e">TIME_LO</a></td></tr> +<tr class="separator:acccaa3dd87a57ebd5f7ae504771e904e"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a1ffe0be2c45f5d7aa2686abf40cd1693" id="r_a1ffe0be2c45f5d7aa2686abf40cd1693"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1ffe0be2c45f5d7aa2686abf40cd1693">TIME_HI</a></td></tr> +<tr class="separator:a1ffe0be2c45f5d7aa2686abf40cd1693"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ab5fa56ca5c2f9d547f58d169d6da96e5" id="r_ab5fa56ca5c2f9d547f58d169d6da96e5"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab5fa56ca5c2f9d547f58d169d6da96e5">TIMECMP_LO</a></td></tr> +<tr class="separator:ab5fa56ca5c2f9d547f58d169d6da96e5"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:af05df268c8f699401cf752e4249ba422" id="r_af05df268c8f699401cf752e4249ba422"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af05df268c8f699401cf752e4249ba422">TIMECMP_HI</a></td></tr> +<tr class="separator:af05df268c8f699401cf752e4249ba422"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>MTIME module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a1ffe0be2c45f5d7aa2686abf40cd1693" name="a1ffe0be2c45f5d7aa2686abf40cd1693"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a1ffe0be2c45f5d7aa2686abf40cd1693">&#9670;&#160;</a></span>TIME_HI</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_mtime_t::TIME_HI</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: time register high word </p> + +</div> +</div> +<a id="acccaa3dd87a57ebd5f7ae504771e904e" name="acccaa3dd87a57ebd5f7ae504771e904e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#acccaa3dd87a57ebd5f7ae504771e904e">&#9670;&#160;</a></span>TIME_LO</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_mtime_t::TIME_LO</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: time register low word </p> + +</div> +</div> +<a id="af05df268c8f699401cf752e4249ba422" name="af05df268c8f699401cf752e4249ba422"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af05df268c8f699401cf752e4249ba422">&#9670;&#160;</a></span>TIMECMP_HI</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_mtime_t::TIMECMP_HI</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 12: compare register high word </p> + +</div> +</div> +<a id="ab5fa56ca5c2f9d547f58d169d6da96e5" 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magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_neoled_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__neoled_8h_source.html">neorv32_neoled.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:adfe7618c002ff88dd22e65fcedfd6139" id="r_adfe7618c002ff88dd22e65fcedfd6139"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adfe7618c002ff88dd22e65fcedfd6139">CTRL</a></td></tr> +<tr class="separator:adfe7618c002ff88dd22e65fcedfd6139"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a995fb1d63a9dfb3f20d715932781c1de" id="r_a995fb1d63a9dfb3f20d715932781c1de"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a995fb1d63a9dfb3f20d715932781c1de">DATA</a></td></tr> +<tr class="separator:a995fb1d63a9dfb3f20d715932781c1de"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>NEOLED module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="adfe7618c002ff88dd22e65fcedfd6139" name="adfe7618c002ff88dd22e65fcedfd6139"></a> +<h2 class="memtitle"><span class="permalink"><a href="#adfe7618c002ff88dd22e65fcedfd6139">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_neoled_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register </p> + +</div> +</div> +<a id="a995fb1d63a9dfb3f20d715932781c1de" name="a995fb1d63a9dfb3f20d715932781c1de"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a995fb1d63a9dfb3f20d715932781c1de">&#9670;&#160;</a></span>DATA</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_neoled_t::DATA</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: data register (<a class="el" href="neorv32__neoled_8h.html#ab99c7fed050816eae0fa0315562e0412">NEORV32_NEOLED_CTRL_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__neoled_8h_source.html">neorv32_neoled.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__onewire__t.html b/sw/structneorv32__onewire__t.html new file mode 100644 index 000000000..b8b1fd76f --- /dev/null +++ b/sw/structneorv32__onewire__t.html @@ -0,0 +1,147 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: neorv32_onewire_t Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script 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searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_onewire_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__onewire_8h_source.html">neorv32_onewire.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a310df3bab43e4438417b2ff948f4712a" id="r_a310df3bab43e4438417b2ff948f4712a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a310df3bab43e4438417b2ff948f4712a">CTRL</a></td></tr> +<tr class="separator:a310df3bab43e4438417b2ff948f4712a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a2c04aa736b901940ed65b96202c8af7a" id="r_a2c04aa736b901940ed65b96202c8af7a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2c04aa736b901940ed65b96202c8af7a">DATA</a></td></tr> +<tr class="separator:a2c04aa736b901940ed65b96202c8af7a"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>ONEWIRE module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a310df3bab43e4438417b2ff948f4712a" name="a310df3bab43e4438417b2ff948f4712a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a310df3bab43e4438417b2ff948f4712a">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_onewire_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__onewire_8h.html#ade1a01f533843880868ec7496d116831">NEORV32_ONEWIRE_CTRL_enum</a>) </p> + +</div> +</div> +<a id="a2c04aa736b901940ed65b96202c8af7a" name="a2c04aa736b901940ed65b96202c8af7a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a2c04aa736b901940ed65b96202c8af7a">&#9670;&#160;</a></span>DATA</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_onewire_t::DATA</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: transmission data register (<a class="el" href="neorv32__onewire_8h.html#ae770490afa8662fb8577065531d51368">NEORV32_ONEWIRE_DATA_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__onewire_8h_source.html">neorv32_onewire.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__pwm__t.html b/sw/structneorv32__pwm__t.html new file mode 100644 index 000000000..a5c2cdcd0 --- /dev/null +++ b/sw/structneorv32__pwm__t.html @@ -0,0 +1,130 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html 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valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5df0cf6c7c250365db3ada8db7cc19e9">CHANNEL_CFG</a> [16]</td></tr> +<tr class="separator:a5df0cf6c7c250365db3ada8db7cc19e9"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>PWM module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a5df0cf6c7c250365db3ada8db7cc19e9" name="a5df0cf6c7c250365db3ada8db7cc19e9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5df0cf6c7c250365db3ada8db7cc19e9">&#9670;&#160;</a></span>CHANNEL_CFG</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_pwm_t::CHANNEL_CFG[16]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0..64: channel configuration 0..15 (<a class="el" href="neorv32__pwm_8h.html#acbcb6d5d80029fb404efcd7123ff5175">CHANNEL_CFG_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__pwm_8h_source.html">neorv32_pwm.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__sdi__t.html b/sw/structneorv32__sdi__t.html new file mode 100644 index 000000000..4ca0d7ea5 --- /dev/null +++ b/sw/structneorv32__sdi__t.html @@ -0,0 +1,147 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> 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valign="bottom"><a class="el" href="#af494f25cbcd8478cf384eb868e447303">CTRL</a></td></tr> +<tr class="separator:af494f25cbcd8478cf384eb868e447303"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a3ea6903c0924d0a1b633b6a2b0ae44f1" id="r_a3ea6903c0924d0a1b633b6a2b0ae44f1"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3ea6903c0924d0a1b633b6a2b0ae44f1">DATA</a></td></tr> +<tr class="separator:a3ea6903c0924d0a1b633b6a2b0ae44f1"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>SDI module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="af494f25cbcd8478cf384eb868e447303" name="af494f25cbcd8478cf384eb868e447303"></a> +<h2 class="memtitle"><span class="permalink"><a href="#af494f25cbcd8478cf384eb868e447303">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_sdi_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__sdi_8h.html#abad9f422cbdff1b73100e98f7ab20ec6">NEORV32_SDI_CTRL_enum</a>) </p> + +</div> +</div> +<a id="a3ea6903c0924d0a1b633b6a2b0ae44f1" name="a3ea6903c0924d0a1b633b6a2b0ae44f1"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3ea6903c0924d0a1b633b6a2b0ae44f1">&#9670;&#160;</a></span>DATA</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_sdi_t::DATA</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: data register </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__sdi_8h_source.html">neorv32_sdi.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__slink__t.html b/sw/structneorv32__slink__t.html new file mode 100644 index 000000000..5715a272a --- /dev/null +++ b/sw/structneorv32__slink__t.html @@ -0,0 +1,181 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" 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id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_slink_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__slink_8h_source.html">neorv32_slink.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a39ece6aeeea6982002e164902a1e784f" id="r_a39ece6aeeea6982002e164902a1e784f"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a39ece6aeeea6982002e164902a1e784f">CTRL</a></td></tr> +<tr class="separator:a39ece6aeeea6982002e164902a1e784f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0b2417a1a587da45909ce2a948f90e22" id="r_a0b2417a1a587da45909ce2a948f90e22"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0b2417a1a587da45909ce2a948f90e22">ROUTE</a></td></tr> +<tr class="separator:a0b2417a1a587da45909ce2a948f90e22"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8af7d4ea9787cf94c599c82133c6aa74" id="r_a8af7d4ea9787cf94c599c82133c6aa74"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8af7d4ea9787cf94c599c82133c6aa74">DATA</a></td></tr> +<tr class="separator:a8af7d4ea9787cf94c599c82133c6aa74"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ada8f10141d2161b83a5a367722ed6a77" id="r_ada8f10141d2161b83a5a367722ed6a77"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ada8f10141d2161b83a5a367722ed6a77">DATA_LAST</a></td></tr> +<tr class="separator:ada8f10141d2161b83a5a367722ed6a77"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>SLINK module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a39ece6aeeea6982002e164902a1e784f" name="a39ece6aeeea6982002e164902a1e784f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a39ece6aeeea6982002e164902a1e784f">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__slink_8h.html#ac0385a56c38315d492b3414d98235ef1">NEORV32_SLINK_CTRL_enum</a>) </p> + +</div> +</div> +<a id="a8af7d4ea9787cf94c599c82133c6aa74" name="a8af7d4ea9787cf94c599c82133c6aa74"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8af7d4ea9787cf94c599c82133c6aa74">&#9670;&#160;</a></span>DATA</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_t::DATA</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 8: RX/TX data register </p> + +</div> +</div> +<a id="ada8f10141d2161b83a5a367722ed6a77" name="ada8f10141d2161b83a5a367722ed6a77"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ada8f10141d2161b83a5a367722ed6a77">&#9670;&#160;</a></span>DATA_LAST</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_t::DATA_LAST</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 12: RX/TX data register (+ TX end-of-stream) </p> + +</div> +</div> +<a id="a0b2417a1a587da45909ce2a948f90e22" name="a0b2417a1a587da45909ce2a948f90e22"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0b2417a1a587da45909ce2a948f90e22">&#9670;&#160;</a></span>ROUTE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_slink_t::ROUTE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: routing information (<a class="el" href="neorv32__slink_8h.html#ac3e5e02fd89a357135adca6d28cd0e45">NEORV32_SLINK_ROUTE_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__slink_8h_source.html">neorv32_slink.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img 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type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_spi_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__spi_8h_source.html">neorv32_spi.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a34fa748f0e3ceb75822c0a5553bd0420" id="r_a34fa748f0e3ceb75822c0a5553bd0420"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a34fa748f0e3ceb75822c0a5553bd0420">CTRL</a></td></tr> +<tr class="separator:a34fa748f0e3ceb75822c0a5553bd0420"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a3901bad351213e34820197a33d589f1e" id="r_a3901bad351213e34820197a33d589f1e"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3901bad351213e34820197a33d589f1e">DATA</a></td></tr> +<tr class="separator:a3901bad351213e34820197a33d589f1e"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>SPI module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a34fa748f0e3ceb75822c0a5553bd0420" name="a34fa748f0e3ceb75822c0a5553bd0420"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a34fa748f0e3ceb75822c0a5553bd0420">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_spi_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__spi_8h.html#ae269b2f5b2afd46ae16801762ade2c3b">NEORV32_SPI_CTRL_enum</a>) </p> + +</div> +</div> +<a id="a3901bad351213e34820197a33d589f1e" name="a3901bad351213e34820197a33d589f1e"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3901bad351213e34820197a33d589f1e">&#9670;&#160;</a></span>DATA</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_spi_t::DATA</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: data register (<a class="el" href="neorv32__spi_8h.html#aab478c23898c0b06cee53a1cbda38bf8">NEORV32_SPI_DATA_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__spi_8h_source.html">neorv32_spi.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__sysinfo__t.html b/sw/structneorv32__sysinfo__t.html new file mode 100644 index 000000000..b36af5b29 --- /dev/null +++ b/sw/structneorv32__sysinfo__t.html @@ -0,0 +1,181 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework Documentation: neorv32_sysinfo_t Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="clipboard.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="cookie.js"></script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* 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+</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_sysinfo_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__sysinfo_8h_source.html">neorv32_sysinfo.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a3f8ce96050fc0a680afa9b7fdf7cb35c" id="r_a3f8ce96050fc0a680afa9b7fdf7cb35c"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3f8ce96050fc0a680afa9b7fdf7cb35c">CLK</a></td></tr> +<tr class="separator:a3f8ce96050fc0a680afa9b7fdf7cb35c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a51eee92b1824c1b19eb0a83a0a9c7d4c" id="r_a51eee92b1824c1b19eb0a83a0a9c7d4c"><td class="memItemLeft" align="right" valign="top">const uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a51eee92b1824c1b19eb0a83a0a9c7d4c">MEM</a> [4]</td></tr> +<tr class="separator:a51eee92b1824c1b19eb0a83a0a9c7d4c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac43abe3b416da3a2895d1d06537a14c3" id="r_ac43abe3b416da3a2895d1d06537a14c3"><td class="memItemLeft" align="right" valign="top">const uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac43abe3b416da3a2895d1d06537a14c3">SOC</a></td></tr> +<tr class="separator:ac43abe3b416da3a2895d1d06537a14c3"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ada99a36ccda38b254d5b6a84883101f6" id="r_ada99a36ccda38b254d5b6a84883101f6"><td class="memItemLeft" align="right" valign="top">const uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ada99a36ccda38b254d5b6a84883101f6">CACHE</a></td></tr> +<tr class="separator:ada99a36ccda38b254d5b6a84883101f6"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>SYSINFO module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="ada99a36ccda38b254d5b6a84883101f6" name="ada99a36ccda38b254d5b6a84883101f6"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ada99a36ccda38b254d5b6a84883101f6">&#9670;&#160;</a></span>CACHE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const uint32_t neorv32_sysinfo_t::CACHE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 12: Cache configuration (<a class="el" href="neorv32__sysinfo_8h.html#a50ee5bda9789b5cffae281db5d10a1ea">NEORV32_SYSINFO_CACHE_enum</a>) </p> + +</div> +</div> +<a id="a3f8ce96050fc0a680afa9b7fdf7cb35c" name="a3f8ce96050fc0a680afa9b7fdf7cb35c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a3f8ce96050fc0a680afa9b7fdf7cb35c">&#9670;&#160;</a></span>CLK</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_sysinfo_t::CLK</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: Clock speed in Hz </p> + +</div> +</div> +<a id="a51eee92b1824c1b19eb0a83a0a9c7d4c" name="a51eee92b1824c1b19eb0a83a0a9c7d4c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a51eee92b1824c1b19eb0a83a0a9c7d4c">&#9670;&#160;</a></span>MEM</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const uint8_t neorv32_sysinfo_t::MEM[4]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: Internal memory sizes (<a class="el" href="neorv32__sysinfo_8h.html#aebaa5f3f231003a05c899cc1491b8c5f">NEORV32_SYSINFO_MEM_enum</a>) </p> + +</div> +</div> +<a id="ac43abe3b416da3a2895d1d06537a14c3" name="ac43abe3b416da3a2895d1d06537a14c3"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ac43abe3b416da3a2895d1d06537a14c3">&#9670;&#160;</a></span>SOC</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const uint32_t neorv32_sysinfo_t::SOC</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 8: SoC features (<a class="el" href="neorv32__sysinfo_8h.html#ae41ebd5785b09640a00df194b1a0fa08">NEORV32_SYSINFO_SOC_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__sysinfo_8h_source.html">neorv32_sysinfo.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__trng__t.html b/sw/structneorv32__trng__t.html new file mode 100644 index 000000000..db51a927a --- /dev/null +++ b/sw/structneorv32__trng__t.html @@ -0,0 +1,130 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 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class="memitem:ae2ff37ce30fb85ef59d9012534bc7e67" id="r_ae2ff37ce30fb85ef59d9012534bc7e67"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae2ff37ce30fb85ef59d9012534bc7e67">CTRL</a></td></tr> +<tr class="separator:ae2ff37ce30fb85ef59d9012534bc7e67"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>TRNG module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="ae2ff37ce30fb85ef59d9012534bc7e67" name="ae2ff37ce30fb85ef59d9012534bc7e67"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae2ff37ce30fb85ef59d9012534bc7e67">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_trng_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__trng_8h.html#a1440e1355bf5bff17760992adc156b1a">NEORV32_TRNG_CTRL_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__trng_8h_source.html">neorv32_trng.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__twi__t.html b/sw/structneorv32__twi__t.html new file mode 100644 index 000000000..d77d7cdc8 --- /dev/null +++ b/sw/structneorv32__twi__t.html @@ -0,0 +1,147 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html 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valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a148a1c681a2632881b25ee41652b5304">CTRL</a></td></tr> +<tr class="separator:a148a1c681a2632881b25ee41652b5304"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae311e0827bdb178c6dd8c4535b80d5cb" id="r_ae311e0827bdb178c6dd8c4535b80d5cb"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae311e0827bdb178c6dd8c4535b80d5cb">DCMD</a></td></tr> +<tr class="separator:ae311e0827bdb178c6dd8c4535b80d5cb"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>TWI module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a148a1c681a2632881b25ee41652b5304" name="a148a1c681a2632881b25ee41652b5304"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a148a1c681a2632881b25ee41652b5304">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_twi_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__twi_8h.html#a71ef393d3b34d2dd0698590994b7dafa">NEORV32_TWI_CTRL_enum</a>) </p> + +</div> +</div> +<a id="ae311e0827bdb178c6dd8c4535b80d5cb" name="ae311e0827bdb178c6dd8c4535b80d5cb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ae311e0827bdb178c6dd8c4535b80d5cb">&#9670;&#160;</a></span>DCMD</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_twi_t::DCMD</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: data/cmd register (<a class="el" href="neorv32__twi_8h.html#a3421852c63baca60fe58c990b1c653d8">NEORV32_TWI_DCMD_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__twi_8h_source.html">neorv32_twi.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__uart__t.html b/sw/structneorv32__uart__t.html new file mode 100644 index 000000000..3bb27b977 --- /dev/null +++ b/sw/structneorv32__uart__t.html @@ -0,0 +1,147 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta 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class="separator:a0a6227aeea38335d2b9a9da46b35451b"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a38eec82aae9ed522a0d2afb9a9560036" id="r_a38eec82aae9ed522a0d2afb9a9560036"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a38eec82aae9ed522a0d2afb9a9560036">DATA</a></td></tr> +<tr class="separator:a38eec82aae9ed522a0d2afb9a9560036"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>UART module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a0a6227aeea38335d2b9a9da46b35451b" name="a0a6227aeea38335d2b9a9da46b35451b"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0a6227aeea38335d2b9a9da46b35451b">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_uart_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__uart_8h.html#ad9f75f453beca1619344bb4213352afc">NEORV32_UART_CTRL_enum</a>) </p> + +</div> +</div> +<a id="a38eec82aae9ed522a0d2afb9a9560036" name="a38eec82aae9ed522a0d2afb9a9560036"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a38eec82aae9ed522a0d2afb9a9560036">&#9670;&#160;</a></span>DATA</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_uart_t::DATA</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: data register (<a class="el" href="neorv32__uart_8h.html#adcf35350a9ea18a59c32c35f528643f2">NEORV32_UART_DATA_enum</a>) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__uart_8h_source.html">neorv32_uart.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__wdt__t.html b/sw/structneorv32__wdt__t.html new file mode 100644 index 000000000..dc2f6634e --- /dev/null +++ b/sw/structneorv32__wdt__t.html @@ -0,0 +1,147 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=11"/> +<meta name="generator" content="Doxygen 1.12.0"/> +<meta name="viewport" content="width=device-width, initial-scale=1"/> +<title>NEORV32 Software Framework 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+</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_wdt_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__wdt_8h_source.html">neorv32_wdt.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a6ae41e28d08b0f06118c499f52b56f41" id="r_a6ae41e28d08b0f06118c499f52b56f41"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6ae41e28d08b0f06118c499f52b56f41">CTRL</a></td></tr> +<tr class="separator:a6ae41e28d08b0f06118c499f52b56f41"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a0a273e8ca2bd92547bf7727ec65a9449" id="r_a0a273e8ca2bd92547bf7727ec65a9449"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0a273e8ca2bd92547bf7727ec65a9449">RESET</a></td></tr> +<tr class="separator:a0a273e8ca2bd92547bf7727ec65a9449"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>WDT module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a6ae41e28d08b0f06118c499f52b56f41" name="a6ae41e28d08b0f06118c499f52b56f41"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a6ae41e28d08b0f06118c499f52b56f41">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_wdt_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__wdt_8h.html#a0a4cb24fd818277c5bb9b10ff519f23e">NEORV32_WDT_CTRL_enum</a>) </p> + +</div> +</div> +<a id="a0a273e8ca2bd92547bf7727ec65a9449" name="a0a273e8ca2bd92547bf7727ec65a9449"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a0a273e8ca2bd92547bf7727ec65a9449">&#9670;&#160;</a></span>RESET</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_wdt_t::RESET</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: WDT reset trigger (write password to "feed" watchdog) </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__wdt_8h_source.html">neorv32_wdt.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" 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magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_xip_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__xip_8h_source.html">neorv32_xip.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a7ead9d6a4f784d766a6b2755c6d35235" id="r_a7ead9d6a4f784d766a6b2755c6d35235"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7ead9d6a4f784d766a6b2755c6d35235">CTRL</a></td></tr> +<tr class="separator:a7ead9d6a4f784d766a6b2755c6d35235"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aacb77d586c3caec518e8e0024cfe745c" id="r_aacb77d586c3caec518e8e0024cfe745c"><td class="memItemLeft" align="right" valign="top">const uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aacb77d586c3caec518e8e0024cfe745c">reserved</a></td></tr> +<tr class="separator:aacb77d586c3caec518e8e0024cfe745c"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ad64048bb3544e712b1c668c2ef343ccb" id="r_ad64048bb3544e712b1c668c2ef343ccb"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad64048bb3544e712b1c668c2ef343ccb">DATA_LO</a></td></tr> +<tr class="separator:ad64048bb3544e712b1c668c2ef343ccb"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a516ab9c075ef6d1fb741e243db7703b2" id="r_a516ab9c075ef6d1fb741e243db7703b2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a516ab9c075ef6d1fb741e243db7703b2">DATA_HI</a></td></tr> +<tr class="separator:a516ab9c075ef6d1fb741e243db7703b2"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>XIP module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a7ead9d6a4f784d766a6b2755c6d35235" name="a7ead9d6a4f784d766a6b2755c6d35235"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a7ead9d6a4f784d766a6b2755c6d35235">&#9670;&#160;</a></span>CTRL</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_xip_t::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: control register (<a class="el" href="neorv32__xip_8h.html#a72ed1ff87de1222cc3a13177c7483ceb">NEORV32_XIP_CTRL_enum</a>) </p> + +</div> +</div> +<a id="a516ab9c075ef6d1fb741e243db7703b2" name="a516ab9c075ef6d1fb741e243db7703b2"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a516ab9c075ef6d1fb741e243db7703b2">&#9670;&#160;</a></span>DATA_HI</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_xip_t::DATA_HI</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 12: SPI data register high </p> + +</div> +</div> +<a id="ad64048bb3544e712b1c668c2ef343ccb" name="ad64048bb3544e712b1c668c2ef343ccb"></a> +<h2 class="memtitle"><span class="permalink"><a href="#ad64048bb3544e712b1c668c2ef343ccb">&#9670;&#160;</a></span>DATA_LO</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_xip_t::DATA_LO</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 8: SPI data register low </p> + +</div> +</div> +<a id="aacb77d586c3caec518e8e0024cfe745c" name="aacb77d586c3caec518e8e0024cfe745c"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aacb77d586c3caec518e8e0024cfe745c">&#9670;&#160;</a></span>reserved</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">const uint32_t neorv32_xip_t::reserved</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 4: reserved </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__xip_8h_source.html">neorv32_xip.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structneorv32__xirq__t.html b/sw/structneorv32__xirq__t.html new file mode 100644 index 000000000..bf21350de --- /dev/null +++ b/sw/structneorv32__xirq__t.html @@ -0,0 +1,249 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" 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+</script> +<script type="text/javascript" src="menudata.js"></script> +<script type="text/javascript" src="menu.js"></script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { + initMenu('',true,false,'search.php','Search',false); + $(function() { init_search(); }); +}); +/* @license-end */ +</script> +<div id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">neorv32_xirq_t Struct Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="neorv32__xirq_8h_source.html">neorv32_xirq.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:aef3c2b491207abd68bf6392f97096a74" id="r_aef3c2b491207abd68bf6392f97096a74"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aef3c2b491207abd68bf6392f97096a74">EIE</a></td></tr> +<tr class="separator:aef3c2b491207abd68bf6392f97096a74"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a788d8004f3b85fb66e947415d8fcc058" id="r_a788d8004f3b85fb66e947415d8fcc058"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a788d8004f3b85fb66e947415d8fcc058">EIP</a></td></tr> +<tr class="separator:a788d8004f3b85fb66e947415d8fcc058"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ae4f7f3f41210ff329b6f82d5dfada88a" id="r_ae4f7f3f41210ff329b6f82d5dfada88a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae4f7f3f41210ff329b6f82d5dfada88a">ESC</a></td></tr> +<tr class="separator:ae4f7f3f41210ff329b6f82d5dfada88a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ab7117c210b5f0a8ebc369eeba6a4a5bc" id="r_ab7117c210b5f0a8ebc369eeba6a4a5bc"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab7117c210b5f0a8ebc369eeba6a4a5bc">TTYP</a></td></tr> +<tr class="separator:ab7117c210b5f0a8ebc369eeba6a4a5bc"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5fe0036a2cada585228b60aaa780e92a" id="r_a5fe0036a2cada585228b60aaa780e92a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5fe0036a2cada585228b60aaa780e92a">TPOL</a></td></tr> +<tr class="separator:a5fe0036a2cada585228b60aaa780e92a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a9be02c0398fab5763a3afbd7a018f092" id="r_a9be02c0398fab5763a3afbd7a018f092"><td class="memItemLeft" align="right" valign="top">const uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9be02c0398fab5763a3afbd7a018f092">reserved0</a></td></tr> +<tr class="separator:a9be02c0398fab5763a3afbd7a018f092"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:ac4c999cf3da75e39753619f917d9d654" id="r_ac4c999cf3da75e39753619f917d9d654"><td class="memItemLeft" align="right" valign="top">const uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac4c999cf3da75e39753619f917d9d654">reserved1</a></td></tr> +<tr class="separator:ac4c999cf3da75e39753619f917d9d654"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:afba6ed500e1448719783923975b2dc64" id="r_afba6ed500e1448719783923975b2dc64"><td class="memItemLeft" align="right" valign="top">const uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afba6ed500e1448719783923975b2dc64">reserved2</a></td></tr> +<tr class="separator:afba6ed500e1448719783923975b2dc64"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>XIRQ module prototype </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="aef3c2b491207abd68bf6392f97096a74" name="aef3c2b491207abd68bf6392f97096a74"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aef3c2b491207abd68bf6392f97096a74">&#9670;&#160;</a></span>EIE</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t neorv32_xirq_t::EIE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>offset 0: external interrupt enable register </p> + +</div> +</div> +<a id="a788d8004f3b85fb66e947415d8fcc058" name="a788d8004f3b85fb66e947415d8fcc058"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a788d8004f3b85fb66e947415d8fcc058">&#9670;&#160;</a></span>EIP</h2> + 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+<p>offset 12: external interrupt source register </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/lib/include/<a class="el" href="neorv32__xirq_8h_source.html">neorv32_xirq.h</a></li> +</ul> +</div><!-- contents --> +<!-- start footer part --> +<hr class="footer"/><address class="footer"><small> +Generated by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.12.0 +</small></address> +</div><!-- doc-content --> +</body> +</html> diff --git a/sw/structrecord.html b/sw/structrecord.html new file mode 100644 index 000000000..b61ef1b3e --- /dev/null +++ b/sw/structrecord.html @@ -0,0 +1,155 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml" lang="en-US"> +<head> +<meta http-equiv="Content-Type" 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id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function() { codefold.init(0); }); +/* @license-end */ +</script> +<script type="text/javascript" src="menudata.js"></script> +<script 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id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">t_neorv32_spi Struct Reference</div></div> +</div><!--header--> +<div class="contents"> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a487a6510820871ff8d0da7699463f6d9" id="r_a487a6510820871ff8d0da7699463f6d9"><td class="memItemLeft" align="right" valign="top">uint8_t *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a487a6510820871ff8d0da7699463f6d9">ptrSpiBuf</a></td></tr> +<tr class="separator:a487a6510820871ff8d0da7699463f6d9"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a435c266758a440d32de4344472e3514a" id="r_a435c266758a440d32de4344472e3514a"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a435c266758a440d32de4344472e3514a">uint8Csn</a></td></tr> +<tr class="separator:a435c266758a440d32de4344472e3514a"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a71fb3f91af197e1abdbe97d62130ad0f" id="r_a71fb3f91af197e1abdbe97d62130ad0f"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a71fb3f91af197e1abdbe97d62130ad0f">uint16Fifo</a></td></tr> +<tr class="separator:a71fb3f91af197e1abdbe97d62130ad0f"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa4d96f72e57fb6930ab43de6fb0a85ae" id="r_aa4d96f72e57fb6930ab43de6fb0a85ae"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa4d96f72e57fb6930ab43de6fb0a85ae">uint32Total</a></td></tr> +<tr class="separator:aa4d96f72e57fb6930ab43de6fb0a85ae"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:aa89b7a769e54e331798e4d68d02a7b43" id="r_aa89b7a769e54e331798e4d68d02a7b43"><td class="memItemLeft" align="right" valign="top">volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa89b7a769e54e331798e4d68d02a7b43">uint32Write</a></td></tr> +<tr class="separator:aa89b7a769e54e331798e4d68d02a7b43"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a5750a54f8312ec2fed349eb9fbeff323" id="r_a5750a54f8312ec2fed349eb9fbeff323"><td class="memItemLeft" align="right" valign="top">volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5750a54f8312ec2fed349eb9fbeff323">uint32Read</a></td></tr> +<tr class="separator:a5750a54f8312ec2fed349eb9fbeff323"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a8ed31f9393bee5b963e08582b6c517ed" id="r_a8ed31f9393bee5b963e08582b6c517ed"><td class="memItemLeft" align="right" valign="top">volatile uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8ed31f9393bee5b963e08582b6c517ed">uint8IsBusy</a></td></tr> +<tr class="separator:a8ed31f9393bee5b963e08582b6c517ed"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a id="a487a6510820871ff8d0da7699463f6d9" name="a487a6510820871ff8d0da7699463f6d9"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a487a6510820871ff8d0da7699463f6d9">&#9670;&#160;</a></span>ptrSpiBuf</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t* t_neorv32_spi::ptrSpiBuf</td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI buffer data pointer </p> + +</div> +</div> +<a id="a71fb3f91af197e1abdbe97d62130ad0f" name="a71fb3f91af197e1abdbe97d62130ad0f"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a71fb3f91af197e1abdbe97d62130ad0f">&#9670;&#160;</a></span>uint16Fifo</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint16_t t_neorv32_spi::uint16Fifo</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Number of elements in Fifo </p> + +</div> +</div> +<a id="a5750a54f8312ec2fed349eb9fbeff323" name="a5750a54f8312ec2fed349eb9fbeff323"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a5750a54f8312ec2fed349eb9fbeff323">&#9670;&#160;</a></span>uint32Read</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">volatile uint32_t t_neorv32_spi::uint32Read</td> + </tr> + </table> +</div><div class="memdoc"> +<p>From SPI core read elements </p> + +</div> +</div> +<a id="aa4d96f72e57fb6930ab43de6fb0a85ae" name="aa4d96f72e57fb6930ab43de6fb0a85ae"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa4d96f72e57fb6930ab43de6fb0a85ae">&#9670;&#160;</a></span>uint32Total</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t t_neorv32_spi::uint32Total</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Number of elements in buffer </p> + +</div> +</div> +<a id="aa89b7a769e54e331798e4d68d02a7b43" name="aa89b7a769e54e331798e4d68d02a7b43"></a> +<h2 class="memtitle"><span class="permalink"><a href="#aa89b7a769e54e331798e4d68d02a7b43">&#9670;&#160;</a></span>uint32Write</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">volatile uint32_t t_neorv32_spi::uint32Write</td> + </tr> + </table> +</div><div class="memdoc"> +<p>To SPI core write elements </p> + +</div> +</div> +<a id="a435c266758a440d32de4344472e3514a" name="a435c266758a440d32de4344472e3514a"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a435c266758a440d32de4344472e3514a">&#9670;&#160;</a></span>uint8Csn</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t t_neorv32_spi::uint8Csn</td> + </tr> + </table> +</div><div class="memdoc"> +<p>SPI chip select channel </p> + +</div> +</div> +<a id="a8ed31f9393bee5b963e08582b6c517ed" name="a8ed31f9393bee5b963e08582b6c517ed"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a8ed31f9393bee5b963e08582b6c517ed">&#9670;&#160;</a></span>uint8IsBusy</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">volatile uint8_t t_neorv32_spi::uint8IsBusy</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Spi Core is Busy </p> + +</div> +</div> +<hr/>The documentation for this struct was generated from the following file:<ul> +<li>sw/example/demo_spi_irq/drv/<a class="el" href="neorv32__spi__irq_8h_source.html">neorv32_spi_irq.h</a></li> +</ul> +</div><!-- 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id="main-nav"></div> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +$(function(){ initResizable(false); }); +/* @license-end */ +</script> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +</div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<div id="MSearchResults"> +<div class="SRPage"> +<div id="SRIndex"> +<div id="SRResults"></div> +<div class="SRStatus" id="Loading">Loading...</div> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</div> +</div> +</div> + +</div><!-- top --> +<div id="doc-content"> +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">float_conv_t Union Reference</div></div> +</div><!--header--> +<div class="contents"> + +<p><code>#include &lt;<a class="el" href="float__corner__test_2neorv32__zfinx__extension__intrinsics_8h_source.html">neorv32_zfinx_extension_intrinsics.h</a>&gt;</code></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a59ad19d41b1d973a6bda9032e1937606" id="r_a59ad19d41b1d973a6bda9032e1937606"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a59ad19d41b1d973a6bda9032e1937606">binary_value</a></td></tr> +<tr class="separator:a59ad19d41b1d973a6bda9032e1937606"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a95f2e38b437bd8d4e8de7f61d7474788" id="r_a95f2e38b437bd8d4e8de7f61d7474788"><td class="memItemLeft" align="right" valign="top">float&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a95f2e38b437bd8d4e8de7f61d7474788">float_value</a></td></tr> +<tr class="separator:a95f2e38b437bd8d4e8de7f61d7474788"><td class="memSeparator" colspan="2">&#160;</td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> +<div class="textblock"><p>Sanity check Custom data type to access floating-point values as native floats and in binary representation </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a id="a59ad19d41b1d973a6bda9032e1937606" name="a59ad19d41b1d973a6bda9032e1937606"></a> +<h2 class="memtitle"><span class="permalink"><a href="#a59ad19d41b1d973a6bda9032e1937606">&#9670;&#160;</a></span>binary_value</h2> + +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t float_conv_t::binary_value</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Access as 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href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"><div class="title">subwords16_t Union Reference</div></div> +</div><!--header--> +<div class="contents"> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:af3542fb53e1cf8cf51043e17123a5955" id="r_af3542fb53e1cf8cf51043e17123a5955"><td class="memItemLeft" align="right" valign="top"><a id="af3542fb53e1cf8cf51043e17123a5955" name="af3542fb53e1cf8cf51043e17123a5955"></a> +uint16_t&#160;</td><td class="memItemRight" valign="bottom"><b>uint16</b> [sizeof(uint16_t)/sizeof(uint16_t)]</td></tr> +<tr class="separator:af3542fb53e1cf8cf51043e17123a5955"><td class="memSeparator" colspan="2">&#160;</td></tr> +<tr class="memitem:a59531d2a833b3d540767c7fdd085a6d5" id="r_a59531d2a833b3d540767c7fdd085a6d5"><td class="memItemLeft" align="right" valign="top"><a id="a59531d2a833b3d540767c7fdd085a6d5" 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type="text/css"/> +<script type="text/javascript" src="search/searchdata.js"></script> +<script type="text/javascript" src="search/search.js"></script> +<link href="doxygen.css" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr id="projectrow"> + <td id="projectlogo"><img alt="Logo" src="neorv32_logo_small.png"/></td> + <td id="projectalign"> + <div id="projectname">NEORV32 Software Framework Documentation + </div> + <div id="projectbrief">The NEORV32 RISC-V Processor</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<!-- Generated by Doxygen 1.12.0 --> +<script type="text/javascript"> +/* @license magnet:?xt=urn:btih:d3d9a9a6595521f9666a5e94cc830dab83b65699&amp;dn=expat.txt MIT */ +var searchBox = new SearchBox("searchBox", "search/",'.html'); +/* @license-end */ +</script> +<script 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#toc{border:0!important;text-align:left!important;padding:0!important;margin:0!important} +body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-break-before:always} +.listingblock code[data-lang]::before{display:block} +#footer{padding:0 .9375em} +.hide-on-print{display:none!important} +.print-only{display:block!important} +.hide-for-print{display:none!important} +.show-for-print{display:inherit!important}} +@media amzn-kf8,print{#header>h1:first-child{margin-top:1.25rem} +.sect1{padding:0!important} +.sect1+.sect1{border:0} +#footer{background:none} +#footer-text{color:rgba(0,0,0,.6);font-size:.9em}} +@media amzn-kf8{#header,#content,#footnotes,#footer{padding:0}} +</style> +<link rel="stylesheet" href="https://cdnjs.cloudflare.com/ajax/libs/font-awesome/4.7.0/css/font-awesome.min.css"> +</head> +<body class="book toc2 toc-left"> +<div id="header"> +<h1>The NEORV32 RISC-V Processor - User Guide</h1> +<div class="details"> +<span id="revnumber">version v1.10.5-r58-gf1069d11</span> +</div> +<div id="toc" class="toc2"> +<div id="toctitle">Table of Contents</div> +<ul class="sectlevel1"> +<li><a href="#_software_toolchain_setup">1. Software Toolchain Setup</a> +<ul class="sectlevel2"> +<li><a href="#_building_the_toolchain_from_scratch">1.1. Building the Toolchain from Scratch</a></li> +<li><a href="#_downloading_and_installing_a_prebuilt_toolchain">1.2. Downloading and Installing a Prebuilt Toolchain</a> +<ul class="sectlevel3"> +<li><a href="#_use_the_pre_built_toolchains">1.2.1. Use The Pre-Built Toolchains</a></li> +<li><a href="#_use_a_third_party_toolchain">1.2.2. Use a Third Party Toolchain</a></li> +</ul> +</li> +<li><a href="#_installation">1.3. Installation</a></li> +<li><a href="#_testing_the_installation">1.4. Testing the Installation</a></li> +</ul> +</li> +<li><a href="#_general_hardware_setup">2. General Hardware Setup</a></li> +<li><a href="#_general_software_framework_setup">3. General Software Framework Setup</a> +<ul class="sectlevel2"> +<li><a href="#_modifying_the_linker_script">3.1. Modifying the Linker Script</a></li> +<li><a href="#_overriding_the_default_configuration">3.2. Overriding the Default Configuration</a></li> +</ul> +</li> +<li><a href="#_application_program_compilation">4. Application Program Compilation</a></li> +<li><a href="#_uploading_and_starting_of_a_binary_executable_image_via_uart">5. Uploading and Starting of a Binary Executable Image via UART</a></li> +<li><a href="#_installing_an_executable_directly_into_memory">6. Installing an Executable Directly Into Memory</a></li> +<li><a href="#_setup_of_a_new_application_program_project">7. Setup of a New Application Program Project</a></li> +<li><a href="#_application_specific_processor_configuration">8. Application-Specific Processor Configuration</a> +<ul class="sectlevel2"> +<li><a href="#_optimize_for_performance">8.1. Optimize for Performance</a></li> +<li><a href="#_optimize_for_size">8.2. Optimize for Size</a></li> +<li><a href="#_optimize_for_clock_speed">8.3. Optimize for Clock Speed</a></li> +<li><a href="#_optimize_for_energy">8.4. Optimize for Energy</a></li> +</ul> +</li> +<li><a href="#_adding_custom_hardware_modules">9. Adding Custom Hardware Modules</a> +<ul class="sectlevel2"> +<li><a href="#_standard_external_interfaces">9.1. Standard (<em>External</em>) Interfaces</a></li> +<li><a href="#_external_bus_interface">9.2. External Bus Interface</a></li> +<li><a href="#_custom_functions_subsystem">9.3. Custom Functions Subsystem</a></li> +<li><a href="#_custom_functions_unit">9.4. Custom Functions Unit</a></li> +<li><a href="#_comparative_summary">9.5. Comparative Summary</a></li> +</ul> +</li> +<li><a href="#_customizing_the_internal_bootloader">10. Customizing the Internal Bootloader</a> +<ul class="sectlevel2"> +<li><a href="#_auto_boot_configuration">10.1. Auto-Boot Configuration</a></li> +</ul> +</li> +<li><a href="#_programming_an_external_spi_flash_via_the_bootloader">11. Programming an External SPI Flash via the Bootloader</a> +<ul class="sectlevel2"> +<li><a href="#_programming_an_executable">11.1. Programming an Executable</a></li> +</ul> +</li> +<li><a href="#_packaging_the_processor_as_vivado_ip_block">12. Packaging the Processor as Vivado IP Block</a></li> +<li><a href="#_simulating_the_processor">13. Simulating the Processor</a> +<ul class="sectlevel2"> +<li><a href="#_testbench">13.1. Testbench</a></li> +<li><a href="#_faster_simulation_console_output">13.2. Faster Simulation Console Output</a></li> +<li><a href="#_simulation_using_a_shell_script_with_ghdl">13.3. Simulation using a shell script (with GHDL)</a></li> +<li><a href="#_simulation_using_application_makefiles_in_console_with_ghdl">13.4. Simulation using Application Makefiles (In-Console with GHDL)</a> +<ul class="sectlevel3"> +<li><a href="#_hello_world">13.4.1. Hello World!</a></li> +</ul> +</li> +<li><a href="#_advanced_simulation_using_vunit">13.5. Advanced Simulation using VUnit</a></li> +</ul> +</li> +<li><a href="#_vhdl_development_environment">14. VHDL Development Environment</a></li> +<li><a href="#_building_the_documentation">15. Building the Documentation</a></li> +<li><a href="#_zephyr_rtos_support">16. Zephyr RTOS Support</a></li> +<li><a href="#_freertos_support">17. FreeRTOS Support</a></li> +<li><a href="#_litex_soc_builder_support">18. LiteX SoC Builder Support</a> +<ul class="sectlevel2"> +<li><a href="#_litex_setup">18.1. LiteX Setup</a></li> +<li><a href="#_litex_simulation">18.2. LiteX Simulation</a></li> +</ul> +</li> +<li><a href="#_debugging_using_the_on_chip_debugger">19. Debugging using the On-Chip Debugger</a> +<ul class="sectlevel2"> +<li><a href="#_hardware_requirements">19.1. Hardware Requirements</a></li> +<li><a href="#_openocd">19.2. OpenOCD</a></li> +<li><a href="#_debugging_with_gdb">19.3. Debugging with GDB</a> +<ul class="sectlevel3"> +<li><a href="#_software_breakpoints">19.3.1. Software Breakpoints</a></li> +<li><a href="#_hardware_breakpoints">19.3.2. Hardware Breakpoints</a></li> +</ul> +</li> +<li><a href="#_segger_embedded_studio">19.4. Segger Embedded Studio</a></li> +</ul> +</li> +<li><a href="#_neorv32_in_verilog">20. NEORV32 in Verilog</a></li> +<li><a href="#_eclipse_ide">21. Eclipse IDE</a> +<ul class="sectlevel2"> +<li><a href="#_eclipse_prerequisites">21.1. Eclipse Prerequisites</a></li> +<li><a href="#_import_the_provided_eclipse_example_project">21.2. Import The Provided Eclipse Example Project</a></li> +<li><a href="#_setup_a_new_eclipse_project_from_scratch">21.3. Setup a new Eclipse Project from Scratch</a> +<ul class="sectlevel3"> +<li><a href="#_create_a_new_project">21.3.1. Create a new Project</a></li> +<li><a href="#_add_initial_files">21.3.2. Add Initial Files</a></li> +<li><a href="#_add_build_targets_optional">21.3.3. Add Build Targets (optional)</a></li> +</ul> +</li> +<li><a href="#_configure_build_tools">21.4. Configure Build Tools</a></li> +<li><a href="#_adjust_default_build_configuration_optional">21.5. Adjust Default Build Configuration (optional)</a> +<ul class="sectlevel3"> +<li><a href="#_add_neorv32_software_framework">21.5.1. Add NEORV32 Software Framework</a></li> +<li><a href="#_setup_openocd">21.5.2. Setup OpenOCD</a></li> +<li><a href="#_setup_serial_terminal">21.5.3. Setup Serial Terminal</a></li> +</ul> +</li> +<li><a href="#_eclipse_setup_references">21.6. Eclipse Setup References</a></li> +</ul> +</li> +<li><a href="#_legal">22. Legal</a> +<ul class="sectlevel2"> +<li><a href="#_about">About</a></li> +<li><a href="#_license">License</a></li> +<li><a href="#_proprietary_notice">Proprietary Notice</a></li> +<li><a href="#_disclaimer">Disclaimer</a></li> +<li><a href="#_limitation_of_liability_for_external_links">Limitation of Liability for External Links</a></li> +<li><a href="#_citing">Citing</a></li> +<li><a href="#_acknowledgments">Acknowledgments</a></li> +</ul> +</li> +</ul> +</div> +</div> +<div id="content"> +<div id="preamble"> +<div class="sectionbody"> +<div class="imageblock text-center"> +<div class="content"> +<a class="image" href="https://github.com/stnolting/neorv32"><img src="../img/neorv32_logo.png" alt="neorv32 logo"></a> +</div> +</div> +<div class="imageblock text-center"> +<div class="content"> +<a class="image" href="https://riscv.org/"><img src="../img/riscv_logo.png" alt="riscv logo" width="350"></a> +</div> +</div> +<div class="paragraph text-center"> +<p><a href="https://github.com/stnolting/neorv32"><span class="image"><img src="https://img.shields.io/badge/GitHub-stnolting%2Fneorv32-ffbd00?style=flat-square&amp;logo=github&amp;" alt="GitHub stnolting%2Fneorv32 ffbd00?style=flat square&amp;logo=github&amp;" title="homepage"></span></a> +<a href="https://github.com/stnolting/neorv32/blob/main/LICENSE"><span class="image"><img src="https://img.shields.io/github/license/stnolting/neorv32?longCache=true&amp;style=flat-square" alt="neorv32?longCache=true&amp;style=flat square" title="license"></span></a> +<a href="https://github.com/stnolting/neorv32/releases/tag/nightly"><span class="image"><img src="https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&amp;style=flat-square&amp;logo=asciidoctor" alt="data%20sheet PDF ffbd00?longCache=true&amp;style=flat square&amp;logo=asciidoctor" title="datasheet (pdf)"></span></a> +<a href="https://stnolting.github.io/neorv32"><span class="image"><img src="https://img.shields.io/badge/-HTML-ffbd00?longCache=true&amp;style=flat-square" alt=" HTML ffbd00?longCache=true&amp;style=flat square" title="datasheet (html)"></span></a> +<a href="https://github.com/stnolting/neorv32/releases/tag/nightly"><span class="image"><img src="https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&amp;style=flat-square&amp;logo=asciidoctor" alt="user%20guide PDF ffbd00?longCache=true&amp;style=flat square&amp;logo=asciidoctor" title="userguide (pdf)"></span></a> +<a href="https://stnolting.github.io/neorv32/sw/files.html"><span class="image"><img src="https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&amp;style=flat-square&amp;logo=Doxygen" alt="doxygen HTML ffbd00?longCache=true&amp;style=flat square&amp;logo=Doxygen" title="doxygen"></span></a><br> +<a href="https://github.com/stnolting/neorv32/releases"><span class="image"><img src="https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&amp;style=flat-square&amp;logo=GitHub" alt="neorv32?longCache=true&amp;style=flat square&amp;logo=GitHub" title="release"></span></a> +<a href="https://github.com/stnolting/neorv32/releases"><span class="image"><img src="https://img.shields.io/github/commits-since/stnolting/neorv32/latest?longCache=true&amp;style=flat-square&amp;logo=GitHub" alt="latest?longCache=true&amp;style=flat square&amp;logo=GitHub" title="release-commits"></span></a></p> +</div> +<div class="paragraph"> +<p><strong>Let&#8217;s Get It Started!</strong></p> +</div> +<div class="paragraph"> +<p>This user guide uses the NEORV32 project <em>as is</em> from the official <code>neorv32</code> repository. +To make your first NEORV32 project run, follow the guides from the upcoming sections. It is recommended to +follow these guides step by step and eventually in the presented order.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +This guide uses the minimalistic and platform/toolchain agnostic SoC <strong>test setups</strong> from +<code>rtl/test_setups</code> for illustration. You can use one of the provided test setups for +your first FPGA tests.<br> +<br> +For more sophisticated example setups have a look at the +<a href="https://github.com/stnolting/neorv32-setups">neorv32-setups</a> repository, +which provides <strong>SoC setups</strong> for various FPGAs, boards and toolchains. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p><strong>Quick Links</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="#_software_toolchain_setup">Toolchain</a>, <a href="#_general_hardware_setup">hardware</a> and <a href="#_general_software_framework_setup">general software framework</a> setup</p> +</li> +<li> +<p><a href="#_application_program_compilation">compile</a> an application and <a href="#_uploading_and_starting_of_a_binary_executable_image_via_uart">upload</a> it or making it +<a href="#_installing_an_executable_directly_into_memory">persistent</a> in internal memory</p> +</li> +<li> +<p>setup a new <a href="#_setup_of_a_new_application_program_project">application project</a></p> +</li> +<li> +<p><a href="#_application_specific_processor_configuration">optimizing</a> the core for your application</p> +</li> +<li> +<p>add <a href="#_adding_custom_hardware_modules">custom hardware extensions</a> and <a href="#_customizing_the_internal_bootloader">customizing the bootloader</a></p> +</li> +<li> +<p><a href="#_programming_an_external_spi_flash_via_the_bootloader">program</a> an external SPI flash for persistent application storage</p> +</li> +<li> +<p>generate an AMD Vivado <a href="#_packaging_the_processor_as_vivado_ip_block">IP block</a></p> +</li> +<li> +<p><a href="#_simulating_the_processor">simulate</a> the processor and <a href="#_building_the_documentation">build the documentation</a></p> +</li> +<li> +<p>RTOS support for <a href="#_zephyr_rtos_support">Zephyr</a> and <a href="#_freertos_support">FreeRTOS</a></p> +</li> +<li> +<p>build SoCs using <a href="#_litex_soc_builder_support">LiteX</a></p> +</li> +<li> +<p>in-system <a href="#_debugging_using_the_on_chip_debugger">debugging</a> of the whole processor</p> +</li> +<li> +<p><a href="#_neorv32_in_verilog">NEORV32 in Verilog</a> - an all-Verilog "version" of the processor</p> +</li> +<li> +<p>use the <a href="#_eclipse_ide">Eclipse IDE</a> to develop and debug code for the NEORV32</p> +</li> +</ul> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_software_toolchain_setup">1. Software Toolchain Setup</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>To compile (and debug) executables for the NEORV32 a RISC-V toolchain is required. +There are two possibilities to get this:</p> +</div> +<div class="olist arabic"> +<ol class="arabic"> +<li> +<p>Download and <em>build</em> the official RISC-V GNU toolchain yourself.</p> +</li> +<li> +<p>Download and install a prebuilt version of the toolchain; this might also done via the package manager / app store of your OS</p> +</li> +</ol> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The default toolchain prefix (<code>RISCV_PREFIX</code> variable) for this project is <strong><code>riscv32-unknown-elf-</code></strong>. Of course you can use any other RISC-V +toolchain (like <code>riscv64-unknown-elf-</code>) that is capable to emit code for a <code>rv32</code> architecture. Just change <code>RISCV_PREFIX</code> +according to your needs. +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_building_the_toolchain_from_scratch">1.1. Building the Toolchain from Scratch</h3> +<div class="paragraph"> +<p>To build the toolchain by yourself you can follow the guide from the official <a href="https://github.com/riscv-collab/riscv-gnu-toolchain" class="bare">https://github.com/riscv-collab/riscv-gnu-toolchain</a> GitHub page. +You need to make sure the generated toolchain fits the architecture of the NEORV32 core. To get a toolchain that even supports minimal +ISA extension configurations, it is recommend to compile for <code>rv32i</code> only. Please note that this minimal ISA also provides further ISA +extensions like <code>m</code> or <code>c</code>. Of course you can use a <em>multilib</em> approach to generate toolchains for several target ISAs at once.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 1. Preparing GCC build for <code>rv32i</code> (minimal ISA)</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">$ git clone https://github.com/riscv/riscv-gnu-toolchain +$ cd riscv-gnu-toolchain + +$ riscv-gnu-toolchain$ ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32 +$ riscv-gnu-toolchain$ make</code></pre> +</div> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Keep in mind that - for instance - a toolchain build with <code>--with-arch=rv32imc</code> provides library code (like the C +standard library) compiled entirely utilizing compressed (<code>C</code>) and <code>mul</code>/<code>div</code> instructions (<code>M</code>). Hence, this +code CANNOT be executed (without emulation) on an architecture that does not support these ISA extensions. +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_downloading_and_installing_a_prebuilt_toolchain">1.2. Downloading and Installing a Prebuilt Toolchain</h3> +<div class="paragraph"> +<p>Alternatively, you can download a prebuilt toolchain.</p> +</div> +<div class="sect3"> +<h4 id="_use_the_pre_built_toolchains">1.2.1. Use The Pre-Built Toolchains</h4> +<div class="paragraph"> +<p>We have compiled several GCC toolchains on a 64-bit x86 Ubuntu (Ubuntu on Windows, actually) and uploaded it to +GitHub. You can directly download the according toolchain archive as single <em>zip-file</em> within a packed +release from <a href="https://github.com/stnolting/riscv-gcc-prebuilt" class="bare">https://github.com/stnolting/riscv-gcc-prebuilt</a>. More information about downloading and installing +these prebuilt toolchains can be found in the repository&#8217;s README.</p> +</div> +</div> +<div class="sect3"> +<h4 id="_use_a_third_party_toolchain">1.2.2. Use a Third Party Toolchain</h4> +<div class="paragraph"> +<p>Of course you can also use any other prebuilt version of the toolchain. There are a lot RISC-V GCC packages out there - +even for Windows. On Linux system you might even be able to fetch a toolchain via your distribution&#8217;s package manager.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Make sure the toolchain can (also) emit code for a <code>rv32i</code> architecture, uses the <code>ilp32</code> or <code>ilp32e</code> ABI and <strong>was not build</strong> using +CPU extensions that are not supported by the NEORV32 (like <code>D</code>). +</td> +</tr> +</table> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_installation">1.3. Installation</h3> +<div class="paragraph"> +<p>Now you have the toolchain binaries. The last step is to add them to your <code>PATH</code> environment variable (if you have not +already done so): make sure to add the <em>binaries</em> folder (<code>bin</code>) of your toolchain.</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">$ export PATH=$PATH:/opt/riscv/bin</code></pre> +</div> +</div> +<div class="paragraph"> +<p>You should add this command to your <code>.bashrc</code> (if you are using bash) to automatically add the RISC-V +toolchain at every console start.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_testing_the_installation">1.4. Testing the Installation</h3> +<div class="paragraph"> +<p>To make sure everything works fine, navigate to an example project in the NEORV32 example folder and +execute the following command:</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">neorv32/sw/example/demo_blink_led$ make check</code></pre> +</div> +</div> +<div class="paragraph"> +<p>This will test all the tools required for generating NEORV32 executables. +Everything is working fine if <code>Toolchain check OK</code> appears at the end.</p> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_general_hardware_setup">2. General Hardware Setup</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>This guide shows the basics of setting up a NEORV32 project for simulation or synthesis +<em>from scratch</em>. It uses a simple, exemplary test "SoC" setup of the processor to keep things simple at the beginning. +This simple setup is intended for a first test / evaluation of the NEORV32.</p> +</div> +<div class="paragraph"> +<p>The NEORV32 project features three minimalistic pre-configured test setups in +<a href="https://github.com/stnolting/neorv32/blob/main/rtl/test_setups"><code>rtl/test_setups</code></a>. +These test setups only implement very basic processor and CPU features and mainly differ in the actual boot configuration.</p> +</div> +<div class="imageblock text-center"> +<div class="content"> +<img src="../img/neorv32_test_setup.png" alt="neorv32 test setup"> +</div> +<div class="title">Figure 1. NEORV32 "hello world" test setup (<code>rtl/test_setups/neorv32_test_setup_bootloader.vhd</code>)</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Create a new project with your FPGA/ASIC/simulator EDA tool of choice.</p> +</li> +<li> +<p>Add all VHDL files from the project&#8217;s <code>rtl/core</code> folder to your project. +Make sure to add all these rtl files to a new library called <code>neorv32</code>. If your toolchain does not +provide a field to enter the library name, check out the "properties" menu of the added rtl files.</p> +</li> +</ol> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Compile Order and File-List Files</div> +Some tools (like Lattice Radiant) might require a <em>manual compile order</em> of the VHDL source files to +identify the dependencies. The <code>rtl</code> folder features file-list files that list all required HDL files in +their recommended compilation order (see <a href="https://stnolting.github.io/neorv32/#_file_list_files" class="bare">https://stnolting.github.io/neorv32/#_file_list_files</a>). +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="3"> +<li> +<p>The <code>rtl/core/neorv32_top.vhd</code> VHDL file is the top entity of the NEORV32 processor, which can be +instantiated within the actual project. However, in this tutorial we will use one of the pre-defined +test setups from <code>rtl/test_setups</code> (see above).</p> +</li> +</ol> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Make sure to include the <code>neorv32</code> package into your design when instantiating the processor: add +<code>library neorv32;</code> and <code>use neorv32.neorv32_package.all;</code> to your design unit. +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="4"> +<li> +<p>Add the pre-defined test setup of choice to the project, too, and select it as <strong>top entity</strong>.</p> +</li> +<li> +<p>The entity of the test setups provides a minimal set of configuration generics, that might have +to be adapted to match your FPGA and board:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="title">Listing 2. Test setup entity - configuration generics</div> +<div class="content"> +<pre class="highlight"><code class="language-vhdl" data-lang="vhdl">generic ( + -- adapt these for your setup -- + CLOCK_FREQUENCY : natural := 100000000; <i class="conum" data-value="1"></i><b>(1)</b> + MEM_INT_IMEM_SIZE : natural := 16*1024; <i class="conum" data-value="2"></i><b>(2)</b> + MEM_INT_DMEM_SIZE : natural := 8*1024 <i class="conum" data-value="3"></i><b>(3)</b> +);</code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td>Clock frequency of <code>clk_i</code> signal in Hertz</td> +</tr> +<tr> +<td><i class="conum" data-value="2"></i><b>2</b></td> +<td>Default size of internal instruction memory: 16kB</td> +</tr> +<tr> +<td><i class="conum" data-value="3"></i><b>3</b></td> +<td>Default size of internal data memory: 8kB</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="6"> +<li> +<p>If you want to or if your FPGA does not provide sufficient resources you can modify the +<em>memory sizes</em> (<code>MEM_INT_IMEM_SIZE</code> and <code>MEM_INT_DMEM_SIZE</code>).</p> +</li> +<li> +<p>There is one generic that has to be set according to your FPGA board setup: the actual clock frequency +of the top&#8217;s clock input signal (<code>clk_i</code>). Use the <code>CLOCK_FREQUENCY</code> generic to specify your clock source&#8217;s +frequency in Hertz (Hz).</p> +</li> +</ol> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Memory Layout</div> +If you have changed the default memory configuration (<code>MEM_INT_IMEM_SIZE</code> and <code>MEM_INT_DMEM_SIZE</code> generics) +keep those new sizes in mind - these values are required for setting up the software framework in the next +section <a href="#_general_software_framework_setup">General Software Framework Setup</a>. +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="8"> +<li> +<p>Assign the signals of the test setup top entity to the according pins of your FPGA board. +All the signals can be found in the entity declaration of the corresponding test setup, e.g.:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="title">Listing 3. Ports of <code>neorv32_test_setup_bootloader.vhd</code></div> +<div class="content"> +<pre class="highlight"><code class="language-vhdl" data-lang="vhdl">port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- GPIO -- + gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output + -- UART0 -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic -- UART0 receive data +);</code></pre> +</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Signal Polarity</div> +If your FPGA board has inverse polarity for certain input/output you need to add inverters. Example: The reset signal +<code>rstn_i</code> is low-active by default; the LEDs connected to <code>gpio_o</code> are high-active by default. +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="9"> +<li> +<p>Attach the clock input <code>clk_i</code> to your clock source and connect the reset line <code>rstn_i</code> to a button of +your FPGA board. Check whether it is low-active or high-active - the reset signal of the processor is +<strong>low-active</strong>, so maybe you need to invert the input signal.</p> +</li> +<li> +<p>If possible, connected at least bit <code>0</code> of the GPIO output port <code>gpio_o</code> to a LED (see "Signal Polarity" note above).</p> +</li> +<li> +<p>If your are using a UART-based test setup connect the UART communication signals <code>uart0_txd_o</code> and <code>uart0_rxd_i</code> +to the host interface (e.g. a USB-UART converter).</p> +</li> +<li> +<p>If you are using the on-chip debugger setup connect the processor&#8217;s JTAG signal <code>jtag_*</code> to a suitable JTAG adapter.</p> +</li> +<li> +<p>Perform the project HDL compilation (synthesis, mapping, placement, routing, bitstream generation).</p> +</li> +<li> +<p>Program the generated bitstream into your FPGA and press the button connected to the reset signal.</p> +</li> +<li> +<p>Done! The LED(s) connected to <code>gpio_o</code> should be flashing now.</p> +</li> +</ol> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_general_software_framework_setup">3. General Software Framework Setup</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>To allow executables to be <em>actually executed</em> on the NEORV32 Processor the configuration of the software framework +has to be aware to the hardware configuration. This guide focuses on the <strong>memory configuration</strong>. To enable +certain CPU ISA features refer to the <a href="#_enabling_risc_v_cpu_extensions">[_enabling_risc_v_cpu_extensions]</a> section.</p> +</div> +<div class="paragraph"> +<p>This guide shows how to configure the linker script for a given hardware memory configuration. More information regarding the +linker script itself can be found in the according section of the data sheet: <a href="https://stnolting.github.io/neorv32/#_linker_script" class="bare">https://stnolting.github.io/neorv32/#_linker_script</a></p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +If you have <strong>not</strong> changed the <em>default</em> memory configuration in section <a href="#_general_hardware_setup">General Hardware Setup</a> +you are already done and you can skip the rest of this section. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Always keep the processor&#8217;s <a href="https://stnolting.github.io/neorv32/#_address_space">Address Space</a> layout in mind +when modifying the linker script +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>There are two options to modify the default memory configuration of the linker script:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p><a href="#_modifying_the_linker_script">Modifying the Linker Script</a></p> +</li> +<li> +<p><a href="#_overriding_the_default_configuration">Overriding the Default Configuration</a> (recommended!)</p> +</li> +</ol> +</div> +<div class="sect2"> +<h3 id="_modifying_the_linker_script">3.1. Modifying the Linker Script</h3> +<div class="paragraph"> +<p>This will modify the linker script <em>itself</em>.</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Open the NEORV32 linker script <code>sw/common/neorv32.ld</code> with a text editor. Right at the +beginning of this script you will find the <code> NEORV32 memory configuration </code> configuration section:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="title">Listing 4. Cut-out of the linker script <code>neorv32.ld</code></div> +<div class="content"> +<pre class="highlight"><code>/* Default rom/ram (IMEM/DMEM) sizes */ +__neorv32_rom_size = DEFINED(__neorv32_rom_size) ? __neorv32_rom_size : 2048M; <i class="conum" data-value="1"></i><b>(1)</b> +__neorv32_ram_size = DEFINED(__neorv32_ram_size) ? __neorv32_ram_size : 8K; <i class="conum" data-value="2"></i><b>(2)</b> + +/* Default HEAP size (= 0; no heap at all) */ +__neorv32_heap_size = DEFINED(__neorv32_heap_size) ? __neorv32_heap_size : 0; <i class="conum" data-value="3"></i><b>(3)</b> + +/* Default section base addresses - do not change this unless the hardware-defined address space layout is changed! */ +__neorv32_rom_base = DEFINED(__neorv32_rom_base) ? __neorv32_rom_base : 0x00000000; /* = VHDL package's "ispace_base_c" */ <i class="conum" data-value="4"></i><b>(4)</b> +__neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x80000000; /* = VHDL package's "dspace_base_c" */ <i class="conum" data-value="5"></i><b>(5)</b></code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td>Default (max) size of the instruction memory address space (right-most value) (internal/external IMEM): 2048MB</td> +</tr> +<tr> +<td><i class="conum" data-value="2"></i><b>2</b></td> +<td>Default size of the data memory address space (right-most value) (internal/external DMEM): 8kB</td> +</tr> +<tr> +<td><i class="conum" data-value="3"></i><b>3</b></td> +<td>Default size of the HEAP (right-most value): 0kB</td> +</tr> +<tr> +<td><i class="conum" data-value="4"></i><b>4</b></td> +<td>Default base address of the instruction memory address space (right-most value): <code>0x00000000</code></td> +</tr> +<tr> +<td><i class="conum" data-value="5"></i><b>5</b></td> +<td>Default base address of the data memory address space (right-most value): <code>0x80000000</code></td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="2"> +<li> +<p>Only the the <code>neorv32_ram_size</code> variable needs to modified! If you have changed the default DMEM (<em>MEM_INT_DMEM_SIZE</em> generic) +size then change the right-most parameter (here: <code>8kB</code>) so it is equal to your DMEM hardware configuration. The <code>neorv32_rom_size</code> +does not need to be modified even if you have changed the default IMEM size. +For more information see <a href="https://stnolting.github.io/neorv32/#_linker_script" class="bare">https://stnolting.github.io/neorv32/#_linker_script</a></p> +</li> +</ol> +</div> +<div class="olist arabic"> +<ol class="arabic" start="3"> +<li> +<p>Done! Save your changes and close the linker script.</p> +</li> +</ol> +</div> +</div> +<div class="sect2"> +<h3 id="_overriding_the_default_configuration">3.2. Overriding the Default Configuration</h3> +<div class="paragraph"> +<p>This will not change the default linker script at all. Hence, <strong>this approach is recommended</strong> as it allows a +per-project memory configuration without changing the code base.</p> +</div> +<div class="paragraph"> +<p>The RAM and ROM sizes from <a href="#_modifying_the_linker_script">Modifying the Linker Script</a> (as well as the according base addresses) can also be modified +by overriding the default values when invoking <code>make</code>. Therefore, the command needs to pass the according +values to the linker using the makefile&#8217;s <code>USER_FLAGS</code> variable.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +See section "Application Makefile" of the data sheet for more information regarding the default makefile variables: +<a href="https://stnolting.github.io/neorv32/#_application_makefile" class="bare">https://stnolting.github.io/neorv32/#_application_makefile</a> +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="title">Listing 5. Example: override default RAM (DMEM) and ROM (IMEM) size while invoking make</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">$ make USER_FLAGS+="-Wl,--defsym,__neorv32_ram_size=16k -Wl,--defsym,__neorv32_rom_size=32k" clean_all exe</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The <code>-Wl</code> passes the following command/flag to the linker while <code>--defsym</code> defines a symbol for the linker. +Hence, the default linker script section sizes are overridden. In this example the RAM size (=DMEM) is set to +16kB and the ROM size (=IMEM) is set to 32kB.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +When using this approach the customized attributes have to be specified every time the makefile is invoked! +You can put the RAM/ROM override commands into the project&#8217;s local makefile or define a simple shell script that defines +all the setup-related parameters (memory sizes, RISC-V ISA extensions, optimization goal, further tuning flags, etc.). +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_application_program_compilation">4. Application Program Compilation</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>This guide shows how to compile an example C-code application into a NEORV32 executable that +can be uploaded via the bootloader or the on-chip debugger.</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Open a terminal console and navigate to one of the project&#8217;s example programs. For instance, navigate to the +simple <code>sw/example_demo_blink_led</code> example program. This program uses the NEORV32 GPIO module to display +an 8-bit counter on the lowest eight bit of the <code>gpio_o</code> output port.</p> +</li> +<li> +<p>To compile the project and generate an executable simply execute:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">neorv32/sw/example/demo_blink_led$ make clean_all exe</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="3"> +<li> +<p>We are using the <code>clean_all</code> target to make sure everything is re-build.</p> +</li> +<li> +<p>This will compile and link the application sources together with all the included libraries. At the end, +your application is transformed into an ELF file (<code>main.elf</code>). The <em>NEORV32 image generator</em> (in <code>sw/image_gen</code>) +takes this file and creates a final executable. The makefile will show the resulting memory utilization and +the executable size:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">neorv32/sw/example/demo_blink_led$ make clean_all exe +Memory utilization: + text data bss dec hex filename + 1004 0 0 1004 3ec main.elf +Compiling ../../../sw/image_gen/image_gen +Executable (neorv32_exe.bin) size in bytes: +1016</code></pre> +</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Make sure the size of the <code>text</code> segment (3176 bytes here) does not overflow the size of the processor&#8217;s +IMEM (if used at all) - otherwise there will be an error during synthesis or during bootloader upload. +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="5"> +<li> +<p>That&#8217;s it. The <code>exe</code> target has created the actual executable <code>neorv32_exe.bin</code> in the current folder +that is ready to be uploaded to the processor.</p> +</li> +</ol> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +The compilation process will also create a <code>main.asm</code> assembly listing file in the current folder, which +shows the actual assembly code of the application. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_uploading_and_starting_of_a_binary_executable_image_via_uart">5. Uploading and Starting of a Binary Executable Image via UART</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>Follow this guide to use the bootloader to upload an executable via UART.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +This concept uses the default "Indirect Boot" scenario that uses the bootloader to upload new executables. +See datasheet section <a href="https://stnolting.github.io/neorv32/#_indirect_boot">Indirect Boot</a> for more information. +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +If your FPGA board does not provide such an interface - don&#8217;t worry! +Section <a href="#_installing_an_executable_directly_into_memory">Installing an Executable Directly Into Memory</a> shows how to +run custom programs on your FPGA setup without having a UART. +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Connect the primary UART (UART0) interface of your FPGA board to a serial port of your host computer.</p> +</li> +<li> +<p>Start a terminal program. In this tutorial, I am using TeraTerm for Windows. You can download it for free +from <a href="https://ttssh2.osdn.jp/index.html.en" class="bare">https://ttssh2.osdn.jp/index.html.en</a> . On Linux you could use <code>cutecom</code> (recommended) or <code>GTKTerm</code>, +which you can get here <a href="https://github.com/Jeija/gtkterm.git" class="bare">https://github.com/Jeija/gtkterm.git</a> (or install via your package manager).</p> +</li> +</ol> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<em>Any</em> terminal program that can connect to a serial port should work. However, make sure the program +can transfer data in <em>raw</em> byte mode without any protocol overhead around it. Some terminal programs struggle with +transmitting files larger than 4kB (see <a href="https://github.com/stnolting/neorv32/pull/215" class="bare">https://github.com/stnolting/neorv32/pull/215</a>). Try a different program +if uploading a binary does not work (terminal stall). +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="3"> +<li> +<p>Open a connection to the the serial port your UART is connected to. Configure the terminal setting according to the +following parameters:</p> +<div class="ulist"> +<ul> +<li> +<p>19200 Baud</p> +</li> +<li> +<p>8 data bits</p> +</li> +<li> +<p>1 stop bit</p> +</li> +<li> +<p>no parity bits</p> +</li> +<li> +<p><em>no</em> transmission/flow control protocol</p> +</li> +<li> +<p>newline on <code>\r\n</code> (carriage return <strong>and</strong> line feed)</p> +</li> +</ul> +</div> +</li> +</ol> +</div> +<div class="olist arabic"> +<ol class="arabic" start="4"> +<li> +<p>Also make sure that single chars are send from your computer <em>without</em> any consecutive "new line" or "carriage +return" commands. This is highly dependent on your terminal application of choice, TeraTerm only +sends the raw chars by default. In <code>cutecom</code>, change <code>LF</code> to <code>None</code> in the drop-down menu +next to the input text box.</p> +</li> +<li> +<p>Press the NEORV32 reset button to restart the bootloader. The status LED starts blinking and the +bootloader intro screen appears in your console. Hurry up and press any key (hit space!) to abort the +automatic boot sequence and to start the actual bootloader user interface console.</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="title">Listing 6. Bootloader console; aborted auto-boot sequence</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">&lt;&lt; NEORV32 Bootloader &gt;&gt; + +BLDV: Mar 7 2023 +HWV: 0x01080107 +CID: 0x00000000 +CLK: 0x05f5e100 +MISA: 0x40901106 +XISA: 0xc0000fab +SOC: 0xffff402f +IMEM: 0x00008000 +DMEM: 0x00002000 + +Autoboot in 10s. Press any key to abort. +Aborted. + +Available CMDs: + h: Help + r: Restart + u: Upload + s: Store to flash + l: Load from flash + x: Boot from flash (XIP) + e: Execute +CMD:&gt;</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="6"> +<li> +<p>Execute the "Upload" command by typing <code>u</code>. Now the bootloader is waiting for a binary executable to be send.</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">CMD:&gt; u +Awaiting neorv32_exe.bin...</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="7"> +<li> +<p>Use the "send file" option of your terminal program to send a NEORV32 executable (<code>neorv32_exe.bin</code>).</p> +</li> +<li> +<p>Again, make sure to transmit the executable in raw binary mode (no transfer protocol). +When using TeraTerm, select the "binary" option in the send file dialog.</p> +</li> +<li> +<p>If everything went fine, OK will appear in your terminal:</p> +</li> +</ol> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Make sure to upload the NEORV32 executable <code>neorv32_exe.bin</code>. Uploading any other file (like <code>main.bin</code>) +will cause an <code>ERR_EXE</code> bootloader error (see <a href="https://stnolting.github.io/neorv32/#_bootloader_error_codes" class="bare">https://stnolting.github.io/neorv32/#_bootloader_error_codes</a>). +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">CMD:&gt; u +Awaiting neorv32_exe.bin... OK</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="10"> +<li> +<p>The executable is now in the instruction memory of the processor. To execute the program right +now run the "Execute" command by typing <code>e</code>:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">CMD:&gt; u +Awaiting neorv32_exe.bin... OK +CMD:&gt; e +Booting... +Blinking LED demo program</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="11"> +<li> +<p>If everything went fine, you should see the LEDs blinking.</p> +</li> +</ol> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The bootloader will print error codes if something went wrong. +See section <a href="https://stnolting.github.io/neorv32/#_bootloader">Bootloader</a> of the NEORV32 datasheet for more information. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +See section <a href="#_programming_an_external_spi_flash_via_the_bootloader">Programming an External SPI Flash via the Bootloader</a> to learn how to use an external SPI +flash for nonvolatile program storage. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +Executables can also be uploaded via the <strong>on-chip debugger</strong>. +See section <a href="#_debugging_with_gdb">Debugging with GDB</a> for more information. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_installing_an_executable_directly_into_memory">6. Installing an Executable Directly Into Memory</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>If you do not want to use the bootloader (or the on-chip debugger) for executable upload or if your setup does not provide +a serial interface for that, you can also directly install an application into embedded memory.</p> +</div> +<div class="paragraph"> +<p>This concept uses the "Direct Boot" scenario that implements the processor-internal IMEM as ROM, which is +pre-initialized with the application&#8217;s executable during synthesis. Hence, it provides <em>non-volatile</em> storage of the +executable inside the processor. This storage cannot be altered during runtime and any source code modification of +the application requires to re-program the FPGA via the bitstream.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +See datasheet section <a href="https://stnolting.github.io/neorv32/#_direct_boot">Direct Boot</a> for more information. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>Using the IMEM as ROM:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>for this boot concept the bootloader is no longer required</p> +</li> +<li> +<p>this concept only works for the internal IMEM (but can be extended to work with external memories coupled via the processor&#8217;s bus interface)</p> +</li> +<li> +<p>make sure that the memory components (like block RAM) the IMEM is mapped to support an initialization via the bitstream</p> +</li> +</ul> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>At first, make sure your processor setup actually implements the internal IMEM: the <code>MEM_INT_IMEM_EN</code> generics has to be set to <code>true</code>:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="title">Listing 7. Processor top entity configuration - enable internal IMEM</div> +<div class="content"> +<pre class="highlight"><code class="language-vhdl" data-lang="vhdl"> -- Internal Instruction memory -- + MEM_INT_IMEM_EN =&gt; true, -- implement processor-internal instruction memory</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="2"> +<li> +<p>For this setup we do not want the bootloader to be implemented at all. Disable implementation of the bootloader by setting the +<code>INT_BOOTLOADER_EN</code> generic to <code>false</code>. This will also modify the processor-internal IMEM so it is initialized with the executable during synthesis.</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="title">Listing 8. Processor top entity configuration - disable internal bootloader</div> +<div class="content"> +<pre class="highlight"><code class="language-vhdl" data-lang="vhdl"> -- General -- + INT_BOOTLOADER_EN =&gt; false, -- boot configuration: false = boot from int/ext (I)MEM</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="3"> +<li> +<p>To generate an "initialization image" for the IMEM that contains the actual application, run the <code>install</code> target when compiling your application:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">neorv32/sw/example/demo_blink_led$ make clean_all install +Memory utilization: + text data bss dec hex filename + 1004 0 0 1004 3ec main.elf +Compiling ../../../sw/image_gen/image_gen +Executable (neorv32_exe.bin) size in bytes: +1016 +Installing application image to ../../../rtl/core/neorv32_application_image.vhd</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="4"> +<li> +<p>The <code>install</code> target has compiled all the application sources but instead of creating an executable (<code>neorv32_exe.bit</code>) that can be uploaded via the +bootloader, it has created a VHDL memory initialization image <code>core/neorv32_application_image.vhd</code>.</p> +</li> +<li> +<p>This VHDL file is automatically copied to the core&#8217;s rtl folder (<code>rtl/core</code>) so it will be included for the next synthesis.</p> +</li> +<li> +<p>Perform a new synthesis. The IMEM will be build as pre-initialized ROM (inferring embedded memories if possible).</p> +</li> +<li> +<p>Upload your bitstream. Your application code now resides unchangeable in the processor&#8217;s IMEM and is directly executed after reset.</p> +</li> +</ol> +</div> +<div class="paragraph"> +<p>The synthesis tool / simulator will print asserts to inform about the (IMEM) memory / boot configuration:</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code>NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-internal IMEM). +NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as ROM (1016 bytes), pre-initialized with application.</code></pre> +</div> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_setup_of_a_new_application_program_project">7. Setup of a New Application Program Project</h2> +<div class="sectionbody"> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>The easiest way of creating a <em>new</em> software application project is to copy an <em>existing</em> one. This will keep all +file dependencies. For example you can copy <code>sw/example/demo_blink_led</code> to <code>sw/example/flux_capacitor</code>.</p> +</li> +<li> +<p>If you want to place you application somewhere outside <code>sw/example</code> you need to adapt the application&#8217;s makefile. +In the makefile you will find a variable that keeps the relative or absolute path to the NEORV32 repository home +folder. Just modify this variable according to your new project&#8217;s home location:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-makefile" data-lang="makefile"># Relative or absolute path to the NEORV32 home folder (use default if not set by user) +NEORV32_HOME ?= ../../..</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="3"> +<li> +<p>If your project contains additional source files outside of the project folder, you can add them to +the <code>APP_SRC</code> variable:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-makefile" data-lang="makefile"># User's application sources (add additional files here) +APP_SRC = $(wildcard *.c) ../somewhere/some_file.c</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="4"> +<li> +<p>You also can add a folder containing your application&#8217;s include files to the +<code>APP_INC</code> variable (do not forget the <code>-I</code> prefix):</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-makefile" data-lang="makefile"># User's application include folders (don't forget the '-I' before each entry) +APP_INC = -I . -I ../somewhere/include_stuff_folder</code></pre> +</div> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_application_specific_processor_configuration">8. Application-Specific Processor Configuration</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The processor&#8217;s configuration options, which are mainly defined via the top entity VHDL generics, allow +to tailor the entire SoC according to the application-specific requirements. Note that this chapter does not focus on optional +<em>SoC features</em> like IO/peripheral modules - it rather gives ideas on how to optimize for <em>overall goals</em> +like performance and area.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Please keep in mind that optimizing the design in one direction (like performance) will also effect other potential +optimization goals (like area and energy). +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_optimize_for_performance">8.1. Optimize for Performance</h3> +<div class="paragraph"> +<p>The following points show some concepts to optimize the processor for performance regardless of the costs +(i.e. increasing area and energy requirements):</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Enable all performance-related RISC-V CPU extensions that implement dedicated hardware accelerators instead +of emulating operations entirely in software: <code>M</code>, <code>C</code>, <code>Zfinx</code></p> +</li> +<li> +<p>Enable mapping of compleX CPU operations to dedicated hardware: <code>FAST_MUL_EN &#8658; true</code> to use DSP slices for +multiplications, <code>FAST_SHIFT_EN &#8658; true</code> use a fast barrel shifter for shift operations.</p> +</li> +<li> +<p>Implement the instruction cache: <code>ICACHE_EN &#8658; true</code></p> +</li> +<li> +<p>Use as many <em>internal</em> memory as possible to reduce memory access latency: <code>MEM_INT_IMEM_EN &#8658; true</code> and +<code>MEM_INT_DMEM_EN &#8658; true</code>, maximize <code>MEM_INT_IMEM_SIZE</code> and <code>MEM_INT_DMEM_SIZE</code></p> +</li> +<li> +<p><em>To be continued&#8230;&#8203;</em></p> +</li> +</ul> +</div> +</div> +<div class="sect2"> +<h3 id="_optimize_for_size">8.2. Optimize for Size</h3> +<div class="paragraph"> +<p>The NEORV32 is a size-optimized processor system that is intended to fit into tiny niches within large SoC +designs or to be used a customized microcontroller in really tiny / low-power FPGAs (like Lattice iCE40). +Here are some ideas how to make the processor even smaller while maintaining it&#8217;s <em>general purpose system</em> +concept and maximum RISC-V compatibility.</p> +</div> +<div class="paragraph"> +<p><strong>SoC</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>This is obvious, but exclude all unused optional IO/peripheral modules from synthesis via the processor +configuration generics.</p> +</li> +<li> +<p>If an IO module provides an option to configure the number of "channels", constrain this number to the +actually required value (e.g. the PWM module <code>IO_PWM_NUM_CH</code> or the external interrupt controller <code>XIRQ_NUM_CH</code>).</p> +</li> +<li> +<p>Disable the instruction cache (<code>ICACHE_EN &#8658; false</code>) if the design only uses processor-internal IMEM +and DMEM memories.</p> +</li> +<li> +<p><em>To be continued&#8230;&#8203;</em></p> +</li> +</ul> +</div> +<div class="paragraph"> +<p><strong>CPU</strong></p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Use the <em>embedded</em> RISC-V CPU architecture extension (<code>CPU_EXTENSION_RISCV_E</code>) to reduce block RAM utilization.</p> +</li> +<li> +<p>The compressed instructions extension (<code>CPU_EXTENSION_RISCV_C</code>) requires additional logic for the decoder but +also reduces program code size by approximately 30%.</p> +</li> +<li> +<p>If not explicitly used/required, exclude the CPU standard counters <code>[m]instret[h]</code> +(number of instruction) and <code>[m]cycle[h]</code> (number of cycles) from synthesis by disabling the <code>Zicntr</code> ISA extension +(note, this is not RISC-V compliant).</p> +</li> +<li> +<p>Map CPU shift operations to a small and iterative shifter unit (<code>FAST_SHIFT_EN &#8658; false</code>).</p> +</li> +<li> +<p>If you have unused DSP block available, you can map multiplication operations to those slices instead of +using LUTs to implement the multiplier (<code>FAST_MUL_EN &#8658; true</code>).</p> +</li> +<li> +<p>If there is no need to execute division in hardware, use the <code>Zmmul</code> extension instead of the full-scale +<code>M</code> extension.</p> +</li> +<li> +<p>Disable CPU extension that are not explicitly used.</p> +</li> +<li> +<p><em>To be continued&#8230;&#8203;</em></p> +</li> +</ul> +</div> +</div> +<div class="sect2"> +<h3 id="_optimize_for_clock_speed">8.3. Optimize for Clock Speed</h3> +<div class="paragraph"> +<p>The NEORV32 Processor and CPU are designed to provide minimal logic between register stages to keep the +critical path as short as possible. When enabling additional extension or modules the impact on the existing +logic is also kept at a minimum to prevent timing degrading. If there is a major impact on existing +logic (example: many physical memory protection address configuration registers) the VHDL code automatically +adds additional register stages to maintain critical path length. Obviously, this increases operation latency.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +Enable the "ASIC style" / full-reset register file option (<code>REGFILE_HW_RST</code>) to obtain maximum clock speed for +the CPU (at the cost of an increased hardware footprint). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>In order to optimize for a minimal critical path (= maximum clock speed) the following points should be considered:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Complex CPU extensions (in terms of hardware requirements) should be avoided (examples: floating-point unit, physical memory protection).</p> +</li> +<li> +<p>Large carry chains (&gt;32-bit) should be avoided (i.e. constrain the HPM counter sizes via <code>HPM_CNT_WIDTH</code>).</p> +</li> +<li> +<p>If the target FPGA provides sufficient DSP resources, CPU multiplication operations can be mapped to DSP slices (<code>FAST_MUL_EN &#8658; true</code>) +reducing LUT usage and critical path impact while also increasing overall performance.</p> +</li> +<li> +<p>Use the synchronous (registered) RX path configuration of the external bus interface (<code>XBUS_ASYNC_RX &#8658; false</code>).</p> +</li> +<li> +<p><em>To be continued&#8230;&#8203;</em></p> +</li> +</ul> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The short and fixed-length critical path allows to integrate the core into existing clock domains. +So no clock domain-crossing and no sub-clock generation is required. However, for very high clock +frequencies (this is technology / platform dependent) clock domain crossing becomes crucial for chip-internal +connections. +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_optimize_for_energy">8.4. Optimize for Energy</h3> +<div class="paragraph"> +<p>There are no <em>dedicated</em> configuration options to optimize the processor for energy (minimal consumption; +energy/instruction ratio) yet. However, a reduced processor area (<a href="#_optimize_for_size">Optimize for Size</a>) will also reduce +static energy consumption.</p> +</div> +<div class="paragraph"> +<p>To optimize your setup for low-power applications, you can make use of the CPU sleep mode (<code>wfi</code> instruction). +Put the CPU to sleep mode whenever possible. If the clock gating feature is enabled (<code>CLOCK_GATING_EN</code>) the entire +CPU complex will be disconnected from the clock tree while in sleep mode.</p> +</div> +<div class="paragraph"> +<p>Disable all processor modules that are not actually used (exclude them +from synthesis if they will be <em>never</em> used; disable a module via it&#8217;s control register if the module is not +<em>currently</em> used).</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Processor-internal clock generator shutdown</div> +If <em>no</em> IO/peripheral module is currently enabled, the processor&#8217;s internal clock generator circuit will be +shut down reducing switching activity and thus, dynamic energy consumption. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_adding_custom_hardware_modules">9. Adding Custom Hardware Modules</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>In resemblance to the RISC-V ISA, the NEORV32 processor was designed to ease customization and <em>extensibility</em>. +The processor provides several predefined options to add application-specific custom hardware modules and accelerators. +A <a href="#_comparative_summary">Comparative Summary</a> is given at the end of this section.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Debugging/Testing Custom Hardware Modules</div> +Custom hardware IP modules connected via the external bus interface or integrated as CFU can be debugged "in-system" using the +"bus explorer" example program (<code>sw/example_bus_explorer</code>). This program provides an interactive console (via UART0) +that allows to perform arbitrary read and write access from/to any memory-mapped register. +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_standard_external_interfaces">9.1. Standard (<em>External</em>) Interfaces</h3> +<div class="paragraph"> +<p>The processor already provides a set of standard interfaces that are intended to connect <em>chip-external</em> devices. +However, these interfaces can also be used chip-internally. The most suitable interfaces are +<a href="https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio">GPIO</a>, +<a href="https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0">UART</a>, +<a href="https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi">SPI</a> and +<a href="https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi">TWI</a>.</p> +</div> +<div class="paragraph"> +<p>The SPI and especially the GPIO interfaces might be the most straightforward approaches since they +have a minimal protocol overhead. Device-specific interrupt capabilities could be added using the +<a href="https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq">External Interrupt Controller (XIRQ)</a>.</p> +</div> +<div class="paragraph"> +<p>Beyond simplicity, these interface only provide a very limited bandwidth and require more sophisticated +software handling ("bit-banging" for the GPIO). Hence, it is not recommend to use them for <em>chip-internal</em> communication.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_external_bus_interface">9.2. External Bus Interface</h3> +<div class="paragraph"> +<p>The <a href="https://stnolting.github.io/neorv32/#_processor_external_bus_interface_xbus">External Bus Interface</a> +provides the classic approach for attaching custom IP. By default, the bus interface implements the widely adopted +Wishbone interface standard. This project also includes wrappers to convert to other protocol standards like ARM&#8217;s +AXI4-Lite or Intel&#8217;s Avalon protocols. By using a full-featured bus protocol, complex SoC designs can be implemented +including several modules and even multi-core architectures. Many FPGA EDA tools provide graphical editors to build +and customize whole SoC architectures and even include pre-defined IP libraries.</p> +</div> +<div class="paragraph"> +<p>Custom hardware modules attached to the processor&#8217;s bus interface have no limitations regarding their functionality. +User-defined interfaces (like DDR memory access) can be implemented and the hardware module can operate completely +independent of the CPU.</p> +</div> +<div class="paragraph"> +<p>The bus interface uses a memory-mapped approach. All data transfers are handled by simple load/store operations since the +external bus interface is mapped into the processor&#8217;s <a href="https://stnolting.github.io/neorv32/#_address_space">address space</a>. +This allows a very simple still high-bandwidth communications. However, high bus traffic may increase access latencies.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_custom_functions_subsystem">9.3. Custom Functions Subsystem</h3> +<div class="paragraph"> +<p>The <a href="https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a> is +an "empty" template for a memory-mapped, processor-internal module.</p> +</div> +<div class="paragraph"> +<p>The basic idea of this subsystem is to provide a convenient, simple and flexible platform, where the user can +concentrate on implementing the actual design logic rather than taking care of the communication between the +CPU/software and the design logic. Note that the CFS does not have direct access to memory. All data (and control +instruction) have to be send by the CPU.</p> +</div> +<div class="paragraph"> +<p>The use-cases for the CFS include medium-scale hardware accelerators that need to be tightly-coupled to the CPU. +Potential use cases could be DSP modules like CORDIC, cryptographic accelerators or custom interfaces (like IIS).</p> +</div> +</div> +<div class="sect2"> +<h3 id="_custom_functions_unit">9.4. Custom Functions Unit</h3> +<div class="paragraph"> +<p>The <a href="https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a> is a functional +unit that is integrated right into the CPU&#8217;s pipeline. It allows to implement custom RISC-V instructions. +This extension option is intended for rather small logic that implements operations, which cannot be emulated +in pure software in an efficient way. Since the CFU has direct access to the core&#8217;s register file it can operate +with minimal data latency.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_comparative_summary">9.5. Comparative Summary</h3> +<div class="paragraph"> +<p>The following table gives a comparative summary of the most important factors when choosing one of the +chip-internal extension options:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><a href="https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu">Custom Functions Unit (CFU)</a> for CPU-internal custom RISC-V instructions</p> +</li> +<li> +<p><a href="https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs">Custom Functions Subsystem (CFS)</a> for tightly-coupled processor-internal co-processors</p> +</li> +<li> +<p><a href="https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone">External Bus Interface (WISHBONE)</a> for processor-external memory-mapped modules</p> +</li> +</ul> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 1. Comparison of On-Chip Extension Options</caption> +<colgroup> +<col style="width: 25%;"> +<col style="width: 25%;"> +<col style="width: 25%;"> +<col style="width: 25%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top"></th> +<th class="tableblock halign-center valign-top">Custom Functions Unit (CFU)</th> +<th class="tableblock halign-center valign-top">Custom Functions Subsystem (CFS)</th> +<th class="tableblock halign-center valign-top">External Bus Interface</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>RTL location</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">CPU-internal</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">processor-internal</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">processor-external</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>HW complexity/size</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">small</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">medium</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">large</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>CPU-independent operation</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">yes</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">yes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>CPU interface</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">register file access</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">memory-mapped</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">memory-mapped</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Low-level access mechanism</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">custom instructions</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">load/store</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">load/store</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Access latency</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">minimal</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">low</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">medium to high</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>External IO interfaces</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">not supported</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">yes, but limited</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">yes, user-defined</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Exception capability</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">yes</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>Interrupt capability</strong></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">no</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">yes</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">user-defined</p></td> +</tr> +</tbody> +</table> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_customizing_the_internal_bootloader">10. Customizing the Internal Bootloader</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 bootloader provides several options to configure and customize it for a certain application setup. +This configuration is done by passing <em>defines</em> when compiling the bootloader. Of course you can also +modify to bootloader source code to provide a setup that perfectly fits your needs.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Each time the bootloader sources are modified, the bootloader has to be re-compiled (and re-installed to the +bootloader ROM) and the processor has to be re-synthesized. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Keep in mind that the maximum size for the bootloader is limited to 8kB and it should be compiled using the +minimal base &amp; privileged ISA <code>rv32i_zicsr_zifencei</code> only to ensure it can work independently of the actual CPU configuration. +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 2. Bootloader configuration parameters</caption> +<colgroup> +<col style="width: 18.1818%;"> +<col style="width: 9.0909%;"> +<col style="width: 18.1818%;"> +<col style="width: 54.5455%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-left valign-top">Parameter</th> +<th class="tableblock halign-center valign-top">Default</th> +<th class="tableblock halign-center valign-top">Legal values</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock">Memory layout</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>EXE_BASE_ADDR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>any</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Base address / boot address for the executable (see section "Address Space" in the NEORV32 data sheet)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock">Serial console interface</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>UART_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code>, <code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set to <code>0</code> to disable UART0 (no serial console at all)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>UART_BAUD</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>19200</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>any</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Baud rate of UART0</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>UART_HW_HANDSHAKE_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code>, <code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set to <code>1</code> to enable UART0 hardware flow control</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock">Status LED</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>STATUS_LED_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code>, <code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Enable bootloader status led ("heart beat") at <code>GPIO</code> output port pin #<code>STATUS_LED_PIN</code> when <code>1</code></p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>STATUS_LED_PIN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code> &#8230;&#8203; <code>31</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>GPIO</code> output pin used for the high-active status LED</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock">Auto-boot configuration</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>AUTO_BOOT_TIMEOUT</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>10</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>any</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Time in seconds after the auto-boot sequence starts (if there is no UART input by the user); set to 0 to disabled auto-boot sequence</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock">SPI configuration</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SPI_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>1</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code>, <code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set <code>1</code> to enable the usage of the SPI module (including load/store executables from/to SPI flash options)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SPI_FLASH_CS</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code> &#8230;&#8203; <code>7</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI chip select output (<code>spi_csn_o</code>) for selecting flash</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SPI_FLASH_ADDR_BYTES</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>3</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>2</code>, <code>3</code>, <code>4</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI flash address size in number of bytes (2=16-bit, 3=24-bit, 4=32-bit)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SPI_FLASH_SECTOR_SIZE</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>65536</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>any</em></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI flash sector size in bytes</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SPI_FLASH_CLK_PRSC</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CLK_PRSC_8</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>CLK_PRSC_2</code> <code>CLK_PRSC_4</code> <code>CLK_PRSC_8</code> <code>CLK_PRSC_64</code> <code>CLK_PRSC_128</code> <code>CLK_PRSC_1024</code> <code>CLK_PRSC_2024</code> <code>CLK_PRSC_4096</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">SPI clock pre-scaler (dividing main processor clock)</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>SPI_BOOT_BASE_ADDR</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00400000</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><em>any</em> 32-bit value</p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Defines the <em>base</em> address of the executable in external flash</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock">XIP configuration</p></td> +</tr> +<tr> +<td class="tableblock halign-left valign-top"><p class="tableblock"><code>XIP_EN</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0</code>, <code>1</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">Set <code>1</code> to enable the XIP options</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The XIP options re-use the "SPI configuration" options for configuring the XIP&#8217;s SPI connection. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>Each configuration parameter is implemented as C-language <code>define</code> that can be manually overridden (<em>redefined</em>) when +invoking the bootloader&#8217;s makefile. The according parameter and its new value has to be <em>appended</em> +(using <code>+=</code>) to the makefile <code>USER_FLAGS</code> variable. Make sure to use the <code>-D</code> prefix here.</p> +</div> +<div class="paragraph"> +<p>For example, to configure a UART Baud rate of 57600 and redirecting the status LED to GPIO output pin 20 +use the following command:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 9. Example: customizing, re-compiling and re-installing the bootloader</div> +<div class="content"> +<pre class="highlight"><code class="language-console" data-lang="console">sw/bootloader$ make USER_FLAGS+=-DUART_BAUD=57600 USER_FLAGS+=-DSTATUS_LED_PIN=20 clean_all bootloader</code></pre> +</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The <code>clean_all</code> target ensure that all libraries are re-compiled. The <code>bootloader</code> target will automatically +compile and install the bootloader to the HDL boot ROM (updating <code>rtl/core/neorv32_bootloader_image.vhd</code>). +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_auto_boot_configuration">10.1. Auto-Boot Configuration</h3> +<div class="paragraph"> +<p>The default bootloader provides a UART-based user interface that allows to upload new executables +at any time. Optionally, the executable can also be programmed to an external SPI flash by the bootloader (see +section <a href="#_programming_an_external_spi_flash_via_the_bootloader">Programming an External SPI Flash via the Bootloader</a>).</p> +</div> +<div class="paragraph"> +<p>The bootloader also provides an <em>automatic boot sequence</em> (auto-boot) which will start copying an executable +from external SPI flash to IMEM using the default SPI configuration. By this, the default bootloader +provides a "non-volatile program storage" mechanism that automatically boots from external SPI flash +(after <code>AUTO_BOOT_TIMEOUT</code>) while still providing the option to re-program the SPI flash at any time +via the UART console.</p> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_programming_an_external_spi_flash_via_the_bootloader">11. Programming an External SPI Flash via the Bootloader</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The default processor-internal NEORV32 bootloader supports automatic booting from an external SPI flash. +This guide shows how to write an executable to the SPI flash via the bootloader so it can be automatically +fetched and executed after processor reset. For example, you can use a section of the FPGA bitstream configuration +memory to store an application executable.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Customization</div> +This section assumes the <em>default</em> configuration of the NEORV32 bootloader. +See section <a href="#_customizing_the_internal_bootloader">Customizing the Internal Bootloader</a> on how to customize the bootloader and its setting +(for example the SPI chip-select port, the SPI clock speed or the <strong>flash base address</strong> for storing the executable). +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_programming_an_executable">11.1. Programming an Executable</h3> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>At first, reset the NEORV32 processor and wait until the bootloader start screen appears in your terminal program.</p> +</li> +<li> +<p>Abort the auto boot sequence and start the user console by pressing any key.</p> +</li> +<li> +<p>Press u to upload the executable that you want to store to the external flash:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code>CMD:&gt; u +Awaiting neorv32_exe.bin...</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="4"> +<li> +<p>Send the binary in raw binary via your terminal program. When the upload is completed and "OK" +appears, press <code>s</code> to trigger the programming of the flash (do not execute the image via the <code>e</code> +command as this might corrupt the image):</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code>CMD:&gt; u +Awaiting neorv32_exe.bin... OK +CMD:&gt; s +Write 0x000013FC bytes to SPI flash @ 0x02000000? (y/n)</code></pre> +</div> +</div> +<div class="olist arabic"> +<ol class="arabic" start="5"> +<li> +<p>The bootloader shows the size of the executable and the base address inside the SPI flash where the +executable is going to be stored. A prompt appears: Type <code>y</code> to start the programming or type <code>n</code> to +abort.</p> +</li> +</ol> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +Section <a href="#_customizing_the_internal_bootloader">Customizing the Internal Bootloader</a> show the according C-language <code>define</code> that can be modified +to specify the base address of the executable inside the SPI flash. +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code>CMD:&gt; u +Awaiting neorv32_exe.bin... OK +CMD:&gt; s +Write 0x000013FC bytes to SPI flash @ 0x02000000? (y/n) y +Flashing... OK +CMD:&gt;</code></pre> +</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The bootloader stores the executable in <strong>little-endian</strong> byte-order to the flash. +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="6"> +<li> +<p>If "OK" appears in the terminal line, the programming process was successful. Now you can use the +auto boot sequence to automatically boot your application from the flash at system start-up without +any user interaction.</p> +</li> +</ol> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_packaging_the_processor_as_vivado_ip_block">12. Packaging the Processor as Vivado IP Block</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>Packaging the entire processor as IP module allows easy integration of the core (or even several cores) +into a block-design-based Vivado project. The NEORV32 repository provides a full-scale TCL script that +automatically packages the processor as Vivado IP block. For this, a specialized wrapper for the processor&#8217;s +top entity is provided (<code>rtl/system_integration/neorv32_vivado_ip.vhd</code>) that features AXI4-Lite (via XBUS) +and AXI4-Stream (via SLINK) compatible interfaces.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">General AXI Wrapper</div> +The provided AXI wrapper can also be used for custom (AXI) setups outside of Vivado and/or IP block designs. +</td> +</tr> +</table> +</div> +<div class="imageblock"> +<div class="content"> +<img src="../img/vivado_ip_soc.png" alt="vivado ip soc"> +</div> +<div class="title">Figure 2. Example Vivado SoC using the NEORV32 IP Block</div> +</div> +<div class="paragraph"> +<p>Besides packaging the HDL modules, the TCL script also generates a simplified customization GUI that allows an easy +and intuitive configuration of the processor. The rather complex VHDL configuration generics are renamed and provided +with tool tips to make it easier to understand the different configuration options.</p> +</div> +<div class="imageblock"> +<div class="content"> +<img src="../img/vivado_ip_gui.png" alt="vivado ip gui"> +</div> +<div class="title">Figure 3. NEORV32 IP Customization GUI</div> +</div> +<div class="paragraph"> +<p>The following steps show how to package the processor using the provided TCL script and how to import +the generated IP block into the Vivado IP repository.</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Open the Vivado GUI.</p> +</li> +<li> +<p>In GUI mode select either "Tools &#8594; Run TCL Script" to directly execute the script or open the TCL +shell ("Window &#8594; Tcl Console") to manually invoke the script.</p> +</li> +<li> +<p>Use <code>cd</code> in the TCL console to navigate to the project&#8217;s <code>neorv32/rtl/system_integration</code> folder.</p> +</li> +<li> +<p>Execute <code>source neorv32_vivado_ip.tcl</code> in the TCL console.</p> +</li> +<li> +<p>A second Vivado instance will open automatically packaging the IP module. After this process is completed, +the second Vivado instance will automatically close again.</p> +</li> +<li> +<p>A new folder <code>neorv32_vivado_ip_work</code> is created in <code>neorv32/rtl/system_integration</code> which contains the IP-packaging +Vivado project.</p> +</li> +<li> +<p>Inside, the <code>packaged_ip</code> folder provides the actual IP module.</p> +</li> +<li> +<p>Open your design project in Vivado.</p> +</li> +<li> +<p>Click on "Settings" in the "Project Manager" on the left side.</p> +</li> +<li> +<p>Under "Project Settings" expand the "IP" section and click on "Repository".</p> +</li> +<li> +<p>Click the large plus button and select the previously generated IP folder (<code>path/to/neorv32/rtl/system_integration/neorv32_vivado_ip_work/packaged_ip</code>).</p> +</li> +<li> +<p>Click "Select" and close the Settings menu with "Apply" and "OK".</p> +</li> +<li> +<p>You will find the NEORV32 in the "User Repository" section of the Vivado IP catalog.</p> +</li> +</ol> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">Combinatorial Loops DRC Errors</div> +If the TRNG is enabled it is recommended to add the following commands to the project&#8217;s constraints file in order +to prevent DRC errors during bitstream generation: +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-xdc" data-lang="xdc">set_property SEVERITY {warning} [get_drc_checks LUTLP-1] +set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1] +set_property ALLOW_COMBINATORIAL_LOOPS TRUE</code></pre> +</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Re-Packaging the IP Core</div> +For every change that is made right to the hardware (excluding configuration made via the customization GUI!) +the NEORV32 IP module needs to be re-packaged by re-executing the packing script (<code>neorv32_vivado_ip.tcl</code>).<br> +<br> +This also applies if an executable installed right into the IMEM (see section <a href="#_installing_an_executable_directly_into_memory">Installing an Executable Directly Into Memory</a>) +shall be updated. It is <strong>not</strong> not possible to replace the IMEM image (<code>neorv32_application_image.vhd</code>) file +in the packaged_ip folder. For the Vivado design suite, the new program to be executed must be compiled and installed using the +<code>install</code> makefile target. Next, the <code>neorv32_vivado_ip.tcl</code> script has to be executed again. Finally, Vivado will prompt to upgrade +the NEORV32 IP. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_simulating_the_processor">13. Simulating the Processor</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 project includes a core CPU, built-in peripherals in the Processor Subsystem, and additional peripherals in +the templates and examples. +Therefore, there is a wide range of possible testing and verification strategies.</p> +</div> +<div class="paragraph"> +<p>On the one hand, a simple smoke testbench allows ensuring that functionality is correct from a software point of view. +That is used for running the RISC-V architecture tests, in order to guarantee compliance with the ISA specification(s).</p> +</div> +<div class="paragraph"> +<p>On the other hand, <a href="http://vunit.github.io/">VUnit</a> and <a href="http://vunit.github.io/verification_components/user_guide.html">Verification Components</a> +are used for verifying the functionality of the various peripherals from a hardware point of view.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">AMD Vivado / ISIM</div> +When using AMD Vivado (ISIM for simulation) make sure to <strong>turn of</strong> "incremental compilation" (<em>Project Setting</em> +&#8594; <em>Simulation</em> &#8594; <em>Advanced</em> &#8594; _Enable incremental compilation). This will slow down simulation relaunch but will +ensure that all application images (<code>*_image.vhd</code>) are reanalyzed when recompiling the NEORV32 application or bootloader +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +The processor can check if it is being <em>simulated</em> by checking the SYSINFO <em>SYSINFO_SOC_IS_SIM</em> flag +(see <a href="https://stnolting.github.io/neorv32/#_system_configuration_information_memory_sysinfo" class="bare">https://stnolting.github.io/neorv32/#_system_configuration_information_memory_sysinfo</a>). +Note that this flag is not guaranteed to be set correctly (depending on the HDL toolchain&#8217;s pragma support). +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_testbench">13.1. Testbench</h3> +<div class="paragraph"> +<p>A plain-VHDL (no third-party libraries) testbench (<code>sim/simple/neorv32_tb.simple.vhd</code>) can be used for simulating and +testing the processor. +This testbench features a 100MHz clock and enables all optional peripheral and CPU extensions except for the <code>E</code>.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +In the simple testbench several optional extensions are disabled, such as C or E. +If software is compiled using instructions corresponding to disabled extensions, the whole processor will hang in an eternal exception loop and, therefore, the simulation will timeout. +The <code>MARCH</code> must be a subset of the extensions enabled in the testbench. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">True Random Number Generator</div> +The NEORV32 TRNG will be set to "simulation mode" when enabled for simulation (replacing the ring-oscillators +by pseudo-random LFSRs). See the neoTRNG documentation for more information. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The simulation setup is configured via the "User Configuration" section located right at the beginning of +the testbench&#8217;s architecture. Each configuration constant provides comments to explain the functionality.</p> +</div> +<div class="paragraph"> +<p>Besides the actual NEORV32 Processor, the testbench also simulates "external" components that are connected +to the processor&#8217;s external bus/memory interface. These components are:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>an external instruction memory (that also allows booting from it)</p> +</li> +<li> +<p>an external data memory</p> +</li> +<li> +<p>an external memory to simulate "external IO devices"</p> +</li> +<li> +<p>a memory-mapped registers to trigger the processor&#8217;s interrupt signals</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>The following table shows the base addresses of these four components and their default configuration and +properties:</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="paragraph"> +<p>Attributes:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>r</code> = read</p> +</li> +<li> +<p><code>w</code> = write</p> +</li> +<li> +<p><code>e</code> = execute</p> +</li> +<li> +<p><code>8</code> = byte-accessible</p> +</li> +<li> +<p><code>16</code> = half-word-accessible</p> +</li> +<li> +<p><code>32</code> = word-accessible</p> +</li> +</ul> +</div> +</td> +</tr> +</table> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 3. Testbench: processor-external memories</caption> +<colgroup> +<col style="width: 17.3913%;"> +<col style="width: 13.0434%;"> +<col style="width: 21.7391%;"> +<col style="width: 47.8262%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">Base address</th> +<th class="tableblock halign-right valign-top">Size</th> +<th class="tableblock halign-center valign-top">Attributes</th> +<th class="tableblock halign-left valign-top">Description</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x00000000</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>imem_size_c</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>r/w/e 8/16/32</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">external IMEM (initialized with application image)</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0x80000000</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock"><code>dmem_size_c</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>r/w/e 8/16/32</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">external DMEM</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xf0000000</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">64 bytes</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>r/w/e 8/16/32</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">external "IO" memory</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>0xff000000</code></p></td> +<td class="tableblock halign-right valign-top"><p class="tableblock">4 bytes</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>-/w/- -/-/32</code></p></td> +<td class="tableblock halign-left valign-top"><p class="tableblock">memory-mapped register to trigger "machine external", "machine software" and "SoC Fast Interrupt" interrupts</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +The simulated NEORV32 does not use the bootloader and <em>directly boots</em> the current application image (from +the <code>rtl/core/neorv32_application_image.vhd</code> image file). +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">UART output during simulation</div> +Data written to the NEORV32 UART0 / UART1 transmitter is send to a virtual UART receiver implemented +as part of the testbench. Received chars are send to the simulator console and are also stored to a log file +(<code>neorv32.testbench_uart0.out</code> for UART0, <code>neorv32.testbench_uart1.out</code> for UART1) inside the simulation&#8217;s home folder. +<strong>Please note that printing via the native UART receiver takes a lot of time.</strong> For faster simulation console output +see section <a href="#_faster_simulation_console_output">Faster Simulation Console Output</a>. +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_faster_simulation_console_output">13.2. Faster Simulation Console Output</h3> +<div class="paragraph"> +<p>When printing data via the physical UART the communication speed will always be based on the configured BAUD +rate. For a simulation this might take some time. To have faster output you can enable the <strong>simulation mode</strong> +for UART0/UART1 (see section <a href="https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0">Documentation: Primary Universal Asynchronous Receiver and Transmitter (UART0)</a>).</p> +</div> +<div class="paragraph"> +<p>ASCII data sent to UART0|UART1 will be immediately printed to the simulator console and logged to files in the simulator +execution directory:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p><code>neorv32.uart?.sim_mode.text.out</code>: ASCII data.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>You can "automatically" enable the simulation mode of UART0/UART1 when compiling an application. +In this case, the "real" UART0/UART1 transmitter unit is permanently disabled. +To enable the simulation mode just compile and install your application and add <em>UART?_SIM_MODE</em> to the compiler&#8217;s +<em>USER_FLAGS</em> variable (do not forget the <code>-D</code> suffix flag):</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">sw/example/demo_blink_led$ make USER_FLAGS+=-DUART0_SIM_MODE clean_all all</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The provided define will change the default UART0/UART1 setup function in order to set the simulation +mode flag in the according UART&#8217;s control register.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The UART simulation output (to file and to screen) outputs "complete lines" at once. A line is +completed with a line feed (newline, ASCII <code>\n</code> = 10). +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_simulation_using_a_shell_script_with_ghdl">13.3. Simulation using a shell script (with GHDL)</h3> +<div class="paragraph"> +<p>To simulate the processor using <em>GHDL</em> navigate to the <code>sim/simple/</code> folder and run the provided shell script. +Any arguments that are provided while executing this script are passed to GHDL. +For example the simulation time can be set to 20ms using <code>--stop-time=20ms</code> as argument.</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">neorv32/sim/simple$ sh ghdl.sh --stop-time=20ms</code></pre> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_simulation_using_application_makefiles_in_console_with_ghdl">13.4. Simulation using Application Makefiles (In-Console with GHDL)</h3> +<div class="paragraph"> +<p>To directly compile and run a program in the console (using the default testbench and GHDL +as simulator) you can use the <code>sim</code> makefile target. Make sure to use the UART simulation mode +(<code>USER_FLAGS+=-DUART0_SIM_MODE</code> and/or <code>USER_FLAGS+=-DUART1_SIM_MODE</code>) to get +faster / direct-to-console UART output.</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">sw/example/demo_blink_led$ make USER_FLAGS+=-DUART0_SIM_MODE clean_all sim +[...] +Blinking LED demo program</code></pre> +</div> +</div> +<div class="sect3"> +<h4 id="_hello_world">13.4.1. Hello World!</h4> +<div class="paragraph"> +<p>To do a quick test of the NEORV32 make sure to have <a href="https://github.com/ghdl/ghdl">GHDL</a> and a +<a href="https://github.com/stnolting/riscv-gcc-prebuilt">RISC-V gcc toolchain</a> installed. +Navigate to the project&#8217;s <code>sw/example/hello_world</code> folder and run <code>make USER_FLAGS+=-DUART0_SIM_MODE clean_all sim</code>:</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +The simulator will output some <em>sanity check</em> notes (and warnings or even errors if something is ill-configured) +right at the beginning of the simulation to give a brief overview of the actual NEORV32 SoC and CPU configurations. +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">neorv32/sw/example/hello_world$ make USER_FLAGS+=-DUART0_SIM_MODE clean_all sim +../../../sw/lib/source/neorv32_uart.c: In function 'neorv32_uart_setup': +../../../sw/lib/source/neorv32_uart.c:116:2: warning: #warning UART0_SIM_MODE (primary UART) enabled! Sending all UART0.TX data to text.io simulation output instead of real UART0 transmitter. Use this for simulations only! [-Wcpp] + 116 | #warning UART0_SIM_MODE (primary UART) enabled! Sending all UART0.TX data to text.io simulation output instead of real UART0 transmitter. Use this for simulations only! <i class="conum" data-value="1"></i><b>(1)</b> + | ^~~~~~~ +Memory utilization: + text data bss dec hex filename + 4664 0 116 4780 12ac main.elf <i class="conum" data-value="2"></i><b>(2)</b> +Compiling ../../../sw/image_gen/image_gen +Installing application image to ../../../rtl/core/neorv32_application_image.vhd <i class="conum" data-value="3"></i><b>(3)</b> +Simulating neorv32_application_image.vhd... +Tip: Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to auto-enable UART[0/1]'s simulation mode (redirect UART output to simulator console). <i class="conum" data-value="4"></i><b>(4)</b> +Using simulation run arguments: --stop-time=10ms <i class="conum" data-value="5"></i><b>(5)</b> +../../rtl/core/neorv32_top.vhd:355:5:@0ms:(assertion note): [NEORV32] The NEORV32 RISC-V Processor (version 0x01090504), github.com/stnolting/neorv32 <i class="conum" data-value="6"></i><b>(6)</b> +../../rtl/core/neorv32_top.vhd:361:5:@0ms:(assertion note): [NEORV32] Processor Configuration: IMEM DMEM I-CACHE D-CACHE WISHBONE GPIO MTIME UART0 UART1 SPI SDI TWI PWM WDT TRNG CFS NEOLED XIRQ GPTMR XIP ONEWIRE DMA SLINK CRC SYSINFO OCD +../../rtl/core/neorv32_clockgate.vhd:60:3:@0ms:(assertion warning): [NEORV32] Clock gating enabled (using generic clock switch). +../../rtl/core/neorv32_cpu.vhd:142:3:@0ms:(assertion note): [NEORV32] CPU ISA: rv32imabu_zicsr_zicntr_zicond_zifencei_zfinx_zihpm_zxcfu_sdext_sdtrig_smpmp +../../rtl/core/neorv32_cpu.vhd:163:3:@0ms:(assertion note): [NEORV32] CPU tuning options: fast_mul fast_shift +../../rtl/core/neorv32_cpu.vhd:170:3:@0ms:(assertion warning): [NEORV32] Assuming this is a simulation. +../../rtl/core/neorv32_cpu_cp_fpu.vhd:292:3:@0ms:(assertion warning): [NEORV32] The floating-point unit (Zfinx) is still in experimental state. +../../rtl/core/mem/neorv32_imem.legacy.vhd:72:3:@0ms:(assertion note): [NEORV32] Implementing LEGACY processor-internal IMEM as pre-initialized ROM. +../../rtl/core/neorv32_wishbone.vhd:117:3:@0ms:(assertion note): [NEORV32] Ext. Bus Interface (WISHBONE) - PIPELINED Wishbone protocol, auto-timeout, LITTLE-endian byte order, registered RX, registered TX +../../rtl/core/neorv32_trng.vhd:343:3:@0ms:(assertion note): [neoTRNG NOTE] &lt;&lt; neoTRNG V3 - A Tiny and Platform-Independent True Random Number Generator &gt;&gt; +../../rtl/core/neorv32_trng.vhd:545:5:@0ms:(assertion warning): [neoTRNG WARNING] Implementing non-physical pseudo-RNG! +../../rtl/core/neorv32_trng.vhd:545:5:@0ms:(assertion warning): [neoTRNG WARNING] Implementing non-physical pseudo-RNG! +../../rtl/core/neorv32_trng.vhd:545:5:@0ms:(assertion warning): [neoTRNG WARNING] Implementing non-physical pseudo-RNG! +../../rtl/core/neorv32_debug_dm.vhd:227:3:@0ms:(assertion note): [NEORV32] OCD DM compatible to debug spec. version 1.0 +<i class="conum" data-value="7"></i><b>(7)</b> + ## ## ## ## + ## ## ######### ######## ######## ## ## ######## ######## ## ################ +#### ## ## ## ## ## ## ## ## ## ## ## ## ## #### #### +## ## ## ## ## ## ## ## ## ## ## ## ## ## ###### ## +## ## ## ######### ## ## ######### ## ## ##### ## ## #### ###### #### +## ## ## ## ## ## ## ## ## ## ## ## ## ## ###### ## +## #### ## ## ## ## ## ## ## ## ## ## ## #### #### +## ## ######### ######## ## ## ## ######## ########## ## ################ + ## ## ## ## +Hello world! :)</code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td>Notifier that "simulation mode" of UART0 is enabled (by the <code>USER_FLAGS+=-DUART0_SIM_MODE</code> makefile flag). All UART0 output is send to the simulator console.</td> +</tr> +<tr> +<td><i class="conum" data-value="2"></i><b>2</b></td> +<td>Final executable size (<code>text</code>) and <em>static</em> data memory requirements (<code>data</code>, <code>bss</code>).</td> +</tr> +<tr> +<td><i class="conum" data-value="3"></i><b>3</b></td> +<td>The application code is <em>installed</em> as pre-initialized IMEM. This is the default approach for simulation.</td> +</tr> +<tr> +<td><i class="conum" data-value="4"></i><b>4</b></td> +<td>A note regarding UART "simulation mode", but we have already enabled that.</td> +</tr> +<tr> +<td><i class="conum" data-value="5"></i><b>5</b></td> +<td>List of (default) arguments that were send to the simulator. Here: maximum simulation time (10ms).</td> +</tr> +<tr> +<td><i class="conum" data-value="6"></i><b>6</b></td> +<td>"Sanity checks" from the core&#8217;s VHDL files. These reports give some brief information about the SoC/CPU configuration (&#8594; generics). If there are problems with the current configuration, an ERROR will appear.</td> +</tr> +<tr> +<td><i class="conum" data-value="7"></i><b>7</b></td> +<td>Execution of the actual program starts.</td> +</tr> +</table> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_advanced_simulation_using_vunit">13.5. Advanced Simulation using VUnit</h3> +<div class="paragraph"> +<p><a href="https://vunit.github.io/">VUnit</a> is an open source unit testing framework for VHDL/SystemVerilog. +It allows continuous and automated testing of HDL code by complementing traditional testing methodologies. +The motto of VUnit is <em>"testing early and often"</em> through automation.</p> +</div> +<div class="paragraph"> +<p>VUnit is composed by a <a href="http://vunit.github.io/py/ui.html">Python interface</a> and multiple optional +<a href="http://vunit.github.io/vhdl_libraries.html">VHDL libraries</a>. +The Python interface allows declaring sources and simulation options, and it handles the compilation, execution and +gathering of the results regardless of the simulator used. +That allows having a single <code>run.py</code> script to be used with GHDL, ModelSim/QuestaSim, Riviera PRO, etc. +On the other hand, the VUnit&#8217;s VHDL libraries provide utilities for assertions, logging, having virtual queues, handling CSV files, etc. +The <a href="http://vunit.github.io/verification_components/user_guide.html">Verification Component Library</a> uses those features +for abstracting away bit-toggling when verifying standard interfaces such as Wishbone, AXI, Avalon, UARTs, etc.</p> +</div> +<div class="paragraph"> +<p>Testbench sources in <code>sim</code> (such as <code>sim/neorv32_tb.vhd</code> and <code>sim/uart_rx*.vhd</code>) use VUnit&#8217;s VHDL libraries for testing +NEORV32 and peripherals. +The entry-point for executing the tests is <code>sim/run.py</code>.</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash"># ./sim/run.py -l +neorv32.neorv32_tb.all +Listed 1 tests + +# ./sim/run.py -v +Compiling into neorv32: rtl/core/neorv32_uart.vhd passed +Compiling into neorv32: rtl/core/neorv32_twi.vhd passed +Compiling into neorv32: rtl/core/neorv32_trng.vhd passed +...</code></pre> +</div> +</div> +<div class="paragraph"> +<p>See <a href="http://vunit.github.io/user_guide.html">VUnit: User Guide</a> and <a href="http://vunit.github.io/cli.html">VUnit: Command Line Interface</a> for further info about VUnit&#8217;s features.</p> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_vhdl_development_environment">14. VHDL Development Environment</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>To navigate and develop the NEORV32 processor VHDL code you can use the free and open source VHDL-LS language server. +The easiest way to get started is to install the <a href="https://marketplace.visualstudio.com/items?itemName=hbohlin.vhdl-ls">VHDL-LS VSCode extension</a>. +The VHDL-LS server requires a <code>vhdl_ls.toml</code> file which is automatically generated by the <code>sim/run.py</code> script. See <a href="#_simulating_the_processor">Simulate the processor</a> for further information.</p> +</div> +<div class="olist arabic"> +<ol class="arabic"> +<li> +<p>Run <code>sim/run.py</code> to create the library mapping file</p> +</li> +<li> +<p>Install the VHDL-LS VSCode extension</p> +</li> +<li> +<p>Open the root folder of the NEORV32 repository in VSCode</p> +</li> +<li> +<p>Open any VHDL file</p> +</li> +</ol> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_building_the_documentation">15. Building the Documentation</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The documentation (datasheet + user guide) is written using <code>asciidoc</code>. The according source files +can be found in <code>docs/&#8230;&#8203;</code>. The documentation of the software framework is written <em>in-code</em> using <code>doxygen</code>.</p> +</div> +<div class="paragraph"> +<p>A makefiles in the project&#8217;s <code>docs</code> directory is provided to build all of the documentation as HTML pages +or as PDF documents.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +Pre-rendered PDFs are available online as <em>nightly pre-releases</em>: <a href="https://github.com/stnolting/neorv32/releases" class="bare">https://github.com/stnolting/neorv32/releases</a>. +The HTML-based documentation is also available online at the project&#8217;s <a href="https://stnolting.github.io/neorv32/">GitHub Pages</a>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>The makefile provides a help target to show all available build options and their according outputs.</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">neorv32/docs$ make help</code></pre> +</div> +</div> +<div class="listingblock"> +<div class="title">Listing 10. Example: Generate HTML documentation (data sheet) using <code>asciidoctor</code></div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">neorv32/docs$ make html</code></pre> +</div> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +If you don&#8217;t have <code>asciidoctor</code> / <code>asciidoctor-pdf</code> installed, you can still generate all the documentation using +a <em>docker container</em> via <code>make container</code>. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_zephyr_rtos_support">16. Zephyr RTOS Support</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 processor is supported by upstream Zephyr RTOS: <a href="https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html" class="bare">https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html</a></p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +The absolute path to the NEORV32 executable image generator binary (<code>&#8230;&#8203;/neorv32/sw/image_gen</code>) has to be added to the <code>PATH</code> variable +so the Zephyr build system can generate executables and memory-initialization images. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +Zephyr OS port provided by GitHub user <a href="https://github.com/henrikbrixandersen">henrikbrixandersen</a> +(see <a href="https://github.com/stnolting/neorv32/discussions/172" class="bare">https://github.com/stnolting/neorv32/discussions/172</a>). โค๏ธ +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_freertos_support">17. FreeRTOS Support</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>A NEORV32-specific port and a simple demo for FreeRTOS (<a href="https://github.com/FreeRTOS/FreeRTOS" class="bare">https://github.com/FreeRTOS/FreeRTOS</a>) are +available in a separate repository on GitHub: <a href="https://github.com/stnolting/neorv32-freertos" class="bare">https://github.com/stnolting/neorv32-freertos</a></p> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_litex_soc_builder_support">18. LiteX SoC Builder Support</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p><a href="https://github.com/enjoy-digital/litex">LiteX</a> is a SoC builder framework by <a href="https://github.com/enjoy-digital">Enjoy-Digital</a> +that allows easy creation of complete system-on-chip designs - including sophisticated interfaces like Ethernet, serial ATA +and DDR memory controller. The NEORV32 has been ported to the LiteX framework to be used as central processing unit.</p> +</div> +<div class="paragraph"> +<p>The default microcontroller-like NEORV32 processor is not directly supported as all the peripherals would provide some <em>redundancy</em>. +Instead, the LiteX port uses a <em>core complex wrapper</em> that only includes the actual NEORV32 CPU, the instruction cache (optional), +the RISC-V machine system timer (optional), the on-chip debugger (optional) and the internal bus infrastructure. +The specific implementation of optional modules as well as RISC-V ISA configuration and performance optimization options are +controlled by a single <em>CONFIGURATION</em> option wrapped in the LiteX build flow. The external bus interface is used to connect to +other LiteX SoC parts.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Core Complex Wrapper</div> +The NEORV32 core complex wrapper used by LiteX for integration can be found in +<code>rtl/system_integration/neorv32_litex_core_complex.vhd</code>. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">LiteX NEORV32 Documentation</div> +More information can be found in the "NEORV32" section of the LiteX project wiki: <a href="https://github.com/enjoy-digital/litex/wiki/CPUs" class="bare">https://github.com/enjoy-digital/litex/wiki/CPUs</a> +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Work-In-Progress ๐Ÿšง</div> +UG: synthesis - how to create a whole NEORV32 + LiteX SoC for a FPGA<br> +LiteX: debugger - the NEORV32 on-chip-debugger is not supported by the LiteX port yet<br> +LiteX: external interrupt - the "RISC-V machine external interrupt" is not supported by the LiteX port yet +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_litex_setup">18.1. LiteX Setup</h3> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Install LiteX and the RISC-V compiler following the excellent quick start guide: <a href="https://github.com/enjoy-digital/litex/wiki#quick-start-guide" class="bare">https://github.com/enjoy-digital/litex/wiki#quick-start-guide</a></p> +</li> +<li> +<p>The NEORV32 port for LiteX uses GHDL and yosys for converting the VHDL files via the <a href="https://github.com/ghdl/ghdl-yosys-plugin">GHDL-yosys-plugin</a>. +You can download prebuilt packages for example from <a href="https://github.com/YosysHQ/fpga-toolchain" class="bare">https://github.com/YosysHQ/fpga-toolchain</a>, which is _no longer maintained. It is superdesed +by <a href="https://github.com/YosysHQ/fpga-toolchain" class="bare">https://github.com/YosysHQ/fpga-toolchain</a>.</p> +</li> +<li> +<p><em>EXPERIMENTAL:</em> GHDL provides a <a href="https://ghdl.github.io/ghdl/using/Synthesis.html">synthesis options</a>, which converts a VHDL setup into a plain-Verilog +module (not tested on LiteX yet). Check out <a href="https://github.com/stnolting/neorv32-verilog">neorv32-verilog</a> for more information.</p> +</li> +</ol> +</div> +<div class="admonitionblock warning"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-warning" title="Warning"></i> +</td> +<td class="content"> +<div class="title">GHDL-yosys Plugin</div> +If you would like to use the experimental GHDL Yosys plugin for VHDL on Linux or MacOS, you will need to set +the <code>GHDL_PREFIX</code> environment variable. e.g. <code>export GHDL_PREFIX=&lt;install_dir&gt;/fpga-toolchain/lib/ghdl</code>. +On Windows this is not necessary.<br> +<br> +If you are using an existing Makefile set up for ghdl-yosys-plugin and see ERROR: This version of yosys +is built without plugin support you probably need to remove <code>-m ghdl</code> from your yosys parameters. This is +because the plugin is typically loaded from a separate file but it is provided built into yosys in this +package.<br> +- from <a href="https://github.com/YosysHQ/fpga-toolchain" class="bare">https://github.com/YosysHQ/fpga-toolchain</a><br> +<br> +<strong>This means you might have to edit the call to yosys in <code>litex/soc/cores/cpu/neorv32/core.py</code>.</strong> +</td> +</tr> +</table> +</div> +<div class="olist arabic"> +<ol class="arabic" start="3"> +<li> +<p>Add the <code>bin</code> folder of the ghdl-yosys-plugin to your <code>PATH</code> environment variable. You can test your yosys installation +and check for the GHDL plugin:</p> +</li> +</ol> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">$ yosys -H + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf &lt;claire@yosyshq.com&gt; | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.10+12 (open-tool-forge build) (git sha1 356ec7bb, gcc 9.3.0-17ubuntu1~20.04 -Os) + + +-- Running command `help' -- + + ... <i class="conum" data-value="1"></i><b>(1)</b> + ghdl load VHDL designs using GHDL <i class="conum" data-value="2"></i><b>(2)</b> + ...</code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td>A long list of plugins&#8230;&#8203;</td> +</tr> +<tr> +<td><i class="conum" data-value="2"></i><b>2</b></td> +<td>This is the plugin we need.</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_litex_simulation">18.2. LiteX Simulation</h3> +<div class="paragraph"> +<p>Start a simulation right in your console using the NEORV32 as target CPU:</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">$ litex_sim --cpu-type=neorv32</code></pre> +</div> +</div> +<div class="paragraph"> +<p>LiteX will start running its BIOS:</p> +</div> +<div class="listingblock"> +<div class="content"> +<pre class="highlight"><code> __ _ __ _ __ + / / (_) /____ | |/_/ + / /__/ / __/ -_)&gt; &lt; + /____/_/\__/\__/_/|_| + Build your hardware, easily! + + (c) Copyright 2012-2022 Enjoy-Digital + (c) Copyright 2007-2015 M-Labs + + BIOS built on Jul 19 2022 12:21:36 + BIOS CRC passed (6f76f1e8) + + LiteX git sha1: 0654279a + +--=============== SoC ==================-- +CPU: NEORV32-standard @ 1MHz +BUS: WISHBONE 32-bit @ 4GiB +CSR: 32-bit data +ROM: 128KiB +SRAM: 8KiB + + +--============== Boot ==================-- +Booting from serial... +Press Q or ESC to abort boot completely. +sL5DdSMmkekro +Timeout +No boot medium found + +--============= Console ================-- + +litex&gt; help + +LiteX BIOS, available commands: + +flush_cpu_dcache - Flush CPU data cache +crc - Compute CRC32 of a part of the address space +ident - Identifier of the system +help - Print this help + +serialboot - Boot from Serial (SFL) +reboot - Reboot +boot - Boot from Memory + +mem_cmp - Compare memory content +mem_speed - Test memory speed +mem_test - Test memory access +mem_copy - Copy address space +mem_write - Write address space +mem_read - Read address space +mem_list - List available memory regions + + +litex&gt;</code></pre> +</div> +</div> +<div class="paragraph"> +<p>You can use the provided console to execute LiteX commands.</p> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_debugging_using_the_on_chip_debugger">19. Debugging using the On-Chip Debugger</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>The NEORV32 on-chip debugger ("OCD") allows <em>online</em> in-system debugging via an external JTAG access port from a +host machine. The general flow is independent of the host machine&#8217;s operating system. However, this tutorial uses +Windows and Linux (Ubuntu on Windows / WSL) in parallel running the upstream version of OpenOCD and the +RISC-V <em>GNU debugger</em> <code>gdb</code>.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">TLDR</div> +You can start a pre-configured debug session (using default <code>main.elf</code> as executable and +<code>target extended-remote localhost:3333</code> as GDB connection configuration) by using the <strong>GDB</strong> makefile target +(i.e. <code>make gdb</code>). +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">OCD Hardware Implementation</div> +See datasheet section <a href="https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd">On Chip Debugger (OCD)</a> +for more information regarding the actual hardware. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">OCD CPU Requirements</div> +The on-chip debugger is only implemented if the <em>ON_CHIP_DEBUGGER_EN</em> generic is set <em>true</em>. Furthermore, it requires +the <code>Zicsr</code> and <code>Zifencei</code> CPU extension, which are always enabled by the CPU. +</td> +</tr> +</table> +</div> +<div class="sect2"> +<h3 id="_hardware_requirements">19.1. Hardware Requirements</h3> +<div class="paragraph"> +<p>Make sure the on-chip debugger of your NEORV32 setup is implemented (<code>ON_CHIP_DEBUGGER_EN</code> generic = true). This +tutorial uses <code>gdb</code> to <strong>directly upload an executable</strong> to the processor. If you are using the default +processor setup <em>with</em> internal instruction memory (IMEM) make sure it is implemented as RAM +(<code>INT_BOOTLOADER_EN</code> generic = true).</p> +</div> +<div class="paragraph"> +<p>Connect a JTAG adapter to the NEORV32 <code>jtag_*</code> interface signals. If you do not have a full-scale JTAG adapter, you can +also use a FTDI-based adapter like the "FT2232H-56Q Mini Module", which is a simple and inexpensive FTDI breakout board.</p> +</div> +<table class="tableblock frame-all grid-rows stretch"> +<caption class="title">Table 4. JTAG pin mapping</caption> +<colgroup> +<col style="width: 42.8571%;"> +<col style="width: 28.5714%;"> +<col style="width: 28.5715%;"> +</colgroup> +<thead> +<tr> +<th class="tableblock halign-center valign-top">NEORV32 top signal</th> +<th class="tableblock halign-center valign-top">JTAG signal</th> +<th class="tableblock halign-center valign-top">Default FTDI port</th> +</tr> +</thead> +<tbody> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>jtag_tck_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">TCK</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">D0</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>jtag_tdi_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">TDI</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">D1</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>jtag_tdo_o</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">TDO</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">D2</p></td> +</tr> +<tr> +<td class="tableblock halign-center valign-top"><p class="tableblock"><code>jtag_tms_i</code></p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">TMS</p></td> +<td class="tableblock halign-center valign-top"><p class="tableblock">D3</p></td> +</tr> +</tbody> +</table> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">JTAG TAP Reset</div> +The NEORV32 JTAG TAP does not provide a dedicated reset signal ("TRST"). However, the missing TRST is not a problem, +since JTAG-level resets can be triggered using with TMS signaling. +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_openocd">19.2. OpenOCD</h3> +<div class="paragraph"> +<p>The NEORV32 on-chip debugger can be accessed using the upstream version of OpenOCD. A pre-configured OpenOCD configuration +file is provided (<code>sw/openocd/openocd_neorv32.cfg</code>) that allows an easy access to the NEORV32 CPU.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +You might need to adapt <code>ftdi vid_pid</code>, <code>ftdi channel</code> and <code>ftdi layout_init</code> in <code>sw/openocd/openocd_neorv32.cfg</code> +according to your interface chip and your operating system. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +If you want to modify the JTAG clock speed (via <code>adapter speed</code> in <code>sw/openocd/openocd_neorv32.cfg</code>) make sure to meet +the clock requirements noted in <a href="https://stnolting.github.io/neorv32/#_debug_module_dm">Documentation: Debug Transport Module (DTM)</a>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>To access the processor using OpenOCD, open a terminal and start OpenOCD with the pre-configured configuration file.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 11. Connecting via OpenOCD (on Windows) using the default <code>openocd_neorv32.cfg</code> script</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">N:\Projects\neorv32\sw\openocd&gt;openocd -f openocd_neorv32.cfg +Open On-Chip Debugger 0.11.0 (2021-11-18) [https://github.com/sysprogs/openocd] +Licensed under GNU GPL v2 +libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +Info : clock speed 1000 kHz +Info : JTAG tap: neorv32.cpu tap/device found: 0x00000000 (mfg: 0x000 (&lt;invalid&gt;), part: 0x0000, ver: 0x0) +Info : datacount=1 progbufsize=2 +Info : Disabling abstract command reads from CSRs. +Info : Examined RISC-V core; found 1 harts +Info : hart 0: XLEN=32, misa=0x40901107 +Info : starting gdb server for neorv32.cpu.0 on 3333 +Info : Listening on port 3333 for gdb connections +Target HALTED. +Ready for remote connections. +Info : Listening on port 6666 for tcl connections +Info : Listening on port 4444 for telnet connections</code></pre> +</div> +</div> +<div class="paragraph"> +<p>OpenOCD has successfully connected to the NEORV32 on-chip debugger and has examined the CPU (showing the content of +the <code>misa</code> CSRs). The processor is halted and OpenOCD waits fot <code>gdb</code> to connect via port 3333.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_debugging_with_gdb">19.3. Debugging with GDB</h3> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">GDB + SVD</div> +Together with a third-party plugin the processor&#8217;s SVD file can be imported right into GDB to allow comfortable +debugging of peripheral/IO devices (see <a href="https://github.com/stnolting/neorv32/discussions/656" class="bare">https://github.com/stnolting/neorv32/discussions/656</a>). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>This guide uses the simple "blink example" from <code>sw/example/demo_blink_led</code> as simplified test application to +show the basics of in-system debugging.</p> +</div> +<div class="paragraph"> +<p>At first, the application needs to be compiled. We will use the minimal machine architecture configuration +(<code>rv32i</code>) here to be independent of the actual processor/CPU configuration. +Navigate to <code>sw/example/demo_blink_led</code> and compile the application:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 12. Compile the test application</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">.../neorv32/sw/example/demo_blink_led$ make MARCH=rv32i USER_FLAGS+=-g clean_all all</code></pre> +</div> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Adding debug symbols to the executable</div> +<code>USER_FLAGS+=-g</code> passes the <code>-g</code> flag to the compiler so it adds debug information/symbols +to the generated ELF file. This is optional but will provide more sophisticated debugging information +(like source file line numbers). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>This will generate an ELF file <code>main.elf</code> that contains all the symbols required for debugging. +Furthermore, an assembly listing file <code>main.asm</code> is generated that we will use to define breakpoints.</p> +</div> +<div class="paragraph"> +<p>Open another terminal in <code>sw/example/demo_blink_led</code> and start <code>gdb</code>.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 13. Starting GDB (on Linux (Ubuntu on Windows))</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">.../neorv32/sw/example/demo_blink_led$ riscv32-unknown-elf-gdb +GNU gdb (GDB) 10.1 +Copyright (C) 2020 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later &lt;http://gnu.org/licenses/gpl.html&gt; +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv32-unknown-elf". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +&lt;https://www.gnu.org/software/gdb/bugs/&gt;. +Find the GDB manual and other documentation resources online at: + &lt;http://www.gnu.org/software/gdb/documentation/&gt;. + +For help, type "help". +Type "apropos word" to search for commands related to "word". +(gdb)</code></pre> +</div> +</div> +<div class="paragraph"> +<p>Now connect to OpenOCD using the default port 3333 on your machine. +We will use the previously generated ELF file <code>main.elf</code> from the <code>demo_blink_led</code> example. +Finally, upload the program to the processor and start debugging.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The executable that is uploaded to the processor is <strong>not</strong> the default NEORV32 executable (<code>neorv32_exe.bin</code>) that +is used for uploading via the bootloader. Instead, all the required sections (like <code>.text</code>) are extracted from <code>mail.elf</code> +by GDB and uploaded via the debugger&#8217;s indirect memory access. +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="title">Listing 14. Running GDB</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">(gdb) target extended-remote localhost:3333 <i class="conum" data-value="1"></i><b>(1)</b> +Remote debugging using localhost:3333 +warning: No executable has been specified and target does not support +determining executable automatically. Try using the "file" command. +0xffff0c94 in ?? () <i class="conum" data-value="2"></i><b>(2)</b> +(gdb) file main.elf <i class="conum" data-value="3"></i><b>(3)</b> +A program is being debugged already. +Are you sure you want to change the file? (y or n) y +Reading symbols from main.elf... +(gdb) load <i class="conum" data-value="4"></i><b>(4)</b> +Loading section .text, size 0xd0c lma 0x0 +Loading section .rodata, size 0x39c lma 0xd0c +Start address 0x00000000, load size 4264 +Transfer rate: 43 KB/sec, 2132 bytes/write. +(gdb)</code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td>Connect to OpenOCD</td> +</tr> +<tr> +<td><i class="conum" data-value="2"></i><b>2</b></td> +<td>The CPU was still executing code from the bootloader ROM - but that does not matter here</td> +</tr> +<tr> +<td><i class="conum" data-value="3"></i><b>3</b></td> +<td>Select <code>mail.elf</code> from the <code>demo_blink_led</code> example</td> +</tr> +<tr> +<td><i class="conum" data-value="4"></i><b>4</b></td> +<td>Upload the executable</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>After the upload, GDB will make the processor jump to the beginning of the uploaded executable +(by default, this is the beginning of the instruction memory at <code>0x00000000</code>) skipping the bootloader +and halting the CPU right before executing the <code>demo_blink_led</code> application.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +After gdb has connected to the CPU, it is recommended to disable the CPU&#8217;s global interrupt flag +(<code>mstatus.mie</code>, = bit #3) to prevent unintended calls of potentially outdated trap handlers. The global +interrupt flag can be cleared using the following gdb command: +<code>set $mstatus = ($mstatus &amp; ~(1&lt;&lt;3))</code>. Interrupts can be enabled globally again by the following command: +<code>set $mstatus = ($mstatus | (1&lt;&lt;3))</code>. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_software_breakpoints">19.3.1. Software Breakpoints</h4> +<div class="paragraph"> +<p>The following steps are just a small showcase that illustrate a simple debugging scheme.</p> +</div> +<div class="paragraph"> +<p>While compiling <code>demo_blink_led</code>, an assembly listing file <code>main.asm</code> was generated. +Open this file with a text editor to check out what the CPU is going to do when resumed.</p> +</div> +<div class="paragraph"> +<p>The <code>demo_blink_led</code> example implements a simple counter on the 8 lowest GPIO output ports. The program uses +"busy wait" to have a visible delay between increments. This waiting is done by calling the <code>neorv32_cpu_delay_ms</code> +function. We will add a <em>breakpoint</em> right at the end of this wait function so we can step through the iterations +of the counter.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 15. Cut-out from <code>main.asm</code> generated from the <code>demo_blink_led</code> example</div> +<div class="content"> +<pre class="highlight"><code class="language-assembly" data-lang="assembly">00000688 &lt;__neorv32_cpu_delay_ms_end&gt;: + 688: 01c12083 lw ra,28(sp) + 68c: 02010113 addi sp,sp,32 + 690: 00008067 ret</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The very last instruction of the <code>neorv32_cpu_delay_ms</code> function is <code>ret</code> (= return) +at hexadecimal <code>690</code> in this example. Add this address as <em>breakpoint</em> to GDB.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The address might be different if you use a different version of the software framework or +if different ISA options are configured. +</td> +</tr> +</table> +</div> +<div class="listingblock"> +<div class="title">Listing 16. Adding a GDB software breakpoint</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">(gdb) b * 0x690 <i class="conum" data-value="1"></i><b>(1)</b> +Breakpoint 1 at 0x690</code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td><code>b</code> is an alias for <code>break</code>, which adds a <em>software</em> breakpoint.</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">How do <em>software</em> breakpoints work?</div> +Software breakpoints are used for debugging programs that are accessed from read/write memory (RAM) like IMEM. The debugger +temporarily replaces the instruction word of the instruction, where the breakpoint shall be inserted, by a <code>ebreak</code> / <code>c.ebreak</code> +instruction. Whenever execution reaches this instruction, debug mode is entered and the debugger restores the original +instruction at this address to maintain original program behavior.<br> +<br> +When debugging programs executed from ROM <em>hardware-assisted</em> breakpoints using the core&#8217;s trigger module have to be used. +See section <a href="#_hardware_breakpoints">Hardware Breakpoints</a> for more information. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>Now execute <code>c</code> (= continue). The CPU will resume operation until it hits the break-point. +By this we can move from one counter increment to another.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 17. Iterating from breakpoint to breakpoint</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">Breakpoint 1 at 0x690 +(gdb) c +Continuing. + +Breakpoint 1, 0x00000690 in neorv32_cpu_delay_ms () +(gdb) c +Continuing. + +Breakpoint 1, 0x00000690 in neorv32_cpu_delay_ms () +(gdb) c +Continuing.</code></pre> +</div> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Hardcoded EBREAK Instructions In The Program Code</div> +If your original application code uses the BREAK instruction (for example for some OS calls/signaling) this +instruction will cause an enter to debug mode when executed. These situation cannot be continued using gdb&#8217;s +<code>c</code> nor can they be "stepped-over" using the single-step command <code>s</code>. You need to declare the <code>ebreak</code> instruction +as breakpoint to be able to resume operation after executing it. See <a href="https://sourceware.org/pipermail/gdb/2021-January/049125.html" class="bare">https://sourceware.org/pipermail/gdb/2021-January/049125.html</a> +</td> +</tr> +</table> +</div> +</div> +<div class="sect3"> +<h4 id="_hardware_breakpoints">19.3.2. Hardware Breakpoints</h4> +<div class="paragraph"> +<p>Hardware-assisted breakpoints using the CPU&#8217;s trigger module are required when debugging code that is executed from +read-only memory (ROM) as GDB cannot temporarily replace instructions by BREAK instructions.</p> +</div> +<div class="paragraph"> +<p>From a user point of view hardware breakpoints behave like software breakpoints. GDB provides a command to setup +a hardware-assisted breakpoint:</p> +</div> +<div class="listingblock"> +<div class="title">Listing 18. Adding a GDB hardware breakpoint</div> +<div class="content"> +<pre class="highlight"><code class="language-bash" data-lang="bash">(gdb) hb * 0x690 <i class="conum" data-value="1"></i><b>(1)</b> +Breakpoint 1 at 0x690</code></pre> +</div> +</div> +<div class="colist arabic"> +<table> +<tr> +<td><i class="conum" data-value="1"></i><b>1</b></td> +<td><code>hb</code> is an alias for <code>hbreak</code>, which adds a <em>hardware</em> breakpoint.</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +The CPU&#8217;s trigger module only provides a single <em>instruction address match</em> type trigger. Hence, only +a single <code>hb</code> hardware-assisted breakpoint can be used. +</td> +</tr> +</table> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_segger_embedded_studio">19.4. Segger Embedded Studio</h3> +<div class="paragraph"> +<p>Software for the NEORV32 processor can also be developed and debugged <em>in-system</em> using Segger Embedded Studio +and a Segger J-Link probe. The following links provide further information as well as an excellent tutorial.</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Segger Embedded Studio: <a href="https://www.segger.com/products/development-tools/embedded-studio" class="bare">https://www.segger.com/products/development-tools/embedded-studio</a></p> +</li> +<li> +<p>Segger notes regarding NEORV32: <a href="https://wiki.segger.com/J-Link_NEORV32" class="bare">https://wiki.segger.com/J-Link_NEORV32</a></p> +</li> +<li> +<p>Excellent tutorial: <a href="https://www.emb4fun.com/riscv/ses4rv/index.html" class="bare">https://www.emb4fun.com/riscv/ses4rv/index.html</a></p> +</li> +</ul> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_neorv32_in_verilog">20. NEORV32 in Verilog</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>If you are more of a Verilog fan or if your EDA toolchain does not support VHDL or mixed-language designs +you can use an <strong>all-Verilog</strong> version of the processor provided by the +<a href="https://github.com/stnolting/neorv32-verilog"><code>neorv32-verilog</code></a> repository.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +Note that this is <strong>not a manual re-implementation of the core in Verilog</strong> but rather an automated conversion. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>GHDL&#8217;s synthesis feature is used to convert a pre-configured NEORV32 setup - including all peripherals, memories +and memory images - into a single, unoptimized plain-Verilog module file without any (technology-specific) primitives.</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">GHDL Synthesis</div> +More information regarding GHDL&#8217;s synthesis option can be found at <a href="https://ghdl.github.io/ghdl/using/Synthesis.html" class="bare">https://ghdl.github.io/ghdl/using/Synthesis.html</a>. +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>An intermediate VHDL wrapper is provided that can be used to configure the processor (using VHDL generics) and to +customize the interface ports. After conversion, a single Verilog file is generated that contains the whole NEORV32 +processor. The original processor module hierarchy is preserved as well as most (all?) signal names, which allows +easy inspection and debugging of simulation waveforms and synthesis results.</p> +</div> +<div class="listingblock"> +<div class="title">Listing 19. Example: interface of the resulting NEORV32 Verilog module (for a minimal SoC configuration)</div> +<div class="content"> +<pre class="highlight"><code class="language-verilog" data-lang="verilog">module neorv32_verilog_wrapper + (input clk_i, + input rstn_i, + input uart0_rxd_i, + output uart0_txd_o);</code></pre> +</div> +</div> +<div class="paragraph"> +<p>The generated Verilog code has been simulated and verified with +<a href="https://github.com/steveicarus/iverilog">Icarus Verilog</a> +(simulation) and AMD Vivado (simulation and synthesis).</p> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +For detailed information check out the <code>neorv32-verilog</code> repository at <a href="https://github.com/stnolting/neorv32-verilog" class="bare">https://github.com/stnolting/neorv32-verilog</a>. +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +<div class="sect1"> +<h2 id="_eclipse_ide">21. Eclipse IDE</h2> +<div class="sectionbody"> +<div class="paragraph"> +<p>Eclipse (<a href="https://www.eclipse.org/" class="bare">https://www.eclipse.org/</a>) is an interactive development environment that can be used to develop, debug and profile +application code for the NEORV32 RISC-V Processor. This chapter shows how to import the provided example setup +from the NEORV32 project repository. Additionally, all the required steps to create a compatible project from +scratch are illustrated in this chapter.</p> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">This is a Makefile-Based Project!</div> +Note that the provided Eclipse project as well as the setup tutorial in this section implement a <strong>makefile-based project</strong>. +Hence, the makefile in the example folder (that includes the main NEORV32 makefile) is used for building the application +instead of the Eclipse-managed build. Therefore, <strong>all compiler options, include folder, source files, etc. have to be +defined within the project&#8217;s makefile</strong>. +</td> +</tr> +</table> +</div> +<div class="imageblock text-center"> +<div class="content"> +<img src="../img/eclipse.png" alt="eclipse"> +</div> +<div class="title">Figure 4. Developing and debugging code for the NEORV32 using the Eclipse IDE</div> +</div> +<div class="sect2"> +<h3 id="_eclipse_prerequisites">21.1. Eclipse Prerequisites</h3> +<div class="paragraph"> +<p>The following tools are required:</p> +</div> +<div class="ulist"> +<ul> +<li> +<p>Eclipse IDE (<strong>Eclipse IDE for Embedded C/C++ Developers</strong>): <a href="https://www.eclipse.org/downloads/" class="bare">https://www.eclipse.org/downloads/</a></p> +</li> +<li> +<p>Precompiled RISC-V GCC toolchain: e.g. <a href="https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack" class="bare">https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack</a></p> +</li> +<li> +<p>Precompiled OpenOCD binaries: e.g. <a href="https://github.com/xpack-dev-tools/openocd-xpack" class="bare">https://github.com/xpack-dev-tools/openocd-xpack</a></p> +</li> +<li> +<p>Build tools like make: e.g. <a href="https://github.com/xpack-dev-tools/windows-build-tools-xpack" class="bare">https://github.com/xpack-dev-tools/windows-build-tools-xpack</a></p> +</li> +</ul> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">XPack Windows Build Tools</div> +The NEORV32 makefile relies on the <code>basename</code> command which is not part of the default XPack +Windows Build Tools. However, you can just open the <code>bin</code> folder, copy <code>busybox.exe</code> and rename +that copy to <code>basename.exe</code>. +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_import_the_provided_eclipse_example_project">21.2. Import The Provided Eclipse Example Project</h3> +<div class="paragraph"> +<p>A pre-configured Eclipse project is available in <code>neorv32/sw/example/eclipse</code>. +To import it:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Open Eclipse.</p> +</li> +<li> +<p>Click on <strong>File &gt; Import</strong>, expand <strong>General</strong> and select <strong>Projects from Folder or Archive</strong>.</p> +</li> +<li> +<p>Click <strong>Next</strong>.</p> +</li> +<li> +<p>Click on <strong>Directory</strong> and select the provided example project folder (see directory above).</p> +</li> +<li> +<p>Click <strong>Finish</strong>.</p> +</li> +</ol> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">NEORV32 Folder and File Paths</div> +The provided example project uses <strong>relative paths</strong> for including all the NEORV32-specific files and folders +(in the Eclipse configuration files). Note that these paths need to be adjusted when moving this example setup +to a different location (makefile, NEORV32 sources, etc.). +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Executables Configuration</div> +Make sure to adjust the binaries / installation folders of the RISC-V GCC toolchain +and OpenOCD according to your installation. See the following chapter for more information. +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_setup_a_new_eclipse_project_from_scratch">21.3. Setup a new Eclipse Project from Scratch</h3> +<div class="paragraph"> +<p>This chapter shows all the steps required to create an Eclipse project for the NEORV32 entirely from scratch.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">This is an early version! ;)</div> +The provided Eclipse project as well as the tutorial from this chapter are in a very early stage. +This setup was build and tested on Windows. +Feel free to open a new issue or pull request to improve this setup. +</td> +</tr> +</table> +</div> +<div class="sect3"> +<h4 id="_create_a_new_project">21.3.1. Create a new Project</h4> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Select <strong>File &gt; New &gt; Project</strong>.</p> +</li> +<li> +<p>Expand <strong>C/C** and select **C project</strong>.</p> +</li> +<li> +<p>In the <strong>C++ Project</strong> wizard:</p> +<div class="ulist"> +<ul> +<li> +<p>Enter a <strong>Project name</strong>.</p> +</li> +<li> +<p>Uncheck the box next to <strong>Use default location</strong> and specify a location using <strong>Browse</strong> where you want to create the project.</p> +</li> +<li> +<p>From the <strong>Project type</strong> list expand <strong>Makefile project</strong> and select <strong>Empty Project</strong>.</p> +</li> +<li> +<p>Select <strong>RISC-V Cross GCC</strong> from the <strong>Toolchain</strong> list on the right side.</p> +</li> +<li> +<p>Click <strong>Next</strong>.</p> +</li> +<li> +<p>Skip the next page using the default configuration by clicking <strong>Next</strong>.</p> +</li> +</ul> +</div> +</li> +<li> +<p>In the <strong>GNU RISC-V Cross Toolchain</strong> wizard configure the <strong>Toolchain name</strong> and <strong>Toolchain path</strong> according to your RISC-V GCC installation.</p> +<div class="ulist"> +<ul> +<li> +<p>Example: <code>Toolchain name: xPack GNU RISC-V Embedded GCC (riscv-none-elf-gcc)</code></p> +</li> +<li> +<p>Example: <code>Toolchain path: C:\Program Files (x86)\xpack-riscv-none-elf-gcc-13.2.0-2\bin</code></p> +</li> +</ul> +</div> +</li> +<li> +<p>Click <strong>Finish</strong>.</p> +</li> +</ol> +</div> +<div class="paragraph"> +<p>If you need to reconfigure the RISC-V GCC binaries and/or paths:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>right-click on the project in the left view, select <strong>Properties</strong></p> +</li> +<li> +<p>expand <strong>MCU</strong> and select <strong>RISC-V Toolchain Paths</strong></p> +</li> +<li> +<p>adjust the <strong>Toolchain folder</strong> and the <strong>Toolchain name</strong> if required</p> +</li> +<li> +<p>Click <strong>Apply</strong>.</p> +</li> +</ol> +</div> +</div> +<div class="sect3"> +<h4 id="_add_initial_files">21.3.2. Add Initial Files</h4> +<div class="paragraph"> +<p>Start a simple project by adding two initial files. Further files can be added later. Only the makefile is really +relevant here.</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Add a new file by right-clicking on the project and select <strong>New &gt; File</strong> and enter <code>main.c</code> in the filename box.</p> +</li> +<li> +<p>Add another new file by right-clicking on the project and select <strong>New &gt; File</strong> and enter <code>makefile</code> in the filename</p> +</li> +<li> +<p>Copy the makefile of an existing NEORV32 example program and paste it to the new (empty) makefile.</p> +</li> +</ol> +</div> +</div> +<div class="sect3"> +<h4 id="_add_build_targets_optional">21.3.3. Add Build Targets (optional)</h4> +<div class="paragraph"> +<p>This step adds some of the targets of the NEORV32 makefile for easy access. This step is optional.</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>In the project explorer right-click on the project and select <strong>Build Target &gt; Create&#8230;&#8203;</strong>.</p> +</li> +<li> +<p>Add &#8220;all&#8221; as <strong>Target name</strong> (keep all the default checked boxes).</p> +</li> +<li> +<p>Repeat these steps for all further targets that you wish to add (e..g <code>clean_all</code>, <code>exe</code>, <code>elf</code>).</p> +</li> +</ol> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Clean-All Target</div> +Adding the <code>clean_all</code> target is highly recommended. Executing this target once after importing the project ensures +that there are no (incompatible) artifacts left from previous builds. +</td> +</tr> +</table> +</div> +<div class="admonitionblock tip"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-tip" title="Tip"></i> +</td> +<td class="content"> +<div class="title">Available Target</div> +See the NEORV32 data sheet for a list and description of all available makefile targets: +<a href="https://stnolting.github.io/neorv32/#_makefile_targets" class="bare">https://stnolting.github.io/neorv32/#_makefile_targets</a> +</td> +</tr> +</table> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_configure_build_tools">21.4. Configure Build Tools</h3> +<div class="paragraph"> +<p>This step is only required if your system does not provide any build tools (like <code>make</code>) by default.</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>In the project explorer right-click on the project and select <strong>Properties</strong>.</p> +</li> +<li> +<p>Expand <strong>MCU</strong> and click on <strong>Build Tools Path</strong>.</p> +</li> +<li> +<p>Configure the <strong>Build tools folder</strong>.</p> +<div class="ulist"> +<ul> +<li> +<p>Example: <code>Build tools folder: C:/xpack/xpack-windows-build-tools-4.4.1-2/bin</code></p> +</li> +</ul> +</div> +</li> +<li> +<p>Click <strong>Apply and Close</strong>.</p> +</li> +</ol> +</div> +</div> +<div class="sect2"> +<h3 id="_adjust_default_build_configuration_optional">21.5. Adjust Default Build Configuration (optional)</h3> +<div class="paragraph"> +<p>This will simplify the auto-build by replacing the default <code>make all</code> command by <code>make elf</code>. Thus, only +the required <code>main.elf</code> file gets generated instead of <em>all</em> executable files (like HDL and memory image files).</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>In the project explorer right-click on the project and select <strong>Properties</strong>.</p> +</li> +<li> +<p>Select <strong>C/C++ Build</strong> and click on the <strong>Behavior</strong> Tab.</p> +</li> +<li> +<p>Update the default targets in the <strong>Workbench Build Behavior</strong> box:</p> +<div class="ulist"> +<ul> +<li> +<p><strong>Build on resource save:</strong> <code>elf</code> (only build the ELF file)</p> +</li> +<li> +<p><strong>Build (Incremental build):</strong> <code>elf</code> (only build the ELF file)</p> +</li> +<li> +<p><strong>Clean:</strong> <code>clean</code> (only remove project-local build artifacts)</p> +</li> +</ul> +</div> +</li> +<li> +<p>Click <strong>Apply and Close</strong>.</p> +</li> +</ol> +</div> +<div class="sect3"> +<h4 id="_add_neorv32_software_framework">21.5.1. Add NEORV32 Software Framework</h4> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>In the project explorer right-click on the project and select <strong>Properties</strong>.</p> +</li> +<li> +<p>Expand <strong>C/C++ General</strong>, click on <strong>Paths and Symbols</strong> and highlight <strong>Assembly</strong> under <strong>Languages</strong>.</p> +</li> +<li> +<p>In the <strong>Include</strong> tab click <strong>Add&#8230;&#8203;</strong></p> +<div class="ulist"> +<ul> +<li> +<p>Check the box in front of <strong>Add to all languages</strong> and click on <strong>File System&#8230;&#8203;</strong> and select the NEORV32 library include folder (<code>path/to/neorv32/sw/lib/include</code>).</p> +</li> +<li> +<p>Click <strong>OK</strong>.</p> +</li> +</ul> +</div> +</li> +<li> +<p>In the <strong>Include</strong> tab click <strong>Add&#8230;&#8203;</strong>.</p> +<div class="ulist"> +<ul> +<li> +<p>Check the box in front of <strong>Add to all languages</strong> and click on <strong>File System&#8230;&#8203;</strong> and select the NEORV32 commons folder (<code>path/to/neorv32/sw/common</code>).</p> +</li> +<li> +<p>Click <strong>OK</strong>.</p> +</li> +</ul> +</div> +</li> +<li> +<p>Click on the <strong>Source Location<strong> tab and click </strong>Link Folder&#8230;&#8203;</strong>*.</p> +<div class="ulist"> +<ul> +<li> +<p>Check the box in front of <strong>Link to folder in the system</strong> and click the <strong>Browse</strong> button.</p> +</li> +<li> +<p>Select the source folder of the NEORV32 software framework (<code>path/to/neorv32/sw/lib/source</code>).</p> +</li> +<li> +<p>Click <strong>OK</strong>.</p> +</li> +</ul> +</div> +</li> +<li> +<p>Click <strong>Apply and Close</strong>.</p> +</li> +</ol> +</div> +</div> +<div class="sect3"> +<h4 id="_setup_openocd">21.5.2. Setup OpenOCD</h4> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>In the project explorer right-click on the project and select <strong>Properties</strong>.</p> +</li> +<li> +<p>Expand <strong>MCU</strong> and select <strong>OpenOCD Path</strong>.</p> +<div class="ulist"> +<ul> +<li> +<p>Configure the <strong>Executable</strong> and <strong>Folder</strong> according to your openOCD installation.</p> +</li> +<li> +<p>Example: <code>Executable: openocd.exe</code></p> +</li> +<li> +<p>Example: <code>Folder: C:\OpenOCD\bin</code></p> +</li> +<li> +<p>Click <strong>Apply and Close</strong>.</p> +</li> +</ul> +</div> +</li> +<li> +<p>In the top bar of Eclipse click on the tiny arrow right next to the <strong>Debug</strong> bug icon and select <strong>Debug Configurations</strong>.</p> +</li> +<li> +<p>Double-click on <strong>GDB OpenOCD Debugging</strong>; several menu tabs will open on the right.</p> +<div class="ulist"> +<ul> +<li> +<p>In the <strong>Main</strong> tab add <code>main.elf</code> to the <strong>C/C++ Application</strong> box.</p> +</li> +<li> +<p>In the <strong>Debugger</strong> tab add the NEORV32 OpenOCD script with a <code>-f</code> in front of it-</p> +</li> +<li> +<p>Example: <code>Config options: -f ../../openocd/openocd_neorv32.cfg</code></p> +</li> +<li> +<p>In the <strong>Startup</strong> tab uncheck he box in front of <strong>Initial Reset</strong> and add <code>monitor reset halt</code> to the box below.</p> +</li> +<li> +<p>In the "Common" tab mark <strong>Shared file</strong> to store the run-configuration right in the project folder instead of the workspace(optional).</p> +</li> +<li> +<p>In the <strong>SVD Path</strong> tab add the NEORV32 SVD file (<code>path/to/neorv32/sw/svd/neorv32.svd</code>).</p> +</li> +</ul> +</div> +</li> +<li> +<p>Click <strong>Apply</strong> and then <strong>Close</strong>.</p> +</li> +</ol> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Default Debug Configuration</div> +When you start debugging the first time you might need to select the provided debug configuration: +<strong>GDB OpenOCD Debugging &gt; eclipse_example Default</strong> +</td> +</tr> +</table> +</div> +<div class="admonitionblock important"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-important" title="Important"></i> +</td> +<td class="content"> +<div class="title">Debug Symbols</div> +For debugging the ELF has to compiled to contain according debug symbols. +Debug symbols are enabled by the project&#8217;s local makefile: <code>USER_FLAGS += -ggdb -gdwarf-3</code> +(this configuration seems to work best for Eclipse - at least for me). +</td> +</tr> +</table> +</div> +<div class="paragraph"> +<p>If you need to reconfigure OpenOCD binaries and/or paths:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>right-click on the project in the left view, select <strong>Properties</strong></p> +</li> +<li> +<p>expand <strong>MCU</strong> and select <strong>OpenOCD Path</strong></p> +</li> +<li> +<p>adjust the <strong>Folder</strong> and the <strong>Executable</strong> name if required</p> +</li> +<li> +<p>Click <strong>Apply</strong>.</p> +</li> +</ol> +</div> +</div> +<div class="sect3"> +<h4 id="_setup_serial_terminal">21.5.3. Setup Serial Terminal</h4> +<div class="paragraph"> +<p>A serial terminal can be added to Eclipse by installing it as a plugin. +I recommend "TM Terminal" which is already installed in some Eclipse bundles.</p> +</div> +<div class="paragraph"> +<p>Open a TM Terminal serial console:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Click on <strong>Window &gt; Show View &gt; Terminal</strong> to open the terminal.</p> +</li> +<li> +<p>A <strong>Terminal</strong> tab appears on the bottom. Click the tiny screen button on the right (or press Ctrl+Alt+Shift) +to open the terminal configuration.</p> +</li> +<li> +<p>Select <strong>Serial Terminal</strong> in <strong>Choose Terminal</strong> and configure the settings according to the processor&#8217;s +UART configuration.</p> +</li> +</ol> +</div> +<div class="paragraph"> +<p>Installing TM Terminal from the Eclipse market place:</p> +</div> +<div class="olist arabic"> +<ol class="arabic" start="1"> +<li> +<p>Click on <strong>Help &gt; Eclipse Marketplace&#8230;&#8203;</strong>.</p> +</li> +<li> +<p>Enter "TM Terminal" to the <strong>Find</strong> line and hit enter.</p> +</li> +<li> +<p>Select <strong>TM Terminal</strong> from the list and install it.</p> +</li> +<li> +<p>After installation restart Eclipse.</p> +</li> +</ol> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_eclipse_setup_references">21.6. Eclipse Setup References</h3> +<div class="ulist"> +<ul> +<li> +<p>Eclipse help: <a href="https://help.eclipse.org/latest/index.jsp" class="bare">https://help.eclipse.org/latest/index.jsp</a></p> +</li> +<li> +<p>Importing an existing project into Eclipse: <a href="https://help.eclipse.org/latest/index.jsp?topic=%2Forg.eclipse.cdt.doc.user%2Fgetting_started%2Fcdt_w_import.htm" class="bare">https://help.eclipse.org/latest/index.jsp?topic=%2Forg.eclipse.cdt.doc.user%2Fgetting_started%2Fcdt_w_import.htm</a></p> +</li> +<li> +<p>Eclipse OpenOCD Plug-In: <a href="https://eclipse-embed-cdt.github.io/debug/openocd/" class="bare">https://eclipse-embed-cdt.github.io/debug/openocd/</a></p> +</li> +</ul> +</div> +<div style="page-break-after: always;"></div> +</div> +</div> +</div> +<div class="sect1"> +<h2 id="_legal">22. Legal</h2> +<div class="sectionbody"> +<div class="sect2"> +<h3 id="_about">About</h3> +<div class="exampleblock"> +<div class="content"> +<div class="paragraph"> +<p><strong>The NEORV32 RISC-V Processor</strong><br> +<a href="https://github.com/stnolting/neorv32" class="bare">https://github.com/stnolting/neorv32</a><br> +Stephan Nolting, M.Sc.<br> +๐Ÿ‡ช๐Ÿ‡บ European Union<br> +<code>stnolting[รคt]gmail[d0t]com</code></p> +</div> +</div> +</div> +</div> +<div class="sect2"> +<h3 id="_license">License</h3> +<div class="paragraph"> +<p><strong>BSD 3-Clause License</strong></p> +</div> +<div class="paragraph"> +<p>Copyright (c) NEORV32 contributors. +Copyright (c) 2020 - 2024, Stephan Nolting. All rights reserved.</p> +</div> +<div class="paragraph"> +<p>Redistribution and use in source and binary forms, with or without modification, are permitted provided that +the following conditions are met:</p> +</div> +<div class="olist arabic"> +<ol class="arabic"> +<li> +<p>Redistributions of source code must retain the above copyright notice, this list of conditions and the +following disclaimer.</p> +</li> +<li> +<p>Redistributions in binary form must reproduce the above copyright notice, this list of conditions and +the following disclaimer in the documentation and/or other materials provided with the distribution.</p> +</li> +<li> +<p>Neither the name of the copyright holder nor the names of its contributors may be used to endorse or +promote products derived from this software without specific prior written permission.</p> +</li> +</ol> +</div> +<div class="paragraph"> +<p>THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE.</p> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">SPDX Identifier</div> +<code>SPDX-License-Identifier: BSD-3-Clause</code> +</td> +</tr> +</table> +</div> +<div style="page-break-after: always;"></div> +</div> +<div class="sect2"> +<h3 id="_proprietary_notice">Proprietary Notice</h3> +<div class="ulist"> +<ul> +<li> +<p>"GitHub" is a subsidiary of Microsoft Corporation.</p> +</li> +<li> +<p>"Vivado" and "Artix" are trademarks of AMD Inc.</p> +</li> +<li> +<p>"AXI", "AXI", "AXI4-Lite", "AXI4-Stream", "AHB", "AHB3" and "AHB3-Lite" are trademarks of Arm Holdings plc.</p> +</li> +<li> +<p>"ModelSim" is a trademark of Mentor Graphics โ€“ A Siemens Business.</p> +</li> +<li> +<p>"Quartus [Prime]" and "Cyclone" are trademarks of Intel Corporation.</p> +</li> +<li> +<p>"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.</p> +</li> +<li> +<p>"GateMate" is a trademark of Cologne Chip AG.</p> +</li> +<li> +<p>"Windows" is a trademark of Microsoft Corporation.</p> +</li> +<li> +<p>"Tera Term" copyright by T. Teranishi.</p> +</li> +<li> +<p>"NeoPixel" is a trademark of Adafruit Industries.</p> +</li> +<li> +<p>"Segger Embedded Studio" and "J-Link" are trademarks of Segger Microcontroller Systems GmbH.</p> +</li> +<li> +<p>Images/figures made with <em>Microsoft Power Point</em>.</p> +</li> +<li> +<p>Timing diagrams made with <em>WaveDrom Editor</em>.</p> +</li> +<li> +<p>Documentation made with <code>asciidoctor</code>.</p> +</li> +</ul> +</div> +<div class="paragraph"> +<p>All further/unreferenced projects/products/brands belong to their according copyright holders. +No copyright infringement intended.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_disclaimer">Disclaimer</h3> +<div class="paragraph"> +<p>This project is released under the BSD 3-Clause license. NO COPYRIGHT INFRINGEMENT INTENDED. +Other implied or used projects/sources might have different licensing โ€“ see their according +documentation for more information.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_limitation_of_liability_for_external_links">Limitation of Liability for External Links</h3> +<div class="paragraph"> +<p>This document contains links to the websites of third parties ("external links"). As the content of these websites +is not under our control, we cannot assume any liability for such external content. In all cases, the provider of +information of the linked websites is liable for the content and accuracy of the information provided. At the +point in time when the links were placed, no infringements of the law were recognizable to us. As soon as an +infringement of the law becomes known to us, we will immediately remove the link in question.</p> +</div> +</div> +<div class="sect2"> +<h3 id="_citing">Citing</h3> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +This is an open-source project that is free of charge. Use this project in any way you like +(as long as it complies to the permissive license). Please cite it appropriately. ๐Ÿ‘ +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">Contributors &amp; Community ๐Ÿค</div> +Please add as many <a href="https://github.com/stnolting/neorv32/graphs/contributors">contributors</a> as possible to the <code>author</code> field.<br> +This project would not be where it is without them. +</td> +</tr> +</table> +</div> +<div class="admonitionblock note"> +<table> +<tr> +<td class="icon"> +<i class="fa icon-note" title="Note"></i> +</td> +<td class="content"> +<div class="title">DOI</div> +This project provides a <em>digital object identifier</em> provided by <a href="https://zenodo.org">zenodo</a>: +<a href="https://doi.org/10.5281/zenodo.5018888"><span class="image"><img src="https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg" alt="zenodo.5018888" title="zenodo"></span></a> +</td> +</tr> +</table> +</div> +</div> +<div class="sect2"> +<h3 id="_acknowledgments">Acknowledgments</h3> +<div class="paragraph"> +<p><strong>A big shout-out to the community and all the <a href="https://github.com/stnolting/neorv32/graphs/contributors">contributors</a>, +who helped improving this project! This project would not be where it is without them. โค๏ธ</strong></p> +</div> +<div class="paragraph"> +<p><a href="https://riscv.org">RISC-V</a> - instruction sets want to be free!</p> +</div> +<div class="paragraph"> +<p>Continuous integration provided by <a href="https://github.com/features/actions">GitHub Actions</a> +and powered by <a href="https://github.com/ghdl/ghdl">GHDL</a>.</p> +</div> +</div> +</div> +</div> +</div> +<div id="footer"> +<div id="footer-text"> +Version v1.10.5-r58-gf1069d11<br> +</div> +</div> +<script type="text/x-mathjax-config"> +MathJax.Hub.Config({ + messageStyle: "none", + tex2jax: { + inlineMath: [["\\(", "\\)"]], + displayMath: [["\\[", "\\]"]], + ignoreClass: "nostem|nolatexmath" + }, + asciimath2jax: { + delimiters: [["\\$", "\\$"]], + ignoreClass: "nostem|noasciimath" + }, + TeX: { equationNumbers: { autoNumber: "none" } } +}) +MathJax.Hub.Register.StartupHook("AsciiMath Jax Ready", function () { + MathJax.InputJax.AsciiMath.postfilterHooks.Add(function (data, node) { + if ((node = data.script.parentNode) && (node = node.parentNode) && node.classList.contains("stemblock")) { + data.math.root.display = "block" + } + return data + }) +}) +</script> +<script src="https://cdnjs.cloudflare.com/ajax/libs/mathjax/2.7.9/MathJax.js?config=TeX-MML-AM_HTMLorMML"></script> +</body> +</html> \ No newline at end of file