From b3155be575b6c847ebd04cfa2b5ce394e6a7d6b2 Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 1 Nov 2024 14:34:21 +0100 Subject: [PATCH] [mepc] use CPU BOOT_ADDR as reset value --- docs/datasheet/cpu_csr.adoc | 2 +- rtl/core/neorv32_cpu_control.vhd | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/datasheet/cpu_csr.adoc b/docs/datasheet/cpu_csr.adoc index 7af2b6447..6f1b3eeca 100644 --- a/docs/datasheet/cpu_csr.adoc +++ b/docs/datasheet/cpu_csr.adoc @@ -360,7 +360,7 @@ As software does not need to determine the interrupt cause the reduction in late |======================= | Name | Machine exception program counter | Address | `0x341` -| Reset value | `0x00000000` +| Reset value | `BOOT_ADDR` (CPU boot address, see <<_cpu_top_entity_generics>>) | ISA | `Zicsr` | Description | The `mepc` CSR provides the instruction address where execution has stopped/failed when an interrupt is triggered / an exception is raised. See section <<_traps_exceptions_and_interrupts>> for a list of all legal values. diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd index fdef023fd..6eae8ccba 100644 --- a/rtl/core/neorv32_cpu_control.vhd +++ b/rtl/core/neorv32_cpu_control.vhd @@ -1410,7 +1410,7 @@ begin csr.mie_firq <= (others => '0'); csr.mtvec <= (others => '0'); csr.mscratch <= x"19880704"; - csr.mepc <= (others => '0'); + csr.mepc <= BOOT_ADDR(XLEN-1 downto 2) & "00"; -- 32-bit-aligned boot address csr.mcause <= (others => '0'); csr.mtval <= (others => '0'); csr.mtinst <= (others => '0');