From 78a1ca16357620b1c7f016fdeda05f9a7eee2fe3 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Mon, 29 Jan 2024 21:00:45 +0100 Subject: [PATCH 1/3] extend switchable clock domain When the CPU is in sleep mode and clock gating is enabled the CPU itself is shut down together with the CPU's bus switch and - if implemented - the caches. --- rtl/core/neorv32_package.vhd | 2 +- rtl/core/neorv32_top.vhd | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index aefce02e0..c6225389d 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -56,7 +56,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090308"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090309"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index d0b74281a..80fc1b888 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -602,7 +602,7 @@ begin ICACHE_UC_PBEGIN => uncached_begin_c(31 downto 28) ) port map ( - clk_i => clk_i, + clk_i => clk_cpu, rstn_i => rstn_sys, clear_i => i_fence, cpu_req_i => cpu_i_req, @@ -630,7 +630,7 @@ begin DCACHE_UC_PBEGIN => uncached_begin_c(31 downto 28) ) port map ( - clk_i => clk_i, + clk_i => clk_cpu, rstn_i => rstn_sys, clear_i => d_fence, cpu_req_i => cpu_d_req, @@ -655,7 +655,7 @@ begin PORT_B_READ_ONLY => true -- i-fetch is read-only ) port map ( - clk_i => clk_i, + clk_i => clk_cpu, rstn_i => rstn_sys, a_req_i => dcache_req, -- prioritized a_rsp_o => dcache_rsp, From 25a5724e35b18fb48a617baa1d940e9e2d73fb08 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Mon, 29 Jan 2024 21:05:53 +0100 Subject: [PATCH 2/3] [docs] extend clock gating section --- docs/datasheet/soc.adoc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index f75232d45..9cb53b6f5 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -311,9 +311,10 @@ before being further processed. ==== Clock Gating The single clock domain of the processor can be split into an always-on clock domain and a switchable clock domain. -The switchable clock domain is used to clock the CPU core. This domain can be deactivated at runtime to reduce power -consumption. The always-on clock domain is used to clock all other processor modules like peripherals, memories and IO -devices. Hence, these modules can continue operation (e.g. a timer keeps running) even if the CPU is shut down. +The switchable clock domain is used to clock the CPU core, the CPU's bus switch and - if implemented - the caches. +This domain can be deactivated to reduce power consumption. The always-on clock domain is used to clock all other +processor modules like peripherals, memories and IO devices. Hence, these modules can continue operation (e.g. a +timer keeps running) even if the CPU is shut down. The splitting into two clock domain is enabled by the `CLOCK_GATING_EN` generic (<<_processor_top_entity_generics>>). When enabled, a generic clock switching gate is added to decouple the switchable clock from the always-on clock domain From 2d469c6e9caaeab7df55aec1713018593cc60324 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Mon, 29 Jan 2024 21:06:09 +0100 Subject: [PATCH 3/3] [CHANGELOG] add v1.9.3.9 --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 76352c562..0cd1270c2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Link | |:----:|:-------:|:--------|:----:| +| 29.01.2024 | 1.9.3.9 | :test_tube: extend switchable clock domain (CPU bus switch, i-cache, d-cache) | [#780](https://github.com/stnolting/neorv32/pull/780) | | 29.01.2024 | 1.9.3.8 | top entity input ports now have default values `'L'` or `'h'` modeling a pull-down or pull-resistor in case they are not explicitly assigned during instantiation | [#779](https://github.com/stnolting/neorv32/pull/779) | | 28.01.2024 | 1.9.3.7 | FIFO module _NULL assertion_ fix | [#778](https://github.com/stnolting/neorv32/pull/778) | | 27.01.2024 | 1.9.3.6 | improve CPU's front end (instruction fetch) increasing overall performance | [#777](https://github.com/stnolting/neorv32/pull/777) |