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Tsizer returns an error with the -g2012 option (as well as with -g2009 and -g2005-sv), showing the message:
SIZER: The root scope $unit must be a module. error: Code generation had 1 error(s).
However, the output statistic was generated as well. The code contains only modules and works without issues when using the default -g2005 option.
The text was updated successfully, but these errors were encountered:
We likely just need to modify the code to skip the SystemVerilog $unit scope.
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Tsizer returns an error with the -g2012 option (as well as with -g2009 and -g2005-sv), showing the message:
However, the output statistic was generated as well.
The code contains only modules and works without issues when using the default -g2005 option.
The text was updated successfully, but these errors were encountered: