Nested generate statement not reported as syntax error

[YikeZhou]

Please consider the following example.

module top (y, x);
  output y;
  input x;
  genvar i;

generate
generate
for (i=0; i<1; i=i+1) begin
  assign y = x;
end
endgenerate
endgenerate

endmodule

iverilog (latest master, ef7f0a8) accepts this code and generates a.out without any errors or warnings.
Verilator as well as other commercial simulators available on https://www.edaplayground.com/ complained about syntax error of nested generate regions.

According to IEEE Std 1364™-2005, Annex A:

• "generate_region" can produce the keywords generate and endgenerate.
• "generate_region" is derived from "non_port_module_item"
• "module_or_generate_item" -> "loop_generate_construct" -> "generate_block" -> "module_or_generate_item" -> ... There can not be any "generate_region" in "module_or_generate_item".

Related BNF:

generate_region ::=
    generate { module_or_generate_item } endgenerate

module_or_generate_item ::=
    ... | { attribute_instance } loop_generate_construct

loop_generate_construct ::=
    for ( genvar_initialization ; genvar_expression ; genvar_iteration )
        generate_block

generate_block ::=
    module_or_generate_item
    | begin [ : generate_block_identifier ] { module_or_generate_item } end

non_port_module_item ::=
    module_or_generate_item
        | generate_region

Therefore, the code above is not valid Verilog. Maybe iverilog can report syntax error on such input files?