From 8210cce91d99d2f95ea29b1d87f4369ac1186664 Mon Sep 17 00:00:00 2001 From: lyaniix <151337984+lyaniix@users.noreply.github.com> Date: Mon, 15 Apr 2024 22:25:56 +0800 Subject: [PATCH] Add files via upload --- .../ChatChisel.ipynb | 89368 ++++++++++++++++ 1 file changed, 89368 insertions(+) create mode 100644 VLSI24/submitted_notebooks/Submission-ChatChisel Enabling Agile Hardware Design with Large Language Models/ChatChisel.ipynb diff --git a/VLSI24/submitted_notebooks/Submission-ChatChisel Enabling Agile Hardware Design with Large Language Models/ChatChisel.ipynb b/VLSI24/submitted_notebooks/Submission-ChatChisel Enabling Agile Hardware Design with Large Language Models/ChatChisel.ipynb new file mode 100644 index 0000000..4ef8b15 --- /dev/null +++ b/VLSI24/submitted_notebooks/Submission-ChatChisel Enabling Agile Hardware Design with Large Language Models/ChatChisel.ipynb @@ -0,0 +1,89368 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "id": "9bb39b76-a73b-41b8-b57f-69151739d7e1", + "metadata": { + "id": "9bb39b76-a73b-41b8-b57f-69151739d7e1" + }, + "source": [ + "# **ChatChisel: Enabling Agile Hardware Design with Large Language Models**" + ] + }, + { + "cell_type": "markdown", + "id": "06045525-bb66-496d-99f3-d14e746d3d56", + "metadata": { + "id": "06045525-bb66-496d-99f3-d14e746d3d56" + }, + "source": [ + "\"Open" + ] + }, + { + "cell_type": "markdown", + "id": "caa40864-7e00-43ab-9a5d-37f560983c90", + "metadata": { + "id": "caa40864-7e00-43ab-9a5d-37f560983c90" + }, + "source": [ + "```\n", + "National ASIC Center, School of Integrate Circuits, Southeast University&\n", + "National Center of Technology Innovation for Electronic Design Automation, April 2024\n", + "SPDX-License-Identifier: Apache-2.0\n", + "```" + ] + }, + { + "cell_type": "markdown", + "id": "a7aac8f2-a280-4b08-887d-7ebdd6ebf6eb", + "metadata": { + "id": "a7aac8f2-a280-4b08-887d-7ebdd6ebf6eb" + }, + "source": [ + "\n", + "|Name|Affiliation|IEEE Member|SSCS Member|\n", + "|:--:|:----------:|:----------:|:----------:|\n", + "| **Team** **member**:\n", + "|Qi Tian*
Email: qi_tian@seu.edu.cn|National ASIC Center, School of Integrate Circuits, Southeast University|No|No|\n", + "|Tianyang Liu*
Email: liutianyang@seu.edu.cn|National ASIC Center, School of Integrate Circuits, Southeast University|No|No|\n", + "|Junyan Li*
Email: lyaniix.123@gmail.com|National ASIC Center, School of Integrate Circuits, Southeast University|No|No|\n", + "|Jianmin Ye
Email: jianmin_y@seu.edu.cn|National ASIC Center, School of Integrate Circuits, Southeast University|No|No|\n", + "|LikTung Fu
Email: zdy22@mails.tsinghua.edu.cn|National ASIC Center, School of Integrate Circuits, Southeast University|No|No|\n", + "|Shengchu Su
Email: xzx21@mails.tsinghua.edu.cn|National ASIC Center, School of Integrate Circuits, Southeast University|No|No|\n", + "|Gwokwaa Wan
Email: gwokwaa@nctieda.com|National Center of Technology Innovation for Electronic Design Automation|No|No|\n", + "|Layton Zhang
Email: layton@nctieda.com|National Center of Technology Innovation for Electronic Design Automation|No|No|\n", + "|SamZaak Wong
Email: samzaak@nctieda.com|National Center of Technology Innovation for Electronic Design Automation|No|No|\n", + "Silin Ye
Email: yesilin@nctieda.com |National Center of Technology Innovation for Electronic Design Automation|No|No|\n", + "***Advisor:***\n", + "|Jun Yang
Email: yangjun@nctieda.com|National ASIC Center, School of Integrated Circuits , Southeast University|Yes|No|\n", + "|Xi Wang*
Email: xi.wang@seu.edu.cn |National ASIC Center, School of Integrated Circuits , Southeast University|No|No|" + ] + }, + { + "cell_type": "markdown", + "id": "40ba8b5a-325c-43f9-b736-cf3ab8818668", + "metadata": { + "id": "40ba8b5a-325c-43f9-b736-cf3ab8818668" + }, + "source": [ + "## Abstract\n", + "In this notebook, **we introduce ChatChisel, a language-based agile hardware design workflow capable of generating Chisel code from language specifications**. With the increasing complexity of integrated circuits, agile hardware design methodologies become crucial. Modern hardware description languages (HDLs) like Chisel improve design quality, but manual implementations remain error-prone and time-consuming. Large language models (LLMs) offer potential for hardware design automation through natural language but face challenges in generating large circuits using Verilog. We assess LLM capabilities for Chisel and Verilog generation, demonstrating superior Chisel generation ability. We present ChatChisel as the first language-based agile hardware design workflow, generating Chisel code from language specifications. ChatChisel utilizes four LLM-based modules for decomposition, generation, error correction, and composition of hardware designs. Techniques like LLM collaboration and RAG enhance ChatChisel’s performance. Using GPT-3.5-turbo, **we implemented an RV32I RISC-V CPU with a 5-stage pipeline and dynamic branch prediction**. We validate our approach through extensive evaluations. **Experimental results reveal that ChatChisel can outperform LLM-based hardware design with Verilog by an average of 31.86%, implying significant design capability enhancement and design process acceleration with ChatChisel**." + ] + }, + { + "cell_type": "markdown", + "id": "8bdc48c0-f004-47e8-b2ce-7870a7ee7f45", + "metadata": { + "id": "8bdc48c0-f004-47e8-b2ce-7870a7ee7f45" + }, + "source": [ + "## Background\n", + "With the increasing demand for computing in areas such as deep learning, big data, and blockchain, driven by advancements in information technology, the scale and complexity of integrated circuits (ICs) are growing rapidly. The emerging domain-specific architectures (DSAs) targeting distinct application domains feature customized instructions, programming models, microarchitectures, heterogeneity, etc. Such customization inevitably complicates the ASIC design, especially the implementation and verification processes. To address this challenge, there is a pressing need for agile hardware development capabilities.\n", + "\n", + "Current digital circuit designs primarily rely on manually written, relatively primitive hardware description languages(i.e., Verilog and SystemVerilog). Implementations based on traditional HDLs may encounter issues in maintaining readability and modularity, leading to challenges in code reusability and scalability for complex designs, which cannot satisfy the needs of agile design iterations. To address these limitations, modern HDLs such as Chisel have been introduced. Chisel is a Scala-based hardware construction language that describes digital circuits and systems using an object-oriented approach, enabling more expressive, concise, and maintainable designs. This facilitates rapid prototyping and iterative development, making it well-suited for the demands of agile hardware design. However, manual implementations based on modern HDLs still require considerable effort and time. Given that human-driven implementations are error-prone, this does not necessarily reduce the large amount of time spent in debugging and verification processes. Further advancements in design automation and tool support are strongly desired to streamline the development process and minimize errors in complex digital circuit designs.\n", + "\n", + "Machine Learning (ML) has been widely applied in Electronic Design Automation (EDA) to enhance the degree of design automation. While most ML-based optimizations in EDA tools focus on the backend processes, such as placement, routing, timing, and power analysis. However, the frontend of the design flow, which involves the initial creation and verification of hardware descriptions, has seen limited automation advancements. The emergence of large language models (LLMs) such as ChatGPT represents a significant opportunity to bridge this gap and further enhance the efficiency of agile hardware design. LLMs enable RTL-level circuit design using natural language, converting functional descriptions into HDL and modifying the generated HDL based on linter feedback to correct syntax errors. This reduces the time spent on manual HDL writing and fixing syntax errors, consequently improving circuit design and iteration efficiency. However, there are some challenges associated with LLM-based circuit design methodologies:\n", + "- LLMs have limited tokens, and cannot directly generate large-scale circuits\n", + "- LLMs may exhibit hallucinations, in\u0002accurately converting the description of circuits into HDL\n", + "- LLMs’ output is significantly influenced by the given prompt,leading to variations in the quality of generated circuits\n", + "\n", + "This notebook demonstrates that the ability of LLMs to generate Chisel is superior to Verilog under the same conditions. To address the mentioned challenges in LLM-based circuit generation, we propose a LLM-based digital circuit generation framework with Chisel. The framework consists of four LLMs, responsible for design decomposition, generation, error correction, and composition, respectively." + ] + }, + { + "cell_type": "markdown", + "id": "b58ed139-5144-44c5-954d-2575ef18d292", + "metadata": { + "id": "b58ed139-5144-44c5-954d-2575ef18d292" + }, + "source": [ + "## Design & Methodology\n", + "\n", + "- Design Decomposition: LLMs struggle to generate large-scale circuits mainly due to two limitations. First, the limited number of input and output tokens in LLMs restricts the scale of circuits they can generate. Second, LLMs have limited generation capabilities and may overlook certain details in complex circuit descriptions. Generally, LLMs perform better in classification tasks compared to generation tasks. Therefore, we utilize an LLM to automatically decompose complex design into simpler modules, enabling it to focus on generating multiple logically simple leaf modules separately.\n", + " \n", + "- Tool Enhanced LLM Error Correction: LLMs often suffer from hallucinations during generation. In circuit generation, these inaccuracies can be classified into two types: alignment and correctness. Alignment refers to LLM-generated circuits that do not align with the input prompt in terms of functionality, while correctness refers to LLM-generated design exposing syntax or functionality errors in certain circuit structures. To address these issues, we employ tool-assisted error correction methodology. For syntax errors, we utilize an LLM with feedback from a linter for syntax check and correction. For errors captured in functionality verification, we employ an LLM that extracts feedback from testbench output information.\n", + " \n", + "- Structured Prompt with RAG: The generation capability of LLMs is limited by the scale and diversity of the training dataset. LLMs struggle to accurately generate content with limited training data. For instance, the lack of Chisel design knowledge impedes the capability of Llama2 to generate circuits in Chisel. Therefore, we employ the RAG technique to enhance the generation capability of LLM in specific domains without requiring additional training. We build a local knowledge base from high-quality open-source hardware designs and use the LangChain framework to integrate and vectorize information into structured prompts for LLMs." + ] + }, + { + "cell_type": "markdown", + "id": "4149bce2-a089-491a-b384-a3b9d5eb8467", + "metadata": { + "id": "4149bce2-a089-491a-b384-a3b9d5eb8467" + }, + "source": [ + "Based on the proposed solutions, we introduce the ChatChisel framework.\n", + "\n", + "![workflow.png][workflow_png]\n", + "\n", + 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xAIgUFBfWaLhkzZox+q2mwUkeOHKlu5+fnq7+A58jMzJTKykp9SC1jQ6ioqFB/icj7oHkzBNsA72UiIiIiIiIiIiIiIiIiIrJrt+CLzWZTf00mk/pLdikpKVJVVaX32ZdPr1699L6m69mzp/qL5o4gOTlZfvrpJ/n1119l/vz59apFlJWVqb9RUVHqLxF5J6Pii/HeJiIiIiIiIiIiIiIiIiKidgy+kGupqan6LTsEUMxms97XdMXFxeqvn5+fqvCyatUqdaIcw/FcCxcurFMNpqSkRP2NjY1Vf4nIO6HqCzgG5YiIiIiIiIiIiIiIiIiIujoGXzpYWlqafsuupZVXtm/frv6icsy+fftUM0oBAQHy5JNPSlhYmAq97Ny5U40DRvAlLi5O/SUi72Q0S0ZERERERERERERERERERLUYfOlgeXl5+i27lgZffvzxR/UX0924caOqDnHMMcfI9OnT5YILLpDq6uo6VWYYfCEiIiIiIiIiIiIiIiIiIqLOisGXDmYETwzR0dH6reZBE0dgs9mksLBQ3T7uuOPE399fMjMzVX9kZKT6C8awQYMGqb9EREREREREREREREREREREnYVPNUqAuFBWVibl5eV6X8t98MEHqrv22mtlzpw5+lB66qmn5Msvv9T7RC6//HK55ZZb9L6me+mll+TDDz9Ut+Pj4+WGG26QGTNmSGVlpcyePVtVgpk1a5b069dPsrOz5ZtvvhGz2Sy///67hIaGqscRkffBfnPdunVyxRVXqI6IyNsllKTJ/uLaKnPNdVLseP2W98utKJL1eXv1vuabGDFYIv1C9D7vtyBzo36r+QYGd5f+Qd30Pu+H9Yz13RJYx1jXnQXf083H97T343u6+fie9n58TzcP39Peryu+p/l+bh6+n71fVz1GExERUetA1iE4OJjBl4729ttvy2uvvab3iQqn3H///Xpf061atUpeffVV6d27t2raaMiQIRIQECAvv/yyWv4hISFy/vnnqw1g06ZNsnr1ahk/fry89dZb4uPjo0+FiLzNddddJ2vXrmXwhYg6jQ35+2R97j69r/n+0e9U/Zb3Sy3Lkblpa/S+5juz21HSPaBlzV+2p7cOztdvNd/EyEEyIbzzVCCcm7ZaW9+5el/zdA+I1Nb10Xqf9+N7uvn4nvZ+fE83H9/T3o/v6ebhe9r7dcX3NN/PzcP3s/frqsdoIiIiah1G8IVNHXUw5yaG0tPT9VvNgxDLM888I3fccYcMHjxYFi9eLBs3bpSvv/5akHEaOXKkWvmQmJio/k6ZMoWhFyIiImpVVdrnjspqW4u7zqRa++fqNTS1w3Q6E1evoakdtpfOxFZd5fJ1NKXDNDoTvqeb3/E97f34nm5+15nwPd38ju9p78f3dPO7zvSedjX/Te34fvZ+fD83v+tsx2giIiJqHUadFwZfOhjCKY7S0tL0W83j7++vmjhKTU2VRx55RJ577jm57777pKioSHr16iXDhw9X45WUlEhurj0tf9xxx6m/RERERERERERERERERERERJ0Jgy8drFu3bqr5IUNLgy9QUVEhTzzxhCxZskRycnIkIyNDBgwYIFOnThWLxaLG2bp1q1itVomJialXdYaIvA+rMhERERERERERERERERER1TLOoTL40sFMJpMKpRhQiaWwsFDva54NGzbI3r17xWazyQknnCCnnHKKCr2EhYWp+/EcO3fuVGV/LrvsMvHz81PDiYiIiIiIiIiIiIiIiIiIiDoTBl+8gGNzRwijJCQk6H3Ng6oxCL1ERkbKwIEDpU+fPhIYGFiTdkIwpry8XDWJdM4556hhRERERERERERERERERERERJ0Ngy9eYOzYsfotOzRD1BIRERHqL0I0ZrNZVZUxpKamyp49e9RtVHsJDQ1Vt4nIu7GpIyIiIiIiIiIiIiIiIiKi+hh88QJHHXVUnZPaGzdu1G81z5gxY9Tf3NxcKS4uVrcBVWBWr14tFRUVMmTIEDnrrLP0e4iIiIiIiIiIiIiIiIiIiIg6H59qlAVxoaysTDWH01o++OAD1V177bUyZ84cfShBVVWVXHLJJTWVWMLCwmTu3LkSHBys+psqJydHzjzzTLX+zj77bOnevbsKvSxbtkz27t0r/v7+8vrrr8uoUaP0R1BDsBzffPNN+fLLL/Uhta6//nq5+OKL9b7GJScny6OPPio7duzQh9R6+OGHZebMmXofUV033HCDCq5dccUVqiMi8nZlVVYps1Xofc0X4de8z0MdobLaJkWVZXpf84WYA8TsU1uxz9vlVdQGrZsrwOQnAb4Wvc/7FVWWauu7Su9rHrOPr7auA/U+78f3dPPxPe39+J5uPr6nvR/f083D97T364rvab6fm4fvZ+/XVY/RRERE1DrQAg5yFQy+eImXXnpJPvzwQ3Ub1V8eeeQROf3001V/U6Cay2OPPSY///yzCtCcd955kpWVJWvXrpWMjAyprKyU22+/XS644AK1EVDj8F548skn5a233tKH1HrggQdUIMFTCQkJctNNN7ms6oMwEoJKRK4w+EJERERERERERETk3X5MXSXFNvdBnmBTgJzdfYreR0RERC1lBF/Y1JGXOOaYY/RbIsgi/fDDD3qf51JSUuS2226ThQsXqmnExcVJZmamLF68WNLS0lTo5eqrr5Zzzz2XoReiTsaxOTQiIiIiIiIiIiIi8j4FlSWqQpO7DvcTERFR62PwxUuMGTNGevToofeJbNmyRTVN5AmEWp555hm57rrrZN26dVJaWqqGJyYmqhBMQUGBWCwWefrpp+XSSy9tdhNKRNRx3BTnIiIiIiIiIiIiIiIiIiLq0hh88RIBAQGqWSKD1WqVxx9/XLZv364PqevgwYPyyy+/qDALmo768ccf5fDhw6qpI6OaC6ZRXFysTpjjdu/evVXzR0RERERERERERERERERERERHAgZfvMjs2bMlIiJC7xPVTNG//vUvueuuu+T111+Xd955R+6//3655JJL5Oabb5YXXnhBfvrpJ0lOTpby8nIJCgpSj7PZbBIVFaUqyPj5+alhVVVVsmTJEjW9J598UtavX6+GE1HnwKaOiIiIiIiIiIiIiIiIiIhqGa1mMPjiRUJDQ+Wcc87R++xVYNCM0fLly+Xzzz+Xjz/+WBYvXix79uyRlJQUKSsrU49BhReEXdAPM2bMkGeffVaFXiorK9Uw+PXXX9W0UCnm//7v/+SJJ56QVatW6fcSERERERERERERERERERERdQ5G8QAGX7zMxRdfLKNHj1a3UaVl0KBBMmrUKOnbt6/06tVLYmNjVTUXdBaLRbKzs1XoBcaPHy/PPPOM3H333bJgwQIVjjESTnDyySeryjAlJSWSnp4u8+bNk4cfflgeeughWbp0qT4WERERERERERERERERERERUefgU+2YjHCA6iEISbSWDz74QHXXXnutzJkzRx9KzrA6Dh06JHfeeackJCSocIuvr29NgAVhGHRGP0IvEyZMkAsuuEAFZsLDw+Xdd9+VL774QoqKitQ4cNZZZ8nw4cPl6aefVk0iTZo0SZKSktRzoTIMKsdgOjNnzpSTTjpJfxQB3gtoHuqtt97Sh9R64IEH5IYbbtD7God1etNNN8nGjRv1IbXQnNXZZ5+t97mH9Y9msPbv3y+HDx/Wh9qh+k///v2ld+/eEhkZqbYdTxUWFqr5w3QdKwX17NlTBg4cqEJXnkyvtLS0zuMNmLfAwEC9TyQ3N1cSExPVNhgfHy/Dhg1T2y+5hu3mzz//lCuuuEJ1RERERERERERERORdPk76QworS/W++kLNgXJp75l6H9GRKb20WH4+uFfK9Qv3nc3qM0AGhEXqfdTROnp9Watssjs3WworyiXUz1+GRkaLxdek33vkami5+5tMcka/wRIfGKwPoYbgHHRwcDCDL94Iq2Tv3r1y8803S1ZWlj7UrkePHirYgK5fv36qIkxcXJxERERIcXGxvPjii6p6C0IMBqzozz77TP73v/+p5o4GDBggJ5xwglRUVKgAxcGDB1UIBmEFBGAmTpwos2bNkunTp+tT6Nq8JfiC+UBTVV9++aVs375dvT+xDp35+/urMNOUKVNUgKp79+76Pa6hOS1sH9g2cnJy6r3vMS1ME9O75JJLZNy4cQ0GYD755BN57bXX9L5a119/vXo8Kg599dVX8umnn6rwi9VqVTskBLbGjBmjj03OGHwhIiIiIiIiIiIi8m4MvtCRAmGEIv0clNnHR0It/mJvTKRxu3Kz5N5Vf0ixi3NY8O/J02Rq9956H7UGLOtybZ1BIC5EN5nVbU901PpCQGHR4YPywc7NUlBRLlXV1eKrbWthfv5yxfCxMqNnP4+3uc6ooeUe7OcnT06ZKcMiY/Qh1BAGX7wEmio6cOCA6lC1xYCqHjNmzKip2nLiiSeq4ABCCKgCgyCC8RchhDVr1sgLL7ygqmdg3RlQ3eXf//63+nvPPfeo0AGmhcAMoGIMggcYjlAGAjdY72FhYSrocNppp8nRRx+txu2qvCH4gsoub7zxhsydO1fy8vLqrGN3EGD673//q0JSrmDdL1q0SG032P4QlsJ25w62IVSRufHGG+XCCy+UgIAA/Z66Xn31VXnsscf0vlpYVldddZW8/fbb6rUg9OL4fD/99JOaZ3KNwRciIiIiIiIiIiIi78bgC3VGuWVlsi4zRValHZbk4gIptFqlWvtn008hI3xg8vEVH+1GmMVfegSFyqjoOJkU1116BIdq99WNJ2zPyZTblv8mRRVWfUhdT0yZKSf07Kv3UVNgnaQUF8qSw4myNTtDVQ2x2mwqNFKloiSiwiPa2hI/k69E+gdI/7AIGRvdTeviJdLFub2OWl8bs9Lk0XXLJL24WG1vBh/tX3xwsPzfpONlfEw3feiRp6HlHuJnkRemniIjo2L1IdQQI/jieTso1Gq2bNmiwgEIslxzzTXy4IMPqlAFQhEGI4xiQJMwWGG9evVSFV7QJAyajdm2bZs888wz8tBDD8m+ffvqBCJQBeapp56S448/Xr799ls1vb59+6rOYDKZ1HSioqJUU0mo9DJkyBAVgliwYIE8/PDDahpo/oY6Rnp6uvznP/9RzVehOosnoRdoKMSC0Mv3338vjzzyiNoe8/PzGxwfsP0ggPPcc8/Jjz/+qKbRVCtWrFDVYBD4auz5iIiIiIiIiIiIiIiIqPUhQLE2I0XuX7VIblj6i/x3yxpVfWNHTqYcLMyTxMJ8SS4qUF2S1mFYQkGebMvOUOO9vWOD3L78N3lqwwopa8b5ImqaksoK+e7Abrlp6Ty13D/Zs1VWpx+WvXk5at0cKqpdX4e0dYdh+7T7NmSmydyDe+X5TavUekbTOt4AMZcFyQmSXlxUJ/QC6MfwuQf3iI3nEqkJGHxpJ6WlpfL777+rkMt9992nmqvZsGGDpKSkqGADql8g1GBANZdRo0bpfaKaI8Lj0DQR7NmzR2655RY1DJUyMA3HIMHIkSNVIGby5MkqbLBq1SoVcsE0UTXGmY+Pj6oeg4oeEyZMkJNPPll69+6tposqI3fffbd89913+tjUXhAu+eWXX2TevHl1mq8yhISEyKRJk+S4446TY489VgWjGoMiT2gO6/nnn1eVXpwDLNgGUOUH08R25AyhlZdeekk1u9QUaEbpt99+U9s6NR3eo0RERERERERERERERC2xJy9H7l65QB5ft1xWpCWpkEt2WamU2Sprqry4g/sxXm55mRwuLpSkwgJtGMMJbQXL+5fEfXLTknkqbITgEZZ7vrVcNUflHBpxhHsqq6pUUzpZZSVqPWeW1hZd6EjYhhIL8tzOPYanFhfVNN9E5AkGX9oBmie59dZb5dlnn1VVVDIyMiQ+Pl6mTZsmQ4cOVeOg4srYsWPVbUDzRWiiqEePHqq/srJStm7dKq+88orqR9WN1atXS2pqqhQXF6thgCaKbr75ZlWlZcyYMSpY8+abb6oqIajk0r17d31M13ByHU3YdOvWTYUfTjjhBNXEDYI3qFKDyjLJycn62NTWsrKyZPHixXWq/xj+8Y9/yNdff63WC4IoaNYIVWFQ3QfbTmys6/JXqNryzjvvqCpCzlVXrrzySvnss8/UdoZpolmip59+ul6gBo/FcyPM4ilMF1VmiIiIiIiIiIiIiIiIqH1VVtnk6/075IFVf6hqLxl6Mzkt0VDwoitCUAUVcj7Zs03uXPG7Ws7NhXDRE+uWy6vb1sme/BzV31gwqTHesr78fU0SHRCk97kWpd3vbzLrfUSNY/CljSH0guZkNm3aJEVFRdKvXz/VnNAxxxwj/fv3V8EVwDCEUzA+gg4YF00SPf744yoUAwi/LFy4UD766CPZvHmzVFRUqOGAaV133XXyxhtvyHnnnacCLmjPCsEFNKGEKh4I1qDqiycQvEHgZeDAgXLSSSep0AxCDgjuoNkdhl/aB5b53r31y44dddRRcumll6oKPgilICCFDtsBKsBccskl8thjj9ULOqG6CyoPrVy5sl7o5YILLpAbb7xRTbNnz55qetgGzz33XLnqqqv0sezw2Pnz58uOHTv0IY1DpRdUrRkwYIDcf//9qpIQtnVUgcF2GxMTo49JRERERERERERERERErQVN5by0eY28u3OzJBcXSoXTOSJqPizbFalJ8tymP+WaP35STRF9vHuLCr2g2kpzJBTkyv2rF6lmpXLKSqWqhYEXb+Pr4yOz+gyUUD+LPqQuDD9Nu9/E1hCoCRh8aUO7d++WRx99VFV4QQWVU045RQUWEChAqATD8/Ly1LgIAFxzzTVqfARLUNEF4ZMRI0aoZoYMaDLp/fffrxN6QXWPF198UQUXBg8erJq/AVR6WbRokQo7jB49WlWDaSqEZ/A4VH9BWAfhm/Xr16uKMgy/tD2sb1RocVZeXq6aLMI24gzrLDQ0VIVX0HyVI2xzf/zxhwpZORo+fLhcfvnlKijjPE1sT6hOhHEcodIQAljOAZqGIHyFMNdll12mbiNQheaU0LSWUd2IXGNTR0RERERERERERERE1FQIZrywabXMO7Rf8srrnh+ilkEVlrtXLpSnN66UeYn7VTNSRlNEzQ0X7dWm8di65apZIzQJdKSaENtNbhozWSL9A/QhdujH8IlxDbdiQuSMwZc29NVXX0l6erqqyDF9+nTVvFFgYGBN1RUECozQAMbLzs5WQYXMzExVlQPNFCHEMHXqVNVskcEIywCGI1CD50BAxTg5/uWXX6qmZRCcQLBg0KBBzT5xjsdhvocNGybHH3+8+Pn5ybp16+THH3/Ux6C2gm0EFVKc7dq1SwWb9u3bpwIwrmC9Oa9zjI9qL86OPfZY1eyWqyANYNt1FUxB+Mk5RNOQ2bNny5QpU9S2arwPMI9oXgvbFREREREREREREREREbUONG/0/q7N8sfhBBWAaQwqcfQMCZVpPfrI34ePlRtHT1LdWf0Gy6S4HhLhFFLo6iqrq1TQJbO0RC3fljYlhOanXtqyWgVoKj0IzqDJoOGRMXJqn4Fy3ciJal1dO3KCnNirnxqO+71VgMksJ/XqL/+bfro8e+xJcvu4KfLS8bNUP4bjfqKm8Kl2c9YcJ7NRVaK1fPDBB6q79tprZc6cOfrQI9fy5cvlvvvuU8GT008/XVXfcIbQy86dO9WJ//DwcBVyQNDl+++/V00d/f3vf5ebbrpJjbt06VK57bbb1G1HL7zwgqrG4QihF4Qi0LQMqmqgQ3ClNaDiS1JSkmqeBuGFp59+WiZPnqzfe2TCe+HJJ5+Ut956Sx9S64EHHpAbbrhB72scmp3COt24caM+pNbrr78uZ599tt5nh6aOUPHn559/1ofUwvYSHR0tJ5xwgqqYMn78eNWkVUPee+891cyQM1QZQpNGzkEZA8JWeK0IZDnCto3qRNh+Da+++qpqZskZtkNUJkLAhprun//8p6xYsUKuuOIK1REREREREREREVHnVVJSon7Dx0WmdOTIGG6Wygau8TRXiMTtPHIrOHRFOE8TFRWlzs/gr3Ml/o42/9B+eXHzaimwNnzON8TPIn8bNFymdu+jmpnxN5m1zqSCMGCtskmFrUrKbZVSWGGVVenJ8lPCXukWFCzPTT1Fgs21G/72nEy5bflvUqSN58oTU2bKCT376n2dW2ZZicxZ9LOklRTpQ+pqymu12mzyzKY/5TdtnTVWLaZfaIRcOnS0DIuMkUBtXVm0dYX1BTjxj/WE9VVWVSnpJcXadrBPlh0+pB7z9+Hj1HiGjl5fmF8EtPCaLb4mMfn6SvNKOXQuDS13vB9f0N5XI6Ni9SHUEOQrgoODGXxpKzfffLOqrIEqKajYYlS3cGY0WYT7jWobaEoIH3YRLEEIBqECrIvrrrtOtmzZoqpvoEIMViKaHELwwYBgwyeffKI+ME+cOFFGjRqlqmm0JoRf8NoQ2kHTTc8++6zamI5U7RV8wfTPOOMMvc8OzVR9+OGHLsMqBix7bCtxcXFy0kknyWmnnaa2O+fqLVarVa2rV155RR9SC01xIUjjDuYDzSSheSNHaALrv//9r/Tu3Vsf4j748re//U015YV5paa75ZZbVKCOwRciIiIiIqLOIysrS/1Gs2PHDn0IEXUmxknMiIgI9Rstmhcnag783r9//351oSMuMkT1d9zG+QHn31ypc+t94mjxC3QffKgoLZekhVv1PjoS4FwdOpznQ2eEYIYPH67OofXp00cfs/2lFBfJ3X8ukP35ufqQ+hBsOTq+p1wzYrz0DA5VJ9yNsIs7VdXVUlxhlZzyMkkqKpBJ8T0kwKGyCIMvtZryWhcfTpTH1y9Xy9YdVHC5eOgoObXPIIkNDFIBpcZCIgiUIPiEajIIMI2NjtfvsetK68ubMPjSehh8aUPbt2+Xf/zjH+o2KnjgINcUWO4ff/yxCpig2sf555+vhhtVX9AkDD4QozoHwg5XXnmlGuf555+XuXPnSn5+vgq8TJo0qc2SpXgOVCHBvGIeUS3kSNVQ8OX666+Xf/3rXx4v54aCL999950KkjhDyAmVddB0VUMQdMGXb3wJR8jk8ssvl9jY2h0iXgcqu6AaUGuZMGGCvPzyy9K/f399iPvgC97799xzT6sHsboKBl+IiIiIiIi8F05iLlmyRAVdcDITYRec0EQlYFxMgr9E1PngBKbjyUz8oI4r+2NiYtTJTHQYTuQKjgerV6+WNWvWqItI8Vs6jgn43d/4GxnmJ5GhFhkxwP1FidS5WIIDxcfX/Wno6qpqsRbzc8GRJC27XFKzyiQtS3uPa+vXOHbgXAiOG8cee6w6XuCcXXvCyd/Xt62TT/dsF1u16+ohCLic2W+wXD50jHQLCmk08OIMz4EqJRYTKnTUPpbBl1qevtbc8jK5988/ZEt2uj6kPoQh0JTRjJ79JNTi3+SqKAgsofkkVIdxxOBLx2DwpfUw+NKGXnvtNXn77bdl4MCBMnPmzHqVNzyBkAs+DCMJiqaLEHZB5Y+XXnpJ3Y+rDJAYRZACwRo0OWM0kTRixAh1AG2t5o1cwWazYcMGlVRHWANhhyMV3gcIjLzxxhv6kFqXXXaZPPjggxIUFKQPadimTZtk9uzZ6v3lCNVWvvjiC9VckTM0iZWWliY//fSTfPTRR3LgwAH9HvewfWDbQyjJqMbSUICnuTC/qCDjSfDl3nvvVaEfd80pUcPY1BEREREREZH3QWVefFdbtWqVFBYWqpOYjic0LX4+EhnqJz1jA6RbDC8EIeps0nAiM6dcMnKsUlFZpX7nxQlN/FaLH9cHDRpUE4Dp3r27/ijq6vC7PsIuOD4g/KIqulRVypQxkep4EBVmkYhQs4SH+Kngi9nkKwGWpp9DICLvUFFZrY4RZdaqmgBManaZrN+Vp27jeIEOlfpxvDjllFPUSdq2dqgoX25f/puq+uLO8T36yB3jpqjKIY7BlZZqSpACJ6mTiwpkXuI+2ZqdIfnWMqnSBvpp+8a4wGAZH9tNZvUeKJH+Tf8sjWnnlZfJlqx02ZmbJfsLciW/vFxKKu2tcUCoxSIxAUEyOa6HHNO9l8RqtxuC14TXhxAJYH5f3rJWBVdcuWLoGBkTU7fCCgJGCDQg3GCYe3CvPLPxT6mosulD6vLTPoNcN2qinNN/qAQ5NCvVGjpqfTkvS0eullFDsPzXZ6bK6rTDklZSqCrc2PTJIouIoFCUf6AMiYiSMdHxMlybtqUJ5+8xj7vzsuWP5IOyNz9HcstKaqaPJqbw2kdHx8n0Hn2lR0ioR+8mBl9aD4MvbQSVWC699FLZt2+fnHjiierLT3Ogosrnn3+uvkw98sgjamXhr9GE0ZAhQ9SXLHyIRpgCIReEXsaMGSPjxo1r09CLAfPy7bffqvn43//+5zK0cSTAWwThDoRGnKGZKVTaQVNBnkCVHKMakKORI0eqwJS77QXzgPV76NAhVfUDlX3QJFZDEMa544475JprrlFfxhsKviAshbBMU6GiDKq49O1bm/R0F3xparNQVBcrvhAREREREXmHlJQUdTHQ6tWrZN++/er7Ok5qThgWLgN6BEtEmJ9EaV10hEUiQnBC00f8zOh4UpOos8GJTJzQrLRVS0pmmaRll0lGrlW2HyiUPYlFNQEYNO2N5u5xQhO/z1LXharduIARxwV04cEmFXg5ZnSkDOgZLBY/X3VcMPlqnf6XiI4MONtaYdOOGxX2IExRSaWs2pYra3fkyZa9BWKxWNQxAxeTX3XVVap6WFv6aPdWeXP7erG5Pg0sPYJD5NGjZ8iwyOhWDb2Ap0GK3PJyeXfnRlmbkSK5ZaVSihC5Xp0GF1H7+fhKkHasjQ4IlL8OGK6q05g9CCuklxSpIMmq9MNSqM1DaWWFmna5zaaq3zgGLUza82CawWaLhGnraHJ8T7ls6GgVhnFlT162PLx2qRRX2MMzmFZueanb5Rxu8VfNETkK1l7Tg5OnyZCIaNWPIM49f/4h67Tl4A6W193jj5XwZgSAGtNR68t5WTpyXkbuoKmtD3dvUa+hyGpVrwFNO1Vp8+W4RkzavJm1Y26Ati4CzX4ys1c/uWn0ZP1e97B+V6Ymyaf7tktGSbEK1JTZKsWmPYcxfeO1Y7rh/v4yJDxK/jFygvQOCdPHcI3Bl9bD4EsbwYlphA1QwQOVPfDlpzmwWn799VdJTExUQZfMzEwVekBAAV+gjKZ1sI4wHM3h4DmRGG2vpmRQieS3335T83jRRRfJnXfeqd9z5EE1HVehDYRL3nnnHZk+fbo+xD2sK4Rk0DSQs1mzZslzzz3XaLNYWOb4woRyyaj2s3LlSvn9999l9+7d+hh14Qs3nrNXr17qSrMXXnhBdc5uv/12ufDCC/U+zyH0hA9njts5gy9tg8EXIiIiIiKijocLWnChUklJiQq8RIb4ysQR4TJxWIQM6RMs/hY0h4Ifz7XOzBOaREcSIwSDrrTcpsIv63fmyaY9BZJXWKF+bEeHJun/8pe/6I+irgJN3X388ceyePFiKSgokF5xgTJldKRMHRcl8VH+EhxoYgCSqAsqLrVJcVml7DpYpB0z8mXBmkyxWPxl6NChcuONNzb74vnGIEhx18oFsjEzTR9SF6ppXDdyolw4eKRHQZKm8iRIgUDDMxtXqqohjhVYXEGwIMo/QM7qN0SuGj6uwXlOKMiTR9ctlcMIp1da64RcGoNP7qim0j8sUv41/hgZFFH/nF1jr80TzqEGVKPBNBGqcCXS319bZieqyjFt8e2io9ZXS4IfWKu/Htovn+zeKiklhSqE0xQn9x4gDx/V8LldzNfr2zfIspREySkrU6EpT6ACTK/gMLlqxHgVGHK3zhh8aT1G8IWftFoZyhciYIDmZZobegHsFMaOHatub926VZKTk1VVDTRhZIReALfRzAzCMQjFtFfoBVCNpl+/fur2ggULJCMjQ90+EmHZx8XF6X218EMXEvwIojRmx44dKqTiyuDBgyU0NFTvcw/LHONhfo477ji5/vrrVaUYhMkQfHKGpqjwpQsQUnFXchVfxhBgQUCmKR2m15LtnIiIvMefOTtlUeZmtx3uJyIiIurKUA323XfflcOHD0uv6Eq5eFY3eeS6oXL56b1l8sgIiY30l7BgswQHmMTf4svQC9ERBqGFIO39HR5ilm7R/jJ1bJRcc24feWTOULns9F7SL95HXZyIpspdXXhGRy5UZcfFsPjtF7+znnZcnDysHR/+dlIPGdw7WCJC/Rh6IeqiEHqL0z4jThkVKVee1Vtu+Fs/8TNVyvbt2+XBBx9stLJ/c6UWF0liYZ7eV1+0f6Bq5qgtQi+eyCgtlqc2rJANmamNhigAxQKyy0rlx4N7VHM2DUF1l+SiQimsKG9S6AUwdrH2eARRXtyyWs1ne9iWndFgkGZUdDcZHhXTJqEXT7Tl+moOrKfvD+yW17atkwPadt7U0IsnMP+Pr1su8xP3SWYpmjXyLPQCqCyE+frf1rWyKi1ZH0rtgZ+2WhGqcaxevVrd7tmzp/rbEghaoLNarRIZGSnHHHOMyyaMkGLCcJRJa28IviBBhbZKN2/erA898vTp00eFi1xB8OXDDz9UbXm7g6o4r7/+uuzfv18fUguBFVTxaWqbjgicYLtAs1dXX321zJgxQ7+nFio3GYEkhKlQEchVgGfZsmWyd+9evY+IiLqixJIM2V+c6rbD/URERERdUVJSkqpyi8q8aPb5jKnxcselg+TM4+OlT7cgdULTwhOaRF0OAm5RYRYZ0CtIztL2B3deNkhmTYmVvLw8dZHgbbfdpn4TpCPbV199papf41hRWlqqTmpfdnpv6REToMKQvgxBEpEGzZxFap8ZZ06KkX9dPkhiI0ySmpoqzzzzjCxcuFAfq/UkFxdIXgOtegyPipUewY1fjN1WfkjYLZuy0lSTNE2RW14mX+zb0WD4omlRF9cQckBlk492b1FN2rQlzO+uvCy3IR1U5zm+e2+x+Jr0Ie2vLddXcyQXFchX2nQRSHHTsE2LYH5f2bJWVqUnN3veMV+pJUXy6tZ1sjev8eIJ1Dr4rbwVIaGJq35QhaVHjx760OZDhQ6EGU477TQVekFbsd4GrxVBCoR+tm3bpg898iBgMm3aNL2vLgRe3nrrLZXqRwgGX3IwDB2aIEIoBiXr8OGlwkU7dVi3o0ePVsEUZ/v27VPlMRtqdgxVYDB/7raP8PBw/ZY9qDRhwgS9r9aBAwdUMAfNZjUG8/Lnn3+qK1io/bjaPoiIWlNltU0qGuhwPxEd+YymNdF8h9EhiN9WMG3H58JzYx6IiLzF0qVL5b777pMtW7aofdSc2X3l0tN6qWYrQgLN2nc1fUQi6rJwQiokyKz2C1ec2UcuP6O3CkDgt1I0/b1kyRJ9TDrSvPnmm/Lpp5+qk9cDegbLs7eMlJMmx6qT20RErgT6m2Ts4HB59PrhMrBXsLpwGedm/vjjD32M1pFYkN9gtZORUTHi10HVXuBQYX5NiALz0TMkVIZEREmopbbFC1cQJtiRkymJ2uM95e9rkklxPeT6URPl+eNOlv9OO1V1L06dpZrhiQkI0sesC/O3IjVJDhe7v+i9NZTZKiW1xH1lGTR5MygiUu/rGO25vjyxMClBkooK9L668LlsbEy8PDDp+Jp1je7fk6fJ7IHDJC4wWB/TNbxrvj+wS5amJqrKLc6M6T969Any3olnyZszzpQ7xk2R3iH1z9Hi9R8szJPP920XK3/rahemhzT67TrQXI/NxQptLlQDQYeqGWiu50g0d+5cVfEFTcCgfb7WgGAJmrZBVRAEHLwNTsbjKoaUlBRVseTss8/W7zmy4HUiXIKKLQcPHtSH1kJlFYRGVq1aJT/++KN88cUX8tlnn8m3336rgiu4usNVeAXr9fbbb1fNWrlav3iuf/7zn+q9gx0kQixozsoYF8NwtRkCN19++aUqpelo/PjxcsEFF0hERITqx/aEx+CHO8cTGDi5gMAOtl+89/EcGBfjoEOTTgjhoFzn888/Lxs2bJCpU6fWTNfR2rVr1fSdITg0efJkvY+aav78+WobGzdunOqIiFrbloIE7QO4+7KQ/r5+Mia8v95HREcqhE9Qmv+ll16Sr7/+WnUIT6OpzbawcuVKdTW08Vz4TIrvjPgsSkTU0dasWSMvvviiuvAj0OIj/3fNUDlmdJSEBjetYisRdR04odm/R5D07RYoKzZnqwvjcLEkmjnv1q2bPhYdCfD75/vvv6/W8YlHxcpN5/eTftq6R1UHIqKGoDlMVIQaPzRcikptsn1fljpW4JwLzge2hp8O7pG9+a6rTODE/bkDhkr/sPrnd1oLKnH8emi/WKtcn2dGuADzcVb/oXLX+GPlrH5D5KTeA+S0voOkf2iEqrbi7rEIYAwIj5CRUbH6kLqM547wD5Crho+Xa0dN0KbdX4UVeoeGS/fgEOkWFCLdtW5IRLRMju8hO/OyJKesVJ9CLTShg5DHyKjalhSCzH4yIba7nKrNK+b3mPheqhoKAiyuXD1ivPx9+Dg1rtGdor3WAeGRYjGZpKCiXFUvKbC6vgA+0j9Qzhs4QgVg2kpHra+GnhfL5tQ+A+sFVUq15fzJ7q2qqpErp2vzdMu4KTIiMkZ6aOsO6xpdH23dj46Ol5m9+sl4bVtABZ0x2l9n+/Nz5eWta1W1GmdYBrMHDJMbx0yWYRExEhcULLEBQeq9NDGuu+zOzZasshJ9bDssu+zyEjkqvme9kFVzXj+5hvPmaBmHn8JaEQIO0BrNHBkQuEDlF3TeKjo6Wv3dsWOHuprhSIX1esUVV7hdvwi/pKWlqeope/bsUR2CK1lZWSpM4srf//53FQhxt34RUkEVod9++0219/i3v/1NTjnlFJk5c6bqTjzxRPnLX/6iyuEhfOQM4zh+qcbz4PnOPPNMfUgtXLmGK9ieffZZNV9nnXVWTXfuuefKtddeq55n+fLl6jVh3oiIiKhzQJjh8ccfl3POOaemu/jii9WxvzEIwb799tt1HovPA10JXq/j63fscFLUU4sWLXI5jbvuusvlZ7mOgEA0PtMi8G102H7aCqbt+Fx4blZ8ISJvkJmZqS78wPffgb1C5PnbR8n4IeESFOC9v88QkXdA9Zep46JV9Q/AfuSpp55q089U1L5QoeGVV15R63R4/xC56uw+0j0GFyuyDBgReQ77Dew/jhkdKdnZ2eockKtWA5oKTfMUVbiv3BpgMkt0QKDe1zGMAME/RoyXoRFRqlpGz+BQFaJAmOKSIaPVOK6gks2eBpqO8TeZ5MphY+WF40+Rs/oPlsHa9BF8QHAE1UrMPnqn3Q6z+MuwyBg5f+AIMbm4ON2mPdfW7Mw6zR0F+/nJ6Og4GRcTr7pR0bFi0ZapO3hNxrhGh8djOoBwTbmb0AxEBQRIkD5uR2nL9dVUaHoopcT9Z6qJcT2kh7a+A8zm2nWtddjuI/0DpG9ouBzXvY+2bQzRH1ELZz1/S9ovaW6mP6VbL7ls6Gg1fWxnPto/vG6EoQaHR8llw0ar4c7yy8vlj+QEvY/aEoMvrSQ5OVn27t2rbrdm8KUziI21p/QQ/EDY40iFijbHH3+8arbIVaWTprryyitVkMaTBK8RqsHJgF27dtXpsN3hBznnEwQnnHCCCqwg4eYoKipK5syZo+53hoAOvowjsGOEd9DhOVC1Bs/jWCmG2g+bOiIiopZAJUcEKxyP76goh7LcqB7XEIRd8RnA8bG4qrGzwGckvMaW/HiE1+v4+h07NAHpyecjVP9DSMbVNFDVrTV+3CIiotaDk9Q4sRkcYJL7rxosfboFitnM72VE5Bl/i68KRDx07TDVj8pRCErQkeHVV19Vv6HGRPjL3ZcPlqgwNm1ERM2D/ccNf+uvKkYlJCTIBx98oN/TfOVVVW6rhwBO1Jt8Ovb0cJ+QcDlv4HAVwHE+94EQwUm9+6nKLO5klBS7bIYGUNnj7P5DpF9ohAq7IJzQEJP2/COiYlQIxhVU8MAyNWB6CM0YgQoEZhp6BixvxwCG6tRj7I8q1NZVWQMtsGB8d6GS9tKW66upEKSpdDof6mhrTkaD9wPCKeEu1ndGSZEsSznkspkwbEsXDhohMYGum8bCOkKgqUdw/XO+mN6O3CxVrYbaFoMvrQSBBPxYjZBBa4QiOpOgoKCa8Abarj2S4bXOnj1bnnzySRk1apQ+tGkGDBgg//73v+Xmm29W1VjaItCAyjB4DpSkd54+yj0NHDhQ3X/ppZfqQ4mIiKirQSBkwYIFsnDhwlZt4tQbIGSCaoRoevLWW2+Vl19+WQWJ2wLCLAgoNwbt/q9fv17vIyIib4ZgqFEV7a7LB0n3GDa/RkRNh+ofE4aFy+yZ3VX/smXLZN68eeo2dV5fffWVai4eTZXceH4/iY/mMYKIWiYmwiK3XjRALH4iP/30k/z888/6Pc1Trf1zdeLem4yL6SY9Q8L0vvrig0JUNRF3rLZKqax2HW5AEzb2wEvjiisqJKW4UPbm5bht5SC7rFRKbW13sRLWlbe3sNCW66upULklyj9A76tvYVKCvLRljaSXFOtDPLe/IFfbHlxXexkYHinDomJqAkuuhPn5S7ybpolSte2siIUF2hyDL63EKE0eEhKiggVdCYIVRnNHR3rwBcLCwlRzQ7hK49FHH5Xp06fr9zRszJgxctttt8n//vc/1bQAQi+NbSvx8fFy0UUXeVRFKDg4WM444ww1X/fee69qOxhValzBcNx/xx13yBtvvKEeh8c3Bq8BFW9Qcq+rVTYiIiI6EqGpQ4RDdu7cqQ85MuCHaARe8LkLbe/jCtu2aj4H7XA3tvzwA8bGjRtl9+7d+hAiIvJWaGr4yy+/VBVRcbIaJ62JiJrLz+wj55/UU44eGaGaiH/nnXdU5UXqnBCKRDgSQfuLT+0pE4byGEFErWNQ72CZ85d+quLse++9p37XaC6Lr68E+9VtCcARmorJLW+bi4M8NSYmTlVacQdVTroHuW8toSkxEVT/SCoqkIXJCfLOjo3y7zVL5Kal8+WKhT/ItYvnyu3Lf5dXt61TlVdcwePbMkiEdeWqeRxDjrauyjq4Ukh7rq/GBJv9pF+Y+5ANqh3NT9wnt634Te5b9YcsTTnk8fLbl58rFVWuLw5E005Wm029d9x1RZVW8fN1vS4RssopK9X7qK0w+NJKjKs8EXzpimJiYtTfffv2qb9HusDAQBUcOf/88+XZZ5+VX375Rd5880155pln5J///KfccMMN6i/6X3vtNfnhhx/k9ddfl2uuuUZVikF4xpNKLwjH3H333eoL1ffff6+mhWozN910k3oOBFfQ5vj777+v7n/kkUfktNNOU48zNXCgBNyPYM3JJ5+sHvftt9/Wew147hdffFEN//HHH9VruP7662X8+PH1mlAyXHDBBerKcecOw6n52qIyEBEREaCpHXwOyMvL04d0fgj0JCUlqTay8aN0a5syZYoMGjRI3cb0N2zY0GBFGcwPgi9Gk0gzZsyoeTwREXkPnNB86623pKCgQGZMilEnq/3M/OmMiFomPMQsN54/QIb2DZacnBx1QhP7Gep8lixZIvn5+XLG1Hg5a1o3sfjxGEFErQNVpKZPjFbBaxwrWlL1xexrUs3PuIMQR3JRxx6HULWjMWFuzkF56nBxoQq0INxy54rf5b9b1shX+3eqpmw2Z6WrKi8JBXlyqChfMktLxNZBVVeCzGa1ztwprCiXnDaqYuyp9lhfnkKTQif16t/gNl5cWSEHtXW7Mi1Znt+0Sq5dNFee2rBSEgvzGgzhHCp0/75YnpokNy2ZLzcumee2w/0bMlP1R9SF911rVb0h9/jJrJUYwRejyZ+uxmjeCScY2upqWm+DIALWNyqfjB07Vk466SQ599xzZc6cOSo0gr/onzVrlkyYMEH69esnkZGRjQZSHKEyS1xcnArZTJw4UU3rr3/9q1x33XXqOa6++mo5++yz5YQTTpARI0ZI9+7dVSinKQICAtTjEMhxfg1XXnmlnHnmmWq48RqioqLEz8/9AQXVf4YPH16vM6oCERERkXfBFe1z586VxYsXd5nPcS3Vv39/6dWrl94nsnLlSjl8+LDeV9+hQ4dUaXsDmp1MTk7W+4iIyFvghCZCk6MGhsrV5/RRJ6uJiFpDbKRF/n52HwkN9lPVAletWqXfQ50Fmi79448/1O2TJsdKaBCPEUTUugL9TXLu9O6q6aN169apCrPNgUtoewQ3fJH+jpxMsXn5b0AIODQHqnu8t2uT3LXid/n+wG7ZnZejKr4g3IJqIOXa/TYvCiAEmv0ksoGmewqtVjlYmKv3ea/mrq/mGBvbTc7oO7jR50SFlozSYtmfnyu/Jx2Qf61cKP9evViSiusHXMq1cTO1cd3BtnOwMK/RDqEb6jgMvrQS40rShgIBRzIj+FKB9vD0Zp+6EoRgECBBc0EItyAcgr/ox/CmhF3cwTQwLVQVwvTRYbkHBQWp6istrQji6jWEh4er6WN4V2vCi4iI6Eh3ySWX1FTtQyndL774QlV/aQ1FRUWqqYiHH35YhWrRIVD70ksvqdLu+MzoCBVRUCEObVkbHa5uysrK0seoVVJSIgsWLKgzLpozwpWXxjScy8dnZmbKr7/+WjM+KrS0BD6DIRBsSExMVM/pqk1mhInWr18vGRkZqn/06NEyYMCABivEOMN08RoQUHr88cfVujOW6z333CMffPCBWneeBJcwDsZFRQMEnY118/LLL0tCQoJH08DyM5YlOix3V68HFwc4jjdv3jzJzW3+jzVYDggMffLJJ3LLLbfULAPcxjDc5+3tYhOR98I+yzihOX1CtESHt88Vi0TUdYzoHypHjYhQn4UXLVqkD6XOAmF3VOqZqK3Dgb2D9KFERK0LoZejR0aq79gIZTdX31D3TcHArrwsySwr0fuOHGjG6cVNq+XLvTsksTBfiiqsHv1OgPNf7RnccITKJXGB7o8rqBSyJv2w1weV2lOgySyXDRsjFwwaIf4NVMsxYAvAtoEA1PLUQ/Lg6iWy3qkyC6qxWDu4SSlqOZ7JbiUICEBblFLvDPDjvxG8wA//REREROTdRo4cKaeffrreJ7Jjxw7VdCJCKM2FHxNwVdK9996rmmdE2GH37t2qw/DPPvtM7rrrLtWMomN5d1SswwkANOuIZiTRoflF/MjjHMTYunWrCn8Y46FJSH9/f/XcCNtgGF6HIwQ9XnnllZrH4LW2BILBqPhnwLxv2rTJ5bJDE1K4z3gdY8aMUc1SegrfL/B6brzxRrVMcBvTM5YrXjOWJ5qqfPvttxsMlmBa33zzjQrLoMT+ihUratYNgiP33XefR1cfY/kZyxId5sFoxskRwjqO43333XcqFNUcmPevv/5abrvtNrWdYNswlgFuYxju+/3338Vmc90eMxFRQ7BPxLGpd3ygnDDJHgwlImpNaDpt2gR7RWSEpvE5hjoHfJZHWAnfOU6YEMNm8IiozeA0m3GsWPTHH+p7dXP0DgmT4AYu1E8rKZblKYf0viMDwg3zEvfJguQEybeWu2zSJsTPIkfF95Arho2Vf40/Vl46fpa8PfMseWHqyRLl37TWFFqLSVvpg8Kj9D7X1qanSkLhkdNEeWuIDgiUS4eOkaeOPVEmxnbzOLiEyi578rLlv5vXqKauHPFSqs6Pn9BaiVHxpCUnCjozVCMxmnk6ePCg+ktEraelFX2IiIicISyCahkIYgCCCwhVIETQnKoZeAyugnz00UdVsz64ct7xszHCCKjKgqYxP/74Y/nqq69qQuO4smbSpEmqGgoqo6BLT09XwRnHJoQQIkHVEEzbGG/KlCkqxINjJUIVGIbncYTnwY9FxmOM520uPBeamURTkIbly5erJo2c4bMxKtIY0Hwlqul5AvOJQMoLL7ygShxj3vEaHcNApaWlqv1vhM/ff/99eeONN9Rycoblj6o3//3vf9VJFgRkjLCKsW4QKkIlmMbKKWO+jGVpzJOrbQbTdRwPz+FJRRlnxnLAvCN0g2ZIHNchbmMY7kNVoT///LNZ2zARdV2OJzSPGxslIYFsvoKI2saYwWHSv0eQupIfVQypc1i9erXs27dPwoLNcuyYSH0oEVHbGNYvRMYNCZcc7Xs7wtnN0SskTLoFuW/uqFL7/PtDwm5JLW7exSneKKOkWL7XXhMqezjz8/VVYZdXp58u90w4Ti4cPFJO6TNAxsd2k+GR0dIvNELMHdjqwejoOPFvoOWIrLIS+Wb/TrXeyA5nzNBE1ITY7nLfpOPl5eNPldkDhjfYbJQBVXQOFOTKTwf31lTSCTCZJaKBxyJcc/2oic3urho+TuKDgvWpUVth8KWVGD96o63PlpZO76yM8I+rH/yJqGV48oaIiFobwhuDBg2SCy+8UDV1CAgmIJDSnM9zeAyqiOAHYSOUcP7558u7776rmlFCxY/Jkyer4QhmYPiaNWtUP6CZxfPOO0/69++vDxFV2WTx4sUqQIFj4dq1a+WXX37R7xWZOnWqnHXWWWr+EZ6JjY1VzzF06FB9DDt8TkXgBPehQ8WWlsDrM57LgKAOmjRyDHZUVlaqeTaqnOA7gxHSaQymg6DKO++8o0I7xnSxzq644gp56KGHZM6cOXUqzyDM8u2338qPP/5YrzkphF0+/PBD1XyUMS0sF4SfHnjgATWtIUOGyN69e5t9RVlbwHpHqAjLwZj37t27y5133qkqCCEQg9sYhvsQNMIwhKOIiDxlnNAMDjTJDFZ7IaI2FGDxVc2pAYIv+JxL3g/hSITGp46LlqCAljdpT0TUEIufr0wbH62+DxtNcTZVuMVfjo7rqfe5llhYIG9u3+AyKNIZbc/JUM0buYKQywWDR8rA8EgVCMLyQRNDZh9f8dH+VVVVS1V1x4VKBkfYwzfuIKjxx+GDMvfgXlYlcYLAUndtnY6JiZerho+VV6adJs8ed7Kc3Lu/ahLJHZu2TNekJ0ue1f4bJirvhDcQfAnT7jt3wLBmd2f2GyyRHVRVqCth8KWV4Efvc845R/3AjCslu+IPrUbwhU0dEREREXUOfn5+csIJJ8isWbP0ISIbN25UTdKUlHje1jM+AyOkgSZzjFDF3/72N7nuuuvU52RUcjnxxBPl8ssvl5gY+wlFVCnBlUu42hUQXMF4eJwBARM0XYMqMQjL4DkKCwvVfQg6XHzxxdKnTx8VJEH45frrr5cnnnhCBW4cDR8+XIU7cB+60047Tb+neTAPmN+jjjqqJjSE142gjmO1FVQhQRjGgGXhaTNHCJ/Mnz9fLScDgj6PPPKIXHvttXLmmWfKlVdeqZp9QmDIgHnD+nOswogf6fFjGZp8MmD5oWmj22+/XX2PwbQefPBBVUHHWIfeAMsBr8dYDlje2K6wjlGtaNy4cfLXv/5Vzj77bHU/5h3NNaH5ACIiTxknNI8ZHSU9Yz2rykVE1FwzJ9s/D6N5NVRKJO9nfLZGVTAiovaA5o4C/E3qezwqqDYVmn2Z0aufRPj760Pqq6yukqWpifLqtnVSVFG/+WJPVWjfw70hjLEtJ9NlRRSLr69M79FXIiz+qkqIKxmlxS1aBg2xeRCowbyd3HtAg831FGrfVz7YvUU154QgTHPgUVhfRyIEV6ICAqV/WIRMjushN40+Sp4//hQZF+P+d7isslJVTcfQJyRMv1VfclGB2r5C/SzN6tDMFuaR2haDL60EV43ecMMN6sd6/HiPH01Q+aUrNX1kBF/Y1BFR6/PkynAiIqLmwGe4Cy64QDXdAwiboEJLU5qLQdgDn32NSi8ItyBcgpCH2WxWxzE074PPyoMHD1bjAKqQOAY7MA5COAjjGLZs2aIqfuCkAJphMqBSCYInmD4giBIfHy+9evWSyMi65ccDAwNV0AP3oTM+tzaXEQxBhRTHqi9o0sgxBL5///6a4AsCG+PHj1dhI0/s3LlTVSAwYJledtllahmiOg6mh9cxYMAAVbXHWH+A5922bZveZw+PIJTkWAUGQZEZM2aoyjUhISFqWqhGg+cwwkne4MCBA2pbNGB5T58+XTWzinWOLjw8vM56wPcxbFtGU05ERI1JSEhQf48fHy0mE797EVHbio6wyPD+oeqzNj7zkfczTjr3iueV2kTUPlCJMCrMT32vTU5O1oc2zaCIKJnWvY/e51ppZaX8emi//Hv1YtmandGkAEuhtVw+2bNVXti8WspslfrQjpNbbr+wypnZ1yRhFvcBILzmpSmJUtpGVdgO5NdvjtoZAi8I5/QJCdeHuIaADqr0vLhlTZ3ARmPwGlEN56kNK+SXxL32gUcwNG0VGxgko6Li5JoR4902YYQAkWNYalhkjKoE5MqhwgLZmMnqwt7KOIfK4Esrwg/Ejz32mLrSFIl9VH7BFar4sd7xB/0jFX58hq7wWomIiIiOFPhiMGzYMFVBw6hegiALmjw6fPiw6m8Mqh2iSR8DQiYo275r1y71Y77RIRTiWM4dzUo4VkgBhGUwL5gGIEzz8ccfq2aUjCaDEIyZPXt2i5ssaikEbCZNmqT3iZo/LAc0cYQfp3DbqJyDJonQBJMnYVYEa9DkkGPVHVQ2QTDFCPoYML2+ffvWCb4g4IIwuhH8QOUZfCcxYD0fffTRNevbgGljOgj0eAOcDEKAxXE5YPtAkMdxu8J25vwdBFWCjCAWEVFjjBOavXlCk4jaAU5u9Yqzn4BBc5nk3VBREZ/zTb4+Eh3mWYidiKg1xERY1F9Pf5tx5u9rkvMGjZCewfZzd+4UV1TI+sxUeXTdMnlg9SJZmJygQhXOVUWsVVWSUlwovycdkH+vWSI3LZ0nn+zZJgkFuc2uQNKa3M0DQjkNhU9WpyXLfO01eXrxV1NtzEpTIaHGdAsOlouGjFShDXcwjwi/zEvcK3es+F3+u2WNbNKmj3XoDMP25ufIp3u2ym3LfpW7/1yorbsEySkr1cfonLAssY160kQXKqz0CA5pcJk6GhweLQPCXV8sV65tR+/t3CS787L1IY1DqGZLVrrL9UOty3j/MvjSynAFKX6of/LJJ6V///7qxxOUPP/tt9/Ular4ARo/hB9pcOA1fkx3LE9PREREnUO0JUxiLeFuO9xPRy6LxSInnXRSnSaP1qxZIz/++GNNU0QNQfDFMZyAQMvDDz8st912W50OzQ05ViJBWMGxCgmgggeqd6ApHwNCDJgmIBBzySWXSI8ePTwKkbQlk8mkgi+9e/fWh4iqrIKgCZYJlqEBQRNPK6ng+4JzkAPVbJyDKgZUynGeNkIfxpc+nFApLa39YQPzi+m5Wn6oSIPpeQNsG84lndHc1Z133llv23rhhRf0Meyw3XpTk01E5L1w4RKq9Vr8fCU20n5ygYiorcVH2a88R6CXvBs+l+NzJSr1sCoYEbUnI/iSkpKi/jZHv9AImTNqompmpSFo/gZNuaxMTZKXt6yVW5b9Kn9f+KNcsfCHmu6aP35SYYtXtq6VZSmHZF9+ruSVl7VZYKSpIizuq3p8vm+7rM1IqVPRBqEEBChe2rKmRWGQAJNZotxUFIGduVny/ObVklCQr5pTyiwtkZ8P7pXk4gJ9DDuTj6/M6Nlfzu4/tMEmjwBBCiz/udp0Hlu3XK5b/HOddYUOwx5YtUg+3rNNNmSmyaHCfCn1ICzi7cqrbPKp9ppu1bbRj/ZsabDyDcJafyQflHw3F0ahEgwqwxhC/fzkxF7um5w6WJgnj61dJl/v3+k2zIRtDOGk7xN2y20rfpNXt62XUi+oiNRVMPjSBsLCwlT57Yceekguvvhi9cNyfn6+aotvxYoVKgSDH8Tx431nrY6Cq0fxIzSuRF28eLEqO4+DL656vfrqq/WxiKi1dPSJPSI68k2NHiknx4132+F+OrKh+ZzzzjuvpnIIghLfffed+tzaGOdgNx6LUryo8OLYIcDiGJDBD8iufiBBwAPVTQwYz3gOhHQwrwjIeAOE3dGEkQFNG6HJDHzW3759uxqGUArGca7W4g6WiXNoAyEbd58HcJ9zWMVxuTqvHyxDPMbb4TU4z3tubm697QpdamqqPoadt/zwRkTezzihiVLyZp7QJKJ2EhvJ4EtnYfx+z3AkEbU341jR3IovYPb1landesuVw8Z4VPWi3GZTJ+0TCvJUtZC9ebXdPq0fzeUguIHqF972rXtYZLTbwAJCPf9Zv0JuXjpfbl/xm+quX/KLCvkc0u5ryW8IwWY/6RfmvkltLKslKYly758L5brFv6hQ0Ue7t0qBi+aZQ/z85LKho+XYbr30Ie5hnhGkQRWe/QW5ddYVOgxL0l4bwkmV1UfOhUFYU2jWakdulny2Z7v8U1ueWJfPb1otb+7YUNOh/5+qKtFWsVa5bsZqdFSsRAXUVv3E724n9OwrQyOi9SF12bRlfqAwT97fuVl7znlyk8P2hO7W5b/KPxbNlVuX/Sbv7NgomzLT1fup2uveLUcuBl/aiL+/v2pv/8orr5SnnnpKXd06c+ZM9SMzDlK40nXVqlWqKSRcSbts2TJVphtfdnClkTf9UIurRXGVKMqM46pVBHd++OEH+eOPP2T16tWq3X38iH/OOefIG2+8oU5EEBERUecSag6UcL9gtx3upyMbvtwh9ILwi1FZBMHmjz76SHbs2KH6PYXp4PPv448/3mhnNGnkKCsrS33mdAUBh7lz56rPzN4gJCREjjrqKL1PVLAHgRc0v2M0tYNmivDdoCmcgz3uQkKAyiioWOCooWAQpuUcrDE09Dze4IwzznC5HTl32I7xnYyIqDE45kCcXn2BiKg9GPschHqdKyCSdzHCSUaVHiKi9mLsd3BhUUsEmM1yZr8hcs3w8WLx9f6LYJprVHScxAe5rpSLqi+pJUWyOStd1mWkqg6VWFQoQbsPzUE1VhXHHYRtjorrIaYGfocpq6yUQ0X5cqAgV1UNySkvdfvbCyqQ3DTmKDm+e59GK790ZVinCPUcLMiTrdkZMu/QPvl2/66aDv3bcjJVSMaVCIu/qq5j9qm73mIDtOU/erLbbQnrDesP69Jxe0KHyjrYrrCOs8tKxXYEBY46CwZf2hB+bEYIpE+fPqps/K233qpKcN98882qv1+/fqoEN8qgo3IKrqZduHCh/Pzzz/Ltt9/KL7/8oqqprF27VgVlcOUoAigonY4KMmhfFFfTovqKux+u3cFjcLIAX67w/IcOHaq5KnXjxo0q0IIwDuYBwRyEXDAfOOmBcZF0R3UXlMQ3SovPmTNHBg4cqD8DEREREXU2CArg892JJ56o+vEZE812OjZP5IpzMztoLgdhkFNPPbXRzvmx+JyKkDUqChpOO+20mko0uB+flREi9zSggfGa+nnZU/jMP3bs2Jr5g0WLFqmAuwHNHOGzs6cQlu/WrZveZ4cmU/EdwBV8L0DVE0d4PKYD0dF1r1TB5358p3AFVR3xXE3hbvkWFRXpt5rHqO7jCK8F26erbcmxmzJlCoMvROQRY38YG8F9BhG1nzi9eojNZlO/z5L3MoIvRuUFIqL2Eh9lP1a0pOKLIcziL+cOGCp3TzhW4gJdn9Dv7LoHhcis3gMbDIsgiIAmjtAhOAEIOPxj5AQJMvup/uaYHN9TRkbF6n0t46P96x0cKreMPVrOHzTiiA4rtRasy+IKqxRYy2s69Bvr2BlCTteOnCjDo+o3SY7tByGqG0dNUu+bhjhuT0bn6W+V1DYYfGknQUFBEhcXp34Q/8tf/iI33HCDuhLx/fffl4cfflg1iYTy52gmCYEUXHGEgxmqqSCMsmHDBlm5cqUKoOBH9Pnz58u8efPU1a44MYAf/7/55htVjh5BFQRWcJXsggUL1A/v6NCP8TEuHoOADYbhvuXLl6uTB3ieLVu2qOozCONgHhBywXyNGjVKXWF50003ySuvvCLPPfeceh1nnnmmKkXvfNKCiIiIiDofBAvOP/98GTx4sOpH1RKEtRuCkAU+KxrQxOfWrVtV8ACfg111aJonMDCwXpM7CIN/+eWXNRVdMB+XXnqpCo4bEAD56quvPP7xB+HxvLw8va/19ejRQ1V1MSAotH//fnUbYXfc15SmmVB9Z+jQoTWVdwCf0zdv3lzvCzT68XwIrhvwuRzfO4ymkbBOjfUJWJ8IFjk2OwVY1/hu0NjVZOHh4fotOwRlEJhxhGmh2aeWwPyjKSlHmCbWu6ttyuiMbct4/UREDTEqvsSwCQsiakeOVaacP0eRdzEq8vixOTwiamd+ZvvvCM5NADdXqMVfTujZT54+9kSZPWBYqwUqMB1f6fh9JJp1+ov2uk7vO8jjSinRAYHyzzFHqaBDS6qroHrIdSMnqMoxrQG/Z3QPDpHLho6R/xw7U8bFxLdK9RdMo6sHafqFhssDk46Xk3sPcLss0CzY1O595JGjpsswN80eeQrbJcMY7YfLup3hB+/Q0FCJjY2V3r17qx+gccXiZZddJvfee6+8+OKL8sEHH8h///tfueeee9Rw3D9s2DD1OJQwxw/9+OEeVwMglIIOVyjhxxok0FHBBT8GozILrvxEeAYd+lEaHuPgMUYpTUy3V69eMmbMGDn++ONVk0WXX365qlDzn//8Rz799FM1XyhXj6ouCO5MnjxZ/YiPH9Xxg3xTfsgnoqbjiRsiImov+FyHEMsFF1ygD2kcAt7HHHOM3ieqKuE777yjwtjOVUoQtkAVGQTAnZsrwufYL774ok6gBRVohg8fLieccIKMHj1aHyqqCc6ffvqppjkhR84VThBCQWgcn5fxOTopKUm/p3UgZHHsscfqffbQh/ED+aRJk9Tn5qbC9wR8Njdgub388ssq5I6TI6imgu8AWMYY7lhdBY9DcMaAYBLmw9HXX38t7733nvq+gMfiewLW2ccff9xouX18d3CEoMwnn3yiKslgWliPCC+haymse3z3MCCc//rrr6sgEKr/GFBxBt9vEOzHMiEi8pRxIsHME5pE1I6wzzF+6kHVF/JeRvCcv80RUXszrntpzf1PoNksg8Oj5O/Dx8kr006Vq4ePl76h4U0OVaBiBpriuX/iVLlzwrHi73RRU0eJCQxU1VuuGTFewhuo1oHXe1y3XvL4lJlyjPYXQYeWwDoaGRUnjxx9ggoXNbY88XyNPSemEOkfIBNje8j9k46Xp489SU7rO0giLQH2ETyEeekWHKLCTpjG6f1qL4zqjILNFpnZq596TZ5utxivf1iE3DxmslrnU+J7SrBfwxV+0ETY+Nju8uBR0+XO8ceoxzfl+fC+wnb42NEztG2xaeuMms9H++DmsuYOrgJ09SNycyHMge7aa69V4QlqGH5sRocfc43OuR/rxxhu/Lju7j5A1ZaIiAh1habRoXy4WXvzosPVto5/jY4lwok63l133aUqPl1xxRWqIyIiagqET+677z51LDE8//zzqgkhdxBeePLJJ1WQwJnzY/GVYteuXfLggw+qSi+AAA3C3vjM6VjVBQEFBGMQaEDlQ6N6CD6zfvjhhyrUYFQiQdDl0UcflSFDhqjPtZ999pkKZhsQwMA0HEMngDDH7bffrprpNKDJHHT4MeKSSy5pUrAHoRlMz4CQOPodPycj/IFljOZBHT3zzDOqaqLjD1UI/lx00UV6n6gA+tNPPy19+/bVh9iXE5ogfeKJJ2peB5Ypguf4XI/bWO4IxiMAY5y4RaWX+++/X1WTNJ4T46HCI9YPAi4GfDfAMsFnfpxwwXTwGHyPcAwlOa9vBJMQ2nd8rSEhIWp9o5krTAvbHAI3js1kuXqdzst25syZ6jUb2wVeF6pWPvbYYzXzhKCREcB3XK4YF80+4eKBq666Sh9KRNQwBDFx/LnktF5yqdYREbWXM25drX3mq1aftRyrB5J3QVj8o48+kstO7y0Xn9pTH0pE1PY27ymQe17ZoX5TcWxOubWgGZjCCqvklZdJUaVV0oqL5FBhviRqXXFl3Qtiwv39pU9IuMQEBEmPoFAJtVgk2M+iwiUICDjHAcpslZJcVKg9h+tmp3sEh6rwTEOyy0q1rm6lWkOg2U9VV3EXREBTN+mlxZJUVCAbMlLVbQjWHofmbYZFxKgmjmIDg8WkTQNN1GDciqr6YVQ/X5P0DglTlTsag2WaWVoiaSVFsisvS3bmZNVZlghDDAyLlAHhkdIvNKJJgaEKbR6xrgoryqWg3CoHCnMlQ3tdBwvyxKY9ryM8T6QlUHritxrtdeJ1h/r5q6Z7XAVuOmp9NfS8vj6+0iskVAJMZn2IHX7jyrWW2Zsz0patu+0W1VywnNEEVt+wcAk1WyQqIFBtt663GtewZEu06WZr67VQe58kFuTLoaL8essd75H+IZHSKzRENScWpD0fgkuheD4322lzXj+5ht821e+E2gbC4Esng1WGH8I9+WvcBudAC/rdvdmIyLsw+EJERC3RnOALPkOiqgqCJWjKxpGrxyKYgvFfeumlmvBLQxwDDvjMumLFCnnkkUfqVGNBBUQERBDWBgRaEITBuIDPs6iOiBAGQhYGfJdB9RI0z+nKnXfeKVdffbXe1zhPgi94/W+88Yb873//04fYQygIvgwYMEAfYudJ8AUQQFm6dKmaJoJFjUFQCE2RIghkLDMDwkSo8oL149zEkaF79+4qMLJw4ULVDKrBeX0jYILmU5966im300KFHqzjf//73/qQ5gVfAOEeNOuK5etcQciVpq5fIuraGHwhoo5y5q2rxVZVrZqTR2iZvNO7776rqiJefkZvuWgWgy9E1H6M4AvO57m6KKk1VWv/rDablGsdTsYjwOHI5OMrATjH6GsSi/YXYRFvh1eA11RUYa0JtCB4EWT2U52n1TuaA8sPYQl0jsvS32RWQYYAs0l8WtA8FAIXWE8V+vpyhudBUMdfW19+JjREdWSeC25ou8VrRigLAZiWLm8Dnq+sEs9XWW+5q/eI9nxH+jL3Vkbwhe3TdEIIqxghFvygjR/ccdUj2rPHlZZougg/FOMKzsjISFXqHR36cT/avMdjGXoh6jz4fiUiovaGiiK48vS8887ThzQMlT7QnA6ax0RIEyEKV/CZderUqXL22Wer25CSkiJfffWV+ms47rjjVHjCMcDRs2dPOfPMM/U+e1l4VDL59ddfVfDEgM/Hf/3rX+XKK6+sE6Aw4LW1Nrx+NMmDSiSGCRMmuF0OnsBrx3JA2Oeaa65xO62BAweqwAuqokyZMqVe6AWwrNGkKarBjB07Vh9aC2EZhKNmzJhRs17cwXeJWbNmyW233aae2xEei2o6aDa1f//++tCWQYWb2bNnq+Vw8sknu50/LB+Mh2VGROQphC+JiDoCf+rpHIyLSu2nUImI2g9OskN7nBvASXqEJVARBNUqugWF1OliA4MkVLsPTSV1htALYC5RUSU6ILDmdeC1oXJJW4ZeANPH8zgvS1QAwTJsaSgC6wBVXCK06TlO3/F5UGkEIaUjOYDR0HaLij6oSNQay9uA6WB6rpa7eo90gWXu7VjxhYioE/jXv/6lrr5mxRciImoOBEQQKkEzMAY0E4RAQWPy8vLqBFKgoceiGgiqcmRlZUlOTo5qMgk/FiNsEh8fr4Io6NDEjhFgQGUTPIdj9RBMH1VcELJwhNfgWBUGEDZBMzuOPwbhaw6eH037YHxMG4EQhCP69etXJ6DSGFQcQVNGBsw7Xovzj09owgnjGSEcV/MFGC8hIUHvszfdg1CPq8AKGE0HYZlifaSnp6tlhvExH0bQ3WgCqSFYDhkZGaq5IvwFLJMePXpIXFycCvB4uq1gHKxfjI95w/xgXHRYRpjHxl6n87JFiB/zgqC/M3w/xTrFc6FZJnSA7QjLGfNohP/xOoiIPGE0YcGKL0TU3s66fbX22blann32WRWYJu/01ltvqSZXLz+jl1w0i8cJImo/m/bky72v7FTfoefPn68PJSIiZ/gdEL8PMvhCRNQJMPhCRESdDb5mILCBEAhuI/yBLyHt3dwmnhvfa4zwjTEPnZWxTFv6ehBQQjDFWC/OASNPYfliWpgnzA9+kGssfNNSjs8JR8J6JaKOw+ALEXWUs29fIxWVVQy+eDkj+HLFGb3lQjZ1RETtaOPufLnvfwy+EBE1Br9roqmjLh982bx5s+zfv1/vIyKywxXauHIaVwzjimU0EdaR7r77blmwYAGDL0RERERERK3o3XfflY8//pjBFyJqd2ffvloqKqvlmWeekYkTJ+pDydu8+eab8vnnnzP4QkTtbsOuPLn/1V2qOed58+bpQ4mIyFmXC75s3bpVlTlHKW78RWlvlMkuKipSpcaJiBzhqmHj6mf8NUIwo0ePluOPP141vdCeGHwhIiIiIiJqfQy+EFFHOffONVJurZKnn35aJk2apA8lb/PGG2/IF198IVee2VsuOIXBFyJqP0bFF1yU+8svv+hDiYjIWZcIvmRmZsqaNWtk9erVKviCUt54TfiLziiNXWW2iM3sr24TEYFvVaX42CrFV+tEqmsCMNhxxsXFyYknnijTpk2TAQMG2B/QxtjUERERERERUet755135JNPPmHwhYja3V/uXCtlVhsrvni51157Tb766iu58qw+csHJPfShRERtb8OufLn/1Z0SGBgoP//8sz6UiIicHdHBFzRftGrVKlm+fLlkZWVJYWGhlJZbxWa2SLX4SrXJLNU+JqlC2/O+ZqlS/W3bDj0RdS7azlH7v9ZVV6nwCzqfqgoxWUtF22tIeHi46mbOnKkqwIwZM8b+wDbC4AsREREREVHre/vtt+XTTz9l8IWI2t3su9ZKabmNFV+8HIMvRNRRGHwhIvKMEXw5otIee/fulX//+9/y4IMPqvKDu3btkrTsXMkXPykNi5fy4BgpD4kSa2C4VASGSqV/sFRaAqTK5CfVviZ27Nixq+kQiMO+ocrsr+0ngtQ+wxoUKWXavqQsIFyyikrl4MGD8vXXX6v9DspjtyUfHx/9FhERERERERERdX4ur0clL2NcN8yf5oiovdXuf7gDIiLyxBETfFm7dq3cd9998scff0hSUpLkFpeqk9M4SV0RGKGaMlKVXXzRmewVXlSVFx4wiKgR2gdL7DNUIMZs0fYpYVIeEiNlobGSU14lycnJ6grB//u//1P7HyIiIiIiIuoc3BRCJiJqc8aJTO6HvJuxfrieiKi9GXsdX7ReQUREjToi9pa///67PPbYY3LgwAEptlaKNThKykLj1Mlpo5oLEVFrQQgG+5ZKS7CUB0dqXZRk5+Wr4N3tt98uy5Yt08ckIiIiIiIib8YraImoo/gy+NIpGOuHxwsi6ijc/xAReabTB19eeeUVefHFF1XFBZslSFVhqAgItQdeVEUXIqI2on3gRBWpCv8QKQ+NlZIKmwrgoW3mDz/8UB+pdfDDLRERERERUevjCWci6ij8qadz4eoiovbGj6lERE3TqZMh1113nXzzzTeSlpYm1qAIKQ+JFpufPwMvRNSusM+x+QWqptWqTBZJSUmRjz76SJ599ll9DCIiIiIiIvJGDL4QUUep1hux4H7Iu3H9EFFH40WxREQNM/aTnTYhctddd8mGDRukoKBAykJjpSIgTKp8zdo9PAAQUQfQdqqoNFUWFieV/iGSk5MjP/30kyxevFgfgYiIiIiIiIiIyI4nMjuH2qaO1B8ionbH4wURkWc6ZfDl1VdfleXLl4vNZpPSsG5SaQmWal+Tfi9R851/2kny4dMPydcv/0e+fPEJuXfOlRLo76/fS9Q4hF/KgyO1/VKQFBUVyXPPPaeaP2opfrglIiIiIiJqfbySn4g6Cn/p6Rx4nCCijmLsfnx92coFEZEnOt3e8pdffpGvv/5arFarWAPDxWYJYNy6A7x4/+0qHNJQ9+lzj6kQyUsP3CG3X3WxHD12lP5o7zR+xFC57JzTZdLoETJ6yCAZM2ywnHPidPnbaSfpYxB5ptrXLOXB0TXNHj366KNSWFio30tERERERERERF2dr6/9N20GK7xbbcUXnoM4EpkCYsQSOULrRopfSF99aOvDtPEceC48Z1fi6xcqgd2mSkj/v0rooIslqOdJXW4ZtBT3P0REDTM+r3Wq4MvOnTvltddek/z8fLFZAqUiMFwbyh1+Rxjcr48KhzTUjR85VIVIZhw9US48/RR59JY58voj98q5J03Xp+JdesTFSve4GDHp6Vl8mAgPDZH+vXuofqKmqDaZpTw0Rqp9fGX79u3y7rvv6vcQERERERGRt+AJZyLqKDyR2TnUBl/UHzrC+EeNlpD+50nogPMlsPsJ+tDWh2njOfBceM6uIjD+OAkf/g8J7n26BMYdIwExkySw2zQxh/TSx6CG8XMqEVFTdJrgS2lpqbz33nuSmpqqNyUSzeaNvJyv9m0AIRJ/i0UFSPr27C5TJ46VWy6/0CubEEpITpHMnFy9z660rEwOHDqs9xE1jc3sL9bgSNUs2/fffy9ffvmlfk/T8ccQIiIiIiKi1sfgS+dnDuquX0U/Ut1uK36hA+3PEzFMXb3uDbxxnlrTkf76tB2Q/of7IW/WVdcPKpREjLheIsf+y96NuVOCujfvglb/mPESOeq2mmlhum1ZXaUpfMzBYgqIVhVIfC240LptYNp4DjwXnrMjoOpK5Jg71DoIG3qVPrTt+MdMlKCep2jrur992fpaVILM1xwoPrhNHuO5ASIiz3Sa4Mvvv/8uK1eulGrxUU0cIfxC3gNfAMqtViktL5eycqtUVVXp99TlZzarqip/OeUEuesfl3tV+GX/oSR55eOvZO3WHZKYkia7ExLlvW/nys+Ll+tjEDVdpX+IVASGSUFBgXz00UeSmZmp30NERERERERELeUfO1ldRY8Ot9tKUO9T7Vfr95stfmH99aEdyxvnqTUd6a+P5zE7h5rgSxfLv/iYAsQc3EsFVFQX2k/8o8c1K7AQEDVWew8PrJkWpovpU/vytUSIOaSPfR0EtW2Ve2wngfHHqKAPdnYVRYmSv+sNyd36guTvfk+s+fv0MTsO3toFNoskW0NkX2mY7CiNlO0lUbK3LEIOWUMlsyJQbNUdu6NmLpKIqGk6TfBl3rx5qupLhX+wVGodeZcyq1Ve/+w7ueSO/1Pd+bfeJ/c8+z9ZtHq9FBaV6GPZqSaEQkLktGnHyDle1OxRubVCm9918sALr8lNDz8ttz3xgnzy4zzJyS/QxyBqOjR1ZA0Ikypfk6pYtWTJEv0eIiIiIiIioraDE1t1r9a/QzUv0Bz2q/Vv9cqr9VEJxH4VfUybVgUx+UfWXq3vJSdsvXGeWtOR/vp4BX/nwIo8Bh8xBfUQSxOb6bGEDxZzaH8VfqCuwy8U4Zruar1XVZZKWdoKsebtksqiQ2LN3y1V1jx9zPZRWe0reTZ/OVQeKovye8n7GUPl6ZQJ8mzKeHk1bbS8nTFSPsgYLh9kDpd30kfI62mj5KXUsfJ48iTt/lHyQ05/2V4aJVkVgVJaZdan2vaM3Y+vb6c5lUtE1KE6xd5yzZo1smXLFlXtpSIgRDtYcifvbVDh5XB6hmzfe0C27d0vW3fvk/nL/pTHXn1X7n/hVdm5/2C9LwmRYaFy5oyp0j0uVh/S8UpKy+Tg4VTZc/CQ7D+UzNALtYpqk59UWYLUe+DXX3/VhxIRERERERG1nfpX6/eXgJjxLbhaf1DNtHi1PlHL+fragwAMVnQOXTm3UV1Vif+JrzlYOx40LfjiHz1eTP4R6vFqOtQloGkjH5O92n+1rVQqig7ihupXf7XtoT2UVZllfXGsfJw5VN5KHyFvpI+UH3L7y6qi7rK7NFIFYVKswZJWESzpFUGSURGo3Q5Sw1AJ5kB5uGzUHr8gv498mDlMPf69jOEyL7evpFqD9GchIiJv0SkSJAsWLJCysjKx+QdJlX6wJO9Xqq2z5LR0WbJmg9z/wmuq6SBHuKphcN/eMnn0cH1IXdER4XLdhX+Vtx67T7548Qn56r//Ud2nzz8mz993m5w1o+GrlIzHv/bw3drjH695PLpPnn1UXv6/u+Tis2bpY9vddfWl8uw9t9R0/3fj1TKoTy/93rqmTZ4g/7nzRvn0ucdq5027/fjtN8jIQQNkzoV/qTMtDJ8wcpj+aDvn5zPGGdKvj9w350r56JmH60177PAh+qOpM6mw2D8Ib9++XTZv3qxuNwWvAiIiIiIiImp9XeuEM6/WJ/ImDLx0DkaT/l07+FIuVbYytRBwPMBxwRNoTscvfIj2OLNUVZao6VAXoS5e18N9tgqxlWao2+2hqtpHcioDZGl+D3k+dZx8ljVEVhXFq6DLYWuI5FX6q0BMlT5/jamoNkmhzU/SrUGyvyxcNhXHyLy8vvJK2hg17YPlYVJe1TanWo3jBM8NEBF5xuuDL4mJifL777+r25X+qPbCHXxng2aQdu5PkO9+WyzFpaX6ULvQ4GAZNXiA3ldrxpRJ8vy9t8oVs8+QY8ePUWGPMUMHqW7CiKFy4pTJctvfL5J751whgf71w1COjz9+4ngZO6z28Woao4bJ9KMnyNSJ4/RH2B0zYYycfOxRNd20SeMlKiJcv7cWAjX3XXelnHr8MTJh5NDa6Wq3T592rNyr3Yf5dpzWjKMnSo/YGH0Kds7Ph3EmjRouD/3zWpk9a4a67TztB66/Sr0+6lxsfgFSZfaX8vJy+fnnn/WhRERERERE1JG6yolnXq1P5H2Mn7kZgPFuXD8abd9fVW5vmgbHAxwXPOEfOVI1VQZV5bnaNs9K/l1Ttfb5oUK/3bZKq/xkbm4/eTt9hHyXO1D2lYar5okQdEFzRy2FsIy12iQFNosK0Swr6KGaRvooc5gklrd+c4tG4IXBFyIiz3j9J40lS5ZIQUGB2PwC1Ylj6pyQjP9h4RJJycjSh9iZTL7Sr2cPvc/ulOOOlluvuEgmjRohUeFhYjab62RvcZAP8LdIj/hYOffkE+QfF/xFv8du1JCBct2Fs2se7+enPd7pg4Gv1u/v5ydBAXW3KX+LRZu2f02Hfuf2Ey86Y5ZcdNYsbb67S6D2eMdp43ZQYICMGz5Em49BdaaFeTaZTPqYds7Ph8eeNfN4GTtssAoFOT63Me2Rg/rLebNmugz8kBfTvthV6lVfEOYrdQqBNYZfsomIiIiIiKi5qqusda7W9+PV+kQdzvhN0fl3S/IurLgA1VJRuN8eftSOBzgu4PjQEF//SFVhzMfXT6q144+1YK821LNliCb5AuOPkfChV0vE6NskcsxdenenRIy8SUL7zxa/kN762A2zRI6Q0MGXadO5tWY6mGbooEvEL7SfPpZr5sBuEjrgfAkbcqX6i353AuOPVeOhw+3m8vULlaBesyRixPXavN5R53WH9D270eXeEn6hA9VycXy9WEYY5rgeIkbdoq2Dv7qcl5C+59qXQdwx2no0q2F4Tcaycbd8TAExEtz7DO113+jwutHdIeHD50hQzxPVdNyxVvvKjtIoeS1tpPye31t2l0VIbqW/x1VdmqukyqyaRFpXHC9vpY+UX/P6SL6t9c7bGGcEeJwgImqYsZ/0+uDLn3/+qf5W+gdLNRPBnVpuQaHsS0zS+2pFhofpt0R6dYuTK/5yhmoCyWy2h0QqbTb5c+NW+fdLb8jrn30rBw+nqi8c2ITDQ0PlnBOnyUnHTFbjAqrBDB/Uv+bxGDcxJU0++O5neeWjL+W1T7+RP/5cK1l5ecgaq3E8NX7EELn47FkSFx1Z58NGudUqew4ekvXbd0me9jrNJpOEBAXq93oOYZwBvXpKRWWlbN+7X3Wl5XV/VEJ4ZrRetYY6l0qLth/TtlyE+dDkUVPwwy0REREREVHr6zIXGVRVSJW16VfrW3i1PlGbMX7q4cVO1BlY83ZrxwH7Ra04LuD40BB1/Ajqrt3yUc3c2EpS7Xc0wi90gIQNuUKC+5yhgjOWsIEqfGHv0MzSUAmIO1ZCB14sgd2m6o9yDQGSkP5/lQDtmGcJG1QzHUwzIGaihA64QHz96ld7NyBogeCMf/RY9beh4IU5uLcaDx1uN4efNo8ImQT1mCmWiOHavA6o+7q114tAiiVihP6I1mUKiBR/bZkbr9cSNUotIywrx/WAZRkQd4yEDDhPzaMjv4ih9mWgmki0n5/xNQfVLBtXy8ceGrpCArtP017bUDVN47lwG683qOdJ9rCS9tzOSqvM8m32IPkoc6gKvxTaLGJrheounsIevKzKpAIw83L7ynsZw2V3aYT9zhZi8I68XUVVleRZy1RXWGFt4hlXotbn9d9Wk5OT1V+bmdUtjgQlpWX6rVoBAbXrFhVcUCkFlWAAlWJ+X7FGHvzvmzJ30XL54Lu58sbn30pufqG6H4f77rExMv2oCaofRgzqrwIkBjS19OUvC+StL7+Tj3+cLx9+/7M88fr7cs19j8vbX/2gj+WZU46bIv179VAVYwzZefnyzDsfy21PvCD3P/+q3PDQU7J1z/5mfWlFhZf8oiJ5TpveXU//V3W4nZtfoI9hFxEaIqMG1W8iirxbldks1SZ70t3YtxERERERERG1vWqpKKi9Wt/i4dX6OAHW0VfrB8ROlrAhf9emc3vNdBq62tyR49XruAq9IUE9T1HjhQ2+TPyj6zaN3RQ4UYcTk5hHvN6aK9aHXSuB3Y5Xy6a9NXWejCv21ZX5jZxY9gvpK6EDL1Lj4kQ0nsuZ64oLt2uP+btav12V8W5i8IU6g+rKErHma8eB6ip1XPDX3tcN7c/8I0eJrzlQHXes+bu17bzxpvIQcgjpd64KzfhaItWwyqJkKc1YJaUpi7Tp7JEqW7l2GAsUc3Avtd/GPswVDA/sNk3MgfHiY7JIlbVIynO2SMnh37W/W7XjmlWbRk+xRI10H+rUhuO14nXiL/rd8jXr42nLRK900hTqtfc9WywRw8TXL0RVWSvP3iTFST9LWeYaqaooUAESv7ABEtz71Lap/OLwevFcgfHHiSmomwoulaYtV+vBVpaljeej1gHmOUA71juqriiSqvJ87W8hdm72Ydq6x7CazlZbCR3rCQElv5B+2usOVusX6xnrG89XWWS/kNrXL0wtGywjPC9g8ofKQ+XtjBGyrKC7pFmDW6U5o5bIs/nL9pIo+ShrmPxZ2E0qqlpnfhh86doQLvk5ca+8u3OTy27x4UR9zLZXpb3xNmalyXOb/pQbl8yT6xb/LLcu+011/1w6X+Zo/Y+uXSb5Vvu54MbmfZM2LaLW1LFHgUaUlZVJZmamdstHqvSTxdS5ufoi5xgimTJulGoSyIBQyQ8LFktiSqoUl5ZKTn6B/LZ8tRxKrd0ZIiQzbGB/vU/7kGiuu61YtP6Rg/tLVVW15BYUqGkkpaXLzv0Jsm7rTn2sxqFpoYmjhteZPqrR/K7Nz/e/L1HVbBKSU2Tjzj3yzlc/qIoyTYWDxqrN2+T7BUtl/6HDqsPtXQfqHrgwD/Ex9iuuqDPBvsweykpL4wGdiIiIiIiI2k9nu1ofJ94QkAnuc5a6QtwSVnsFuHG1OcIcvjjJ6Ibj1eu4Cr0hftp8queJHiNm9bqbDq8ndMCF2rwdpeYRr9c+zwPU8sTJytAB52nzFaM/ou01Z558/aO0ZTFGLQ//mIn2E7lu4Ep8VANQyzikt9jKc/V77OswuNepbiouDFCPwfoN6XtOg89xpOKJzM4BF2aSHQIjVQg0aMcFU1APVRHEFewX7OFGH6my5ktZ9mb7HQ3APgCVTrB/QPgCz1Oc+JMU7Hlfig/NleLDv0nh/k+lYPe7UlGUiDeQtt+KkoD4Y+uFQNCcX2D36WLyD1fpCAR28ne/JUUJ30jJ4YXqL/oripLEZEEVl44/TYaQjv21m6WyOFl7rZ9L0cFvpTR1qbYcfpTCA19qx2KETkxiDumj7ZtrLwRuCz6mQFXhBs+v1kHSPLUecFsFoFDXXFtPar8e0tf+IE1hwleSv+tNKUlbKtVVFWoYtgEMMzpME2rWEyrLaeuzouiQtn7fU+sZ69t4Prx+bA94Pr/QvjVhm/3lYarKy5biGCmu8vOaShMV1b5yuDxYvs0eKHPz+ou1BeEX43QajxddW0WVTRYlH5Sv9+902a1OP6yP2bb25+fK/asWyX/Wr5D5h/bL5ux02ZmbJXvyslW3W+u2ZWfIFq2z6sfOxuZ9Z479uwlRSxn5A68OvmRnZ0tFRYVU+Zq0PbtXzyp5KCwkWL9VK0+v3jJm6GDpGRerbhtKy8pl8pgRctOlf6vprpx9hgQ6VImB6IhwGT7AfkVJamaWCpAY0DTQtEnj5X8P/ksevfU6OdGhWSQ0UeSpodr00cSRo/yCIlm2fpMUFhfrQ+xfhpau2yjJqRn6EM9hftZt2VlneridmplZJzSEyjAWS21VG+o8jIovGRlN2z744ZaIiIiIiIhaov2u1j/HxdX6q9XV2xX1rtY/WV3t7UpQr5MlIHaKOiGGE4G28hwpz9qortav0F4HfiXxC+uvTpy55Xy1fgNqx9OWid48Q1Ooq9a114MKAj6+/mIry5TStGVSnDxfrHm48MqmLZMIdbIyqMeJ9ge1sebOU0XhfnW2DcvCHNitwWWMZimwPn18zOpktP2kuB3WIU5qouICKiDgJDO2A7UOCxO0MXDiOlqduMZ4XY3xUw8rvng3rp9aFQX7VDhBWyqqIoh/1Bj7HU78YyfamwXSjjeoNmYrbrzyNUI0fuGD1P63uqpc21etkLKMP6WyNE3Q1F6VtUBspZnqeFRyeIHqxz4EQUXnKl1ozs8ciPMMPtqxI1tKtH0e9jmoVoJ9FP6ivyTpF1WBpKP5x4xT+1K89qqKYilJXSLW3O3afGZr/UUqUGjN3SFlWetUmATHK1Q/aegY3mIIohTsVUEhtQ6sqNaSq/bz5ahAU2mv2oJKLCbtGGNAULayJEWNj+0E8DkCw4zOaHqxznrSXmvJoV/U+sV6xvrF8+G5sR2UZeK126vWmcOGyI7qUapJoQPl4Spo4m20I6hkVQbKooJe8kteX9UUUku017mBkooK+WLvDpeVOYwusbDpF3z/mX7Y5bSMDvc3BZrV+WzvNpfTQtdeQZD2gndSUYVV8srLXHYllfaQWVvB86/Slumj65bJn2nJklRUIMU4d+/m+GjT9v2Gxua9zNb49wuipvDqNIlxYrja1LKDAnkHVEzpGR+n99VKy8pWf3t3i5PQ4CB124CqJrNPniGXnn1ana5fz7pX3pi1bSQsNETd/umPZZKUmq5uG0K06Y4dNljOOOE4uXfOFfLmo/fJOSdO0+/1TM+4GAkJCtT77AqKi2XVpm16Xy006VRW7nmoxoDQDCrbOMvKzReb09UFjEF0TlUm+xeS9PS62ygRERERERFRW7N6fLX+8Nqr9Svypdzjq/Vn1L1a/9BPUrAXV+v/pK7eLtj/mX61/iGcxakJPThfrY8gBiq6+PgFqxNd5VmbJH/nG1J08Dt1Eq7gwOdSuP8TsZXliq8lTH9Ux/EL6aMqq+D1VFdXqeYp8ne9LcVJ81XQo3D/F9rfxVKN0I8pUPy15Y5l3JZaMk9qO7HaK7eg6QmLm+ALxjch1KJB0xVGsApwQjwg9mi1fqqrrKqZjIK9H6jtQK3DvR9LWdZatX7RrEdA7KS2abrDi/G3vc6F16Rpb29tf1GevdEeevDxVdU+nPdlqpqUNtwe4ijUxt+gvc8bPymrmvgx2y+atZWkS2nqYtXcTz3VNhUKMQI4ON6gYpcBzfSh0hgCEtgfodpZRcGBmn1TDdyXv0cqCg+ixz6sg6BCDvaDoIIl2jJ2Xmbox+uo1psJMmmvE9VP2kqVrUzKc7dp6xABIwfqeLJZG15k7zeZxWQJt99ugvrraZcKvWD9OlPNPmWtU59HYF9htXyeFicp1hCxVXvvGxNbVUGln/yR31t+yB3QrIBOewfvfH19ZENWqsvKHEa3IbNplezR1M2vh/a7nJbR/ZywR8pt9de9Own5efL53h0up/XtgV1SXNH0c3Pk3obMVPnvljWyNz9HrFWeryeijuDVwRejKZCqRq7IoM7hhKMnSM/4uhVdrBUVknA4Rd02m82qkokjf4ufRIaH1ev8LfXTzEbqddOuPfLap1/LgeTDdT4YYNrBgYHSu3s3OW7CGPnnFRfKjZf8Tb+3ca7mD2GUohIXH8BbWWWljVcXHCGMpo4YfCEiIiIiIup4Xe27ttXjq/Un1V6tn79fNbvQGPvV+oPVSayaq/XT/5TKEser9TP0q/V/V/3ayC6v1kcIwmSJULfx3Ai8VBYfVlfuq6v1MZ2cbVKSuqjmqvOO5B97lPY6umm3fLTXmyzFSb/UXNWurtYvy5QSVLwp2K/G97WEq4o7bakl82TTxrHm71PrHyev0TySq8oCqFCAYAzYtGlb83ao2xAQd7Q6MYttrUKbVknyr9o4qBpQoK/DdCk+9LP21/77rykwtt4J9K6Cv/l5N66fuspztmjvZXs1BQTbnI8jOBaY/LH/1t772vEG4RJPmAO7a/sb/PZerfb39pCmawjgoPm9av1CUTwfghSAClPq+KWp0o5FqOziLniD4dgXIhzYkWpeuzYfPtq/oO4zJLj36fU6hIO0mVWP8TH5q/12m7FZtWWTo/fUhSBKnfXTjCppqERmzH9j6wnsnwFyZE9Wrry2epskl/hqW0rrhF78TSaJCwmS3uEh0iM0REL9W7eSToHNIssLusuSgh5NDuoYux/n81JtxaItiz4hYS4rcxjdjhztPaOP74nsshLZrj3G1bSMbldetuSUe/55bndelmSVFrucFqqQ9A5tw/dGF5NvLZOPd2+VxMJ8Hg+pU2ifvWUzpaba2w5mxZfOr1d8nJx/+sn1mjrKzsuX9Vt36X31HU7PVM0GNdat3rRVTQtQaeX3Favllseek/998rXsSTgk5RV1PzQhxILqM7NPmSFTJ9b9caUpfH18VCUbV5COJXJm04MvTW3qiIiIiIiIiKilOsPV+rhtDu6tPb+Pel5r7lYVeHGG+8oz16rn6kjqqvWawI82vznbpLK0/jxhWSLEU40rZbVl69g0RGtr8Tzh6vv8vaqKC6Cqix+a4XCAIIyfvp2o58jbKdV6CEmtw5A+GElta+VZG8Te7EVdqhmLYlwQZ29WyRTctSq+GL8d8kSSdzPWD5sht8P7XL3ftfc93v8IPBrVmrDv8Uc4A/se7XijxtP+esLHHKD+IoRic64y4oKtPBMzo24jBGLyj1K3UTnFR6+4jfCGq32Po2pVYaRj34PGa8c+E0FDNP3mqkOg0KgMo42sxm872jJpKBCEZodaAE0pohlDxZP1pG1vBcU58uHGHXIgN1+qWmGVhVj85KxhA+Rf0ybLHVMnym3HTZTbtb//On6yXDt5jPTUWxhoDYU2i/yS21fWFtmrpHnK2O+01/7HV9uuxsZox/wGgjaJRQWqSSRPJRTkSWZpsd7nWlZZiSQVNbwNGHAx+s7cLLfv2m5BwRIXWPc8JDXfqrTDsikrze1nFZwjjQ8KkSnxPeWYbr1kSES0tv3wnD51HK8OvlTU7Dz5obIzi44Ilxsu+auMHz6kTjIVzfqs3bpDNu+yp75z8guktLTuB+HSsjJ59u2P5dH/vdNg9+KHn8uhlNoSa0UlpSrw8vGP8+T2J1+Qa+57TL745XcpLKr9wQVbVbfYaDl2guurm5zlFRbWa74ITR+NHqp9yXcyuF8fiY+xf9gmqkM/6JeUlDTphw1+uSYiIiIiImp9XfGEs/dfrd9NVaOBqspiexMVbiBYo05+diDHq9ZxIhAnX4N7neryan37a7S/Zl9z7Qk1c3AvCR96lUSM+qfbLqTfX/SxG9ca84TqLajiAqo6UHjd4IvaTgLsTZpXlWdLWeZ6dRsQXDJCUNqGICbt9bl6bnQ+WNfqfegjJr+Ob7aqXek/9fA3H++G37CBq6kW3u943wOaU7NEjlS3A6IniEnbhwMqc5Vn1e4XGmcsYG1/4EEFFjSTpsZVfLT1o4co1HGoadPqeA7z62tWwR13HYI6aD5OBY/0bbNzwmv2fD1Zq0zy+e482ZaerSp6tESgn1mm9+8l90w/Si4YPVQm9YyXEbHRMiQmUobGRsrY7jFy8qA+cue0iXL60AGtVgEmpzJQ5uf1kdQK+2ccTxivtD2PE/1CIyTCooexXEgpLpT0koaDLI42ZqWJtZFmjHD/1mzPPs8VV1ZIYqH7cNywiBgJ9Wvdqj1dFZqpWp6a5LYZKgSkLhkyWp469kS5fdwU1T04eZo8cvT0Brchorbk1cEXpt07N1R5ufSc0+TZe26RWVOPkcCAuju6Q6np8uW8BVJSVqb6N+7cLdkFdQ9YcdHRMnHUcBVqcddVVFaqyjDlVnsopXtcjPoLufkFsjcxSdZt2ymvfvK1fDl/QZ3qL2aTqV4VGnd27kuQgqK6B3Q0u3TatGP0vlrnnjRdusXWzgdRHdoHVezfuI8jIiIiIiLqWF3xe5n9av1d9pNm6mr9Qd51tb4lTJ34g2pbmVQUJarb7thPfnYcx6vW8Tos0WNdXqmPDieHa65wd7hSH8ESXOVvCRvstkM4xlOtMU9qOylA0xPa8tW2E7NTc0eW8KHqebQxVUAKTVAYVHBJv/AH1QkCYie7fG50FlT7MZ5Xe56upOaUL38fok4G7/fynO1q/4CqXWgmDfsH/8hR2tvYoo4v5TnbBM2qtRUfX1Rht+87cNxBGKRZPA4UaOO1cfgAr6Msc63kbX2x8W7Hq+oY3RVgF7mysJssSSlrNEDRGIvZJH+fMFKuGD9CxnSLkaigAPEz+YrJ10dVrjBpndnXV4ItfjI4OlIuGjNU/j5xZKs1NZRsDZEvMwc1ucmj9hQTECR9w9w3FZRfXibJxY1/zoPiigrZmu1Z5fu9eTkqaNGYzNISySxzHbwxaetpfGw3tS6p5YoqrLK/IFfvq29MTLycN3C4DAmPkl4hYdIzOFT6h0XoVV9a5z1D1FTc8qhVBFgscs3558j7Tz2oug+ffkheefAumXPBbDlq9EgJCa6bYs3KzZP3vvlRtuzapw/RdqLFJbJx+y6x2WoPbiHBgXLFX86Q6y/6qwrSGHB79qwZ8tw9t8p1F/5VH2qH/pceuEP+cvIJqtoMIJmfX1gkYcHBYnJoOgvDS0o9azswKy9ftu3dXydR7Gc2y6xpx8pD/7xWTj72KJlx9ET5vxuuVsEXf22ZELnCHzSIiIiIiIioI5VlrnO4Wj/G4Wr98V5wtb5D+EH7/uxp8Kbj4HXXnmDByV/nK/RrOl9700M1V+vrcHLYmr9PBZLcdY0FgOpq+TyBNWeLNm/2pgewnRjNHSEg5RfaDxMWNGVkzd1Rd507BGgwHy6fV+8QkLE/d/3nP9Kx0kvHSEurrRruCeN3PK4tB9r7XTWbp/YPPmIK6iGB8cdof3H88NGrQK1Wo3rKaBrPRzsGGBXAGoJ9khHaU8226RWqcMwwApHY9/n6harb7vhaItRzNgYBH18/9xfQ+vq5Dwo0pva1a1tZtU3t7xvrKosOaY/zvOqGt6mqKK7Z5/v4BohvQLS67Uq+zV8WF/SQ4orGP1s0JDooUG6eMk5mDOgt3UKDVcAF8srKZVdmjqxPSZdt6VmSXWI/X4TwRHRQgEzr10v+qT0uIhBhq5aprPaV7aXRsrKwu7ZvaXyvUrP/acfjhb/ZLONj7J8FXbFp87Qnr34TlK6klBRKUgPVWRwdKMiV7DIXTWQ6OVxcKAXlrj8bRloCZGik+22JmibfWi6FWufOcd16S0xg/QpGPF5SR/Lq4AtPDnceCJMM6tNLjh4zUnWTR4+Q4QP7S1x0pJjNtR8csU6T0tLlxfc/k1+WrKyp0mL44Luf5eBh+4dUwIeLPt3j5fJzz5D/Pfgv+eLFJ1SH2/+87AI56dijpE+Pugdh9M84epLccsWF8saj98oHehjnnSf/T0467qiaDzSA5pXWbdul9zUMIZkFK9dKTl7dtgajwsPkrBnHy91zrpD7rv+7Cr0gcMPtl9zx0Q/9RqlUT/DHECIiIiIiotbXVb+7u79af7QKI+BkVGe5Wt+nTsjCPYyH19iWcBKyKOHb+lfmu+gK936kP0pbH2WZUnxorhQe+NJtV5q6RB+7aZo7T1BZnKyardLWkKru4h9hD0hZIkao5k0AzWaV525Xt13BtubquVx1RQe/1R/VNRg/9fA3xPbxyy+/yE033SRvvPGG5OXl6UMbx/XjGvYP9qbosH8IEv+4o+3BEG1/bs3fW6cKlCdU02oqQOcjfiF9ayqRuYJ9uV9oX9zQ+qrVY42QpK0sS7ttDy6g4pVf2CB12xXsx/xUNS3Xv7tWlqap46Fi8hNff9cV3jGvpsDmV3+vKkVFDGxnvmpabX2s8gYVhQekymqvJKEqk4UPUbddmZvbT5KtDQeYGoPzTKj0clzfHqqaC9iqquS3vYnynyVr5eU/N8rrq7fIK6s2yVNL18oPu/ZLpf7bfZCfWY7v11POHTFQ9beUtdokC/N7SWGVfT4apO9+2vPcAJ5pdHScBJrdz9++/FyPqrPszs2WfKu9xYfGZJWVqFBLYxC6QfjGlX5h4RIX4FkLD9S40sqKBqssxQUGu9l7ErU/Yz/p1cEX6lxQ7s2xc1ZSWibzl/0pd/3nvzJv6Z/1mg2Cg4dT5dVPv5bElNSaLxWYVlREmAwb2E/GDR+iOtzuHhsjAf6WejtW9PtrH15w/6ghg+QoPYwzYcRQiQyr/YCE+flp0XJZuXGLPqRxy9dvkq/mLZBihyoxeL6QoEDp3S1e+nTvpqrbIFCzLzHJPgKRM32j5RdnIiIiIiIi6hBefLW+mo5+MsUXJy1D+qjb7njyXICAT0MnUhu6kr8hda5a1157tTb/rq7Od+6M1wt4vE1b5gjAuOuqrHUvxGpIa8wTYBqoNqNOKGvTQZUXe3NYQ7TegNr79XVvUNuVvg7twSQ0h+T6OR07W2m6ekxXYfymyd+H2kdmZqbs2LFDVq9eLW+++aYUF3tWLaMpF651Jer9n7td22eXahszAhs91X4C+3NrzlaMoI/pGatD2BLHh6AeM90GQALip2jHK+35NKpiVk5t+A7VyipLUrVb2vtKmx9L5Ajxjx5rv9MBpo3m1kyBtVXmneG1VFnt1SpQlQxNs7map4C4o8Tk4bHIlYrCBKmy2cMB5uCeEtTzZHXbHf/ocY0eG72dvdnFPdpmgub0fMQSMVQCux2v31sroSxMVUdBpZTmwoXQfx01WI7p010CzPbPHYXlFfLhxh3yyeadsj0jSw7mFsjhgiJJyiuUHRk58tXWPfLBhh1SUmGvHhToZ5ZZg/qpAIzz+ajmQJNHqwrdV1Vx1t4XxfYLjZD4IPefi1CdpaCBSiCAYNGGzNR6IRWEkFydPyyvrJQtWQ03i4SwDUI37gyLiFEVa6h1oPWLhj6hsEkp8kYMvlCbwZcCBEQSklLki19+k9uffEGefedj2bx7rxSVuC5ZhscsWrVeHn75LVm+frMKp7iDcZNS0mXFhrrBFTRpVKF/IMFu1wjiGB8OKm022XswSZ5//1N57+sfVRNLnsK4H/84X97+6gdJy8yu98UU/QnJKfLC+59Jbn7j6VTq2vjDBhERERERUevjdy3P2K/WT9Bu6Vfrx7b0av1U9Vj8GtP0q/VTa67Wr9Ke1wht+PqFiCV8mLrtil/4IDEFxOp99dUJgJgC1MlUVywRw8XX0rxmKuxXrdt/A8JV6+aQ3up2R2rNeUJzV1Xl9pNMpoAodRLZpFdIwAnh8ryd6j5HtuI0qbLpQShzsJhDB6jbVBer+3YMH3+zLF26VN577z2prLT/htwQ45jC1VUfqj0htIH9uD3IiJBbklgL9qn7m8JasFeb3lYVhFCVyKLHSuigi8U/aow+hrbP1/ZlIX3PkaCeJ6kqVBi3PGeLth+qreiOfX55prbfMkI0/pES3Pt0CewxXR1TwC+0v4T0/4sExB6l9Wnr111IRxuOY6X9fu3Ypu3L8DjMB6BiTEifs7Tj52Str/mn2spzNtdUz8GxKrDbVAkZ8Dc1nwbMe2Dc0RI+9BoJ7nN6g8e+zqI0fYV9+WqvG01SYb1i/RrLt6raR1aXD5OSqpYFGfpGhMkZQ/qr8AqUVlTIa6s3yfy9iZJZXCq2qtqT+/iLk/05JWXy275EVQGmwmbfPsID/OXiscOkW0jLK4ogyPNrXh/Jr2y4+aTa/U/77oAiAgKkb6j7z0U5ZaWS2kh1lvyKclXxxVmYn0ViAgL1vlp4pbvzshusJFOgTfNQoeuKXX6+vqpSDXfVRF2b6SGNfrsOfOizNVDCqKk2b96suokTJ8qkSZP0oQ1bu3atbNy4UWx+AVpXf0dIHWfjjt3y/YIl8vWvfzTYfff7Ypm7ZLksX7dZdh9MlLyCwkZ/gKrQtr20rGz1HKgMczA5RTJz8iQzN1cOpaTJxu17tOEr5c0vvtOmv0jWbdsppWW16dJdBw7KL9r9CUmHVbNKuQUF6nE79ibI3EXL5K0vvpfvFy6W9drjUJnFkfPr+umPZbI38ZBYtQ9DhpKyMtl/KFmWrN2g3ZcsuXkFat4wX3jMO1//IDv3HZQLTj9JYiIj9EeJFBaXyC+LV6iqNgbn5/teW15b9+yTUqc2CjH/vy1fJd/o46Fbtn6TCvlQ5+NXkqc+gF1zzTWqmTBPLF68WPbs2SPjxo1THRFRa9tXnCIZ1jzJsha47PIqiiXK0rLSskRERERtad68efLaG6/LLz//LLNmzfLoJMGff/6pvmuNGRymuiMJQh44cagqc9jKpDx7s6oqUqO6Sp1c9Asfqo1jUaEXnLisqiiQ0sML1FXzjnAVun/kKDWOq+lhaVsihqmgBZ4T1VpQDUQb2T6Cg8Bux4l/zCT1/Dg5WZqyWCpL7b+X4PkDokaJryVCm6ivOtmH5naqtM+qjjA8pNdpqgoJxoPK4iR7pQEdmk/yj5moxkXlEVSTseZu0++1QwgnuLc2HVw9r6ZTpU5AVuTvsY+gC+w+TZ2Yk+pKVeXA3gSQpqpSnZxUQR8fkxoHzTe4q16CefGPGV/7+BZoj3nCMjQH9xC/4N5qfUl1tWoaxMfXpD3nDilLX4GR9LHt0LwSAks4KYzxTNrzo5qM8zo0YD7RzIW9SkMtt6/vCDFvZYbkFlTItGnTpH//2hPc1DaM8xN9jx0uucmZkphwUMrKymTChAn6GK798ccfkpSUJEePipTBfezBia6g0WMIVFWo4KQlbJD2XteOH5Wl2v58oVQWJeoj1GrsGIJjBd7j5sA49dw4lpgCY8UvbKAExE6UwPhj1XHDL3ywmCxh2q6oSjvG7JCixB+luqLuCXhbea42Trj2nN3V82Efh32YJWqMNp0p6rhgCRug9vmV+fvEN1DbV2m3bWX1q51hmL92bFPHEVQO0+bPT9u/BcRNVsEZdQzVPm/gNRvhSudjEQTEHa3fX/8Yg/1stXYsxDLytYSqZW4OilfTDoidpB4bEH+M+GvHRgQZfbX78dqbuk/EfhbLUx0PcexNW6rfY9foOnLQ0OsBx2m5ei5Ak1TV1nztNfVSyxfbkimouwqjYvlawyfKx3tLpajCfRDCE4OjI+TUIf1rqlP8sueg/LwnQUqsted8XEETL2mFxRIdFCCDtGlAqL9FskvKZGdm08LBrpRVmSXMZJWBAfnaOtEHOklMLZHlm3MkKipKzjrrLH1o28Oyyi4rkdXprrcxVHEZGRUrQyPtzR66sis3W75N2FXTZJShV0i4hPhZVNNGzjDdk3sPkCA3zSyh0sy3B3a5DMd0Cw6Ry4aO0qbdcJjIkF9eJqszDsvchL3y9f6daro/Hdwjcw/ulV8S98nSlEQV3Cm1VUpMgLaf8/A8jmFffo7s1+Y3pbiwXpdfXi5R/tpnZX3FZ5eVyvxD++WrfTtkfhKeO0nCtNfRI9j+Oyxe72/a/emlriuVDQyPlBk9tc/DbqAJKYSKXM2L0WGdoGmjbTmZNcP25uXImvQUqXT6nGfoGxqm1pnjdNKKiyTMElCzvBqb94mx3WV8rOfVjwDzuTEzTX7W1tO3B+zr7scE+7rDsCXautualaGa2YoKCHS7PTnKt5bL1uyMOq/FsQsymxts/gsaWs4I1IVb3G+bWE7bcjIkqaig3mOdtxdyDQUwLBYLgy/UPFm5eariSYNdVrakZ+dIdm6+FJWUNqksJMZFqAOP33/osGzcsUuWb9giS9dulJUbN8vGnXvkQNJhyczJrRN6gTztcXhuPG6TNh6aMsLjVmzYLBt27FaPw/yXu/hg4/y6MrTpO4ZeDAimIIyTkKzN287dat4wX1t275WUjCyZMWWinDljqmqKyZCcliGvfPxVnek5P196Vk690AugQg5ek+O4DL10XhY9+HL11VeL2cPSewy+EFFbW5y1RQ6WaB/wy3JcdrnWQhke2rlL6RIREdGRbeXKlfL7b79Jenq6bNq0SU488cRGLzZYtWpV1w2+aGzWPBUcMQfGCprEEakWa/4+KUlZqE5COmrshBiat0HQASEGnBzEbdV0UnVVTeACV3EHdZ+hrmZXJy6rbNp0Nkhp2jJtPL3yAk6k4iSlNl/2E5ZB2jTxgzimk6nmCyfFgnrNEv+okVKt9atAhqZ+8KVCLOFDtcfHqROcJv8I8TUFqflGMwtqfnqdIgFoBkN7/fZmeZoYfNFgeaD6DE7aoQqBOtlq8lfLBM8D5sBu2jSmSnDPk7X7e0tZxio1vCXaa57wODRDgb+YFtZJVWWZlKYuUsu8Hmw72rJUJ1jxGL9gbfradlGtLV1tm8NJXkA4J6j7dAnsOVPbHiLUtuDoSA++/LICF+wx+NJejPMT3ccMkPgRfeTw1v1yMOGgOg8yZkxtVRFnCxculOTkZJkyOkoG9255pYfOwpNjCKBpPP/IkapqVmXRQSlOmqf24848CVUgCFFZdEg93uQfrfYdvuZgVbUFHfYHKjBZnidl2nGjJPl39fz1aPsMhO18tGMMwjM+5gD1OhCGsU8nWIVlSpIXaMcQq9oXuQu+VNtKVNUrU2C8CvEhLIn5UNOxhKp5Lk1dItrBRYUCoanBF0AFLRWe0faFvv7han5xLDT5R2mP0zptOPan1bZibR7XS1n6ypp9qae8LfiiLV11TKgsPKiOLXit6pilL98lyUWyJDEVecsWQcWWMd1iJDIoQFYnpcpHG3dIQZlny66yqlpSCorllEF9VZNJOPEcFxwkP+85qM1XC2dMYxNfmRySIWYcIF04mFoiKzbnSExMjJx55pn60Paz+HCiWLX3kTPMbUxgsBzbvbfbCisIcqxxEZwZFxsvYRZ/SSioH4bFc02J7yndg12HDFenHZbFKYnq+Z2Ni+kuZ/YbIqYGwgF43P78HHlj+3r5fN92WZpySLZmZ0piYZ6kFhepcEYGupJiSS0pkgPaPG7KSldBCgRZ+oSGq3n3xMd7tsoXe7fLyrTkel2aNm1j2c1N3CP/27JWDd+TlyOHCvMlqShf+oZGqAo20JLgC6rzPL95lQrzOM+H0WVp4xynzQ+e/7lNf9YM35SdLoUVVpfLG5KKCmVtRkqdaW3MSlNBlmi9qk9rBl9StHX0we7N8sGuzbJI2zY3a+sG6yhFW57p2jrDusNfrLuD2jpFiGdpaqJs0caLDwqR6MAgt9srltOLm1fLH8kH67weo4vwD5ChEe6DXmja6+2dm1R4ydXj86xlcnRcT7fhlUOFBfLMppXqPef82Artu9TR3Xq5nXey6xTBlzVr1jD4QlJutapqKQh6oMPtsnJtZ9vIBws8rriktOZxBUXah0IPHteYU6YeLXn52oe18nIVYjHmDX/RP274ELnuwtnSr2d37UOkfVeENN+KjVvk50XLVT91bf6laJe7Wv7+97+Ln1/jaVNg8IWI2tr6vH1SVFmqfcmsdNnhg/mYcP4YS0RERN4Lvzsh8BISGy7JB5Nk69atMnPmzAbDL1264gt469X6pRliDupuP2HpY1YnK80hfbXXM16bzjESoP1FU0k46VdZlKQ9n73Jh/onG6u1/yq11zdYLQdUtjEF9VAnaXHSDvNj0eYPTSKhIoq9uaOmB1+qMP8+Jm0Z9VKv29ccoq5gx/JCZYHA+OO0ZTBZhUcQNkEgx/VJwKZpr3mqsuaLf8QQwYlonPTV/qef4J6vtiFX0FQWTlirwIv2GKxzNIFliR6jKhgYVX8QzjFr2wtO+jqfcHb1+iorq+SnRfvl5c82y49/HJC5ixPqdbGRAdKrm/a4VpSRXSKPv7Vavpy/t97z/bwsQc3XsAFR+tiemb8yQ3IKKuT444+XAQPYHFRbM85PxA7tLQNPGKe9L3xV+CUhIUEdJ0aMGKGPWRcqviD4oiq+dKHgCypkVeTtlLKM1VKeudZekUl7LzrDfhjNHZVp45Rnb6xpGs0Z9iOouFWWvqrh6WnPi9AKmlFCCAb7BlRDsZVlaI9HlamVUpLyh6oohv22OzhO4TnKtee0laD5tXI1b9bCA1Ke/qcUH16g7ev3SEVxslizN2nT/VM7fmzWdmnOF5tWq8dhXBxvUJUM81OhHW+wbIqT56vjRWVhomoaTk1HW254HY4qiw+pZYSAIZp1wvzVoR1DMW0sS7W/046DqJ6F564sTdfmbYu2j14uJamLtft3qnGbylaWWfNaVTN2TtPwdB1BY6+nzrRcPFcN/XXjc0d51ka1ntVnkZIc+d/GBMktdX2MaYqyykrZnpEtaw6nyeKEw5JeVL/SSEOKrBVi0fYXo+LtFX2C/f0kJb9IDuY1fR04QzNOE4MzJczsOohzMLW0w4IvqNixMjVZVSNxxc/XJDN79nNZCQVVUj7bs02Si+s3hzSr90AViliXWbfKGyA80D8ssibw4eynxD2yIydL76vrLwOGypjoeL2vvqKKCnl350b5RJuvzdkZKuiCUAfCNjh/5wzDcB/GySwtkcSiAlmXkSK+viIDw6Iarb6BoAlCIAXW8nodqqugss2C5AR5b+cmOViYL8WVFaqyCp4XVVTGxsTXBEKaG3zB8vxs73aZf2if5JSXuZyXAJNZrhkxTvqGRcj+/Fz57sCumvuKtWXW0NnUEm2eHaeFrtxmU68tLtB+vGyN4Aum8fX+HfLW9g3adpMmh7V1gQoteC4sK2dYhnhMkbbusP0mFxXKpuw0ydWWwYioGBVic4ZhCL3sysuu95rQoWrM8d37uF3vCLa8u2OTtp3ku3w85vWk3v0lwM2F8Kg2g9BMnovH4nGjo1y/J6iWEXypv3a9SGskJola28VnnSovP3iX/N+NV8vp04+Tgb3tSe6jx4yUmy+7QB644SoZPXSQepMZsnLyZP7SlXofkV1T9nHcHxIREREREXkGV/MHx4TJli1b5P7771dNWZB7OCFlNGtkKzks5U5XqTdFVXmOFCV8q5pKwsk6e+WXGPELHaA6hFkQtMHV+hgH4+IxzhDaKDr4nZSmr1AnXxHgwJXgqAKD6WCatrIsbZzvxWbFxSXu4eRo8aG5anywVx/ppc9PN6my4qr/+epEW3PhxG9ZxkrteX5UJ2yrtX++fmHqeSzhg1X4B8EhH1OgVJamqaad2lprzhNO4Frz92vTrFShF/xV/U4ndh3hvhJtHaMig33Z+4ivf6Q9/ILnD9WeX1v+CMVUFB7U1rVnF4tZK6rk0593ycKws+W3gTfV7wbcKA99sFsOHm54u2iKCu05739pufxsmunyOZfHzJY3vtwqVVVN++3Gk+bYqG1YQgJk8InjZeisSZKXlyeff/65/Pjjj/q9dRlVzLva2kIlk4qiQ9r784D6i353sI/BeJUlafqQ+hAowXvdk+nhGIAgY5l2fEIFmcIDX6mu+PBvahjuU+G+RqjpFCVJKQIq2vFCTUM7HqBfTUPbT6lQS2GCPv/1T8SDCllq95Vlb6iZH0yvNH2lHoZBMCfT/tq0Dred4fH2+xPUc7qECmkIpxTsk7K05TXzXJTwjbY//UMFTtXzuWk2rjF1Xmtxsj60VlPWUWOvx3Farp6rDvW6s7XnTFTLFK972+7fJTm/aQEVd3BiPDGvQDamZEhqQdOr6OMk+rw9ByWn1L48UFHk7OED6pz/aa7SKrOsL7aHdxvSEccLNLUzLNIe9nElvaRQsstdryMERVBxwxmaihkeFaM6V83G4CiKKh0ILThDmCax0PWxHdMaHO4+fJqlzc9TG1bIDwl7VOUWNJXTVMUVVtmTly3v7tgs7+7cJGXa/LTEdu11frh7i6SVFKvX3RbWZ6bK3MS9KnThSoifn8wZOUHGxXZrsFJOR8K6ennLGvl49zbVjFChtbzJywvrCqGeb/bvlBc2r1ahGWcB2jY0oYEAjhFOciexIF/SSt3vX9K1+w4Xuw/LodqOqxBPqJ9FNStGnvPq4AuRN4qNipTxw4fIOSdOlzuuukSev+82+ez5x+Shf14rF581S0YMHCD+ltomjopLy+SbXxfK6k3b9SHU1eHHpqbijyFERERERESe8QsOkDHnT5eg6FBVSfjhhx+WkhLXP8wfyRcZ4KRV/s43JXfrc+ov+l3ByamCvR+p8Qr3f+42zIAr7fO2v9zo9HDSriRlkeTtekMK932qrlDHY3EFe2nqYjUM92EcVycHDWo6Sb9K/vZXVFWY8uxNajqYXuH+z6Rgz/vqJGBJ0nw1T+hKkn/TH12r2lYuZVkbJX/XW1J04GvBFfqqaoD2F/35u9+RMm06RQlfqWnkbX1RUFHAWcGeD+z3a8sAj3eG5ViWuUHNV6G2PBH6QIgIV+aXZW1QryF/x6vq/rLs9fqjWqY95wnNUeVte9H+fNpf1TxVI3ByFuNh2WOdYf1jO1DPj+V/8DttWi9p28THLuff1evz9zfJ304dIj4Ja6Si/2QpHXS8UzdNEnrMlNe/2KzGbw2L1iTJmtLekjX6r3Wey9ZjhPik7ZGiP3+SPt1DxMe3ib/d8KeeDuUfGiRDZk2SgTPGSU5OjnzyySfy66+/6vfWx5/m2h/239iPoAoIjgmoIoJhTYUAByqUqWoi5TkNBjoaUmd+tOk1FP5rEVR9qCyumWf12isKVADnSIdlite9O69CbK38Ec3WxHCio5ySMtmXXRu66BkWIvEhLW+lolo7EKwrjpMqNweEjvycisoWo6Jj3Va4yC0vV03KuIJwCZrPcRYfGCz9QiNUh9uuoCkiVLlwlldepqq0uIJp9Q5B1b76sspKVNhhRWqSy+k2BdYGmtP57sBuVTmm0kVAxxMIonx7YJccdlERp7XgdaO5JYSQXMF6/dugkTK9Z1+x+DbcNGxHQejltW3rVbNZ2drraem7AdvQwqQEeV2bpnP4CVv5qOg4l4EsyCwrdrssAU1iobqUO6XafQfyXYcWEfTCe8aVvmHh0jckQu8jT/hoO06X2wquhinXdlyt5YMPPlDdtddeK3PmzNGHNuzl/2fvLACjONow/OZyd7m4uxAkBIK7O8WhQFsqtKUG/dtSd3d3WmrUDajRFmvRUijuBIcQd/fk7pJ/vrnd3N7lLgYhAeZph7ud3Z2d3b3Myrzzfh98gK+//hqVLl4seUu5AkHLsnLRe+gQYXJ5qQ8KgbR01Tp8u2wFsvKapsQWXHy45iSwxrcK//77L1xdG2aR+uyzz2LFihWYM2cOTwKBQHCu+T5pA4rqGOXqrnbG9eGjpSmBQCAQCM4N8rsHEiXQd3m6rKysZlogaCiZmZn83VPMtEHoNLE/0mPP4OBPm1CeV8LDbj/xxBNwc3OTljbx1ltvYdWqVZg9MQzXsyQ4t1CIHXIUoRBD1F1QbaxkqZx3HjYGCpnjwO5HudsIL6Os0WUQVBcVlaNSA1UG7vLS1A7QuiAXEwe1jn06sQkHtutGVBvKUUXbqm5aJ8nZ0tJ1Mv0WTOGm2JTp+NNvoQkdxwXFFZj9xHoc7nMfSmPGS7lm1CXZCPn1HnxzX0fEtPeVcptGVm4ZZj3yN+ImvYHy8D48T11ZCN3JzfA+uR4D+3XG7l++x5fPjUJMh8Zt6963D+FEQglvm8aOHSvlXhiQCwp1K9j6lJO8nJzqW16ZT8loZL9R6btymj7lsmla+Wkvj1JGRkbNNaLL5YN5GURZXjFil/2H+P9iERgYyPsuRo4cKc0FHnvsMezcuRP3XdsO4weJUAMCQXNDIpDPMrpge1Hd4U8aA3VqN6bTnAah0jpKru3eCbN7duLf9awdenHjDuxNNTnmKbEVNqcu1A5VeCViOwI0ta+HG3dn441vT6Fz585YuHChlHv+OFmQi3s3/80FA7a4q1tfzO7YTZoyQXv/9v7t+O30UVOGAhJZvDhgJD+2z+zchI3J8aYZCigUzNuDL6sV/obcSx7eus6muGBcRDs83XcYHNl9ohISppA7y5KTh+t0aCERCDlrRLh5ooItl15WwsPk1HUu/Zxd8HjvIRgUZPv54Vm2f2uT4qQpS1zZtuhIUSghe8yN6YWbO/fk38lp5MEta3Awp/bvjaDQQs/3HyFNmfd78clYu24vVO/Heg+Gv0KA9E9KAp7YvkGaahoUxundoeNqXErqq7tyP5XQkV9x5gQWxu6uU7BE5462GcT2w8lRjcTiAh6eqq5zR8d/PvvtTmsbbfF3TsIW+r3bcisiR5yXB43G8OAIKccM/bae2LYB2zPMIUdtMTUyCo/1GVqrbaEQTHf9uxrxhbW3e11UF9zZrZ9dAZrAjJq1HdTf2qqFLx9++CG++uorIXwRtCo+e/EJDOjRFTons6uLEvqTKiwuwd7Dx7Bk5VocPnWaPSQL0YvAjCx82bRpU62XrvYQwheBQNDcCOGLQCAQCJobes9w+vRpnuLi4niizivqjJI/ld/lT4GgMZD4Re7UNFYaasQvFfml6N+/Px555BG4u7tLSwvhi0BwIUJvs/cezsCNC04j97bvUeVQe6Sy6+FV6LTtDfz83jS4OtsevdsQFv64Hx8dC0LOpGdR7aiFV+pulC7/EFMvH4NBY0dh2VsvY0RkBeZf1xOOjo3rlLjv7VgcTyjGpEmT0KlTp5rroC3hhnWecp48bZ1HyCIR+lSuK+fL08r1bJWlXFfOI2ha+UnQd+vps/kk6Lu9/MZ8Kq8RSkpzi3Dw501I2nkcwcHBmD9/PgYNGsTnPfroo9i1a5cQvggE5wl9tQovJfdDQoX5fu1scNNqML5jJNKKSrA9Ma1eYYqLRoNrundk61n2/4R7uqNLoEngSCUcSMtCOitTCQkZlh0+hdyyxon37wg8hAHuGdKUmQ27svHmd6fQpUsXbhRwvik2VOKh/9bhYHbtuhEjQyO54EKjCPtUpK/AfVvW4GiuKcSkknt79MfVHbrw70tPHcb7B3by70roSnp39/64Jsq0nAyJVyjkjfXZI0HAo70HY2pkRynHzMGcDDy9YxOyyizPkwytOygoFDPbdYaXkw7Ojmr++6ioMiK1pAhLTx5BbK5twQbVs19gKNv/4fDU6kyZCuoSvtC6yv3wYutHefnAkR1HEvacKsjBtVFdmyx82ZmRgpf3/Gd3vzt6+uCJvkP5NpUSL3LpOZJndmNMKirAF0fsh3W6Probd0lRomblUZ6H1olPN1X4klJchMe3b7DrhEJ09QnA1VExCHF1h5PKkZ9PColFQq3f4o5iW3qK3b/3DuwYvDpwNELdzO2MsboKL+7ejDWJts8b7e+dXftKU2aSigtx7+a/eNiquqDQYe8PGwd3jenYyBzPy8G9W/6uJfChv6uXBozCsJDaYhtBbS4I4YtwfBG0RtqFh8LDzRXdojsg2M8P7SJCoGYXxJz8AiSnZyI+ORXxqWnc7SU9KxuV+rOL9Se4+HDLTQTYzdPGjRvh4eEh5dbNc889h+XLlwvhi0AgaDaE8EUgEAgE55qCggKcOXOGC1wSEhJw6tQp7uxCqaSkpFboGbWTBlpXZ2hcnODkquOfFLJGYB8ajSq/1pHDoypf81yq86lD08XH9BJTKX6pLCjDgAED8MADD8DT02SHLoQvAsGFicFYhcfe3YrfMRLFI25HtVVEf8eKInj9+jBemqTBzMtqd4Y1lGFzVyF3whMoJ+eiPSswKCYYffr3RlTvXkg4tA8/v/A4vnt5NMICG99Be/Pz+5CeU8HfDTk5mTpB5DatuT4J+m493ZRPCu3EO8zof+r05J+mPAdHaZq1zbx9ZvN5M83+UdGIfJpNGTRNIaLYJy9DLpcSLcfXodX5CqYRz3ye5bqUTB/sk7ZNq0mftC7NY4WyBItrhJKS7ALsW7wRaftPIzQ0FPfeey93CyPB5O7du4XwRSA4T1RUqfFQwmAUGW0PPG4so9qF49a+XZFfXoHn121DVmndTm+eOicsnDoazhq1lGPCkbU3Wkez0LLSaKwVPom28dz6bUgqaFwIm2lecZjpV7uzff2uLLz13Wl07doVCxYskHLPH1Xs6vrRod348USslGNJpIcXFg6fCG8n8zPbkdws3P/fGhRVWobmIkeVt4dexsUKBAlKHtyylrtzWDMqNBLPKQQ1xqoqvLB7s00hCQlW3h82HlGePlKOCVqHQhwtO3O85rqlhK4nUyI7YnbHrgh2cYNa2pYMnV9yD/kodg+2pydLuZY4q9WsniMxLDhcyjFTl/BFhsLq3BDdDf0DQ+Gm0dDVkws1iior4Mn2K9zN1HfUGOELhTh6Yde/2JOVbnO/A5xd8USfIegTEMJdTJTQ+Vb+pulckssOud/Ygtx7hoe0kabMqOk6TRdcRlOFL4tPHsbHsbvthpMaGBSGO7v24S49yr9LgtahMFwUjmpF/Amb4hc633d07YtrrQRWy9nyr+/danOdgew8vTpoDJystrclLYk75SjrSufWOpwS/Z28Z+O3ui45Ds/v/BdGq22SoOeD4ePZ77Px95iXIhr2N+Ti4tK6hS/UkNM6QvgiaI24u7pC58T+kHTswZc15JWVepSTRTe7uaFPwTmAXSg8K/NR2ULH0+DkDr2uYY4sjUEWvmzYsKHmZWt9COGLQCBoboTwRSAQCATnitjYWOzZswc7duyoEbrIidB5ucIrzB/eEQFwCfCC1kXHkhMctRqo1CqoHCk58g4r+i6oA3pZKb/WkV9cKl/zXKLzXXwtBxjI4pcDP22CobAcgwcPxt133w0vLy8hfBEILmCOxeXiulf2IGv2Z6h0sw6JUQ1d5gl0WPUAvn9uGIL9GxZqWkl2Xhmuee0Y9B7BSDp6GLc+NB8xAwehOCcb2/9chr0b1uPJ2R0waXhbkwCjkdz47F5k5VUicmhX3oSZxCOSmINB0ybRiGm6RsBB0+wLF3mw77IIpGZaOd9BXoeypPIpQ16OIW9HXo+Qr790LTaVQxNUN1MZ1J/FtyV1bMkf8vr8X+k7wevIv5g+6NO8runTvDifaZpfk8eolcemFN/l/NrbqtkSx/oaoaQ4Mx97v1uHjCMJiIiIwEMPPcT7J+i+5r7r2mH8QCF8EQiamyy9Mx5LGAyjxV9u0wjxcMUTIwagnY8n71T+Jy4JH27fjwqD7fAvBHWIT+oYiVv7doOmkc8iK4+fwZd7YlHWyMHQg9zSMDfoCGuqFfe5jJYWvhCbUxPx1I6N0NsQIHhqnfDe0PGI9jaH+vvp1GEsOLirlnAg2ssX7wwbB2/JHSWvshz3b16DE/k5fFpJpLsXPhwxAT5OznyanDDIEYOcMayJ8fbHO0PHwcPKoSe5pAgPsHWSi22LkLr4BuDZvsMRpnD8sKaa/bc7Mw3P7PgHBXbC7YyPaI8n+gy1cL0h6hO+0PIk+JjRLrqWYwwdOeq659drRkOFLyS8+PzoPiw9edhmiCPa5tyY3pjVIaaWWMQWh0nExLZrT/jyysDRGBlaW/iipCnCF3INenjrertOQ8Gubnx/KZyS5RXektMFeXhy+0YuYLJFd79AvDl4jIUDy8n8XP5bsxXei34rHw2fDD9n0+9S5qPY3fj++CFpynSc23v64FiepesRCY0e6z0EkyOjpBwTHx7aZVNcNiykDV4aMLLWb0tgGyF8EQgErR4HowHuBSm83WioM8q5Ijk5GT8s+QmVzh7QOzdMnNJQ5FBHQvgiEAhaE0L4IhAIBIKzobCwEHv37uUdQyR8yc/P544vhIuPBzxCfOAR6gfvNoFwD/SG2lkLrTOJXdRQqU0il5qOKoGgGbAWvwwZMgR33HEHvvzyS6xevVoIXwSCCxByffl++XG8vsMNeTNeRbVVyCN69+Lz96u4PvAInpg3UMptGFVV1bjrxfUY+dzXMBoM+O7JR9Bv4niU5OVh/76jKIIOobl78P3rk+Hq0rRQSjc+sxdZ+ZXcgYTEL4TpUihdD9mHhdBDnpa+mz5NX+pezjRPymFfTN8srrt8vnIhBpvPJ83/mOtnmrwoKUzJxp7v1iH7ZAqio6P5cTp27Bjuv649xg30l5YSCATNxf4SX7yX1kuaajpa9nxx35A+GNYmlLu1ECRI+XTXIaw9GW8lMbHEVavBA0P7YlC4tajSPgl5BXhm/TZkldTtKGOLrs45uC/kANQOluKSdTuz8Pb3LSt8oTAu8zetRla5pVsnQR35z/YfgbFhbfk0iWOe27kJG1Pi+bSSy9tG46Feg2pcRkiI9PLuzfgr8TSfVkJOKm8NuQy9/EzHnwQM92z5C3nltcUI06VyZZGIzAZWB6qLLccQCin0cM9BmBIZVWs9ayjMz1M7/sHWtCQpxxJrkY5MfcIXCl9DIgilW449Gip82Z6RzEMc5ZTVPle0nxQOal6X3g3aJtFSwhd7rkEy13fsxvfD2qXHGjr3JCr56dQRKccSOg7WDiylrL6Pbl2PPVlpUo4ZF7WGLT+uxrWIoPBm5IqzPztdyjEJwia06cAFSNZMb9cJD7Pfq/yrI4HS49s28HOnhM4X/a7p9y1oGLLwpVXLhOxocgQCwSUExQweOHAg1qxZg99++63Z0/r16zFy5EguLnnwvnvgoi+FriyfXYjOZXtkuqw1po0TnQACgUAgEAgEgtYIhTH69ddf8dJLL2HRokVc3E1hjapdHNF+VA/0v20iBs+fhp7XjUb0+L4I7dUB3pEm8YuThwvUOq1J+CLudwXNDImsgrq2RY9ZI6D20GHr1q345JNP+MAvgUBwYaJ2VGHKyEj4pe+BLmGXlGum2kGFokFzsCLWgC17knH4VE6D0/6jmVi3PQlh0Z3RpktXDLviCvz98x9YXxaJ092vhz7lJJ7636Ami1440qWP3g9R6B1Kzt6U3EzJy427pOk8peThyq+dPLlLyc2ZJ62bDlpXKblI4QIpOVPSQsOut3TN5clJwxO1izVJo4ZK48ivyTWJRKmUVJQczI4wF/kl2yPEl18rSKx78uRJPjhOIBCcPwqMDeuUr4/eIQHoExpQI3ohKHzR5OhI+LB2si5KKvX448gplDfQuaXcYMQvh081SfRCVFY72nS4kZ+RWvJZyV/ngjbutgfvknjlkELQkFNehpMFudKUGerE7+EXaBFah7738g+yKTwpNxgs3F1SS4tQaMOogQQs9sog8YQt0QtBrjNUH1vrWaNzVKNfQLA0VZu8ijJk2xCa1AU5eIwPb9dgAUpDIGHSd8cPIddOXSic0vXR3c7pNpuL04V5XFBiCwoh1DcwpF7RC0HL9PEPtuuYQk5CmaUl0pQJKr83+03ZgkRQ1q5Daey3ae0o46Nz5m40VJY1JOIqVewbiXuSS2o70nhondDFW4htm4LwxxEIBK0eegFAo0Yvu+wyzJw5s9nSmDFjcODAAW7BvnDhQm7f+vQTj8HTsQqu5QV8pNA5QbqfEuI+gUAgEAgEAsGFCnUCkdDllVdewZIlS7B//35kZmfBs0MQ7ywacPsUdJ48EKF9ompcXqjTjjrXBIKWQil+cXR34uKXo0ePSnMFAsGFiK+nDk/f1hNu276G2lhbyKb3DEFBYQV+PaTF97tU5rTbsVb6Ybe6Jv100AmuXiYHchqUFXfoIHJC+iErfAg0x7dgai8X9Ig+uw4JubtNiD9bGex80L1L9yuHwS3QCyUlpk6xwpLGhS4RCARNo8R4FoJCCXJsmd2zM9yswt8Qkd6euKFnjCl0Wx0cy8rFjweP1QrZY4v9aZnYnljbIaKhGKpVbDvShAJ50/XVtTlxUqu5uMQecYV5XBBAnCnKQ2aZpZCAoE789p61o3p08vLj86yh3aYwMUZJuHIiL5eLbKwhAQuFULKGlsyqQ4zi7+wCb52lQ0tdkPDHnniC3FDq2pYtvJ2cbda7qZDTzuITsdyhxcbPCBFunritcy+EuLpJOa2bnLIyu393bhptneGprAlly9pqBwj6TSUWWYpO6I6sq2+ATdEK1elYfrbFMSYhTIFVWKQoLx909fFHoHPtMJupJYXIUPyNpJcVIdfGQIwI9psLdrswzldro1ULX0SnsEAgIAwGA0+jR4/G5MmTmy1R+bQdsmRfu3YtfvjhBz5a9flnnoa/qxau5XlwqLIf/7Ox0IsTgUAgEAgEAoHgQoNcXV5//XWsXLmSO77otdVoM6wLBsybhF7XjuLhGrzC/flodbX27F9cCwTnEqX4ReWmRVZWFs8vKRMdmgLBhQiJRob3DcMQ72y47P1FyjVTDRWqtc5oP2IK+t30kDnNebBW6jvngZrUbeatKC8pxZLnH8fXD9+DPUfTUDlgFhxL8+B+Yi3mTO0EtfrsXq3LghfxDrz1QU43fh3D0O2KYXDxM4VfLxbXCYHgvFBeZRm2rrFo2N/vtd07cYGLLVkhCRiGRoZicHiQzfkylUYj1pxKxKH0bCnHNskFxfhh/zG7DhUNgYQv1TZq0xquD3UJAYi0kmLkSR3/+7LS+XGzhnfi2xBdBLi4IoglW5BzTIG+gos6bLnIEJGs3AAb4gIS4uTaCM0kE8i26Wpnf2zhqtZC62j7d0niCapjY/DVOcPjHDqvHMjJ4CGjbB17jcoR10TFoKOXDzuXdf3iWw/k8GMPP3bs3DW1xVL2cNWwc6eyP/hGFm0pofBVtkQrRGJRYY1jCwmzKCSSUpRFLkLkMuPn7IIIj9pOSfnsb+VMYZ40BfY932YdSDhDoZUEDUduL4XwRXBR4+PpgSmjh+GhW6/Haw/dhWfumos5MyYjNFBYRF2IUHw2Nze3ZkuurqaLmZHdIJSVlWHKlCk8xBKNAnzy8ccRGeAL17JcqIxNv4ltKmL0j0AgEAgEAoGgpYmPj8enn36KL774wuSS4aLmHUID5k1G58kDENStLdwCvXmYBYGgNWMSv0Six1UjoPMxvYQvLT93gxwEAsH5Reekxvyru0Cz4xeb72wq+l6BFYs+h09wMALbtmtQSj12GJq2XbDedTj+DZyKzBH3QO8eBLc17+Dxa6IQGWo77ENjEG++WzeVpeVI3n0CFQWmzlOtplV3pQgEFw0a1dkNFo3y9cbIduEWYXWscdGoMa1ze+4MUxeF5RX4/egpu8IGCqXz59HTiM+rHaqkMajYPtfVwrR030BdQoDcijKklRRx4U9sjklQbk1Xb9ud+OTeEe3lJ01ZQs4xVG6RvqKWK4dMjI8/d6Sxhpw56hKjkBikrt+HNSRmOJeiERJfNSTMUkOpMBhQYrDdZ2Wsti8caq1U2BDwyDT22JnOXePw0enQ0dtHmrIko7QEORWm+wISZh3Ptwx9RA5G9JtWO6jQ0y9QyjVDIpmjeWYx3Yn83FruNrSPPXwDWZtw7n4jlxLibu0CgkQcg3p1w9A+PS1Su/BQaYmLmxH9e+Oj5x7FD2+/iB/eegHP3zPProBF5+SEG2dMxrtPPID751yLWRPHYsKwwbh87DBcf/lExLRvx5chQcx3bz7Py1z08pOYOW60VMKFSWOOkaB+KLTS/PnzsWfPHj6a9f777kP3qPZwKc2Bil3UzhYh7hMIBAKBQCAQXCiQIPyNN97AqlWrkJaWhrD+0eh36wS0G9EdXhEBcPZ2h6NGhDESXDiUF5Yhceexmg5NtaN4sSgQXMh0bu+Dm0d5w2PNW1BZhaou7zQWKSXViP1nrZRTN/mpifjzu8UoHv8Qcv27oSioOwyBUXA+tRltSo9i3OAIOJ6DNkO0Oq0XfXkljvyxDSn7T1MPKs/zdhcjrwWC84GLY9PdlVw1GlzbPRreuvodITr6eePqbtH1dqIfSMvGb4dP2Qy9EpuRjf8SUy0cH5qCBlVwcKhdhlxsSwtfvHU6m+4VBIkujuXl8PAtScW1BSq8E9/Pdic+iU96+wfBkS1jTRkrl0L3kPglq7x2+CQqt6uvf5OupVXsPqExZ4zOfWvuy+nmG4AhQWHSlCVU940pCfg78fRFIbhtrCyuil3D6Xw3BkcHFftdBttsG0joRa4vREJRAdJLi/l3GXI3CnEzDaygUF4urE2yhoRI5PJCKb4oX8o1E+Lqjo7nMBTWpYYQvrRySOxCAg4SM3zywuN45q7b8NSdt1ikdx6/H1++9gz/HuRvWx15oUP7dfMVUzG8Xy/07doZfbvFYMrIobh2ynhpCUtuvXIaT/3YcmFBAfB0d4Mzu9lxc3GBr5cnXJx1uGL8KC50oWWozCG9euDG6RPRo1OUVMqFRWOPkaB+yAFmxIgRePTRR5GYmIjFixdjzpwbMax/X+iKs+GoL5OWbBpC+CIQCAQCgUAgaO2cOnUKCxcuxFdffYXjx4/D0dsZva4dja4zhsC7bZBwdxFckJRkF+Lgz5uQfvAMtNLoU3dX0aEpEFzIqB1VuHp8FNyOr4E27bCUa8Lg7ImiUXfh5w8+QGFGmpRrn5WfLESmd2eU+XVEtUqNagcV1MYyuO74AY/c1BMe7g232K+Tlu3HFNihyliFo39u4+JINVQICAjg+Rq1OGGC+nFQaaHxiIKWtSFy0ri3k+YKGoKHqlL61jhUKgdcHtMe3YL80BCdCIWuuSyqDXqFmP7G7VFuMGDFsTiczDaHJyEKyivwxe7DyGefZwu53LRmxxd77hUE9XDEFebx8C0UxsUaf2dXdPDylqZqQx38HhqtNGWGBBtHcrNxqiCPi2CsoXLbe9ouV+eoho/OWZqqDdXTVngZexRWVthdnrZFLh8tCW3/xujuiHAzheazhvb3+xOHcMLKnaS1Yi/8FVHQyHNXUEnL23eQoXBbtiDRiq3zSi5Px/NMx3F/VgZvH5Qo3Y3CXN1thuIiB6OsslIeIoxChVkT7e0LP2f7v19B3QjhSytmSJ8eePXBuzD3qsu5mIEEGeTu0jYsxCJ1bh+JQT26YkS/3ggJuDiFL7RfkSHB7AHDPILQzdUFUZER0pSZy4b0xxXjRyPQzxeO7KHXHh3Zuj6e7jU3DbRsSGAA21brdUghlxpydeluQ5zTmGN0sVBSUoL77rsPt912W6PSAw88wEMZWWNLiOLEjnmfPn3wxBNPoIpd1L7++muMHTsWM6dOglNxDjTltS9M9WP6zQnhi0AgEAgEAoGgNbNr1y689tpr+Pvvv5GVm422w7uh/60T0WZwDFz9PFv8BaxA0BSUopeggEBER0fzfOH4IhBc+IQGuuH5eT3huvkLqKqVnRwOqAyMRnaFBpt/WSLl2SY3MQ67t+1G8cDrueCFU10Nl+3fY3RoEQb3DGlQh2pDEK1O6+TYih04syUWxnI95syZA09Pk8uBuO0RNAS1Swjc2kyBe9urapJLmBiY2hhCtOTu0fj35m28PDC2QwQXtDQUDyctZsS0h5O67nVyS8uw7MhpLsYgjFVVWHHsDM7kFZyTd/yuKj0cbXhZVEvHQWXDEeV808XHH+42BCpERmkx9mWl23S+CXV1h4+T/U58P2cXhLvbdpNJKSnCqYLaoWAIEr346WyLFshJxt48Iq20xKZIxx7kymHP1YdchgLYPrQ0HTx9MDu6G5zs/P6Tigvx2eG9yC43uV22ZoJdTY4ptiDHlXQbYhF7pLNzXaK3LaYj0VKwi+1tkWsLubfYghxbSvV6HuZI+auwdjfyppBJXrVDJuWVl/PzQW5GtD9KyGWG3GbIdUbQNFr1kbuUO4VJ5HLndVdicO/uCPD1sRAz2IIufE5aLbQ2bJMuBk4lJCE1K9viN6HXGxCfnCJNmRkzqB+C/X0tHh6T0zPw0sdf4rYnX8KXvyzHGbZeXFIKSq3UuLn5+UhMS5emWgckdiInl9cfvhufvfgEHrntBvTr2lmaa6Yxx+hCQ36hbv1ivbi4GNu2bUP//v25GKUhqV+/fti6dSsXzdSHvD01+/vr0qULHn74YYSEhODbb79FVFQU5t50I7SledCUNS6Gp3zD2pg2TnQqCAQCgUAgEAjOJ5s3b8aHH36IuLg46II80Wv2GHSeMhCeYX7QuLTsiDaBoKmQ6OUQiV4OnUGgfwDuvPNO+PoKG+lLDa1XJ7iGT4BHh9k8uYZPhMazozRXcCHjqHLAmIER6OYYB9dDK6VcwC1tHzQ/P40B/bqg67CRUm5t9KUl+OTB+5HbbSYMHsFSLqAuL4B27x+YO6MTnLQN71Ctj4vhXQ+92yKHlCqDEcZKPU8UJkhfVgF9STkqistQUViK8sISlOeXoDSvCKW5haw9LkBJVj6KM/JQxFJhWi4KU7JRkJyN/MRMnvLiM5B7Jh05p1ORfSrFlI4nI+t4EjKOJiLjSALSY8/wNj3tYBxS959Gyr5TSNlzEsm7TyBp13Ek7TyOxO1HkbDtCOK3HuaClro4/tcunNq4H5Ws7tdffz0mTpwIx0Z0ogsajy5wMLy63gPvbvfXJLe2V0hzbUMuKl4xd1ms4xF1ozS3ZXFwdIKjzg+OzoHmpBP3Go3By7EcOpV9hwZ7jO/QBgGujRcgdAnwQ6/gugdD01v83SnpWHMqgYdOScgvNH0/R32YPupyqGyEOrLoVW9hwtw8eAgWW+RUlOOMjZAtBAkBtI72+zed1WrukmGL/IoK7o5hi17+QVxoYA8SHNgLY0Xij5P5udJU3ZQZ9NiVad8tLpQdF+863GXOF2p2LEaGRrLURsqxhH6re7PSsPhELHctac2Eu3my34Xtvm5y/9mX3bA+XBKobc9Itita8nV2tvubJteWfv7me0ElFNIrkSVyOlJi7W5E4hUSjFlTWWXEAbYPtD6FClNCLjPkNiNoOg7s5tTmGS8vZzemrFE5V3zzzTc8zZs3D7fffruUWzdvv/02fvzxR1S6eLFk3wrrYuS1h+Zj8sghFkIWOlXFpWVISE1DfmER1OymmxxK/L29oHPSIjMnD4+8+QG27z8krXFxMbBnN9x21eVoExrMGiwjtu07hEU//Y7UjCxpCRO/LHgN3aI7SFNABXvg+urX5fj8599RWlYOLw93/unq4owbLp+EMYP6clePrNw8LF21Fn9v3obyiqbZ6TUH9825BldMGAN3dtNG4iaj0YhFS3/H+9/WHqHS0GN0oeBgNMA1LwmLFi3C3LlzsXLlSgQFBUlzgby8PEyePJmLUUic0hD0ej3S0tKwevXqmhEbMqmpqZg6dSo+++wz3lZZb49ITk7GTz/9hH///ReTJk2CM7s4fvDRJ6jQ6FDh7MXuRet/aeGSmwRVlcFm+fZ48cUX8fvvv/ORJpQEAoHgXJNZQaMX7D/40M16gJOXNCUQCASCi5n169dzp8OUlBSE9olC1+lD4OLjDrXO9gi/5oA6zSoKSmCokF8EmV5d1HqFYeuNhpQnC87N6/IPE2yCOhxryqu1jgLKott8eVbNp3lZ5XoO7L9aYnfzbPPXmvXlZwjlQorvDLkcKpuodRwY5qza8+QseT1b69dCXkReR1GuvXrUTCuzrXbP5rYV2+AdwdbLKlYxf6WnL/Oxrvlg67Qd2tU0oUAWvaQdOgM/b1/cf//96NGjB9555x2sWbMGsyeG4XqWBBcOWu8ucA4cApWGRvRWw1CajtKUtTCW27Zxd/LuCqeA/tC4hsJB7crDURDVVZUoz9yBksSVcAmfBK17G/a7VaHaWIHy7L1s3na+3IVIY4/RxcLmPcm4Y1Eyiqc+Dcf9K9DdX4WBQ/oiul9/FKan4MiO7Zh0+3w4WlnY71v1Oxa++REKr10Ag7Pp2Yfe33iufgV3RiXgzqu7Q60+d+NIb3lhH9KyKxAzbRC7znpQA8bbMHIc5u0i/U95bJomUUXzaR77yr5TZjXl0X9G6VmOsvnyVA6txJDWl/NNy9A/8rboK5vHy6Ll2Sdth1eDfadlGHw+nzaty/P4P6bvNXnSJM2t+W4xj/1TswxfyjzNFpAX4f9I+bzeMjxbnicvIH+r+WJex2qajret68SpDftwdMUOlLP7j2uuuQazZs2Cl5cX5s+fjyNHjuDhGzpgdD/RGXWucY2YApewy9j13/xutzL/OPIPL5CmaqNjbbl7u6vh4GgOuWkoTUPuvpekqZZD6xkNj443QqU1vz85X3XTuLdl1zcXVOZZhnu70KisdsQzSQOQXtk4EcuwNqHoHRpQS1Q4sm1YjQtMXlk5dqVk8O8ylaz9XH7sNJLyi6Qc+wS7u2II2w6FPTqYYTkI+WyYE3AUozxqD2D+e1sm3lscxwfzvv7661Juy0Digbf2bcMfZ45LOWbcNFq4qNXILLN0EyHxwmuDRqNfQIiUY5vNqQl4asc/0EvXGxknRzU/d0WVln3VLhoN3hp8md3wSwQJW+7d8rddZxcSiTzdd6hdgYXMtvRkPLdrE6uD7T7Dmzr1wG1detW4fMg8u3MT1ibFSVOWdPcNwNtDx8G1nm3LlBj0eHDLGhzMyZRyLLksvB2e7z+Cf6dwRs+wY5lYXMinrfF20uHOrv0wKbKDVY1rczg3C/ez7RbbcUx5ZeBou0IbmfrqPjemF27u3FOaMkHCpHs3r+Hhs2wR4+PPf1d+urrbiFPsN/DotvVIK7XtEDMmrC2e6TfcroBqV2YqHtu2gYuflHhqdbg+uhsWHdnL2g+zSG9wcBheHTjGorxDuZl4aMtaFFkdw1HsuNFvb1XCKSnHRHf2m35ryFi4qc/fu5eLBQ1rF1xcXITwpTXSOyYabz56L8KCzLEF6SFk2/5YLFq6DLkFhahkf2ikVqTQN07sZE4dNRydO7TF219+j12HjkhrXVyQCCg00B8uzjp+Q0HHIT2r9oP6ys/eQ4c25pdVufkFeOq9T7B+2y4px4yftxf8fby4Yw4JZNKzsrm4qDXx8v134MoJY6QpQG8w2BW+NPQYXSjIwpfPP/+chyhatWoVAgPNNzMkAlq3bh0XwDQGb29v7v5iPWLDWvhivT2ZrKwsPu+3337D4MGDufvLuws+QEm1CqVOnmYrXDvQPtG+rVixAsHBtlWj1gjhi0AgEAgEAoHgfLBs2TL8/PPPSE9PR/uRPdBxfF+4BTSP8JFGepMYoZxGgheU8BHhZQXF/FNfVslHj/MOOcLuO+U6XjY34T30Wb+8ptXpDWJNMbXLs7uFOjctz5RfTyoWrnM9S8yLWq1EkzaKbjDSOlJ3ZcNo1HbMCytPEdfI2CjHulNTKXrx9vDCQw89hJ49e/KXY6+++irWrl17SQlfXEnc4UUOJ+bX3SSEKDq9BCQCqQudX1/oAgfBQWXuoDRWFqI0cQUMZZYdSc2JyskbHh2uh9Yziu2G6dm+2liGsrQtKE74nU8rcfLpzvfb0SWI1b12J0NZxlYYipPgGjEJKo008rO6CobSVH5c9EVnTHkXEI09RhcT5ZVGvPL5Hny7vQLzHr4THdnfe7XRiB1//oo9R5JZm5CGO596FFEDh0prsHYiNwuvzbkBp4c9hPLgLizH9PfhHL8TIauewK9vjEGwv33r/aZwywv7kZZdDhdfD1OG1KCZPtg/UvtmcW2Sl1H+w/835csfNXk104oWWlFeTdl8Uf6PNG36wv+1WIY+TdP0PpUSdTJbf8rv3OQ8ZaI8Zb5yeeW0vIz18nKyzlcur/xUzv/rr7/4NaLL5YP59mTObI7F4T/+Q1leMWbMmIHZs2fDx8cUnuCuu+7C0aNH8ciNHTCqrxC+nGuE8KXpqDRubHudoPFsD0cnH9bu+8BQkorCE19JS1yYGFn7+0FaD+wvadzfm4tGDVethq1tvr8hnhjZHx39TP2LJXo97lvxD/SyWJBBThj55RUNcsFgzQjctFqU6Q3n0DWjGs+F70KkU22hgix8Icd7CkHb0qyIP4nX9v5Xy+mG+ipZKwuD1YC6SHcvvD9sPPzrCQVEYV/mb1qNLBtheOhsWm6Nlcvu5xcMHc/DJNmjnF33X9i1Cf+kJEg5llCIomujuuKG6O52hQ8kvHhlz1Ycyc2sVQfCy0mHNwePtenq0VLCF/pd0nbf2r+9lmBDJtzNA0/3G4auPuY+aFu0lPCFRFYUlum74welHEtIDDUhoj3u7tafn0dbkHiGhFr/pSXZdHyhkFAkehkVGinl1CarjAQ4f/NQV0oolNaAwDBsTU+SckzMY/tyk9W+5FWW477Na3Ay37KftrO3H/9tH8nLNmVI3MrWvzmmZy0hlaB+Lgjhy1tvvYXFixdfcsKXKSOH4rl75nGHD5mComK8sehbLFv7D7dnsibIzxee7m5IzcxCUUnrj9HWnKxc9B46RJhfVmVk5+LRNz/AtgvUCacxwpeLjfocXwhqqwxWdmD1Qe4wOp35wUiGnGCmTJlSp+OLTEFBAbd//+KLL9CpUycugPnw44+RW1yOIhK/qCxFNUpk4cvy5cu5W01DEMIXgUAgEAgEAkFz88knn2DDhg3Izs5GzNRBaDeiG5y9bVv/NgUKf5ATl4a8M+nIjc9ASVaBKSyC3ggjiVz0hppPPppcgjqqKMnI08o8GWW+8lOZL6PMU86T8+l1ifUyyu/yJyVby8rI+co8wla+rTwZW/Pk77bybeXJyN+Vn3JSYp1v/UnYm0efdc1TfhL0vTHL2VvGulNTKXrxcHXHY489xp1e6MUY8corr/ABFZeS8MUlbBwP7yM7nhBV+kIUnvwOlXl1D6by6DgHOv9+7Jv5nFTkHUbh8S9RbbQ9orY50Hi0h2fHm3gnn5LKvFjkH/lYmjJBAhDPqBvYOiQAsd2xQcIXtgNwDiIhhHnfqo2lKDq1BOXZe6Sc1gWdQ41nFKr1xdAXW3bsNOYYXYycSszHZbf9gpf/XI7YzZuwe9N/yOx5NbJ0wVAXZaPdrk/x9E+/wsnNJDpZ9tYrWLHtJPIvf9liQJPP97fjg2vcMXpABFQq82/jXPDIgiM4dKoQ3bp1Q0QElV+3gMP609535acsKLEWkig/7X2va3kZyrP+tJXX1E/5O1HXcvKn/J1QTtMnXR+of8Ja+JK44xgO/boZpTmF3N35pptugp+fucOdwuIdO3ZMCF+aCSF8aTpOPt3g2uZyOLLrHL+ms7arvmN3ofBrTnssz2srTZ0dt/btiiu6sHsABgk2Hly9CcezGjeQtjnx1ZThlfBtcFLV7veThS8DBgzgYu2W5kR+Lu6rw0XFmnER7fB032HcRbouyg0GPLJ1HXZn2Q8ppKSh5W5JS8LzuzZxwZMtfHTO6O4biHHhbdGVfXppnbh4J6e8FP+mJmJDcjyO5+fYFTlNatMBD/UaDJ10rVXSUsIXgoQqHx7chT/jT0g5ltA1cUBACJ7oO7RO15SWEr4Qx/Ny8Nj29cgoLZFyLCGXIRIcjWX73scvCL6SCCqnrBR7stPxd+JpxLJtlhtt9x1SqKxXBo7i7i32IGf0F3dvxprE2ueRQhIVKpyI7LkbkejmJVYG1UcJ1Z9QHtuGOiQJbCOEL62Yy8eMwLN33wZXZ3NcuOKSUrz62df45a8NUk799OwcjeljR8BJa248SQTy3jeLMXJAH0wYOgghgX41DysVFZU4FhePZes24VSCpVLNGgolRKGY2keEw1lLN1Usk/2SyiorcToxCSv/+Q+HjltaNFnj4+mBmeNGs7LawdPNHWq1+eJgMBiRlZePtVu2Y81/O3jerVdOQ4c24fw7QQ4tv7O67j96nJUzCv26xfB82jcqW4YcXHYciOXiIYL27Ytf/rR5fOR5tmhsfQlyX7lsyEB0bh8JXy9P6ORjxaCRizn5hdi2/yD+XL8Z5Yq/t3bhoZg1aSzbjhu6RLVDdFvzxYOET4eOn0RcUiqfLiguxk+r1rHplDqPkTXkFnTZ4P4Y1KsbAn19eBgluW60PwXFRWw7cfhtzQbuHGOL++Zci0A/8wsUeXvFpaWYwY5tp3aRcHIyNeB6VmZCShp+ZeXV99uQaYjw5VzSGOELUVZWhl27dmHhwoUICAjAuHHjeDuXmJGDIicPVDnavnGRQx0J4YtAIBAIBAKBoLXw/PPPY+/evSgqKkLP60Yjon80nNzrHpnXEIoz8pCXkIm8+AzkxqejorAElaUVqCwp56OY2rdvDw8PD54oFKm7u3vNNCUKS6tE2aGl5Fzk21uWOBfLyzSmrKZswzq/rjKIxm7jXC1/LvKt86w7NZWiF1edC5588knu9KIMlXspCl8cdf7w6nIX/6yh2ojSlHUoTrD9ToQgAYlXzB1Qu4RKOWy1Kj1KklajNPlvKef84KB2hlfnO6DxaEdTPK+aPWeXpf+L4jO/8mkZXeBguEfO5OvI8DBGWTtY2sNDQ1RV5sNB4wa3iCkWHanGsgwUnPgahuJEKaflUTsHQuvTlZ8HOicqrTvKM7bz86ekMcfoYsRorMa3fx7Gkq1lyIoeh2yPaBjCusCocYHKUA7PXx7BdVeNxZib5iE/NREv3TIXqeOfRrmfOXw6MXH5DHz6FL0/tD/Aqak888kx7DqSz99BjR49mudRu6Zs25TTLflpnXchIvdPKIUvKftO4cCSf9j1ogBjxozh7x/pHZ8SWfjy6JwojOzjK+UKzhVC+NJ0bB2Hi0X4sq/EH++n9ZCmzo4B4cHc9UV29fjp0Al8u+9ILdeSloJCHFGoI1v8tTUT7y+Jw8CBA/k9a0tTbKjEQ/+tw8Hshrn8PdJ7MKa3jZam7ENn4quj+/H5kX2mjDogdxkqd1okuRfWDYkuFh7cjT/jj9s931qVI3ekIQGExlHFl6PwNeQYkldRbne9dh7eXGzS3tN233VLCl+IM4X5eHrHP4izEy6IHE+msnNzd7d+dh1vWlL4UlllxNKTh/lvwjoElgwJn+jckfOOHM6Mzh0Js8itxV5IfxL7kONN34Bgdodc930NiYfe2Lu11u+A1lLm1OVuZKsMeasNLUNQPxeE8OXNN9/EkiVLLjnhy2VDBuDF+26Ht4dZvEEiiV2xR/H+14ux5/AxKbduJo8ciif+dxMPeyND4ojV/2zF9HEjERYYAJ2TtuaBhbZRWFKKk/GJ+OrX5TZDAxG3XDmNlx0RHAhXF2c4KhpFEmWUlJbhTHIqFq9Yg2VrN0pzLJk8aiiuHDcaUZER8HR3hUattnhwop8liSh+WrUWL39isub79IXH0b8HWY2aKC0rxyuffI2V/2zBs/Nvw/TLRvJ8EnAo60TxbCsqK1kDYvqp7zxwGLc/86rN4yPPs6Yp9R3UsyvuuO5KtA0LhbubCw9DpKwXrVOpNyAnPx872HY/+G4pUjKy+Lx+3bvgpfv+hwBfb6hZg03rKqH9kZ1/MnPyeCinXQcP13mMlJBw6cbpk9Grc0f4epsEOcrRGlQ3cpYpKCrBkdNxWLpyHfs97JTmmvn1w9e5SEeGtvfVbyswrE9PdGofCQ9Xl5pyqVGn+cfPJODTJb9h0869PL8uWrvwhdDr9Th06BAWLFjAR89MnjwZy5ev4OKkEp0XqjSWL+oJF7ZPKrZvf/zxB8LCGvZiVQhfBAKBQCAQCATNxcMPP8zvaSvZc8bA2ycjqFtbaJxr38c2hryEDKTsPYn0Q/HQk9CltJwLXrw8PXmo0O7du/MR7m5ublyEQC8pKMnf5U/lc4pAUB/KTs3IIV1x6Jd/kXYwDs5aHZ5++ulaohfi5Zdfxvr16y8p4QuNCPfseAuc/Ogls/ndhr7gJPJi35OmaqPz72vqYFObX8ZSiKSCE1/CUBQv5Zw/NJ7RcA0dC0fnAFBYosqC4yhNXgNjRa60hAm3tlfCJYQ6A8ztSWX+URSe+h5VFflsf1xZTjU7LGq4BI+E1qcbHzlfVVmAsoz/UJG9lwt8WgvUSewcOJgLWyhsUzWJlpLXoiRxhbSEmYYeo4uV/KIKzH54JU70mY+iHjMsnFx0WccQseENPLzwAyx99UXsdOyEogE3Wiyj1hfjF5eXMahn84y8ffbTY9h5OB8PPvggf58kaF6U1wgSvqTHxmPfj+tRnJGPYcOG4X//+5/NkOR33HEHjh8/LoQvzYQQvjSdi1n4UmTU4qnEgShgn2dLgKsz3p40Er4upuN0Kicfj63ZgtLKxl3bSXDRwdcLFTTAN9/2QOHGonGowoMh+9HJ2fZ1efXWTCxYEodBgwbxe9aWpordL5GQZPHJWCnHPu4aLd4ZNg5dvGuHAbLFjowUPL5tg12HDhkSObw3dDw6elk62tkjubgQ7xzYju3pKVLO2UPCiQd6DcSw4Age9sYWLS18IaeRtYmn8WYdIY882bGc37UfJkV2sCn/aEnhC5FbUY7PYvdgRcJJuwKkxkKhkebF9Ma0ttFc/FMfDXU5qsuF6Eie6TgWVdo+jjINdTIS2EYWvoij1wrZdehIjQBChl729egUhafuvBUP33YDdxCpDxJMOOuc4KLT1aSQAH/MvnwiDwVE85TiDdqGl7sbesVE47arLkdMBxoRYsnt18zEnBlT2Ly28HBztRByEDRN+V07tufuI2MGkf2tJVdNGIv5s2dhQI8u8Pfx4qIO69ECNE2iHKUohQQtyn2h+tM+ElSGnG9dJ7IhVR4H7mzCsHV85HlKmlpffx8fdIlqz8Urzk5OtepF65DbDJ2TcUMH4KaZU6Q5puNI61CdrEUvhPJYKMuu6xjJ0O/owVtm47Ih/REeHMiXs36ZTHWj7dL+Du7VHfOvv8rmuSTXGOX2SAhFobr6dO3Ef0vKcunG0I3Np+1fMX40X/digBpTenn6xBNP8PBJP/30EyZMGI+h/ftAV5wNR32ZtKQS0+/Hju7QJta/OYFAIBAIBAKB4Fzw+uuvc6cXEr0Mf/BKhPTqcFail8L0XBxduQO7v/obcf8c5AIYLyc3DOk/CLfPm4eXXnoJd911Fxeck/ilXbt2PLwDdTRRWAEvLy+4urpypxchehGcDbLoReuowbPPPotevXrVEr1cspAAovB0LTGHo85PcgexjcatrUXnGolFDKWpMJacu46ExqBn+1B05hcUHP8CBSe+Qkny3zYFHQ6O1KaZ2xMSilC9SfTCpw0lLJWiqrIQpWn/oPDEN7zMotOLUZFzoFWJXgiV1pMnU6iqut8VNPQYXax4uTvhvhv7QLV/NTtSlu9gKvw6IjOwJxbcczcOHY5DabepFqIXB1TB+7/P0DsmUMppDhr/fkhwbsg+kYyDP23iopf+/fvzAXC2RC8EDRY1Ic7ThQS5ebm3vxoeHa6vSa4RU/k8J++u8Ii6Ad5d72XpPp68Yu6CW+R0qF1s/w5kqO11DhwCj463WK1/J1zDJ7FGuuHuUFQPt8gZ8Ox8O7y63F1TllyeW+RMdu2t3ansEjKG74/Ovz8XbSqha3nNPre/Dk4+3aU5ZlQaN7iEXgbPTnPZthT7wOpAx0Xn10da0hIqi8qsKZ8lqgsdE9ew8Ww//sfL8eh4M9Su5sGyTcHNsRJDPBoW9qY+csrKsTM5XZoCIrzcMTiCnB4aDr2bH9s+AvcN7oWHhvXBuKjIRq1vjyBNKcK0pkgFFwLk2NnDL8CuQ4iSEFd3nhpKG3dP+CqiYNgjxMUdQS5u0lT9hLq5439d+qBfYAjvozpbAl1ccXeP/hgQGGpX9NIaoLoNDYnAZWH2Q4YVVJTj2xMHcTjXtiilpfFx0uH66G6YENH+nJw7d40TbovphfGsvIaIXogQNzdEsN9mXVDdevsH2xWsBNPfAvvd1gX18fYPoN+UeAfSVOT7aXEEWyH5hUXYuG03StgFWQm5cpCLxlUTxuCVB+7EC/fejqF9Gmf35unuhiB/X+4YcjI+CfuOnuDbUz5gkVCCwutMGz1cyjExfuhAXDPpMh7aRm5kikpK8duajXjpoy/w+9pNfJqgP9J24SG4bsp4tj1z7FMST5DAIzKMNQKKhoUeIMi5hOoTe/I08goKG/XQp9cbeKggSuaHERM0XV5RWTO/wk48P1ucTX3pZogOE22PQij9tHodPln8G0+rN22tOVYEhbUaPbBfjVuL0WhEOTtHVN9Kq/rSdqhMeX9oOVq+IdC5mHf1DPTp0okLZmQMbH0SW+08eBjxyakWx4jcbaLbRuDmK6ZahFGyhZNGw5YJ4/U5evoMT1RHJfT7IvFLr5j6rehk5Bfe1uKPkpISPiqG3GAak2hEK7laWSOfQ2d2PshWnWK/21rfOpGLFTlU0eiPkydP4tSpU7j//vtxxbTJcCrOgYOVpZq8F435jQsEAoFAIBAIBOeazz//HJs2beL3pf1vm4CAzhFw1DRNGFCaW4hT6/dh56JVOLVuL/KTshAaEIybbroJTz31FG699VZMmjQJMTExXOhCYY0EguaCOjRJ9KKqduDumTRYQflMLwAq8w6hykoAQR1hWo8oacoS6tRSu7ehL1IOe6at0kNfdKblhCHVBh6KiMIQUaqqsG3lXptqVBttj7gk8YuhJNlUZmkaW67u0Z2tniYfo4uHoX1CMaFNMTx2fi/lmCCRS3GfWTje+RrkT3oSBldLJw9txnE47FmB5ghxJGP1mktwHjn0y2YUpOagR48eXJAbGmq/k15+fydO14WFo84XTr494eTXuyZpvWO44MM1cjqf1nh2ZCmKJ61XJ+6m5db+aptiEYLKdGt7BVzDJ7Cyu1ut3xnOwcNZsnQYsweJbNzazuTbdPLuwtaPrimrprzAQaw+1/CQfUpou7z+Hu3ZD9OyjXJ08jLvr18vqF0tHau0bFseHW6ES8hotp9deVnmbUbz9ciFxy3ycn7tV0JlUZly+ZQ0Xh3h2mYanENGsv2IMZXj2R4q7qbWdOjvbYh7KtxUZ3+PYayqxh9HTyFf6g+gkCizunZEOx+zK099hHm4YWbXKER6e6I9W29KdFuoz4FIv7NLHpwd7Tuc1LQ/reiC0dbDG15apRDaNtHefvCw4YZvD1+dCw8fVB9RXj5wszFY3B4UyqaDpw/u7T4AN3Tsxh0/mgL1iQ4NDgc5ctCns2PrF9S7abS4OioGUWz/7UGOOF8e3c9DO7VGSLh0S0wv3NW1L3faaQp07rr6BuCJvkMwMaIDPLQN/126qDXo7Vd3VAgqr5OXuR/cGvo7oL+HuvBmf1NdfBrmjiSoG8fnGNJ3CwwG9mDUwM70hnDgwAGe+vTpg759+0q5dfPff//h8OHDMGp0LNWv9LuYiE9Jg7enB9pHhFqMSKILHDmL+Hl7oW14CHp27oiIkCCkZ+cit8DSXq1Tu0iMHMBucBQNOf2BJ6dn4v1vluD7P1fzcEb/7tqH0KAAhAT41VxASZxAbiSb2Lzi0lLuzvHQrddzpxdZ9EIhjb745U9898cqHDh2EvtZ8vF0R8e2bbhQgRK5v5xOTMaJM6ZYyPfffB36dIm2cD/JzivAp0uX4dMly7Dmvx3YsG03/t6yHfnFJUjPzMbeI8f5ctPHjuQOJTIUiofC5VDonDPJaVjL1v1j/b8Y2Ksb365MXkER3v92CT7/+Q8+f+OOPcjNL7B5fOjY/L5ukzR1dvWNDAuBP7sR+uq35fj+j9XYvGc/9h4+zo/VntgjcHF25nVwdDSVTcc7MS2DzTuGopISLkJZsXEL/H280ZaVJUMhjlZs2IxXP/2a78/qf7dyYU2lXl/nMSImjRjMhVMktJEhgRWFaHr/m8VYt20n1m/dhbjEFH6u5eXoXPp6eaJQqpfM7GkT2Dk3h+Si309BUTEW/vALvmb7vW7rTi6oISGVUmhDYpp4ds721hO2iwQj2vJCTJ06FcuXL8d1113HrdBlcnNz8cYbb+Duu+/G8OHD0a9fv3pTZGQktzWdOXMmH0mqpKioCIsXL+ahhEaOHGlz/brSZZddhmnTpvE2rm3btvDx8cEfv/0KvY4dI8VvSFNWwPftmmuuafAL/3///ZfHE6YXtpQEAoFAIBAIBIKzYdmyZfj555+5mLzz5AFoP7IHVOrGd+7RoICE/w7j8J/bkLr/NIrS89gzgjcmTpzI76t79+7NO5Pc3d25i4tA0JzI754qisrI3xuvvfYa79Ssyz2InrXOnDmD7lEePF0qkKCDRsObOsSkzhQHFcuvQEX2HtO0Aq1nFO+AM7mnmCDhTEnCn9wtRYaPhA8YyDsWXagDMGAQn3YOGACtVxfWzrhwIQbbkLSGCaqLa/h46Hx78Q5HSmq3NtAXnIBz0DA+ktyFfTqx+dX6Qhgrcvgocxp1Ly+v9e4sObfkW5RHo+VVWuW7C6qnBlr3dnw9jUcHvi8UDsi6Do46fy7usQUJhaiD0zlkFKvjUN55adrXgdD59+P1Ifj+StDx0fn2NHWOsnVcaL2aYzSQd9KqnQPZfhSjSm8eAU55LuwY0Cj8hu5PlaGkzmNkC+pEpXBPziy5BA1R1G0AP/Yat3C2fhkPA2UL6+2RmwFVkFx1XEJHw5X9LvixksrUenZkv4UqGMubb6SxRq1CkI8Ovy5eC2OXMahyMr9XqnJyRZVPOIyewaYDKaGqMsBj3Tt4YjJrFzo2XyfEpr05SM4sx8CBAxEdHS3lCpoL+RpRpTdyR7pO0Z1w77338neFdUHvJOkd5NCePogMaVqnm8A+1A5Q2+OgEFZSGL3yrB3SVG3ITYTaF6XbCbWZZen/SlNsGbcw1g714E5ltBxPDo48X+3sz75bdVqzNoDaaEetFxydfGEsSWZlmvtbaB4JQijsn0rjwcuygNZn10hHJ0+o6Fqp2B/ruhF0ndS4R7LFNNKy5jaIw+ujYfXx4C4udC2hax9B1xu1S6BUB+v1VOx/0/5SGfqieH4tJahddmP7oPFoy8PlmbarhAbyOrL9c+XXHZqvLzwlzWPnyqsTSx1Ztta8jWo93w86JnJ5/F4i52BNfZuKs8qIhAp3pOob7u5hj6IKPRc8xPj7sn10gLuTFh46J8RmsN+aoe7QOuGe7rhncE8ueKF1KeQKOchsTz47RxpnlR7X+Z2At9py4LCSk0klPCReeHg4Ro8eLeW2LE4qR+zMTEVaqX2nGupPuyaqS52CC2vIoSSnooyHPLIHlXs1K5eELI2BzhuFSCJhTS+/IKjZPmSWltQbVonQsmV7BwTjlk49MbVtR0R5+fK8+vgnJQFxhbYFx+QaQ64jDSmH0LNn7jWJp5FRViLlWNKePX+PCrV9LfPQ6vhvf3dWKi/HFlllpSjW69GH7adS0EX5f7PtVlbZ1gqMCWuLSI+6BWT11b2PfzB6+dsXlpBwicJmkSMQLefp5IRMVlYZ+7utb1g5ORNFs/N1Y3R3XNmhMxeWkJClMdD2KWzUptREGOwcv47evriiA2sf7ZxP6lOnUEn/pSfZrXNnbz/MaNfpnAjqLlXomV+rZdenajuWA+SGUGHl1HA2yDE0yTaQ3BEaAnVoL126FJUuXizVr/S72AgN9MfM8aO5UCHAx5s3ztbQ6SPnkNgTp/D5L3/ivz0HpDnA5WNG4Nm7b7MQOZDzyVe//slFIMWlphAsdLGYftkIPDp3DneEkSHByBPvLMSG7bsxqFc3vPHwPTxsj8zu2KO4+8W3uIhEZsKwQXju7rlctEMYjVVcGEMiDXIzeZOVQY4zMiSe+WzpMixZtZY7zyihMDvUqGTmmi4OX7/2LK+HTElZGZ7/4HP8sd4sVCFWLnqPh3KSycjOxSNvfoDt+w9JOSZsHZ9t+w7hpsee59/Ptr50DEgUkpGdU3OslVwzeRwPW0Xhfwg6l0tWrsFzHyzi0zIv338HrmS/ARkSsyxa+jsX81hT3zFa8NRDuGzogBrxEt2krf1vJ17++At+nGTcXV1x75xruMOPRjHik0QvNzz8rDRV+1hTeSQCevb9T7kAhqDf1AdsuwN6duXTBL0c/3HF33hx4RdSjm0c2I2Ha14SFi1axJ1VVq5ciaAg80UwLy+Px0COioriDVpDIAt3cmVZtWoVt1FX0pTy7EGCFooBPGvWLJT6hKOKHgQkXPKSoTLq8dtvv6FNm7pjIMqQJTx1TlDnASWBQCAQCAQCgaCpkMvLwoULkZ2djbA+HdHr+jHQeTS+I6eypBzHVu1E0q7jKMsrhrNOxwXpJAgnVxdfX8vR8wJBc0PvnX5cshiGSj3efvttLnqx9S5FCT1rbdiwAbMnhuF6li4lnIOGm0Z0K8IXGcoyUHhsEXc7UeLWZirvpDOPLK9GRfZ+FJz4kn01vQSmji+X4FGgcEkOGnfwzjwF5AxTrS9CRf5RlFLInXJzhxh1JNIoegeVWVhDdanM2c+FElzo4aBGtbEMRXFLUZ65C56d7+CCHJnqqgoUn/kV5Vm7Lctjdeadcwq4S41U7yp9AYpO/giVk2etOlQWnETB0Y+lKTM6v77QBQ6C2iWEVcuFrWPd+VjNt1GW/h+r0y9SHuARdSPv4CXRjKmz0+oFebURVYYytu9pKEvZgIrcgzybnHjco65j63k2eH8qC0/WeYyUmEQ8I3mnqKOTN9uE6bhZwOpGnZmG8mx27veiLG0TK8/SOafW9tg65Rn/sTL9oPHsYHIAUHS00vpGVl5pynp2TrdLueeeSr0RHy05iE+SOqFg7EOoqtXZa4n7sb/R4+BCfP3cCLi7nt37obp4ftFxbD+Ux12DadCXoHmR+yfI3S4iLJwf9y5dutR7naB3kqdPn8bjN0VheG9xb3OuITGJS9hl7DyY27XK/OPIP7xAmqqNLqA/3NtdzZopxfWLXbdy970kTdlehreT7HxTm0ltT7WhgoseVRq6Dzb/Dnj7nbYZxfG/SjkkNhkCV3YtVLHrm5lq1maXw1iazq4FTlygQqIQa6zrRnh1uYeLSEgUQ05jepaonaX1tZ7RppBLclvF8stYG1l06kc+ydtati7V2XQ9UNadOqhNndTUBpclr0NJ8l/crYZCE5E4Ui6Xh/4rPI3ynAMmpxjfnnwf5PLoGBXH/YyKvFg+betcUTtuut6b60DiysIT37JrqGmA8NlwoMQP76adm0GgIe6ueGb0QER4mfquqON8b2omvt5zGCmFtkUcJHa5qXcMeoWw34nUVhzOyMG7/+1BapHtjvyGMt4rEVf5noTawX73/cotGfjwpzMYOnQoXnjhBSm3ZaHaninMQ0Gl/f5j6idr5+HVKGcNIre8DAnFtsW1RFPLVUIihqyyEmSzbfHtFeUjqbiI58mQOCLSwxMRbp4IcHGFt5MzgtinrhEuL/Gs3LwK286Bbmot2nl6NzhUEtU5riAPxQbbjoXeTjpEutsXoJTo9VyEY5DuFW1B4hJy81HWqcSgx2m2XaOd9dqybZKgqC7qq3uwi1uDQ1dR/yMdUxK+5LPfX3xBPtJKi9j5M4sUNY4qXi86d0GubtydiM6dK9u/plLfcSBHl7aeXjwUmD1I+EK/CXt/7Z7sN03Hv2G/CIEtyESEzA5atXTIjibnkoGcMn5c/hcefn0Bflq1Dqls2vqY0I05uZv07RaD/107EzEd7MdiJrLz8rFs7T8WQgxyEFm3dRdyFAIWgpxlwiT3kG4dO8CD3RjIkHBBzxpLEuXcfs3MmtSnayeLhwVyM5EdSHp26ggvT8s4ZqcSk/HzX+triUiIrNz8GhFJS3C29aXwR+R24+nmhtlTJ+CpO2/F24/dh0UvPYmvX38Wc2ZMhjM7xjJ03MgJpbkgAU/b8NCaGzSitKwcW/bssxC9ENxx5sBhFJVa2psFB/ghuq19oQaF0Np18EiN6IWg7ymZlr9dUt5RWKSGIv+mrB9EadToM888g/Hjx2PUqFENSrQsrUPrWtOU8mwlGtW6ZcsWPnrWhO3LFf0dNRTrfRcIBAKBQCAQCJpCbGwsD3FEohcKbdTtymFNEr2UZOVj348bcWbzIZTmFGLQwIF44IEHcOONN6J79+5C9CJoEehZ7s033miw6IW4lN89VeYdruX8odJ6QuPeXpoyQ+4rSiEECSBIWME7ERlq90ge6kDr2x0qJx+pE8wSyqN5Or/eXERj0TnoQCPUtVxwIScSYzgFDGTreLP58vsSOqem80rlKZfn5cmdhMryrEQihMW68no26mBrPyjkhEv4RC7wIEGOdaejCeqMNJWlRO0WbuoYpY5Ya2EJwfJovzXu7eAcMsbU8cnzm7A/1vlW82QozyV8EhcYkQMQCXnYwtJcBSyP5mlcw7krDIXJsKbW9hy1oHAdWp8ups5iG9tWOwdz9wJyWGgutBpHXDsxGr5xG+CSVNvRyBqHzd/h3lmdm1X0Qsht1KX+Dvx8ExQQyAerdepk+R7bHuL8XESwNohElyQAJGFG0ekfUXj8C+gLT7OZ5vNMbZnWi7XxTqaOZGqrnPz78fbZTDX0xUls/c9N5bDyShJXcCFLQyA3mbKM/1Bw9FMUxf2CstQNLP2D0pR1rLwlXHRSA2t/NW4RvB5EScIfyD/8IV+WCx8VGEpS+DxKBUc+QnnWTp5PTmR0raZjwGHX78rcQ2zbP6E8cwdK2fZLk9eyepk7/x3ZNVvrYx7MaguqE9WhIucACo59jsKT37Ft7mLl1O4/aQrRznno65bJrqpn/3eYXlyKz3YdQnaJqW/MWa1G39BA3DWwJ0ZEhiHM0x1ezk7wc3FGO29PzOwShfuG9Eb3IP+aPpWsklL8dOgE0s5S9OKrLscw99Q6RS9KWlPfANVEdk6xl3r6BTZJnOKjc7ZZnpyaWq4SEnaQ0KKrjz8GB4VhWtto3NK5B+7rMaAm3dG1D65s3xkjQtuwbQYh0t2zUaIXgoQotvaBEoVraqjohaBlaR1bZVGqS/RCkONLN98Am+vKiVx0rOvkqtagex3r1Sd6Ieqre0NFLwT9Hfqy3wi5o/QPCMHkyA64Prqbxbmb360fZnXogtFhbXmIInLDORvRC1HfcaBt1CV6IehY0W/J1vqU6G+q9fyVX9hYPm20MsRNJZCTV4Ddh47g48W/4p6X38aCb5ciPiW1Voc5hevpHh2FsYP7Szm2ITEGhfOxhsQJufmWoZJItOIhhYKhMEhKoQJdaLtEtceN0ydZpCkjh8LN1fKlqRzixroMIjE1rZbgprVwtvUNDfDHI7fdiLcfvw/zrp6B6WNH4LIh/TGkTw8M7NEV7cJDz2uM8RBWH3fJXUamrLwcqRmKm2gFCWxfKQySEi1r4L08agtGZOh3Wcxu/qyh3zEJrJQ05mZNbgus2wRS8FFIIhoV05hE69g69k0tzzqNHTuWC8MoZJwJq7ZM2nfRxgkEAoFAIBAIzidpaWn48ssvkZKSAu/IQPS6bjTcAup+SWYLCg+w7ZMVSN13kru+XH311fjf//6HIUOGcIfG8/mcIxAood9f927deXjY1tRB0FoxVuZBX0Shkc3PpiqVE9TulgNeqKPMkUIeKCDBTGWuaQQ4F06Q04t7+5pOOepQ05ckgUIhlSSt4t9lkYyDozMfVU6diHVBQglHHVnZN+FcVlXxjjgaiV5dZW1jb3JjMc2jxL7bGcFpDTmikODDFAJC0dax9Sn8j77wDPTFiVLHp61nfrYvtGxFHndzKUn+m6eytH+lTk7TOhRqQuMewY8TQfVrjv0hXEJG8RBKJhcD+VhX832o2R8DdRJK+8P+tsgdRxc0hJ3DusPZ0344OpNzr4o7HlB5VUar0c+sPEeXEGi8mjfUT4CvM+67Mgrqrd+xvbR9fKhj1WvrIsyIqcKAHpLoqBlRiWbqvELiyHfeeYc7uJA4kt4DNoSa9/DifF3wUPtYnr2bu14Z2HXJUJrKRZzkpmJq58yQ6JKEfoTGs6MkRDT/CEggQs5XlQUneDlUXlnGdlb+Hrad+sOnlCStZukvHk7PWJbOriGFXCxC1xIqz2gtTFW71oghaT6JdXiYOKv2npzRaJ4pxcFYYRrwqvXsZL5GM6iNJ8ELtc20Dm2/PGcfKzNLWoLhoIJaOgb2INeYiux9KI7/nV3XDnFHsNLUfyzLOQt0KiMme5+Bj9q2c0ZjILeIQ+nZ+HbfEZTpTYIhJ/bc0jXQFzf2jsE9g3ri3sG9cA9L89n3mTEd0N7HkztIEBnFJfhw2wEcpAHqPKfpDPNIRZC2dj+KPcR9bfNAYWXIaYPEFxRKR05hbh7c5YXELuLIt05IUEMiqABnV4tzR04vJI4hYZv4u7k0adXCF4EJEgykZWXj0PFTWLxyDR549T0sXb0OpeWWF3snrZYLKuqC1rEWIMgYjJZx2qhRoDBIBDmRKBsJ+k5OM37eXhbJx8sTaquXnPJ61mUQFZWWiuTWxNnUV+fkhHtvugZXjB+Fnp07crcVd1cXLlCi41zIbpKSMzJRKd1gnQ9o29Zxzauqqmudd5mMnFyFcMOM9TFpCBSeqblEHjqdjju1NCbROvZoSnnWiey0GoIQvggEAoFAIBAIzicrVqzA4cOHudil+xXD4BHS+NH1GUcTsfurv5EXnwGtowZ33303rrzySoSFhcFJGvQgEFxIXNLPZdVVqCw8bSlEYM/8GrfwmlHuhNajg81R7iScIZz8ekHrRR1qcicym18Uj6KT36EsfQsXddAoeLnzjeBuLr7dpSnbmNxWHKAvOMFHkNNIciqvqsKyM9AWFF6BRtHTiPfK/KNSrgkShVDHpDwivvD4VzzMREOg0Bkm0Yv53QiN2qf9Kzj2GR/1X3Tqe00ykr4AAP/0SURBVLbtT/hIfGNZhrSUCR7WJ3U935fi+GUoS93IExfAJK3inZ4y1EGpdovk36l+VM9zvT/Uierk15udD8V7DPpd5B9n5XxZsz/kaKAvjKeZpmXYeXHUesM5YIBFR2pt2HGiUBtpm1B44hteXjF3MjCHuSJUjjqoXUOlqeaB3mdNHBaJQe4pcI9dSQdOmmNGm5cAh21LcePkKDhpm1/E2ZR3bIKmQ+JIEkb2798fGqvBjg1BnK8LHy7uyNjBmiXFdY+1eRU5By3aX4LaNpUThf1hbaVbGHexUmIsyzKFo2Pry1QbSqBn7ScJSeqDrg8kgnTy7grXiMlw7zAbnp1uh1eX+fCKuZO1iVbhFx1UrA71uyvYQu0WwfaFhKRmyLlN494WLmHja5Jz0LBabbpK686uFfbbZxLQVLBrkEmEY2CHo5Id53z2ee76PSK0xRjqkaa89DYZfVUVtiam4pOdB3l4I7oSkPgh2N0Vnf190Ts4ED2D/dHRzxs+LqbjTf1pR7Ny8SlbZ39aJioMtvtTGkp7XSFGeKRA7WC7n06J6D0QCASChiHfpwnHlwsMcmw5fDIOny7+DVv2HOAqVRk6pSSwqCvckU5n+0UkCTW8rZw8DOwCnpVnO9QQKd2pHv/tPVBvOnSCrAJt46QI9XMh0ND6zrxsJEb178vdUeiPjY7XkVNxeGHh57jlsRdw+zOv4rMly1BU3HBV79liNBrZjZLl3xTVTRn6SEl4UCAXUymh9akcwVnShLZNPFwLBAKBQCAQCM6GvXv3YvXq1dyZsOOEvvCLsnqZ3gBOrd+H/T9sQH5SFhe6PPHEExg3bpwIayS4oLnU3z1V5h6oJSShzjGNRwdpCrxjzCRCMUFCGWWYIxK90Eh0GepMq8jZBwq3UGUo4Z2J1BFIo+HNOHABSV2dafQWgkQvFIaBRpDTSHIKxUAOJPXBt1l0ho94t+7MpHKps7FmRHxxQoM6KTWeUSYhiiJcDx0LCk1BghwS+5hG/afwbVNdKdyDkuKE36V9iIexLJPXjafKfFNdDZbviWQBEh/Bz+p5LveH0NC501HHrvmdA4lzihP+4OdY3h9yNChN22i5bQeTU4vao62UYRsS4ZDYR3ZXoHAY+iLLsCK8rGYMdSTj5qrF3MujYNz4FdTllo7ODuz37Lz1Ozx8ZTtER3pLuc2N6RiId+Dnl7oGxAkubqoMxTBW1HY/J8FKVaVV28raepXa5J5OYQCtw8xROdVWbTbBRTXV9b8/d/LtDc9Oc+HWdiacg4Zz5y0KC0fOLBqP9mzbjQ9Fag8KsSfviwx37goYaApdp0iOzv7SEibIuctCHGlFVUUuF9E2J44O1RjukYIeLrad6xtLqd6ALfGpWLh9P7Ynptb0sTmqHLi7Cwlh5D6TMrbs0tgT+HjHAexNzeTCmbPBS12Bmb6n+WdjEH0DAoFA0DCE40srpEObMAzsWbdzCznAxCenma0WJSg8kauz/Zt3b3d3Xr41fbt2hp+PpcU1hcFJyzSNwMgvLKrlDHImOQUvf/xVvenHFX/x5SlEkLWDSPvwUB4SqDVyNvUd1Ks73N3MN6eZuflY8N1P+HP9ZuyOPYp9R47zMEJaTePiAso05UbnWFw8d5pR4krxKtk+2aJjZAR3qVFC61M5grNEOn/ixYZAIBAIBAKB4HxAYpfffvsN+fn5CO0dhfC+0VBpGjeS/eDPm3Bs9S4UpuXw8ABPPvkk+vXr12C3Q4FA0DqhkdqGIvacr3g+JfcNreQ0QuIURxcKVWN+D1FdUYDKnIP8O3clodALivcUNMpbpfOxHEUeMhoOVp141Knn6BwgTdWGC2hyD5rCMFRVsgwDKASExUj98wgJgKw7/4yl6SjL2MoFPtbwsBWsvkpo+WpDOe/wdG0zDe5RN8Cr8//4CH+PjnO4i4oS6nBsTshlRWXhYkBuPvFcrCILmzjse2XeYRtOLS41oUBsQSEwSIijPA7cDaA8l82zfKepFFc1J31iAnHTYFe47/5RyjHhcmYr2uTswBXjOkLTyGtkUxHdmBcGNe/vxHu85oGOq9Whtb5e1IILEBv/F0TXFYu2zQIb+ZLQ0cGB3uFbbu9sHE2c/PrANXwStN5deShBckEjRxkHqNjhYG1kRb4NkWPT4aIdhWiT4I42Wo9aybaLl/1jXW2sPC/XZR91BS73OY1gTe3rbVMoMxgQm5GDL/ccxoJt+7AxLglHMnNwKicfx7PzsCclA0sPHseLG7djxbE4xOWyex+jvd9Ow1A7VOMyjyR01OU1+NcrNztC+CIQCAQNQwhfWiHtw8PxwM3X4bF5c9CpnelFgzU+nh5oHxFaE4pIprS0vE5hAoUjGj3QMoYyub1MGzMMnm6WD+85BQXYe+QY/346KQXl5WYVKoXMiYqM4MKJ04nJNlNKRhZ3qEnLNClxj7J6FZdajjiJDAvB1ZMu43WwhvaxJUUxZ1NfN3ZclDcjJCIisUtxqVkF3q9bZ7jUIVKyB4WSCvSztCZsCEUlpfy8KMUWzmw/hvTuXmt/aHpo3x4WIipa7/iZBF5Oa6GUHc8HH3wQt99+e4ukhx9+mNehqVgL1wQCgUAgEAgEguZg3bp12LdvH5w8XRA9oS+0ro17Djmz+RBLsSjLK8Lo0aNx7733Ijo6uklhAgQCQeujsvAELBxCHByhdgvnnV/k/EIj3WuopjBGZ2o65Ej0onR7IRwcnfnIdetR5Bq3NtISEmw7Do722xES5VTmHpamWh6Vkzc7Jpb1NZZnNapz0jl4BDw73Qa3yGlwDhwKnW9vaL1jTCP83dvxjs/ziUpD59b8/orEKNwByEbHMHVsWgt5oKLQG3XVudrU0WyFsTKXnWDr8Nrnp1NP56TGjVM7wSN2OZzSTe89HVg9NVu/x53T28PL4/ydA/ndoRgY1bqRz4/od24eqihsXrVle6DSuEBdh6jO0clPEqOYseW+Yo1tUYcp3/paRu0ghbKzh10hAs+3/2MhJy+XoGHs+hnItmvah2pDGcoy/kP+4fdZ+ggFxxdxB6/mhJzCKvOP1Z8KTrLm+tyJcJoKHVEKeXSl32noVNbXj6ZhqKri4Y7+PZOC7/YfxUc7DuDD7fvxEUuLdh3Cn8dO42B6NvLLKiwiLzQFcq0Z55mIoR6p0DQgxJGM3P5Qf5xAIBAI6qdVt5aX6k2/zkmL9hFhuGL8aLz8wJ1489F7cM+NV+P2a2bwRN9fe2g++nWLsbjBouN1JO5MncIEZ50Trp40FvfOuQbD+/XC6IF98chtN7DvvaFWm28Wyd1l18GjKCgq5tP/7NyDhLR0/l2mbVgI7mV1mTySPagrhBMUaum2WdPx5iN3Y/zQgVIusG3vQZyIT7Q4ryS8oP187u65mDp6GIb07sHr9b9rZuL1h+/GjHEjpSXPP2dTX+sbX18vT8wcN4ofJxLI3HzFVIwc0BeOjvWPIMln50DptkNl9+/eBVdNGMO3ffXky9AurGFxkLeyfVL+PlQqB/47ev6eeTX7M2HYIDw7/zb+XXlDlVdYhA3bd0tT5xf5eFof16KiImzZsgW9evXCiBEjzmuimMCbN2/mdbCHub6W9ZanG9PGWe+7QCAQCAQCgUDQEFJSUrBkyRKUlZWh7ZCu8G4TKM1pGNknU3Bk+XZUlpRzp5dbbrkFkZG2B2gIBIILE+7kUWHl5KHz4yFs1O6RUKkUg2KMZVwoI+PgyObVGkWuhkpjYxQ5LdsIqqsMMFKHaCvhbEf8cwFQ6FgeGspR58/dYxwctdzogFxQ6BxQ5+f5pLajTDXIpcUe1VW2QjM0/n2F6bi13Hvf8CB3zJscDqft30NdnAnPfUsxOigXYwdZibOaGQdV498PCc4/YuBa82Isy6rlGKLSuMPJp5s0ZQmFRaPQcyS8M1PNw8fVB7W73KXMCpPI00OaMkGiPQrjw78bSmu1jSSGtAU5uNQlCCSXLO6kJl872d9/RV4sSpP+4iITfeEpHjqPVdY0v7HYeIdcrS/h1xklVWz/KKxdcdzPdaaSxJXs2J6bEENnC4lHurnk4Fq/E3B3bLrjjjXlBgPSi0pwJq+AO76cyi1AYkER8s6B4IWgU9LPLQNjPJPgobY8Dw1F9A0IBAJBw2jVwpdLGbqQebi5okuHthg3ZCCunTIeN06fzBN9H9y7O5+vJDsvH6v/3SpN2YbKDQ0MwLWTx+Hx22/CI3NvxLQxw+Hl7iYtYSIxNR0/LDeFKCJy8wuxYuNmlCgcULQaDRdN3H/Ttfji5afw7RvP8fTKA3fiphmTMbRvTwT4mp1JSMDx65qNyC0wK6WpPhRiafywgbj3xmvw5B0383rdMH0SBvfqjmB/ijPcMpxNfcnlRvnQ6ubigptmTuHH6aPnHsUtV0yFPyunIQ+2CSlpKK+wvCEK9vfFnbOv5Nu+euI4+Hpbhqmyx7qtO3nSK0I4ubPfEQmU5P154JbZXPziqfhN0PIbt+/Glt37pZzzi3ycrI+XVqvl4qENGzZgxYoV5zXRNkkYRHWwh7m+lvVuyHkXCAQCgUAgEAjOBStXruTiF992wegwphdU6oaHb6goKsW+HzagNKcQwcHB3OklJCREmnvhk5GRgRdeeAE33XST3fTUU0/hww8/xKpVqxAfHw+jVQhgwYWPeD4DqvQl0Bcn0sGQcsDaCjdoPaKgcQunlyFSLjmcZHOhTF1UG0psjxqvlY6b3EXswupjNyRF66Ch4XlIQKQLGgJH6iiVxCbknlKasg75sR8g/8hCFB77AoayDD7v/GHj968439Y4OFq+P+SrX4B/Q46ODrjisihM8kuE6tsHEXr4Z8y/KgZuLufXyUx0Y15YiI7n5kFfksSuLZaiFWpbdf79oAscJOWYINGKa/gEKcSa+XyQSIXCqtUHiTK1VoIacnuhbVH4PSXV+mLoC+P4d7r2sYsb/y6jdg6Fk29PacoEiXKcfLqzMu0LXxzUzhbXjmpUwViRy5OMxqM9K5/CDDYeEg2Rq4wScmqj/VFCQh+1WwS77qTbTVVV5dzZzFo005JoHYzo75aJK31OQd0I55SGQJczErqcy3tDchQb4p6Gy73j4KOpaHS7fwFeYgUCgaBFadXCF/HygV0Y2Q01OcCQSwiFKaJE3zUKdxYiJ78AX/6yHNv3xUo5tiEHl7LyCnizMtqFh3LXFndXF4sb94zsHHz3xyqcSUqRckz8se5f/PzXegvxi5NWi/DgQPTt1hkDenTlqXP7SPj7eNeqI7Fh2y58uuQ3vg0lLjodL4ecbqhetJ/qRryQbS6aWt/123dxIZIMOasE+vrw49QrJpofn8S0dFRU1q9M3sDKOpWQZPH3QGKPkAB/aduebLphf8ok4vnoh1/w7659FuIXcgKS96dNSJBFCKZKvYE7vXz8468oLD43MTQbi/z7tH7AdHd3x9NPP43p06djypQp5zXNmDGDb5vqYA9zfa1uaaVJ0cYJBAKBQCAQCJoTCm/0999/85HKHUb3grOXVYdlPRz6ZTMKkrPg4eHB730vNqeX8vJyHD58GDt27LCbVq9ejcWLF+O9997joU4//vhjJCcnSyUILgbEc5kJfcFJ7uYi46ByhJZGwCtHtFdX8Y5FEsrIGEqSeIejEnLzKM/cbnPkuEVK+MMkuLlAqNYXsd+LpfiNOiapo7M+tO7teGgO+YUAudmUZ+1EaeoG6AtphP9pGErTLDpDG4XV+5KGQqEuWG1MEwxygFHrbIcdp45UR52lw0F1tb6WW9C5Ii65AAVF5t8W/akmpxchI6cU+Sz/VGK+RcrJL+PrnE7KZ5/5SMk0d/IWl+r5PIOxGgmphSgsroC3hw73zYrGZ7f4463bOyO6rWnfUtl6aVmm3zitp9wGlStTVFKJ42dykZ1XxutGlJTpa7ZP26Pt1I1pRdEOtW7E+WleyO2lMv8Ev3aYcWDtjR9cwyfCK+ZOeETNgWenuezzBjj59rJyVKnm7WdFTv0DNsllyzloCFwjpkDr3YWLVNwip/OQc7IokaC23hTix+ScXpl/VGovzZB7DNXPJewy7uTl5NcHbu2uhMad3S83ok12cFDx661aCgdIohfXsPG1xCu24E40Vs5jjk4+cAkZzetEwiH6pP3gIh6FmFTl6MyWG8Xrr7yO0XddQH+4s2PtGjpOym1dOKsM6O+egev9jsNXbekW1JogYc4wj1RM8Y5HkLaU/aqb3pZY94sIBAKBwBL5fk04vrRCjp4+gx37D3ORSl031jSPltm0cy+efu8TLFv3D3sgqzuWJYWrWbxyTU0IIyUUTufQidN4/bNvsWrTVhitbBxJXPPVb8vxwfc/sYe9ZIvwO9ZUVFTi8Mk4HDh+UsoxQcKJP9b/i+c+WMTD7pSW234ApH0jgU1mbsta2ja1vtsPxOLLX5cjPSun1jkkwcn2/Yfw57p/2TGuf7Rgdl4BPlu6jD1MJ9i01qtm/zVm1GFSegbe+uJ7fPHzn0hISbdr10fnl87zu1//iHe+/IGv11LIx9D6WFJ4rlGjRmHq1KktkmjbyhBh1pjra1lvB/lFl51jLxAIBAKBQCAQnAv++OMP5OXlIbxfNIJ7tJNyG8aJNXuQvOcEf8l62223oVOnTtKcS4tS9oydm5uLpKQkxMbG8rBRCxcu5C46AsHFRGXeEdOI9hoc4OgSbDFqnTonKQSDEupMU45SJxzULlC7hNocPS4nPoq8LIOXeaGgL0mpVV9H5wDu5EKOAdY4qN1qOhNphL9FWI5qIwzlWdz1RUbr3RUqre3QGXVBYhWVtmFOwNboS5JrdTaTAwB1vFqj8+kJlZPZ2ZmoZvUn0VRz8MUvB7Hg+72QX51U6o14asEWbNqVhPXbEnH3S+twz0vra9Lv607h4Tf+wb2vbMB9r27knx/9uB+l5QbsO5rB5xWVVOBpKmO3qQ2PDPHA2IER6NU5AGpHFSoqDXj4rU144t3N7LsRB49n4YHXNvLyH3pjIx5/ZzN/j7ZxRyLL/wfPLdyK+S+vxw/Lj8BgqMKhE1k127+fJfqk+tpDdGReGMjv78Tpaj7KMraxtuQEHWwph+Gg4m2o1qsznPx6cqcWap94e6qAXMZIbFmltx+O3gy7trEynYOGwa3tTC560fn35yIWJVXseliWvlmaAr/OVbL6VStdX1j91C4hcAkezcq6Cm5tpvK6mkQ59t/5koDG8lpC7W44PDpcB6+u98K9/TU8lBMJYupDX8zacCsnFxL36PwH8Dq5hI3jx4woTdvE3VtqYD9otS6A198j+ha+bUr03TV8MnR+vXnYptYKiV8GuGVgTsBRhGjr7hNrCZxURszwicNU7zMI1JDo5ewQ1wuBQCBoGA7sxs3mVZhGPlVU1KdKbzjffPMNT/PmzcPtt98u5dbNSy+9hGXLlqHSxYulxj/4XahQCKGwoAB4e7ijTWgw2oQEo114CFxdTDd1FPbmTHIqTicm8zA4JGZJTs9kD4CW6t7Lx4zAs3ffBldn880gCRluefwFdIgIx6Be3RDdlt0sspuoxLQMHDp+Ekfj4nmZ5ApjDwqBEx4UiLDgAHRp3w7t24RxV5qqqmoujkhKZWWdOMUeJkuQnJGF4pLaNx60jxHBgdx5pneXTuga1Y7vn1wGhVo6dPwU0rKykcLKIDq3b8u2bb4JNRqr+HFQOqsQPTpFcQcTGXIsOZWQjMJiy5tAcmkhxxulW0pBUQkXHlnTlPrSshHBQWz5aPSOiebLp7J5e2KP4dDJ01x8FMnOr3L7mTl5iLNy2iFof6iuPaI7ok/XTvDx8uBil5Nsv/ay8nYcPMyPd0OPEUH7T6GZ6LcWw9aTzyP9vk6zcg+fjkNyWibfP1tCKcL6WNvbHv1eQgL9LG7Q7O2rEgejAa55SVi0aBHmzp3LbdqDgppm83g+SU1N5cIYud6lPuGoUpkFMi4FqVDpK/Dtt9+iS5cuUm7dvPrqq/jll18wZ84cngQCgUAgEAgEgrogkcZjjz2GSmMlhj9wFXw7NDxEUer+09j73TqU5Rfj2muvxXXXXQdXV8sOgYuBhIQEPPLIIzh48KCUAwwfPhxhYWHcJYecXSi8kbXDi5ubG2699VbcfPPNcHJSjjgWXIg888wz2LJlC2ZPDMP1LF3KUGebc+AQ9jAuvaegkeH8Od70LK8vikfBkY9QZbB0gzWNeB/PVpPdSqphrMxHecZ2VOTsg6HE9OxPQhCtZ3upY1CHwhNf83yCjy5vdzXPl6ER/Ln7XpKmauPV5R5WVrQ0xbZqLEdR3FKUZ+6Ucky4d5jN9muwNMWWqzagNHktShJXSDkmbNWBwjHlH17Av6vUrvDoNJftQwc2Jb/fqOadrSQcqsg/xl1heGeoazgXjxjYMStJWsXdBWhUvYOD9G6g2siOzQE2byXbz3Q4+XaHS+g4aGjEv6Kz09YxcIucAeeQUawsszuBsSIbpUl/8+NOo/1JjEJhk+o7RuSo4NlpHqtvKJ8myOmA6s3PHds+1Ufj3g46vz5wdCY3GNO+03LlGf+x8n5mE6bBc7W218RjTXy//AheW7QT/3xzNfy8nXEiPg9T7vgNv384Hf/uSsbS1cfw5P8G1hgYOKodcPuza3DPDb3Rq3Mg8grKuTDlvcdHgZxj7n9tI7b+eB0mzPsF82f3xs0zuppWVEBCl8vvWgZ3Nye8+sBwDOgehMUrjuH97/bgo2fGwoPlh/i74pYn/8asidFcMFNQXIl3v96N66d1hq+XM6vDWix6cRx0Tmps25+Kf3YmYcXHM01/Sla8+d1pbNiVhfnz52PmzJlSrqC1MXv2bKSlpeGZudEY1O3S6aM435BAw6PdLPbZcMcUan8pZFx5xrZa1yZb7Qw5pLAM9r/9+7eqinyUpKwxCV8UDimOOl9W3jX8Gma/fuQ+kw5HrQe75pnvnZVtOdXHo8O1rN3vY7ccclKjfaM2WqaKte+FJ75FZcFxKYfB2mf3dldBx65xNdcXBRZtMFuWQjq5hk/i+8IyTAvVgXW7XOtaxrBe5nxjqFbhdLkHNhSEYV+JPyqrWzaKALm6tHEqwgiPFPRzy4SbY/2O/3Xxx6Z0fPJrPMaNG8ef7QQCgUBgGzIpoPdWjs8xpDwLDAZDo1wk6uPAgQM89enTB3379pVy62bTpk04duwYjBodS5ZK3osZclohMQuJKOJT0nD0dDz2xB7Ff3sOYPPu/djCPncePIIjp+K4YIWWtXZnITq1i8TIAb25aEOGQt2QewgJME7EJ/ByqLzt+2Nx+ORp7lBiMNR93isqK7mzSWJqBo7FxWO3XLc9+3k5B46dxJnkFO5UYi3GkaH6Ul1SM7O4gGffkeNWZZziAooihWiGxBQk8JETrVtaXntkUEZ2rsVydBypztbQulSGcllbAhGiKfUtr6jgIZLiklKx/6hp+a37DiGWHefMnFyUltXePp1LW9A5ycrNZ7+HVO6is23vQf5b2HnwMI6fSUSZdBwaeowIyqd6kGhHeR757+vQEZaXYPfYyVgfa3vbI+ccEgQpl7W3r0oc2MOFtrwQ06ZNw/Lly/mDJr1kbu0UFRVxO3S53npnT1QrXlypy4ugqjLycEkBAQFSbt3Qi9gjR46gZ8+ePAkEAoFAIBAIBHXx008/cUFHcPd26DCmF1QKwX1dVBSWYu/361GUlstDfJLoxdPTU5p7cVFQUIC1a9ciI8PsbnnTTTfhiiuu4O8uBgwYgJEjRyIiIgJxcXEoKTF1qFSyZ6TCwkIMHjwY3t6iA+xCZ8OGDdzRp3uUB0+XMiq1DlqvTqgRsChELyRyqMg5iIrc2qEkyClG60GhfOjvwbSOylEHtUswK68jD/+gCxgIZ//+PKyEhi1L21COpifhhZN3V5Zv7kyr0hezZf6VpmqjCxhg0SmIagMq8w7XCG1k+DbdwqUpooqHfODuAgps1cFYnoPyrB38u+yMwutf02nqwL876vx5eAvqEKWQGVrPKO4EQGGAKnMP8U5GEoSYj60KjlovvpyTf1/ofHvxkfUUYko+5oStY8DL8qSyzPXkx5vtI21D4xrG948cCuo7RrLrgNYjkpVncq2hAXIqrScvR8O2w/fHI4rX19xJW83DXJUkrGB1LJTybJyTJh5rws/bBQt/3IcBPYLRNswLL3y8FZGhHpg9NQb7jmQi9mQWhvQOg7GqGsbqajjr1Ph9/SncMrMbRvQNR2igOxZ8twf9urPfoVqFv7fE49YruuG7P49gAMsj0Yo1b3y5C2FsvS5RfthxMA2zp3QGhTRavfkMnrtrCNpHeOGjxftQyPIeubU/OrDpiGB3Ht5ozdYE9O8WhJWb4vDSvcP4PDXb7qKfD+Ku2ew6bKODe/uhPMSllKJ///7o3LmzlCtobfz6668oLi7GiD5+CA+8dPoozjck9NAXx/N2xpG1QdxxzKYwpJq1XZXcgaw4cQVr0w7VEr0QNq8rFXmsndnF2ucglm/uMyHoOmcsSeaCxMrcg6zNt3wnXm0o4+2eSuPBBYbKcgkSmVDYuvLMHew60ZYLXGQs2nK2HF03VTpv1l6ychTvjGnfqioL+bIktqT5MtRek2DSMrwca//K0nl9qO1VCiI51dQGn2aJnLnYsuW5MJSm8n1Qad3Z8pb7UANrU42VuajM2cfXl9F6duSiTmWdrdvu843KoRo+6gpEOBWhja4ICRUeKK2ys1/NjAOry2jPZEzzjkcnl3y4OiocgprI8YRi7D6aj/bt22Po0KFSrkAgEAisUalU0Gq1ItRRa4ecV0jMQAIYcmuhRAKLrNy8Ol1Z6oOEHCSkIMcNEnKkZ2U3ujwStVDdqD5ULyqHhBLWzir1kV9YVLN/TS3jfNLY+tI8eXkShpzNeSsuLUNSWgYvi84duabYExc1FOvzSJ80fbblCupHhDoSCAQCgUAgEDQHNCp548aN/Ht4/05w1DT85W/izmPIT8xETEwMrr/+evj4WIa1uNghkQ+5TAYHB/MXzN27d8dVV13FHR2VnD59mrvBCAQXE5V5R2Eoy5SmLKFQEvr8o9KUJTQKvThxJQzFFNJFfs51gErjBnI+oY4yU2dZOx4ayNQZaKszs/VDnaElyWu4I4ASk/jFj3emqp2DeKeisgOyMjdWEpuY3wNQuA5yOKBjQ8eFFcqOZf2DhCpyDpmcWBRlgYQ0Tj7Stt35dIOorkJF9h6Upm9h59g8mEsOn2TeHzfKlOaS6CUFpcl/87BVzUWgrwvmTO+KxSuPITGtEGv/S8B1k2OgUZv2LbewAmu3xWPd9gSsZymPTRMkNHngjY14+M1NCPZ3RbcopRDHPkfjcrg7y7xZ3XHNxE6IPZGFEwlW55kdgr1HMhEZ6gkfT1OnNolb2od7Ijm9iPqKYTBW44l3/+V1eOfrPRg3OBIquz938V7oQqAm1BH/V9BssPZIblsKjn2OolPfozRlLRddVuYfY+kIF4QUnV6K/CMfofjMz+y6dISLShoKiVtKUzei4PiXprLzDpvLPfUjCk/9wPJsC2kIcnMpTvyT16/2+otRHPcTb1MLjn+B/Nj3axLtixISnxSf+Q2Fx7/mIYioDNrPksRVrOxFKEtj5bH9U5ZBZZLwxhoSnhQn/Mld1OSy6HiVZWzlx4jCQMlUG8ugLzjO8/MPs2PI1iMhkOn4HuPfS9j1PP/oJ6xuX6JMsS5BZeUf/tCiXsXxv0lzWw4SvwRqy9DXNQu3BR7BWK8kBFH4o/P07t1FZUBPlyzcGnAEk73jEakr4qGYzgXmUGuiBRIIBIKGIIQvAoHgooNG+uSWGpFbZt+9KL/ciH3p5dicUIotiaU4mVsJvdH+zXAeK+tgRgVffndKGTKKz/7mtTHCF3FzKxAIBAKBQCBoKFu3bkVeXh682wQisGsbKbd+SrIKcGrDflQZjBg/fnyD3QkvZug+3MvLi4/GV0KuL1lZpjC3BN3b0zEnp8YvvvgCTz/9NA+FROnee+/F559/zh0cyV23Lijk9O7du/nytJ6yjI8++og745aWmjunZWj7JHgix8mXX365Zj1KNL106VIu1hHUpjHPZRc71NFH4YyoY9AaY1kGKhWjvq0xFJ3mIW8qcvZLAgo7x5Udb3IIoQ62C5Eqtm8VmTtQGLeE70N1lb3BTeRIUI7qygI+RU4G1KFJIYRqH18asZ/FOxurjGVSnn3o+FGHKxfS2Pn9VivCc9QHnXfqZC2O/4OP7CfXAtuYwjpRZ2rhqe9N57AR22ksjo4OmHdVdxw4lolvfj/Mww9170ShlkwE+bli9pQYXD/VlEgoQ/SI9ke7UC9s3ZfC1u+B9uFePF8JhS43GKpMSXoX9NPqE8jJL8MbX+zEa4t2oKCoEq9/XtvF4LLBbbgbDC1LVOqN2Hc0E9GR3vyaQSKXYX3CUFZuQEpGEW5j+2DvnY6cL9qh1o18fsR5Oj8YK/LYtegMynP2cZFKccLvKD7zC0u/ojR5DRdnkNsLiVCqqxr/fpbEmhQuiJd95reack2h+ZK5m0xdGMsy2frHbK9fmma6lhbGsWVO1CS6tlrA2k5+Xc07xNtzKoP2k5zQaN+pnae6WJTByqRrkC14nfJizWWx41Wa9Bc7VrutHGJo0wZ+7OgYlqf/x8MgmY7vL/w71YHEM1TnKukaJkNONRRKT1kvqmdrgFpTrcqIjro8TPJKwLyAw5jmEw8nh3MjQLEFbbO7Sw5uDzyMWb6n0M81k7vPULijc43oGxAIBIK6kdtJB3bDZrMVLi8v5y9czhXffPMNT/PmzcPtt98u5dbNiy++iN9//x2VLl4sCfvgxnL5mBF49u7b4OpstmAkR4/Jc++TpgSC1o2D0QDXvCQsWrQIc+fOxcqVK/noSyWVxmosP1YEg6Ipo6+UT3efYR4aDG/jArU0vIbyD2dWIDazHCWVVdBX8cWgUzvAW+eIUe1c4eNsHpWVWmTA1sQSlBmqUaqv5us7shVctSr0CXFG14DaMWFTU1P5iFC53qU+4ahS2F+6FKRBpS/HV199xUeQNoTXXnsNP//8M+bMmcOTQCAQCAQCgUBgC3qOf+CBB3D06FF0nTkUnScPkObUz5Hl23Hkj6083AKJJS7WEEcyCQkJeOSRR3hIKJl33nkHEydOlKbM7Nu3j4d9UkLiFjmPQiZ9/fXXPHwShUGisEiyQEWj0XDxjJ+fHyZMmICrr77a5rE9c+YMfvjhB+zatYuLaPLz86GXnDipDA8PD/Tq1QuPP/44QkJCeD5B53zNmjVYtmwZkpOT+XoUflXG3d2dh4z93//+h1mzZkm5Ahk6j//99x9mTwzD9Sxd6pBriYpCOPAnZTNVhmKT0KIuyHWE1td48LA/FLqHXEgIEoEYqaOtNIV3OpJjCoXikVFpPUyhfhRj9EhUUquzUAG5yajUJrEDUQ1TRyKFiVDi6BzEw2bIVNOSbNvUgafEVh2ok9HWCHsKcUHhjRw0bmxf20HjFiE52VAoiWxT5yB1Glbk1XQ68nVY+RSSSOPenh8bOi7UyUkdicbyLDY/gC1nfs9g7xhwhxm2rMYtEhqPDtyRhYfp4J2Zp1FZeIKH5WjoMSIcHJ1ZnbzZPrnyfaJQTdzpRdonQ0kqDKXJtc6dktrbO7tjTa+tZz2wHEdP5/DQQjdMi+EvtT9ZcgDvfruHi1xkxgyMwJtf7sKCJ8egX9cgLF51FKs2xeGjZ8fiyKkc3P/aRmz98TqMn/sLPN10iAg1hTaLCHLH4/MGYMQNi3HHtT15iCIiMa0Iz37wHz59fhzuenEddiy5Hl4eTkjLKsG1D66Av7czIsM8kZFTijPJ+Xj3sdHILSjD/55jyy6djbzCcjzx3mYuvHn9weG8TGve/fE01mzPwl133cXD7AlaJ3TdJrHrs3OjMbCb6KO4UNAF9Id7u6ulttkECVNy970kTQkudgqNWiRVuCGx0h2nyz2RzL5nGpxRVW15j9NQSNDioa5EsKaUh1Zq51TIPwM1ZXB0aB4h6LKNafhsWQJ/Pnn44YelXIFAIBBYQ+9MXFxcWrfji1BRCwSC+qgwVCMuvxIJ+fqalFigR3qxAZksHcksx5rTZnvK7cmlPKUVGVBYUYUyfRVKWSJ3mDOsnNUni7gbDJFdasCaU8UsX8+XL2D5tHxxZRV3fNmWVMq311jktk20cQKBQCAQCASCc83evXu5s4ezlysiBnSScuunMCUHcf8c4Peo5PZysYteGgsJUaxRHiMSnMjHnjrHlK4sJF6hPBIjff/99/jrr79qOb9kZmZyp5g///wTJ06c4MvLoheCvufk5PDllPlVVVX4559/8MEHH2Dnzp1ISkqyEL0QNE1uMNb5AhPiucwSLtjgo7iPW6R6RS8EH8HOfqM0ijxjKx9tLo8iL074A6Vp//BQQTRq3Vo4QUIM0yhy8zbrEr0QJJKwWJ6tb0vQYSxLt1ruRC0hBmGrDrZEL4RpxHwaX55GzNP+yftKYTpo/+k4KEfa83XYcazI3seOzeqa48KXLU7gwg/aZ+X27R2DamMFDy1lCkuxXNr2byhNXY/K/MNc9EI09BgRFAKDwm/I+2QuV9qnrJ02z52S2ts7u2NNIpd7ru+Du67thWmjOtSM5BzYIxj33tAbowaE16Tu0f5cHNOlgy/8fZxxzaROmDE2CiVlBnRu58Pnublo2Xp9cPXEaAzpGcJTz87+yC8sx7yre+DKcdEY2ieMp2mjO+ChW/ohqo03HmafOifTgCZylnnz4REY3i+M16dzO188d9dg9Ozkz5d99LZ+8HTXmr6zbXaN8q1xh7FG3h/RDrVu5PMjnS6BQHCB4OFYiRiXPAz3SMWVvqcwLzAW9wfvxySveHR0zoe7Ss/FLPS3bTtVwxFVCNUWY7B7Og+jND/oIK73P46JXgno45aJEG1Js4leCPnyIF8vBAKBQFA3QvgiEAguaKpYOyE3FVOj3XF1V0+eJnZ0h0blgEojcDKnAilFBiTm63EwvQLFFVWI8NJgCltGXr53sI6VZXJ4WSsJZSisUWaJgZc/JMKlZtnxHdy4g0x+mZEv03hMN6qNaePEza1AIBAIBAKBoCFs2LCBh+EJ6tYOLj6m0ewNIX7rYZTlFyMmJgbDh9semX6pQi4uFD5KSUREBNq0MYeRIgFKYGAgZsyYgWeeeQYffvghT+Qgc+211/KRRwQJWn777TculFFC4Y3INUYWp7Rr1w73338/FixYUFMOhTtSOr0QJMj5+++/ueDFaDQJ+CdPnozXX3+9pg7PPfccrrrqKvFMYQfx7ql5IBEHiT5IHEKJBDFV+iIu/rjYIDcc2j/Tvqaz/c7j+28PEq2QeKTmuNSxbH1wJx1yY+FlpYPCUpyLY8z3SSpX3ifaVkvQv1sQrp3SmbutyHRu74vrJnfGtZPMqWfnAMyaGI2QAHKpAfy9Xbj4pW2oJ8KDPTBrQjR0To6YPrYDz6dpSuMGR8LHU4dZ46Ph4aaFirWVlNxdtLiWbYPKu4rNc9KaXqOrVA7o0zUQs6fG4K7reuKWK7pieL9wqNUqhAW542pWtoZ9pya3d0wApo5szwU3ddEc7VBGRgZ3U79ZEfrOOpHj1cKFC7F69WrEx8fXXEcElojrhEBw4ULCFleVHkGaUrTTFaKrSy7GeSXhRv9juDv4IO4OOojbAg5jjv9RzPY7juv8TuAGv6O4xf8I7giMxYOh+zE38Ahm+JxGP7dMROkKEKYthre6AppmFLxYI+7jBQKBoGG0auGL4Ow4ejoeX/26HJ8t/b0m/bRyrTRXILj4CPXQoI2XKXXy02JEW1cY2cNppaEa+1LLsC+9nLu70I3iyEhXdGTLyMsPCHNBlC+9RHHgjjFZJQbES24uXfyd0CtYV7NsZzY9MNyF3TYDTuom3HRKq4gHZ4FAIBAIBALBuYREFeT6QZDbi4MU7rM+cuPSkLD1MP9+qbu9kJsKhSmilJ6eju3bt+O9997jLi1Khg0bhsjISGkK/Dt1MFK4Cgp7OmLECJ7GjBnDOxdHjx4tLQkcP34ccXFx0pRpm5RHIZJkRo4cycMSjRo1qqYcCrVA5fv7m0N7UMcmhemRIcHMNddcg3HjxtXUYcqUKTzMEeUJBALBhYaT1hFe7pZhpnmeh5NFcnZS8+VIdEJQH6Enm3Zz0UCrceTf6X2Qp5vleu6uWu7mQvOV0PpyefK6MiSMIbFMmxAP7gAjb5M+aR15WUdHNu2h4/W1haLIc055eTliY2P5dcxeWrVqFX788Ud+naPQf5988kktYabATHOeL4FAcH4gIYyXuoKLVzo656GHazYXtAx0S8cQ9zSWUjHIPR393TLQ2zULnZ1zEelUCH9NGbQOLSAOlNodIXwRCASChiEcXy5i4lNSsXjFGnz7+8qa9OeGzdJcgeDihtxeony0rB1hbQmbzioxIqnAJGRxc1Ih0FXNXVtk3FkeiWWo3aHco1kV0BtNVodtWTkuGnNzqXV0QM8gJ+7+Mqqtq5TbeEQbJxAIBAKBQCA4l5w8eRLkGOIe6AOfdsFSbv0k7zuF8sJS4fbCWLRoEe644w6eyHHllVdewcqVK3mYIZn+/ftzZxdXV/OzQN++fTFw4ECEhobCzc0NajV73mBJq9Vyl5aOHTtKSwIVFRVISTGHjSG3GHLpUUIOLhQuSVmOt7c3OnToAGdnZ2kp8JBJyrBJFAqJypbXo0T1pDpQ3QQCgUDQemjpbky6zuTm5iIxMRGHDh3C4sWL8dFHH1lcowTi/Z1AcDHj6FDNBS06lRHOKgNcWHJm351YUjtUtXg7LSOELwKBQNAwhOPLRUylXo/svHxk5ebVpDzFCDKB4GLHWSFW0dPLZKPpQbXcUA0DxTWywk2yrSXyyo0gXYwD+8+WqwsJYbycHeHk2PibTvlGtTEPzuLmViAQCAQCgUBQH8eOHeOf3pGBUDtp+PeGkHk4gX+Si8ml7PZCnDp1Crt27eJp//79NWIimaFDh+LOO+/kQhblPTodNxKZUOihAwcO8LARNHL+5Zdfxty5c3l4IyVKoYtGo0FAQIA0ZWLHjh146qmn8OWXX+Lo0aPcFUZGuV0vLy/u8iJTXFxcs91169ZxwY783CGeKQQCgaB1cb7bZRK3Uvg9chAbMmQIwsLCpDkm6JpBYfdWrFjBRZoCa8R19ELCUJyM0tQNKE1ZU5PK0s0ueQLBhYDcfSDu4wUCgaBu5PcewvFFIBBctJTpzXE2SdRCTi2E3liF4sraMTjLDNVwZDeRFB6JwiZRE0Rr5JTWtjHMKDZg+bEirDheBEMj2yq5bRNtnEAgEAgEAoHgXEICCYKELw2lMC2XpRz+MpWcTAS26dGjBx544AE8+OCD6NWrFxerKKHQEOQWc/fdd+O5557D+++/jx9++AF//PEHtm3bhvj4eGnJ2qhUKgwePNji+FPYIwpb9c0333ABDKUNGzbU6ogMDAzkoYxcXFykHPBtUafl22+/jXvuuYfXixxkxPOHbcRxEQgELYXcj3m+2iEKn0dizHnz5uGxxx7Dm2++yd3N6FoiQwLKNWvWIDU1VcoRyOdH9DtfWBjLM1GWthmlqRtrUkX2LmmuQHBhYG5/RAMkEAgEDUEIXwQCwUXLjpQyflNI94Wd/HRo560BaV9I3JJWbLYDJ8gBZl9aGapAoY4c0NnPCRq2cBVrhw6klaO4wlIos5/lpRXpkVFigGMTR3yINk4gEAgEAoFAcK4oKSmxcHxpKNknk2GsNKBz5861Rn5filxxxRW8M1BOFOro448/5mKWq666iju9UNghJRQi4r333sN3332HPXv28POQkJDAXWDouNJ69YWQItcWcpIZMWKElAMYjUYeuujIkSO8E/Ktt97C559/joKCAmkJwMnJCRMnTsStt95qcf6o45IEMHv37uX1euaZZ7B7927xDGIDcUwEAkFLIb9NOl/tEF2XgoODefg7Cp1Hok66RpGAUsnp06frFGxealBIQkJcLy4sqqsMqNIXoqpSkfTF0lyB4MJCCF8EAoGgYbRq4YtozAUCQWMg95WfYgt4+utUMQ5nVqCa/adROaCTvxb9Qp1rxCzbk0qxOaGUL5NYoMeqE8VIKTSwh1jw5Vy1KnT2d+Lhjgorq7D+TDFO51YiPl+Pv04W42RuBX9DEeKu4cKaxmFaQTwwCwQCgUAgEAjOFdRBReIXCnHkHWEZNqcuMo8m8s9+/frVcjG5FOnTpw9mzJhRkyZMmMBDQHXq1ImHFSJ3FiXkwLJq1Sps3LgR2dnZPG/q1KlcCPPqq6/iySefxO23346RI0fyefagY09OMg899BBeeuklTJ8+3WIEfnl5Oc6cOYMlS5ZwBxnls4S/vz8PW0HhjUg8Q+dSCdWLRC8///wzD2MhsES8exIIBC1FSzc/1P55e3tjwIABUo4JurbJ1zSChJgk6Pzrr7/wwQcfcJcYElxSevbZZ3k4v7S0tHrfc9F9yn///YeFCxdi/vz5NWU88cQT+OKLL3iYP4PBcqAaQeXGxcXx6xhtT16P0htvvMHd1Wj7zYW8X+J6IRAIzjdysyraH4FAIGgYwvFFIBBcNCQX6rkwhdLRrAoe6shZ7YBJHd3golHBz0WNoW1coGI3ijllRuxPL8fWxFKsjyvBqdxKGFmT0y1Qhz4hOl4eCWDcnBy5UOZ0rh7/xJdgA1v2WHYFKo1gZat4eY1Guk9tTBsnbm4FAoFAIBAIBHVBriCER6gf1DpLRxJ7GCr0yDicwL+T4EMA6HQ6eHh41CRnZ2c4OjpKc2uTl5fHXV5KS0v5dLdu3XD99ddj9OjR/Ds5xNDIer1ez+fXBTnJ0Aj8SZMm4a677uIhKEgIQ24wMtQRuXXr1prtEfSs4Ovri759++K6667jYpt33nmHC3BkqCNx06ZNOHHihJQjkBHvngQCQUshv+tp6XbIzc1N+mZGvm6VlZXhs88+wyOPPMJFnSTAXL9+Pb8WUaLQeuSMRiH5KJ9EMtbQ/h04cIC7qL322mv48ccf+TVJLmP16tU8tB8JSWl7SsjBjJYnF7ZPP/2Ub09ejxKJbkhIc/LkSWkNgUAguPgQfQMCgUBQN3I72aqFLwKBoG66RXfAKw/ciUUvPYlH5t6AkAA/ac6lAzm4qFmiEEZOage4aVXw1DmCfUWfEGdM7+SB9j6mF//U7sX46zC1kzsPZUTr5JUbkVNqhIeTCoPDnDE43IWXQXizcqZEu6N/qDOfn19WhexSAy8nyE2NyR3d+Wdjkd9niBesAoFAIBAIBIJzxcGDB/mnb7sg/tkQ8hMyUFlSzp1FSHAhaDw0Kr6oqEiaYsff15eHHFK651BookOHDklTtaHnAuWzAYltqAwSslx55ZVcSKMkNze3ZkS8cl1yo6HtR0dHY8yYMbjtttu4W41MYWEhTwKBQCBoHbSWfkwScVpDYZEIEsCQuJbuM8j1ha5BSjEnCTGTk5Oxc+dOLoCxdb0jtxaaR44xp06dsriOEeRqlpWVxcWdclghgrbz559/cjcYKjclJcVC+EnQNTYpKYm7yTQX8nVW9DsLBILzjeg9EAgEgsYhHF9agM7t2+Kdx+/DV68+YzN9+sLjWPDUQ3jo1usxuFd3aa3azLhsJBc82Crjy1eexifPP463Hr0Hc2dNR/uIhsVqH9ijGz585pGaMm6/ZqY05/zw0v131NoXe4mWvdQZM7AvJg4fjGF9e2L62BEY3q+3NOfSQadW4coYD1zZxRMzO3vg8k7umBrtjunse/8wZ4R7auCoeDLVqR3Q3lvLnVpo2VldPXFVFw8uYukVooOnztws0mqh7mouoKH5V7LlaHnaztj2rmjjpeGhkBqLvMrF2sYJBAKBQCAQCM4/NJKa8I4M5p8NIe3QGf5JIXbI6UTQNJT39TTiPDY2tqZDjzrkKAQDhXawBy37+++/Y/v27bWcXFxdXfmnEnd3d6jVJgE+dSb+8MMPSE1NtRhlT+4xdE6tnWaoPIEl4rlMIBC0NC3ZDtF1ikLoKQkPD0ebNm34d6obiVFiYmJw00034fXXX8eCBQt4ev755zF06FC+HF3LyFVs7dq1Fq4tlL9lyxYexki+xvXo0QOPP/54TTlU5rx582o5z5DQha6PchgjEoZec801eOutt/h677//Pg+TRGEJm9MNQT4/zbcFgUAgsE1N+9OMbZxAIBBcTAjhSwvg6e6Gvl1jMLh3d5tpeL9eGD2oL66aOBaP334THp03x6aTR0RwEAb16mazjCF9emBE/14YN3Qg5syYjBfvvR2zp06Q1rTP2MH9MHJA75oyJo0YjLZhIdLc5qdXTHStfbGXaNlLgX7dYuw6ueicnOCk1fIbHxedM/t+6cXkJ+FJhKeGi1BI5BLqoUGIu5p/d5ecW6yhdbx0jnzZSLYerRvM1qFwSLYgBxiaT8vR8lR2gKu6SaIXjrReY9o4cXMrEAgEAoFAILAHuY5QKADCLdCLfzaE3DPp/HPAgAH8U9B4SIRCjjkyGRkZvENu7ty5uPXWWzF//nz8/PPPFiPYraF5JJihEBB33HEH/5Q7Ayl0xNdffy0taer0UwqVyG2GRsI/+OCDPFEYClrvjTfewKOPPspFODIDBw5E27ZtpSmBzMX67kkgELR+5Hc956sdIjEkOaNQSk9P54JLEo+QE4sScguLjIzk38lNbOzYsXjmmWdw8803Y/z48Rg1ahRPU6ZM4dc6CutHkMiFnFlycnL4NEFuLnQtok8ZCuk3Y8aMmnKozBtuuIE7lbm4mEOKx8fHW4To69KlC2bPno3LLrusZt3p06fj3nvvbdaQjXVdwwUCgaA5ka8Tom9AIBAIGkarFr5cChiNVUjLykZyekZNKigqhiN7qPByd0PHthG4Ytwo3HvjtQj085XWqk1ZRYVFGSkZmTxPq9HA38ebi0RuuXIabp45RVqjNlR+7y6doJFGjhFhgQHo372LNHX+oAe+zNw8i32yTunsuF2s0Lm458ar8dFzj+Kh267nLkG2+H3dJqz+dyuOxcVj6aq1WLNluzRH0Lpp/IsN8TJWIBAIBAKBQGAPpUuIs2fDHT1Kc0xhbyisjqBpeHh4YPjw4VyQQlCnH4lYqDNx69at2L17Nw89NHr0aD7fHuTWQutRqAga3b506VKe/v77bx5aQmbq1Kl8e46OjlIOeOfl/v37sWHDBvz00098vd9++43nyYIo6pSkzkKlSEcgEAgELYvcj3m+OjQ///xz3HXXXTyRWPLVV1/FypUreYghmX79+nFRiuwQRkIUuoZ169YNAQEBcHJy4q5jlGgehUokhxiZo0ePIj8/X5oyiUZIoKuEQhNRvlwOlenn58fLUoYKrKystFiXnF8oJBItQ+vRJwlQSaRD6zcX8js50fEsEAjON3KXgGh/BAKBoGEIx5cWplKvx8+r1+Oh1xfUpLtffAuvfPo1jp9J4MeAHGJGD+yLcUPtj8LLzs23KOPB197HHc++jq+XrUBeQSFX54cG+mPmePagEm07djuFywkPMcWDz8kv4A8gLs7OGNavF887nxjZtjft2GOxT9bpzc+/l5a++Ahh52rCsMEYOaAPotqEw00x2kHJyfhELPhuKZ5892N89dtypGWZR1QIWi9CxCIQCAQCgUAgOJfI4gbCyd32s4MtKopMghkfHx/+KWg81PFGI87/97//1YyOlyFRDIlNaJ4cMsIW9CKbOuxkUQq5uOTm5vIkj5Dv27cvHnnkET4anjoeZajTsXt3U4hkGsmfl5fH16PQFQSVOWvWLO7+MmjQIIsORYEJ8XwmEAhaCrkf83y1QySwpJBDlPbu3cvdVAoLTSJYgsIW3XnnnVywKXeyktDS09OT1zE5OZmHRaIQfh988AEPM0QCGjncIkH3JCQClSFRS1CQ6X2zDDnMPPnkk9wR7fTp0zWh+qw7dv39/S3uUchVjcIivfPOOzyEoLLuolNYIBAIBAKBQCAcX1qYquoqJKdnYt+R4zVp16Ej+H3tP1zQkJKRxZdzd3PBqAH2LRsr9HqLMijtOBCLr35djp//Wo/SsnL+ANAmNBgj+vWW1rJkaJ+ecHN25i40B46dRFl5BVQqB3Rq18auWKa5oIeprNz8WvukTORycrHipNHAzcWZO//UBQmEElLSEHviNNKF6OXCQXoYb8yLDfEALxAIBAKBQCCwB4UsINQ6LRw1ZieQujBU6GEo13PhBgk0LkVIFEIdbzQCXk400r2xUKfclVdeiZdffpl3yJHI5LnnnuMdcxQCon379jwchHI7EyaYQxGTGIXmU4gk6kikdakMSlTexx9/zEMeXXHFFdydhwa2yNAoe1qelnnzzTfx+OOP8/WefvppHr6Cypw3bx7fL3n0vkAgEAhaCa1Ed0cCyvvvvx8PPPAAevfubSGSJFHKnj17eBi+hx9+mLvELFy4EEuWLMHq1au5U5nSMcYarVaLMWPG1IRDImj5f//9F59++ikXz1DZ5JCmFMwQdP0kpzMZmn/8+HH88ssv/PpIgtAffvjBIrRScyC/vxOv5gQCwXmnpv0RDZBAIBA0BAd242bzFptGFVnbEJ4N33zzDU/0wuX222+XcuuGXkCRArzSxYslbyn3wmdgz2544+G7Eejng5KyMjz/wef4Y/0maa4ZZ50Tnpl/G6aPGcFfbCWlZ+DOZ1/HifhEPv/eG6/B3Kun89BEpxKTMXnufTzfmiA/X3z24hOIbteGP0+t37oTdz3/hmmmBAlb3nnsPkSEBCG/qBivf/YNbpt1OdqHh3FRzec//YEF3y6Rlm4+Vi56Dx0iwqBnDzKLlv6O98/DNlsjDf2NXOw4GA1wzUvCokWLeIx8sl9VjhIhS/fnn3/eYoTr+YQ6COiFsjL+MJGamsofzOV6l/qEo0plDiGmK8yAurIU7777Lrcpbwj0wnrx4sWYM2cOTwKBQCAQCAQCgQyN2n7ooYfg6ueJSa/fJuXWTUlOIVY9sgi+vr58xLXg7KHXK3JYBhohT+GPlCKV+qD1qYOR1pdHv9NIeeqArK8ccmylDkFal8qh5XU6Ha+HeFFeN9SRS526syeG4XqWBAKB4Hzx+e+J+HVDKhdJkkPYuYTC5JEw5ODBg1IOMHPmTERFRUlT4GGCvL29ERwczBO951Jeb+h6smnTJnz22WfcLUZ+/0bXt7Zt23IHMnJliY2N5SGOZOj9Vc+ePaUpoKysjJdDIhUSuFjj5uaG0NBQXHvttZg+fTq/9hG0/cTERHz33XdYvny5hcMLQeJd2n6vXr1wxx138FBJzcHEiRP59fWVuzqjV7SnlCsQCATNz5K/U/DNyiRcc801vG9VIBAIBLah+0Ia7NPwNzAtAN3cXsqQ40pmdh5/gUVo1Rp4ezZ+JF56dg4XsxD0ustFp+PflYwa0BeB/r78OzmIbNy+G/uPnuDb1mo06Nu1M3TSQ0drpG1YCB669Xo8f888/knT9pg2ZjhfjhJ9t+bGGZMt5tN+XzN5HN594n588cpT+PKVp7Ho5afwxiN3Y+LwwdJaddO7Syc8Pu8mLHz2kZoyKH38/GN4dv5cDOrVjS8nb/u6qePhKsWIJ2HTlFFDa+qk3L/u0VF48o6bef7866/iefaIbtsG9865BgueeojXX67Dpy8+jlceuBNTRw2r8xxT+bQdEmPR74V+i3NnTccHzzxsPi4vPYkX7rkdw/qe2/BY8ota6xe2ZAH+zz//8AduGmV5PhNtc+PGjbwO9jDX17Le8tSl3sYJBAKBQCAQCM4NJAgndB6NCHNUKMIcnWvo/p8666jjkL9waYTohaD15Zc1VAYlKq8h5dAyNKqeOjFpPepEpLKsn6EEAoFA0HqQm/fz9X6IwuaR+EVOkyZNwogRI9C5c2d4eXnVut6kpaVh6dKlOHToEBe9kFMaDWhdsGABXnjhBS66veWWW9ClSxdpDdvQOzQa+EXuLpTGjx/Pr1UyVDY5udAAssOHD0u5pusiOZuRMIgcXm6++WbExMRIc00OMFTHDRs28PBL8v3QuUa8vxMIBC2NuKcXCASChtGqhS8C06gt5a11Uy9wsniGsC6DxA4kbCGBCzmt7Ik9irzCImzffwhFJaW8k75DmzAM7dPDtEIrxM/bG2MH98fU0cP4J03bo2enjnw5SvTdmsE9u9XM79OlMx64+TrMu3o6K3cADwc1hB2HYSxNGDYI99wwC7dcOU1aszZ0bO+49go8dcfNmDl+FBeMyGVQGtm/NxfXDGN5hLxtmnZxNolQSPjSr1tMTZ2U+xceFMjFN5Q/kpVtjxunT8Jzd8/jAp4xg/ry+st1GN6vNyaNGIL5bF8enXcj2keESmtZQuXTdiaPHIqenaPw+O1zWLmTMXqgeZ+G9e2JKWyZ+9kxm37ZSGnNs0d+wLR+0KQXuzSC8dixY3wEy/lMtE355bI9zPW1rLfllEAgEAgEAoFAcHbIoY6cmiB8oZHeAoFAIBAIzj/nuxuTnMBkYSUlEqTQezV7xMXFYdeuXTUhiEgkc91112Hw4MFc7EKhiEhAK9+H1AW5JXfq1Ik7utx33308HCCJaMg1RiYlJYVvT6/XSzkmYSe50QwdOhQ33XQTd36mcEtDhgyRljA5169Zs4Y7MDcnot9ZIBCcb6pFT4JAIBA0ilYtfBFqaiDA1xuOktq+lN3En0lu/A18oJ9vjVMMHdOc/AL+XYYELSRsoXv3/MIibN13iOdv3n0A8Slp/LuXhzsXOLRWHB1V3MmGXFLok6bt4aTV8OUo0XdrSKwiz+8e3QGXjx3Bw07tOBCLH5f/zYVB5RWVbF0t2oaHYtaEsejfvfbIBirnnhuvxuxpExDToR3cXV2Qk5fPBUXf/bEK6/7bicS0DLacFp7ubnydwpJS5BUUIa+oCAajSaxUVVWNfDbN81kqKCqG3mB6AFSrHeHibNpvqqMtbr3qctx8xVT07NwR3uw8FhSX8H2R65CUls6PQ2RoMKaNGoa7Zl+FkAA/aW0zVL7puOi4o8tlgwdw++1/d+3D0lVrcejEaVZnI5/fuV0bXD3pMrsimsYii7WsRVs0mpFi2M+aNYvHuz+fibZJ26Y62MNcX9tPxo1p45oqehMIBAKBQCAQXPzII5yd3BsufCkvMq1DoY4EgksZ8e5JIBC0NK21HSInFqWohQQofn5+Fs4wFFKJBojZg/ZN3j96t0Xv0SIjIzFo0CAe3omcZ5Tk5Zndz5UDOcnFjEQyXbt2xYQJE7hoRun+QqKXhghwmoK4TggEgpZG9A0IBAJBwxCOL62Ybh3bo0enKP4wQTfY8clpyM7Nk+Y2nLGD+yE00J9/r6jU4/iZBP5dZmjfHlzYQhyLi8e+o8f597yCQi7yIBcYEt+QCORcCRkuFNqFhyAtMwvPLViE1z/7Bot++h0vLPwCX/zyJwqLS/gNR1hwAHdusWbmZSMxfewI+Pt4c0HIX5u34f5X38Urn3yNL37+A29/9QMeffMDvP/tEsSePM3X+WzpMjz0+vv4/Kc/UCQ9rFXq9fjlrw08n9KLH32BU4nJfF590Lm/dvI4BPv7ce3FjgOH+TaVdXjkjQ+wZOUalJaVw83VhTvAkKuLPdSOjmgXEYaDx0/hiXc+wltffI9Pl/yGZxd8imVrNvLfGP1moyMjMKTXuXEJkh8wrR806aF37NixfLRISyTaNtXBHub6Wj0gSzeq4sFZIBC0JvIqi5FTWWg30XyBQCAQtE5qHF8aI3wpMK0jHF8EAoFAIGgZWns/pvV7qyNHjiApKYnnUzpz5gyWLFmCjIwMaYnakDj3hx9+QGxsLCoqKqRck5MLiWCst0GuNLILzb59+7B8+XJkZ2dbLEdhACmR04sMiWIorzmQt+1w3j16BAKBwNTuCOGLQCAQ1I3cTgrHl1YIOYVMHTUMD956PdqEBvO8vMJCLpwwKpTu9UGuHbdfMxPXT5sENxdnfjxPxCdi+YbN0hLgQpbeMdFc2FJRUYk9scdQXGKOh7r9QCx3gSFCAwO4KOJ8QOIKCqvzxStP2UwLn30Eg3p2l5ZuPsrKK/HD8r/xz849OJmQhNTMLC4OWrzibxw6cYovQ6GIOrdvy7/L0HGdMW4kfDw9UMWOOwlO3vt6CXbHHuXCo7SsHMQlpWD/0RP4edU6rP1vJ1/vFNvGviPH+TyDwcjzqqqrkJSWwfMpxZ44bXGO6mLq6OFc9ER/8MdZvd/56gds3XuwVh0W/fQHtuw5wOtKv5XxwwaibWiIVIolVBY515D4h5xjTicmIyUjC4dPxuHTpcuQILkEkRNNp/aR/HtzQrasSpvW85lo22eDcuSKQCAQtDTb847hn+xDdhPNFwgEAkHrhJwYCZW64Y/4Rr0pbEFdoTsFgkuBS/Xdk0AgaHlae0dmYGAgD2Uks2PHDjz22GOYO3cuT+SEvHv3bmg0tR21ZShM0p49e/Dcc8/hjjvuwFtvvYUPP/wQ77//Ph599FEubJEh8UqPHj1qhC9ZWVl82fvvvx9PPvkk/07ptddew4svvshDI8kMGDCAO9I0BzXCF9HvLBAIzjPybarSaUsgEAgE9hHClxaGRBOTRw7Bc3fPxfP3zMN7TzyA9598EHffMAt9u3SGlj04kBPHsjX/4J8de6S1auPt4cHLoPTy/Xfgg6cfwhsP340bLp/IQ9jQg1RKRiYWLV2GtKxsaS1gcK8eCAsK5N+z8wuw7UAs/y6z98hxHJMcYijUja2QPs0B1Tc8OBBD+/S0mQb16sbDQDU3J+MTsXbLDu5ioiQ7Lx8nziRyJxfCx9uTf8rQcW0fEcb3I7egAL/8tR7xKbbDVOUVFvHyzjXkFtQ1qj2/KaqorMSG7bsRezLOpniKBD3rt+1EkeRi0yYkGN3Z+ragv0sSy+w6dLhWWcnpmVy8Q1A55HYjqI38nNyYNo6Op0AgEDQn5OqSWZFvN9F8gUAgEFxEiJeoAgFHCF8EAkFLIb/raa3tULt27TBy5EhpCigsLMT+/fvx33//8XTixAmMGjUKnTt3lpawTWVlJQ4fPoxt27bhl19+weLFi7F06VJs3LiRhygiaHDZlVdeiV69elkcl8TERC6u+euvv/h6lJYtW2bhINO7d28elryucORng7hOCAQCgUAgEFwYiDdcLQwJX/p1j8G0McMxbfRwjB3SH8P79QQ5vajVjsjMzcO3f6zCd3+sRn6RyXnFFl7urqYyWKIwNaMH9UPfbjGS8KAaR06fwbtfLeauHkpIQOKi0/Eb+IPHT3JXECUkhKBwRyScoIcOcjYZ0KOrNLf5ICeMo6fjsW3/IZuJHFQyc3KlpZsPEgnZO+7kwqKXRkmSQ42Szu0j+XElTickY8tey+N+PujSsT28pRBWBUXF2H3oaM1IUFts2rUPufmmTk0SOUWG2R4lQWIXEsqUlZvtSZWkZWfXCILo9y2ojXheFggEAoFAIBC0NHInjhBYCwQCgUDQUrTuF0TkdnzjjTfycN/0XUmHDh1w7733YubMmfDy8pJya0MhwoOCgmrWLygoQG5uLvLy8qDX67ngZfjw4XjiiScwa9YseHqaBxfSOlFRpoF5ZWVlfD1KRdK72sjISMyZMwePPPIIunbt2mxiXvM9E/8QCASC84Z4ZhMIBILGIRxfWgFqlSO3cFQ5qriooLi0FMfPJOK731fhgVfexQ9/rrZwabEFXfioDEoOKgcuPCAXkd2HjuCtL77HM+99wh0/ShWxT0nAEtOhHV9XbzDyz+umjsetV02zSAE+3iivqOTr+Hl7Ykjv5g8xRMIXEty8+snXNtM7X/6A2FNx0tLNh95gErbYoqSsnIchsgUJjuSbkfSsHC4gOt/4sIdDjcYkPKG6yqGZ7JFXUIic/AL+nYQ8FKbJFvR3KYdhsgW541wqf7tNRrpPFcdJIBAIBAKBQNBiSPeiwvFFcKkjnssEAkFLIfdjNkc7RGGDKBTRokWLalLfvn2luQ2D7hFI4HLnnXfi7bffxjPPPMNFJhRq6IUXXuCCmLZt2+Kuu+6y2A45xcjodDrccMMNePfdd/HOO+/gqaee4mVQmKM33ngDCxYswMMPP4yJEyfy0ErKzl0Ss7z00kv44IMP8Oqrr/L1KFE9aL1XXnkFN998M1/OyclJWuvcQ+IdwmAQ1wuBQHB+kVsdZdsoEAgEAvu06jdcl0JjTk4qXy9biTueea0mzX/hLTz17sf44tc/sevQEWTm5ElL2yctO8eiDEr3v/IuXvz4S/zy9wYcOnHaQvRCkICFhCwECR36dYvBTTOm1EqXDRkAF2eTewnd6Pfv0RWBfr58urmgC3phcQmOn0mwmU4mJLWImERJXQ+lSqeTusQzzYkjeziV/4ZIUFVUUsq/14VcV1rP2sWmwYhnwAZgOi8k8Goo4uZWIBAIBAKBQHAuqa4y3bgL4YvgUker1fJP0aEpEAjON835roecVHr27ImhQ4fWJH9/f2luw6FBluHh4Rg8eDCmTZvGQwpNmDCBl03uLBqNBjExMRbbUbrD0PrkzDJo0CCMHTsWl19+OS+DnGLGjx+PIUOGcHGNq6urtIYZKr979+48nBJtk9ajRPUYPXo0D4tEYhnaRnPi7W0K5Z5bZBkKXyAQCJqbvEJTu6N0wxIIBAKBfYTjSwtDgoRTCUnYuu9gTdpxIJaHHSKnkIZCYWeUZVAi0cyx0/E8zI01JFwhAYusWFepHODr5YkAX59aidxLZCEHPY61CwvB4PPg+tJU6KFRJUQCTUIrOcTQ315LCXZsQaND6GUkjei4++67W3169tlneX2p3nUhRhYKBAKBQCAQCFoK+V5UCF8ElzpyR3D+/9m7D/gmzvMP4D9L3nuAB7YxGMzee4UQAiGQBLL33rMjbbrbpO2/O03TJmnTzCYkzWgGZIcQ9t7DGAwG44X33kPS/55Xd7a8B97+ffN5I+nudDrJ4u70vs89Dwc0iaibZefbM2z3hQFNOV+Q4BQJapHsKu0N2pHlJUjG29tbrUOa9J21ZT0S2CJ9bMbzZDu6OtjFkXGcyMxruuw7EVFXydL3Ox0JXCQiGogY+DJAzZgwFsPDh6hAFsms8vc338V9v/hds+2x3/wFyecy1HN9vDwxd8oEdb83cndzhZ+Pt/6osaAW6s52lvyiIv0eEDZ4kH6ve+UUFNSWJPL29MDkMfaauM0Zpn0fAv3tV2RUVdfgXGbL5bW6k/yolfSschWIpGXt7U2ubpHtlR/zdvV/xNuYFoeIiIiIepjxe7srrzYn6gvCw8PVbXYBBzSJqHulZJarWw5o9m5SNkpk5/M4QUTdK0vf7/A4QUTUNry0a4C6YMZk+Hh7qvspGZl497N12LL3YLPt2137sC/2uCrNIhH+k0bHYMKoEer5vcHZ1HOoqLJfJeHm5orI0BB1v6HoyHAMHdL0vM6UmJaugkfEiKERmD2p+wOFYk+eRoGe7SfAzxcXzp6u7jdn1uTxGKSn7iwsLkbsqTPqfo9yclJZiX7729/i008/xYYNG/pMk+2VOsSy/bYGgwlOeiAMg/uIiIiIqMew1BGRMmTIEHWbXWDvUyAi6g4W7TjMwJe+wfj7GJkXiIi6g8ViQ45+fmoE4BERUdNqsxqr//dSHBTuGmOih2HS6FEwm0zawdOqAiTyCusylDTFYrFg56GjKC4tU49DBwVh7pSJ6r7B3dUVj9xyHZ587D78+P7bMT4mWp/T9bLzC5CrNeHq7Iyp40ap7Wlo5eKFCAvu+h+T2w8cRo6+PYMC/XH7VSswpJnML7KdAb51tW+FfN5GVhC5AtPD3U3db4+TZ5Nx+MRJ9e/I1cUFly6Yg0Wzpulz65NtW7ZgNrw8PNTyEvRy9OQpfW7nkcCjH9x9i/qOfO/OmxAR2vIJm037jpZ5BmLH8TPYFX8WBxLP9Zkm27vzRKLa/oaBL0YCGO7jiIiIiKinGOeizPhCA11ERIS6lZIjNRb+RiOi7pGl7XNKy+0XzXFAs3cbNMjepyt/MyKi7pJfXI3ySgt8fHxUIyKi1vHSrgFo/rTJtUEYhSUlKqClLbbtO4SktHR1X8oJzZ06qV5wybiYaFyx+AKsunghFkyfAovVqs/pehIoIoEeEsgjHbfTxo/Bd26/AaOHR6n58n4fuPEqrFqyUAX8dLW4U2fw9dadqKqqhrPZrH1WE/GTB+7AikXza4Nc5PbaZYvxf48/hGsvXaymGeS9FJWWqvtu2mc8T/usJWhEPu8LZkxFyKAgNa8l5RWV+PDrDUjLzFZxFlHhYXjk1utx19WX1/79ZX2XXjBXbdvUcaNhMjmp5d//4pvaIKfONHHUSFy55EL1HZmu/Y3yC4v1Oc1xQpWLJ6rdffpsk+2vjXSpZX8sGZSIiIiIiHqCTT8XZcYXGuik1JGbmxsqqyxqgIGIqDukZJRDYlA5oNn7BQXZ+2GZ8YWIutO57Ap1nJCsU2azWZ9KREQtYcaXAUYCHeZPnwR3d3vAypmUNOw82LbAF8kKs+/YCVTX1KjgkpioSBVgYpBMMsGBASprSEZ2LpLSMvQ53ePdz79BSrr9Nf18vHHNssX47fcexEv/9zP85cffwW2rVqgySIdPdH4mk4Yk6GT12i/w1badquSRfCYXzpqO79x2A579+eNqm+T2wZuuwSXzZ2NYeJj+TLvC4hIcO3laBfJIoI4Ezvz+8YfxwlM/xv3XX4khbcxaI+WpZDuycvNUAM64kcNx5zVXqM9DtkHW9907blTbJtsoy8nyu48c09fQuWKGRSLQ3w8ebm5IOpeB0nJ7StcWad81m5OpzzbZ/oa4byMiIiKiHqefkjLwhQY6d3d3lW1BfqalZ1foU4mIupZjmSMOaPZuw4cPh4eHB6qqrTgYX6hPJSLqWvuP2ysKjB07Vt0SEVHzjGzGDHwZYCRQJSZqqPoCSADLoeMnUVDUWtaNOht27kVugf0EP8DPB4tmT1f3xcihEaokj2Q5kfWWV3Rvh5FkSXlu9fs4mZik+nD9fX0weUwMLpw5DdMn2E8O3vv8G6RlZqn7XU0yp7zw1v/w9qdf4Zx239XVBcMjhmDOlAlqm+RWSv2UlpUjJT1Tf1ad1Wu+ROyp0yoriK+3l8rIsmD6ZAwND4WzuW3/dMvKK/DJt1vwf/98DXuPxKl1SZmqGRPHqW2Q9UkmGcn0IvNlOVlentcV5DsiP+ZLysqwP/a4PnXgas8+jinoiYiIiKgzsdQRUZ0JEyao2z3H7AMMRERdSY7Be+Py1X0OaPZ+Q4YMwcyZM9X9b3Znq1sioq6UV1iFLQfz1P0FCxaoWyIiap2TdqLd5MhrRUUFKis7L33fG2+8odr999+PBx54QJ/ash/84AfYtGkTqjz9tRagT+37JCBDsqO4ubjAYrXg1NkUZObaD2LtIVlCIsNCYXJyQqn299p3NE6f07zgoECVqUWyf1htVpWVJVnPktIWHu7umDhqhMrYYdP+y87Lx/HTZ9W81X/5NWZNGo/07Fx8//d/w8G4E2p6e0hAhpf2GlbtaynZW87qpZXaytPDXb2/yWNGqewmYYODUFpWgbjTidhz5Jgq1eTn640wvTZrek4OTiYmq/uGSaNjEKD9jURT8w0h8lkOi4TZZG7x8w/VtiEiJFjbnmi1vNyXQBP5nOISEhGfmITUjEwVKONIAkTGjhiGaeNGY+q4MfD38UZKRpb6XDfs2qeywrR1G9xcXRAdGYHwkMGYMnaUCn5yd3NRn82ppBQcPZmgXv9MSioqq5pO7dzWv43j9zK/qBhH4u0ZdoaFD8E/n/oRRgyNwIkzZ3H3T39bG0Q10LiV5MClohhPPvkkVq5cqU9t2bPPPovVq1fjjjvuUI2IqLO9lbIBxTXNZ+LycfbArZH1S/MREVHvYPzeHrdyLsavmqdPbdm+/3yNxK2x+OEPf4gVK1boU4kGph07duAXv/gFAv1c8fR3xyFskLs+h4io8x05VYgnXzqJikoL/vCHP2D27Nn6HOqttm3bhl/96lfw8XTG3384gccJIupS63Zm4e/vJmL8hAnqOOHp6anPISKipri4uKh9Za8OfHn88cexefPmfhf40h9JsMm/fv0TRIaFYNeho3jwyT91e8YXRz5engjw9VWBMDU1NcgrKkZeDwdZyDZJCSYpKSRXVUpWlfyiIhSXlulLNE2eNyjAH67aP9qSsnL1nI5mZJFgmiA/X7Udcl8+Gwmgkc/HYrHoS3WNJXNn4f8ef0gF8Hzy7Vb86C//0OcMPO4lOXCuKFY/mFetWqVPbRkDX4ioqzHwhYio7+pI4Mve17/C2W3H8MQTT2D58uX6VKKBqaSkRP1biI+Px/1XReGqi+qXIyYi6kzPvXcGX2zPwsSJEzmg2UfIceLnP/85jh49igevjsKqRTxOEFHX+cU/j2P/iUI8+uijuPrqq/WpRETUHCPwhcW8qVOMjxmhMtlUVdfgSHxCjwa9CAkmkUw2klkkITm1x4NehGxTakaWyvAi2yXb11rQi5BlElPPqedJmabzKUMkwS1Zefkqy4vx2WTnF3R50IsYHT0UXh7uavsPxA3sMkdGuGEzcYdNYgp6IiIiIupUVvuNycRuASJvb29ccMEF6v7GfTkoq+j638hENDCdy67AjiP2MkcXXnghg176CDlOXHzxxeq+lB+prml7nx4RUXscO1OM42dLVJm1RYsW6VOJiKgtenUPV3sGhalnjYyKgIe7GwqLi7HnSOsll2jgGREZARdnZ2Tk5uLbnfv0qQOUHsPCfRwRERER9RTjXJSBL0R2MrAQEBCAs+ll2H+iQJ9KRNS59hwrQEFxNcLCwjig2cdIgOSwYcNwOq0U2w/n6VOJiDqPxWrDl9szVRD2nDlzEBgYqM8hIqK2YOALdYq16zfj4af+hB/+8e84dPykPpWozmsffooHf/UH/PLZF5GdZ7+yZaDjPo6IiIiIeorNaj8XZWZBIrvQ0FDMmDFDXcW/flc2ikpr9DlERJ3jVHIpPtuWoe7PnTuXA5p9jARHLl68GJVVVrz9VSoOnez5DONE1L98uydbBUhKkN0VV1yhTyUiorbipV3UKaR0zuY9B7DrcCyKS0v1qUR1Yk+dxibtO7I/9oQ+ZSCzDy60J/CFAxJE1NWm+o3AnMAxzTaZT0RE/YfNZq91xIwvRHbyb0HKWPj5+SH2TDHWbErX5xARnb/cwiq8/lmyKnUUExODlStX6nOoL1m2bBnmzZuH1MxyvP5JCvK0vysRUWc4cbYE7647h+KyGtx4442IjIzU5xARUVsx4wsRUbez79u4jyOi3mSk9xCM9Ylstsl8IiLqP4xzUQa+ENWZMGECrr32WpVe/qudWfhmd7Y+h4jo/Lz+aTJiE4rg6+uHu+66iwOafdTgwYNx7733IioqCgkppXh5TbI+h4io40rKa/DPDxKRnlOB6667DvPnz+fvNCKidqjt41L/JyKibtT+jC9ERF3NzeQCd5Nrs03mExFRP2JP+MIOVSIHnp6eWLFiBS6//HLkF1Xjna/TkJxRrs8lIuqY19YmY8fhfFVK7c4778TUqVOZ2bcPkxIkjz32GExmM3YdzcPbX6bqc4iIOub59xNVOTw5PkgQtpeXlz6HiIjagxlfiIh6CPdxRERERNRTjHNRDrwR1RcQEICbb74ZkyZNUlfdvvC/RH0OEVH7SfYoaeWVFtx6662qpJqbm5s+l/qqyZMn4+6770ZFlRWfbc3EemYII6IOkH3IM2+fxs4j+erxQw89pDJLERFR+xh9W7y0i4iou+ljC+0JfOGABBERERF1JpvVnvKFGV+IGgsNDcUjjzwCZ2dnxCYUq2wNRETttWZTOt5bl4bishpceOGFuPLKK+Ht7a3Ppb7MbDarDGHLly9HQYk9Q9hHG9P1uURErdsbV4D/e/UkNh/IRVW1FQ8//DBGjhypzyUioo5gDxcRUQ9hxhciIiIi6inM+ELUspiYGDz++OOwav9WJFvDH/9zCnlFVfpcIqLmlZbX4OWPk/DhhnRk5Faq/cldd92FwMBAfQnqD3x9fXHLLbfg9ttvx7mcCny8MR2vf5qMEu3vT0TUkrWbM/DaJ8nYf7wAHp4++MUvfoFLL71Un0tERB3FUkdERN1N37VxH0dEREREPUY/FWXGF6LmXXTRRXjiiSdQY3PB9sN5+PMbCTh+tlifS0TU2OnUUvz1rdNYtysbOQVVKtPL9773PQwdOlRfgvqTIUOGYNWqVfj+97+PapsHvtyRhRc/TMLZ9DJ9CSKiOmnZFSpATgIjz54rw7hx4/DLX/4SCxcuZEYwIqJOwB4uIqLuxlJHRERERNTDjHNRBr4QNc/NzQ2LFy/GU089hWHDR+DwqSK8+MFZbNqfoy9BRGRXY7Fhx5F8PP9+IvYcK0CVxYSbbrpJZXoZO3asvhT1RwEBAViyZIkKlBw+Yhy2H8rFP/93Ft/szlaZYIiIElJK8eGGc3j2v6fx1Y4sZOdXYunSpXjssccwbdo0VV6TiIjOHzO+EBF1O3sQS3v2cdwfEhEREVFnslmt6pYB1kQtk+CXmTNnqowNcjXuyeRSvPVlKt7W2sH4QlRW2f8tEdHAlF9cjS0HJNAhEW98lowTZ0swNGqYygBy9dVXM9PLAOHh4YHZs2fjkUcewfSZc3HsdDHe/ToNf3v7DN7Rbo8mFLFvj2gAOppQrM4bX9COER9vzECstm/wDQjFHXfcgdtuuw2jR4/WlyQios7AwBfqdaLCwzB78oTaNmvieIQNHqTPJeo/uI8jIiIiop5is9rPRZnxhahtJBX93XffrTI4lFV74LNtmXhlTTKeey9RlbZIzijXlySigSBJ+zf/6ZYMFdiw+stUbNyfg3M51Zg/fz4ef/xxLFq0CEFBQfrSNBCYzWbExMTgnnvuwe133IHB4aMRe7oIn27NwEsfJ+GF/9kzhslAeHpOBSwW9gsS9QcVVVZk5VWq4Oh9cQVYvztbZXd5Wft3/9LHZ/HZ1kwVFBkeNQa33nqryg4lJdIiIiL0NRARUWdxsjUz8lpRUYHKykr90fl74403VLv//vvxwAMP6FNbJhHSu3btQpWnv9YC9KnU242OjsJdV10Bf19v7aBfhXc+W4fdh2P1uU0bNzIaS+fPQnREOAYF+sPTw12fo9G+ocWlpcjIzsX+Yyewbtsu5Bexpjb1Xa6luXAtL1JX/8jJbls8//zzeP3111U0uDQiIiIiIoPxe3vcyrkYv2qePrVlm/7yPrJPpODpp59W6bWJqG1yc3Nx7Ngx7Ny5EwcPHkRBfg4CfV0Q6OeKiSN9ERPhpd13wSB/NwwOcNWfRf2dlLkpq7CgvFJr2m2p1uRxaXkNFk3nxVx9WUFxNfKKqtVtQUk1ikpqtFatSp/lFFQhp7AKgwYNxuTJk1WTILlhw4bpz6aBqqCgANnZ2Th06BAOHDigjhdmJ4s6Pni4meHuaoaPp1kdKwb5uyI40H68MEZq5EZy8jUcuKkdydHvyI1k75MhnsbLNljGWKL+jbGq+mqXsd8xlmm0qDah9nXU/5vQ4Ll1r6etXbtv3/7aKfZbh2Xs9OzZ6v8yv/YJtQvL/5taV+2Nw0NJeCiP9UmN7sg843NVj9X/66jPu8HEfG0/IWon63fkxjG/on1y/Sf7ernY7xgLGs9t5vWV2mXq39Yt3fRnpv7vcN9J+6/2c1f/1xh3aldqrKv2U61dxvH11edqf1j3VH2K8bje59rMMnLjuJxM0O/V3WrzZBljQqN1qf/XLafmG8sayxgLNVA72Vheu6175/X/SDJPgtgqq62o0pq6rbLfSkCMm4cvJk2apNr48eO148UgVR6NiIg6l4uLCzw9PXt34MvDDz+M3bt3M/Clj5kzZSL+/MRjCBkUqP3AL8evn3sFa7/drM+tz93VFTddsQwXz52FEUPD4eftDbO56SsOq6qrkZWbh/2xJ/DBug3Yc/iYPqd3ChschLDgwThw7IQ+hcjOtTQPruWFKlW2pDRsCwa+EBEREVFzOhT48uf3kB2fimeeeQZTpkzRpxJRW1RL/0RWFtLT07F9+3Y1sJmUlARfL2f4+7ioAU0PNxN8tMdBfq6qDQ5wU8+tHTiRG8cBG/1ObS9dve46GWSpG3IxZtXv0rMvIxouVzvBQd0y+r36N7XUY30ZY169lxX6Y8fJxnrlpnbASdGnq//XLVc3kOQ4zc54KDfqI6t9sn5TO9+Y4fBZNFjGmG5Xf7m6RfRpWnMcEMwrqoHValPN4nBrscqgl1UFv6hWY0W1BfbbGhvGRXvDr8GgpuP21G6j/aZOw+m1j40p7fhcHd6Tot1xvK8W0ycY0+u2y5iir0umGPPqNsBB/c/V8VbIXYeXa3Zd8rjeoKZqDg/kpvY59m0zHhn36tZtv21K3TL6HXlNjfFYyplVVFnUrTGwWVVtQ2FJNcaMGaMGM+fMmaMGM6W5uztczEcDXklJiTpeHD9+HPv370dCQgIKCwtRXFysvmrubnK8MMNTa6Lu35uwfxftjC+q/cYgD2WpepObXrSRun8XzS/ZhkUaz2pm2frvTaM9lCmNtt9Bc9Prz7A/sK9L9tm6Bv/w6z/S6RObnOeowQJNLS/7iXpaXWndIm4u9cdDGj21doJ2x2G/KBp9rg00+BgUx9W1+AeonWH/LjbcT4tG6zLoMxo/o7GmtrGhpl67KbVLNbF4s2uoXbf+Plt6sv4em9ocCWgJDg5GYGCgavJ4woQJCA0NVccHGZAlIqKu0ScCX5jxpW9qa+BLgK8P7r52JVYuXojgoACVYttisSA1MxtnU9ORnJ4OX28vRA0J01oo/LXl5QdveUUljiWcwb/f+Qhb9h3U19Z7LJo1HUvmz0RESAjStPfy87/9U59DZOdWmgeX8kJ85zvfaXMQCwNfiIiIiKg5HQl82fjHd5FzKg3PPvusGrQjovazWq3qin5pRgaYvLw8NagpfWomkxPcXU0qCMbDzVk9Z8AMaup35abR9jtocnqjifYJ9nV1/aBmc8vKoKa8pL1p71Zutely38XJCV7OJnhrzcusNXXfCZuzy+DqYmp5ULP2gXHH8XshU+stXY9sQ1MaTW5yOftEWYc9OKnplbXw1KbnNaG57XTU3Os7ql2imUWbXYNat/1zbfbzNCbrH7/j5kgwiwxaDh48WA1kSpP7cvw0Al6IWlJeXq6OFZIJpqqqSgW+yLFCWlFRkbp1pIK+2sFx+YbPbc+62vtcY778++3oc9uipWU783Xbuy5DfHw84uLiEDlrjD6lMVmV437FeJyy54TKFDV27Fh9Tuvb0dbtEu15rsxz3Be397mOjMfG+lp6bkMtrau5ec1xnO94v6l1NdTccxvy8vJSgS7e3t7w8PBQxwyj+fn5sbQsEVE3cHZ2VvtjZnyhTtfWwJfv3XkTblixFIF+vupEIyE5FR+t24ij8QkoKilFUWkpXF1c4Kt9UX28PVWAzNL5s+Ht6YGaGgv2HTuOP7/8Jo6dOqOvsXf46f134MbLL4Gbqyt2HYrFnT/5tT6HyM6tLB8uZQV47LHHcOedd+pTW8bAFyIiIiJqTocCX/7wLnIS0vCPf/xDXYlIROdHSiDJVf3SlyZNBjJlYFPa+Q5qNly2tcctac9zHee1d7CppXnnu66Ovq5oz7ocnTx5UpW4unCwJ7yczfYAF715m53gYTbB2eQEV605a+t00W735JXhzbMFiImJaRRg6Pi6Hd0m0d7nynyjK7gjzzUY95tbV0uae92ObFd71+Wora8jQS3+/v5qMNNxQFPuyyAnUUfIxZ9yrJAgGOO2Je35bjfUnmVbcz7r6m/b4bieNWvW4N1338W4K+Zg6Jy6AJb6ZHn738/OCcm7jyPuk5249tprcd111+nTW9cV76G9esPfQPTUuhyXlcFWOS4wwIWIqOf0icCXhx56CHv27GHgSx/TlsCXZQvm4CcP3IkhwYPUCfuJxCT8+SV7EEthSYm+VH2S9eXWlctx7fKL4amdSFRqPwg+37RdW//LqGjlx0F3+t33H8K1l16s7u88eJSBL9SIUeqoPYEvL7zwAl577TUGvhARERFRIx0JfNnw+3eQe/ocnnvuOVVvnog6l5RDksZBzfbrqW2Q5zp2kzqu6/PPP8fq1atxQ6QvloX62ANctCYBLi7aYuYmXvejtCK8eiYfy5Ytw913361PbV1nfY6iJz/LztJZ62rveozlZTDT1dVV3SciaooEvbz00ksYe9lsTLh6gT61dcfW7lCBL+zvJSIiOj99otQRA1/6ptYCX9y1H4t//8UPsHDmVBUFey4rR2VuWbd9t4p2b0l4yGD86L7bsXTebJjNJmTl5uHJf7yEDbv26Uv0PAa+UGuMwJdHH30Ud911lz61ZQx8ISIiIqLmdCjw5Xf/Re6ZdHWe6ZhanYiIGpOr+SVD1tXhvrgnum19lJ+eK8aLp/Nw+eWX4/HHH9enEhFRf/P+++/jxRdfxOjlMzHp2oX61NYx8IWIiKhzGIEvvTr3VjMxOdTHzZs2CRNGjVBBL9U1FmzavR9b9h5sNehFpGVm4/0v1yM7L189DvL3x+I5M9T9zhTg64NbrliOP/7gETz/5I/wz6d+jBe026d//F3ce92VGB4xRF/SbkLMCDxx7234+UN3YeyIYfpUIDx0sJpmtMsWzdfn1CdBQD994E48+/PH1WsZr/fMT7+Px++6BTHDhupLUr+gXzXEfRwRERER9RSb1X4uypTcREStk45UUdWO3/GSDUZI5h8iIuq/zGazujXOr4mIiKhnsIeLut2MiWPh7+uj7ucWFOLLrTtUZpi2OhgXj1NJyeq+ZH0ZHzMCwUGB6nFnmDQ6Bj++/w7ce91KXLZoAZbMnYmLtbZk3ixcunAu7rhqBZ6451bMmlSXDnzokFCsXHwBrr7kIoyIitSnAqGDBqlpRps2fow+xy5scBC+f+fN+MHdt+CaZYtxyYI56rWM11t2wRxcc+lizJnMmvv9kdVq1e+1rjPTBBMRERERGeeiPM8kImqdEfhS3Y5BTRd9/9pamSsiIurbjEBym6Xtfb1ERETU+ZjxhbpddGQ4nPUo6LTMLMSePK3ut1VZeQVOnk1BjZ4hJijAD9ENMrB01PiYaDx623VYdsFcDAkZjNKKCmzdfxhvfPQ5vtm+G4XFJRgcGIAFM6bgvuvrMr9UV9egsKRUm1+Kcm37DFXVVWqa0crL68qHSdDLY7fdgBsuW4ox0cPg5eGOjOxcbNt/CO989rW6zc4rgI+nJwL9fPVnUb/AXRsRERER9TT99zYzvhARtc7V1VXdtivwRc/4wsAXIqL+rTbwpR0XORIREVHnY+ALdbuQQUH6PeBcZrYKZGmv5LSM2lSxnu5uCArwV/fP1w3Ll6rsKh5urkhITsXTr76ltdV47aNP8Owb7+CZ197GuaxsuLm6YsbEcbjkgjnqeQePx+Opf7yEn/71Be3+STVNJKakq2lG+3DdRn0OcP3yJSrDi5RVKquowAdffauW+csrb+Hl99eq2588/Rz+8/FnOJ2Sqj+L+gX9olru44iIiIiopxjnosz4QkTUug5lfNF7XVnqiIiof3N2dla37OslIiLqWby0i7qdq95ZYLFYkJ2Xr+63V3llJawOVygaGWTOx8KZU1WToJaikhK89/k3+HLzDsSfSVKZWBKSUvHV1l34WmtVVdXwcHfDBdOnwF1bPie/APtij2P34VjkFRTqawRKysrUNKMlpqap6TMnjsOKC+fDx8sT1TUWbNi5Dy+9v0Ytc+LMWZUJR253HYrFW2u/xM6DR9XzqH9pz48hDkgQERERUafST0XNnfBbioiovzMCX6ra8TveKHXEwBciov6trtQRA1+IiIh6Uq8OfAkODla3TjamiOuPJHClohele100ezqCgwLU/WMJifh88zaUlperxwZ5vPvIMRSXlamkHRGhIRg7Yrh9ZjtcOGsawkPt32/JevPaB58gJT1TPW4oKzcPuQ7BNNT3Oelluvz8/NQtEREREVF3s+lZCxhgTUTUOjc3N3Vb3Y4uSqPUEQNfiIj6NyPwxcpSR11GLqIuKyur12RaV6msrKz3WhUVFQM6o498BqdPn8aWLVtUS0hIQHmDsTMiot6gVwe+REVFqVuTtUbdUv8iVxb6eXvrj3reqOFD1TbJCWpNjQWXL1qAO666rFGbPCYGNfpJlZenO4aEDFb320OCZVycndXJ0tGTCTiRmKTPoYHAZLV3eg0e3P7vDhERERFRZ2CpIyKitqvN+NKuUkf2/WtVL7roi4iIOp+RQdEILKfOd/bsWXz/+9+vbX//+9+Rk5Ojz+18mzZtqvd6a9euRU3NwBunLCkpwRdffIGf//znePLJJ/HMM8+o9tRTTyE1NVVfioio9+gTgS9OFga+9CfV+gmCyckJQf4dy3jh6+OtPd/+9a2sqkJRSam6fz6MIBzp+J0wagTuuuaKJttVSxfBX3t9Ye5gmaVBAf7q1mK1Ij0rp0ujk6n3MdXYA1+MrFZERERERN3NCHwxrlAlIqLmubq6qtvq9gS+9FCpo5oDW1D1znNtb2teha2EmYaJiDqqttRRN2d8OXDgAB599NEm29GjR/WlWrdnz54m1/H0008jOztbX6pnFRcX12YbkXbo0CGVhaWrSFCH4+udOXOmRzL6SKaVl156qd7fZf369frcrlVUVIS3334bL7zwgnrN/fv3Iz4+XjW5X1p6/mNyRESdrVf3cEVERKhbJ2Z86Vcys3P1e8CQkEFw1zsP2mNoWAhcXZzV/aKSMsR3QsYUxw5fb08PBPj5Ntukm0PKNEnQjcXa/qAVZ2c9Ctxmqw0EooFBAvmcbPbvTEhIiLptC16JS0RERESdyeiY53kmEVHrjIwv1e0oc+CidzN1d8YXa2YqLCcOtLlZTx3VNrJSfzYREbVXXcaX7g2MyMzMxLfffttk2759e5sCL+UYtWPHjibXsXfvXhV4QT1H/oaHDx+u93dJSur66gES5LN582a88847KuhnIGa7IaK+pfbiLvX/Xio8PFydNDhpO1ljoJj6PglSqa62HyjDQ4Ixd+pEdb+tgoMCMXHUCPXdkC/y2bR0ZObm6XPPn2Rh+Wb7bnzvd8+02n78l+ex7+hx/ZlErTNZ7D84PD09ERAQoO63hbHTJiIiIiLqDMz4QkTUdrWBL+3I+OLcQxlfiIioe/XGUkeSxaUt2VqysrJU9g4iRwUFBdi4caMKrjJMmzYNv/3tb/Hcc8/hr3/9qxq/JSLqLYyLunp1D5ePj09tKRATs770G9v2H0aOduAUUjJo5eKF7cr6snjODIwYas8GVF5RiV0Hj3ZKqaBivVySlGAqLC7Bxl37Wm1b9h5ERk5dBpu2Ml5LToqDg9oe/EB9n8lq7/AaNGgQnJ3tWYuIiIiIiLqb0THPwBciotYZpY6q2jGo6Wa27197PPDFyQlOru5wcvdsssHNXS1DREQdU1vqyNL9pXCaExsbq0rStEQC4Y8cOYLjx3lhL9UnQVOSacbR1VdfjcsvvxxLlizBsmXLEBgYqM8hIuo9enUPl5wwjB492n6/qlzdUt8Xe+q0ypJi0U4EJfBjztSJuOmKZfrclk0aPRJXLrkQ3l6e6sTsdHIqvty6Q597fpLOZah1yvduxNDIDpVgaqva13JywviYaAyPGKLPof7OXG2vPTpy5Eh121ZMQU9EREREnYoZX4iI2swIfGlPxpeeKnXUiNkZ5gUr4HLtA023y2+Hk7efvjAREbWXcT4t5WF60qRJkzB06FB1v7i4GAcPHkRlZfOl7MrLy3HgwAGUltov0p01a1bt82lgq6ioUNmADPK9GD9+PNzd3dVjGdczMh0REfUmvb6Ha8GCBerWubIUTnrHHPVtZeUVeOPjz5GaYU+TFuDrg9tWLse9118Jf+1+cy6YMRXfveNGjB05XAWMFBSXYM23m5GRXZdx5YrFF+BnD96Jnz5wJy5dOFef2jZH4k+hTDugizHRUa0G4yycORWjhkfpj+pYte+pkTbcxaXpjB67D8eiuNReH3NY+BDcsvLSZgNtZLrj5yKPp44dpVpXBudQ55MyR0bgy6JFi9QtEREREVFPMH6zMMCaiKh1tYEv7eib7DWljpxMMIUPhzlmUtMtehzgwv4lIqKOqg0A6OHxK7mI3DFwZefOncjIyNAfNZaWloYdO+ouKpbABilxQyS/FWtq6qpw+Pn51Qa9EBH1ZuanNPr9emSn1hnlYwySFkva9OnTMWPGDH1q66TU0aZNm1BUWACrszusZntNXeq9IkJDsHT+bHh7eqBa+x5t3nMA8YlJ+ly7vIJCWKxWjI6Ogo+Xp2oxUZEYM3wYIsNC4KkdREMHByE8JBgLZkzBNZcsxtWXXISJo0fCzdVVBc98/M0mvPfFN7XBKuJ7d9yEpfNmI3poOOLPJOHwiVP6nNZl5+Zj4qiR2vYHq9eQLCx+Pl4oKStDdp5emsnXBxfOnIZbVy3H8oXzkJyWjoTkVDXPMHHUCEwZO1o74TXBbDIhIycPCUkpGDtiuHpvEqgj64uOCNdeIxyuri7qNYODAlXQTKa2vPzbCx0UhJUXL8T1K5aqAJfjpxPV+h++5TrccsUyXKB9LoO150gQDfUNLpUlcK4qw5gxY/DAAw/Aw8NDn9O6ffv2qQj8KVOmqEZEREREZDB+bw8eHYngMZH61Jad/HofaiqrccMNN7TrvJSIaCCSIMHVq1dDQlluGNq27Cgy/PleSqEaPLrlllu6LcOWJeEobKln9EcayfgyYRZMgfZy8q2xJh5HTeweWJNPqWZLS4STbwBgMsOydyMsezbAcmSXpDaAKSQCtooyWPZtgiXxRO1zUFIIU3A4rGlnULP9S1gPboP1zHGYIobDydVNfyU7W3kprMf2qHVYD+2A5ehuWOT14/arbUFZMZwCBsPJuek+YcuxvbDEH6rb3vQkOA0KAyrKUbNrvdpma+xewMsXJv9B+rOIiDpPZmYm1q1bB+9B/oiaO06f2rrs+BStpXa4vzchIQFff/21/gi44IIL4OnpiaNHj6rHRUVFmDBhAmJiYhoFu0t2mo0bN+LTTz9V92WZhQsX1ltfSEgIli5dCn9/f31KfXJ8y8/Px549e9Tz/ve//6n1ffnll6p8kmQMkWAJCZpoLdhesqNJ2aXPP/8c7733nlqP/L4pKytT25GXl4cPP/xQX7rpbZPXPHbsGM6ePauaBP0MHjwYzs71L07OyclR22wsl5qaqtbj5lZ3fJJsOY5BQZMnT8bcuXMbrUvI5yDvVcYxP/roI7z//vvqM5Dtl0Aief9eXl4duuBAMvZ8++23SEy0jw2JefPmYdq0afoju6SkJBw6dKjRe5LA3TNnzuCTTz7BO++8U/u5SlCufDZGYK+Q15IxCPleSZmsbdu26XOgvldhYWHqfcr65X3J8x3PbTrz+0BE1F4ShOri4tL7A19khyo76Vh1sHZCjZunfQb1Wm0JfJEAj5SMLBSVlCIqPAz+Pt7a8p7q/ujhQzF13CjMmzoJC6ZPxrxpkzFt3GgMCbEfSHPyC/D2p1/hvc/XISOnLttL1JBQ3LZqBUIGBan1rv7kC6Rn5ehzW1dSVo7S8goVjBPo5wtfby/EDBuKyWNGqewuyxbMxeWLFmDJvFmYOWmctowftu8/3Oi9OTmZsEDbZinH5K6dLI0eHqXKOS1fOFf9o9t16KgK1jmTmoYRQyMwJHgQvDw8EB0ZjgkxI9R7lmw1KxbOw+I5MzFhVDQSU86pABfJMPPorderrDcSGBTk74e9sceRW1Covzr1VpKxyq0sD05WC2666SZ1otwe+/fvV42BL0RERETUkPF7uz2BL/Ff7oWlioEvRERtIf1Rb775purPujmq6QHAhkxwwvspReo50g/Q1GBZVzjfwJeaQ9tVcIusQ5o1IwXmIcPswS0SwCLTs1JVMIp55ARIkEvNuv+pIBXjObDUqCwylg0fq+2xZiTDVlwA58lz4eThZX8hmxWW4/tRs+UTWCTIJekUrJkpsGWfgy0nHdacc7BmaU2eq63TydMbThK40mCwrGbrZ7Ae3V372rbcTJXhpmbzp7DG7ob1XCKs2WkwR42CKaxx5mYiovMlgS8y0O85yBfD5o3Xp7auswNfJHAlOjoa69evV49ljE+CE2bOnKnGJRxJUIwEJsTFxanHF198sdoGCVQwtBT4IoEqEujx73//W23D7t27VcCNbJMEWpw+fVoFoezdu1dtR2RkZL3AEkcSiCLBLnKclWATCYCR9cg6ZPsk6MXb21sFUBia2rYNGzbglVdewa5du1QrKSnB7NmzG72uBG787ne/q10uPT1djVv6+vrqS7Q98EU+BwlMefnll1XwkwSOnDhxovYzkO2XzyUgIABDhgxpdxBsWwNfJOjl2WefrfeeJOhJ/i7PPfcctm7dqn4vGp+r/G1yc3NVwJOMwQopfSVBvmvWrFHrKyysG3OS0kfyXPl7yvrlM5Xvi5HtqDO/D0REHWEEvvT6UkdiyZIlamPN1WUwWXq4Li51mvzCIny2cRt++eyLWPPNZpUFRb6YkvlEsqNMGDVCtcjQYHi4uyFPW/6b7bvx5D9ewjufrVOBM47GRA9TgSAiITkFx0+fVffbY+fBI/jDi//BniNxqNAO1hIAI0E3yxbMwaUXzFEBMNFDI7QDfSXWbdulLXdMf2ad2JMJ+HTjVhV846y9HwluuWT+bEzV1iPrM5xMTMZfXlmNTzZsVe/Ny9NDe9/DsHjODLX8vGmTEBY8CAWFxTinB/Dk5OWjuLRURc9Ks1gtKC6xl0yi3k1KHJlqqhAeHo7ly5frU4mIiIiIeobNalW33ZWBgIior5M+K/ues21MToCLvovt8XJH7SAZXGwlhfWa5cQBWI7sgK0w1x7UIstZ9QsmteOJrbSo/nPys1Czcx0skv2lskIuA1eBLupWSJ/WwW2o3rgGlvjDKlgF1ZV184Xc16bJPMuJg6hZ/6EKommkrKT+a2ut5uBWFVQj92X77K/vsG4iok5kDP7brD27n5HtkGCHsWPH6lOggjekpFFDycnJ2L59u/4IKpDCCIBojQQ5SIDMP/7xD5U1RrKDSPCKBDQYJGhCAkwk+4cEhUi2EQm2aUimSYaUt956SwW8SFYQYz0SuCKBE5LpRYJ0WiPLy7YYLTs7W2WzaUi233G5c+fOdSgJgPE5PP/889i8ebMKTpFtMMh9mSbzXnjhBRV4ImM6XUGCVhzfk/zNJWOLvK4E40j2G8fP9eTJk+pz3bJlS+17l89KPjN5vmSQcSSBLxLAYqxfMr4Y76Uzvw9EROerT/RwSVkQOfBKpgTniroDB/VOJxOT8Itn/4XHfvMX/PCPf28yOMRQWFyi5v/r3Q/xk6efw6+efRFvrvkCW/cdUtMlEOXdz9fh9/96HT/68z/wjzffUxlksvPy9TXUkWAZTw8PVFVX42DcSVUOqb0k64tkZPnzy2/ip0+/gFf/txabdu/H3qNxKuOKfVtew4/+8hz+/d7HSM9unFFG1vHOZ1/jF3/7F95a+6V6D7KOf7/7kZruKPbUafzrnQ/Ve3vurffx6Yat6n3vOhSLD7/eqF7r59pnuWXfQbW8BMi8pL3u11t3qfa89pzsvDw1j3o3c2Wp6mSRyHuJSCciIiIi6klGRyUDX4iI2sYoB2Bpx6CVi56dpEcDXyzVqNn8Carefb7JVnNgq75gMyw1sJw8BFt52y+8suVkwpqS0GywieVMHGq2fwVbVpo9MEVon5VkdDGPnwnzqMlw8vavy+5itcByLhE1Wz6DNSfdPq0ZtspyWOMPAzV9J9iIiPo243zaCCzvKRKAEBoaqrKcGFJSUlT2DscAEAl0kJL6EuQgJFBm4sSJbfpdIOuRgAoJXjh16lRtcMPQoUOxatUqPPLII7j++usxevRoNV3INkigg2SicQyGkHVJYI4EvkjWHIOs65prrsEDDzygLiCVY6hkCulN5LeUZGeXz0GCc+R9SXadu+66C3/5y1/wpz/9Sd2XaTJPgnreffddFRDSHSRw5b///a/azptvvll9lrNmzdLn2kkmHckEY2R2kfJDgYGBteWxHEmGUPmbyjxpkoFHdOb3gYioM/SJHi6p+yZpy4RzZanWGPzSm0lwxpa9B7Fu+25s2LWvyeCQhpLS0rFt/2EV+PHaB5/gr6+9hT+9/Cb+8spbePn9Nfjom40qGOZUUgpqmom+lcwqzs5mFUxz6PhJfWr7yfolIEWyy7zx8ed45vX/1tuWj7/ZpLblbOo5/RmNpWVm49ude/HqB2vV82Qdq9d+ibiEupR0BlmPrO+dT7/GC2//T73Wn195Ey+++6F6rZ0HjyLToaSTlFd6bvV7qm3efaDZz4N6D9lnOVeXYdCgQVixYoU+lYiIiIio5xiBL6yvTkTUNkaZiKp2XNHvog8i9mjgi9UKa/IplQGlqSblhVpktcBWUgSnQWFwufQmuN74KFyuvMde5qgZkjVGXtc8ZR5crn0Irtc/DJeLVsHJ3VMFpFj2b4Y1N0NfWjsWmcxwnroALqvu0pa7Es5LroHLVdprjJtRF/yiHbesaYkqU0xzATWKtn5bWTFMEdFqfWp7L78dTqFD9QWIiDqXkfHFMbikJ0gmDynFI6WNjFKmElggQS7FxcXqscjPz1dZQAwSKCNleNpCnvv555/XywgiF63/8Ic/xIMPPqhK+91777346U9/iksuuURfwl4OSjKMpKam6lPsJY6++OKLekEvsq4nnngC999/P2699VYVOPHQQw/Bx8dHX6J3kKCRtWvX1n4O8nnL9t5xxx0qWEfGAG677bbaz0D+DpJdJTY2Vj3uapJNRcYifvCDH+Duu+/GLbfcou5feeWV+hJ2koHF+Pwl44+8h5///Oe4/fbb1TSDfD/k7yDzpF1++eXqvKgzvw9ERJ2h2wJfvLzs9VslBVZHSJYEqTNostbAtawA5qpyfQ71J1JeSAJlpExR7MnTOJZwBqkZWSqLSkukPNLQIaGQn8ISSHI0PsE+4zxIQElmbh7iE5PatS0Geb6UKJLnyTpy8lv+7kvAUKK27eq1Tp1B8rmMJl9LPqOE5FTV5D71blLiSPZZkrFKoqtHjhypz2kfOYkUjrVGiYiIiIg6TB8zZMYXIqK2MTK+tC/wxX4rV+H3ZU6+gXBZeh2cp10A89jpcJ44G6aoUfrcpjjBefI8uCy8As7jZ6gAFvPEOYC7B6xZabAmnawXvOIUPhzOCy6DOXocnAYPgSkkUgXWuFywAk6BwfpSGksNrAmxsJWX6hOaZgodCuel18N50lz79mrbYtLWS0TUFYzAF/RwqSMje4ZkcJk8ebK6L6SkkZQ2Mkj5HclWIiRgY+rUqeri87aQMjY7d+7UHwEBAQEquEHG74YNG4agoCBERkaq4BvpCx8xYoS+JBAXF4djx+qqA0iGEAm8MMi6rrvuOrUuyRgigRvyfAnWkGCS3kTK9kggi0E+70svvVRlepfvgwQgSfad+fPn60vYy/0cP36824JhL7vsMixYsADh4eEq84xk9ZGAFfmcDRLAY2T+kW2WzCxTpkxpNIYh47tSmUPmSRs+fLj6HdmZ3wcios7QbT1ccpASksaqI2QHKRGCsuM1WarhVpanBpKJRMywSAwK8NNOGmpwOD4BhQ61FIl6ipPsq0rz1D7r6quvxhVXXFHbUdZe6en2VL6yLyQiIiIiOl82vWOegS9ERG1j/J6vbk/gi56tpEczvmjb4OTqBic3j6abi5u+YPMkCEVleNGWV5xdtHU2P0jq5OkN87QL4BQUKgcatQ3quSYzrOeSVEaWWk4mmMdO05ZtXBbaKSQSpiHD9Ud21sI82PLtg3RNkvWNnwXz0Bi1nYr2/uHSsf4YIqLWGIEvxvl1T5OxOAk0MEhgg2R9kRJHcjyS+8ZFlhIkI60tWSAlo40EOhjPFVL2Rl7Lza3+sUR+Y8h6Zb6hoqICZ86cUdsg2SflvlFmR0h5nRkzZjTqP5dgCscAkp4m237y5Ml6n4ME6pSXl6v3ZDQJMKqsrNSXsJMApIbTukJUVJQKUHH8LOVvHBYWpgJyHJWVtb2UoaPO/D4QEZ0vI6txt/VwSUShcEx51V7R0dH40Y9+pKILTTVVcCvpnnp41PslJKXgF8++iO/9/hn876tv9alEPcdJ28m6a/soU00l5s2bhzvvvFPVyOwoI+WgEURIRERERHRejE4BBr4QEbWJUeqoXYEvJvtAYo9mfDE7w7xgBVyufaDJ5jx5rr5gM7Tnm4aNqQsiaQPJ0mIKidAf1WcryJbRMv2RRlu/lFFqkskMU8N5UspISik1w8nNHabho+UAp08hIupaxvl0T5c6MsjxSgJIHAMcpLSRBChIEIxjlpU5c+aoLCVtIRllpDyRo4iIiGYzlEs2mYbrLi0tVZ+TrCsrK0ufaicZQprrP+9NWdBl28+dO6c/stu1axd+97vf4amnnqrXXnnlFX0JOylHJQFIXc3Pz6+2Cocj+RwbXlhrDBa3V2d+H4iIzpcRwNltvwCMnakcWDta7khIlKLUkhPOVeVwK6uLJqSBKzMnDxt37cP6HXtUqSOiniTZqNyKs1SZIznJfPTRR1VKwfNhBL4w4wsRERERdQajg7MtV3cSEZFjxhd10ya9I+OLCabwaJhHTW6ySWmhFpnMgKe3/qBtJPgEzWSSsVU3CAKSz8jsrD9ogrunfsdBS4N0ko3Go33bS0R0PuoyvvSeAXwpVeNY7khKG8lF6adPn8bRo0fVNMmkMm3atDZnKJffD0Y5JYME2TQXSC+fiwQ7ODJ+g0iwQ8OgUCm3VFs2qhdratslk8vevXsbtYalfDoaZNJZ5O/V1r93azrz+0BE1Fm6LfBFIjVlhyo/9Dpa7sggdeiuueYa7Z4NzhXFKqsCyx4RUW9grirX9knZcK6yX3304x//WJVoOx8SjS/R4LIPdazBSURERETUUUbHPANfiIjapjbjSzsGaYyML0zjX8ep0YCY9nm28JnaSov0ezrtuOUkwTgt4bGNiLqRMdDfW0odCbkY07HckfQvx8XF4cSJEygutpebk7IzEiDTHg2DGiRwobngBclsIhk9HDUXFCFaWldvD5BYuHAhvvOd77TaLrnkkk4LPOkNuvL7QETUEd22V5GduZGm7OzZs+q2o3x8fHDHHXfglltuUQEvzpUlKvjFXNP1tfGIiJrjUlEMt7I8FfwidSyfeOIJXHTRRfrcjsvIyFCR5BL00p9OjImIiIioZ6jOSL0/kp2NRERtY/web1+pI/stA1/qOAUES/SL/khjqYEtp+nszTaLBdbM+hdQSjYZJ19//RERUc8zzqdtlt4TnCHZNaZOnYoRI0boU4CtW7di06ZN+iNg9uzZ7couLgGgDcvwp6am1gbSNCQXcsp8R/J8WY+zs7Ma53MkpY/Ky8v1R3Xkt0tHLqZvLgijrKz5cnltIdsvgUWOpEzTtddeixtvvLHFtmjRIjVu0B905veBiKizdGsPl1FTMDY2Vt2eDykbIoEvP/nJTxAYEABzVRlcS/PgXFk/YpCIqKtJAJ5reYFqppoqjBkzBr///e+xcuXKTglUkRqswrEuKxERERHR+ZBOYMn2wsAXIqK2MQZmqpoYRGuOkfGlYUmEgcw0JApO7g6lDqxWWE8ega28cZ+uLSMZtvQk/ZGd06AwOPnZL64kIuoNJIhD9KZSRyIyMlIFvxgOHjyosr4IGV+Teca2t4X8boiJialXrubQoUNqnQ0DTORxfHx8bb+2kIs6pd9c1iOBOWFhYfocOynHJGOHDdclATEStNMab+/6Ze7S0tKQm5urP7KT47FR6qmjZPujoqL0R3byGRQWFqr32FyTYBlp/eX3V2d+H4iIOku37lFmzJihbrds2YL09HR1/3yEhISoske//vWvMW/ePJirK+Balg+XsgLtfjmcGuxciYg6k5PNCueqcnhWFsGlvAhm7fHy5ctVpheJ3vb0bKIOdTtJhPRXX32l7jumpyQiIiIi6iijI5JljoiI2s4IfGlfxpdeUOrIUgPLrnWoXvt6s80Su0dfuOs5DR4Cp4i6DATCmnYG1eveh/VsPGwlhbAV58MStw/V6z9Qj2uZXWAeP1P7YPvH1fJE1D8YA/e9LfDFy8tLZXUxSMaNiooKdV+CXqKjo9X99hg1alSjEkqvvvoqNm7ciLy8PJVNRQJAZAzwlVdeQU5Ojr4kMGvWLBXoYBg7dmy9jDSy7Ouvv66eK+uQdZ08eVKtf/v27fpSzZNgHkfJyclYs2aNupV1yfq//PJLfPzxx/oSHSfvQ0pFGSTY480331S3jsd8+d1VVFSEHTt2tCl4p6/pzO8DEVFn6NbAFyn5IamrJEJTdvSdQaIJJejl0UcfVUEwJks1XCuK4Faar7VcVXpEphERdRaTpUoFurgXZ8O1LA8mbT8zcvgwPPjgg7j33nsxZcoUfcnzt2vXLpw+fVrtOzujbBIRERERkU0ftOXVdUREbdeRUkfOeoBhjwa+WC2wnDmOmiM7m23Wc4n6wl3Pyc0DzvOWwSmgrjyCrbJCBd9Ur3sP1R+/iqo1r6F64xoVCCMZYRTtszSPnADz2Gn2x0REvURt4EsvKnUkZLskOMMxQMMwZ84c+Pr66o/aTvqopWSPY8CKZJL5+9//jp/+9KfqgtAf//jHePbZZ7F37159Cajlr776apXlwyBZU+TiUUeS9UWeK+uQdf32t7/Fp59+qs9tmWS4cXyvEuSzdu1aPPnkk2pdP/vZz/Dvf/+7UzK0R0REYNWqVbXZTiTAY926dfjd736Hxx9/HN/73vdqm7yXv/71rzhz5oxatj/pzO8DEVFn6NZeLinTYUT/yUGgpqZG3e8Mo0ePxt1334277roL0yZPgrO1Gs6VJXApL4RbSY7KBCPlkMzVlXCydN7rElF/ZlNljCR4TrJISSk1CahzK8lV+xbZp0ybMA633nyzOoG75pprVD3PziRR6NJBJvtOljoiIiIiok7BwBcionary/iibtrEtTdkfBHSF1qjbUMzzWax6At2D/PQGDgvWlW/ZFFVBaxpibAkHIU1IRa2rDQVtKNI0MuI8XBeeAWcvP3s04iIegnjnNrayzK+COlPliAXRxJ0MH78+A79FpDSSJKp484778Tw4cPVNBnnk8wsktVjw4YN2Lx5M06cOFFb5k/K4dxzzz2YPn16vdeUbOkSPOJ4sac8R54r65B1SWkceZ2bb75ZX6J58l5XrFhRr/ROdna2urBU1iUZVyRQ48orr9TndpybmxuWLl2KW265BT4+PmqaZDY5cOAA1q9fj6+//lo1GQfdtGmTygTTG78f56szvw9ERJ2hW/cqkkZZDmKyM5MdvUT+dSaJEJXoQomi/MEPfoAlF1+MkEB/VQJJMr+4leXDtTQX7iU5cCvOhltpnhq8lsHstjYXvTU1r+VW0mwz1lm/yfS61tTzGrfi2tbw+U03Wc6haZ+RY3Nu0Bot37DJMu1pnbGO8gatqWUaNMkG5Kr97Y1b+317Mx47NmNe3TqK6rfy1lphE62p5YzW1PKtN1e9NTWvo81YZ8PW1LL1W0H9VlbXmlqfq7ZMoybLOjTHddiblDXT/oZNPVeatkz9pi3b1iYZo7T9hGR0cS/R9hWyz5DvizZPvgODvD1w+aWXqGCX73//++rEW07U/P399b1R55CamHKyLPtM2XcyFT0RdaWtubFYl3Wg2SbziYiof2CpIyKi9jOuEK9qR2l1F73ntccDX3obZxeYx86A64pbYZ44G06uzZQu0o5TToEhcLnoKjgvuRamIVH6DCKi3kMG/5V2HB+6i7u7u7qg0jGzxrRp01TGko6SEkoS9CHZPORC0MGDB+tz6pMMLDJeJ33oS5YsUc9zJL9FpNzSww8/jOuuu67ReiSA5dJLL8UjjzyigitaI8EosrwEYchrO3JcV1MZcDoiODhYjQvIeOTcuXPrBdw4kvcl71/KS/VHnfV9ICLqDE42o8erAUkDVllZqT/qPJLy6+c//zkOHz6sdoKSXqwrlJaWIjMzE+np6ar+n7xebm6uqqdnvC+bk/brU2u2dnX2Gcv2vpOYvqHuc9N+urbhU2xliQazW/tTyuJOHY2sbS76tH2bqHRu97LxCu1ZaysbXWuAft+13aL6dmq3fn5+KqBFUj/KrUQkSykj+XEgJ7fNndB2hj/84Q/44IMPMHnyZJUmUaLgiYi6ylspG1BcU64/aszH2QO3Ri7WHxERUW/yxhtvqDZu5VyMXzVPn9q8mooqfPzIc6oj/IsvvtCnEhFRS5577jl8/PHHeCwmEJeG2q/ubs2/T+fhk3PFuP/++9VgT3ewZiTDlpupP2obp6AQmEKHqvuNnm8ywxQ5ovlMK1WVsCQet2eP0cmypqhR+qMWWC2waq8lr2crLYItPxu2kiLVB2cKDIaTT4DW/OCkbZuTp7f+pPqsSSe15xTqjzQSVDN8LNBcMA0RUScrLy/HZZddBhcPN1z5/KP61NYdW7sDcZ/sxB133KFae2VkZKhxL4NcGD5q1KhGWTQkE4lcYCljfkIyc4wcObLRcgUFBdi9e7f+CKpffNKkSc32SUtQp4y/nT17Vo29SZNpkiEtKCgIISEhGDp0KMLCwmA2m/VnNSaZUNLS0lS5/5SUFJSUlKjfKfJ8eT+yDhlXbMu2yXCnZHk5deoUkpOT1XuS7ZFtkKoR8hnJ2GFr60pMTFRZSwzNfbaiuLhYvZZse35+vnpNIe9BAo4CAwNVNhoJ/GjvWIJ8nrGxscjKytKnQG2HkV3F0PC70Nzn09T6ZOyhYab59n4XRGd9H4iIOkL2NbKP6vbAF/HJJ5+omm6SVkyiIZcvX67P6Xzy9mSnL0EwcgIi70sO9BIAYzR53NqVbsZ84+NquHxbn29wfCzrPJ/nt1V71+E4v6ltbM/zRcPH3fG+Gy4vmYakRcxow49vjTxftjN130mV/k/a+W6zsU7D+a6vLdq7DmO+sZ0dfb7B8XFb/u6iva/ZUHuf7zhfTrwkyEVO6CRSXE5Spcl9OVGVfVdXkxSAv//975GTk6P2kytXrtTnEBF1DQa+EBH1Xe0NfKkur8SaR59XnQKfffaZPpWIiFry73//G++99x4eHBGAK4b46lNb9npiAT5ILVSl2W+77TZ9KjVJSi5VlKmSR5ALsTy84OTm0fyFaEREvYSMo8kYl7ObC67653f0qa0738CX3kL6+6W8jYy/WSwW1bcuAR6SCac9ffoSACPrkJI48lz5rdLRAAnZJhkLlCbrkHXVZubpIrL98l0wAozk9eRzkNdv79hGX9ZZ3wciovaQ7Jyyr+mRwBeJ9PvHP/6hauoNGzYMP/3pTzFjxgx9bteTA6e8N8fWGmOHbHxc7d1Bn+8OvTMOCOezzfK+u/s9i/NdR8Pn//e//8U777yjOoQjZ47Wp7YsZW+8OgG96aabVM3G1nT2NrfGWL6j303R3dvc0Plsc1f8m5TIbSPQpSdIRLnsFyUy/ZJLLsF9992noqKJiLoSA1+IiPqu9ga+VJVWYO13XoC3t7e6MIWIiFr3+uuvY/Xq1bh7uD+uiWgm+0kDbyUV4J3kQtx66624++679alERNSfyCC/9OGaXZ1x9b++q09tXX8JfCEiIuppPZrxRcjArpTxSEhIUKm0XnrppS6PuCSS75lcodPWDmFhnIA+8MADKjUtUVeSKOjHH38c27ZtU/VXH3300UY1SYmIugIDX4iI+q72Br5UlpTjk+/+U5XzXLNmjT6ViIha8tZbb+G1117DbVH+uHFo2wJf3k0uxOqkAtxwww2qX4mIiPofGWK7+OKLYTKbcc1L39Onto6BL0RERJ3DCHzpsVyRUoNOBnS9vLxw9OhRlQGGiGigkyvIdu3apep/3nvvvQx6ISIiIqLOZ+14tkgiooFK0meL6qavIWySi8m+n62urla3RETU/xjn1FLqhoiIiHpOjxZJnTRpkopklROCtWvXYv369focoq7RTIKjNjmf5xK1hewD33//fZUeU8obxcTE6HOIiIiIiDqP8dtGSnwSEVHbyFWEokoPHmwLF30wVMquExFR/6XOqzl+QERE1KN6vJdr2bJluPzyy1FSUqJK0EjKUCn1QUQ0UEigy7PPPqtKceXm5uKaa67BokWL9LlERERERJ3Lpg/aMvCFiKjtajO+tCfwhRlfiIgGBLPZrG558SwREVHP6fFeLh8fH9x4441qoPfMmTN499138Zvf/AZnz57VlyDqPOeTyptpwKkr7N+/H08++STWrFmD06dP47LLLsN1110Hd3d3fQkiIiIios5ldMjzNw4RUdsZGV/aE/jiqge+MOMLEVH/ZgSU2ywsd0RERNRTesXlXUOGDFEDvY899pgqe/TVV1/hj3/8IzZv3qwvQUTU/3z55Zf4+9//jnXr1ql937333oubbroJwcHB+hJERERERJ2PpY6IiNrPyPhS1Y6r+ZnxhYhoYDDOq6WPl4iIiHpGr+nlkoHeSy+9FE888QSmTp2KvXv34l//+hf+85//4NChQ/pSROfnfFINMk0hdQYpa3TgwAG1b3vllVdw7NgxREdH4yc/+QmuuOIKFQhIRERERNSl9GwFzPhCRNR2dRlf1E2buOg9rwx8ISLq34xSR8Z5NhEREXW/XnV5l4eHB+bMmaOyHixduhSnTp3CO++8g2effRb/+Mc/sHXrVhQXF+tLExH1HRkZGfj666/xhz/8QWV5kX2blHS74IIL8Oijj2L+/Pmq9BsRERERUVdjxhciovYzMr60p9SRix5gyFJHRET9mxH4YmWpIyIioh7TK3u5YmJicOutt+LGG29U2Q8kI8JHH32Ef/7zn/jTn/6Ezz77TA0Y5+fn688gapvzuaKRV0NSWxUWFqp9lGSr2rRpk9p3/d///R9efvllfPHFF4iLi1P7NtnH3XnnnZg0aZL+TCIiIiKirmfTB20Z+EJE1HYdCnxhqSMiogHBOK+2sdQRERFRj3GyNVO/paKiApWVlfqjnpGbm4vMzEw1SBwbG6tuZUBZBoxDQkLg7u6uMiT4+fmp5u/vr1pbGG/bCGZo6mNo5qOpp+Eyjo9bWndDLa2nPTrjtWS7O2M9bdWR9XR0GckaJG3cyrkYv2qePrVlx9buQNwnO7FgwQLVmtLUa7V1Gx0Das5nPY6Mx62tu6Hm1tNeHVmP4zK94d9OR167oKBAtfLyctVkPyq3WVlZat81aNAgjBs3DhMmTFC3sh8LCgrSn01E1LPeStmA4ppy/VFjPs4euDVysf6IiIh6kzfeeEO1tv7OKUrPw9e/eB2RkZHqeURE1Drpl5SMrRP93fHHiSH61JbFFVXiicMZGD16tCrpTkRE/dP111+PnJwcXPG3B+Hu66VPbZkx7nDHHXeoRkRERB0jFylIZaFeHfhiKCsrUwEwUipkz5496oemZHspKipCTU2NCoAxmryptjDednsG2JvS0ec11JPrafictga+NNSd76GjryXfGSmX1ZHAFwmyaq4UTUe3R57X3uCUpnT0eQ315Hocn3M+/y578j0YwS7Gc93c3ODr66sC8iTQZdasWQgNDVUBL56enmoZIqLegoEvRER9V3sDXwrP5WDdL9/A0KFD8Z///EefSkRELUlISMD999+PMb6u+OvkMH1qyxJKqvDdg+mIjo7GK6+8ok8lIqL+RjJ7y8WPlz/9ADwCvPWpLWPgC/UEGbtwHMMQLi4uqhER9VWyD5Nx1z4R+GKQTZUAGDmBkAFm2T4jkMGxETUnKSlJtY4EvkRFRalG1BwJcpHm7e2tmtw3gvKCg4NVwItjoBMRUW/CwBcior6r3YEvqTlY9+Qb6vfN66+/rk8lIqKWSH/SXXfdhRHervjH1LYFviSVVePh/ecQERGBN998U59KRET9zS233IL09HRc9uf74Bnkq09tGQNfqCeUlpbi7bffVlU2DHfeeSemTZumPyIi6nv6ZOBLU6qqqlSTbTUaUXM++eQTrF27tkOBL6tWrcLKlSv1qUSNSYCLZHmRlFpGIyLqKxj4QkTUd7U38KUgJRvfPPUmhg8fjldffVWfSkRELZEBTRnYjPR0wYvTh+hTW5ZWXoP796Wpi2HeffddfSoREfU3t99+O1JTU7HiT/fCa5CfPrVlfTHwRaozyPHs2LFj+pTW3XbbbZgyZYr+iHpaYWEhfvazn2HDhg36FOCZZ57B8uXL9UdERH1Pvwl8IWqP9nYIC0ZeExHRQLAlNxYVlir9UWPuZlcsDJqgPyIiot6k3YEvSVn45jerMWLECLz88sv6VCIiaklubi6uu+46hLo749WZ4frUlmVX1uDOPWkICAjAhx9+qE8lIqL+RjJmJCcn49Lf3w2fkAB9asv64rhDU0ETrWFQRe/CwBci6o+MwBeT/piIiIiIBrBJvsMxwz+m2SbziYiofzCufzGZ2CVARNRW0pkqqq1NXkPYJBe93HF1dbW6JSKi/sk4r7ZZreqWiIiIuh97uYiIiIgI/i5eCHT1abbJfCIi6h+MwBcnfUCWiIhaZ5QzrmpP4Is+EMrAFyKi/s1sNqtbWzuOEf1FWFgYxo0b12wzjp9ERERdjYEvRERERERERAMIM74QEbWfMXBX3XTV+Ca56LtZCXypqamxPyAion5nIAe+LFq0CD/96U+bbRMnTtSXJCIi6lrs5SIiIiIiIiIaSPQOeQa+EBG1nbHPbG+pI7PWrFYrs74QEfVjA7nUUXh4OGbMmNFsCw4O1pckIiLqWuzlIiIiIiIiIhpAmPGFiKhjnJ2dYdF2oW0NfZGKcs76rpaBL0RE/VddxpeBF/jSUfKbJDMzE99++y1efPFFPPHEE7VNHsv0rKys2t8uDVVVVWHv3r3YunVrbTtx4oSaJ+tds2YN/vSnP+Hdd99FRUUFioqKsGPHjnrLp6SkqOUdNbXeppbLzs6ut8yRI0dgsVj0ufbjfmJiItatW4eXXnoJv/zlL2vf3/PPP49NmzahoKBAX7q+9r43R/J5JScn1y4jr/frX/8a77//Ps6dO9fs50lE1B+Yn9Lo9+uR9JuOO2mi/uDw4cOqDR4dieAxkfrUlmXHp2gtFVOmTFHtfMkJzQsvvIBvvvlGtbS0NIwePRouLi76EkRERERERG3X3t85pTlFOLv9GEJCQrB8+XJ9KhERtUYGmKTP9IahfjBJVEsbfJRahCqrDddccw08PT31qURE1J98/fXXKkhj+IIJ8Az00ae2rLPHHbpDZWWlCkiRgA7DvHnzMG3aNP1R25SUlNQGhGzYsAG7du1Sv2dOnjypWkJCAmJjY1WToKKIiAgVfOqorKwMb731FtauXYvdu3erNmjQIHh5eanAmU8//VQFj0iw/8KFC1X2tQ8//BAff/xx7fLye0jGZhylp6er58vYjbFcUFAQxowZAyeHY7+s+7nnnqtdZsiQIRg7dqxaJjc3F2+88Qbee+89bN68Wc2X9yfBK8b7O3bsGI4fP662QbLiOK67ve/Nzc1NPU8CZmT86dVXX1XbL8vI65w6dQrx8fE4ffo0AgMD1efq+DdctmwZYmJi9EdERH2PHCtknJ2XdxF1Mzm5+Oyzz2rbvn37eNWPTk7MSktL9UdERERERNQVbDb7laiOnatERNQ6Y2CpXeWOTPZ9Lft+iIj6r7pSR8ym0Zri4mKVfUQCOCQoRAIyJFDEkTyW6RJkI9lRvvzySzV24EgCWTIyMlRgh9EkaOWLL77AV199hbNnz6qxBjn+SpYTCRpxd3evt7wEojRcrzxv586d9ZaT5phZRZIGSACLMU8ubg4LC6v9Hsjrbt++XWWYkeVycnLqnQfk5+eroBfZTglSkec7au97E7JN8nryeW3ZsqV2GSEBS5K1Rj5PCcg5c+aMmk5E1F8Y/VsMfCGiHiMnZZLOTyKP3377bUgCqri4OH0uERF1lvzqkm5rRETU+xkd8ix1RETUPka2Xsng0lZG4EvDgTUiIuo/jGwkVsvAK3VUWFiosoc01STYQjKlGSRQQzK9yFiAY/DFqFGjcPXVV+P+++/HZZddhshIexZLWV4CR15++WXs2bOn1TI9kjlGgmSaurhWjuGSkcVRUlKSKoFkkOARCbiR4BxHsq0SrGKQIBgJLDFItpThw4frj+zjHrKuyZMn47bbbsMvfvEL/OY3v1HtkUcewbhx49RyEpCybds21VqrwNHSexPyXiRLjGy/EWTj7e2NRYsW4Z577lGfrwTnyIXYDQNtiIj6OuP4wF4uIuox5eXleOedd/DMM8/gtddeUxlwJPqZiIg6T6W1GjvzjmOXaie6sB1XryOvR0REvZzeX8zAFyKi9jECX6pbGXhz5KJffeh4pTcREfUvdRlfBl7gy/r16/F///d/TTYpLeSYKeXcuXOq1JDcGqRUz+OPP4777rsPt956Kx566CH1eMaMGfoS9sATGTtwDD5pimRRkWwpEkDzxz/+EX/6059UwIerq6uaLwEqjqWNJKgmLy9Pf2TPRiNZYERoaCj8/f3VfZnmuM0S7JOamqo/giqDFBAQoD+yny+sXLkSP/zhD3HnnXeqcodXXnmlajfffDNuueWW2nVLIMvBgwdVeaOWtPTe5BxDsrwcOHBAXxqqNJJ8po899hhuv/12df+73/2u2laekxBRf8VeLiLqMXKCJfUkDx06pE4cecJFRNT5zE5mleovrSIXyeXZXdZk/fI68npERNS71V4Jw8AXIqJ2qQ18ace4JksdERH1f2azvS9kIJY6kswuUmKnqXbq1KnaTCbyG0TGARwzvkdHR6uMKPPnz8ewYcMwePBgjBgxAosXL8YNN9xQGxwitm7dWi/LSlM8PDzU82SdEnhyxRVXYMGCBbWlCkNCQjBlyhR1X2RmZtYLaJHHR44cUfcnTJigtklI1noJvjF+R2VlZan3Zhg/fnzta4jAwECsWLEC06dPx5AhQ1SJJTmHkCbzJk2apAJrDFLGqGGWmYZaem8SECQZYeRCY8OSJUtUYIxklwkODlbv5aKLLsJNN91U73MlIupP2MtFRERE1I85O5kwxS8aVu3HudVm7ZpmlVubeh15PSIi6t1s2r5bGDWQiYiobYwrxttX6sh+y1JHRET910DO+NJWchyUzCmOwRnTpk1T5YCMUlEGOd5OnTpVBcEYJDOLY3mkpkgAysUXX6yynchvHWkSGGL8fSR4xLHckQSlnj59ujY4Jzk5WQWhCAkYkcAcgwT4GMdyWU6CYYQsI1lkHH9bSaCLZICRMk9S7knKNEnGmldffVWVO5IM+BJkY5CSR60FyLb03rKzs3H48GF9SfvrSyadoKAgfYqdLD9r1qx6nysRUX/CkQmiXkhOhiSC2Wg7d+5UtSYlolhO7qQG5q9+9Ss88cQT6iRJlikpKdGfXV971iXp8aROZHMpA3Nzc+utS5pMa0hOAPfu3VtvOdkOg7FNEoXc8LUkUtp4jrGtRER0fkJc/THMMwTmLgpKMWs/smX98jpERNT7GVeiMuMLEVH71GV8afvApqs+EMaML0RE/ddAzvgiWUcefvjhJpsEatQGjVZV1Qv2EOHh4fDy8tIf1efn56fmO2ptrMDIbtIc+f0j5Y4k84tBAl+kHJMcp6X0kdxKRhTJyjJq1Ch9KXu5JQl2kfkS+GKYOHGiyuriSJaRsY2nn366NtDlX//6F95880189NFH2LhxY6tlmxpq6b1JBhojEEfI9kRERNQLxjF4enqqz5aIqD9iLxdRLyQnUX//+99r2wcffICcnBx88803+N3vfofXXnsNa9asUVHC7733nlrm9ddfbzIIpT3r+t///od//vOfKgDm6NGjtan7DHJi6rguaQ1PVoVEKH/11Vf1lpPtMBjb9OKLL6oTS0eff/557XNkW1tL8UdERK0zOZkw1X+Edts1V/bLeu3r56klEVFfYHTIN9URSkREzTMG71jqiIiIHA3kjC9SOuiWW25psknJIqMEkGQLlnEDRxJQ2lwwvgQTeXt764/sGo5XNOTr61sbpNocCQgZM2aM/ghITU1FYWGhCqqJj49X0yQ4Zvjw4SozimRPETJekpGRoYJkkpKS1DQhGWQct1OyvGzYsAF/+9vf8OGHH2Lbtm0qG4sEp0iZozlz5mD58uWNgmVa09J7k21yJNtjnLMQEQ0kHJ0g6oXKyspw7Nix2iYZUqQmpgSlyK3UnTQ6TOSETJZ5//331UmUkZbP0HBdEnQiQS9Nrau0tBQJCQkqaEUCYhwjl4VEZTuuS5qR3s+RnMTKSaDjcrIdBmObJLVhwyhteU3jOXLSKSeKRER0/ga5+mK4ZyicnexXIXUWs7Y+Wa+sn4iI+gi9v5gZX4iI2qdjpY4Y+EJE1N8Z59XSLz7QSGCIBHQ01SRzivHZSNC9kRnHIJ9Xc8EsMs4hASmOWvv90pbAfilB5Bj4IhnoJShFxkkOHjyopsl82f7IyEiMHDlSTZMMLXIRr9wa4yby/mRZx+2SkkhykbIEysh4i6zjgQcewG9/+1v85Cc/wXe+8x3ceeediIqK0p/RNu25aEE+0+Y+15bmERH1dezlIuoDJPDlnXfeURHR1113He666y5Mnz5dn2snWVy2bNnSarq/tLQ0lUlFbpcuXarWddVVV2HYsGH6EvaMLVJqaP369U0Gtpwv6SiS1HxyUtgwaltO+GSetMGDB7Mznoiokzhp/03zH9Hp5Y5kfdP8R6r1ExFR32B0dPJcm4iofepKHbU/8KUr+leIiKh3cHZ2VrcDsdRRW8mYgPT3O0pPT2+UrcQgASZyYayjlsoYtZUcyyVLi0FKBMnFwlLmSMZYxPjx41WmmqCgoHpBMnLRsGR7keAWIZlhJLDFUWxsLOLi4vRHUNldbr31VixbtgyzZ89W4x6y3s4MiG1YukjGkxxLHznKy8tTQT5ERP0Re7mI+gA5SfHx8cF3v/td3Hvvvbjjjjvw/e9/H5dddpm+hN2ePXuaLD3kSEoHycndY489hkceeUSt6/7778cPfvADzJo1S1/Knv1Fgl+ys7P1KZ1nwoQJ+PGPf6yim+Xk0NEVV1yh5km755571EkgERF1jgAXH0R7hcLZ1DlZXyR7zAhtfQEu9YMYiYiod7PZ7FeistQREVH71JY6aseV0s76vpYZX4iI+i8joJyBL82TY+ioUaP0R3Z79+7F2bNn9Ud1JNuLlAeSgBSDUXqoM8iYxOjRo/VHUJnpjTJHRpYX+a3k4eFRb/xCAnUkqEXGWIQEyEhmGEcSsON4zJd1DRo0qPa3l1yEIAE00jqLrN8xAEfGk3bv3t0oqEiCcHfu3Nko0z8RUX/BwBeiPkKCXC666CIMHToUISEhmDZtGlatWqXS6RkkIrktgSoSZSxZXuTkTtYl2V4uvPBCXHnllbU1K4WcxDnWq+ws8poSZCPvQVILOoqOjlbzpE2dOhWenp76HCIi6gxT/KLt5Y7Oty9G+6EuATSyPiIi6luMDnlmfCEiap+OZHxxZakjIqJ+rzbwxTLwSh21lXxGkydPrpdBRcYepCzQ/v37VVmjsrIy5Obm4ptvvlEZ8I0AE7Fw4UJEREToj86PjE9MmTJFf2QPfDHKHElGlrCwMHVfSjNJ4IoxZiKZXiRYxzBp0iSVGcZRwzJCx44dU1lWhAT0SICNZORvLiNLR8j7aVgh4OOPP8batWuRkZGhPlcZO1qzZo36XMvLy/WliIj6ByO4kL1cRH2AROtKkIjjSZT8Iw4PD0doaKg+xU4ytbRETg7nz5+vMsg4ks4bOalzPHmUE0s5MSIiov7D38UbI72GwLlBXeX2kufLemR9RETUx+h9sQx8ISJqHyPjSxUDX4iIyIEESAiblYEvLZELcG+88UaVoUTIsXHDhg3461//il/96lf4xS9+gSeffBL/+te/cPToUbWMkACTSy+9FF5eXvqU8yOZXBwDcCQY5fTp0+q+XCzs6+ur7gsZL5HgFyGZUoztkuwzkg2mYRZNCUJxtG7dOvWeJMP9T3/6U/zpT39SwTCOFyCfLxnrkcAg43MVRlDRr3/9a/W5PvXUU3jttdeQlZXVqa9NRNSbsJeL+o1t27a12s5XU+ts2LqCZEXx9m48sCgnYI4nM6JhRHFDTQXLGKSsUMN5RUVF+j0iIuovJvkOg5tJrlZte4d9Q/L8SX7D9EdERNSXGL8ZGPhCRNQ+dRlf1E2bsNQREVH/Vxf40vF+loFAAi6WLFmCG264oXYcQi7klWwrEiDy5Zdf4ttvv8XJkydrj5uSmeW+++7D2LFjGwWZdJT8DpKyS0aQioyBSBYU2T65ONjZ2VlNFzJmIiWNhCxjjJdMnDgRwcHB6r4jmS4XMRukPNL69evxySef4NNPP1UljiSz/5AhQ/Qlzp+8n9mzZ+Pqq6+uF9QiwS+bNm2q/Vzls77pppvqlXkiIupP2MtF/cYbb7zRajufwBR5blPrbNi6k3S4GFcbtZVEMzcX0SsndEYnjkHS7xERUf/i5+Jlz/oiJY86QJ430iscfs6dc6UNERF1Mz3wpbM6jomIBgqjD6a6lYuOHLnova9VVVX1LpxqrhERUd9jBJRbmfGlVRJIct111+G73/0uli5d2uQFv0Kyqdxxxx34/ve/rzLYNywpdL4kk4tj1hchmV0kK40jGU+R7C4NSfBIUxloJKDl/vvvV9vccBxGMtc8+OCDWLFiRbPvu6MCAwNx/fXX495771WfXUPy2g888ABWrlyp/gZERP2JcYGXk3anyV9qFRUVqKys1B8R9W5Sn/DRRx9VadrcfDwxKKZhtKx06NZ91cetnAf/yMH6o5YVpGQj7pMd+qOmpR1IULdS+/Hvf/97oywsjl599VU8/fTT+iNg8eLF+P3vfw8/Pz99ClQE7uOPP64/sp+U/PnPf0ZUVJQ+xU7qXv7sZz9T6QANzzzzDJYvX64/arwuOeH6wx/+gMGDG7//tLQ0/OQnP8G+ffv0KcBvf/tbXHvtter+oUOHVESwI6kJ6VgPU7Rlu0RblyMios5XVFOGT9J3orimQp/SRtoh1cfZAytD58DX2VOfSEREPckIwh+3ci7Gr5qnT23e2e3HsPe1r3DJJZeo838iIrJf8NSaU6dOYfXq1bh7eACuiagrg9CS1WcL8G5KYZODZk15+eWX9XtERNRX/POf/8QHH3yAqTcvxsiLp+pTW3Zs7Q7EfbJTBXdI6wskC4tkZ8nIyNCnQGVIMUoBtYdkT5HSQVJiqKCgALm5uSpwSIJFJAO+BKZER0errCpNZao8322R50vZotTUVH0K1GvJWEfDgJWUlBT1Wo6mTp2KyMhI/VF9Mr4qmV3kvEG2r6amRgWmSJYZCZiRDEEHDhxAfn6+Wl7er2SJMQJpzue9yecopZsSExORl5enpkmgiwTDyOtLII+M8ziue/r06apSABFRXyVJHTw9PRn4Qv1DSUkJduzYgbfeegsZ2ZnwHxqMYfPHI2CYPV2eXMjo+E1va9CLQYJfmpJ1Ihlntx1DYWq2Oum4+eabMXPmzBZrTfZ04ItspyzTVNTv3r178Z3vfEedaBpeeeUVFSwjmgp8+e9//6tO8hxlZ2erepXbt2/Xp7Q98EXqeUrEMxERdb29+fE4VJiIGlvbs3s5m8yY7DscswKYFpWIqLdob+BL4taj2PefdVi2bJmqNU9ERFBlFNpCBuhujfLHTUPr+nFaklhahbeTCvVHTYsrqkRhtUUNuD3//PMtXlBFRES9z4svvoj3338fU25YhJhLputTW9YXA1+6ggxRSla0srIyFfhiDF46lhvqqyTgRcau5H3Je5KsNd2RdVM+Uxnflc9UXk9eW7LWMeMnEfVXxrGDpY6oX5C0cAsXLlRp3CKHRCD/bCZS9sajprJKBbn4RQxWt0ZrL8fnGq00uwApe+JV0IvUbXzooYdUgEhLQS+9gWR1OXLkSKMSRsXFxdi6dWu9oBe5Gkmy2BjkxMyoe2mQ9TnGz8n9M2fOqKjijpCsPUwJSUTUPcb6DIWXc9Pl75rjZXbHOO15RETUh+mn701dOUlENBDJ1dFyEaAEtUgLLjjXqIUUpqs2N8gDc7TWVsO9XHFLlF+TbVagB4qqLai0WtWV7XfddVez5amJiKj3kgwegv3a7SfBGDLuIFlPJDOJr69vvwh6EfI+/P39VbYXOb53V+CJvI68nryufK7dFXBDRNTT2MtF/YYcyOfOnavqFI4YHo2s48k4+sFWddvZJDX4sU92Iu9MOubMmaOuCpKsJxJR1ttJCkHJjLNu3TrVsSOPJa3d2rVr8cUXX+hL2S1YsKBeoIucJDXMOiPPkUCa0tJSFTwjKfjeffddVX6qNcaJnyNJLSxBM7JdkjlGbomIqGt4O3tgjHcEnJ3sHTStkeVGa8vL84iIqO8yAtcZ+EJEZCd9Sg8//DDGjx+vHmdUWDDEwwW3RPnXtpuH+qkm9yWYpT1k+Yat3GLF1uxSnCqpQtjQYepirgsvvFBd3EVERH2LEfjieIEoERERdS/2clG/IoEnM2bMwIMPPojx48Yj51Qajn60DelHE/Ulzt+pb/bjxOe7UZiSrcoUydU4EyZM0Of2DSdOnMC//vUvPPXUU/j5z3+O3/zmN6pGtWRvMUi2lyVLlqjUUAYJUhk7dqz+yG7Pnj2qdNMvf/lL/OpXv1Klis6ePdumtLwSaTx0aP2sAVJOSco6yXa99tpr9TLQEBFR5xvtEwEfCWRppW/GSftPlpNAGSIi6tuMDnle9UdEZCfZe2fPno37779fZfOV8kR78spxuKAC4R4ujYJWzpes9/XEAhwurMCwkTHqIi65mIvZXoiIeh+5ULO1ZgSU2ywdC3xpap0NGxEREbWMgS/U78hJ5pQpU1RnhWRhkawsx9ZsR9rBBH2JjrFU1aiamyfX7UdxZj4uv/xy3HbbbYiJidGX6Bskde7FF1+MlJQUrF+/Hl9++SU2btyI5OS6zDiRkZG49dZbMW7cuHqd4RKoIlcfDR8+XJ8Clell3759aj1fffUVzp07h2XLltVbpjmS8WX69OmN1rdr1y61vgMHDqj6nkRE1HWkdNFYn6Ewm1rO+mJ2MnWoNBIREfU+NiszvhARNST7RCllfeedd+KKK65AankNPk4rwuqkAmRV1OhLnb99eeV442wB4ooqMXb8BHXxllzE1ReyCBMRDURvvPFGq2379u1qWVsHSh1JUEtT62zYiIiIqGXs5aJ+S7KwSJrYWbNmIf9sJuLW7kDK3nh9bvtUFJbiyAdbkPDtQe2BBddffz1uvPHGRmV/+gIpV3TDDTfglltuQWhoqD7VzigX9dhjj6ngFcdsL0KCYCZNmqRKO0lwUUMyTwKOLrnkEvj4+OhTWyYZZCRrzpgxY/QpdaTTiVehEhF1vRjvIQhw8dIfNUHbFftr82U5IiLqB1jqiIioWZIBV/p8pN/E6uWHrzNK8NKZfJwsrtSX6LhdueUqkCZeW5dcrCV9KNK/wv0xEVHvJOX8y8rKcPr0adUqfJ3qNz9T7f3wqSNVa6vwaTFq+Xrra9BSs86p1y0uLlbbQkRERM1zsjVTdLCiogKVlef/g46op8XHx+Ott95SUde+4YMwZvlMRM0dp89tXXF6HmLXbEfG0bPw8/bB1VdfjaVLl7aplE9TTp06hWPHjumPgLCwMNXZ4epalypXSg7t3btXf2QPVpHMKA3rPEs2lIMHDyI9PV2fAsycORPh4eH6I6jMKY8//rj+yB6c8qc//UkFuRw9elSVJZIsK/I4JCREdfBIFhsPDw/9GY2VlJSockknT55UJ9yyGwkMDMTo0aNVAIusq7XtclRYWIi4uDgkJCQgLy9Prc/Pzw/Dhg1TgUuScpiIiLpWbFESduQdh8VqUYEutbQzRckGMy9wLCb49r2ATyKigcC4CnTcyrkYv2qePrV5p9YfwKF3NqrfNo8++qg+lYiIHOXn56uMtB988AHOJiZigp8bro7ww6zA5vtLWrI1uxTvpxbhTEmV6iO54447VKZdIiLqvaQfXPrp//vf/6oAFP/IwYiaNx7BYyP1JaQDpW6IzT8yWL/XNgUpWfq9+uRC3rPbj6EgORuhg4NVMKaU4ms4PkBERERQY+wyrs3AFxoQJKBCTk43bdoEn9BAjF42A8MXTtTnNi8vUcok7UDmsSRV/kcypcgJpq+vr75E79dU4Muf//xnla3GarWqiHX5ty4pdSXDi5QfaisJvJGTfyHPlVJIHc3QIrsi2Q7ZHrkvOygJoOFVT0RE3aPcUoUvMvciq7JAn1In2M0fK0JmwsNcF6RJRES9R3sDX6R86+H3NuGaa67BI488ok8lIqKGpH9ULl565513VDnmEd6uuGKID5aGtG/gcUNWKT5IKURSWbXqV5Ly0nLxEBER9X7V1dXqAlI535bboBFhGH3pLIRPa3t2l/bITTiHY5/sQM7JNAyNiMTtt9+O2bNnq75yIiIiaswIfOGIMg0II0eOxG233aYytRRn5OHEl3uQsOGQPrdpmXFJOPK/LciIPavK8Uj62UWLFvWpoJfWSFCJRIkHBQWp99WeoBchOxLJ9CJNTrzPpyyRPFfWIeuS7ZFAGga9EBF1HwlqkYwuZqe6fa/sm81ak+kMeiEi6kf0619YVpSIqGXSTyEZeO+55x5cdNFFOF1ShfdTCvG/1CKUWqz6Ui37OqMY7+lBL9KvJJleGPRCRNR3yAWj06ZNU+X/JQAl93Q64j7ZgaQddVndO0vWiWQc+WALso4nY8TwaDUmMW/ePAa9EBERtQFHlWnAGD58uEoJuGLFCpRkFSD+q7049c0BfW59qftOIvajbciOT1UdHHKCKSe1LZX/ISIi6uuGeYYg2M2vrtKRzaayvch0IiLqP2xWe+ALA82JiNpGLoiSC6quvPJK5NmcsTatCK8nFuBceY2+RNM+O1esgmRSy6rVxViyDrk4i4iI+p4JEybgrrvuwuLFi1GQko3jn+9udnyhI9KPJqoxiZxTaRg3dhwefPBBVRpPAm+IiIioeUaBI/Zy0YAydOhQ3HTTTVi1ahUq8ktwct0+FQDjKHFbLOI+3YW8xAwsWLAAd999tyoPZDab9SWIiIj6JzeTCyb4DpMUALVNHst0IiLqP2o7BBj4QkTUZsOGDVMlsOWiKrfAwdiQVYJ/n8nDsaKmS8WvPVeED1OLkF5eoy7CkufJRVlERNR3jRo1SpWru+yyy1Ccka/GF45/uguWqpYDIVtz7lACjq3ZobLJTJ06VV2IO2XKFJ6vExERtQOPmjTghIeHq44KqWdvKa1SUdkSnS1OfrMfJ77YjcLUbHUljqSflat6iIiIBoqhHoMR5haosr7IrTwmIqL+hYEvREQdExISgssvv1xdJDVs5CjsyyvHfxLzsT23TF/CTgJePtZaTrVVXXwlF2HJxVhERNT3SSCk7Nevu+46oMKCU98ewNEPt6KisFRfon1S9sbj2NqdyD+boTK8SHm9iRMn6nOJiIiorZxsRo9XAxUVFaisbPqKhd4mKSkJqampyMrKUttN1BbZ2dnYs2cPMjMz4ezlhhGLJiNxaywqCkoQFBSkShz1h06JY8eO4cMPP9Qf2QN/rrrqKgQGBupTqLP4+fkhICAAgwcPVp1hPj4++hyi/iU/P7+28bjbP52zFCInxIJBWWYMMfnpU6m/8fX1Vc3b21sds1xdXfU5RNTXvPHGG6qNWzkX41fN06c27/hnuxD78XaVfUA61omIqH2qqqoQFxeHd999V/UtDfdyxYowb6354L2UQlXiqNTJGStXrlR9MKGhofoziYiov8jJycG6devw8ccfo7CkGKETh2PCVfPgE9r2fveknXGI/3IvCtNyMH/+fJVNZvTo0fpcIiIiagspC+jp6dn3Al/279+vflgWFxejvLwcNTU1yM3NRUFBgZpWXV2tL0nUOvm+lJaWwmq1wtXbA1Ul5XBycoKXl1e/GfwpKytT/0YMbm5uKjiDtUE7n4eHh9qxygCiBMHIZ+3s7Ky+T7Nnz1ZpKon6mpSUFJw+fbpesEtRUZHat8j+U47D1P/YzE6w+LvAXFANJ0uTp4rUD7i7u9drcuySAJioqCiMGTNGBXES9Xbyu1V+B548eVKfMjBt2LABGzduVIEv/kOD9anNK0zJxrG1O3DhhRdiyZIl+tSBhwGA1J24v+qf4uPjsWPHDpw5cwYh7s64ONgLX6SXoMzJjPHjx+OCCy5QF8dQ3yfHCWlyzJB+Hun/ISIqLCzE9u3b8f7776s+tJDxURh/5XwEDm894DFx61HEf70Pxel5WLRoEW6++WaMHDlSn0tERERt1acCX2RbpBPv1KlT6gfluXPn1DQJWpCABWFzcQbc3WDzcIfNiz88qH2ctO+SrcYCJ7MZNtf+FhCi/RN3/FcutSuU2jvUSZy0faZTRZW205Jbbf+p7Z8kfbwEwEgd7+joaIwYMQJz5szhYCL1ahLMcvz4cdUOHDigMmRJoIsR7KKOvc7O2jHXDdD2m9YAZgQh6ovUcatcO17pxy03V1cVACNZ4cLCwlSKZQmA4dVm1BtYLBYcPXpUHZMkAFMGj6VJR7P8NpTsnwNZXl6eav6RbR9cLUjJVgHxku1yoGIAIHUF7q8GHvnbyt9b+DibUFxjVRfByD5ELpCh/kH6duRYIbfSjEAYOXZImXRpLCFINDDJBdoHDx7E22+/rfrSBo+OwNjL5yBkXJS+RGMJGw7h1Df7UZJVgKVLl+LGG29U/cdERETUfn0i8EUCXSRdaHJKCo7HxamSNFWwwRY8CDZvT9jkaiwV7OKm/frQ7mtvSgUtuDGTBbWTxWpvJifA2axPJGqn6hqtWYCaajhp953KK9RgoikrF04Z2XC22tSVXhIAI7Vgx40bh3nzWk9FT9RdJEWr/EA/GhuL+BMnkJ6erqZZgwKAQD97cKlbg+Ou7De92JlL1Cep45Z2vJLbqip7EExZGUzp2erYJSn5pU2aNEl15EvmMmZDoO6WnJysBpClfKdcQSmDx/Jb1WhSakIE+btiVKSXuj9QpWQ2XX7QSTtUN/2rH4gMcdfvDUx5RdXILaxSt1btXN0Y1JRgINn/MQCQ2qOt+yu5WMsWPHADzvq1qmqJfLL3KzHLbv9TVg6nUq1pt3KhkwQ3yTFDgpskaFwy/Eg/jxw3BnJQKdFAJYGvsbGxWL16tbqILCg6DKMvnYnw6TH6EnVOrT+ggl5Kc4qwfPly3HDDDRg6dKg+l4iIiNqr1we+SF1ESRGXmJiIgsJCWH29VceAJSwYtkEBsMmAm1xtLple5MekmRH1RNTLyGBijdaKSuCUnQfzuUwVAONUXKrS4krHyMUXX6x+3BD1NPlRvmbNGhXsIpnVyrTDqm1wIKzhYbAG+avgFpsEuvC4S9Q/yU8COW5JAExhCUyp6SoAxik9C37e3moAWDKWLV68mB1y1OUku9iJEydUk0HktLQ0dWwym4GhIR7w9nSGj9bk1tfLfj90kBuGDBrYQRz5Rc2U/ZVEj80EvgT4DuyB2dIKC0rLLSgurUGOBMDoLT65VN02DACcPn26GugkMjS3v7I5OdmzIrrbA8Zt7tLkvhts0r/l76OvgfqVGgtg1Xa48luJv5f6n0rtOCvnylXVcCot03YA5TBJIExePpzyi2r7eYYMGVIbOClZf4loYJELyt555x1s27YN/hGDEbN0GoYtmKDPhSptlLD+ACoKSnH55ZfjuuuuQ3h4uD6XiIiIOqLXBr6UlJTg3Xffxfr161X6V2tYMKwhg2CLCFWdA1Yfb2bkIKK+p8YCU1GxGkx0SkqFKSMHptx8dRWQDCI+9NBD+oJE3W/Dhg348MMP1Y9zOe7aBgXCGhECm48XrP5+2lkDB3iIBhrJWuZUqB230rNgPpcFU/I5+Pv6qg78q666SnXmE3UFyZjw6aefIi4uTgVjFhQUIDjADaOivDF2uDeGD/GEu6tJa2a4uZngIbfqsQkmyUJG1AEyTl1aXoOycgtKtNv03EocPFGA+KRSnE4tha+2/5MAmAULFuCSSy5BcHCw/kwayJraX8n5s2QptoYOtgePy3l07UVb2q0ETsl9ScVERH2WBL+g0h4Eg9JSmOR8OStXa3kqkFwCYKRdffXVmDt3rv4sIhooEhIS8L///Q/ffPMNfEICMOKiKSoA5sTnu1WJI2t5NVauXKl+W8s5JhEREZ0fyVIumRh7VeCLpIL76KOPsHfvXnXVjGV8DCyjo+1Xw3h56ksREfVtTnoAjPPBYzClpKvUuEuWLFHBL6z/Td2pqKgIH3zwAbZu3YqkpKS64663l+q0JyKSlP2mwmKYTifBHJ8IU2kZRo0ahRUrVuCKK67QFyLqHDJ4/Oabb6oyIfJ7cHSUN0YN9ca0MX4ICXJDqNY83HgRBHU96SXJzKtARm4lYk8X42RSCQ6cKISvnz+mTZuGa6+9luWPBriG+yu5YMsaHARb5BD7RVu+2rm0ZEkkogFBBY0XlcCUXwQnyfabJRc7FSAmJkadM0tWByIhF/1KZjAphyd9MnLreH/+/Pn6ktTXSYCs9LedPHkSbn5eiF44Eac3HoK1okaVRrvgggtUSXzqH3x8fODt7a1upUl/PxERdZ9eF/gi6d92796NI0eOwObpAcvE0bDEDIPNj+lfiah/MmXmwPlQHEwJSTCZTLjoootwzTXXqKvpibpafHw83nvvPezbtw/FVguPu0TUsrJymDO049a+o3DKzlVXsMpx695779UXIDo/e/bsUb8JDx8+jLBB7pg/ORAzx/mrgJeQQDd9KaLuV1RaowJgth3KxbpdWSirdMKECRNUWnopAUcDj+P+Ss6dLdFDYY0Kt1+0xeBxooHNaoVTUSmciovhfDBOXewkpY+WLl2K22+/HU7M9jRg5eTkqIt+pQ9GsoTJ2ItjKy8vV7cjR47Un0H9gQQ6qaoG2r7BzdsDlSXlqmxmSEgIL37sZyTQpWEzgmCmTp3KoHkioi7WqwJf/v3vf6u0b3l5ebAFB6Fm+gRYwkNVHWQiov7MlFcA05kUOO+PBWpqMGXKFPz85z9XJZCIuop00ssVqgcPHuRxl4jaxZSaAee4UzCdOgsvLy8sW7YMjz76qD6XqGPef/99bNy4UQVlSnaXyxaEYEyUDwL9mC2Beo/cwiocPFGId9elIS27QmW/WrVqFZYvX64vQQOB4/7KOjQMlvGj7eW5vTh4RUT1ycVO5oPHYD6drErmSXaHO++8k/09A0xKSooKeNm1axdSU1NVq66uhk36X9zdYXOXWzd1HJHMQdRPSVk0ixVwNrOceH9VWQ0nGU+tqNLuV8JstdUGwERFRSE6Olr1+0sAzKBBg/QnERFRZ+k1gS9ffPEFXnjhBRXVbB0eiZrJY2CVwTciooGisgrmpDQ47zkMp8JiLFy4EE899ZQ+k6hzZWZm4ne/+53qeOFxl4g6QoI2nVLS4bJtn/pR8f3vf18FwBB1xF/+8hdV6laugpWAl6WzByMm0gsmE6+Ipt6nusaGg/GFeOfrVJw4W4Lw8HBceeWVKmsj9X+O+yvLhFGwjBkB6+Ag7cDI/RURNc0pNx/mhCR7qWsbVBmbxx9/HH5+fvoS1F9J38uOHTtUlrC0tDTVrBLgIqXxJGDS30eVxLM5O6tACAmEcZLgCOqfLBaVEUr7kQOYWbq1X6rR/sY11XCq1m6rtdsKCYKptJfAy8qFW2UVhg4ditDQUJUBRoLopeQVERF1DhftvMrT07NnA1+SkpLwi1/8Qp342bw9UX3ZRbAOCtTnEhENLKazqXD9fKNKfXvbbbepK4GIOtvvf/97rF+/nsddIjo/NRaVrcx53xFERkbiJz/5CcaOHavPJGqbl19+WZULEfddGYX5UwJZ1oj6hKMJRdi4Lwdf7sjC4MGDVcbGSZMm6XOpP3LcX9XMnw7LiKGw+Xirx0RELZEsHqbkc/aLnYpKcPHFF6vjBvVfp0+fVqWljx49qgJgbIMCVLCLJSIU8POF1Vc7fjDjLlH/JoEw1dUwlVUA2r7fnJquMoFJEEyw9vtBAmAWLVqEJUuWwNub55REROfLCHwxP9VMWoGamhpYJBK1C/31r3/FsWPHYDOZULNoDqwRYfocIqKBx+bvq/0PMJ3LxJkzZ1QNUIn+JuosH3zwAT7++GPU2Gw87hLR+dHO362DAmAqKkbx2RQVyD5x4kSVxp2oLaRciDRJ9X7vlVEq24u/N0sbUd8gAVpDQz1QVmHB0ZPZqmyBpC6X83fqfxz3VxL0UjNB+43m4a7PJSJqhWTz0M6bbX4+MCWmICkxEQEBAarcBfU/Ulr6tddeUxnCCp2dYBk/CpZxMbAOi4AtLBg2L097uRsi6t8ku4/s/z3dYQvwhS3QH9aQIO1Y4IvSqkpkxZ/C2bNnkZ6errKABQcH608kIqKOMJvNKvilxwJfVq9ejc8//xyScMY6diRqpo0HnJgelogGNmtQAJxKylCdnqmyYkn69IiICH0uUcdt27YNr7/+OoqLi3ncJaLO4ewMW4AfTGkZyDybrH47TJgwQZU/ImrJN998g7feeguFhYVYPi8EN10SDnc3kz6XqG/w8XRWwS9n0soQG5+qvs8zZsxQHS3UfzjuryzjY1AzfaIaxCAiai91sZPZpLK/SH/P8OHDERbGi1H6EzlmvPvuuyr4pXpICGpmTYYlOhK2oABoJ7vsgyEayNxcVbZAa5A/bIMCYdP2B2XS/3/6NFJSUtQiI0eOVLdERNR+RuBLj5Q6kvqWUhtZOg6sUUNQvWCm/eSfiEhjq7HCklMMS2q+dlsCVNbAZm1yV9VpnKQuu5szzIN9YI4IhPMgL9Uh0ROc8grhsmGHSn8oZSN+/etfY9CgQfpcovaTDEJ//OMfkZCQwOMuEXU6c+xJuGzerbK93Hzzzbj++uv1OUSNydWvL7zwApKTkzFznD8eunY4wgaxvBH1XcfOFOMPr59CcTlw33334ZprrtHnUF/nuL+yRoWjeuEs2KQ8BRFRR1VVw3X7PpjiEjBu3Dh873vf40BnPyEl8bZv366OGZZxI+1ZXkLYl0dETZPSd6asHJj3xcKUm68ufL3gggvU7wkiImo/o9RRjwS+/OhHP8K+fftUZoOaxXNhDQ7S5/Rug0zl+r2+Kcfqod8j6r1slTWoPJyK6lMZsGQWw1pcYa+J2bVxL9rZptaczTD7esAU4gPXMaFwnRAOJ9eeuZrPnHAWzht2wmyx4q677sItt9yizyFqv//85z948803e+S4y2Mn0QBQUQnXLXtgOnVW1amWcqa8epWaIoGYTz/9NE6cOIGJI31w35VRiBnKQWTq+z749hxeXZus9n0PPPAAFi5cqM+hvspxf2WVq/bnT++Sc2ieKxMNPKbCYjhv3AlTWiYWLVqEhx9+mBc79XEvvvgiPvvsM5SVldmzvIwarkpbdTYeM4j6H1PKOZjjE7V2Rg3Yrlq1isEvREQdYAS+dHupI+k8kME3VRt54mhYtRPBviLYVAZXJ0ufbQU21qCmXs5qQ+XhFFRsS4AlrQC2sio1rdtor2Urr4I1r0xlmjF5ucMc4gOnHkhFavPxgjkjGygsRm5uLq688kp9DlH75OXlqU6YoqKiHjnu8thJNABIySN/X5gSU1Gan4/IyEiMGTNGn0lUR0rdSgr44UM8cd9VwzBmWOcPCBD1hCGD3ZFTUIXYU1mqTr9crenuznOIvszYX0k6+poFM2ANHazP6Vw8VyYaeGxS8sbLQwW+ZCanqMDx0aNH63Opr1mzZg3++9//ory8HNWL58IyJlr7+3rqczsXjxlE/Y8EydkC/GEbHAjryUQ1fjp48GCMGDFCX4KIiNrCKHXU7XU8pPNAop9lULcvBb0QUdez5Jeicm8SrLkl2gOrPrUHaK9tzS5G5e4zsBZV6BO7mbaDtkQPVXfPnTunSsQRdYRkWEtNTeVxl4i6lDXQX5WBEFu2bFFB7kSOSkpK8O2336r7cycGYnw0g16o//D3ccF1S4YgQLuV0pKHDx/W51Bf5Li/sg6PhDUsWN0nIuosliEhsA6LUBnX169fr4ImqO/ZvXs33nvvPfV3rJk0BpaxIwE3lvAkovaxBfiq/UfN9Alq7PTtt9/GkSNH9LlERNQWRgKDbg18kSwy27ZtU/elY7wrUv4RUd9VFZcOS2ah/kij7adcYkLgcUEMPC4c1bVNew3n6MGwGdldbNo+61wBqk+k2x/3AOkEsXl7qn2nXEFC1F5WqxUbN26EVDXkcZeIupR2/LSMjobN1UWVhTh+/Lg+g8guNjYWKSkp8PF0xoIpgfpUov5DMhlNH+uvMudu3rxZn0p9kbG/ksFL64gofSoRUScym2EZM0KdO588eRJHjx7VZ1BfkZycrMpKZ2ZmwhoRCsuUcfocIqKOsUweC8vIYWr/8uqrr+L06dP6HCIiaqtuDXyRK2akZIfNxVnVuiQiclR9LB2oqcv04jwsCB4Xj4HbvJFaG9HlTV7LOTJAf3WNti2VR9P0B91Pgl6sUUPU/bi4OJXqkKg9ZOD52LFjPO4SUbewBgepTl+5YnXTpk36VCI7VTLEasX4ET6IDGV9f+p/TCYnLJ45CC7OJhw8eJDn7n2Ysb+yDgmGNdBPn0pE1LmsgwJgDQ9FZWWlumCF+g7Jbvnxxx8jPj5e+zsGomb2FJVll4jofNg83FEzYyKsg4NUQOTq1atVcB0REbVdtwa+rF271t55oJ3UWwfzKj+zyYRQnwAMCwjBEJ9AuDu76HOIBiZLdpF+z85ldCicIwJg8nGDyauLm487XIYGwTW6fu12a2b9bepulrEx6lbSHEqpOKL22LBhg0rV3p+OuyYnJ4R4+6tjZ7hvEDxdmEaYqNdwtl+56mRywvbt25GRkaHPoIEuLS0N+/fvV/cXTAnSvip6hj2ifmbMMG9VxqugoKA22y31LY77K8uIoRLRpO73FXKuHOpjP1ce4hsIDxdXfQ4R9TqS9UW/QGXv3r04e/asuk+9n/y9JLubzccbllmTYQ2t35fYV3i7uiPCLwhR/sEI9vZTxxAi6lm2IH9YpoyFzc0Vu3btUgHZRETUdk42qX/QBKlNKRHnnenyyy9Xg7fVS+arVOh9zTCzQwmW8xAdGIqLoifCx80Tvm4ecDE7o8ZiQUl1BUorK5BVWojP4/eisqZaf0bnOGvhlUrUu+X9co0qMWTwum463CZH6o/s/Jw8MNwcDF+TB0xSC6mTndmxH4fWrNMfaUxOuPwPTyDTVojEmixYHTewO1itcHvvczjlFSAmJgb//ve/9RlErXvkkUdU1peePO521rEz1DsAy0dP146b2rHT3ROucuy0WlBWVYmSqnLklhXj0xN7UF5dpT+jc/DYSdROlVVw046jTjn5+O1vf4v58+frM2gge+utt/Daa68hIsQDf/7OOAT4MOCf+q91u7Lxt/+exvDhw/HMM8/Az4/nEn2Jsb+y+fui6qpLYPPs2gxVnXWuPNR/MJaMnAIfNw/4aefLqp9JO1curarQzpUrkF1aiM9OsJ+JqNepqITbZxvglJmDu+++G7feeqs+g3qzJ598Elu3boVlxiRUz5zYbUGSnXXMWDhsPMYGD4Wfuwc8XdxVwEuVpQbFVeUoq6zEiZxUbEuKU2WzOxOPGURtVFUNlx37YT52CmFhYfjb3/6G4OBgfSYRETXFxcUFnp6e3ZvxRYJphKRBH4gkw8td05fgzmlLMDF0GM7kZ2B3yklsOxuHXSnxOJ6VAm83D1w6ahoemXMZrh4/D84ms/5sogGg4e8physN5F64KQAXuIzBLJcRmOoShSld0CLMDbJiWG2Y7jIM811itDYaPk7u+oxuou03JP2tKCzsnB+4NHBkZWWp27583DU5mXDz5Atx38xLMCNiJFKLcrDHOHYmx+NoZhJczC6qo/9h7dh565SL4ObsrD+biLqdmyusgf7qbmpqqrol2rdvn7qdOtqPQS/U780c54/IEA9Vm5/ljvoeY39ljQzr8qCXziD9THdOuxh3T1+KKWHDcTY/q66fSTtXPpaVrAY1l8XY+5mun3gBXEw8VybqNdzdarO+HDp0SN1S73by5EkcPnxYlSevGTui24JeOoO/u5d2LFiBayfOVxleYjOTsTP5BLYnHcfe1FNIzM/E8MBQXDNhHh6bezlmRsTAiVlgiLqfqwssE0Zr56LuSE9PV1mmiIiobcxPafT79dTU1MBiseiPzl9eXh7ee+89dTJYM2eq/DrX5/Qd/qaOZ8DxcnXHPTMuwQXDxmHr2ThsORurbk/lnMPpvPTallaUh7TCXJWO9oJh4xEdEIpzxXkq8rrSUqOvrWMKbN08YE/UTuUbTuj37FzHD4FziK+672/yxIWuYxFtDoaHyRVmmGCtqsGp48eQmngGGakp9VppURH8fQLg6mxftq3tXHIS4o8fVa9puPTSK+Ht5I7BJl9oe0aV/aU7M7+YsnNhSrcHMNx8883qlqg1kmHtjTfe0L6r2jG9B4+753PsdHN2we1TL8LSkVOxLy0BmxKPYmtiHOJzUmuPmwm5cuzMVU2OlXLl0vCAEGSWFmj/ou3HTtt5/HvlsZOo/UxZ9uOWXJk0d+5cfSoNZK+++irKy8ux8oIQRId76VOJ+icPNzOOJBQhKb0Mo0ePxtixY/U51BcY+yvLxNGwDer6UqHnc64sJT/l4qqLoidhe/JxbEm09zOdzElz6GfKqD1XlnPrC6K0c+XAEKQX52lnyvYr/M/nly3PlYk6gfY71hx3ClarFddee60+kXqrDz/8UJXEs46IUmVeu9P5HDMkM5gcM0YEhuGT43tUsMue1JOqT8U4ZpzRjhkZJfk4V5SH4QGhmBM5GoGePsgpLVbXJsox43zwmEHUdjZ3d5jyC2HKyVcJBRYvXgyzmRfJExE1R/aRkvWl20bBkpKS1K3NQzvBcRlYV5fI1TR3TF2MWRGj8J8D3+Kz+L3Yl5qgyhs5stpsOJufiQ1njmBN3G51ork0ZgrunbEUD85ejkfnXKauel8QNQ7uzqzTTP2Pk8nhKgLtF5XjVQUx5lAMNQfB7FS324o/cRTffv0pNn37JTZ/+1W99u1Xn+J0wvFOTcvp5uSM0c5h8IKbPqV72LztA0RG1iyitsjPz1dBrH31uCv/+m+evAgLh0/A24c3Y+3x3eqq1YqaxqWMUgtzsOnMUXyiLXMy9xwuHjlFXfX6wCzt2DlXssAs0ksM9v6rdon6A7n6UTDjC4mqqqrarHVS6ohoIBjkb/+9npaWpm6pb3DcX9kCenc5Bsn0ctvUizB36Bi8If1MJ/ZgT+opVDcYlJTfw8kFWdh45gjWxu1CSlG26me6x+hnmnu5fs49XgXSEFH3s/l6qz4w+Q1fWdnxwAbqepJVd/PmzXDS9sGWkVH61N4v0MNbXZArfSIyNvFNwkEVJCljEY6qLRYczTiL9QmH8GHsDlVqeuWY2SoD70OzV2htOa6dMB+TQ4erC4+IqAuZnGAZEw2bizNOnDiB2NhYfQYREbWk+wNffAbeFX7XTVqgsre8vn89Np45ivLqln/EyJXqN0y8AKHeAfj85D7VeRGXlYKcsmKMHhyOmyYvVGkJJUpbSkAQ9RfOkYHqx75w8nKFybuu4y3CFKAysjhKPH0S51KTkZudhdyc+u1cWjKyMzP0JTuPv8kLHk7dm6Lf2G9KFi7J4kHUFrm5ueq2rx53rxw3B0tHTsY7h7eoTpniynJ9TtPCfAJxy+RFGOo3GFsSj9Wmds8sKcAwOa5OukB10kgnvwwUEFHXMfY7HPAlYQRiOjs7ISKYgS80MAzyt/+O4X6wbzH2V5Kp2BZgzzzaW8nA44XRE/HmwQ349vRhlFa13M8kV/rfNGkhhvgEYd2pg9iTYu9nyiotRExQGG7U5j08m/1MRD3B5uaqmgTfyX6Iei8pNyJlR6yhg7Q2WJ/au0mAyj0zL0GYTwBWH9yIfWmn9DnNWzR8ApaPngZnsxkfx+3EgXOnEZ+TpjK+zI8apwIvpdS0lJwmoq5jDRkEW3ioyka4YcMGfSoREbWk237NGld8GpkLBopI/8G4bPQMdZK49eyxFrNP+Ll7qtrMd01fiphBknZwt4qu/vLkfnwRvw+fntijHn96Yi8ySgqwKHqiygIz2Kt3X4lE1FbuC2PgOjkCLqND4D5vBEzBPvocwM3UONiksqL5zj0//wAMiRhaL2tMZ3CGWf3XnWw+3vo9Xj1PbZeTk6Nu++JxN8TbH1eNn4t1CQdVFjSLVQo2Nc3LxU111N878xJMHTICX2nHzPeObK09dn6mHTM/OrZTZVI7k5eJeUPHasfOy1XnPxF1DSPwRTruS0pK1H0auOTKWDHIzxVeHkzNTANDcEDnZHyp2fUNqj/5T9vb5k9ga+VCG2qesb+SzGU2196bZTfcNwhXjJmFT4/vwebE2EZX7DuSq/tlgPLuGUsxNjhCZYb5X+z2unNlbR0fxe1QZS+kHNKFwyeofqZQnwB9DUTU5aTfSv/dblzAQr3T7t271a1l5DDAtXsviuuoFaNnYG7kGLyybx1OZDffpyi9p0O048tjcy/H1RPmqf7Utw5uVOMRxjFDMvF+ELsN608fhovJjKvGzVUBMM68uIioazg7wzI6Wt2V/Y8EwBARUcu67axEoqGFkfp8IPBydVeBLKmFuerk0GpreuDO3dkFl8RMxYOzlmN6+EgcyTiDNw9sUCeVWSUF6nk1VgtKKsu1eWfVoJ4Exfxn/3pVm1lSFfIEk/oDlxGD4XHhKHgsHgu36VEwedZlfJH64+0REjoEQ8Ij9Uedp3PDaNrGMWNHYmKifo+oZdnZ2eq2rx133bRjogSyVFks6ljXMF27QcoISsf8Q3NWYP6wcaoW9ev7v1HHyKSCrNpjZ2lVBeKyktV0CYKRtL7B3n64e/oSdZwmos5nBGzKVfPGbwAauIzjEcsc0UASEmT/HSPf//MpV2o9dQQ1+ze3uVni9snOV382tZexv7L6995sL1KOSAJZckqL8Hn83mYDxOWc+uIRU1TGQym7HZeZrJ0H2/uZ0ovy6vqZtHPloxlJ9n6mE3u08+lvEek/CPdMX6qtY2CVKSfqScbvdga+9G5Gn5xkfOkL5ILcq8fPw7tHtmJPykl9amODPH1x85RFuHfGJYj0G4Qv4/fjf0e345uEQyirqlTHGumbkWPP9qTj6pghQZRyHJKy0jdMWqiviaifsNlQkZSK9Df/p7X367Wcz76BpRszslsiQrUTOzd1gSOzghERNc9IgtBt0RK15Tn6SDT0+ZAUgpePmYUHZ1+KWRExWH1og+pMaEj+BDL//lnLcc2EecgtK8ZbhzapgbmD6WfsCzVDSj5I2aQ3D27ETG0dowdF6HOI+jBnM8yDfeAc7g+Tl9t5RZnk5ebg5Ik4WFvIFNFnuDjLXlvd5ZXz1Fa1gyzy/ekD5MTk0lHTVRDoBcPH49V965BX1vT3fWJIFO6btQzXT1ygAlveO7xZXXm0KyUezV/vqn0mNVUq+9pbBzdhvLYOGQQgoi4g5/v6cauvlOiTrIyy35QrqIwm6eb7Izk3avhepZxiV6kNfGGZIxpAQgLtwbWVlZW1WUSo96sNHO+FZY7kXFmyCT+gnSvPHToGbxz8FkUVTR9jpw8ZgftmXoprJ8xDQXkp/qudK8sV+/vTEvQlmibn1ZsTj2L1oY2YGj4CE7TzZSLqHsYFT0bmVup9qqur7YFJ2v7Y6luXobo3UoEsky9UpZ4lYFICVJoiF9KuGjcb98+6FDPDY3A8O0U7vmzA16cOIrWw5e+izP/61AG8vn89Lh8zE37ufS/bMFFTbBYrstZ8icwPPkX+5h1a21mv5X6zGRlvf4Si/Uf0Z3QxdzfYvO2/pY1zVSIial63Bb60VOKnP5HBuEfmXI5VY2ejoqZa1UaOzUjS59YZ5OWrUgFKNLWL2YyPYnfio7id2J0Sr57XVofTzyAxPwM3TGZkNZGjnOxMbN34Nfbv3jZg9j9EjvrS935YQLB27LxMBYFatf88nF2xK/mEPreOr7un6uy/bdpiDNaOo0YJwG1Jx1VWtLaSzpw9qSexcuwsfQoRdZWe3BdJMIdjcIc0Cfhoaptk3nvvvYff/OY3tW3Hjh363PaRwJIDBw7gz3/+M5588kl8/vnnvSoAKC8vD6+++mq999qVpRSNQExPd2aopIHDx9PZiP9DYWGh/U5n0Fbq5OoOJ7dmmoubCpCgjqkNHO9lZY7GDI5Q5YekpES1tQbOJjMOnWt8sVSgp4/qZ7pl6kXwcnXDmuO7VMnPndp5dXl124M5JQPM8awUXDthvj6FiLqazc2+3yktLVW31PtIpgX1W8LDvVdf2CsX40ogy+IRk+xZcKsrVGBjQxIkKccMObYkF2bhnSNbVDm8Y5nJzWatb0gywUhWGF83T4wPHqpPJeq7bDUWZP73I+R9uxWlcU1nSbKUlKJw137kfPo1Cnbu06d2LZsXy+EREbWVk62Z3mg5kZOrkzrL9773PRw5cgQ1syajZuYkfWrfMszcfIeVdC4tHzUdi4ZPRHlNFbadjUNqUQ6eXn43Lnvj1/pSdpLlZcnIqYjwC8Jnx/ciNisZyQWNrwKTdUb4BiG9OF+dqDZHIrglpeCq1b/VpzTtrMVPv9c1bh8/DdH+dXWgLdpXa3vqWWxIbjl7jaGzn+/oZH4u/ht3SH/UsrsmTkeUr7/+qE57t8cQExCEMYGDEeLlAxeHklTV2o+DzNJinMjLxilt+6hlN3nMRYQpUH9k99VnH2HLhq/Uff/AIPj5BSAlOREWPb23/BsKChqMi5ZdgYmTp8HFpfUOzF3bNmLth//VH9n94W8v6/fs3infiVRrnv6oe7j/8y0ZPcRDDz2E6667Tp9K1Lz//Oc/ePPNN9UxV469PaWlY6dYOGyCdkycDDdnV2w4fRin8zPw98vua3TsjPIfrI51I4PCsDZuFxLy0nEyO61Rhhcpixbq46+yqFU1UyZJLBg2Dj9aeI127Py/Fgfmz/fYyWNj03hs7P+M49Zf//pXTJ06VZ/a9eRKzFOnTuHYsWOIj49vcvDAx8cHMTExmDtXO7eIsGdNlIHpn/3sZ9iwYYN6LH74wx/innvu0R+13ZkzZ/CHP/wB+/btU7+pRo4cie985zu4+OKLYeoF5UmTkpLwox/9SP02M7zzzjuYMmWK/qhzybFIjkk3LQvH7Zd1fhlKot7qsu/thtVqwzPPPNPhf19Vq/8KS0Ks/kg7z3H3gPOFq+CkHT+b5OEF84jxgJklajrC2F915/lza+fKUhb7ouETYdXOejcnxqqSns+suLfRufLE0Cg12Dk8IBhr4nbjeHYqEvMy9Ll15DdyuE8gMkoKWuxnWjVujip3tLKL+5kmB4fhsujRcDWb9SlAdlkZXji4U3/UsvN9/uKh0ZgfMQzmJgLGCior8EF8LFKLWw9eWxo1EnPDh6oM0A2dKcjHm8cO6I/aZrCnFyYOCkWEjy+8HPox5FdLXkUZErV1HsnOQGULv3eob3HecxjOe4/gjjvuUI16n7i4ODz66KOwhgxC1bXL9andq6Vjhoe2r7hL229PDhuOPSnxOJ2boS68XTZqGu776Dl9KbtH516u+liKKsuwN+UUticfV9nlG5KMMMHeAUgvzmux3+TFKx9RF+f+a/eX+pSmdfXYBNH5sNXUIPO9tcjftAM2qz34y+ztBd/pk+EWEQprZZUKhnEMiHENC0bUDx6CS0Dj/rLO5LJxF8xxpzguQETUAldXV3h4eHRf4Mt3v/tdHD16FDWzp6BmxkR9at/S0smlXAmzZOQUbDt7DHvTTiE+Ow0RfoPwb+3Er2GHxM1TLsT1Exbgd5vex77UBO2Ha+M/QbhvEC4eMRnDA0ORW1aEDaeP4HhWchNLQqUifGrJzY1ep6GuPrl89dJrMGdIXWd2tdWCV4/sw3MH2tbh0NnPdxSfl4MfbPwciYUt10EcGRCEvy++HMP8Gg8Stmd7fN3cMH9IFCYMDkG0fxAivH3h5+4OZ6e6wY4amxWF2r+z1JIinCnIRWx2JrafS9J+dHTev7u+RnZHtoJyWCuqYR7kBSeHEi1NBb6cPXMKO7dtglX724waMw4BgYOxffM3OHniWL0SR2FDIjB/0VJMmzEHTg5/g6b02sCXf70tl5DzBJfa7PXXX8fq1at7deDLilEzsHz0dBzJSMTO5HjEZiapK1VXX/d4o2PajIiR+OVFN+GPm/+nsqNZmzh9kU6dJSOmIGbQENVpsyUxVpUObOpUZ3hACJ5f+SCuePM3Ta7LcL7HTh4b6/THY6Nsu5vDQEtfI9/8cktNi52YHWUct7or8EXew8mTJ7Fu3TocOnRIZTBJT09XgTANubi4ICwsTAW6XHjhhWpaZwa+bNy4Uf32cXztBx54AI888oh67Z7Wc4EvEbj9MpZnpYHjsu/u0s4x0LmBL95+cLvnZ3AKDNanUGfqbYEvchX+0pgp6tx3T+oplYUlzCcAr1z9nUbnylJm4t6Zl+CPmz7A7tSTTR7b5bnSzzQiMAz5FSXYePqoOv9uqk9qYugw/HHZHV3ez7Ry5Fj8Yu5F9YI7ThfkYeVHb+qPWna+z39s2lzcM2kGXEyNz+eKqyrx9N6tKvilNX9bfBmWRI1sMvBl17kU3PPVh/qjls0MjcAMrY3wD0SUnz+CPDzh7hDIJn+pEm27sspKkJCfhwTtfHl7WhLOtnI+3x1kkLB4/xGUn02BtZ+UizRp5/kuwUEIXHyBPqXrMPCl99u8eTN+/etfwzIyCtXLeibzenPHDClndNf0JZgdORrvHtmiMujmlZfg6vHzVJ9Lw8CXz+54EgfSEvDmwQ1IyE3Xp9aRIEkpd3fhsAkI9PRGYn6WKmuUVVKgL1Hfd+ZdoR1jAvHTr9/QpzSNgS/UW0nQS8Y7a1CwbZfK+iLcI4YgaMXF8IiOgktQAGza7/vK1HSUnTyNzA8+U8uIoEsvQsh1K/VHXcN531E47z6kxgRkbICIiBozAl+67ZJDOWGy6/yO9Z524fAJqrTROu0EcO3x3SropSVyNXqN9oNwb+qpRh0MPm4euHHSQtwz4xJMChuOuKwk+Ht44Y5pi1VpBynz0FB2WfMdJWQX7uOLuUNar089L3woQrQT+vMxMzQc350+Dw9MmY2bxk7GwohhiPYPhK+rO9ydnWubn/ZYpst8WU6Wl+fJ8weqmuQ8lH0Vi/J1cajYdhq2ipavXoqIHIbFS1do7TJMmjIL0SNH4yLt/rDoGH0Ju8yMc9i64Wvs2SVlj9qWrrPX0XehXTE4SdQTpDP92onzsSPpuErBLp3uLZFjp6TblVTtDQNV3J1d1MDA/TMvxbyosTiVe06VEbx1yiLcNW0JQrwbX3lRXGVczdS4c3qg4LHx/C0IDsetw8fhjuiJfbLdEDUGYV1Vi70bj1s1NTXYtm0bnn76abz99tuqRFFycnKTQS9Cpsv8rio/FBgYiCFDhuiPtH2UuztCQkJ6RbaXnmD8DmxqYJWoP6v97vfg+bvl5GHU7NlQ1w5qv4cqy2ErK1aPq794G9Wfr4Y19bRa3ibZZvdvrvcca0qCvAlYz55A9foPUf3pm6jZ/qW2822wj9WWseVloWbvRlR//Z5arvrTN+xNe52arZ/r62r695hsl2yf42vL9gtrhrZP37hWbatsg62sRE3vbLX9Vj34NzPMjRyNq8bPw8bTR7AmbpcKemmJnCtLyYldKfGNvnNe2vnVdRMX4N6ZyzA9fKTKBiPTbpt6EW6fthj+TZwL5HXRZ9yXSDDN3CGtl+4YFTgIo7XWVNBLW0X4+OHeSTPxHe2897bxU3Bp9CiMCwrGYA+veufKsk3h2rLTQsJxzajxKivj92bMxxUjx8KtBzM9VWXlIOvDz5D96Trkb9imrpbvDy1v43bkfrUBZQmJvWK/QD0rMzNT3dq8u+j3UwfJnkfGEiTo5ZV961SAigS9tESek1yQ3WTQS5R/sAqiuX3qYvh5eKpxDrkQ6b6Zl2Dl2NlNBgqeK85DwHn2GRD1FFt1DTLeW4uCLTtrg15cgwch+Lor4Dd7GlwHB8FJ+y1vcnODx4hhCLj4ApUFxlC4fa9+r+vYfOz7nZycHHVLRESNGb+DB2bvayeTbC8H0s/gy/j9TaYFbAvpYLly3Bw8OGs5LhszA4e09b17eAs+Pb5X3W5LisMFw8ar+avGzqn3g7qyYYcTNeLp7IKZYS0PmkknwZywSNWZ0FHS2fDI1Lm4cuR4VcZB/p3F5mTi7bhD+M2Ob/HbHRtr2292bFDTj+dmqeVkeXmePF/WMxBVbjuFqrhzqD6Vicq9ibBkFelzmubs4oIQ7e8aFh4JN3d3NaAUGRWNi5ddgZGjxsJZ/1tK9hcV/LJxHY4c3NvsQFjvZv83z8AX6i9umLhApWr/9MQeVZaoI+TYeemoaXhozmVYOW42jmUl470jW/DJ8d3a7VZ8e/oIpoePUJ38t0y5sN6gczXTgvPY2AmWhg3HguBIzB8c3ifbhdq2RzZXLuO8dXzwpz3kGL979248//zzKvhFMrc4CgoKwujRo2ubBKB0tREjRqgML5dddhkuvfRS3HnnnViwYAHMfTg7UGfgOQwNNEZCsx4NfDm2FzXbv6htlj3fwpZ9DjUb1qBmmzZt70atbdKm2Qe+bPnZqNm5rt5zrGfi1HqqN3yMmt3rUbNPe07sHtgc+iFslRVqngS8qPVqr6OW27fJ3uR1dn6N6vUfoGbTJyrAppHyMrV9jq8trysBNzXffoiaXdp2adtqObxd++HYsX6XtuueY1hLJFAlNvMsPo/fh8KKjgVqyrnyFWNn4cHZy3HFmFk4nJ6oMgF8emK36mfacjYW84aOxQOzluOaCfPr9TNVWdjPJJ+HlOaU7IctuTBy+HkFiU8NGYJHps3B7ROmYpp239vVFSlFBfj8dDz+uHtzg3Plb/HPg7uwIy0ZxdVVCNXO46Rc0/2TZ+LuidNViaTuJgOGBdv3IH/jdlSmpduzvfw/e38BGNd15v3jX2lmxMwsWZIlW7ItW2bGxBBwmBtomhS2tPt/d7vbfXfffX9t9213S1tmSJukYY7jmJlRtiRLtixmZhiN/ud75l7pzmhEtlj345zMXAbdOee5z/me5xH22XQojADQVVOPqvc/QVftxEfV0ZlYekXzLhMfwVELhYxMZ/RaxhEZ9ZYiyFuBUWO+uHwHnltyBxaGzcL+vMuizTiC90Wb8erFQ1IkwzR4X1pxlxzIRMGlSpuoj1z0NIs6UxDa6eWvvWsVvSi/HUZ6CX10J7zmzZHT9jiLdjpgS18kMHPT2IuFezzc5Wdj4+B9JTo6Ojo6gOE/BMp3Gzhysrt74Hy/I2XXrl2orKyEJSocloixdziPBX7O/cPsB3p449nFm/Ffh99GbZttxx2js9C58MqlQ8ocKwuEcTg3OBqvZxyVRuGKmGQpZmGqpNrWJnySe16qs0saa2TOZaq0b9SWoa6tBR4urlIAwxRIFNmws9Df3UuGtbU/jj31PW7Kt7FhZ2KKHKWiwhH5FypKcbqsWJkzOKO9PXMd029DZwUdPsxLeqa8BDVtjp1GC0LC8PicNHi7usrpVnOX3FZ1/gx1PvfNTsHzC5YiNSgEzs5OyKypxF+uXsBHedk4WHhTHLsY2bVVvYWdetfrasT3auTWV8PP1R2hnl6I8PLBLL8AtIvjc72ZRMu7FyHe0OT3nq5umBJDYAjxkdPzTdHwcbIaeYPBv7Wff6AsTY31qK3pu4ft4m/PaW/xnISE9Y3E1lJcmI9rWRnKlJUt2/rCFTIF3IWsc6i9VgBzUd3ApViUikb0tHTAydUEJ5fbewE0nL3M3HRYvHgx5s2bp8zV0RmYCxcuyDQWlshQUcKUueOPo7ZTOlRW7MAvT36Mogbb0QruYtkDqSv7tWlMAcj2j4IWZydnpEfGy7C9mxLSpLuFAppPcy9IMU2XsF/YQcC2k+0k6/91s+Yhzj9EtqvlzfXSOXS/OM6r4jiDdUfdbtupt43Tu218LHYuXJURb2bRfjW2tKK9swtGk1HeIz5brW3taGlrk0IeCjKtd25yYBC/pcviN5PfMvrOE7XduuOOO2yin4wmdFJdvXoVP//5z3Hu3DllrhW2lw888ADuuecebNq0CatWrZJl2bJlmD9/vhTEJCUlIT4+Xq7P9n3fvn24efOmnCZcPz09XZkaPgytGRsbK4U2S5YswfLlyxEWFiZ/c5MBioP27NnTO2qVPPTQQ/IcxwK2RUw/lTrLG4uS++ojHZ3pzt92l8Ji6cGdd94p06vdCt2XT8goKipOwn4xpq+Fk/vwOre7zx6ApbSAL0LWQod+jwXmi8dEA9XEilSs1QND8kI4h8fCUlUmthE2GJcp2zh5eMNyPcMarUURDjt5esO4cDWcTC5W0cvRj9F9RhyrJE9sI2wK+043HqerEz31NeipEDZDSxOcI+LEe5LGzmpthvnkHvQ01vUdW9iFXL87R7yfmZk6pUfOMy4a/j0YCWp9RZ+VJWp87GdHtjIjsDAK8H8feRvVrbZtNKMEc8S9va2cHBSJhRHx0s/E0fjLopJwX8pKbBG2cktnOz7OOSttZdretIfr21twvaYcdW1NcDOZhK1s9TO1dnagShzT183D4XHsuV1bOTkgGOuiZ8FFIw6tE3/7V7Os0X6G4na3Xx4eLcUmtIkIozOzGBTBPEXgpcJOulRZLqft4XKmSprlFyhtvC65fbe0sVWKmxrx/vUsZcqWJWGR+HzaMnkNXi6uqBC/jXdzM/H6tQzsL8yTaYxoP/fZylW4Jj5zhb18SfxeaVtEePogxMNLCnQ8jS7IqatG6zgO9ulubkHlmx/AXN8IU4AfgrZuhM+yRfBOS53yxWtuMizClm/NvQn3mCi4RY+NTUucSyrgXFohU+ONVfpJnduj18cygX0bjtoM1v3Lo5Lx42PvyfpHy9yQaJkK+oOs08ocK08u3IDsqmKcL70h+y+YhvrO2Qtler1DN6/gYF6G+MwQbYRom8U+ixtrcLO2Ak0drUgS+1sSOVv6V8qb6mQ03fmhsYgPDOt3HHtut81ICwmTIr/NsYnYEBMvS2pQqPQrDIex2F4tK8Jj0KikohsKprV7Zl662E9Cv/2M5HxUmFaaafLWRsVhjSjcv1qS/IPEcjc0CFugYxT7+qYL1R/tRe2nh9Cj3BuX0GCEPnYfvBekyOmBMHh4oPrjfcoUELxzm/JtbHBqboUh+4YcyLN161Zlro6Ojo6OFg44ZIr5vjexMWa6jvAL8vCRHXDFdh13w2F5dJJMy/DgvFXyJZ2RW4I8vaVPyN4tTrU2VdtMB/HWlWPwdXXHM4s24Zn0zUgO1nPlO6JFvOh3agw6jsBZFzVLmerP6shYmT9ZpamjQ/wdhtdBsSkmQYaYZR5mHnNfwQ386OxRvHHtisznXNZiK4qic4Tr1ra34XhJAd7IviLX53bcnsuen78EO+KTlS1mBj2dmggMlh70MCn+LUDnT+ysRJn2KCYuoTfKg1Rxl5bg6KG9cnqkcPsc8bcq238e7UevD16OiHI4F237stG2+yq6rlfKa7pV1M6y6VqX6swsKOI0ORuRX9fX6Tpc6NR5cdmXaC8gAAD/9ElEQVRWPLpgHbxEW9hu7pSOee7Pvs6mKIPh3t/LPIWXLx2Cq9GEx9LWi7Z3K1JCrGHLZ9ovajK2jRS10IFEhwzh/KnYNpZX1yK/pFyWCvGdtLS24WYx51WIzzK0tfd3VE5XxqPdooDjvffesxG9MK3Q9u3b8ZWvfAVPP/00duzYIaOtqIURWJ588kkZkSUlZXBn1u3g4eGBxMREKa4JCgqaNKKXiWAmX7vOTMda/41mPch0QF373+5LIWRXLIW5ypqO6elsR3eWqDM7h98eWYrzZKohR/RYutF9/pAU2PQ0Wts+iXjfdQ6JhGFuulXgYrIKaElPWwvMGSdhPineycyDd8731Fag+2Y2D6TMGVv66quJtRA5uInCCwq6R8rSqNnSVn54/mq4m0xSNBzg4d0rWtbCNKKMLvzO1RN4/fJRKQx/atFGmeJiTnC0stbMgqKXZkYsUWDUQ4pjBmJ+cBgS/UQ7r0y3iXeT7mH+5ilUeW7eYiyPiJZiJQrAf3T2GP585TwOFObhRj0Hw1kwy9cf84JCZccmYccqRS+MCPOri6fw18wLqG5tQQDFSrNT8HTqIulzGi8Y4aWz2hoNxW1WDAI2r4X7rFg4ubjAO20e/Nevgte8uXLaIzlRTnsvmi+nXaMi5PSkLRtXw3/TGnGRFnSUjfzdVWe6MrFthD1JQZFyMC59IyOBg44YKYbR5TfEz5dXxUFEkd4B6LJwwIxtu9Ha1SEFlC9fPIQj+VflcZ9feqcczBvhE4AmilbHmFgff9w/OxWPJM/vLdtmJSlLh2YstlfLY3MXyAhgw2FTbAIenbPA4X5Gcj5zA0Okj+Sfl6/Hl9NX4rPi+2dEG6AtnMdlXIfrchsdKxRs1u453Cd6CQlC6CMDR3rRYm5uUb7p6Ojo6Ew2xl/4Ms0cn+xUuxVM4iX08bT1svPv09yLclTO78/uQWZlkUyd9OKybTIyjD2MCLP/xmW8eukwThVdw8LweNydvFRZqqOlzdyF5q4+o58dnhxN48gBwE49LlNHCXGUTnVbi0PnkD3cjmpvOiM6zGZ8cjMHv754Wnbq8Rx4PDop7k6YI3M2/+Oydfjmyg14IW0ZYnz85D64Htfndtye++H+qP7m/u1ZERGDr6avkkbrV8Sno3VmOlT3UfRyx/adMu2RQZP2qLnpVke29yAnMwNNxZWwNLYNXWpbZOSXjkvFaNt/DR2Xi9FjvkWn7TSrO3XGnkktkrrFU+PIyacWbkSIp58chfSaaAv/eG4vThZe6w3jvjKm/wtqY0crDuVlyGgxh29aHTSMFiOZzPdpDJgsbSNFLBTFfHPFBvyTaBe/tng1/mHpGvzryo3SOcMoNVOtbaTwpaG5RZYyxflf29CEmoZGGQmmpl58NjuOrDMtUZ6TsRQ9cMTl3r17bVIYrl69Gi+88AKWLl0KHx8fh8enOIbpiIYbiYYCG0aD+elPfwoGy/z+97+Pjz/+WEZMcVTXNjc348yZMzh58mRvqa3VdAhraGtrk9EFXnvtNXz3u9+V+2fhsd555x1kZGTISJyO4LGLi4vluajnxvL73/8ex48fn3RhkGdWbaujM0b1n2jDuzNO9aUQsis91daURQPCqCtNDXAOi4HpjodhuudpmDY9AKfggetDClqchJ1gWLQWprs+A9OOJ2FcuEaKW2RqpHOH0aMZ3ezk5gHj2h0w3fkIjOt3wrTlIRjvfBhO/sHKGoLODpmyyFLaF2XLEXK/og40pCyWx+XxjSvusI0UMw25ZT+TsxFPpG2Aj5sn9t64LG3fP57dI1Mc3Z+yEp9ftg3pEQnK2n0w+ssBYSsz/dHxwmw5cv9eYVvPRLp7rPauCn/HyeLZpcDFEeuj42xE4pUt4pkdxt8v2N0Tn0lZJEUvMgJfVbkUvdDmLRf7uCM2EV8X9vG/rdqE/7V0Lf5+yWppN39j+ToZUVG13bNrqmR0m99lnEWF2M5P/DbuTUxxmCJ0gbiGLyxcLm3lf1iyBhuG2UE7JOIdoUexxUx+vnD2cEfVh59aR9EfOCrnV31gna7+YI+cbjx13jr9oXV6suJkNMA91jrY0NIxMlGBzvSjz+4fu/ebW4HR5W7F5JgfFivbhormerx55RhezziCX53eJd/36Xd5Ln0LAtz7p8XNrSmVUcReuXQQudWlMtr9ovAEGVl3JkO/CX0Q2jbBEVzO+tikiQw2UiiEfCIlDV9bvEr6R+5JmCv3yWi57kaTFG2yeJhMCPPylsu4DtflNtxWFVPOZJouXUW3eHeXiOc+9OF74b0w1To9BHUHjyvfBGNh89uj1D9j6V/R0dHRmS5MgPDF+jFdYAhYooZBHT49Mp0RBS+fik+Gmz1ZlC0juryTeQKhXv4y7OAXlu+Qo2609Ih/N2rL8WH2Gbxy8SDOlVyXjmSqq3X64OjwosYGZcr66CX6BSIlqL+yOS04HPG+ffevsbMd5XZRWhxBZ8NDyfMxLzhU2h/HSwvwh4xzvWkY6Bz5X8usTooX05ZJA/PxuWl4MGkeloVHIcDNNnUPt+P23A9HCSUHBMn9azskmf/5hQVL8VTqQrkvfnKa4hodW2gMxicmY8Pm7ZibskCGufLzD8CKNRuUNfqjvsY6xgkGsY8RG5kWC8xFtWg7kgvzzVtN0aEbtjojYzILXxhunW2Zu8lFmTM8eEUHpBP/MD7JOYebdRWyDXw386SMhubp4opHF6zFl0TbyRDx9hTWV2HXtbP468UDOFmYJe8RQ7rPJCZD28j2iiOOnhVt4mNzFuCOuEQ5kpZheTnNka/PpKbLDgEyVdpGRgBUUcVBasQxiZg3s5wU1msdq7qovb0dp0+ftknXExkZKVP2MMWQzb2/DQoLC/Hb3/5WplP6y1/+IgUqL7/8Mn71q1/hxz/+MTIzM/tdI4Uyb775Jn7yk5/0Fu15Em6Tk5OD3/zmN/jRj36E3/3ud3jllVfk/ll4LC6jqIVpmOxpbW2VqWS/973vyXNRz43lj3/8oxTC/PKXv8S1a9fG7G8wXNTnfoJPQ0dn3Jmsdb5zcCSMmx6AcflmGJdshHHFFjiHDhLdw9kAw2Kx3tq7YFwqPpdugjFtFZyMJlhyr9ikYoJoCw0LVop9i33OXgDn8Bg4J6TCmL4exmWbALGNSk9zA7qzLyhTA+EEY8piGNffaz0uj79EvMuNQZoj0vs3m+AKiyP3eQbadDnDgdvsuX4Br18+gt0556Xte6o4R/qY6Gtiqu4n0tbji8JW9nLgZ6Jt/VH2GRkp8Uxxrmw/onytEflmEjfqa6XgWyXA3QNromKVqT7YebkwJKK385LRWa6LbYfz9DC9BYub+E3cbKiTkVsY8ZD7ILR1n0xZKCMCyBQaETGy05J2LgdUsdNStYUrW1vwXm4m3sq5gkZhM/C8aFNr7WCKxyk6ZzQY7uMJsW8OxmJ0x1FF+Q11NzTCXFOLbkX03d3YhK7qWpjFp5xua7dO108uka5DRsmm1Jn69NrUk6x9v1ZdIup3x4L/wahva5YRv+hPYQSX4oYa7Mm9iNcyjmJ/3mWsjJ0jI4g9mLpKDuDVwsj0F0rz8H7WKbx+5Qjy6yoR7x8qBZgzGfpP6EcZDPYHxPlaB8LeCowW9vm05TKSyxpRh/u7uaNKtAN7C67jx+eO4Vsn9uPbJw7I8q3j+/Hjs8dk6jymt+a63Ibbch/c10ym4XSfHeqeEAfv9PnSBrS2VwOnrGq6kIGGE2eVKcBrfn+xqY6Ojo7OxKFb77dJY3urDPW3ODJRmTM8mB9z17VzMs2DdjQPc2eyM+/VS4dwpaIQdyUvkSEHd4hPN6NtB2GX2Mfp4hxpoBY1VOGxBeuUJTqE9/VCZam8Typ0ADh6sV8qjE5fzaixwoZ6NGnC2w7EysgYLBfbMixtfmOdDEnLcLQqcb7+uDdxrnRScHQ7hS6uBsOgEgZuz/1wf9wv98/jqCwKCZcpITxNLtIR5iU+F4dFYnGoHvXFEXzxU9Me3fvgk7hr56NYtGSFsrQ/7CjTviyaNGG5OX9+2mL4J8bA2d9j6OItnilnZV/iebRUNqLjYhF6Okaeb5uOSPmpqS90dKYqDLle3dKIJVGzlTnDg86Vj6+dlY4dfldhRJc91y/ib5eP4Gh+pmwzGTmNDhqmQ9LC9tfqoDmNS+U3ZSj3mcRkaRtXieMFuXv2Ew5TMMJRStvjk7Alrm9E8lRoGyNDgxDg44UAX29Eie+E38OC/OHr7Sk+A+TnTEFtt8aKuro6ZGVlKVNW0tPTsXDhwlETvRQVFUkhCUUsPFZTk7WzhqKb3NxcfPTRR3jrrbek0EULI7Tk5+fjwoULvcVevMJILRSovPrqq1LAw2lt5Boei/ug8MY+4gsjyjAaDAUvjHjDc1HPjdTU1MgoMjw3HoPXMZGodpVuw+jMNPpeA0bx2Re/JycXNxnxxFHBUB1OFKakLIFh9nzxoqO859BWchl41K+TXxCMS9bDOTBUHl92Ant4yXq+Oz9bGGh9dZQT2/aFq+DkYTdC3GiEYU46nLx8lRkCvh+V3BSV5sDvRnJ/SzfICDXyuDw+RS/CFhgLet8DJ7i6oki8Sdi3y6NHlt6xW9h3tJU5UIppjFTq21rkwCtGDj5fekPayvQz3TNnKTw077uEtvLZ4lyZKvRGbRmeWjjwoJHpCkXX9ZqUHRzFT5tSK7omacL+jNV0XjaIv1tuXZ/NOxCMbLg9Phl+bu5o7uzA+9czcaLUNp1YuJe3HKnP+oPCddVvSDuYIpZHkxcgPbQvUhPTH72dcxWnyork357+p7sS+iJhsnOTna207Wkru4vf5Pzg0NEXvigE3bMVYY/fD/91Vt9L4PZNcjrors1y2mdJmpwOvm+bnNbRmQowgrREbSsmCfn1FVLMyBTQI4FtBduGhva+KFds29lXwbbkpfP7ZZ1zf+pKObhoUUS8zWAPoqY/+tvlwwjy9MHaWcOLljFdYJSwDo0dxDqWfpTBWBkRA2/F7qLYsX2A6J6OYF3+4oKleDApFeGe3qjvaMeHN7LxvVOH8MsLp/BK5iXZFqjlLVFezryIX1w4ie+Kdbgut+G23Af3NZPFLx3FpfLT2d0dwfduld+rd+1D+WvvoeJv70gBjD2NZy+i6v1PYW6wCjedXUwIvms8/IpWO0DbZ6Gjo6OjY4taR46OV3gY9Dl7plflzBfK4oZqmc/SHvWaGfLPxe4Fufd2DEB2VbFUW7MDqKGjFduT0mVYWuZrtocdfn8+tw9rYlP0qC8aDOLena8oRW2brcPCPuxghJcPFoaE946mYmfg+crSYeVlZscc90VHxNHiAlystA0tzaedhXuiIauO3hkK7of74365fx5Hhftysvsd8VQ7NZ2YOrY4i797RFQMlixfjXlp6fAUBv5AhISGIygkTFaSbsLwTV+6UlliJTYuAcFbFsJj+7zBy7Z5cN88B8ZYzW9S/J26i2thaWhXZowApdLWO410hstkflboTLlSXoC7HKTqU8/7wXmr4OYgIsxgnel00BzIuyx/v7VtzdiYsACfX7oVa0X7aA/z779y6ZB03swOGl66k+nAZGgbaduwRmvp6sTxkkIZ1p3lanVf2hh2BKyJsk35ONnbxiB/H8RFhiEuIhSBfj5ynoebK2LCQjBLzI8OC4abS99I92nPGLdbTB2UnZ2tTFlZsGCBTG80Whw7dgx79uzB3Llz8cQTT2Dbtm0IDe0bPU2hCoUnjNwyErrFM8xUREyfpIpmGKXms5/9LL7xjW/I8vWvfx0PPvggPDxsHdh0uPO8XnrpJSl4IYx08/TTT+Nf//Vf8Y//+I/Yvn27TOdEMcz+/fulQKelZeJzkI/Nk6CjM5kZ/aee4hbjhp0w7XjKYXGO7p/GRgtFM87xc0VjPHxXEEUnTv4Oon4wbVKjXYeAp5cUyjhE2BZOnrZ1dE97K3oGE774B8M5fGw65iczFDmwQ/Lh+WuUOX2o7erOlOUyZaWWoUSnTE9xOP+KtMVq25tx5+xF0s+0Iqa/wKa5sw0vXdgv04jG+GnSVE1z+B7R3NUhRdfq3aRFwwiJWqEJWRURA19N5BxGiqnUpP0aCIpNGMGQUGTz0Y1r/XxF6uj97506LEfvM/oh56kwdQXTJGkpa2nCu9czUSPsfNr37FxVOzStj01/W1krhh8NzPUNaM3NE3WNCabQEJkeiNO8mS7CJnYSdQ+nGQmG087ubnJ6Mpf2gokVEOtMPoaqa8cbDsrtNJsxJ6i/4ILtia+rB1Y5SAmtHUxkD9sa9ktcqSyUbYaL0SjTHz27eDNiHbQJ12vFu3p+Jh6et1qZMzPg/WWkLRX6T+hHoT/FERQuMhoXU9wRimbo3xgOaoq8TbEJ8HJxRWFjPX53+Qx+e+k0dufnyvaE6aLt4bysmkqZSo/rchtuy31wX4y4S0HmTMTZZJLClfAnH4DnnERUvPE+aj89hKbzl9Fw6jzaCoqVNa00XbwiU/a1FyrzxW8j9JGdcI8fB1tVqXbUTl0dHR0dnYEZvrfjNlEr5bFyfk8kH147i7khUb2dQyrMk/zS+X24L3UFXly6DcnBgyt+7VFH6Lx99TjeyzwtxTNPpm1wOOKGkV/4wro6Vg+tpsIXfY6euVZbbfNKYh92kJ19sT59o3Rq29tkiNmh4Ij1lMAQaazSufFxXn9nBfe1v/CGDFtLhTUdKMOB++H+uF/un0ZxkuIYOVqcj7MVJVJIw+uiAXuytHBY56wzNOGR0dh61324+/7HsGPnw1iz3la1bRRGsWt0IFxSIgYvqaKkRcNtXV/HLLE0d4oycuHLdK5DdcaGyf4ytC/vMmL8QmAfCpcjhv54bi/unbscnxdt50gjqqm/kQ+zT8s81R3dXTL90fNL7pDztWRWFqGhrQXbkxYrc6Y/k6FtpGOHTpmfnT+Bn104gZezLsrC8LuqUIVPb5idSHGyt42MXuPt6SGLNpKNu5srfL084e46stReU52xbreqqqqk+EVLcHDwqEV7IdXV1Vi7di2+8pWv4Pnnn8cXvvAFPPPMMwgI6BO18jwowOkdAToMGDHm0qVLNlFatm7dimeffVYKbFieeuopvPDCCzJ1E0UsKqWlpXjjjTdkJBjCc6HohaKZxx9/HE8++SQ+97nPYelSq7CQx3j33Xd7158I+p4F+aGjM2MYk3rQ6ALD3HQYFq52WJwYlWUwmLZVG3VlOLDzxlGEFdZ7mlHOEg74GSAaC1MjOYwsM8j9caIo1y4lz1jSZz9PfIX1Sc55JARQhGx7Pxs62vAn+plS6GfaitTQkXW2qJFDmN7incxTUjjM9EdPp2+S87WcL81DW1cnNsyar8yZ/lAkzpH4Z8pLhM3a93xTlL02uk+UzU5CRnxR/YC0by9UlPazex2xJCxKRimk3XqspFAKVuz5fcZZ6Ud6Lds6ev+lq+dR2ty3Hs/Tw9g/wtM5cd6qmDxS/HYpziGcd6ToJpopWBPTPN+LlaU4IOzv0aTtRj4q3/kYVe/uQtV7u1D57sdymp/WaVE001xPTk/iUvPpIeXqdGY6antuP+BioukSddXF8jzcm7JcmdMHo9yeKMzGY6Kep0/E10FK6MGgOKa5sx2vXT6CwzevICUkGs8tvqOfD4X35r2sU4jyDUT4DBuUS/+E1tajH4X+FEdQkBipEZk0dHQMS4DIPqGH58zHlrhEJUVeLX5y/jjezr2KvIY6ZS0rFMh8YeFy/PuqTbJ8Y/l6LAi2pvjmutyG23If3BfT7j2YNE8eQ8t8sc3nFy6T2//9kjVYHz1LWTJ98F6ShtBH74PPisWo3XMIdfuPwtxkFbA6i3dwFyWSL2k8dwlV7+9GuxIlhkLO4Pu2w2/tCrHy6PkgdHR0dHRun/GvlSeXbTgqnCjMkh13q+NSbIxfhqd9nx1vGccQ5u2PpxdtwrPpm/ulLBqK2tYm7LtxCa9lHEFOTSnuSFykLOmDzgsaoGvjZlZIwcFgpxM7xs6UF9uEDbQPO0hj1MvF+jehmZpXX4ur1Zo85QOwKCRCpmkgN+pqkFNbJb9roaL695fPSifFsZICdAxTxU24P+6X8DhqhyRD59IB8h0lV+d3ThzEby6fQUFjvVyuM3zaWltw+sRhfPTe6zh6cA+aGhvg5uaOlNSFWLF6AxYvXY2gkP7OY39nT4Q6+wxZwlz9EZ1oO+qyp7MbvhY3uQ8Xp/6OqoEZA8e5zrRmsj8rmZWFaOvqwL0pyzSdDECHuQsfiLaTKf88XFzxeNo6fGH5dhm6dyRw1NPBvAy8eeU4zpbcwDYH4hbVObM4InE6micOmQxt45XqCvz8/Em8kXMFlyrLxHPQJUuXXRvpaLTSZG4bP971yZQpx0+cVM56LBnbX1WbJmqRin10lNslJSUFjz76qEyhFBERIaOy3HXXXVi0yNYWr6yslFFchgvX1YpeCK/H3d0dLuJ3x+Lp6YnY2FgsW7YMrq59HcVXr16VqZNUKHBhhBdGojEYDHJdnueaNX1RAih6uXbtmjI1/qjtkW7C6Mw0NObN5GKkJzbA+rTftDachD/0AX7sPRSnmm1TJjrcxwSi1leT4ZzOlVyXLenmxAU250P7+QNhv75++SgCPXzkwKjPLbkT7nYpi4aCabYP3LiM168cxeXyfGxNTFeW9MH7sef6BRn1ZabAyAZuBqMUhFRqIqyYhA1Nu1ONkMiUmhSWqFAkzjRDQ8EoAExDxOMwndLBAYQnFG9n1VShy2LBbP9ALA+PlqmzVTrE76mwyZpmQUtTZ4cUtHSK7ZjOaG5giJxPcc0fr5zHfyq28rfF588unJSCmNGkq64BrdduTKvSdnPixMM6k4teH8vkabZ6oVhyXmgsPO38Jjdry/F6xlGx/JyM7sWU0BviRy5mLKyvwofXzsiUedF+QVgR279dKKirlCKZrQ76LaYzhY0NaNP4VuhHGUj4siQ8Ch5KtDY+T3kNtTBrUhMOBAUzO2fPhZ+rGypbmvGSqM/35l+3iTajsiMhWUaGeXTOAlmY0ogDlFS4DbflPrgvij13JCTJY6hw/c/OX4ynU9Px+Nw0PJmShhfTlo1ZeryJwn/DKpmSr+q9T1Cz+yAsnVYflJNoP8Me2wm3CKtgqOH0eVR/8Cna1Qgwog2n6CVw81qx7tik37RnEpimOjo6OlOGcRO+9DoQpmHXUqt4scypKcEj89fIEepaYQtHx+wSxuXLlw7iYmkeVsXMxeLIBPmSOxgMWbssShvCv0camWdLcm1GEWs5nH8VMb7BMNkpdGc6+wquS/W1ijbsIA05bYhBjug5W14inQVDEe3tIx0JzOdZ0FQvHRL21LS1ys44R4boUHB/3C/372owINzTS1kCOZKICu3Xsi/jHfGZUVWuLNEZCTeuZ+Pw/t04cfQAjhz4FGdOHpXzqdrmiPGBRo2nmWKwzmXO8Iq7XYoVURemGqKw2jQbC40x8HQanoNSDaXa+6KtozMEk/1ZocDlYtlNmSqQ7aePJh81l9FxwzzRxwqyZDoiClfo9LfPKa2Fy5Zq2k5S3lSH44VZA7adzEft7+7Vz0E03ZnItrG4qUF2DFDsosJRSQzXzhzihNtlORDaTOa28YMPP5oy5djx48pZjx0T0W4x9dBoQsFLXJxtyq3AwEApLNHC444k4ovJZJLRabTs3r0bP/7xj2VqpeLi4t79aTs7eRymVWptbVXmAPHx8WhubpbiFrWUlJRIEYyWoqIimDUO2fFEvQbdhtGZaUz7Z9/k0j91EUc9N1tTuPWD80UbrkVu7yC15UTRW+dOgj8ZBS6ZVUV4MHU17k9ZCU+NsKVd2Mr0M1EoToHMsugkGf13KD8TfUX2fiam7j5ZdG1AW/lAXoYcvc9R4TOJvPoaZNdU2vx+OYp/aZhVKE4hilYknlNbjcxhiMRjfHzhr0Ryq2xrQX6DXbowDV9URuz/w9K1ctQ90xsRDnxTI7g4Iq++TqYU5fMcqrGVr9VW4b3rWdJWfivnCs6UFTu01W8H18hw+K9fNa2K77L+ojCdmUlvfTBEXTsRMJV0u/jdf2HZNqwS7YG2Ti9prMHH187iz+f3o7WzHQ+INoXYp8uzJ0i00Wlhfe9CjP7CNqde1F3qe7sWtin59ZX9fDLTnfKWJllU1Oi0WrEJYbRaprlT22qKZYbjs2Aklp2JcxHu6S0HL+0vuCFTGzmqvym44bq+moihjuC23Af3xX1y39xOjfoy2y8Qy8KjpNCGwk938azMDw6dksIX/m7NDU3orKyWxdwo/lbKb9klJAjVu/ajdu8R63yBs7s7wh67D36rlqIlOxflL7+F6g/3oL2oL9JL6MP3IGDzGpmuT0dHR0dn8uH4zVZnxDR1tMHT5CZzJH9x+XasYfQXjSGcVVkkR7D/5eIBXK8pkwYo82KGedkaQWRp1GwZspb7GglVLQ3SkTHTHBJDwdHedAqoIX2JGnaQYV+1IQY5ome4oV593dxhFMZsV7fFJuTsaML9cv88Do+nM7qUl5WitqYK3cLIbxTPyfWcTGXJ4IQ7+yHOEDzsYk+Ysy+SjOFYZIzDclNib+fyoEzCF2sdnduFI009TK5YE5si0xrdMXuhTdt5s7YCH2WfkamPCuqr5Mspw/PG+ltHLmrh6KbPL9uGnUp4X7XTfSiYlpBtMsUvM4nJ1DZS9PLs/HQZfpdOIJ5RfkMdPspzHKFisraNtXV1U6Y02kUbGRPGuN3y8emfN728vNymg+p28fPzk9FXtFBQcruRZRiVhRFZGNFFhYKVt956C7/4xS/wve99D7/97W+RmZlpI1bp6OiQAhYtR48exQ9+8AP813/9l015//33lTWstLS0jCgqzWiirdd1dGYS6qM/bYUvBiOcouJt6/vWZlhyL/d2KPQipi03rqCnWROhQrTjzjGz5X4mC2p9NVw7cqxp7GiRtvKmhAX4/PLtWB8/z6ZOvVZdIv1Mfz6/D3m15VIE/tnFWxDpIM1EekSC9DONNMVndWuT7OD0mGEicXYKniorRqsmAqGPaL85Ij7RPxDzNSJxdhoymuJwROJMmeSmpCiqaBE27SDCk+3xyXK0/rqoOCT6BcrOR8LjnBbHGyiyYW5dNVqUNNuM6jieuMdFI2j75mlV/NavUK5OZ6ajtueTsVVnymizpVsOKHpswVo8J9qC+ABrtAqVo/mZMh30J7nncaWiAAvC4vBA6irZdmhhij22FYwmlhoaIwedDJecqhLxjj66UTgnMxzgbRH3h1Fttb4V+lPUVHMqa0VdHurR53eiWIaCxKFYHBohBymxzSlpbsDfsi87HGBLv8pjc9IQ7xcwrGHn3Af3xX1y3zwGj0WsV2K7F17eaIslxxpGaql49R2U/+1dVLz+vixMsdejvBfXfLIfNZ8ehEWJJstIL6GP3AP/9StRs/cwKt/9BLUHjqGjxCpQougl6J6tCNi0RqZCGk/Ux0t/t9bR0dEZmnETvvSpoq0f0w1XgxHlTfV468pxaWg+vmAdvrBsu3gx7uuQaTd34kj+VRli8DdndmN1zFw8v/QO3Dt3mVzu5+aJF5ZuxZNpG+AptuOom5HA45LBRsPPVDiyvLWrL6wyR+YsDo3EIlG0IQZpcHJkz3Cg84fGBl8AhuPguBW4X+6fx3Gkpte5PcLCI+AfEASjMGy9fXyRlDx+qcIMovr1cXbHPGMkYp37cobq6IwWU6GTxVX89lq62kW7eAT17a14ZN5a0XbuQITGWc9oIycLr0kHzW9O78b8sDjpxGGUGLZ3FHzSIfP0oo1yO7azZKSXPxOjpU2GtlEVveycnSJD7BKG230588KAodf1tlGHMPIK0w9pyc7OltFPJjuMKLdkyRI888wzMp2SSnt7u7yGvXv34qWXXsIPf/hD+V2NZEPhCgUsWjIyMrBv375+5fLly8oaViZDmzAFmiUdnUlPT2c7zEd3oevT1wcslhLHUSDGAgPT8Gijvgi7zXzhKMxn9qOnthI9LU3oaaiB+dxBmM8eADQiAicfPzgnLVSmdBzhYjChprVJ2sHtoi14bL7VzxSgEWwzUiIjJL5x5Sh+ffoTrIiZg88K25hRYmgrMV0o/UxMiUSh9/HCbGXL4cEOPcKO0JnGoaKbKNWItdgxmBIUIsUv2kgqVa3NOFKcr0wNjou4j6pgpqXTNvXXcHExGJDGDsoBUmmwM5UicTLetjJHv5uCA6ZX8fdTrk5nptNnT0/Ozg3W+UcKMrE75zySgiLxbPpmfGbRRpv6u6K5XkbX/cuFA9h34xLunrMUX1q+AwvD4+Xy+WGxMtX0A/NWoaihGtnVJegcgXi+ob11RvVLGMQ993RxxcnSIhv/B/0pTGukwkgqjBimDlamSIZimeFEiGebE+DuAbPFIiPxXh/AN3NP4hysioyR9f5w3/24L+6T+2Yqv3XRs+R8NapYc1enFMHwGWAavQOFN+TyyQ7Ta1a89r6M1FJ34BgaT59H04UMtFy9BveEWfK3Uvn2R6jdcwjdzdb3a2cXE8KfeAB+q5eh+pMDUhDTdkO07cq9lOmPHr8fAVvWwsk0AYPO1fMQ566jo6Oj4xi1/dMVEqNEXVuLMOyA/XmX8Iaink4NjZW5Mx8UxqK7JnwvQ8nuunZWGpk0OO+ZuxxfWrEDLyy9E4siErBP7OP1y0dk+MCRoIajUwUwOn0cKylAkSb/MR0NcwKDe3MrE4YYPCeMveGql/kj4s+I+/JROutGG4YUZPoJHmcydFiMOQa7KmmMleSz4pOw6c67sXHLDvmZvtQa7nM8cXUyYY4hXJkaGNWwnRHPgc6MoaGtVbqMjuRn4u2rx/Fe1kkkBoZJYcvTizZJR71KpWgvGdL9rxcPIKe6BNtmL5YOGkZZY8j2E0XX8MqlQzgs9kVGOlKXqQlnGhPdNkZ5+0rRy32zU+CvCIWrhT31+rXLA4buJTOubZyijHW7ReFLUpJtGO3jx4/j6tWrU+K5YMSa7du34+///u/x2c9+FitXroSnp6eyFKitrcWxY8fw61//Grm5ucrc/mzatAnPPvvskGXhwoUDpnAca3QbRmemYn3yR/nZ7+yA+dIxmE/vG7D0VJUoK489zmFRMKSvAzRRZ3uqSmE+pohzPnkVXbtfk2IdS3mxsoZArG9YtAbOwUO/B40nvZ0Jk6S6qmttlud0MC8Db149ho9zziIlJAqfW7oVjy5YK6PBqJQ21kpb+aUL+1FcX4275iwRdvIO6ZNaHJmIgzev4G+Xj2CkA6xocxGK0WcaFL1kVFXYRDtgOogloZEy7QPh75si8cFSFmlhZ6daJ6ii74H41cVT+NaJ/bK8dPUCChrq5bY8NlNQ0IZ2BCMNuChRZbQRCHR0dG4P9berNhWTDfYHOAvr4+Nr1lR4l8puYsOs+dJnwujyqiBFRiipKMD7WafxmmgXgrx8pDiSfRP8DPPywztXT+C9zFOybenURKAcilCx7Uzql2AbTaHJydJCmyhc9KcwrdFsUQhFk4zcpT46TEdHwclwoI+GEb+4zfkKa7ode9Q2gVG+KGIp0UbYGwLuk/tme89zJmUtTfjjlfP4fycP4tuiDfrOyQP42YWTAw5OmkxI0csb76N2/xEZqaVH8SsZvb0Q+uhO+K1agpo9h5X0RtZBM85urgh9+F74rV+J9sIS1B8/g26xzNnVBa6RYTLtXdiTD8J/wyoYPPSI/Do6OjqTnXHzfvY6eyardXibZFcVIcjTmhagvKlOpmZguNkaYSgwLO2LS7dhSWSiXE748kkVNkUwwZ4+WDdrHmrbmvGS2OZDsS3D1KpCluHCEIYMbcjIMjq2lDU3SWUyjT+VGG8/RArjXoWjYg4UDS+VA2nsbJf5TWkYhmhCFY4m3C/3z+PweNMdJ09bx4+5pB49neIFaxScNe3tbThz8ih2ffAmzp46is72dnh6eWPBwiVYuXYTFi1ZCR8/NfVYD9paW9DYUI+2tlY5PZYEOPd1dA3INK07dcaO3nZ3EpNdVQw3xWFf09oo2z+KQvPrKmRearadq8Vnb6ep+He6KAf5tRXwcfeQ4d7pVKGD/8Os0zKtoDqCcrjXH+sXIh35dW3jkPplkjGRbSOdPp+dvwT3zU6Fn6u7rGUrWprxh8tn8XZO5qAjn2Za2zhlGeN2i2mIKObQUlJSgjfeeAN5eXlTog7kNaxevVoKX7761a/iG9/4Bh588EEEBPRFvWIEmNOnT8uURyaTSW6jZdGiRXjuuefkPgYrFNYwwt1EMgX+JDo6o4pqv/SKKUYLRk2hYHegomnXxxxhxxmXrIdxwUpb8Ut9DbqzzqH78gl0Xz2Dnrq+UP5OJhcYF62B0U4wo9OfjPICGRmYUAROW/nP5/dLn9P6WfNkmk8KwFXY9jGVRUFDFQI9fOQ6TMtN3xS3vV5TKqOFjIRZ/mFSIN4yQ22u46UFNnapl3h+F4RY03MSpkJiSqThisQbOtrRoURPCBwideLHedfwt6zLsvwx4xw+zc9Fp9KhzI7WOQH90yqTOF9/eCht/lhFJ9bRmYlM9r6NZlG/LAybJf0mF0rz8H72abx88SDcjC54bME6mTY6zq8vbTT7Dw7nX0F9WzPmhkQjNSRGRgV7+dIhfHztLJo72+Dp4obO7r5obUMxJzgKFc11ytTMoaK1GZcqy2zaAqY1Yqo6siYyVkZUUSluapTty1BwmzBPb/mdbdFZrYhYgVF0n0xZiFgff+lXyW+sQ/YwUiipcJ9qOxck9qWeJ0Wd7+ZmyjbozWtXcGYEbd1EYY308h7qDh6X3wkFLyEP3Y3Qx3bCf90KVL67CzW7D8CiXLNMb/TYfVL0QihsCb5rC8KeehBhTzyA0IfuQdCOzXJbOI9bV+qAjPp7hY6Ojs40ZPyFL5M0HODtcqksX4abVUfcUNhypjgHb2eewJsZx2AyGPB42noZZjDcO0Aams+J71tnp+Ng3hX85vQnePvqCTn6Rr1XIxW+3JW8BBkVBbIjSKc/dEZoO8i8XVyEAW+NxKOGGCxqbJDTw6GwsR4d3WYYhNHDETVjQbiXj1Tk8zg8ngpHBm2InoWdiSnyc6iRQlMFU1yg8s1KZ1Y5Ok7mofNKKW5czsCVS+duqVy9fB6njx/GoX27cPzIfhzcuwtXMy7KY5jEM+Du4QlX1757WFVVgYP7PsGuD97C4f27UVFWoqnDRh+1o34w1OgVY3keOtOLqfCsXK0slCMWteHaL5blyZFFf714UApSHpm/VjpoEgLC5eghRoK5P3WVjIr22zO7Zej3owWZ4gXc6gSmIIIM9+qfWLhejmJq14Ten0lMRNuYHBCM5xcswY74JBm9hX+rmw21+NWlU3jneiYqWwdPVTPT2sapyli3WxSBrFq1ComJfcJycuTIEfzqV7/CmTNn0DGAgIrpgs6dO4dr10Y26n204D1R7wsdV4xeQxHPAw88gBdeeAHbtm2Ty1TKy8tlmiPaKjExtrnir1+/LiO5BAcHD1i4fwpmJspJph53bJ4EHZ3JS++zPwVsstvByTcQxtXbYNqwE85hMXAaqFPAYIRzVDyMWx6CcdU2ud1ko7eenCR/swvCLvZx8xA2jXV0MZ+ls8IGfjfzJF7LOCLnsTPzs8JWjvYNkoV+JvqGaB//5gz9TMdxojBbjvAnI03v+UDKSuTUlKBL2F0zkdPCVtaO4jcaDLKTUYVRYZgSabiwM5LiFxIg/rYUqdjDjtLn5i+2EbbQPm60E7EMlMYoWtjgfMfi86JN1UQf44qIaGkr3xmXaHMdOjo6w2eytur59ZWYFxarTEHW2/vzLstoX4duZiAhwBpd92ElbfSKmGSZCi81JBavZxzFH8/tlSJJDihSYT+H2TK8+p8CmyifQBl9bCZytDgf9R1tyhTvh0mmN2Jdy0hhqvCUA484AIkDkYYiwstH1OfWdrtO7Lu8pb+v5O7EOVgeHi19YRQ7fnA9W7Qzwxc9cp/cN+GxeMypiDXSyweoO0TRi9U/6BISJEUtAZvXwWdZuhS81O49DHOj9d47u7vLKDD+q5f12q8uocHwXblERnnxW7McXgtSYArqG5gyYWj8Bzo6Ojo6gzNuwpfpTkVTnXQgxPjZjrhoaG+RYWlfu3xU5s5cHp0sO/CeFYbmosgE7Ll+EW8I43L/jcuoa7M1XkYifOEoIBqqTKE0WZBGdEQM/mnZugHL9lm2Ieq13O729pyvYB7MvvCzNBRUU4GGIfNxjoQLlWWob2+X+0j0C5Cj1+2hE+NrS1bj31ZuwmdSF9l0wvE753EZ17F3eHB/3C/3z+PweIQG8/Pzl+BLi1bgxbSl8pPT08Fp4ZIWDSc37UjBVrSfzEPbwWs4s2cf9n/64S2VfaKcOLofNdWVMHd1yc/ca1eVo/Tn/OnjOHPyCC5fOI3TJw7j4N5PUFNVqSydKKxP63R3nOvMLNhGsq5nmj8tzZ3tOJp/VYpaPsk5h/mhsXgmfbNoP++UEWCs7eoR7BVtaGWzrShDzV89nN8KUyktj07C+9mnlDljj942Ak+mpGFLbGJvm8h1PYwuWBgSga+lW9tMlqdSFsnlWmZi2zh1UZ+ksYOil0ceecQmQkpTUxP27t2Ln/zkJ/j+97+Pv/71r9izZ49Mg/TWW2/hD3/4A77zne/gf/7nf1BQMPQou7GgXTy7H3/8sRStdAm7RMVgMCAsLEwKVbRQ8EJxC5fPnz8foaGhyhLgxIkTePvtt1FUVASLRvzO73V1dTJdEqPGTCR9nf/yQ0dnxuA0CgJA47LNMN39mREV5+g+QWC/7e94CE7KyGFHOAdHwLT9cZttjKlLlaUD4xQULo61Se7ftONJmDbeB8PC1TCIbfnJadP2J2Da/CCMizfAKaBvxLkKz0turz22OP/xpK8zYXJUWLWtTVLcMFvcXy2NHa04lHdFdlTuvXFRpjJiZybL8phk7L/B9NlHse/6JdSIfWhxcR6+n8nXzQNp4bNkROPxJNDN3aGNq5YvCjuPUQoH4na311LT1irtZVVkzydEfU6YAompkLTikqGoam2RQho+YRxVv0rY9fbMDw6TvqKvL1mDf16+Xp4zP7fHJ/WKXbj9QGLxtJAwuBqM6BDnfK22Ws6jf/GJuWn4cvpKaSt/YeFycR+WO7TVdXR0HNPbno/9a84tcSDvMvzdrdFRtRQ1VOGja2dlaugrlYVSHMm00Rygy76Mt64el6mNKKy0H0zrbnIZdqq7dXGpcBXrnyycmMEFE82lqnLcqKvttSD4mDCN9PKIaMT1Rhi3RsnlAKTh4GE0yUFFpE3z3qjCFEf3z06RvhUKao6XFOCjvJG/+6n75rF4zKmGTaSXbusz7BYVjtBH7oXvisVwdjGh/sgp1Ow+CEu7JtLLI/fI9EU1nx5CZ6W1vdTR0dHRmfqMu/BFHf053eCoY6ZsuGtOf6cQr5hGJsME/vXiAZQ01iC7uliGG+Q8TtsT4R2AtcJgHE70FnbyPbt4M0qbapFRnq/MnXgMTk6YHxSKJ1LSBizLhPE3ELe7vT10WFyoKBUGu9VhoYWOB+bjHAnMr3ytrkq++IR7eWNzrG3HLWFYw52Jc/HY3AXYGBNvYzzyO+dxGdfhulq4P+6X++dxeDyyMjIGDySlIlXcG4pl+MlpGtJTHWNMAExzw2lpK3MAS2M7uisaUVNahrLS4lsrJUWoFy8fxFn8XjzEvY6IHPh+VVVWyFRH7DRqbWlG5pWLOHzgE9TVWP/eE0KvE1ZHZ3pxqigHWxIXajoa+ihvrpOjhdheZlYWoEy0c3+9dBAfXbOmBLTPWR/o4Y1tSelyROtQ9gYFJI8sWIsO8YJ8LD9TmTv26G0jnfHh8DDZOlPCPPvaS7WwjbRnJraNTsYeBC1pQvCyRgSmDR4NZ1IxDu2Wu7u7jI6yc+dOeHr2iZwoLGFEl9deew2///3v8ctf/hI//elP8dvf/hZ//OMf8c4778iIMIyiMhF0dnbiwIED+MEPfoBvf/vbeOmll+S5vvrqq/jxj3+M3bt3K2tCinrmzJnTm6YoNTUVW7Zskd9JZWUlXn/9dfz3f/83vvWtb9mU7373u/jZz36GwsKR/Y7HigmzocYJg0cETN6xNsXg3idS0pl5jEY16Jy8EMalm0ZUnIIjlK37b29YuAZwtUYPcYSTbwCMi9fbbOMcM1tZOgRiv86J82FYshHGFXfCuPZuGNffa/3k9JINcI5PYcguZQM7xPY8P5tji/OfydCeZVTf7UlLHPaz0pck/UwXDuBmXQVuCPuYaUPZwUkflD2Mnrghfv6w/Ezs/Hpq4UaZjvR86Q1l7vjg6+rm0MZVCzv5QoXtOBC3u709x0oKUdveN4pfhakhhpOqwp7zwvZuF+8g9AmtjoqzSX9BmEYpwM0da6NipViF5/y4+EwJDJHLCEUvH97o37m5KDQC84KsqZiqWltkJyiZFxSCR+fMx6KQCGkrMwLjPQlzsSFmllyuo6MzNH227Ni/59wKl8vzpV9lZewcZU4frPe5/P2sU3j10mEpaNmnDMblYCMKKrWwDpkXGosY32CZ7m4o6Iu5P3Ul3ss6idau4UcbmU5w4BDTBml9K/6yLo+Dr4ubMsfqZ7lQUaJMDY70eSmPnbud/RTh5S0HCzHFEWHzEOXtKwcALQzpE8wy0gx9LV9bvKrfoFsVNeovj2XvZ5vs9Ihnu+JNRno50ZveiJFeQh68G96L5stpUvPpQZibrP4UZ3G9YY/fD79Vy1Ar5nNZe1GpXDZpUf4sjnynOjo6OjpW1Dpy3IUv0xU6JD7IOo0V0cm9YWgdcawgS4aaZRoHRwpojj7fOXe5DFXr7eqB35/9VFniGKZQemjeaimS+dO5vZMuVQOdJRyRMlAZKsXL7W5vz/6CG7KTTwsV0ZerymU+zpHAET+Hi26iSbwAMHwhR6+zo200oIF6h9gf98v98zjqCCOGrbVP3+AlDLaIQUbuTRWc3UxwWx4Pl7QoOLmPvsLcKF4Slq9aj7Ub78S8hYuVuf1Jnb8Q3poUHZ3i5SXj4lns3/ORTHsk3naVJeOHWmlP904jnZkHRxclB0fK0OwDcbo4F+9lnZIpAY/c7B+tyVXUlduSFuNzS7Ziln8o/nx+/6Av6/w93TN3KbYkLMTvz3wqI8yMJzO9beyLKTMyZmrb6BHaibmfL8HcL5QgbP3UyZc+Xu0WU/k89thjePLJJxEdbSt0YjQVpgnKysrCxYsXwQgv1dWTYyRXW1sbDh48KEUrjEJDUc7vfvc7/O1vf0NOTo5cx83NDTt27MDixYt776evry8eeughbN26VS4nJSUlMqoNt33llVdk4ff3339fXvdksR2mowVjcA+DR+QWeM16CF6xO+EZe69N8Yq7Tyx7EK4BfU5XnZmD+rudcfC63dzhzM730Cj5yWk5f4pwq7bKWMC0RukRCXIU/0AwlRHXY6HPyR6mqrhnzjIZPTHI0xd/PLdHWeIYDq56IGUV1s+ajz+c2zusTs/RhL8dRzauWhjNQBWAOOJ2t7fnanWFjJxi346x8/LMMEfta9lXeANFYluew4LgMGyOsRWKU2TDDlQeT7X71QgOtNFz62rwp4xz/VIsUUBDcUuYh5eMRkNx+w0lsiNTV1BMo8VtCqe00NGZCFSberK27+2irj6Sn4n7U1bKesMRHeYu7M49LyPoMq1RYX1/kWSkTyA+s2iTKBuRU12CvdcvKUscw/aJEcfM4t387SvHlbkzkwOFeTbRuBh9Kz00UvbfEPovKH6stvO/DER+Yx3auq19PT6urlLsohLm6Y25QSG97QP9QPOCQqVQkpFmVPgsMGrwToo+7QbdEu7TR/Gl8Fg85lSCkVzqDjDSi9U35BoRitCH75EpirR4L0iFk1HYAf5+crn/+pWoP3RcRoExNzSiu6VFWXNyotY7er+Ajo6OztCMrGfkNuirlCencTganC3JlQpppjEajIb2VrQ5UD+vm5UqO+12pixHXm2FDEHIkTqO4AvysugkPL/4Tjm6/aUL+3GqaGaGEhwJdFZk1VbaGAkNne235Kwgh4vyca68RO4v0T9QjsYJ0ozWKW1uwqc3c/He9axBC9fhuoTbPzZHGKlif9wv98/jqNDpwg5K9Qr4yXycmbX9X1amHKJ6MIb7wn3dbHjckQKXueFw8nWHk8kAZ/GSYBAvDCMp9vnlTSYXKXpZtnIt/MT9HYg5KWnYeMcOG/ELR49fvnAWB/ftQl1d/yhNY40avUI3cHWGy1R5VuhIuVFTjs8s3KjMcQwd7kyNZM+yqCTRdt6JB1JXoLSpRo5e+iD7tMPr54viwvBZou28A/fOWY73Mk/K8PAznfFuG/cVXHfYFtqXY8oIVTKT20bfOa0IXNiEgAXNaKtQRmJNAcYzymNMTIwUvnz961/Hgw8+iNmzB49OEBUVJaOmcLuJgCmLgoKCeqPUVFRUSPFKaWmptDcoaElPT8fnPvc5PP7443JdLby+L3zhC3jqqaeQkmLr0NMSEhKCO++8E3FxccqciWWKNEvDxi1oEbxi74FH5GZ4hK+Ha8A8uPjOsSmuAQvkMhe/ucpWkxMngztMXrHKlM5oMUn7xXSmGJfKbqKipX5IP1NTRxtaHIi5mSb0c0vvlH6mgvpKYSsfwofXHKcuop9pSWSiHIi1I3kJ/nb5EI6OY2TEyQpFKLSLGaVFpcvCNEflw+681FLQUIdP86+jVbzfMBoAoxQuDo1UlkJGafmv00fwh4yz2JWXg4uVZThdVoR3cjPxk/PH8aOzR6Wt3NBh+/feNisJqyPjZAdrcVMj3sq50isSz6mrRklzo411VtfehszqiU7prKMzdZgKPpbXLx9BvH+YHCA7GIUNVf0GC1Fo9/D8Nfjs4juwIDxORudlm3G53FZkp0JR5V1zlsg2ZnZghOybsE+vN9Og2PBabV+0cLarjDCmmoQUNh4vGX40TkbuqlQEGT4ubjJalwoFLYwIfLtwn16K8IXH4jEJI8Uwgi6jxdwRl2jj05lM1Hyyvy/SS3CgNdJL+gI5rSVw63qEPfEgQh/dCb/1K6WhXi22NTdan1mD5+S8vj6sz9RkFd7p6OjoTCacREPs0Gqj07WjY/RC07344osyj715zRKY0ya3428g4gwNyreBWR2Xgn9ccz9evXwYb2Qck+kWBoMjiUK9/aQaOzU0GrnVZbhWXYLDN6+Kl+D+Tot75i7Dc+lbsO/GJcQHhMnwgXRE7M+7hK4hwrXnd/d14o8Fm2ISRhQultAg5As8Ge3tW81dOCmMSfvR6kvDopDgHyDvPWnp6sTR4gJhfNo6LJaFR9sopPlCkFVTKUfAa1kh1vvmyo2IF+s2iN/NO7lX8Gp2BkqaGqQRyvQN9vlV7eGoHXbQhYh1H5+7APcnpsLXzQ154vr+88QBnFSukTBs74boeGyMjUeIu5fMJ32wKE+O9qFDZtpgtqC7sgnmWvH36zAjzTkGoYaRjUa6eP40bl7vE4R5ivv7v7/9I2VqcDrE3/L4kX04cfQAmhr7fvsu4mUgbfFyrFm/BcEhYdLgZKoEi6VbCmsc8S9//4LyzcozL3wVc1L6Rv5WWhrw57ajypRjXP/8NpyaW/DEE0/IjjAdnaH4+c9/jrfeegvmpQtgXpamzB1/htN2LgifhX/b+KhMa/Tn8/uGFX49wMNbRjybExxlDcFecgNHCzKl09+e1bEp+Mb6B2UI3xi/YFE3G7H3+kUcunllyDC8t9t26m1j/7aRI0tdlRFPg9Ha1SXPM9Lbd9K2jb9Zvg2eRmuEskefeEp+jiZOTj1I+UoJZj9Thq4mAw4/NxdNNweOLDhckpJm41v/8X/k99+K38LBir57OVqo7RZT7qxevVqZO7aYzWYpHrl586aM7tLc3IzGxka5zFnYYoyW4sqRchERMjoMBSFMl0SYfujkyZMoLu4TfC1atAhz5/Z/b2EEmQsXLihTQHJyMhYuXCgFLaSpqQnHjx9HTU2fUJYCFFXAwvO8cuWKfDeqr69HQ0ODjE6jnqOfnx9mzZol/k5J8rsj+ApXVVUlo8NwPzxmi+IUpaDGy8tLCl8SEhLkdarRYchQ5zfavPnmm/jFL36BrStD8PXH+6cwm4q4BMyHV/QOGD2jxA/VGT3dHehuq4S5vVJUjGY4GVzh7OoPg2sAnI1eaKs8gabrLytbTx6MXtFw8UuB0S1YXkdj7kvKEp3R4DP/fh7V9Z0ypdmqVauUuTqTGbW+6l44F12rlyhzx5bh2MrLo5Pwz+sfxptXjuFvlw8PaSvTmgv28sMDqSuREhyNgoYqXK0oxJH8qw7FMUw7+uUVd2GPsAni/EOkWIJ28sEbGehQRpoPxO3ayrN8/bE4LHLA6ASO0Nqzt7s9I67M1aQQGsi2jRXHWRIaKTsCCSOqZFRVyHW1ODqfipZm7C+0TRfFdBT/tGwt1gv7lW067do/XD6L0+V9dkiAmwcChJ3CT0ZSoMi7qq1F2shaeE474pPx2flLpO3dLGzfP105j9+L/anCF57PmqhYbItPQrR4NmrEfo6XFWJ//o1+7wUjpbOiCte/+Z/ye8CWdTJ9xHRCvb6xvjbj6UswnrmMZ555RhadycePfvQjfPDBB+jasBzdqUnK3PFlqDaDNdkLS7ciLSJeRoY/W3J9SMEO/ZqLIxKwImYOlkbNlin0mFr6Yllev74GrvvTuz8Pbzd3XCi9gZSQaJwruSHTKJ0sujbksW63zbg3cS7+98qN8NT4X+vb26QYcCDoD/joxjUUNtWPyfZv5VzFvx/ti6TG9HRfX7zaZh3CO3OkOB//dHBXr49ieXg0/t/6rTaRWOjPufftPpv831ZtwsPJ80S704O/XL2AH56x+o+5zYrIGJk2z567E+b0pjti6qVdN3NwSrQzjnxB/7B0DT6TukiKaN64dgXfOr5ftiuMHMMIvhRodnabcaGiDK9mXcL1+vEfDDoQrbl5yP/uT60T4vwjX3gKvsvTrdNDULv3MMpffcc6IbZN/H//KoUzkxXn/GK4fHQAK1euxHe+8x1lro6Ojo6OFhcXF+nn1YUvI2A4DgkamMxpefecZThTnIuDNzOQX1fhMDSsr3h5vSNxEZKDIhHs5Yu9uRdxvuwGShutoUjtCfP2x7+sfwhlwtC6Vl0sQxjSgZFZMTyl8FgLX2YqdCAwR/QXFi2XRicN5n2FeXg754ocmTNcaJA+kDQPm2MT4OfqJg3RX104JUf1qM4KFR6THY9cr6a9FfkN9f3WmW6sNiVhlcsw88srvPvmyzh17KAyNTLhC6HgJePiGRzcvxtN4h6ruLq5IWXeIqzbtBW+fv44d/o4OsTfff7CpQgJDVPW6mNUhC8vvQ2nphY5ov35559X5uroDMxUEr6Qu+YsxWML1uJkYTaOiZJTVepQAOrp4oaN8fOREhIj0yN9mnseWVXFuF7juL5l2N1/WveAdNjQGUNnf0VzPc6X2jqfB0JvO2+NmdI23q7wxcm5B27BXQNGcnE29mDlz3IQvLQRdVc9cfyLyehqsXakGNwscnlX8/A7elTGRfiitFsT1eFLUSrfZ1pbreItOmk9PDzkS5DRaJTzJhqLxSIFLxSs8HzVc6RIhSKY4UIhDa9TfXejuIcveia7PPATBdsitkl3rgjG3z9hm85hKmJwC4R3whNw8U2STlIKXtrKj8HcWgpLZz16eizit22Cs8lLFG+5nrm9Gq3Fu5U9TB7cIzbCM+pOeZ7m1nLUXvi2skRnNHj6/5xHVV3nuAoAdW4Ptb6iz4q+q/FguH6me1OW476UlThTnCMHSt2oLXPoZ/J2dceWhDTMCYlGuLe/sJUvSBvYUToLEuLli2+sewh1bc3IrCyS0YmLG6uRUd4XeW8wdFv51qHo5p+Wr0NacLgcDHWhshSvZ2dIkQw7KocDBeJb42bjwaRUKc7p6DbLDtpfXjyJMiWqsBbaysHunmjo7EBBY10/Ec2toAtfRgdd+DL5+eEPf4gPP/wQXRtWoDt1ZP7J0WI4bUaghzeeXrRJDvq5UJaHg3kZKGmscSiajPYLwl3JS+XgWrYDFLMczLuCdrPjFHerYufiqyvvwUfXzqC+rUW8b5txtvg6qlutgw2GYiyEL+zaMg8y8LiytQX/evhTnCkvHpPt7YUvkd4++PmWezHb33ZQQZt4Z/vFhZMympfKcIQv2+OT8K8rNkoBypXqCnzj0CfIbxg8HdH/t+YO2S4QDmr69okDeN+BuCdOtBvfW79NpkhiFLDvnDwgI42lh0bgO2vvRIxP3yAMthe/vnQKv7vsODvBRFD20uuoO3RCfncS7/hzfvFdOA1jkFXTuUtS9NJVZ/09uYQGI/Hb/8zRMnJ6MqILX3R0dHSGRhW+jH+qIyfrKIrpCq/yg+wzeCPjKEK8/PDUwo14Yek2PLlwA+6es1Q6INhhtz1pMV5YslWGHiyor8JL5/fLtEYDiV783DzxzKLN4j5CjvD5IOu0HBk/XNGLztjBTrXd+bkyxzJHmPsKQ3T7rCR8OX2lVExzxM1gcDnX4/rcjqPWuR/uj/t11GnHedm1VXJUEPM7j3XH3mTgWncZaizNfXXJOODt44v0pauwdsMd8NEY+4wGc/XyeRzatwt7P3kPRw9+KiPDHNjzkbLGGDDN606d0Wc8fyujwe6c8zLai69o7yiAeXHZVplT+p45y+Qo1A2i7dyalC7D6DLFX1VLA/5y4YBsOwcSvbgZTdLh4+/uLdMHvp91SradwxW96Nw6ets4NCavbkRtq8WcF0uVOf0x+Znhm2gVbjTkeMDc0We6e0Z3yEgw/vObpYBm0qG0WxNVFzH6CiOfBAcHy8JoJhSVTBbRC6G4hSKVgIAAm3McieiF8Jp8fHx6r5XfJ4voRcsUa5YGxOgVC6NntHjGndFj6UJ7zQW0VRxFZ30WzK1l6G6rgLmlWExno73qDFqK96Cj9pKy9eTC2egJJyPDeut25lhAMZv2U0fnVmH1SZv3b5cOI9DDR/qXXly6DU+pfqbENGkrb6OfaelWbExYgJKGGmFbW/1MA4levF3c8YywlWkzM53FB9lWW3m4ohed24NRZX5+/iQuVpXB4OyEJWGR+PzCZfjSwhWyM3QwvF1c5Yj+Ly9aIW1mdl5SCLUr7xr+cvW8Q9ELYYcqbWVGqhkN0YuOzkyir2/D+jFZYbqh1zOO4kRhNuaFxuLZ9C34/LJteGT+GtkfsUm0ERvjF+DBeatkVHmKXo7lZ8k25pOc8wOKXpKDovDYgnUyItg7mSfxYfYZuf5wRS9jBe0sDoIZqDAKuxrVyxG3u709JU2NyKiukJHBtFS1NuNoSV+65uFypqxE+jn4/NFPco+o+0cLDlbiPrlvHoPHIozSG+BmG2nWTbxzcv5kor24zxfoZDQMT/RyKRNVH+7pFb04ib9vyEN3T2rRi46Ojo7OyNBr9DGgq9ssR9XQcXCq6BqqWuoR7h0gRS73pazAIwvWyk86Ixg28J3ME7ITrkfJ1WePu8kFzy3egtlBEfjzhf0yggzDnOpMHphbmWERf33pNK7VVEljkGkeGGr275esEWU1nk5Nl8pwtXCa87mc63F9bsftuR9HOZtnMhS9nOy6gYLuGrT2dI5bR5qbuwcWL12FFWs2wMvLW5kLdHZ24GrGBZw5eRQN9XVoaW5Cppgeazg6XEdnOsJ2bd/1S/jb5SM4kp+JsqZaBHv6yhFFO1OW49H5a3G/aDvvSFyIm7UVePvqCZwuzumXl1qFzovnltyB9IgE6fTPriqW4Vl1xg+9bewP/WUmn24EL29EyleLkfRcGaK2DRwqOGRZA1z8rM9tXYYXesx9Dje3wE7EPViFuV8sQdxDVXAP64STYXzaxpEwUcIXncmD2uk/XZ4Fg1uw+K1ZR3kyxZG5KV9+DkR3eyW6W21TZujMDNQ+Er0enDr0ipQm4d/M3N2NPdfpZzqM4wVZMoJhqJc/1sSmCFt5BR5dYLWVNyekIbOyUPqZzg2S4sJkMEg/09yQGPzp3D7cqC0fMn22zuhzorQQPz13AoeLbor7b0GSfxAeT0nDV9JX4h+XrcMLC5bi/qTUXlv50TkL8HeLVuCfxLLPpy2TAvFgD09Ut7XitWsZ+GPGOSkA19HRGX3U+lRNDzyZYYSX97JO4bXLR3ClIh/N4h16dmAENiem4cHUVXh4/hrZN8HURuy/YASXm3UVytb9YYrpp9M3yQFIb105JvbXNmA/hg5wvKQAjZpMCnx2rtVW42b94JFaHFHd1oL3cjNR294m0xoxAgzTPA/G+YoSGeGF5eO8a8hv7H9c7mOraEO4T+6bx+CxSE5dNUqaG23+wowIk1ltm95vojH69Pnpe4bhL286fxlV7+9Ge6FV4EPRS9C9d8InfYGc1tHR0dGZ2qi2muE/BPKbHQyZzZDbowVzYNbV1cESGwlL6Njkjx9r/JyHn/qJxh8V1rk1pXIkeqkwOEsaa1FQX4kbYjqrsgierm5yhI2HyQX5dZUytKk9DE379KLNSA2NxUsX9kshza1S39OX219n9GFIWRqShY318hUowN1DOiDiff2REhSK1MAQzA8Ok/meWTiCZ2l4FGb7B8pngI6Kg4U38FLmBRwuvonmTscK+5lMvaUFdT0tqLY0odRSj8LumkFLXmYmGor7OhqcTAYY18bLZbWWZoQb+qK4DIbJxQVBwaHw9PZBSXGBFL0Qi6gjWVQoStm89R5lqo99uz9QvllZuHi53J9KS08HLpkHj95kzLgGp45OzJ8/H4sXL1bm6ugMzOnTp5GVlQVLZKgo/VNwjRcjaTsJw+uy3bwu2s9i0W6y/WRkNDrj2XayQyLAwxueLq64KdpOik3tCfLwwdPpm7EqJlkKRo/mX1WWjBy97bw9pnvbeE9UIlycraOK3nzrbfk5EExLFLKyEdE7qhF9dw3C1tbDLbBLzs/+TaSyVh+M4jLv68XwjOpAT7cTMn8Whc76vmglnjEdiLu/Cp6RHfBJaIdnRIeMItNW7opuTWQYRwQGBmLThg3y+3nx28pvGf1Remq7tXHjRsTExChzdWYibIvYJsVHemLVgsGjPU0FTD6z4eKbKNoj8du3dKKj9qqM8jIUTH3kFrIcLn5zxT7E9kYPmSZpIJh+qHd971niBVPYnZ0NMHiEw13MN/kmwegZhZ6uJji7+MI9dDlcg9LhGjAfrv6p4hyTYXALQo+5RZQ2Za+AwTVA7HeZ2O8cuHjHw+geLOaKGpqjUp2N8txYDC5+MoKNCtM3MW2Ta9BicYy03uMMdizrNfNY1mvmsZkSyhGugQtFSZPrGd1DYW4Z/RRs4827B8vR0taNTZs26fXgFEGtr+izou9qPBiZnwmobWuSdvL12jKUNFlt5XyNn8lN2E8+rp7CjnIV8x0Pmgr18pO28sLweOlnOl6YrSwZObqtfPuwc7GwsQFNws71dXNDkLunTJXB1BMpgcJeFp/poVZbmXby8ohomSaJdnVHd7dMkfTSlQsy2kth0/DSzI4m3S2tqN13RH53j4+F1/ypmd5+INTrG+trcy6pgHNpBRYuXCiLzuTj+PHjyM3NRfcsYX8FBypzx5eRtBndFoscUJRL/4p45ytvrkOxaDMocKHP5WpFIWb5h8Lg5AyLsAMpqLQXS9L/sip2Dh6et0au89eLB1DUUK0sHTm322YwDRxTGh8rKcCR4vxhlaNiXaYIYsqfsdj+VFmRrMe11Le3o6ipHidLi+Q6h0U5WJSHYrs6mimWGNn2ZGlh7/6Oie+5dbb3mCmfQz29kOAfKFMeRXn7ymPcHCDlUVVrizzncxUluFBRKo/bpel32hSbIIWVCf4B6BR2wic3c/Badob03xCKdspbrJHD2s1mXBX7evd6priGm/I+TBacjQY0nrlonRCPrteCFJj8HKfTarpwBVUf7EZ7QbEyBwh58C4EbFor3lkmT1TYgXCqE++BufnynYLvFjo6Ojo6/WH0b0bAHnfhS3dsJHpmgPBFheYiHQ21bc3CMKyShmVOtVUMUy4MSg+TG9bEpSBOGJpBHtaG2Sj+OMGePtiUkIY7Zy+SI95fyziMowWZcvmtojskxh4akezco+GZU1stDUWGrGXuTy8XV+mYoIHqJ4qLwSijDzAv58HCm3jjWoZM33CxsszGGNXpwyJ+UU097aiyNKPcUo+yIUrdtQKYS/peAiwmZzSuDpHLGDVmgWnw8MFaXF3dEBoWgdbmZpSWFDmMvMIXwjETvlzOlh2I8+bN04UvOsNiqgpfVCgGrZdtZ7V05OdUl8i2kykBnZycsVa0nXTShHn7i5qhB0Zng6hjvbB2VqoM8x4fEIq/XToi81nfzkgkve28faZz2zgc4QsFLH7JbYh/ogIxd1cjZEUjvGL5u3BCR40JJXsDUH7I37qyBvfQLqR8uQTOph6Z5uj6X8LRY+kbXcg+d5/ZbXD1N8PVzwzvWe3wTmgTn23objWgo85kEyFGy7gIX5R2a4M4TmxsrDJXZyaidiTPivDEqrSpL3yheIOiEQpBpPgF3TC3ltgIPhwi2i6PyE1wC1oCk3e8+G17orP2slVw4gCTXzK8ondYRSXuIehqzEV3e7UUn3hGb4OLTxKMHqKN72qGR+hKuAUvlcsokjF5x4nClExRUhTD7XrEenK/npHwjBH79ZsLg1ugvA7CT6NnjDw3FieDKzqqz8tlvGb3iE2iXlol6pz54jiJmuP0HUuKZTTH4jW7hSyFe8gKmHwSxPmGS+GLpdPWSW8U5+QVcw9cAxbA5BUDS0cdOhtufcDHZOG9QxVobjPrAsApxGQXvqiofiYKxvtsZdXPVAcXo1HayvQz0Z/ELQzCXgny8JbpLbbOXoQIn0Al0uKtC8SJbiuPDpWtLTINUV5DDYoaG2RaDaag8nRxkXYyU07w01PMY8RLrn+6vEjYylek4OVocQEaOicmKqIufBkddOHL5OfYsWO4fv06LPHR6AmeGJv2VtoM1hmd3V2obGmQA2/ZVuSKNoOltrUJiYHhWBKZKD/djC5ywIqr+Iz2DcLOucuxMSENxfXVeDfzpGxrbofbbTPqO9qRWVMpUwkNtzCFjyrWGIvt7UUvpNXcJSO8qOtQhFLqIAUd98v9a/dnL3ohFKRQIBPl5YsYHz8pgon1sfoQipoapCBHS5s4Ps+VhRFzVV8K0+TdmzAXT89LR2pQCKhzYnSa314+Y3N+fGbok8mrr5PnRKEP0+RRbDOZMPn7oebTAzxhYer0oKu2Dm4xkf0iwTSeuoDqXXuhjfQSct92BNyxTrwPucp5kx2nukYYruvCFx0dHZ3BmDDhC50HM0n4MhiVzfUybVF9ewv83b1kVJcF4XGYFxqDxcLgZAhCjuL5JPc8zpZcV7a6dXSHxPjB8H8ML3ujvgbX6qpwvqJMhrCloXhUUXAzlO3honwcKLqB/QU3cLaiRG6nMzTsxKYIZqjSmVOO7pJ6ZSthJJoMcFmbKJe5O7lioWmkDmgnZGdloLS4YPyFLxw5396B1NRULFmyRJmrozMwU134MhAc5ZpXWy7bTm9XD6SERsvRqqkhsUgXbWdqSAwK66uwO+c8jhdmKVvdOnrbOXpMx7ZxOMIXk5cFC/6pAFF31sEjohMG1x4peCk/4oeijwJR+FEQuhr6jzCiQCZ6hzVU/fW/hKHmYp/zhphbDWgpcpMCF0aNYaojimB8k1rhGSW+B3Wh5pztNirjFvFFtFvs8NWFLzObPuGLB1ZPA+FLT3cbXHwSxG/ZXxh/BjiLT4OLD3osnVJgMiA9ZhjdQuDilyx+s+5wNriiqykflo5aZQVb3MPWit/0XJlWiZFX2soPy5RKJq9ouAUuEvvwkB0TPA+TbyJ6ulrF/m7K/Tk5u8DJ6CbXMbqHiHPrEvWMVUji7OIHVz/ul4IXp97Pnh7x7m+hM5s2rkVcS42oq6xpPCmW8YrZIYUrFPowwk1X43UZlaXHYpbRaRjdhQId0lmvtL/imnu6O+HinyTFM85GTyle7azPphfauo7AI+oOGUHGWZxzd2sFWkp2w9LVv3NgqvHBkXI0tZp1AeAUQq2v6LOazMKXwWAaipvSVm6Fr5uH9C+lhc1CqvQzzUZyUJS0pXfnXpBpQ28X3VYePdhRykgCTDFBEcylqjIZSUDayqL02srik5ED9hXewLHiAtnpOlD61/FAF76MDrrwZfJz9OhR3LhxA5b4GPQETR3hy2Awum5xYzXazZ2I9AnEIsW3siAsTqZBCvTwxsmia6LNOC9FM7eL3mbcOkxHxPqeEXQpgAnz9EKif5D8ZNSeUvFO3z1AW+BiMGBt1Cw8lDwP989ORaJfAMyWHhwrLcBvLp+RYh5H0BfDaDFVbS2TciCSk9GIns5OtObelNNdldXoqq1HR0k52otK5Pzmc5dRf+w0OooV0ZaTE4Lv3YrAOzeI9zhr+tqpgHN9k4z4Eh0drQtfdHR0dAZg3IUv77//vlX4EqcLX7S0ixdbhhhkaFp25tULQ4IpkhgN5nzpDRy8eQVFwggdDXTjcvxp7OxAQWO9VG8zLGBGVXlv4TTncznX0xl9unIq+glf3NfOlt89ndxGLHypqarE7o/eRltbqzLHFmdn5zETvhiUkfO68EVnuJw6dQrZ2dnTTvhCuizdMnUg28/q1kY0tLeKtrNRhua9XH4T+/MuS4f+aKC3naPPdGobhyN8cfHtRtq/FMjILaT2krcUspR8EoDqcz5SBGMPo8TE7qxCwIIWKXDJ+H4MuppsxTFMf9Ra5oqmPHc0XXdHV6MB3nHtMLj1wCOsEz4Jbbj+Ejup+zMewhe13dI7fHXUjuTYcHesWTgxYeFHEwpfKHKhGIRRWygyMbiHwugRJiOekIHELBRzUHRCoQgjrFgoVmnon2KEIhGPiE3yk6KVjspT6KyzRmVgdBRX/3lieyMYcYZikg6xrK3sADpqL1sFKa2lYttAOLtYj+NscENnQw6YiohiFAp0uhpyhfFqlOdOMQrTKLXkvytFKSwywkyHVXxncAuGi3+KqIfyxHEOyuN01l4R+8yFuaVQnovBPUyKaHhPuhrzxLVZ6xXul/NMXrFSxONk8hLnVy7OwepgZ+ooz8g7xLn6yOg1rcWfiuPfXqTTycIHh63CF10AOHWYDsIXIlNN0s9UVyn9SxSMq36mi6U3cODmFWlLjwa6rTz6qCP7KYC5Wl0pIwWotjK/Z9VUSmEMU4JOpOBFRRe+jA668GXy0yt8SaDwpX/EzvFgLNoMthE3asplpHrpW2lrkm1GcUMNjhVkycL5o4HeZtweFS3NMsKLm8GISG9fKYJJCgiSQhamQUoJCkGcj79MHZ0cEIx5QWFYFx2HO+Jm456EOVgdFYdAdw80d3ViT34u/nTlPC6LtmUq4xoVjo6yCnRWWPvP+Ml0RiytuXlozcmDudEqqJeRXh68GwGb1oh3l6n1LDrX66mOdHR0dIbCaDRK4YuzMq0zwVS3NOK4MCQ/yDqN90X5IOsUjuZnonGUDEsdHZ3bx8nZCYzqwmKPUVSo8bPnKFOjj3pM+3y7OtOb2lrHHWc6Vhje/XRRjmwz1bbzQF6GnK+jM2lgtd3T1244u1hgbnVGW5ULutsdm+IGNwv85lhtwKZ8N7RWDDwSqbPWhJYSV7TXmKQYRiI+GP1lItHbLR2VPrup73cw1aEIpbnwIxlhhZFSKH5heiCPiM3wjL0LHlFbZSoge2SklOYC8cOwiNthhIsPUx71j8xk8knsjZ5CEU27EnmlH84GUZ+UoLV4NzpqLsLcXCjPqb3yNNqrzsoIMYQCGgpPCMU3FK60V5+V52OtpMT/xbqcpxYKZVS62yrRIq63pWgX2ipOiOvPlOIabk+RTGvpQfSYrQ5lZ5OvTGvUi7g/PJ/Oxlx53QYXX7iHrpDXzeIevlbUeRT4dIvzypDnNt3Q68GpQ299NU3+ZBSGnyjMtvEzHc6/iob2FmUNHR0dHZ0RMw3b9W5hozH6y57rF2V7obYZl8puylTEOpMHiiB/n3EWv7hwUoohncU7VmpQKB6dMx/PzkvHC2lL8WLaMln4nfO4jOtwXW7DbbkP7muqw7RGjOASsHkNnEzWwUKWzk6YGxrR3dQsXkWsA/tNAX4IfmAHAreIdw8PdzlPR0dHR2d6MgHCl+nj8BwLZAoXYWxOhlEbOjo6tvj5B2D95u1YvW6LKJs1ZQvWrL8DG7fsUNYcAxQnrCPRjc70g9FafvrTn+Lttxlh6NbSvMykThZeqd526kxWuloMyH87pFeU4pPYiqTnypD6tSL4zW1Vq3cbTN7d8I63/vbrr3r2bmsPI8OErqlHyt+VIPbeahi9rE6d7jZnccxg+X3C0NstHTumUw1NkQiFJi0FH6Kt7Ai626vY8MLJ6A4XnyR4RG6GZ8zdcA9dBSeDrWOVQhFLt1XYxkgqRu84+V2LiemQuJ1o27qaChSBSn8YeYZiEXOLNV99Lz3d4vzOywgqEkZ9YWqmW6S7sw7t1eeksMYRTHnU3aFEWXQ2iMN5Wr8rMMJMW+kBWMR+RMUlhT0uAanW4psk53W3FMtoMhZGpZkm6NWfzmRB9zPp6OjojCLTvIGnL4ltht5iTF4Y9evNnCv4n3PH8bMLJ3C8pBCVrS1wcTYi0ssHs3z9ZeF3zuMyrsN1uQ235T6mC+6zYhC4fTPCHrsfwTu3wS06Ak4c8e/uCs/UZIQ9eh9CH74XAZvXyvlTEuUHqftXdHR0dIZm3IQvagecXjnr6OhMVYxGExYtWYG1m7Zi3aZtmrJVCmDiZiUqa44BSt2pjxidGTBF0TvvvIOPP/4YH3zwwS393fVnRUdnckARSu5LYcj8eSSqTvmIH6cTfJNbpVBl7heKEXtf/5SWgWnNcPEzo8fihLqrnr1ODi1uQV1SQJP8Qiki76iFV1w7ujuc5TGu/T4CuX9ynOZo3NDbLR0F9f1v2j0LPd3obLiGttK9aM5/F23lh8VvsJYXKtMPufglwyPqTnhEbpRpfFS4jbmFOebFeiaxHoUfGgwe4TB5xYkb5ywFMp31WcqS/lCAw7RBjuhur+kTvoi/AaPSjAa8Fhff2XALXgqPiI3wjN4Br9idNtcoDqh89sG0SO01l6RYx9nkBffgFXAPWSW/8zzbyo/0F/BMcabtsz+N6fNX6X8zHR0dHR1betvz3rZCR2fiaO3qwvGSAryadQk/v3AC3z99BN89dQj/efKgTeE8LuM6XJfbcNvphsnfD/4bViHwzg0IeeBuhD1+vxTChOzchoAta+GzbJF4Xxmd96GJgCJmovet6ujo6AyNnupIR0dHZwS4ubnDx8cXPr5+NsXL2wfOBoOylo7O6FBfXy+jvnz66afKHB0dnalIa6kL8l4LRfZvIpD92wi0FLvCydCDkFUNmP1smbJWH1Hba6Q/tcfsJCO+OMIzqgMJT1bAP7VF7qu50BU5fwxH1m8icfONEJn+SEdnMjDdO/+7O+pk9JfWEgpg3kFH9VlYuqxRSxjRxT1sLdxCVshpYulsRFdDLnosZnFzDDB5x0Gb7sjFNxkGGZ2lB+aWMimUGZAeC3MXKRP9UVMdjQZM3eQZvQ1esffLaDb87hF5hyib4BGxQTnnQejpRlvFMWvUGPEoGL1iRYkRl2CZtimOdL/01EMXK+nozCx6urrQmpuH+mOn0XjuMrrqGpQlOjr9sQibRaI38DqTCIpYLlaW4ZObOXjjWoYUt7yceVEWfuc8LuM601HwYo+zmyu8FsyF//qV8FuzHO4JcWKm3gWqo6OjM5MY94gvOjo6Ojojp0d5r9br0plF2LxZqKysxCuvvILDhw8rc4eH/qzo6EwuutudUXPJG3mvhSDrV5EoO+CPznoTPCNtO6ZdA7sQmN4kvzcXuA0oYDF4dMPFx4zWUlcUfhiIzJ9GI//NENRe9EJX88QLMfV2S6c/07uTgNFeOqrPo6V4N1qKdqG7rVLMZVQXH7gFL4PJK8a6ooBCD0untXPN4BYiU/+oMAKMk8FFCmO6GnKkUGaicQmYJyO7eERsgVvIUhi94+Fk9Ba/726Y26rQUZcl6rihw6V3t5ajsy5TXFuXvEYnZxN6GNWG92MapThS0Udk6ujo6ExeKLxsOHEOVe/uQvVHe1H9waeofPMDdJSU0YBV1hLodbmOHfr7jY6Ozrij1Dv6+4WOjo7O0OhyxxFQa3Gf0kVHR0cwzu+n9i/ENFBvxUYVW8lP/QV7ZhEQH4boZckoKirCX/7yF5w+fVpZMnVw1B5NpaJjxcVgQHJAMOYFh/aWRP9AZanOsBFVuLnFgNK9ATLyS84fwlGfaRvRhWmOTF7d8nvJngCZvsgRTKFU/GkAsn4j9vPHCJTu958UghcVvd2a3tTV1SnfhqYvgoL8mPaYW8vQXnkc7dXn0NPdKecZ3YJg8p0jvxNzaynMTfnipljgbPSQaZEIxTEmr2jxzUkKYyiQmWiYeskjYrM4R3H+Bld0NRWgpfBDNOe/JSPctBS8j5aij61pnoaAkW0M7iHimeir1yh+MXpGKlPTDetDr9eDE0dt7dDPpZaJ6ExwZH9OpTITCXL3QGpQn03MEuszRNQrnUlHe0ExqncfQEv2dXRWVKG9qAQNJ8/J6C89XWZlLdF2ubvByahH99Xpa88nsuPZUT08lYqOjo6Ojo6Ozlgz7sKXqezyaexxmdJFZ/rBjshHkufjn5evx7+s2IB/WLIGa6LilKW3Bp04z6Smy/2xfHXxKqSFhCtLpxZOJgPfSJUpgXhJtbSMXsj34VBTzdG+fTAdkrPzLThNlMvQHeczj7l3r0B4Wjxu3LiBP//5z7h8eWqlAnDUHk2lMh44cp5zmvMnCzHefnh+wWJ8LX1Vb/lMyiJlqZXp1H6MNZYuJzRc80DB+0HI/EVfh6+Tcw+CFlujvTBCDIUvA8FoMNd+H4GS3QFozndT5k4iJs4frDOGUID5s5/9DO+88w46O62ijuEyk2wYphhqrzwtfuvN1hnORttUQD3d6Ki7Akt3K3/4Mu2PwTUQLv6p1rRHPRYpjKFAZqKh4MUkzo/naemsR2vxJ2grOyiu75SMcNNZnwVzc8GwOoFcg9LlNQqDWF4bU0I5GdzgGrzMKqyZZvSJvnT7fbxR66q33noLzc3K73CS4sj+nEplJrIyIgZfTl9hYxc/kCTqNp0pQ3dLC+qPnEJnua2/hjRdvCpFMGrdbfBwR+CdG0R7pY8dnelMhvbcUT08lYqOjs4tolQ/Eym809HR0ZnsqLbauFntvcbhDKib10XF4Z+WrcO/rKAYwXH5xvL1+P8tXYuvihfkp1IWyW28XRyHstfRGYj10fF4bv4S8QwtlOUzqYvw7Lx0JPgN3FE2FDvik8U+F/fu82mxzyfnpiHAbfJ0wA4XZ193W91LVzc6zuajp21kHTW3Auu82ppKHNr/iTLHiru7B9zcb2GUg+44n7H4RgYh5Z6VCE6OQlZWFv70pz8hNzdXWTow+rMyuYn08sHOxLlSHCLtAfFJm6C3iOn/JeZz2cPJ85WtJo5AUXctCYvCqsjY3rIoNEJZamU6tR/jBaO/VJ70VaYAo6cFvsnWdB9N+W5oKR7YNuyoNaHphjssnZPUCa+3W9MStkNvv/02PvroI3z88cfK3OEx456FHkZuskZv4rX39PSNHiedDdfQ3VYlvxvcAmHyTYTJJ0EYsCYpiKEwxrqPicXoFiLTEhFLR504r0wp7NFi8AiDs4uPMuUYXpt7yEpxeV6wmNvQXnFS3oOeHouMiOMevkGKf6YTzrpjesJQ66pdu3bh3XffRXt7u7JkeOh/uYllXlAo/mHpGoe+NLX8syi0lb8mbGb6QO6ISxw30Xicr78Uv2jtYp6zzsRiae9Ae34RuqoHiPQk2uLOimrUHTqByjc/RNNF0c46oKumDlXv70a1KC1ZOegxdyPgjvXwTLVGZyNDHktnWtJry+rtu46OzjijVzs6Ojo6w0eXq48BHN38REoaKGgZqFCgwA6hZ8QL+vMLluBLi1aIF/vVeGTOfNkZpqMzHJaFRyHK20cYP1brhxFg5gaGIN5vcKcxhTELQsKUKVuWR8Qg2KMv7YK70YSFIREI9/JW5kwdjNH+cHI1KVMCswUdZ/LRuusKKj48jQ/f+ZssB/Z8hPKyYmWlPrq7u5GbfQWffvxO77rDLu++hk8+eBsZF84qe7MSLO67r+/IwyDrHYczm4BZYUi9bzUC4sJw8eJF/PGPf5Tpj3SmHqynt8cnS2HLi2nLpB1wb+JcrImMxWpN4fQ9Yj5thftnpyhbT26mU/sxURg9uqV1TsFL5XFfBn2Ysujt1vSGqY7eeOMNHDp0SJkzMKqdapkmj4SLfwo8IjYNmZ7HNXARnI3W+q/H0onudqvIRcXS2YiuxhtimRnOBnex37miDrAKCrvbKqUoZMzh77S3D8dZilL64WwU/1M8rWIdbZoiFbfAxXB28VOm+kNRjHvYOnF94bJu6GrIQUfNebSVH4alo0bu18U3EW4hy5Qtpgeqg1qvDyeO7pZGvPfee1Ksx3e7oegdRav/ySaUeL8APDZngUNfmloYeZB+NdrSn52/BF9cuFxGwOX0LN9bHwikM3VpupiBynd2oXrXPmWOLR2lFaj68FNUf7wXdUdPw9zQqCyxpcdsRvOVbNR8elAKYOoOHoPRxxueSQnKGkMfS2d6YrEoL2d6D7SOjo6Ojo6OzqRl/CO+6GNnJLwLRmdnuBmNCPHwxPzgMDyYNA+fW7AUn1+4bEBRgo6Oluq2FnTaOfCaOztQ296qTFlhNKEV4dHSMfT3S1bj66Lcm+C4I7W6tQVm9WVOwF9ufUcbqsT8qYYhxAcu6dGipuurdywNbeg4X4i641k4dnifLEcOfIpTxw8ra/RRV1uNg/s+wdGDe3rXHW45LkrGpXPo6OgbXWhgJ3D6MnjeSiew8mKtO85nLsFJUZj3wGr4hAfg1KlTePnll1FZ2T80s4r+rEw+OAr1yZSFsp3fHp8kR4u6GdihODC0FbymSES46dR+TBRdzQZcfykcV38SjaJdUzzygd5uTWvC5sWhrKwMf/nLX3DmzBll7szA5B0P98hN8Iy5B57RO+AatETMi5PpgFiYsscjcgvcQ1fCycg0ZD2wtFejsz7bugMN7TXnYelsEL8XZ7j4zIazyVMKYSiIoTBmrLF0NYjfqDUSjZPJC66BC8WpmGTkFZOXNX0q0zX1KJFnGJnGLWQFnAzW6IUGt2C4h6+DW/BisYOBU3m6BS2Vwh6KaCh0aSs7hO6OOnGdeeiovSyFQdzn9Et5pNd/E81CXze01NfizTffxO7du5W5OtMF2smuwpZmZMLkgGApJqcI5kuLlt92CmidqUfzlWtovpqNhlPn0WPnJzM3NksRS+PZizJKi8HdDW6zYuC7aimCtm9GyH3bEXzvVgRsXguvBXPhEhQoI7205t5E7d4jch9OJmVQlbBtmy9lymM1nrlonaczo+jR23cdHZ3xRql29FRHOjo6OkOjR3wZJ7otFilQYOnSdAppMTg5y2gvTBXw4oJl/VII6OjYsy//Bj65mYOS5kZUtrYgt64ab+VcRW5ttbKGlbmBwXghbRmen78ET6emY1NMAmYNEHXkrZwrOFiUh/KWZrnPK9UVeCXrkvg+uXOjO8LJxQjXFfFwSRG/JePA1V1bWysKxb20p6mhHiVFBejq6lLm3Bo0Sl3d3LBq7UakzF8Eg2HgjoGB0A1bHRKaGof5D66Fu78XDh8+LJ34jY1j3zGmc/sw0stDyfOkAHG2X6Bs87XwHbbLYrUTWGg3TDWmU/sxUTD1UdlBP5Tu80dT3i2kxZtE6O3W9CYwIQJRi2cjLy8Pf/7zn5GZmaks6Y/6LEwnDZSzyRuuAfPgEbkZntHbrCKYWKXE3CWFL0z/Q7o7atFWflRGcbHH3FwsSr68Oc4uvuJmGaUQpr3mgrLG2ELhiaWjXn53NrrDPXw9vGY9CK+4++AWslzO76zNgKXdmsqB181r85r1gFiHZaeYvlOKZiziOh1BIYtb6Eqxf4p6OqXQpbNRsbt7utFWcULeB7aE0y3lkZMy6EcXAE4c0R4mbAnxQnVlJV599VXs2zd4dIa+tkv/m002LOJ3pPWpOfoL8e9HofmW2ES8mLYU66JmKUt0ZgziObG0taO7sUmZYYVpjZouZKCnswsuwYEI3LoRIfdvR9BdWxC4bSMC7tyAQJbtmxB87zYE79wGn6ULRbtnQldtnbIXK4wIY+b+Wbfr9fuMorc9n0HvOeGe3jKVm7akBIbIAZY6kx+2iYwizPSATBP4lfSVtz3YmttzP2raQe5/vFIN6ujo6OjoDIb6Pu8kjDaHVjpzIHd02Obuvh2effZZFBYWomvjCnSnzFbmTk/Y+DN9kcm5r3M7r74WL2daRwLw5nsYTUgVxiKNhVAPr375vzvEy/yn+Tn4r1NH+kXv0NHRkugXiET/QDnaidFertRUylH3Wjjy6X+v3AhPkzU/PzlZWoTnP3lLmbKFz2asj598Lmvb23CxshSttyn+mEi6SxvQfj4f5oJaGfGlp11ciybevpsw0BctXo57H3xCmWOlproSb//tJRQV5t2S+MVgNMLDwxMBgcFISJqD5SvXw8e3fxj4SksD/tx2VJlyjOubu+BUUY2VK1di586dylyd6UpWVpbsSEy5dyVSd65S5vZx80gGLr9xGG4GFzz00EN45JFH4OLS9/smP/jBD2RYd/PSBTAvS1Pm6kwU989OlaNPI+zSGXZ0m5FTW42TZUUob6ED1Tqf9S+jwS0Qpc1sxkPvvWxdMEEsD4/G/1u/VdosKjeEbXPv2y8pU1amW/sxFL9Zvg2ewqYjjz7xlPycCiQlzca3/uP/yO+/vX4RBytGP3Wa2m7967/+KzZv3qzM1ZnqsG1S26fI9Nm49NpBVGYVIj09HV/+8pcRF9d/hP2HH36IH/7wh1iW6o//+/lkZe7UxS1oCTyi7oTBPVhGRxFvd9YFNvSgp7sDXU030V51Bp21V2AxO45+5R66Bl6z7oeTwU1sZkFH9Xk05Iq6VYmyYg/TAXnHPyrXt3TWozHnpQHTIvmlfhUufslgVJfW4j1oKfxQWaLgZIBn1FYZtcWa5qjvWhihpv7qT+U6HmFr5ToGtxC+zFpXYC428d3SIezsqlMweifIdEXaY3F9r/gH4eqXItftaryJxhuvoLu1zLoPBfewNfCMudca8aa7Da0l+9BStEtZOnX56n9fQW5Rs14PTgBqXfVEjC82hXjh1cJ67KtsQWxsLJ577jmsW7dOWdMWtb7qTp2Nrg0rlLk6440j/wUjCP7q4in5nT41ishTg0KkrRzl7Sv9IVq6RR1Fn8d3ThxAQaNV4DdaOPL5DeZfme50VlTh+jf/U34P2LIOYY/fL7+PN1Xvf4Kq96yRnaI+/xn4LEuX33ssFpT85i+90VnCHn8AvisXw+A5cEcto720l5Si9LevoKOsHHN++V9wdrHa/Ob6BhT++LdoLyqBa1Q4Ev7vP8n5t4vx9CUYz1zGM888I4vO5OPf//3fcfToUXRt34Du+Ghl7vSD6eKWh0fJlMX0X/i6MoJhH+xKqhB1cl17K7Jrq7ErbxzSc+rcEhSlMBKampK6zdyF/QU38N1Th2+pvynAzQP/vHwdNsUmyNTWhO3zHzLO4qWr4yPcn6kYcvNh+vQINm7ciH/7t39T5uro6OjoaGH/mLu7+/gJX2i0FxUVwbxxJcwpicrc6clwXoK5jBE3KFjYMSsJq6JiZYhWLUxj81+nD+OjG7oBqXN7jFT4Mu0QtVx3fQu6yxthqWuFpa0Tnj0mzDNES6eZu4cHZienIDzC9sW1u9uM6znZKCnKvyXhi9FohKenNwKCghERGQ0vb9sOb5UySx3+2nZcmXKMyxsfw7myBv7+/ggPD1fm6kxnOHp+IOFLd5cZOXvOIfPd4wgMCMRTTz2Fe+65R1lq5fvf/z4+/vhjXfgyCeCIqP9YvQUpQSE23aONws76OO8a9hXewNXqCjRoUqMR2gkJfoEwGZyxKy9HmTsxDFf4MtPQhS8Do7Zb3/zmN7FlyxZlrs5URyt8YftUnVuCi6/uR11BpXTCvfjiiwgNDVXWtkIRJsWYS1P88P99YeqnsXF28ZFpgBihxeAaAGdRDK7+DIcibM5uWDrq0N1eLYu5rQxdTQVy/kC4+KfCZ/ZnZDQVij6ab76DtopjytL+MJKMi08SnMT7JMU1nfVZMm2QI5i6iOfW02OBublQCnHskWmNfBNlqiWDe4icx3PvrMtEe/VZOc1oLSbf2TLNk9EzEk5GD3lsCli6mm6gq/E6jOKe2B+L0ya/uXA2WEcFm9sq5H7t4T118UsVx7F2rPD4HbUZ8vtU5ms/uIKcAl34MhFohS9PxvqhqLULfy2ox9HqViQkJOCzn/2sHFBgj1pfcbAWB23pTAyO/BeO7E7VVt4YEy+jvHjZDQRo7urEby6exu8zrHXZaKELX2yZLMKXlqwcFP7w11Lo4pWajMgXPwODlycgpgt/8js0Z2TJ9eL/z/+CW0yk/D4YjBxT+OPfoPX6Tcz5xfdEe299vhg5pvRPr6G7pRV+q5Yg4rO2A6huFV34MvlhZ/OxY8fQtWMjumdFKXOnD4zisp19FJExMrJLoLunjFw7EIzAdbj4Jr62z05YrTNp+PmWndgQYxv9rKSpEX+//yNcralQ5tjC54CDbCtam1HabBthmoOzfrBxh8xYoOVA4Q18ee8HypTOWKAKXzZt2oT//b//tzJXR0dHR0eLLnwZQ0b6EszR0c/OS8cdcYk22zCUK9PY/ONBx6PdaIQuDotEkDBETcroFv4x281dckTL6bLifgaKPVRuLxH74OhsKnW1kWcYPramrRUnywqRXVOlzO0jyT9IpmMK8/SCq9EIZ6U7j0FnO8xmmergdFkRbjY4dsRuE8a0duQ7r/dSZRmu19dgTVSsNLI8TC5yr1zGVAmHim727o9ODuZtZiecOrrHLM6ZhhnXK7Qb1UOHCI137T2u72jD2zlXkSYMt8XhUQhy8+i9BzTgi5rqcaykcMj7GCPuH+9FjLevzX3k34Oj+XkfL1SUyrQPg0Hjktce5+Mvv9v/PRjRJbu2Sl4fcXRNPFc+N0S9x7P9A7F11mwbcRUdR+/mWh3P6r2/UFmKRSERSAsJtzl2Tl0VjhYXKFO2jOVzsD56lnwOuF/ulcuq21txTjzbl6rKrRuMhG5xVqKIHcEfHnjAbSk8nFzgLF7kWCk62aUeId0MpdzZKZ34I4WiGu7byGfCbgSalixzKT7sGFwZ7/LmLjhXVMM3Khjuflalvs6t0Pdc9+GwGRwh3O9I9jO880i5dxUCExwLnTpb2pH14UnkfHoOkZGR0oHPTkcVXfgyefiHpWvwVMpCmzqYbfU7og7+85Xzoq1pUOaOnNutg1Xo0FoZEYO5gSHwUdofPpFsC2+I+rhatGPfXnvHoMKX4bQfY1Hnq22n1m7gubd2dcp2t7CxYdC28nbQhS8Do7Zbjz/+OBYtWiTbREeFsI3UTvNTbTfV+Y6Ko+Xa7Yg6rR5D/U6029kXdbmj7RxtP1OwF76Q8oybuPDyfnQ2tOLee+/F008/DS+vvrqCbRHbpOkifNFCQYiTizcMJlGvObGOt8DS2SjTFQ0U4cUepg5ieiQnZxcpGGnI/h26O2qUpeOHwS3YKuARdHfWo7tdnIOdYMdZXKfBPUicqxt6LF2wdFQPKLrRofAlAzkFLboAcAKwF76Qmy2d+EtBA07VtCI5ORnPP/88lixZIpepqPUVfVb0XelMDMMVvqjE+/rjsblpuH92irQFVWgPnhV25D8c+NjhyHbVhkzwFTaki3hnV+xo+pXoK7pcVSHtaHsG8/mtiIiWNrG3q7Cnxf54DrTJ8xvrHProHNnPjuxUphuhray9PtWf5Qj6yyhcp92tdlyrtvWp0kL4u7mL94hgOZ+oNjl9QiNlsghfulvbUPijX6Mtr0BGZwnauQ2Bm9fByWRE2UtvoO6QdbBR0I7NCLrnTrGOrVDKnvb8YhT96k/oqqpBym9/QAMQ7cWlqHj1XbTkXBc2gBHhTz8M35VLlS1uD134MvlhZ/Px48fRuWMDLLOmV8QX+rVZh96VMAcRor4Z7vvNTBb9TQX+7+otuE/8XdV+E7ZJmdUVUqSiTUkd7xcgB2xR0MJIP2HiGfhb9mUcLMxT1rDC+T/ZfDdSgkKVFtPaZr6TexX/cWzwdJI6t4cufNHR0dEZmgkTvszUVEdDGYJzAoLxn+vuRLL41MLOpr/b875NpxhfWukI4IgWGiUMOagN60qhBTu6zpYX481rV8TLuuPOojvE9pvjEjFfGCs0XFzFfrWGLQ2XOvEi/fvLZ/EXTbg6Oge4LcPazQkIQoC7hzgnaycV4QPVKc6htq1VHntPwXXsK7ghO8+0/HjT3VJ0o0Jhx+vZGWJfztgYk4Aob5/esHl8TJky4YR4QWfKKB9XV+xMTMHSsChxfHcZ5pYwnG1tW5tUnP/pynmZYkqFwo//39K1Ms2USn5DHV7OuiiNQAqQ/Fzceu+BKqKho+Ota1cdOgD4t9gQHY8t4j4yzG6YR//7yOvmKH4KVhhOcNfNHDR19v9tMUTv9vgkrIyIRYQwMnmeNn8PcW1tXV1S9PKNQ5/IeY6u6Wx5Cb6+36q2V++xQezHy05I0242yxCHhPf+5cwL+J34W39OPLtPpiwSz2/fM/XBjWx879QhZcrKWD4Hb4nn1iieg81i31FevvI+Ez4H9Z3tuFJVIZ/JYyWOxTjDQZwttrulYZYhWJxz330Zbzp7zPik8zKumW1Dvtvj8tYncC6vQmR6IpK3LVPm6owUzU+gF8et4Mjgfkeyn+Gex0CiF5W2umZcffcYbh69glmzZuGFF17AihXW0am68GVyQCf1jzbfJdravjzKrMvOV5Ti34/tle3QrTBadTBhPuZ7RZt6Z9xs6ST3NPW1P12WbhQ3NeJMWTE2xsYj2L1PeGffATGc9mO063w6aGgTsS3W2g2EbRzP8aSwHbbHJw/YVt4OuvBlYFxfeQ9OdY2IioqCr69v7zPFT7Vop7Xf1WliLzIh2nnaT61IRftp/107rX462qdaHE0T+3n20+o+1fPSLtNOOyr262jPT12u3S9xtJ6jQtRtiTp/OMfIzs7uJ3whhaeyceGVfXBzdsFjjz2Ghx9+GAblt6x2JC+Z64dvfXF6CV9uF6YX8kl6Di5+c9BjEbZ52UE057+jLNWZ6nz9B1dwraBZ/iYoANQZPxg50V74QnKbO/FSfj3O17UhNTUVn/vc55CW1mcn68KXycFIhS+Enbb/vmoTVoRbo7qqVLa24F8O75b2oBat/4U2pBv9L8qybmGD0meTW1eDD29k4f3rWTY2tCOf36myIhnJ8R5x7vTv8dzV/XHbspYmeQ5/zbxo46dyZD87slPTQyPwb+L6tLY43yOe+uh1ZaoPinnoL6M4nuv3dngqtvX58lI0ik/azypan9BImSzCF9Jw6hzKX30X3U3NMAUFwG/VUrjFRqMlOxe1e6zvJEZfH5nqyDU0BM6eHnB2FX97/i3F/ekxm9Hd1g5zQyNac/LQfCVLpj2K/acvo6uyCk2XroqSKdf1TElCxLOPwRTQP531raALXyY/jOB24sQJdN61EZa46RPxhf6AF9OW4e6EOf3SGhEK4+gjV2GdovqXdeHL5IYDfdlepQaFyb6B8tZmvJZ1SQ7C0sK+BUaGYZvhJdqvVnMXvn3igGz/7KFA6tG5aQjz8JLt5dXqctl3dEsDVHWGjXPOTbjsOSqjSLIu0tHR0dHpjy58GUNuNezpvyzfIAyHBTYvvPXtbfi3o3uxv/CGnGZn0KNzFuAp8WIc6TW4ApvCBgpAfnr+hM2LNaGCm1FmkgKCYHQQ5UKFHV40XrgPwuNz1PrDyfMR7d3XiTEQFKLQQfHnKxfwbq7tSJTfb3tQjoZR4bHYOccR244MbUJRz5786wgRxtWi0HCbe6yltasLfxUv7f9zri99jCPnCZ0gNe0tSPYPthGFaOExDxfl40dnj/bLDX3f7FR5P2YHBA56Hwl/aqUtTfibMDDp7NA6Thhx52tLVmFd1CybTjtHaJ8lR9ekXW5/jwdC+3d29Py+lXMV/350jzI19s/Bpcpy+Wwy6oAjKAI6Iv4m/3Fsr4xCcCs4w0mKXja5zoOfk7syd3zp7OnGRXM+TnXdQHvP4KmUXN/eDaeySkSmz8aqv7tXmaujAzRX1uPK20dRdOaaHL3KNBPsXNGFL5MDhl7/1po75KhKlTbRPv/64in89vIZZc7IGM06mPt6bt5iPD43rTfvsyMo4GS74GHqa6PsOyCG036MZp1PB90XF67AjoTkAbelkVvS1IBQTy+b8xotB50ufBkY1z+/DafmFoTNi5M2EOl97bDwbyO+i+neNxF+kdP8lP/1fod4BtR52nWsk9bvamQ2Tsr/yf/UZXJm73F71+GHxfrJaet6/Np/mfVDrONgnnoM/hbVoqKdp87XftrPH870QN+Hu0z9dLTM/rujaUep+JhW4Nqn53DlraMIDgqSUcjuvPNOuUztSF481w/f1oUvNriFrIB33P1wMnnJ9D4NOX+EuSlfWaoz1XnhO5dQXNEmI/NRAKgzvrCushe+kOzGDvwpvx4ZDe1S9ELheEpKilym1ld6qqOJ5VaEL+SZeenSHrUXQv/k3Am8dPW8MscaZYU2K23SwfwvbOmLhR35q4unbWxoRzYvoyuyMziKtrkyz56Wrk58cD0LP79wqjcCzXD9h8NNO8pr++riVYP6y+iL4kh/nquKve9vJEwm4YulrQ3VnxxAza59MtqvwcMdpuAg8d2MjuK+wUZOLiaYfH3g7OYmI8I40Q9LO0/cG0tHJ8wtLehu7IuG4JGUAHNdPTprauWD4TE7XkaN8Zo7m0aSstbtoQtfJj/TUfii+gM+k7rIxmdBGEE1o7oCZ8qLUd/eLt+jCAeUcGDP/JAwXK+rwRc+fVfO15mccKBvnK+f9INzUDEH9rLfRIu9n4bt1UDCF/qE2NYEiOeFkYbzG+pl6m6dsUWP+KKjo6MzNKrwxfAfAmWeDWaq3DUd87fLO++8g8bGRljio9ETHKDMnZ7whZSjMdQoJISjpR0ZC1r8xAsXjQw3Y18qBJqUGVXl0tAkjPLyhYXL5YgU1RFd39GOoyX50hDly2qgmwcM4qWNL93hnj6yw4uRUlTWRcXhS4tWYE5gsFT7qnA9hkpldBk6B4zC+KVRRIOIIVkJBTOfFS/l2o42niNT8PAaG8W5uIjzN4oXbC6lmISj0PlCTdEInQYqHIGifdF2Ev947jS6S5obZScbnRC8FhVeEzuveHzuu7i5weF6JrEPD/GQnyotkssJo+msi54l96/C70wV1W3pkarnqtYWuIhz5/bqneExmUKiUVzjuYoSZS6wJjJW/i2SNfeR94L3jvkya4QxSRGTOgKf94sdc7G+/lJww9FDKjsT5+LB5Pm9jh3up1qsw/PPrKkEI/+wo5TGJR0U6rPk6Jq0z9pd8ckymg8NUWfxPKrXRLotFqnYpzqbzw2jD3BkkaPnN6umCgc04Q3H+jnwF5WTm7hv5S1N8l7xpYp/BxXuj+IovmDR2XMr8HybetrR3NOBbvGvq6cbbTCjpadzzEuzpR1VPY0yysslcyFaxbyhMGReh1NzK7zDAhCzTO800unDxdNNPhettU3IF89JWVkZ4uLikJOTg+vXr8MSGSpKX7QRnfFlU0w8VkfF2tRh1W0t+OXFUzIN3q0wmnUwQ6a/kLZUhrNVUdsypgjiJ+tjtk+0C7TtSJ1o517NuqRMObZ/7NuP0azzH0yeJ8XAfhqxrHofisS5d4o2zl3cB1+3vshwKsOxy4bDPVGJ0m4gb771tvycCgQGBmLThg3y+/nacuS3DJ7S8VYwXsqEU2cXYlemYNaa+QhJjkawKPyU3+con5xWvofMibHOnxsjv8v56nf5qUxrSihLivo9FiHiOz+133vn8TOFn6KkKp/a772fceIzDmFiOkx8Vz/lcn6fx3miiE+uKz/VIrYPludmPdegOVEIShYlKRIBsyMQKIp/YgQCEsPhF88SCr9ZIaKEwicuGN4xQdYSbS2eUQHwjPSHR4Q/3MNZfOEe5ieKL1xDfOAW6gOXYC+4BFmLKdATpgDxLuDvAaP4dPZzg7OvK5x8XODET29ha3qbAC8TejyNsHgaYHE3oNvdGd1uTuhydYJZlC6XHnSaLOg0WtBh6Jal3dksi2eIH+LXzodHQF+9Ie3ciEB0d3Sh6MoNOeAhJCQE0dHRyM3NlWHhw4NcsXmpbXTLmQZTCTkb3UVlZYaLbzI8IjfB4B4qhUMdNRfQXnFSrNU3olZnavPmvlK0tndjtlG8WzfX6WWIYmqut/m83RLubsTWMG8Eufb5VwinQ92MKG4142phCSoqKmTkRLaNan3VExwIy6zpM5p/quHIz2FvdzqCHXlb4hJkZEQV2pH0pxwvsfrEKJz+UvoKaQOrvjf6wnLqqvHpzevSTqbdqabP9BHfaSdzeUWLVQjhyOalr8bfzUOmNeI+6D/i/rU2La8n3MtH+rGu1VbLecP1H9J+ZqRhjsRXsb8n7ISkr29VZKzNveP18f2jrLlJRnLjtfG6tHY9IzowPbfq+xsJ3S2tqN13RH53j4+F1/y58vtE4CT+Di6hQVLQYmlvh4XRW2rqYG5okuIWt5hIOLuKe9htQXdzq4zsQkFLV60o4tNc3whLa5t8qTB4e8E9NkqmUKK4xyKeL6OPN7xSkxG4ZT085yRaBTOjhHNJBZxLK7Bw4UJZdCYf+/btQ3FxMSzJ8ejx60vfO5VhffHCwmXS763Cd+qq1ma8kXNFRpLfW3C9N32/tVTiRkMNckQ9xhRpQ6VV1plY2NfBPgi2Y+zzYYQve+z9NOwnOFyc39tWaeH23A/3x/1y/zpjj7Nopww3ChEfH49169Ypc3V0dHR0tDDytEm8D4xbxJfPfOYzKCkpQdemVeiem6DMnZ4Md8SGPRS9/L91W2U0E5VOYWj85uJp2UHG3LzfWrMFy8SLMV/eCUUvfNHdJ4xQCjwY3vXLi1ZiYUh4b2cYO4n+4cBHssOIL8LfXnunDH2qvlirBi1T8FyrrRL7ES/oBqN42XeVL+EURDBCCY//3fVbxUt5ZO8LMl+O2an17vWrKG9uhsHZSQotHkqejwS/gN71OFp7z83r+OaR3b2RThxFI2F0lb3514VRbY1wsyU2Qb7cu4rz0cL1mDaIqRv4BDtaj/fm/x7bh0/zc+W0o1FDhAYaUzFk1lSgw9wtnRoPJs2To8+1jgAa+V/d94FUR9OJ8L3122RaBu19LGysx1vixYCfFNMwDdMDSalSCa/+zbjembIi/OuRPb35nX+48S7cOWt27/E6xD16IztD3NdMea3cluEG+Teg4+S17MtyvaEivrDDNVT8PeYHh2LbrGSZhkmFUYBeUZwk/DtSYEOR1VAj9sfrOeDfd1/hDfk3mRsYjEfEvoI00Qi4r79cuYDvn7E6WG6HACdPeDu7wQDb52zssMgIL7WWFrRj8EgvKi5v74YzI74sSsSqL+9U5uro9FF7sxyX3ziEqmvFWLx4sVS3Hj16VI/4MsH8y4oNeGJuWm8bQK7X1+Chd1+RzoSRMpp1MNuyH2zYgQ2irdC2UQUNdTKfM0WcrkaDPNY9CXNsOhGI/SjTodoPMlp1PiOlfVe0wwxTr8L7cFW0ZWw/OYrWw+iCjTGzZDooeztCj/gyfhFf7CODTHvEj0iOhqSBykl+yK/aiDLWaau+wTpPbsJ/akQZoszjBtb92C3r3Z91nd7v8ovyoSyTk9p1tMutX+S83mmBup7NOvKjB4EJEfK7PW21Tbj81hEUnswSz1kSvvjFL6K0tBT//d//jUXJvvjPv5u4zrDJgHv4Rpi849BjboXRKxomUcSrObqa8tGU9zeYW0be4agzeXn638+jqr5TRhxJ93Mc0VRHA00RVjPq5ygwx8dxRDhyob4df7pZh+vNnVi+fDk+//nPIysrS9ZX3XMT0bVJT3U0UdxqxBfaoG/f96RMhanCR+mNaxnSN0RoY359yereKMO0H89XlOAPGeeQLexpptVm+k9GP1BtX9rNf826iB+cttqhjmxeHod+oLeF7VvQWCceYyckBQTioaT5NlEVeTxGMaaPjoxmxJe7EpJlJGlt1AZpZxfm4ZAozV2d8BPLKBxPDQyxeT+5rYgvldXWiC/i2vw3rkb4kw9SEassnRgoeGnNuYH2kjLUHT6JrqoaGf2F0WicxHtBZ00NzI3NsLR3oIeRD2jjiHOmkMXJ1cUaKcbfD64RoXL7hpPn4JmaDJ/FaVLc4xYh3kEMVl/gaKFHfJn8/Mu//AtOnTqFzrs3wRLbl753KvPfG7ZLf7Q2ijn96YySxfrsVkUN9DUw3VqKqGv8XMXvSUyrtQIHYrI+yhd15bHiAplazh76MVZFxIrt+s6LYj+m6JkXFIr0sEgEu3vIwT6sfzvMXbhaXSkj36u+jjVRceL4wfAwufaaFq1dHXI97eAcFUYxWRBiTQmkwoG5u2/mYnlEtFzOdoF1p/WYZimsPFR00+E1aEnyD5KRuOijp29CrX/ZJrCermhpksLDoUREvPaF4jyCPGxTXav7Yf/OoaL83v4GR9dEMQvTSGvvMSPac1qF++J159ZZhS/qvSdbxfMS6dUn/OrqtuB4aYFsk+y53eeAMLWStl1Tj8cBwqsiYxDt7SePQ8yiLatsaZEDxKebIMuQcxOmPUexZcsWfPOb31Tm6ujo6OhomZCIL01NTbDM0iO+DESkly82243goOFC9TSNH45IuT8ptTcUK53OjNDBF1OO4G7q7JTHYUQUGhVqBBSKHdSwc2uiZuHhOfNsHAgUzLwsXuIpoKHIhXmC2SlHQ7CgqV4YIPXSwLlDnNs9iXOkKEalQhhUPz53DLvycqSxRzEFO98oumFnlDqChgadp8kkI6ZwNDexVxMTdlj98OxReb00mHh8qs/twy3S8PqvM0d61yt0sB5tuqzaKlwU9484GjVEY/iT/Bz87vIZmWqBRhGdHRwhnhYSbrMuBScXxL44eofLnkpdBB+XPgcmR9i/lHlBilJoRHJfFJMwLcPi0MhepwkNPE/xnfeL6mgi01X49N0Ldk9k1VZKhwhHFVFsw+Nmif1RVU0DlAwV8YXnQDU+/94UO2nX4zl+5+QBuZzPBiPJEEfPr3bE/ng8B+rflxFveA28T6nBoYjz8Zf7JNwX7+0nN3Pk9O3Qhi409LShrqdlnEqrjDZjHsGIXkP2DTg1tcA3IhDRy5KVuTo6fbj7e8EzyBcNJdXIy8pFp2gTmpub9YgvEwwd56lBIcqUldLmpl4B40gZzTpYbcu0ghZGS3lF2AQvZ16S+6JolvuLFPX0LF//XgcNsR9lOlT7QUarzud93RFPQWfffahsa8FvLp3Bu7mZ0pbhfmnDzPYPlIIhdV9kLCK+WCwWzJ07Z0qUlLlzET9rljzvMYv4cjlLRnyRUVySbcVO0xrxmPFZ6y3OanGGs0FbDHA2aorJAIPJCIOLbTG6mGB0VYqbi00xuavFFSYPa3HxcLMWT03xcoertnh79BY3H7V4ws3Xtrj7eVmLaF+sxVsWbaQXe3guPhEBaK1uRIEShczb2xuXLl1CWKAbtiyb2RFf3MNWwz1kOUzesTL6C21+pjZqKfoYXU39HfA6U5t3DpbJiC/zfV2xKdRLRhrRy/iWwQh3MyJQrJPf2onM/CI0NDTA09MT58+fR0+wv/Rd6UwMtxrxhf4zpu/kgC8VWn/ZtdW99uiXF69Ekti/ahU2CNuXohfamEztQN8LfS5ro2NldGBC3xqj5dLGJI5sXtrQtJ9pR9PXQj8VP9k5yEFVqg1N24DfjxTny6gww/UfDifiy/Pzl2K+sP1Vm5c+Q6YT/9HZYzIKNO1j+rtq2tqwOCwCXpp3AN67W434QvFIw7EzUkDiLN41KAxxErZNT5d5zIs4cTixY1xcM6OnUfDCiC1MWcToLKagADSevYTu5hYYvb0Q+ui9cI+LhmtkuPz0SJglSpyMBMP0RZ5zZ8MzOQEeifFwnxUDl1DxrAg7rvH0BXjPnwu/lYulKMYi3rVZeFwnzXN6O+gRXyY/e/fulYN6uxnxxXdge3iqMEfUhc/OS5eCBBVGiDpalI/fXD5zy6IX+g3o5+ag0s0xCb31HP0PLAtE4QBN1vVhXl4yWhejv2pZFh4lo6xz8C/7OFgYMau5q0MKE7fPSpIDaijs4ODfeWJ/CX6Bsm4vE/t6JHmBbA+YenpJWKQ8rlwvyLoeRROqqEPl7oRkPJ2aLtdXj+nl4iLLUymLpC9mqTgv7oeF9S3r90B3D+mTYZ1sD30tjMb+2JwFUmBEocZisX9ur94P3ou5gSEyQryzqG/kYFpRJ2the8g+ocfENdEXwmvX3lN1P4ni2rJrq2R9TxxdU3u3WQpftPc4wI0ior52iO0UBwZTZKPe+3eUlH9fSV8loxCr+6Oo5VpdlWz3tIzGc0D+deVGbBLba49X1daC7fFJ2Dl7LtZExsn51n2GyXsZJs6d/Rz8u0wXnGvqYcizRnxZu3atMldHR0dHRwujWzLiS1+LNl6ob5c6/aDYQmtkEKpfVcOJIzJobKlw9DPVsDRQaHCohUYVX1pV3IwmOTKapAsjQB3ZQrhWZnXlgCpuvhSzw4vQOPQy9b0Y8yWaoonDwiDWjlrn9903c6QqWgsNaUY+GQga1xRgMFSiCr/bp4Lgejyudj06FGjYaqGRpnUKOIL31v7areefixol57KKp7j3ccJoIxSyaJ0phJ11H93I7pcnkyF17Y1p/h2ThXGswpHpvaNpBRztQ6Pu64tXS+OaxpsKBTYTyXg8BxlVtn9firP4HNob/trfw7RH47zS0RkIdi7Pu38NvMMDUFlZKec50SGoM6nQOrZHymjWwWxbtDYBocjywxvXbPbFfbCzgKNxRptbrfOT/ANtRLxckzYLR1tp4X6PlxaK6xn71CH33H3XlCmrV41fBBa93Zp5+IQHykg/QbMjcfnyZZk2hChxZ2Y05qY8dDZch7m5EB11V9BWshcthR+is/72hXg6kw/V9aF2QutMPpYEuOPRaF+EuxlkpESO5NeZuoR7evf3qQlbk6IUQn+OFFbLKSv0qdEe1vrU2Cmp9akRRlqxF29rKWmmDW3rD6JNe7SkQBzf1obmgK1EYcuOJuwUjfezFal3CHuenZtaO5scLc7vN+92MLi7SREJaS8qQeU7H6Pi9ffHpTSeu0RjU5aWq9dQ+fZHqHjjA2t56yNUf7xPpjIiTkYjnN3d6RGHwdMDpgA/uIQEwtzYJCO6tGTlwiUsBKbAABh9va0pkQSmAKsfsPXaDVS++0nf/t/8ELV7D8tlOjOD6fZeQxEHRRtaGjs6ZHT1WxW9MOLW8wuW4unURVgcGiHrO/t6mdFH+C7PASqMwvVi2lIpYNHCAS5+bm5ye7VQSPg5se+1UXHyvLV+Fa7PyLFPpiyUwpin5y2SAgl18LAKp1ODQvFMajpS7AYocZm/3TEpkuEx2S6wj0Hbfsh61zdARtFilF/7fgIufyh5Hl5IWyYFOByMw/PU7oPfOY/LKKx5UazLAT72bJuVJM9jTWSsjCKmjRJG1P3wvvhoRI2Orkn1o2jvsTpYSoVtCdtGdRut34j9Tup8Fu6D+9IyWs8B0Z4HC6Prb4lNxF3xc+Qgcu1++Uzw/twp7iUj8GsFtFMepf7R3yt0dHR0hsa2xdGZUPgS7WFnkFGBrAo6uFwbepBGCEdyf0EYRdqyMSbBJhSgNCSUziL7fVh6LLheVz0sg5bh+LQv0eyQKmpkbsj+kYG4P3tVLc+JBspA0LHgSNTBkTVauJ69GIY4UlYPBQUn7Cizh518tW22+6Mh5a8Yeoyqo47wVuE2ju4j7w9DDGodJ/wbMKeyysGim1KtrMWapmKeMGyX4MvpK0VZIUMrTjTj8Rzw72IPI9/YH8PJ5nVhmqM8PtPrNVtnLAibF4f5D6yBq691hGJPx+iLFXSGD0eO0uGuhY4IVUg5UkazDmY7Y9+WFYp9ORplUy32pUYbG01utc7nuWvvA+0ZpmhyZEfwPji6P6ONh7v7lClubn3OMB2dsSBgVhhS71sF38gg5OVZR9l3mXUrpqP2KlqKPkRzwQdoKfwYrSX70NlwTVmqM+1Q2ildADh5oWdkZaAHHoryhb+hR6Y6Ik7msbcbdEYfjhq3HxzDlAiqbcvONXvRN6cfTErt51djZ5oWV6NRCmsGokzYro5saEZwZmQXLUz1oI24OBrEePvJzkctFOHk1NYoU33QLnbkU7tVnIVd6b9pDYx+vjL6S9OFDNQfOTkupS2voLeu5XHrDp9Aw4mzNsWivA+zLu5x8NtuPHMRdYdOoGbPIWWOLTKyi4Bpk2z2few06vYflct0Zga97bnmPXQqE+Pj10+wwD6IM+W3lnqTwg8KQLbGzbapa+kPYfTWa7VVop5stvHzU5ixIiJGilUo/hgM+jHmBAZLcQ6jxLIfwN7CYr8HI4wEuntKYaOj9fjXo/hwQ3S8dcYgRHh5y30yrRGjqLC0i+9aKN5gFBamVtJCsQqjznAwcm8kLlF4XoyOwn21mrt6z42iDaZEYoQW3hMVtj3sH+B5qPthBPsrVRVyAC7LoeKbMhq+fR/KYNAXw/2wcOC1Fp4T2wp1+Uj8KWP9HFD0w4g59AcxOg4Lz1ELn2tGmNEOOtbR0dHRmTmMm/BluhmHYwFDvNkbnMyryfQ2xENR5KrQIKLRQxWttsT4+MplWtTOIvt90MihkTUctGkVCEdtDtYJ1mI3qoVoO6lGG3vDczi0dHUNaLzZXxvPXFURyzyadtcy2PE5Sp6dclq0HXjHSwrw5rUrsqNPa4zzeFQqrxLG37PzFuNLC1c4VH6PJxP1HFjvofbuzDDG7qejMw1pq2+R4Z0l+rMzodBxRIe7Fr78r9Q4MkbCaNbBdC7Y18djEdXlVhiqzh+JPTOWbccbBdn4682rU7pcb7KOgtXRGW2Y5mqeRojZ2TV8R+x0xdLViK6GXHTWZ8LcXACL+dZG0+pMDXQTbGrg4uyEtcEeuC/SB15O1nqqp3PkvgWdiWdRaHg/QQlF6IzOS2j72o84pyDd3qfGYi+QIYP5MdgR64i6jjaYe2x9TtzLaNcPHOVvtBO009fF63fEqLbI4p56zUtGyAN3wW/lEpkqyD0hblwKo7ZIf7P42zA1EVMXMfqMtjA1Eekxm2XKI3u6auvku7O5vkGZY0tHmdUn6xISZLvvWbHwSEmSy3RmGtPDNxnm4dWvXuNAEkeDOofDkvAobIlNEO/qfYN66avYX3ADPzx7FD85dxw/Ep9/y74s+ztUGJVjZWSMjIoyGBQNMkLtT8+fkPviZ0Gj+P0qywnreD83dzn/J+eP965HcYQWV7GvuQFDp2Cl/5/b/urSKfxY7IuF3+0j61KUoxXSULzxUNI8GxEH/RKZNZXyfP7n3DG5L54fo92q18C/RoJ/gNxWjVbCdEpMG6T9S/Gcfiqu79eXTsvyywvi/M4ek6n7cuv6Cx4dwaj7PP5/nz4s7pdt/Uchycd51+QyFu53uIz1c8C/Mdu3t3KuyJTfLPxuH12N/SlpwX0R9KcLesQXHR0dnYFR68hxE770MoadD1OZdVFxvWpVFRpETJFT2tx/1AihMpbGDA2VoQoNQ0dQfGH/4j8QjkaqDdbY2kev4eZj2fl0Kwx07TS2vO1GCnVbemSoWiJHishvfQzmBGG6KWeNGInbau8nDT0aaTQAaVjSgLZXadNJw9CKFMAwXONEMR2fgymBeo/1e6czBHmHMpD98Sl0tykiACVEs87EcLO+tp/DmQ6A9dGz+oUVHg5jXQcP1JZxvlawORkZ6D6M5bnvKc/HrtK8KV2KWx3bmbfNIM+lzsyhtaaxT4g5yesQHR2dmYt41UeT2YJuxUTSa6upx8KQCDnaXhvNkH/Ogsb63sFkjmDkQUc+NPvCEeocpT8Q9lEUVTjS3164zg7FgQQpownt38Fs+9HESbzf+K1agqC770Dwzm0IuW/7uBTvBam97wDe6QsQfN82UbbbFI/Z1k5US0cHOquH1yGspSUzR9q1/utW2u17G4J2bFHW0pkJ9L6LT5P3HPvBJGS4g2MdsS5qFgI0Pg7eL0a9ojDjvdxMGe2cKeH+mHFWpmHT+r0pWlwTFatMOabN3Cm3fzvnqkzFzE+mfDbbDWhldJZPb17HG9lX+tYrvtlv4CujuQ9Fq6ir37+ehZczL2JPfq4s/M4Uy9ooI6xTGVWMA5QJI7bPDgi0sScqW5vx64un8Hp2BvYV3JD7+lvWZbxxLcMmci2jxC8ICZOCF8J7Y9/GsD+DWQIYOYYlo6ocu2/m4pWsi7g+TOELRaGvi2O/knVJnpsW3tOTpUVyGQujygyXsX4OuL/L4nr/mHFOXjMLv+c11CprWKFoSf17TAsG8ePp6Ojo6Ngy/sIXnX4sDo3EZxcsQZidwdUgXspoSKmoogsVi3iNP1dRgp9Q6TxEoaqW1HfYhvdjGiSGNhxOzkM6BLQdbowqE+Lh2EhkWLswL9swsDQw7dP5TDS+rq4OQ+jNCQxBkJt1dKoKI7qoaacYJtFemBLq4TngfaShpXUscFv71EwM80fDj0bwj85aFcvMvdymeengHhiOcV30LOuM2+BW39Om43MwNZgeL9Y6Y0v+satS9NLTZkZ0tJIazS5Xr874Qkc7X8C1bS/bg7SQcDwyZ/6IxS+jWQc7SsMUKLZxRLjYj/skepbsOx54HwZKo8d2frgiXx0dndEj79Al0SadRk+H1SlsMuq2jM4MQ3/kpwQdlh58Ut6E3eXN6HC22jo9Lrr9PJVgZ+Oz89IR7xugzLFCH86J0gKZWoHQfuzQdFQS+mV+dfG0Qz+atvzh8jkU243w18KR5Y6YHxzmMAoNOyoHwpGvhnb4YPYs0yzZp3pwMxjEu0Z/+5h+K/qvRh1x4i5hIfBIToRnStK4FNeo8N4bZvD0gKc4tte8OfLTFOgvxS49iu+OKY/abuTL78Olq6YOrdeuyw7H7tY2OLu6wD02Cp6pyfI4ruJ6dWYOll4/8PRt4LWDNkcCfQ9MK6ONQN/ebZYih6yaKmWOFfq/jxTftBEA8o7GevsPKlSob2/HpzdzewUs/LxeX4Mu+3q9ow2f3MyxWY9+GQpitHCQ6lCUNDXgg+tZMnWcCr+fKi3qJ2BkpDBGDCPzg0LhZeqr++nDuVJdIYU66nkRfue59osg4+qOBUFh8nutaKfa7KL80sfx5fQV+OLC5TKlkupX4rlp9z/ejMdz0Cmu71RZkc0943dGwbHv83LXRJ3R0dHR0Zk5jH8vgKM3uBkKo3Yw1+OXFi2Xode0RgGFEadFI07lq0qRMLa0YgsqgIOFYUPjjQIJR4WKWu6HhiDhy7XWIOTIiHnCGBtISOEnjDYWwryYHRrjiR13qUEhMv+kPasiY4URZtvZVtvWiosVZcrU5IA5P+1zcNIJsCM+Cb52HWg0nDnShzASj72BmyCM2/TQCGWqj0UhEXKZlqbOdhneUIWGoQr/RrvyruGvVy/i5xdOSnW69u/OcIzsgLxdGNJXe9zhMh2fgymBXnfqDEHRqWxkfXRKjq6/9957+4QvOhMKHe1sjzk6SQvr4IeT5+P5+UuwyEHbQVivPjpnPp5OXaTMGd06uLS5sZ+DnOJKCnK10ImyJjLOJlTtREPnvla0w/tAe8b+PtDxxNzODIusM97o7dZMJv/oFdEmnUZ3aycWLlwo5znrj4TODEN/5Cc/3T092FPRjA9Lm9ECQ299Bd1umBLQzrtvdgr+btEKrBZ2r3YgEiMc0n+zKy9HmUNBepUcDKZFpjQSP1Z7X5q2ZIr9nCkvthmRb0+Ut8+wbeiK1maUNFk77FrEO4J9NEZ/cU72A7TmBYfC0zhwJE9GirYfXMVoDsvDY/oN0KIPjDb/dIUpi+oOn0DV+5+i+oM9aMtT/KrdFjRdvIruFqsQaigYsa7hzAWYG60D4OqPn0HVe7tRvWs/WnPy9NH3M5DeASjTxD/nKIoV+xkGGtQ5GJHevr39ByoUYaip5uy5WV/Xz6/uZjIi3HNgfzfFjIV2KXnYx2H/S2wTx2X6IC117e39hI/DoaSlqZ8ohTDCSpNdah3eNzV6fKi4DvooVGhvFIlzdyRKYWoptgtaTIa+gT05tVW4WFlm0zfAYy0Lj8Zz8xfjCwuX4+uLV0nfkaPBvePJeDwHvA+O0nFVt7WI9rTvHpHJHrV4ROj9Ajo6OjrDZvyFLzMUvgR/TRghavlfS9fiK+LzhQVLZYeMoxf0l66et2nIz5WXSJWvCg2oReLF+jMpi7Ag2KoCVmE4vJ2JKXgxbalNWhy+tNuHr2NoP3a8PTE3DUvCopAaFCrTLj0wO1Uqh1dGxMj1jpcUotwu7VKMtx8+J67hjrhEuR1Hs9Dx8NicBfBx6TN02Dl1SRiFAxk6E4WXyUVcZ4o8Z547r/sxcR82xSRIgYkKz59/EzXt1PmKUpscnIQimufmLcY9CXPkvng/dsQn44W0JQjVjMbni1JubQ0uVJYqc4AHklLFekuxQtxrdTQQjeFsYdzScNMeh8+HfUflUNCItN+GxvC94hnhea6NipOfw2E6PgdTA+tToI30oKOjUnwuF5kfnkRzRR3uuusuPPjgg3B1tR1ZqDNx7Mm/jtNlxTaOCsK2gfX/lxetxN8vWS2d9nRcfDndOv1VYSd8bsEyUZ+mKluMbh1Mu6JGGQGrwugxnxPtFtsv7os2ymeFjbA0PMpGoDvRZFSXo7HD1lHHUb68D8wJzXNniFzaWbSDdBfBRNDXXlVkFshSmVUoS1V2EaquFaE6pxjVuSWy1FwvRc2NUtTmlVnLzXLU5VegrkAphZWoL6pCA0txNRpLRCmtQWMZSy2ayq2F9WBzVYMsLdXWQkFga20T2upYmtFW34z2hha0N7aio0kpzW3obG5HZ0s7ulo70NXWAXN7p7V0dKK70yyLxdxtLd0WWXosPbJt1tvnPgpPZkkhZpu451u3bsXixYvlfP0W6ejoTDYOVrXi3ZJGVHd229RXeoU1+eCgHa1P7R+WrJGfL6Ytw6bYBBtxCf96BY11+NOVcza+Bwqnr9VU2QhN2LH4TOoibBe2rzYSI7/TF0ZfGe31oQhy95T+N9WGpm+Nvjp7G7qj24wLFaW9nZ/0MTFdhZYIb188kZIm/VOqXb8lNhGug0Rf5P44KM5msJyzM1YLe/iZ1PReX9+9iXOl30p7rdMJRmWp2XMYNbsPoun8ZXSUlqNH2G0GJfJNe2EJ6vYdEfNs77kjOssq0XDynPzu7O6G7pYWtFy7jrojp1D1/idozsjS7b8Zhvr37p/8fmpSYTeYhLCPgKnjRgpTLBvsolKZxb7to6yoMNqHI9+2VixiD+/6cKKZOFqP58HzGSn2PgcVDo4199geg+eu1vf2Ke74zLD+H4gWOxENUe8FB1O9dOW8jPpvvw9Pk4uMekafEX1Hn1uwpF/0s/FkPJ6DgaAwyl5IqqOjo6MzM3ESRpvDFqGdStgBGvdb4cknn0RZWRm6tqxGd7I1v+p05SvpK/G8MDRMmvyLVPZqVaeM1qLmodXCl1RGafnNpdM4qon2Qnxc3fDNFRuwfVaSTYhTjurgC26OJocj8whz9AtT+Xzv1GGZj5LwnP7/7P0HYBzHke+PFxY55wwiMIAkSII5iiKpQFFUonKgrGBZVrYt23e+/73zu9+9O793L9z5bFnBki1ZspKVc6ACFZkDCAYwASQAIuecw7+/tTOLwWJ3sQsswAVQH3Kwsz09PTM9vd3V3dVVf7/iQrohcz4FGDrNKAZwfVDU2MAm6JA+zMrB5cFfj+XQHw7u4nPRkb9j3uJBplohWGBQoaqtlQUTnAdFH13YQwE721hHv9n5FZui03n28htoVdKARQIIpc8e3s/XMuJsvH9du1E918CAhHU8dPB/vfoiFgqNQCgqaW5kizq4f+QbJv6Mbwer4n/93eeD7h/X+smSNYNM2uKaSAuDF0g3KTiUplm5kkI+/W7/9/Se9k7Any+/nleqn1bvEBtWEkEohtnFC1PSKF0Jrfr9wOXVf+77jt46dczmM8EH548+fUv7ZiY9PJKeuPQa/tTBe8G9FjbWU4ifH0/MvqAEaVvlF9f65+8/5/3zVQ6cfdbJit8HX5KpuIwSF06nmRcPWH8QJjcJ8wdbpLJF2aECOvbuDp4Qvvzyy+nOO++khIQE+vd//3f6/PPPqWd5NvWsWKjFFs4XsAgGpVcMXtvqxGMwoLu3T9Wl3RSo6n4fbxPLCgCWwK55+6+87846GGn929pLeaDfKFdg4OFcUwOVtTbzwAWUaUNwLdWuGWUX432B4doP4K46H23vv6/bxIo5xvxEPuC+4BIKVnVmR8WaFVlVHGOuT6X243zh/9K75NXYTNEzkgbKjf6B7/jP4YZjeE/6V/2Y+T8fM+9rn+ZA/j/wiXCkYfky8MHh/A1/Br6bAweO8X/tUzuGfY6vhXOQ5dhAOhzC37V4fAAf5u+cgm72hD/0c9V/jmP+HWqn8Q7CzXHMgeZ4SAlfOMAcxrs4pn1yAPZVmhxsPob4fMhwHxwHu5Zj/GXgHP6q1RHqu6O26dz+k6pN2knN5XW0ceNGuuuuu+jo0aP0v//3/6as6aH0n48OP3k41fCLmEt+4TNV3mLStp962iups3ov9fcNPykneDb3/GsOldd00tbUcJobpiuiGodftB/YoDCAcFfCXI1vxF4YsA6feCyJtG/h9LuaNnq5qIHOtXUPqa8wZoWxK+H8YEsOxJiVcdIS7jjgxsAajMNgbOwvR/bTNoNLDB0os0D+TTSsikccjIXBDUWDZtUFK9bTwiN4AhHWeu/99G0OB7ZkXoB0ilU6kKEx6QmrKkZXnPhFnVBp/bfvPqNTdTUcBuuMT2zcMsRqIRa9nawzK+lMU3I9Fi5B5jXKvday+PppGfTf11w8ZKU8xgzzVZ5grA9pTQsLJ5P6nVvkBYU9mXwigTJS/8W3VP3h59Tb0squjoIyZ5B/YjyZ/Hyp5uMvqKephXzCQin+1i0UtnQhefn4UPHvnmElFpD17H8hIeqsrKbaT7+ixl37VaHqU/Gvpe7aOmovKqH2/EJWnAnKnE6Jd97M6bsDn7255LPvMNdF2ATP4+c//znl5uZS17WXUV+ye977+eS2udn082VrB9W1mJd4Lz+PfrPrK5cWXS5PSKH/s/5yVpzRwdjEf/t2G+0qK9ZCBpgREU1PXXYNJYcMuLSpbG2hf/jmU7awZasdsK7zgLPxMG7w7+s3DVqY6sx4BqyG/d3XH2vfBoCyyZOq7jZaWEFd+//t+IK+LCqgP2+6nlYnmxcSA9Sxzx05QI8d2KmFDOYPl1zNSpw6yPs/H97HluB1oEi5JC6JNqROp4zwSB6jsW4FYV3lxbwcy3WcGaMB1uM0WECLMqDPJxlxFNfd5QC8f/2dgyzp27s3Z591ouJ9ooB8v9zJitr/8A//oIUKgiAIRvz8/CgwMHD8FF+2bt1KFRUV1L1xLfVm2narM1mw1wl2BF4CLLHArQ38VRoVA4xgwuynS9bQCiXsOPLvq2NLGIBwhtXbl6bPoCAHplKBdec3OTSMHli4kjZlzBokVNoDzwWFEmgmv3nyKKen4+zkl7PxRqL40qbyB5rI/laa2EYguL5+4gg9dWjPoPvHQMjd85fSDbPn82DG0CGXwSAvsLL+jZNH6KVjOZYBFWB8RsTrVR0NKL5YD+ZAsxsC9G/3fU/lrc3DTgzqoCzamtzUMeaVM4Li+SgHzj7rZEVXfAmODaeAsDHwxy14JFnXrHY4wVhxtJCOvv09W0PAgD2UXpKTzSa2/9f/+l/0xRdfiOKLB7E2OY0tkmTHJThsd6yxHpBxZx2MlaS/WrmefVDbUsgBOB8KoFAkMSrbODNQNFaKLwCWXX65/EJW6rTXBmOyAAqeMLlrtOQmii9jj9+bn5CpsobS0tIoJiaGJyNsbQCf8Jlv/K7v6+HGY87EtT5uvTk6pm/A1rWsN/0YMCufYNP2NQaUSrQw/kAk/sbHLfH1uFoc/rSEqU8t3HK61TFLOgpzmPbdeEx98p4lDDsI4EP8h2NoYeZAfHjZbZugiHn0ne/ZIs+GDRvo7rvvptTUVFbChDLm3IwQ+u3P52uxJw9+kVnkF56p9gZk7N6Oamqv+E77Zh/vwAQKnX6jOn+Wyly0C/3U215DLYXvUGddrjmSMGG5518PUXlNB80J9dd/QqquMH8CW2EA4a6EuRrfiL0wYB0+Ebk9Ldym8svu2nZ6saieClu7bdZXovhyfrElBw4HiisWCe0qLaIPC06y23CjzKsDORUWFrfOzaYYqwVP9rCWG23JvLg27tfeOB3uD1Ybscjt9ZNHzIEav1q5jm6ZnT1ocZoRnFvS1MDuuCGP61jL4lgsd8/8JWzF2CizW4NxJbhawqIvHXsy+USis7KKzv3uT9RVVUMmfz+Kv+VaCpo1nXwjw1nBpXbbdqr56Evq6+qigJQkCl+9jCLWraLSZ14cpPjSdvoM1X+1g5oPH6e+9nbyT4yj6f/jV9Tb3EJdldVs8aVpz0FoX1Hslssp5opL+dzRIoovns+jjz5Khw8fpq7rNlFf0oB19YkK+tGPXXL1EPf8sMKBMfD38/OcVn6BQsmzm6+nDIO1EbhS+r97v6W3Tx3TQgaAdSzU8+xuTgMLdX70ydvs9sdWO2BLocXZeCNVfNlfUUo/3vb2kHyAJbBfrVg3qK7F4tL7P3uXxx/+7/rL+Rn1vhfGJbAA9tfffcbfjcCi2dObrhtksR/zOf+x7zuejzAC62awyJMcEkqzVfwLklJ50ZNxLAdu/R7d/iHfjzNjNMB6nAYKNP9z91f07uk8LWQA67jGuSd3lwMgii9mvI8XkO/2nbzg8Ve/+pUWKgiCIBgRxZcxxFZDaw0yHcoN7T3d7CvyaHWlEqZK2IWOLd+RRuA3+Ja5C5TQlsrCka2JKqQPM3JYIQLhAr4gjUD55SolHF6cOp1dJNjqnCMNWB55Mmc3vZR3yByo4HNnzKH1KRmUoQQPe+c2q3Nz1HUhiOwuKx6k6AGcnfxyNt5IFF9KVGc/t6qMtaWtB1Vg7hH+N99Vgv7HZ05afDAbweTjJakz6IoZs2lWRIzNgQrkRXtPF+XVVNFHBSfp25JCNrFrBB0NrM6xN0iCe4HGMxSjkJ9YiQScmRjUweTmo8suoIWxiUP8tRo1yZ0VFMe7HLjyrJMRvw+3k6molCcP09OHtwIiTHz279/Pk4vztqzRQgYDVyFH3v6eXYNcfPHFPDg2bdrAb0kUXzwTrNJBvbkmOY2ts8Fkub0BdwyOYJAA7o2sVxm5qw4G8PMPhRwov1i3Y1jxBUtkX587w4M7rg4UjaXiC64D5Z+75i/hVbLWeYBB/cNKvoI5+duzFk7Z9uN8obdbt912G61evZqMCiLGzTrM+N24P9x34751mP45kmPWii/6p74ZvzujJINtuOP6Zh0P6eth+qdR2UcPA8ZwYxgwhltvwx231zYZFTEvuOACuueeeygjw9znQ1uENml2Wgj97peTT/ElOPUqCkrZSF6suGKmq+EkNRx7TPtmH/+YxRQ2Yyt5+RhdTqg+Ytm31Hz2De372ALlGy8ff+ppHmxtVBg9P//tUTpR2MKyO2R4YXxBfQVrO7enRWghZg7Ud9BfC+spv6XLbn2FMSuMXQnnB1tyoC0gp3Ypea+irYXHW+Ba9HB1OcuujoDlwMvSZ9KWWfNoppKj7SmkQxav7WijD/NP8ASkji2Z95i6fn1nG692t05Pl6ffPHWEPj1zaog8Drke7jnXT5tOwX5+g/oGOPdUfQ1tLy6gm2YvcCiLA4xRwd0pJhNhydg4XohWHgo6X6m0Arx9afN0KG2asSeTTyTqtn9PFS+b5fuItSsp4fYb2NKLTk9jE1W9+SE17c9l5Ref8FC2+tJy/BS7NQLxN11DLUePU9upMxCIyC8hjqKvuJgiVi/n46A9/yyV/PGv1F3fwBZl0v/hEe3I6BDFF8/npz/9KVsG67p+E/UlTnzFF/BPqq69afb8QfUZ6oqipgZ6+9RR+vZcoaq/zBaqjGTHJtDCuERq6+mmt04e5bAnNl7D9Zhe62As++OCk/TPO74YpDiCMel/XLWBrld1sN6HRz9je/EZ+umXH/B3W+3A+VB8gTuo//btZ7TbsEAZruL+Sd3/paodMbqygysiKGygPoXLoQcXrxrk8gh1+a++/nRIfmJc5x9XracI/wFFXVjg/en2D9k6GPIL7QrGhowkBIfy+NJPFq/mul8HCiP/oK4DiynOjvFbj9PgfT15aDf9KXefFjKAdVxrRRR3lgMgii9mRPFFEARheMZd8QWD3pWVldR92YXUO2tyT9oujkui+bHxNs2u6iDTe/vM/h1h6SW/odamYoU90DHOio7nhj8lLJxNmeJ6cKkEBQlYAylWQhK0eyF4QVPXGnT2FypBNTUskt0YpISEsdBhTOOMEgIPqvMhDBrBuXDNA1N0mVHR6jOMtZzxXDBhh+sWqGc6UVfNSj222JQ+ixJDBkyw4rqIm1NVpoWYcTYeJhEzVb7oWMezJwz/6utPWFCE0K5rSeOd4NmP1VTy4ImtiUIdaFvjnaeGRfB7gclcuIgCtR3tVN7SxIJqQWMdHaosZwHYmnUp6ZQWHsnnxyohXD8fLhtKWpCXdbw6CApMRsUovP9VSalKqBsQtMtVvG2Fp7Vvg4Ggvzg+ibXIYXYQJRT3iGf9TJ0DN1u2yi9MBe+0cr0FxrMcuPqskw3fD7eTd1EprVy5kn7wgx9oocJkBQP1L7zwgl3Fl9r8Mjry1ndUfaqEV6liYAxWFYz8z//5P+nLL78UxRcPBHXnPNWGo+5D24G2J06F6bUu6uX6jjZVN9ez1THU0dZ1InBHHayDdhBtA9IztoUFqv4/qNoGpIN2NthnYPAYbaNxBZAz7Ye763wMaqxOmkbz1H3DnLxuahgWatD2HlTpzlPP9ZOlawYNOsG9H1ZBCWOH3m798pe/pCuvvFILnbygS6Vv+nf903rTsRVu7zuwpfhi3PQw/dPVY9b71t/37dtns20yKmKuWLGCfvSjH9GsWbO0owMTyZlpwfT7Xy7QQicPo1F88Q2fSWGz7iJv/4HB3P6+Lmo99ym1lWzTQtyLl3cg+YZMI++gRPL2DVOfCdTb1UgtZ17XYgju4p//eIL25TXwIiAoAArjhy5LWyu+HG7soBfONtCJ5k6H9ZUovpxfbMmBtuhRbVN3by9b1j3TWMcys7NgHAeLyuD6Z050rEWOBphcxMQhZPFq9QlXR0ZlGlsyL+TUqvZWHmODXAp5GkAmhZuhYyoNLHazNTYH5kTFslVITCSnhZrdZde2w91RFS+Qw5jQmhTHsrgOJkOXJSTzfcCiA8aXMLZU2FRPuVUVdEjJxz9begFdYnCrgeO/P7CDXZ1PVMqe+xs17NjD+9P/+y8oIH1gYpZR5aWjtJya9h6ihu92U09TM3n5mCdI+3vM43TeIcHsJgkEz5lJEetWU9jSbLYYo9PX1sHukdoKzpJ3aDDN/t1vtCOjQxRfPB+L4ssNl1NfQqwWOrGZq/rKGCvHmLj1wlrUrbnVFaourOU6olPVtyG+ZstWc1W9manqLSy4vW/bOxwfVtEfXrJykHV51KV/O36YlRKbu7rYrfNiVc/dMjd7kFu2JlXv/m7/DnrtxGH+7imKL1A+xAIiWGuBMhDuH5Z8Yf0di5F1ML/zoqo//0s9A8DYyv/bsJnrYB3kIay4f150WrUNzZzfaO9uzJzPdb+e/1AUgYulX3/3Oc8hYCHrxvRZrDBzWNXhaO908P5wHbg+0sG8waNffshtl7PKIL+7+Cp1jZnaN3P/b69qs54+tJefDUo5WAwFhlN8cWc5AKL4Ysb7eD75bt9Fmzdvpr//+7/XQgVBEAQjvqqPFxQUJIovEx2424ECQ0xgMAtIWJFSowTTWtXhxqczQCBAZz8uOJj3XU0D52LyDUImClO96pxXtjU7ff3xwpEwjOeG/2YIwDBDWK/uHYKiI4UXW0BYQ17oJvqwmqa6rZWViJwBeQm3Sfr56FRAuxwCsS2FmZGAAZ60sEjWUIdIjXvEYMxo39dEKQcTFb+PviJTYQm7s/nHf/xHLVSYrGCg3p7iS31hJR1561uqzCumtWvXsmn26dOna0cHEMWXiUGMqovjg0IpEtrIWhjqZXPd7Hzd74462F1t4fkAbRsUeKE8CjBJUaLuHQNV/+vCy2hTRqZlIAlhcPv0n/u/5+/C2KC3W7/4xS/oqquu0kKFiYyttsmoiLl48WKeRM7KyuJjOmiL0CZlpoXQ78XiyyBg6SUocT35xywlk9rv7++h7sYCaiv9nHrahio8ugPf8FkUnLKJfIKS+Jpk8nX6fgXX0BVfpooCoCeh11dGxZfjTZ30fGEDHW3sGLa+wpgVxq6EqYFRjgaYVMOE70jGYYzyNNBlUnsKL9bAIiSUxJEOZHCs+h+pLI5+BpTCMb6EsSUsyoL701mRMfTbizbT9IiBhWN43n/67jP6rqRQC5l4lL/4JjV8u4u8Q0No1v/5NXmp/sEQ+vupp6WVlV+acw5TZ3kl9bV3Un9XF5G3iUz+/uQTHsaWXMJXLKLA6WlD0+nrp7IXXqPGnfvIOzyUMv/jX7QDo0MUXzwfXfGl8/pN1D9JLL4AKMH9fNlauy6E0X+GpY4uVR8G+fiqn8qAW36jJVXUX3DdtjY5fZA11oaOdl4MinoQlktmRkZRVMCAtUOk/23JWfpfu762jJ97iuILQDtQ1NjA94b7x6JVjN3rYPzlRG0V/TdVh2LxDUAa9y9cTj+Yt3iQOyQovxQ11fNCJYxPQEkyJTRM5ac5v5BWocqrf9v5Fe3RrMzgGf9/K9dzW4D0ocSIuRuTeltwWbc6KZXHQwDCoajzy68/YSv+ziqD/N3yC+kOda/G94b3BeUZPD/e/0Ofv8fhwym+uLMcAFF8MSOKL4IgCMOjK74MtD5jjO7T0I6ejTBCIPScVEIP/Bejg4pPaFu7MtEFAQbawhBWR5IGOs5YgYJzv1fbsdrKCafsgDzAKhw8u/kZqkY0uADB7HB1BecFNuw7q/QCkJfG8/cqIRca5a4OtjgCAuZx9Xx4Tv0e3fG+JkM5mAhIHTq1aSyppqPv7mClF6wcvvPOO20qvQgTB9STqC/1Olmvl12t+91RB7urLRwvMDA3O8rsOgJtG6zL4N6xYR9hl6XPYh/YutILwCoi3WWgIAgjp66wgo69t4OVXubPn8+TNNaTyIMQEWYI/T1t1F65k1qLP6CWoveotej9MVV6Ad7+keQbmkEmv3BWehHGDhkD8RxON3fSS0VmpRen6ithSmGUo7Fhf6TjMEZ52iiTOguuq4/NHVF9AldlcVhv1C0goi+gjy9hbAnPiQVQN8+ez5aKjUA5B+NEE5nwVUso7uZrKO6Gq2wrvQBVL/uEhlDEhSspdsvlFK/ixt10NZ8HN0dxN6r9666gmCsvpaDZM22nY/KiiLUrzNe6TpQapxJ6e66375MFuDP646E9XAdA+cAaKC9AsQKLb2GNymjtygjqL7hMQ71jTCciIJAtbF2Ykk4rElOGKDvA+utfjhxwafx8vMCCJC/1D9Zl9fu3VnqpUPf9xskjFqUXgLbg3fw8tjQLRQ0duJaeHRXLaV2gub82Kr3Aau8rebncDhnBO0BcWGX54YKldI/a8AmlJV3pBedj4dIHBSdY6cUV4Baput1s7UoH6cJ6GBRrdCtmzjAZy4FHMEnrH0EQhLHA3LKOA5NVOBQEQRgXtLpTBs6nLk3ldXT0nR1UceQsr1KF0svMmQOmSK2RsiJMdjBY8tDiVXTfwhU8AJQZGcMDcRjQx4quu+cvoXuyl7FlPB2sgMqrqWQXSMIYI+3WpKaxpIby3t/FipizZ8+mH/7wh5Sdna0dtY2UBdv0dTVSZ20udVTtoY7q/WOq9CKMLzL04RkUtnbTK8WNdKihw+n6SsathIkKLANg1TtW7q9MmsZuVQE+IS/fr+RmKIbDzYQOLBDANelEX7gUNGs6RW9cTxEXLNdC7GPy8+X44WuWU9RFF1D0ZRso6tJ1FLluFYUuWUC+UQMu0mzhyrWEyYNFlp1kbQSUNLadPU1/OLiL3jp11Kz41+tY8a+3r4/rjPyGATdwAAobTx3aTZ+cPcmuk9H/tgXc+cD6+Jvqek/l7Bmi6OEplDQ30e7yc+zuxxooa0BZ6Mmc3Zx/1uDcvx47SK8ez6XTdTWDlECMIIegqAJrJ787sIM+PnNykOIl6mhsek76eJnYqoluTQXhbT3ddKCiVOX9Hvr23FkOd4WcqnJ2nQflF1tvzN57tMdkKweeABSwBEEQBMfo/Xjvf1HwnhU9qkHtHUbIcYW33nqLWltbqW9GGvVHO+5ACMJYAI3qddMyeFJMp76jnQVQQfB0TKfPkqmhia17rFu3TgsVJiu5ubm8xc6eRnFzplFrdSMdfft7Kj2YT3PnzqV777132FWq3377LZ09e5b6kuPVlqCFCsLk4eLUGXRt5jz2hw3LL1kx8TQ/NkG19em0MW0mXaI2rEzShV4MtWAQ74+5eyf8itaJgN5uwToVJhqFiY+xbSo7lE9lOfk0PWM6t0nLli3TYg2lsLCQ26TIMF+64oJ4LXTy4BeeSb5hM1RdYx58Br0dtdRRvUf75piAuFUqjdnkGzqdN5/gZOrvbqb+XvNKTVhnCYhZrD5nWOKY/CKot72CfNW1A2KXkX/UAvKLmMsbH/cJoL7OOlXxDQyw+0cvJv/IeZyer7oGeQ30ifr7esjL5KulD7fEXtTX1WA+qOHlHajSyKaA6EXqevMHrod7D5mmfvTe5mtaMXBd873r6XuZfNS9L1fHF6rjWWyJpqe1xHzSJOGbg7VUUtVBq1atknpwnNHrqwXhAbS7tl1tbZSh+lHO1ld9URE8diUIE4275y+li1KnU1Z0HGUq+XiBko2z4xLoUiUXQ/EFK/fDNNfaABOxu8qK6YWjB6m+s10LFc4HptJKMpVV0qJFi3gTPI8PP/yQampqqHdeJvUHD1irmAxAMQF9ZVisOttYR7lV5VTe0kx1He3U0tXFbvyhwHCspopyKsvow4IT9M25s2zZqsbKUgisS51tbGBXQlCMwbkt3V1U195OpS2NfP6XxQX06ZlT9InajtdVa2cO0AOXYi1NtKfsHO0sLeYN1rBOWMV1Nh6eD0od+8tL7cbD4pkl8UkWCyzgjHoGKHDACgnyAQomla0tdKiqjD4rOq3y4SR9WVTA4bZA/iEfChvr2eosXByZXVt3WvIT1nah7PLp2dPqvoqow0rJBm6G8IxnVRoV6pyW7k7OS+P5UDD5rPA0fXeucNC9dKs6Hs+AZ9WfW7cAZgSKPcVNjRwO13edPT1U39HB7wsKNVDsgdsjc9xetkimp4c25GBlOc+xGHFHOQBQ+oFCzHDXc/ZZJyqm6jp2JT1r1ixas2awS3xBEATBjLe3N7s78uq3s/SuQzVunaoRdhe33norVVVVsZ9k+EsWhPHGWb+fguCJ+H7yNXmfOUcXX3wx/frXv9ZChcnKCy+8wFvWNatp+rpstvRStPMYpaen04MPPuhwwF7n3/7t3+irr76inuXZ1LNioRYqCJMHez64bYGBLvjCfv7oQXr/9PFBK6iEsUFvtx599FG65pprtFBhIqO3TYnZ06nqeDElJybxJPLatWu1GLbZvn07/eY3v6EZKcH0+K8WaKGTh+DUqygoZSN5efloIURdDSep4dhj2jfHRC74BXkHDigEwQJMy5nXqKupgL8HJW+koKQNRIb0u5tOU1f9MQqIXUk+ISnk5Y1JTE3Jr7eLetorqKNyF7VXfMthIHz2veQbPosVdLx8YKJ9YNVgf1+3Ok/r+/f3UFvZ1+xySccnNI0CopeQHyuoRKvroT+lnd/fR3097dTbVkod1XvVto8VaXT061pQ6bdX7FTphKn0FpDJN0Ql5a3y7LjKs8e1SJOD//Gnk7T7SD39/Oc/p6uvvloLFcYDvb5aHhVIuQ0dlJAyzaX6CmNWGLsShInGs5ffQKuSpmnfHIOJzn0VpfT0IVll7wn47M0ln32H2RUbNsHzeOihh+jEiRPUeeNm6o83u9ydzCQGh1JsUDCFa8pymECqb2+npq4Op5UJ4C4nMThMpRPE/Xb0w6vb2qi8tcklN3Djga3xBShR/OjTt/g50sIi2bosptKq21rYRZyrzzAtNJzzFHMTen5WtjU7ZXELrqZi1Lkx6h5wj66e7yx479PCIsjf2/y+qlpb+X2PZgxlIpUDT8U77zT5frWbrrzySvrlL3+phQqCIAhG/Pz8KDAwcPxcHQmCIAgjR0waTl1OfLKXivcep8TERLrnnnucUnoRhKkAVvg0d3U6NLuLVawVrS28guixA7voUyuzwcLYIe3W5KXmdCnFRsfQ1q1bnVptZrG6ZP+nOqXx8gli5Y+BLRiB2lG16+1PXoOOh5B3YBwFpVxGvuEz2RILfnE6UErxDUmloKSL2BKNjn4dfBrjA1h70dPGtXBNHViICU7eRIEJ68gnKEk7Zjjfy6TOC2bllqCUTeQfvVQ7YMb6+ZA+rL74xywjk1+4iqBPLky+oQk9l8TN1/kjr6mTouLiXa6vBGGigpX6RpcY1iAcx0/W1dCrxw/T04f2itKLIDjJZHV1ZA9YOTlcXUHflRTyBssix2orXbKgAaWGgoZaViBBGvjE94mm7ID7hdVY5AGs3JyqH9kzIO9Q5xrz01mllYbODrbIo+elq+c7C947LKXo7+tMY92ox1AmSzk4r1iqH5FVBUEQhmPcRpemmnAoeB7FTQ30WWE+fXLmpGUbid9LQTgvSN05JWk4V0WFO45SeEgY/ehHP6ILLrhAOzI8MskiTHYwWPL7Azvp6dy99FHBCTZvnFdTRUeqK+mLonx65/Qx+s9937Gf7GdUnM8LT1OrDKyMH9JuTVrCg0PZmueGDRvIpPmWdwZpl9yHt38MeQfEUF93K/W0lanPFhU6OH+9A6LJP2aJ9g3538uWWPp54Hpw3P7+Pu2YeSMVF5h8wygwcQO7KjJbeTHH7WktpfaK76izJoct1JjT8+J7gnUa3xD7Fl5hccYnJFWlN+BqY7IiA9Pnn8CIqBHVV4IwUXn79FH67f7v6eW8Q+yaAu44IB8frCzlMTCE4/gfDu6k548e4HBBEJxDl2WleRcEQRAEQfBcxr/nL8KhcJ44XV9Dzx3ZT388tNeyvXbisHZUEDybfm2CQiaNphY1p0rJz+TLptkvuugiLdQ5pKwIkx34iX7z5FH6C9r23L30RM5uHsT/w8Fd9FTOHl7B+tdjOfRB/nGOK4wv0m5NPmBx7P7776cbbriBLr30UjYh6gwDFl+kLLgLL5Mf9bSUUGvRe2r7kD97WkvUEUMee3mTb/CAu4uOyh0q3jvUWXvArNxioLe9mo+Zt/fZ7RDwj15A/pFziUyaBRr1Dnuaz1Br8QfUeu5Tai35hNord1J/b4f5uOrswyqMf8wi7bstYCEmhPp6WqmzLpdaCt/hNHpaz2nHJw8mkwx+nC9GW1+hrAvCRASK4VBu+VPuPnrq0B56/KBZPsYnxsAQjuNfFZ+h6rZW7SxBEJzBIsuK5osgCOOOuf4RxXpBEIThkSUvwpQBq7zPNNTx5Je+uWKeURDOLyLYTjV8fH2op72LfvzjH9PmzZu1UEEQrNHb9wOVpfRtCUwPF9KJumpp48870m5NNubNm0e33HILt0lBQXCX4xwWxRcpE26jr7eNlUWwQXkEnx01OdTfN9iqFVwJwQoL6Kw9RG1lX5uVWjSLLjp9XQ18DFt7+TfU3VzI4f5R2eTlE8z7ANftqNqtrnmEz4Hllw517d4Og3KhyYd8HFh8AVCUQTqtxR9TW+kX1FayjTqq92hHJw8DOhSiRDHejLa+MuqQCcJEpKa9lRd/7SorZvl4T/k5HgNDuCAII0Nvz6VZFwRBEARB8FzGXfFFhENBEIQRoE8aSSU6JVi6dCndd999vG3ZskULFQRBmEBIuzVpCQsL0/ZcQ8qC++jtqKPOusGWK2ExZcDyihkvkw95+0dp31zDOzCOvAPitW9m+nvaycs7kAJillo239AMdaBPi2HG2z+CXS3Zo6e9gtrLv9Ws1OB5atR+Ge9PKqTMn3dGWl8JgiAIgjUWWVZXkhQEQRgvLNWP1D+CIAjDIa6OBEEQJgJa3SmTRlOD+fPn04033Eg333yzFiIIgjDBkHZLsEJKgvvo72mjvq7BVq16Wsupv7dT+2ZkZB1wuCwy+Q62lGHyCaKA+DUUNG3zoM1aycXL5Eve/rYVX/r7+1jhBcoukx2LtSOpByccMqcgCIIgWDOg+GL+ECYXsBr76dnT9MnZU5YN1rIEwSPQ6h9RfBEEQRiecVN8kcEeQRCEkSOCreAq0u4KgnA+kXZL0JHJ//Ghr6ue+vt6tG+jx8vbD3+0b2a8fILIJyhxyGZ0hzSAvTqgT91rs7Y/ufEySdmfaEjbJQiCINhDb8+9RPNlUrKvvIT+lLuX/nhoj2X7oOC4dlQQzi/SpxYEQRgevY48DxZfRDgUhMnC9IgoyoqOozlRsRTi56eFup/xuo4no1faIuAKzjLRykpqaAT/zrElBIdooZMHqceEqYa0W4I1Vt5whAlIX3cL9bScG35rLaO+3nbtrKmLjHxMYKTpEgRBEKyw9G+kgZ+UNHR2UEFDHeXX11q28papoawtTBxESVsQBME+eh05/oovwpgxPyae7l+4gn62dA1dPWMO+XkPXqEnCO7m9qxF9JMlq+n+RStoblScFup+xus6Ho1odgsTjOjAIJqjKbLo26zIaLtt07Wzsvh3ju3itJlaqOtsTJ/J7eBDi1fR8oQULfT8M9b1mFFxSN+gbCOcfzy1TI45MiAjaMjg3ATAxjvq7+kYYkEGii+tJZ9SS/GHDre20i+mhCuj4REFwImGpb6SdzYpcbV/IriHjPBI+uGCpfTosgvo5tkL+D0IgiAIgiAIgiCMBd7/otD2B9HT00O9vb3at9Hz+uuvU3t7O/XNyqD+yHAt9PyyJjmVrs+cRxckp9HqpNRB2yq1rUhIoSXxSTQzMoYCfXypqauDutyYJ+7mR9nL6PasxbQsMYUnwI7WVFJVW4t2VBhPrMvWwrhEqm1vY+1xV7li+my6asZcWqOVzeTQMMqrrdKOnl/+bvmFtFj9RhKCQymnqoxO1o3NAPd4XceT8T57jky19ZSenk4bNmzQQgXBPl999RUVFxdTX3K82hK00LElMSSU1qVk0CVpM3myf0PqdFqZOI1WaBsm/edGx9E8tXl7maispUk7k+i+hSvogpQ0SguPpOq2Vvqq+Ix2xHmSQ8Lo58vW0mZVby5S9W6wry99VpivHT2/jEU9hsH6S1Q+X6TyeVPGLJV/6Za8xrY0IZmVbObHxlNUQBCVtDRSr0zkjCueXCbHGr3dWrFiBc2dO1cLFaYiaIu+/vprCg32oS3rx6c9Gk/8wjPJN2wGeal2Tae3o5Y6qvdo3xwTmLiOTL6h2jei/t4O6qzNpd7OWv7uSvrDpQV8gpPJP3I+eZl8tBDEa1PxDlF/X5cWoujrpoCYxSo9gxW2/j7qrDtMXfVH1T1U2dyQVk9bOZ8PAuJWkndADO+b6aPupjPU3XhK+z552Xm4ngrL2qQenEDo9RXGrHpnpWuh549poRF069xsWj8tY9B4lb3Nk8YKPIXR9E8E93Bd5jy6N3s5l1EoGhU3NVJ+w0C7JJgxlVaSqaySFi1axJvgebz77rvU2Kj61NlzlNAVoIUKgiCMPV6VNeRdVMp9ipUrV2qhgiAIghFvb2/y9fUdP4svllVOHrTgb2l8Mq86gMKI9Xav5XM53b9wOT28eBVvmLjwVBcFicFhFKheqo/qrMNNRHzQ5HMVYQSrRDKjjIOonsOQsrVgGQ9WuQoGaW7PWmgpj9g2Z8zWjgpTCrH4IrjIeJeVDdOm0wMLV9KDi1bSj1VddUPmfBWWwXWfvl2SNoPumr+E29aR1InDEeYfwO2fj8lEAT4+lBLmGYq27gZtw81zFtDDS1axjPIjlZ+QT4x5je2y9FncfvxYHb9j3mKaFjo58+N8kx4WSSl28naqlEmbiJUPQWPAHzl/TAm8/aMpOPVKu1tg4not5vjT39s5xJKLt38U+ccuJ5+QaeQXOZc/ezvrqKelRJ0w4KMKSjBBSZeQf8ySQQo22PeLmE1ByZdQQNwqLVQQa0cTD0t95SG+jpKUzAfFF8u4wjCbjBUMxhP6J1MBjJHOiY7Vvg0lISiEQv38yaR+XzGBwbwQQBAmIgNjLNK+C4Iw3pjrH+lfCIIgDI+4OtKAJZeattZBW2t3F09UxKpO2vLEFLpt7kJ6YNEK+uH8pTQjIlo703P4vOg0Ha2poLON9Wo/n07UVWtHJhdYMY2JvJ8uWUNbZmZpoZ4NFJIuSE6nyIBALcQ51qpzpoeLqwpBIQovgocC0+BwU/TAopV0zcy57F7Hz9uH6jra6URtNX197ix9evYUHawso6KmBmrv6aZgPz9WCHA3WKEJaxpnGuoor6aKPi44qR2ZPMyNjmVlSljIWT9tOssoPX29/Mx7ys9xXn9WeJoOVZWr/Ghm+SbYz5+mhYXzQLPgPmBlB+6LsGHlsC2mQpm0i7RbgsaA4svUKRPeAVEUnHKZ3S0wfo0Wc/zpaaug/p427ZsZL58gCkpcT8GpV1FQyuXkFzaLw9urdlFfVyPvM14mdSyDgqdtppC0aygk/VrzpvaDp12pzt1EfhFi2UTHJOPSEw7LZIIHVld9qg6t62gbMm5l3Bo627XYUxtP6p9MZmZHxdCd8xbTz5asoa1z7Vso+bakkPaVl9C55gaV92e4zyIIExFdlpWJZ0EQBEEQBM9l/C2+eKhWNDrAvzuw02rbQb/d/z19kH+cSpobeXXCzIho7tDdt3A5LYxN1M72DLYXnaHHD+6mPxzcSS8cPcj3PBlZnzqdV+PcMHs+zYmyv6rEU+ju7eVSj0GBZQnJ5kAngJLMxWkzKMTPn3r6+nigS5jCTMFJI2F0jEdZwaDy9bPm0f2LVrI7HV/1HS723j51jH6v2lC0R0/l7KanDu2hJ3J20R/Qtqp2FQPNJc0NWiruo7Gzg/52IlddV11Lbe+r9nsyAf/4d89fygP4icGh1NXbQ4eqylTeou3fRU9qec35rb4/pt7Bf+3foeSDAqpqbZF2xM3cPDub5ZHLMmbyimxbTPYy6RBptwQrplRJgFsiLx8Hm7cWcfyBm6TuliL12zS68PUi74BYdoHkG5qubjGIQ7saT1N75Q7q64LrD+0Nqvv3CUqigPg1FJS8kTfswx2TyQcKljIZNIDUf4L7gDIzlGmHjlsNbJDBpzqe1j+ZzMBNFCwNYZEgFqjZY295icrv3apvsov+dHgfHRd3XMIERe/XeIpVME8GdTFcm8E9Mz7xfSxgi1NRsXwdKDkKwqRF74qJ4p0gCMKwjJvii6ev9IN1l3dOHxu0vX7iCCuQPJ27lx5TneMvCvOppauLwvz92TfwnfM9y20AnuH7kkLadvY0W32ZrEQHBLGZ1InSzDd2dVJvfx9FBATQRakznBb2oSQDP9NQuIJiVp/BzLgwBRG5VnCR8egMrUlK47YwVbWFaN/z62t5EBkDmm+ePMqrKY/WVHL47rJz9MnZU/RyXi49reJAWXMsKG2GhY3T9G3JWWro7NBCJz5QhoSp+4tSp1Owrx+1qDZ/m8rPJw7uppeOHeJn3l9Rynl9qq6GdpYV0wcFJ+jFvBz6o8rv544coHOTVCH2fBEbFEz+TrTpk7VMDou0W4LGQD+QP4TzTX8PtVd8Rz3NZ4e4PGLwnvSXhbiVO6m19HPqaS1R8bvN4bZQ5/R1N3E8wYynj4EIQxmQnz3vnWFMIbeqfMi4lXHbUVqkxZ66eGL/ZLKC/km4f8Cw/c7uvl7up3x85iRb3BGEiYqlPR+HsZaJDlwB371gKT2yZDV/2nMNPFqg9AJruLjO1rkLtVBhKjI/Jp5+rMrCT1RZuHLGnDFTthIEQRA8n3FTfLEwAWXDwsZ6+qjgJCvAvJufx8ov/t4+tDYlna5SDakgOKKuvY3au7vJ28tES+OTKNtJS0EbUqezsgysvVS2tZAJK0eFqYsMnAsuMtZlJTEklG6es8AygAGlCrST75zKG9bi2On6WspvqNW+Cc5woZI5Lk/PZKWXzt4e+qroDD17+ADtKivmwWRH5NVWseJFRWuzFiII44C0W4KGXgYma1noajhBrUUfUEvRe05vbWXbtbOJ943HWku2UW/HwMSgrfShjGKL4dLS6W4qoNZzn1BbyWfUWXeEelqK1XZOXes4K8V0NZ7QYhK7Ouqo3EGtxR+p+3if2qt2q+OnOD6fo/Y7qveq9D5S1/xA7e/RzjSDex10TyoOnmkqIPNiEw+9nhoPBXLB/Uj/RBCEscRdsuzG9Fn082UXWLa75y9x2TW+Duo8Y1pI2xOIDQym1UmptH5aBn/i+1iQFBJGa1PS+Dor7LgfFmyzJjmVfrp0zaDyY9ygQAKXgbfOyWYLX7Cu48lcPXMO3Ze9nO5duJzumb+UZk8ALwGuIJKpIAiC83gpoc2m1NbR0UGdnZ3at9Fzww03UH19PXVdeRH1padooecXNOAwy+lr8qaChjq65u2/akfsAwsv/7TqIrpACVWwxHGyroZ+9fUndjvIc6PjaHFcIkUHBpGPyay40NvXz76Xj9VU0YHKUg6zBTrrsPoBdwYBPj5aKFzn9PH5udUVdERtOgtjE2heTAJ5q/sqb22mL4rytSODgaACoTMjPIqCfH0tDWdbdzedqKvmSbRNGbMowi+QJ9P2lJfQ2cY6LZYZCBM43quKz7GaCipQx9cmp9N0laa/j1mjFkWrtqOdcirLeEXNaMC9rkxM4Xd1afpMi8ugfPXe3jxxhPfBafUedqv7NwIN38VxSepdxLKlGP09gI6eHs4rrD5xp2soY9lC2kE+vpQVE6fys49eO3GY/n3311pM2yyIjaf/s34zpYVFUHlLEx2rraJL02byMaxK+tGnb/G+LWARZ7nKK5wbqMqNcaVhc3cXnVF5tq+ihBW4HOFMOXlzy+00IyKKrQ39ZtdXg1w4GN9ZQ1c7fZBvf4Abz4ZyrpcnlG0j719/p93rGMEzL1PCeEJwiEWzG8/dpJ71pLpnPDdMRE9EfL7aRT55+bRmzRr6zW9+o4UKgn3+6Z/+iXbt2kU9y7OpZ4X7V77ckDmffrl8La/yQ136Ut4hevzgrmGVMOzx7OU30Kok80DFW6eOqd/6dq6D0FnV6yAILM1dnXS4qoJ/z7YYrj4BrravRkbarjtbj9kCg2D/68JNPKCDOv2YalP/ZceXbjUTbq/Ox7stVu3jQfVc5S1DFWeMsode12OlzeL4JNUeBVraoM6eXjqjZIXvSwuHbX9GmsfWsglkkLXJaWyZBelUtrbSK8cPabHN7eUSVQ5Sw8Ip2MePvE1ae6k2tHVoN9DWGduNVSqPZkVE8/4Ps5dSfFAIr8D+rqSQdpee43Br2cmZMglGK6+MxbsYDXq79eCDD9JNN92khQpTkZ07d9Kvf/1rionwoxf/dYkWKngCXt7+5B0YT96+YfhGfT0t1NtZx8ou9oBLJJN/BJlMAfy9r6+D4/d2qDqv34YFGSeAK75jp2tpz+Fy6umxbeXyktWq/k2L1L65j/bOHnp/ez7VNw4d+0C9uTgrjpbPT1D7WqAL/O7VM7RtVxU99NBDdOONN2qhgiej11d9GdOo64oNWuj5Y2XiNPr39ZtY3hiJDGlLNliXkk5zlKwFea9Hyb57lUy9t/zcoP57W083ywnJIeHswiZMm+w6XF1J24sLeF/HKFf7Y/xBC4fs1tTVoeTVasqpKrPbD3dVfnOEu/snRhaqfIBcFekfSL7eAzIanqumvY0OwPKinXFBV/N2JHkymrFHHbh2X6reZYxKw7hSHouxYIUY/QF8YuwPY1yrkqexcj4WeWGx1l8OH9DOoEFjkq6MDbm7PI31WKU78dmbSz77DtNdd93Fm+B53H777VReXk6dd1xH/WEhWqjr/Ovajaq+mqd9I6pVdci/7dpOnxfaHse3xxzVb/zthispLTxCCzGPpfzz959r384fxvYL9cM/frNN9ZHN/WV3AjfQv159ES8QcnZuZzzBmEN0UBBb5fU0jHMXtkDdj61R1b3FjQ2UV1fFY3FjPY4wUh675Gq6OG0GtxsNqo7//3Z8aXdubCLic/gE+Xy3j66//np65JFHtFBBEATBiJ/qWwUGBpL3vyi0sEH0qE5irxsniF9//XVWpunNzKD+CAysnX8ghC2JT+JOWr1qEF89nqsdsU9TVyf5qE4uJtcxWQbBCv6Cc6rKtRhm0Em8JG0m/WDeIrpixmy6QHVScc6S+GSegECHGb4nMchX2FTPnTIjmFjZmrWQrp6RReumpbPWMs7FtkidD8WI1u5uHqDQgfWZuxcs4biYwILLI2vSwyPppjnZdPPsBex2Z2XSNFqqpZsdl0AzIs2TOdfNmkeXpM/k+zxVX8PCo5H/vvpiPr4oPpHzZFFckuaCYYa6vvk5kbfz1PlQFoJp/9G4WFiZlEIPLV6lOtapg5Qa0NnOVp17dM6xofNrNO+L54V/5xvmzKfL0mfx+fp7wIbBizlRcZQcGkod6lx3uYEwlq3ipkYeTFqg8gL3jQ0+jh25O/jhgmU8AYnBVriraFYCJfyVgpLmJruDXSg3N8+eT1tmZbE7DJQF5Iv+PrJjE2hWZAxFKsG7tr2dy70tnCknGPxFepiQxUDStyWFrAimY3xnGNSB6WV7/GTparpadVZQntDhw0CGEfiMjrJzHZ016jd2e9YiTudC9ZuBNrr+3AvUfc7UfMqWqfxr73Fgpt1D8S4sJVN1HU2bNo0uvvhiLVQQ7LN9+3YqKSmhvuR4tSVooe7jXtVBRr2Eegru9eAvH4O+I2XLzCzL6kz8xuOCQuj2eYtZacBYB6EuRR2FOrvAxuDycPXJSNpXMNp23Zl6zB5oU7CSi629KPnsndN59MmZk9rR0TMjIppuUvW9rTrf3E7G8kB7TXvrkHdslD1Q1zeqtu0O9d5gWhZ5pLdBSGdWVAwFqna7sKHeZj082jw2yiZQkIKS8k2qTbwgOZ3TiVfyA5RPAdJEOcBA2UXTMtQzQz4w3ys2tG96Wwc5SL8W2pnb1Hl4LkyqoJ3HbwCTDLhHhFvLTsOVSeAOecWd78Id6O3W8uXLad68gYFdYeqBtghtUlCAN11/kXOWD4Vxor9XU1qp4q2vq0EFOV780t/TRn2ddQPnqP3+nlZ1ZORuWTu7++i/nj9Arxcn0o7WVNrTEDNo26u2qlMnaVlmBAUH+WpnjR60Jy+8c4yePRpOXzUOve6hKl8qyc2ly9emk4/PwES3s+w+Wk8FJa20bNkyqQcnCHp9hTErjF2dbyAbY+FPiJIBRyJDWssGUJ65N3sFwXU35D307StaW1ih3Nh/h2wIJYNb5mTTFdNns/wMGaKlp4u+OXdWS92s3AsZ9aoZ5j44jz9osgvkIvTDIU/h/jFuZmuizBX5bTjc3T8BmLTcouS4W+YspMszZtFqJVMNjDUouUrd97zoeJoWHkEQFyGjWcuoruatK3kyWvkZII3L1b1gTO/K6UpuVNczPiPG+5AO3h/G/+BSZJ2Sn5NV+QxQ8iQmGZEG3jfkTWzGMUlnx4bcXZ7GY6zSnZhKK8lUVkmLFi3iTfA83nrrLWppaaHehXOJ/Edu/QLlUR/jBVDK6lJ1/PaiwYqFw7FV9U1hjd64YALKYV8Vn3+3bcb2C23Pl+rZSluatKPuAwulUB+hDnJ2bmc8gGIj+uFob1EH7ywdvEjXEzDOXWA+BfmHBUD6hvYCc19YlJMcGqbqzTgeRwjzC3A4p3C+8FFlICE4lK3uQzkHimRoByYLpsoaMhWX0dy5c2nFihVaqCAIgmDEW7UFvr6+58HV0SQAwgqscAAIAEZhVeey9Ey6f9EK2jBtOk90YbUDOrEQ9IpVZxNCAwYa7l+4khUUjKBD+aMFy3iQYlpYOHd0vy8tok/PnuKJuEqVFoQMTEIZwYodXAsbjlsDs693zVtCt89dyIIhhMJS1cFD2tgwGTNXhf9wwVK2nIF0oNQAt07WYLJHvxasi9w+dxFF+QfSidoqfk64h4KAhOPosGKiCNcfKeibo6Pe19fHnzp9pIXpm+EYJpFg2g7Ps0x1bjFhWNHSzHmIezxdX8PxsdIbeX3/whU8SDAWwFWWLuCnhkaocmF/EA33jQ453g8ENOPAkiNw73iGG2cvYCUP5ARWHOF8PDOuj0EJdPBRBn6o8gbXsgYDO/CLOmw5UeejHNgD5QblB2XAUTyA8qqXJ5RjV9GfffP0TF4ZBM1u3Ctce2DyEc+ATsc9qixgBdCERF/qJAgeQHJIGCvRwfIZrF1gpZy1guRowCAkfq+wkALLFF8Xn+E6u6u3h9tPDIKifscKJ2sc1ScjbV/BaNr10QJFhXDVxgKs2nTnQBbaAdTnep2PdhHWbpAnmATBalnEuXZmFt2hZAjrttwoe2CQ4d6FywiWexrVfWJyJreqnBUwUA/DUspWJS+sT7XdBo42j42yCRRX8J6jVJuG62NQxliNQsnl+sx5qhxH8zMe1Z6ZB+Sa0V76sJLV3SpvsEpUxyKLqI0bWqDCsHLUKIuo/xaGa+PcJa+48124BWm3BCuMvwtBMAJ5Iik+hFr7/Khp+e1Uv+KuQVud2j5vSKe/fXKC61t3kV/UQC9830yF8wZfs2nJzdQWM4sam9qpqm7kk+ZQnhSE84lRNoB8C5lvQVwCj6PUtrVSh5Kt9UFBY/8dCr2bp89muQsTqhgDaO3pVnEHCvWmjEx6QMltulyNSbMTtdUsS8GSRm17K8tukG0g40DuwFiDNa7Ib44Yi/4Jj41kLWT59ILkVHZFDVfWeD48JyaYoZQeFxxCG9NmcjzIs9a4mreu5Mlo5WfIhZCJ4c4Cz4Bnaevu4mcbeJdt/OyJKo9RBfep/IXMy/WxXicjXJeF9WMazowNjUV5Go+xSmFqYSnXbmrgkR4sakDxYHFsks3xDXugD4k+ob/6DXer34vgWaxX9e2Ps5fzGD0WsHg6sOb1+wM7rbYd9F/7d7CVLlidRfsKy2AYO8KzoX3yJKA4Bitvjx3cSc8fPegxSo1uQ6t/oNwrCIIg2EaX1cTii6bZis6js1rB0FSGdQlMyKGpaVd59dapo+aDivmx8WwuDqZGsSpnV2kxvXQsh75QDTAsf8B0foTqZGGCPkp1eiNUx8zoeuau+UvoMtXpQwcUgsWzh/fzym6Y2z9cXUF5qsOGVdeYDMR3HePz2LIKgtXct8zN5o5gC2tb59MbJ4+yYLBfXR/ua3xMXiyQYXUGGlJ7q4r0lete6h86sKWtTfTisUP0uUrz+5IiTivQ14c1gmEyD89b1NTA4SMBLoKQF7hPXE+3CoBVPH86vI/NJWI7qDrE6Ogj7+Aj9dpZWdw5Rt5+cuYUvX36GE8Y7io7p/Kxku8JnXfcHyzJRKgO8cGqMpsrR1zB+l08f/QAuy7IjIwhPx+zIhEmWzHZZg2stWxMm8Waynk1lfTckQM8yevI4gsEz0eWruKOvY/Kb+QVyjMm8b4qPsury1FuYFYXE8qh/v48gQYNbmt3IRj0uG3OQs5ne+UEMhbKt6Ny4orWvW7pARN7GNSARRwjjiwl4Hmwmh7Pjlm2IyrP/nLkIH1eeJrdXmGwBHmJ58X7hV9ZTP6NduXXeGNeOV8rFl8EpxlLiy9YeYcVhbAYAWWUj1QbZWyPRoLR4kuIqrcxEP+WqnveU51suJGBW5/O3j7KCI/kdiVc1QkYeIbrFyOO6pORtq+jbdfBaCy+YJUi2g+Adg/3jedzB1DsuDYzi/O8rKVJ1fdH6APVxmBgGBMGyI8MJe/gmZKCw9hMsdEkuLG9Q/uDFV2fFebTm0ou2l50hvMReZ0WFsntcaCvL78/KCYaV5y6M4/RFkDWwao5tJcfnz3J5QDW+XQ5ZHXSNG4/YPoWcSAb4JkhR0DRBArA0aq9wD2jvKA9BR2qHYVCJWSO+bEJ3A7iOXaUFXHemeWREs4jTE4AR2XSnfKKu96Fu9DbLbH4IugWFAL9TXTDxUlaqCAM4O3tRRnTIujLbfupIWERdcdnUr9/8OAtIpHKv/mYNi6JobAQf+3MkdPW0U3/+tRuOpRyPbXNvURdI4S8fPzIr6mEQvI+o+ywFmo9sI1+cXs2zZ8VM6I5rr1H6yn/XKvUgxMIT7b4AmUOKOeGqb48FrpYb4iLhTPGMQajbIAtKjCQ5QG4ydlZWsRyzyElH2EMxdh/x0AX+s1nm+rplbxcJbuepf2VpRy3WMkkcKnzs2UXsNwGTirZ6GUlt2E86GslT0GJGu514EUySckvUAKepmSrirZmVqgw4or85oix6J9gbOSueUspJihY9UN6uE/ytxOHWUbDeA76Dqfra1mZBe6BEA9yGsYkoCyi40reAmfzxB3y84bUGfTw4lWUrt4P5EGUiZfycuirc2cG3qWSRWEZBfe3T12/qq2V3R5hnAVyJSZDq9XzPp6zyzI2t1+loz/PcGNDY1Gexmus0p2IxRfP580336TW1lbqXTRXdeTcYPFF/XZQVwSpOh59MyzMwe/HGTB2vCk9kxXo8JtE/w6IxRfPsPgC61lYgAnx0ZHl9vOJUUbAOM8/7/iCjqu6UN9Q76JtgqVlKA1iMhELbDCnkB4ewe0Txuk8xaoK2kG0O1B6dWRlf6KiW3zJysoSiy+CIAh28PHxGV+LL7qmzWTRSjQ26liZawRugniCSj0zJrb+eGgvd7qP1lSwQABzn388tIcHF5Ab6NxB2NCZGRHDGtsAAuubJ4+yoIEONSb4Piw4QX8+vN8lQRaa4JdnZKoOoj8PmKCz+szhfZwW0saG/adz96n9oSb47YEOLkzkv5J3iCd84GYIz4kJoqfVc+MZAa4Ls6QjBYILhET4KoXAqFPX3s5h+oZOOsiOTaTL0maZ3UL09nBeQUEGz4g8xD1iMOCvqjON+27q7GRBb3FcEq1PGZsBLtxDfad5dQ7cRsD8qzVYabJOXR8dHqwcwmQsTLgOx8b0WXzveAZMBL+s3seL2oAHnlUvN39S7xcDXFhRgLyBKVmsitJBOYHbBwyIOSonz7hYTsaSyzIGnh0TenjPMJ2Le8Xvb7vKd0wSn1K/H5CmntHd1hjGg36t6rSsMBGEYRjLsoKOLg/cKqCYaBzYdQcYvPlYtZuoo78rOas63JVcnz13BL9ls8II2klYcHGFkbavo23XRwsGd3UqW1u4Q28LrLiBxa4fZC22ucGUuhFYkkH7gfYAg1FQeEH7gYF85AkG1l89fpi+PXeWr4n3Dotl+ru3xs/bxO0w6lzkCfIHcgGnod4j0kD+wNQvfP0bcWceeyvZJEDdI5Sa8D7xnl9Xbb3RrDra18dzdnN7BvkB94lnxrVQDjDIjpVzkHNgFQariAGeT5c5kGegX/0rUOfq4ZBX9IH+4RgreWU078JdSLslWCNFQXBEfFQQ3bMphQJ2v0Jeqh9iTWf8HCqdfgX97sWD1NE5dPGAq+w4WErbzwVT+/zL1TcvCmoqId9vn6OFTfvouqVxFNNdQxcujKPN66ZjXmpEyIpMwZ1A/rokbQY9uGiVze3OeUss8ootgv38eIL/yZxdrHABmQWfB7QxFCNQHoHFuD8peQzjCnpcKH6AazW5DSWc++AqHmQMWGmELAU5C3LXUyocyidQ/oVyyJXTZ7ObHls4I785wt39E+uxkf3lpSyfvns6j58Pz4nnRb7g+TFug/zIjIphF0b2GC5vjQyXJ6OVnzH+dMucBVxu8I6O11Vx+Xj9xJFB7xLPjLGkr4oLqLq9lftpuG/Iv5CDAeRihOnb9zaexx5jUZ7Ga6xSmFoM9Gvc074jFViUR78T4xSw4IK6Zzig1IW4PHaszoVVWEEYK6D0gvGJp3P30nv5eaw8CUtecLMFK13C+KBXP9K/EARBGB6T9jnmuFs49FQwgaC7qUEnCyuJc6vLtaMDYDIDqy+QK9DKNna00LnVgWZ0qA0tcnSqsdrHWXBPuvBc39FB7ypBJV91Uq3B5OK2wtOWyZzhwHs9Wl3JmtvWE3HokObXm03LotMJreDxYkNqBsVr5kqxgv2vxw5SUVM9fzdinug7QVjdze/C35+t+YwFmIDKrTJ30mEm9rL0WZaBGZ3VSakEyzAoARAssQp7ONDhWZ08jQdQkDauA4HU1jtEHrxXcJwVcABMyK5JHpgIhfleWFMAjsoJBh8+PXuaLcKcT/Ds66dl8IQhyh9W3O8oKdKODoD7PVxVTr19fSOaLPckZAJRcJaxLCuoo/SWCmaonW0znAX1HwZYsWLHCMLzaqp48BnEu9iujKR9dUe77k6wCswe8MV/b/ZydoVja0N9aQT+prHaEUDpw1ae4zsG4lu7uvidw/qLPUUJKAVjMNm6vUX5gCKlXk6Q78YBvbHI48KmBnrtxBG7yqOY5IGCCgbXbYFypt8vBhSxunQsGCt5ZaTvYiyQdkuwDM7JIJ3gABSPay+ZSauCiinw2KfkZaPuaF90DX14wot25w5tI1yhur6d/vLBafJedT35drdSYM67NKvsS7pypg9t2bSS5q9ZQ8XHDtPWK2ZRgL9tZU9n0Iu81IMTB72+8sR3BsVXtNlQyLW1ZUREcr/YHlhYAwVbo+U5e6DfDAt2WERiPc4DuW1JQhIrqmOyFnKirXgA40ufF+azfIeczYyKHZX85gikr/3k3NI/sR4bgQU9PI81eG48f05lOY/HYDJweUIyj1XYwlHe2sJenrhDfoYSDMZGMF6HPsa7p4/bLR+Qmc80DJVRR8tYlSf8hj1xrFKYHOgKX+6gorWFrayC6aqfbd1nt8Uq9ds1jh3DEr2zwBILLJLCvdnPll5Ajy4zb7AeBQu5K7V6ZTigOAerJkhHTwPp3bNgGbsVHg4syrG3QMcIlNtgfQvx8GlP2c0ZoPwHq1CPqGc1Pvcd8xaz1bDRgjbj1jnZfK+wIKsTExhseVZHz4uFSbdnLWQrXPr9YXtIfb95zgK29n4+gYIlFDZhVR7tHcbUsJDK0X2NJs+NZdWYH8ifH2QtGlL/GxeCQVHYHrDaC2tEcNdk/A3ct3A5//5Q/qHQg3TwPnVZwIh+HNfDdZEmFpw/OOj3sIZ+oJ7TfXMQ5npHFF8EQRCGZ9wUXzx5AGEkoHOkA+sZOjBjB9/JAG5lTF4m2pQxy+YGIQH5Yd3RKm5usKQJQfa+hStoQ+p0bkRHCkz/Bfn48r5untQeWAmhm+cfDphChZBtLz46x/oEZYC32cWPDu4JQgYEFnvbSC1zwKKKr+o4I39hHQAmaO2BAQSYNcUABN4qBCvjIAXuwda96RueAc8yHMgjuAvCZBQGrZbEJfFKbx0IVli9jcEIdPhh3tIZn9QQMOGuAcCsMUzXWk9cGoGbhfIW8+oWvBMMNOhg4GAsyslYYXz2zp5ezreL06bb/L3BjG3PCCfLPQERbAVXGa8yg+ugTnMnhY0N3LbYAn56u3vNv2VnBmSMjKR9dUe77k6wWtceQb6+vCrV3mY9GaK3lbhv1OdZMXE2nwtKH11avjlSlIA1EnuD5XA7p5tVR3nRLe8Ad+cx5A60+/bKkDVoR7BiDqtzt2Yt5HJxceqMQeXLKPe5E3fKK0ZG+i7cibRbgs5k6wcKY0dQoC/dc/UsCtn9V/JpH6p83xMSS90X3U/PflBADU0jM6ve3tFDL39wnPKrVV+osZS8v3iCNkbX0Zb1C2jDtVdTfWUlvfOH39G6rCBamjW6gWq9FpSyP3EYaLs8752hrwvLF7DiYWuDdQxYBrQHLAJYWzW0RxsUZStKbCofGOU2jG3gnhwpcMByYJ02PoFJspmG8QcjrspvjnBH/yQrOn7Q2Igj9yN4fiidwHofwMSsPXnZUd5a4yhP3CE/Y9IQ40+gsKmex6vGm7ErTyMfqxQEe+jtuTv7OVhQCLfyGKfAggv0S+318QD6qFjAAte3+tgxlP2cAcoADy1eSQ8sWkE/XrjcvGVrm+oDox/80OLVdOuchazYYo95MfG84AYKCVAWGEhjOX+HogaUOBwBBQN7C3SMwCIVlBwQD5+OLJvZQ88zPPv9eHb9fvmezffwoLpnKDO4OsZkBBa/frhgKaeH8SYdLDbSnxWb9fPCPRsULDDHcP/ClXxPg+8Ri5tW8v3jOUZzj6MF43Hbzp7i+hqkhkXQumnpvG9ktHkO5SCUU2yDypjh/A3TBs8ZGReC2bNEg7b5rnlLWEEF5d34G8D3B9X9wpoarKEhHbxPvFdroIiE47geFiTdkbWY07R+d4iD51+dNDaLrAVBEATbjJvii4VJMgZu9rdrxtiRigsK4RUeIMjHj66cbtb2tLVBUNSzw9jRwgpkWKhA5xTC7k2zF9BDKv5Di1axdrNRa9hZ0LnVJ20qWpsdKixgpTtMJToDtNz1zr0t0KnHc9gCq5LuVgKERdi2scFP50iA2VOAzm5Zs1nJwxEYyNA715jUMwrSuAdb96ZveAY8izOgE282B0vs/xlCoA40hFEm8J5gPvazwnztiGPigoPZ2gvAyhd7q9d18O51xRd01qB5roN9vQM3XDnBynRnO1djhfHZfZWgDDdRtn5r2LAaCquIwPnsJIwc83uRgXPBWcayrGBQRq/bA3x8VNs3UI+4A9Rl9kC9pA9SuspI2ld3tOujxTj4a6yzrUEb84eDu+j3B3ZYtnNN9tsEva3EPaMds/VM2K6blcUDy8CRogTKBdovW8Cft702w915jPdb02b7PnTQDsBtEwZSsPoIAxwYuMOAEgZWrpwx2+GqaXfhTnnFyEjfhXuRdkswo5eBvj4pC8LwrMhOpBsX+VLQ/tdQeLRQHS9qy7yY9nel0TtfDm8Z0xok99f3jlGRTyZt+cmjdO26uZTSkk/Tp8VQb1c7ffHKK/TpB59T4Z5v6c5r5pK/3+j6DG6cFxPGibGY1HQXXar9h+LKU4f22NywChttvD3aurttWnO1RUdvj12rK0a5DRO2R21YQTGCSTK4YwZQ9rUnyzojvznC3f0TV8ZGAMZh9D4MlNGRT7ZwlLfWOMoTd8jPxnFCjAM6e1/uZKzK02jGKgXBHpZ+jZvbCIz/DucaXwdjx1hE6erYMayOo78LhYBpYRHcH4Q1qO3FBbxAslalBddfsNZyz4KldNuchYPmPnSgOHD3/CW0ZeZcmh4Rqe7Zi8421tO35wppf3kJ14PL4pPpanUdXXnQFuhr21ugYwSLGCPUfSAePvHdVWCVBP18KErgmVCn437x7OhfQwFwVdI0VlKwVqZwBRQP1Ct9qv4ZXL9oYfpmOIb72Tp3EStHQOkJFuLrOtr4neD+sPAFFtugUKk/Bz7PJztKi9lFF0B7mxUdx/tGRpPnaLN+tGCZpaw2d3Xx4lt4KMAC3UqVVph/gEVpUse4EMzoLlwHylxwC3l71iL+nWFMqFS1KUgbG1wkzo2KY2WXtLBITgfjhnobZQSKZ/q18JtBmlGBQep9VfFzQvESYzx4dswrQWnLkTKZM+C3JgiCIDjH+Cu+TAIg5EGjFWDyzWhGHh0vS4dSNf5oKO1tsaqDBt/DEDZ7DJNah6rK2Q/vl0X53Oj6q3TQ6KMRhZCKyRmYT3Nl8t7YuXXFBOJYAu3gMw11bGLU3uZoxZIj9NU9w3V2dWDWVRc8vdU7NArduAdb96ZveAZd03k4MJCwq/wcC60oK+gM6CuBrlQCHZRhcB9HqitsmtG1BZ5VH6yARRNYfRkOo4siY9nwxHLiCOOzIz+xat/Wbw0bLBb09vXz782Z1VUeh8i3ggcBq1J6XYO2CJYnxovBAwiuMZL21R3t+miB6WP9udGx1i1dWQNT5s8e3k/P5O6zbI4mQCwrYVU9Gh8UYvOZ9A2Kg1x/qm0k7wD1rr2zxjuP8X6xigcrjLCqB+3vvOh4HtTAIDjadaycw/5Y4055xVkcvQu3Iu2WoKFPHI5LuRMmPHAtdM+1cynu5EfkV3lCCx2gT9WbHSu30t++q6XTRfVUVtXi9FZc3kRPv55Li6+5lTbcspUuvv0OWrvlWvr2o0/p3W+P05eVQVRdUUn337KQkuNGbkpfx1L2RyG7COOLReHFQ18Z5AC4PbS1YeLRUT8Xj+RsPxhx7RVbo9zGirZOKKvoYwvIXz8bE0juwN39E33RDHBmbASKRZBRAeQ7e4rijvLWFdwhP3vC+I+nlidBsMVAe66XWvcAl/Wwyon0ofjgyPo5FApcHTuGZSUs3ITbGUyeQ+EF4yKPH9xFT+bsoSdydtNjav+bc2e5TwqFgi2zsoYoJKBuvSFzHlsswSJEWF9669RRXnzzpEpDTwfjEhizGI+FJMMBNzN3zltMc6JjuQ2Ee3z9fvHs2IcVLlhVhVtnWPoYqYIClFSQr48d2DnIkuu55iYO0zejda3Lp2ey9RAoASLv8Q7+oOIgL3F/eEdIE+8M4DmgRDHbhhWS8QJzGyWae3D8EpKt2tvR5vkVKk+g/AUlJyiV4vlx7lNaWcX5cAEIi7musCkjkzartMP9A3heZFvhKcN9mdNF/qPNdGR1yQja+/mxCVSp8gT3+cTBgbS+Ly3k5/dRcRbFJ9KKxGnaWYIgCMJYM9CTG2PGSiv6fHBJ6gyeIAIYeDigBDpbQAD8vRJWnNnePnVMO8vM16qhZWHp4E76qOAEa8MCrOyFKX5oAo+Vhi8E2fF4TRDqn8ndS4/n7LK7QRN4PDA/s/mh0XnAgIAO7sHWvekbngHP4iyfF562mKqFAhU6DFhpvyIhhTv9DZ0d7LfY2UGpkQDrKDojvY4r5QTxEH8sgQ9v/I5s/b6st5eO5WhnTRz07rUMnAvOMpZlJb+h1mJNAp04DKA42zE834ymfR1Nuz4aTtfXssIkiA4IotUOfGCPhL7+Ptpbfs7mc1hvT6q8O+5Cm+cq45HHWEmFVTwYkEGbD5PpSA+DUBigeDxnN1sHMiqJegqO5BVPQ9otQRBGSnJ8CG29KJFC9v+NvPuGWoHrSFlEJc3e9LfvG9TWOLDtaBqyvWbYXt/ZrPoMPtTbY647UT+ZVL16qsGbTiddTF7RyTQ/uJZuvWK20/0cR7gjDUGYDOhKJPjNYaJrLDjf/ROMsXgbZDQocYwX56uPcr4Yj/IkCI7AogV3AotS35cUstsyTKQvik206VIfyg6wZo2x48bOTvrmnHlifThgwTUzMoaVFKBIgHHsV/Jy2YoYLOLCdxuEQAAA//RJREFUcuw7qm7AOMnh6gquw2CZ9IoZsy3zHwDWZjamzWKFFihpQIHj2SP72fXNkZoKVmZAOrBChjrZokx6Hrku0/zsqsKgk3U16hn30ocFJ/h+8ey496dVGCyS4G7RdoxUQQFjS+/lH2dlIF0xBMBKFcL07UCleR4JC2G3zMzivMbCaigM4V7eOZ3H7wT3h3f0snpXeGdQOME9ohxg7Op8YlwAbK3gNNo8nxkRY1EexdjTmyeP8iI2KPmijCGtPx/eR1+7MGeEvN6ckclWjZDXsBzzp9x9nBbSxoZ95POhqjLtrOHBYtwO9bt9Oe8QvX7iCFuOwXN+qp7xGX5G84JuXBe/n9Fhrnc84XclCILg6Yyb4stkAY3UZekz2e8mBMGTtTW0RzWWOmj4YVUCwLwfVpU/f/TAsBvMtVlzQgkHaNwhMOrarHAvA9+9s5QAcevcbLurvq0xCsJobB2RER5FgT5jv2oCAtt3SrCHL2p72ymVByNBX6WNDgNMIQ5HQnAIdxwAlJlKWgZcQ+AebN2bvuEZXDEJC/PCWEmOVfO6/9YNqdPZzCw67nk1lbRbHXcWPCvSAjC/B2sAwxGruVZAGYYlAR2jexF3lhNM1KWE2C+rI10FYHx2WLvZqToGtn5f1hs6ERMOTbCVCUTBWcayrGAlHlYW6QO68Hm7NnmoX19PxZX21Z3t+kjZq+SMGs2kN+pLtBm2zA67yoBFEy+2cmLrOaw3dOgLGpwzk+8s453HMJkLRSf8RrBK7qmc3ZzeGyeP0MdnTrIiDJRQdYtiY4k75RWPQ9otQcMyOCdFQXASk8mLbr1iDmX3HqPA/G9QkWhHzPR5qT6IKle96ReS18LrB7Zsq814DNu8q8jXz5c+ev552vnGy/TNS8/Rrq93U+/a26k3JIYC9v6N7rlyOoUEuXeFstSDE4eB+kremT2MchvGA7Ba2xGYNMXqagCrI/ZcMY4Wd/dPWtRz6jgjd8O1EqxJAlh/wervscQd8rOrzzgWeGp5EgRbDLTn7u8nwtIEFrzgComqrwrXu9ZggQ4WUOI+8morWTliOPCbWpKQzApjGD/FGPb2ojM2FWbgagwLMVGn4AmhfLMgbmCynseuNcscZS3N9OqJXIsrfSNQTsDznO9FGnh2KFRgTBrP9IWqJ3Ory7WjA+B+oaCBvIcLntErKDjHmuRUytCswNd3dPAYlS13b3hXeGeHKst5HB9j/8sTUjxy8Zk78lxXIgVwuQ0Xz9YYrc44AxTGdIv7yOv38vP492YN8v8z1U5ica0z4Ld4tLpStcEFQ35TudUVlmtgbAnzPqNCq39E8UUQBGF4RPHFBdAIw89lphL80MTATcIHBccHKT3AvKzeOIb5+7NwOVpgHQQTMdBm/bDgpEUAhXCEzrwzGN0koKHXG3tbLFfCgC1fiBMJuJ/C80KwgN9GR2YKIYxBu9jH5M0CS5HKb2fMq44G+GBFB93ckYihdSkZPEgC7X50QmCm11lgSrFWiw+BcFFcEu/bAx2X1FCzqy5YENDNJYIq9dzuKidGpRRM1E63M4CB+7H2y+kseHZMTgL4tZ4ZGc37kxGRawVPAwMZuuJchH8A3Th7/rgNELgLZ9rXsWjXXcWiMKk60mjXYKr42llZ3H6NBrhBQruHgYU09cyjTW+kjHcew+Q78hE+l2GC+IiNwSUMKMJ881jj6fLKaNDbLRmYEfQygHIrCM4SFR5AP9yUSn47XiJTj1neN9KdeSGV5hfQko2X0Yorr9G2qwdvV1xNyw1bXIrqJ4VG0Z6eDHr7QDW9nVtP+ckbqCttCQUfeIOunt1DFyxJ0a4weqTsTzykzRoejB/oChNQ2oUFW0fAXUFMkHnhTUt3J51QstdY4c7+yZnGOssk1oyIKB63cAQsCeqyY3lrM8vvY4k75OdzzY0WRSFnnnEs8OTyJAjW6O35WLQV+D1+X1rE47SwdnFBUtqgMVn0E1clTWMXZRg7xmINZxZhLo5LtIy5QtEMyjK2lF50kC6sSAGMMc80jOVikRAWYSAf4GbGkfVz9LOdVR4YK4zPjjxDn3tT+iybG6yA4LkQx6iggDH7e7OX00OLV9rdHLmmcgTcLQdp7QasxWDMxx54Z1Ck0N0jxweHDCofuAdb96ZveAZ3ukdCPukYLZy5I8+Lmxssac6NjmU3XRtU2xBiQwHGWdC+GfMai8vsAastsMLkDBhTwriivfil6neN5wRG94KCIAjC2DJuii+WwR5DwzhRgG9gmJ6D+4O1Kek88QBhESbQ4DLBCEy28USS2oeAeGnaDIfKA2jYF1spKsQEBtmcfIJAe7Cy1LI6GOZboeXrDNA+be82W/NIDg2ja2bOtXkNKCdAmBiPyZ6RgrKkDx0a/S4b2V12jldCA3Tg8f7sTejBZcRcJQChZMKtAc4da7ASCavMMdkV4R/IghyuX6SELwzWuAI0nA9Xl7NQiPyAxvgaO24wkAd49/AHC1BWd5QOrBA4UVfFq5PAaMvJGSX4NXeZyyoUX+bHxvO+Ef1+RqqljmfHgBTyEWmtTUmjBQ4GtiAkL0tw32D2+DLx6k7h/GJpd8cI+KH+vqSIO97oqGJQGR1SDFbaq291ENfRb3WsGEn76o52fbRgkAPWSPQVYFjleMvchXSb2tLCzIqMIwFtUYc2cAKli+FcKOK9OWtpzhXGO4/1MgCRFD7OrcGKV1hjG04W0hVFkYY9eWQ4PF1eGR3mvB3rukiYOGgLugXBadYvn0Yb09oo6PD75KUNGuu0LdpCO77ZTWcO7tdCHNOu+lkf/+V56lx7J/WsvYOKpm+msjlbqHPxFvKpKaToI2/RPVvmUoC/YxnGFfShD1GmECYTcDuABSho3yErQW6zJ9dDpsJkHKzJIj6UQWwpHLsLd/ZPvi0ptCgYxyvZ89Y52XatouC8JfHJ3IfAtdGvcHbSbKS4Q36GW436TvME93DPiPyznnSELKyLeVCkH8m4jieXJ0Gwpk+f4B+jZh2u8aE4B3TX+DroC04PNyuhuDJ2HBcUYhnbQB/SlkURI1DAgWseACWXmMCBhYpwuwww2V82jLWNlq4uhwo244Hx2QN9/OjK6bPpwcUrbW7zYuItr9WooABlH7hJvm/hCrvbOsN7cgXkrS4jwu3PcO3GueYGXqwFgnx9+fl0cA+27k3f8Ax4FndhbCuM9+2OPIfbabRxaGPQrtw8O1vFX0UPLVpF182aN6IxMLSBurLOcHmNuYZOJ60VYYZKV0ayBZS/9HGjUaMlI/0KQRCE4Rk3xRdPBx2427MWDdnuV8LBI0tWc4N8YUo6BaiOGCy9wC/uaycOD7HMgY4x3N+gYYPZ+pWJ0+hHSrjAp7GTiA4pzBY+uGglT/wb2TIriwUSKNkYBQko4CxLSGbBAcDSBVwTOAO0VY+rziQaW2i4XjljDt2QOd/SMca94Xr3LljGgodRW9fTaFAdc/3+oOGMvAUQfGZpFj/g8gaDDYgHk3nXZc6jrXMX8iocHeQn3B3Aig8UQRAXfjYxwDHWQPjfVpjP5QeTZejgwzoKfEyik+Eq7+efYAEYMhDy4b5FK7h84Rl18Oxb5y6iS9NnKiHUmzshMN9nLEO7SovplDbooJeTm2cvoBkR5nxFOUF+o5wgPUfl5FxTo2Ugxs/kzYoym6dnWso07g0C6yWpMyzC50iAGU6sRkAK0Jb/cfZyHgwx/nZgDhcuyiDs3zY3WwudWLjbh7AgjBZ0FNEO7is317UYDEU7+ZDqkOJ3iN87Bi2h2IcNSmdo7/A7fFi1qxumjWxVzGgYSfvqjnbdHWCA6rkjB1Tdaq7rU0LC1H0s4wEAuGbCQIee1/Ni4ujStJl057zFg9oBa749V8ju/FDnox1Ee3i9ai+Ng+Z4RpjRvXv+En6vzlqac4XxzmPdUhhcW2XHJbDZWx1MetylnnWRnQF3I/pgCQb6kS/6AAyssmBgxRk8XV4ZDdJuCTr64BzqGkFwhcAAH/rxdXMp4sCr5Fs7uM7rCU+mrnV308fPPctKLcNx4JMPKLewnlrmXUF93n7UGxhOff6hrFATtP8Num19PE1Pca9yp97FkbI/cbBMJnjgO8O4AWQyW+NW+oa+u+42YayA/AOLiXDDaeyDb1T9bV2+Rr8Aljnumr+UVil5DvId4mPx2Fhaq3Nn/wSLxzCOhgktjJ9ckjaDZUQ8l65Eg+fFc9+3cDnLgRhvgwWEj1T+jDXukJ9zqspoZ6nZ+gOeEUoneGcoZ3oa+ETfCX2oi1NncJgO3qk+sQ3FfOQf8gZycJaSh53Bk8uTIFhjac9HMYbpCChz6X1D3TU+Jv6x4feH/qKrY8dQXtHvFuk685tp7zFP5KNN9DMoJOh133CT/Z6C8dnhSg2WX+1tsYHBqj7rY/dMPQaFHSx8PttQp96N/a2ydWSu7YyLZ/Q8dwQWquIeAepB1Ns6uAdb96ZveAY8iztAuwLFLABrJrBiq+OOPD9UVU5/PLSXXfhhDg4W8jE+AjkH83MPqPZsU8YsS3l0BqNijTN5LQiCIExMdFlt3BRf9AuOkWw4aiBEPqA6u4M21ZDCysvVM+bwCuee3j7KVY3v07l76aW8HLtCJjpt6DxCCISli83TZ9PDqqP9kyVr+POnS9fQI4tXq47nKnZVoAsLOmuS0uieBcvoIXX9n6i4OAcbFHCumjFXpelLHaqR3l1WTAVOKr7gXt89fYz9DONN8IRZ9jK+j5+pa/xU3Ruut1EJDlVKWHLF1c54g3egTzYlBIfwIAaeAflzkdYRh8D3wtEcOlZbyUIYnhd5+vASc1w9Pjr/WJkDEPf5IweprMV5H5GjAe8Pph/130ZZa/OIB0hyKsvotRNH+LkxkbckPonLF55Rf148OwZCkBfQEP+yOJ+1qI1wOcnPG1ROkG+PaPmGcoKyeFlGJsGEsKNyggGQ7cUF1NSpr2SP5ntCmdbz/15VBgOUADuaPIdrqC80/5sQevWBLf23g9/dT5aaf28/yFrsVg33cUWrPGXgXHCW8SgrqMP+dHgf/w5Rr/iavLlDioFR/ObM7ddqbVvFdS4UStcmp43YxdloGGn7Otp23V18UZhPz+TuYwVFtG3RgUG8guaBhSv5mQby2qywCzkG1rsABrl0y286+Q219LaSDcpazXXwbFU/4h3hWX6i8gSfer1/vwpfkTSNn38sGM88xvvV3VphcN18HfMzY9Lj5jnZvBoO7Yoj8moqua3DgODC2ERLm4vJD2fNCE8EeWXESLslDMFDO4KCRzNnehTdfkE4Be5/HRWKFqp2VXlqm3sZ5Z2ppH0fva+F2qajqYG+eO11alt1O/V5D3bVGlCwg+a0HKQ7rskiHx83D49I9Se4EcjZF6dNHzpuZdgwxjMWSsrWQPkWSgdQJrb0wQ19fV1+vGXOAopS8iriIf724jNaCmOHu/onkPFeP3GE9pSX8KQc5O5blIzIcql6PjwnnhfPjefHBCbcHTx/9KBD9x/uZLTyM8bVXsk7ZFEUwrvCOzM+Iz7Rz4B8am09F2NzcJcNoPhye9ZCjg+Z2hUldU8uT4Jgi7FU8IcLZt01PqyyQukLY7xQ2sOiQViEgfv8sURXyEA/rldTtHAV3Kst66q2GM1iSGfBgsnHDu50anvn9DHtLLM7NswDPZGzy+6Gse/xwFfVj1h0A6BoiXpbB/dg6970Dc+AZ3EHWMCKBaYA1msPVJTyvjUjzXPw9bkzrPzyh4O76CP1m4B7IpAcEsbKnBjrGs5i8UhBOzQORdJl9HpHLL4IgiDYR68jx03xRb+gp459wyIFOlDGDT6B0aagI4cVuVhp/WTObu78lreYTQ/aAsoDLxw9QJ+dPW3WTPX2YUH1B1mL2BIHOtVYaYLJjRIVF/41jcC/LTRRF8Yl8oodnIMNCjhxqiNe0dpC7+Xn8X3oqyucAW6ZXlCdcKzuhnCUGBzK94HVLdCanRMdq4SgGnr2yH6e8PFUclTn+hslAMElBQYxsEofz4BOPgQgnX0VJZqGcAF3jPFO16UMmP5DfqaFR7LGM+IgLs4ZLzDI8L3q4MPnJd7HfnVtuJ0YCSgH6Pg/nbuHBx+gpIWVXnhG/Xnx7OEBASwsvn7yCE+02VLewuABBmv0cgKrOpcpYRJpoJygXBY01NKfDw9fTr4oyudJVV69o+oAuHHgMq3Swup1H/X+3j2dx2YGRwqUb/524jC9deoYp+Nt8uLVRbgOFNewwbIM3DPVd7Sxv9oJiaUOlRF0wbNA3fWM6kQ/p9oOmKmGT2pYR8PvHYOWsMCEDVY1poVF8NAHfNIj7ngz0vZ1tO26u9Dr+scP7ubOP+o8DHhgkB4DYXpewyQyBsnClBzTruppmBBHvY8VM9ag/YMyDeJ0qfST1DPgWfBMeDbU+3hWgDYS8caC8czjT86c5OugHcbgEQbxkT42rCKFQskHKp/RPjsCyqpot9FWYrD/CiWHoH2Du0GsxnMWT5dXRoy0W4KGp/cDBc/G18dEd183nzIb9lBg0V4tlMi/qZRMe9+ktJkZZFJ1uT16u7tp25//SMX+6dSRsVILNWPq7aaAPS/TnZcmU1T4YIUYdzBQ9qXwTxQ8ub7CxCDcJBvHrKw3LOjSXQyMJeiDw7IK5H+MG+DeoHCj9/WhZALLI7Bsi+OIZ8ti8ljhrv4JlGj+fHgf9w8wLgjlEjwXng/PieedpZ4bFhhgHeaJnN301TgqY7hDfoZVSUyI6ivr8YzLVb6gD4BnxGe26juhz4HJeCNYKAArwniv+O3A6iHyBko2MzWrwc7g6eVJEHQG2nNzWzEWYGHj4apy/s1FBARwXYUFPNg3jx2XujR2jD5kr+ZvFBY4MlQ96AgoNKBvC2CNw/i71628YMHlcAtiogLRHjlnkQPuy+wBq1OuWPYwYnx2KEJiIdFfjhwYdvtU1ak6WKgCRUrU7fY21EsjAeNTOkaLxPbAmBWsnwBYf8GiVR3cg6170zc8A55ltGDcCRa5YJEIZfRkbQ3tNYxNuCPPddAmw+X3Hw/tpsdzdvGYFsZqUP6wqBWWj511xW0c33NU3kBGeBT/VjwOrfrRZVVBEATBPt7/otD2B9GjOoa9qvPmLv72t79RZ6dq/GZPp/5w58y/jzWQV+GOZW95Ce0pPzd0KztHO9UG4QB+NjHZgI4dGvbhwOQZfG4Wq/SxD/c8UNSob2+ns031dFAJqh+fPcUaufDLaVxV3KEEySLV6YayQKsSZGAxo7qtTXVIK7gz/cmZU7yyw9rai/F5IHScqh8seGEVO84pb23i1d1wdQMhBB343Opy+lRLF+4drpk1lwVdCAZYfQGFGCPw5wlBHNeC0G1v1fFw9zQS8BxQPKpSwjcUL/Ad14epx8+KTnO+62C/qFG9h+YG1oqHANaqnhuCOwQodPw/OXuSJxDhNsBdOPvcKBfIf1wbCif2FEBQ5vDuUC7tpYd8OFVXy3mRr+LCJyvM9zV0dLA1GbxjlDUIk3jPxnwy4qicHFFpoMy+j9U1RWe4E2QuB+fYn3Zth9kPrA7KNVY94bkwKIH31azKM34D+H3B4sw29dvCRB/8d9orTwPlzfZ1oEWOgSq4VsK5ON7W3cPXRBjO+bwon3/DcI2EcjDR8C6pIFN5FSUlJdFll12mhQqCfT7//HMqLy+nvuR4tQ3vtmU0oMOdV1vNdc0J1V5gEBa/P7R7GECtVPUHBmdQh+E3+JWqR7CP1SE6qOdQDyAck/r26ijUr1XqeqgrUB9aD/ro6diqT0bavoLRtOtguHrMWfB8qO/QVuN+cO81Kn9Rr6F+xbOVqGeGedjvSs5y24KBbNS19tqO0/W16h01c32N+0LeQCkEZpD1vPlcta/bVPuBCQAjeB/G9s7RINxweeC+PHYsm6DNgVwA3826HIG2EvmAlUXvqbZpp3rmenV9DDzurTin0q0YVF4B2kXd+hkGnnA/pxpqeeUtZCe0TcBRmdTBc49WXnHnu3AHeru1ePFiys6emG4GBfeAtghtEpSTb91kVqQTBFeAyyOvng7a9d1R6klbSn7531NazUFaFdtFGzZfQkkzZlL+wf0Ul5Y+RAmm9MRR+utvH6Omi39KvcEDE7FwcRRy5EO6mPbSAzfPJ3+/kU2qOOLQqUbKO9Ms9eAEQq+vKDyUx648AchDkEd4jGqYzbpdd0U2QNwBGdu27GMEsgom2jBmANkUcg+UhiEXQRblPriS+z9RshvGICCj2sJZ+c1V3NE/ARh7Qt8A4wrY8Nx6GpD79qv7hnyKPsT3Sn6E3GeNq3nrSp6MVn4GSB9pFKrNmIb+jJCLt6k0dpedY/lXB8/K40Yqj5AuZGrkO1woof+hKxINfn7b5XC8yxPuyd1jlaPFVFpJprJKWrRoEW+C5/HKK69Qt+r39S5doDo7I5cbYK1cdweGhSVQTNDB7yrA15ddjkHZCwt34oJCeLFLnarb/3L0wJDxii0zsywujq3TQxrrU9IpyNdPyeImtvKOsQJ7rJuWTpdPz+TzGrs66M1TR/k3CeDyDZajoJyG3yf6vPjd2wJuppeqZ4CFEtQPGI9FHaoDZbb5sfGcFvrkHxQc59+vNViICcUf3LutdGZHxbLbZyjHoL549XiudsRsiQrKjkEqP6GrhDEU6/mNscL4jjHuYG1xHcBKLFwvw20R8gl1Fupde9yYuYAXcSHPYL33xWM5FmWkkYB3AGtCuL513tkCSi9wv4yFQ7AKhHr4r+oecN86Y5HnGL/BWA3qaSj+QMkSC9hhQf5IdYWlfBqfxzrPVyVN47ICpRH8xjC+onsTsGZzRqalTNmbF7tt7kJWVkJaPGak2hJbOLonV/GuqCZTSTnNnz+fli5dqoUKgiAIRrxV3e2r2iCvfjvLjzo6OlhRxV1s2bKFmpubqWvLpdSXkqiFTg0gnMK6ClbgQCcTghq0bNGxtAcsmaSEhlFiSBhrSKMhRQdTVyAYLdDMhkWQGHVvKAKYZDnbUM8N+qVpM+lf1l5Ckf6BfK1ff/c5TwR5GsijjIhIzlsoYJQ2NzrMU7wHdARgyQeFHooheO7J6hMYPqaT1fOi/OC9VrW2cufA1kCHPazLCcotBoxcSUMH1njgcgNp4vxSJfAZOyvuAqvc4FMamvDoDHT29lK5ug4ETKOG90TDZ9dB8jl4jJYsWUL/8R//oYUKgn3+7u/+jg4ePEg9y7OpZ8VCLXR8sG730IahrsUk/vmuc93Rvo6kXR9LUN/DOpe+6gr1Hga00Ma5Ul+PtezhCuOVx2jj0Dbh2euV7Av/1K4+K9od+KiODAjgQRmsqB1NOZ8s8orebv3whz+kO+64QwsVpiIHDhygv//7vydfHy96/7eDLW4IgrM0NHXSr/6wlz5tmk0bL8ikebOnU1rWXCovyKcDuw5Q6ck8+tE//3dKyRpQMOnCBNE//pK+751FbctuoX6vgUkqv/pzFPHKI/SXv5tPy+aPjYLwX94vpte/KKN77rmHfvCDH2ihgiej11d90xKp65pLtVBhOCBHQR5NCAnhfU/sg7ujfwKZD6vL9TQg90HmHotxjZHgDvnZOg1nZVtdpgYVLeZrjvTdT4TyNBb47M0ln32H6a677uJN8DyuvPJKam9vp877bqN+35FbhPjXtRvphsx5vA/r1f/8/ee8r4O+/f/bsJld3cLVGqleISb6oVz3D998OmTC/tnLb+CJfWCdHhQRkBaskpKXFx2qKqP/s+dbVhiwBhP5/7hqA23KmEUmVQPsqyilX33zieX3//Nla+nOeYtZIYDd2BzYyRY5rFkUl0j/tPoii+IHFOL+8ZttrFyoc9f8JewWDQo2UIz71defDrFqinrgXy64lK1QoT6ylQ7cqv1aXQtjIVAIuubtv2pHzPXZY5dczQobff19rPz3H3u/s1snYiwZG/JotPwPdd83zJ7P9w3FkLs+fsN8wMDi+CT6v+svZ6u7qOfeO51Hfzi407KAxgie4d/WXsqWTqDs8nLeIfrPfd9rR0cG8v9H2cu4nrXOOyOo25eqsrgpfRatVOUM7wzKm2+ePMpeA4zjJ+7I8xjV/kAZ0lz2BwOlmt9cuFHFCeZ7+Ned21nxFBifB4qaP/r0LQ4HsA7zi6VrKdjPj5W2oDT0x0N7hlxjengU/bfVG1hhBXMKaEd/s+urIQor719/J1uRQ5v07OH97JLJFo7uyVV8Dh4ln105tHXrVrr33nu1UEEQBMGIn6rnAwMDx9fiS1dXF/XOmU79YZ5h8WW80M3PYSU1NnSK7WmV6qATjg4mlAxwDgQErCq2p0ntKmiYMZmlpw2NYlwTXD1zDq1QDbxZGxWmUw8O69LmfID7xX3j/pFPw+Up3gMm7/T3gHeCsMkK8kMvP1j9g1Vfrg4SWJcTaHOPdKABAinKPtLCp6MVTqMBvxH8VnC/uBbyAL8lvXxPVEzayvnExESx+CI4xWeffTZuFl+ssW738HvEoLIn1LnuaF9H0q6PJbi2Xr9iw7NhsMTV+nqsZQ9XGK88xvOijcQ1ICOM5Flxji5f4HO05RznTwZ5RW+3YOlg4cLxVb4TPIuKigpuk7BS8zax+CKMkAB/H4qL8KO3XviA7vjFT8nb15f2f/EZfXe6kfY3hFBDQDx15n5JC9dfxMfAoc8/offf2UYtG39JfT6DzZqH7HiOfjCrhq7fOIu8vU1aqHs5dLKRjp1p5pX7Ug9ODPT6CmNWGLsSnAMyJGRPXabyxD64tWw5kv4JZD5jGpDXxmpcYyRYP+NI5GfrNJyVbXWZGhvKwmje/UQoT2OBWHzxfGDxBfMlPUvnj5nFF4DJ9qiAIFYggcsVWNfAZP0bp46wtXNrHFl8gZIEJvBhKQTKIdEq3ejAIOrt61O/q3a2FA5FlkXxSSqdubQxbSbHw/jvS3mDrXmgvsN8AZQA4T4uMSSUz8f94hgUZ1YmpbJyzLyYePJS/3TlAWtLLbDWASWGEHUtuGkL9/fncWvUy7D8kh2bQLfMyaY1yamsNABLHbbScWTxBXVXrHrWebHxFss5Yeo6CIc1G13pAQo2a1PSOB/hZg3KGqNlcXyieoZEtuSC54G1Etw3LOZgoSbqOMxppIdH0szIaM4DKID4qXzB4l4cw3nI07XJ6WxhBOkhH2CFF8oW9ixfOYvRGgnGjuC2Dwor+gY3d6vV+4QiFNwvw0KPr7pPLMx5r+A4u5yDcqURd+T5bVkLWdEGZR/zUShjAAo4cLO0WB3D+4ZC1qsnci354Mi6SpO6NvKP81idmxAcwveCcot2Ei61YGUJZQ7KPSi36LsiXzzF4gvGVjDGsmDBAl4UKwiCIAxFt/gyNiM8DoGuq3A+mKUEKTTKjoBgsVYJntAkh+/QIzUVvMpYEITzjBK6BcEV7Bh0EwRBGB+k3RKs6NcdkwvCCFk0J45uvWIO7XjnXXr3k9300VkvOpmwnrqW30gdS6+nfUfP0pGvv+C47Y319Pmrr1LHiq3U6xfMYToBJQcpo/JbeuDWheTn634XRzpSDQqCIAjC5GFgjGXsG3i4Gi5sMrtwwVXz62vp2xEqZGDi/sOCE6xAhkn/dSkZ9ODiVWyN4qdL16jPNfSw+o5Jf1h7QjzEh9tkI3BT9unZU3wcOTA7MoYeXLSSHrGks5oeUumsSkql4qYGh4toT9RW04GKUp57gGLPBcnpfC7uBWk9vHg1bZ6eycp3o1mM+/HZk7SrtJgVgKDQc8X02XydR9R1+HrqWrj/BxetoutmZbFChjvIrSq3KB5CyQL5i+fCtTakmhVroVTx+okjrDQBJQwoJOEdIK6eD8hTvCu4oEI+oUxggTIUnNwJlJnwLo3bA7ytoGtmzGWFnZ7ePnYl93TuXnrp2CFWTrTFaPMcrq3uyV6mlQdzmTKfv5qumjFHpenLiqhwV1RQP9RNuS1wr++czmPFTvyeoCgGSywDZdf8G7gsYxZbIBpvi8dOoVU/UH4SBEEQHDNuii8W4VAq5/PGNTOzWHC5PnMea3pDm1UHGtLXKmHjfiXQzIyI5rYUqyo+zDebixME4Tyj1Z2izCA4i5QVQRDOK9JuCRqWwTkpCsIo8ffzpke2LqLCnZ9SQXswta6+i7oiUtmFEZRbOlbdTttefoXa6mvom1dfpPzOMOqYfbF2thlTXw8F7X6ZblsfR9ERjheFjBYZmJ54DLwzqbAEQRCEwQzMbZg/xhJM1O+vKGErHJ09PezmyJ6iwXBgEv/1k4fpL0cO0Km6GrZmMTsqhm6ek033L1xB9yxYypYp4MIGxxEP8W1N/n9QkMfujTBngNyA0gIUI5AO0psZHkWHqsrpo4ITrPhgDyiFvJyXSzvUc0GJARZgYHED94K04LqprKVZpXOS2ntGbv0Uefb80QP0eeFptqICyyrLEpLpjqxFPAfygLoWFDNSQsKopKWRlSncQY7KA1gxaevuYos1y9Sz4bnM1zJb5wGw3vKnw/vovfw8trgOCzh4F3o+IE9hEQXlYKe6tycP7qbtRYMVktwBFkBD6cm4wfUyXjLuC/nynMrHJ3J2s7JOmcHqjjWjzfOWrk62FoO5Ky6j6hxsKGewIFPR2sL5hftwxcrx1+fOsNIQyjgUruDWD/eBfP6Burc50bF8DNZ0PNHzgaqA+EP6F4IgCMMzbq6OXn31Vc3V0QzqDwvRQoXx5N7s5bQxfRabU5wZGcOC0+K4JBaoLs/I5G2uauR9lLBT295KLx3LUUJK/qQ3JyoIEwFTaQWZysyujjZt2qSFCoJ9tm3bxubaz4erI0EQBL3dEhcfQmVlJbdJGKPbenmKFioIIyMsxJ96e/vo22NN1JmlZGLL4K8X9UZNo7bje6nt9EHa9ek2ql3/MHWHJWrHzYSf/IxWt35DP711AQUG+GihY8Ph0810tKBJ6sEJhF5f9YcG89iVIAjCeCGujjyfl156iedKepdnqxc28rXEff1EZxrr2NIHtiLNsos1sKwCBYM95efo63Nnqa7DtmsbDNsfr6t2mF5jZye7a4FVd7gQg1IL3CfVd7azC5aDlWX0RWEBW3T5RG323OggnbPq/FJ1DtzctHZ3U2tPFyupQOFlW+FpthaTU2m2eAIFENwTLKBYu4aDNRe4/4EiA+LifuAC6IR6lm9LzrJbGDw78sFeOpixgMub/ZWlfBxWaaxB+lDGKG5uYIsf/OzqvvGJvDignv2TM6fYwg2UI+BSabRAmQd5jXuDEgWUgPCscB31mcojuNvTKVd5V9BQR6WtTRynSeUx7g+un07X1/I5n5w5ycpEUIBy1zwNkilpbqR9Kn297AzezrFSynclhazE8kVRAd+nM9cfTZ4jr4oazW63Ub6a1PtGeTyi3i0UpVBGoRCFezFifB64BIN7KSN4JzgH5a5M5XVrV5cqcz3sXutQdTl9qu7nY5XPiHPNrLkU7h9g19UR8uBwdQXnEd6PPUWg4e7JFTC2gjGW7OxsdictCIIgDEV3deTVb2cZZkdHB3WqhtZdXH311dTa2kpd111GfUnxWqgwnvz3NRezJiu0h6HdbQ0KQocSMiFgQvhAYw+BRBCE84/P3lzy2XeYB0B++9vfaqGCYJ+f//znlJubSz3Ls6lnhUy2CIIwvujt1l133cWbMHU5dOgQ/eIXvyCTyYs++t1KLVQQRk59Uwc9+H920755P6GWWRu0UDP+FXnktf9dMkUlUfuau1Qfd6Df69NSTREvP0R/fGA6Xbhs7JWw/vrROXp1WyndfffddOedd2qhgiej11dQHO+69jItVBAEYewR2dnzufzyy3lRb8cDWzGzooVOPGCBJC08gi1eYB+KBlDSONfU6JIFDbjHSQ+L5E+chzSgsOBKGsB4P3DnAyshsCgzFnMSsUHBfB24FfJS/1q6O1mBx6iI4k7wbNMjoihBXbNH5QuUIBxdC3k5LTTccn9QTKpS9weFmInKSPIc+TYtLJzPg8WY3v5+qm5r4TLmjnIBF0wZEZEUGxjMimhQhjnTUMdl99K0mfQvay+hSP9Avtavv/uclXPONz77D5PPnly644476Ic//KEWKgiCIBjx8/OjwMDA8XN1ZNI1oXv7zJ/CuPPe6Tx6/OAuevn4IfqiKJ81U6HkAr+Q0N59/cRh+oM6/mSO2WydKL0IguchLiMEZ4GGK9Mn7a4gCIJw/tDNMYsMI7iLyLAA+tGV6eT39TPk01arhZrpSphL3RfdRx0rtw5SevHq76Ogw+/T5Zn9tGzB+FjC09eaSNmfOFjMx8srEwRBEKwYaM8H5IuJCCb38+treS5ge3EBW9HQJ/1dAfMGOVVlnAbSQpqupgGM9/NV8RmerxirOQlYYEH6uA7uG5ZNxkrpBeDZTtZV0zfnznA+D3ctPLfx/nIqyya00gsYSZ4j31AmkWc4B/kHt1DuKhewMHO0upLvCWnjHelld15MHCvGAFidwTFBEARhYjFuii9BQUH86dVi21SeMPZAyHg57xA9fWgvPZmzhxVcnjiothyzsstTh/awr8OdpcUjElQFQRg7vNo7+DMkRFzFCc4RFhbGn14d7rPeJgiC4Cx6uxUcHMyfwtRFXwCBuYJeLKkTBDewelEyXZbRQUFHP2GlFh0ou/QGx1Cft3nAWieg6gQlFnxKD29dRIH+Y+viSEd88E88LAu2RFlJEARBsMKi+CLNuyBMOGZGRlNUQKD2zTZL45NpbUo6+Zm8qaevj90rwcqMZyAVjyAIgrOMm+JLZGQkf3rVN/KncP6Adiy0VXXNbl2bGhq4giB4JqY6c92ZlJTEn4IwHHFxcfzp1Sx1uyAI44/ebsXGxvKnMHUJDQ3V9oiaW3u0PUEYHSFBvvTwbYso9uQHFFCTr4Xax2/Pa3TLqlDKSA7XQsaexuZu/hQFwImDXl+J4rggCOONV2cXf+oLRwXPY0DxRSagBWGisWXmXLp/0Uq6blYWZccmUIjfgJJ8ZlQMbVHh9y1cTjMjotnwH9xSfVhwwhzBE9DqH1GsFwRBGJ5xU3yxTMCJ4osgCIJr9PWTV4PZtGVaWhp/CsJwiOKLIAjnDUO7JYovQkxMjLZHVNNgntQRBHcwKy2Srl/kT/773iAvu75p+inozA7K7j5Gt2yeM65zVecqzebYpR6cOOj1FVsqFqsvgiCMI3q/3Sg3CZ6FuC4UhIlLVnQ83Tonmx5cvIoe5m01PbLEvGH/oUUraXVyKvl6e1Nteyu9fvIwHawo084WBEEQJhLjpviSkGD2o20SxRdBEASX8GprJ9JcRsyYMYM/BWE4jAP3Xr0DLgAEQRDGGmO7JRO+Aqxd6KuXq+vFioLgPqDEsvWquTS3LYeCSg7YVH7x6Wgk/2//RHdtSqGYSMfmzd1NSZXUgxMNS33V3W2xviAIgjAeeLWYFV+io6P5U/A8RPFFECYuRU311NbTTYnBoezO6M55i+nBRSt5uzRtBiWHhlNXby/lVpXTM7n76P38E9Td16ud7TmIxRdBEIThGTfFl5SUFP7kCTgxGysIguA0rDCoOtgQbqdNm6aFCoJjLANmGLjXJqAFQRDGA73dCgwMpIiICC1UmKpAftHbpOp6mUgW3EtSXAjdeWkSeX35JzJ1tmihOv0UdOxT2pjSTOuXj68M3djSTQ2aqyNRfJk4GOsrsZooCMK40trGH2LxxXMRV0eCMHF5L/84PXFwF71yPJe+KMqnI9UVdKKumo7XVtP3JUX0xokj9Lg6/mTObnpd7dd3mC03egyieCcIguA046b4kp6ebt7p7SWvmjrzviAIgjAsuos4Hx8f8fcsOI1xwMyrvkHbEwRBGHv0dgv1kK+vL+8LUxu9TaoWV0fCGHDp6jRaF1lBgSe/1ELM+NWepaij79BDNy+gsJABP/7jQXFFO/X29XMdKAqAEwuj1URBEITxABamsEgUbUZUVJQWKnga+nicLOgVhIkHLLm8lHeI/nhoDz2Zs4eeyNmtbbv486lDu+n5owdpR2mRZ1p66TL3o2VeQBAEYXjGTfElLS2N/P39ed+7SPzjCYIgOEV/P5nKKnlXVosKroBJluTkZN43FZfzpyAIwphjaLdmzZrFn4KgyzA1DTJRILgfKLX89LYFFHXoDfJrOMdhcHsUcPAtuma+D2VmjP8kYqnm5gjymCgATiz0+spLs74gCIIw1rCFqb5+Cg8Pp4CAAC1U8DTi4uL4U1fyFwRh4gFLLifrqum7kkLaXlRAXxWfocPV5VTV5tmW/nRLhGIVTBAEYXjGTfElNDSUZsyYwfums+fEbKwgCIITeNU2kKnUPIG4Zs0a/hQEZ4Cy6YUXXsj70u4KgjBe6O0WrJTpdZAg6G5vz5S2UUtbD+8LgjtZMDuWNmf2UkDOu2TqaqOgkgOU2bCX7twyj7xN4++S4GSR2e2SXvaFiYPFTXdlDX8KgiCMNXp9Ex8fz5+CZ2JRjKxv4k9BEITxQh/Ttbi1FwRBEOwyboovYMuWLWQymcirsZlMxaVaqCAIgmAP7/xCoo5OCg4OpiuuuEILFQTn2LhxI68GkHZXEITxQm+35syZQ4sXL9ZChanO8uXLuR9YWt1Bx840a6GC4D58vE1097XzaWnHPvL++k8Ut/8FuufSBJqWGKrFGD+q6jsp56R5NTjKvjCx0OsrU0k5merEXaggCGOLV3c3eZ9W8rMiOzubPwXPRFd8MTWI4osgCOOLWHwRBEFwnnFVfFm7dq1FSPTOLyKvHlntJwiCYA+Y1/YuKOb9rKwsSk9P531BcJaMjAxatWoV70u7KwjCWGNstzZt2kRhYWG8LwiZmZksy/T29tO3ObVaqDDVqG1op7aObu2bmYbmTmpUW3tHD1XXtQ3aWtq6+Bzs19S3U0NTB7ypMV3dvRze29dPdY0dfP70lHB6+Mokuj/uIN2/rJsuvzCD4za1mK8B9POMG9LW6ezqpcraVmpu7Rp0LcTRN1zLEfvzGqiyrpNdVqxbt04LFSYKen3l1aLaNG0yWhAEYawwVVSTqbKa24yLLrpICxU8kQGLL+LqSBCE8QMKkqqTwu5To6LG34WrIAjCRMP7XxTa/iB6enqot7dX++YeUDlXVVVRXl4eebV3UH9yAvWHhmhHBUEQBCPeZ4vJOy+f3UX89Kc/paSkJO2IIDgPJp537NhBXQ2N0u4KgjCm6O3W9OnT6e6776agoCDtiDDV8fIyu5rZuXMnNbR00/KsSAoP8eUwYerw8gfHKb+4gRZkxqoyQdTf309Pv5ZLLW3d1NzaSX95+yjtzi2jnTlltOtQGXX39tF7XxbQ9wdKac/hcjpwrIK6evooJT6Uisqa6KlXD9Hy+Yn0zBuHydvbRGlJYZSaGEZL5sTQsnkJ5O/nTb0qjT++fpj2Ha2glQsS6UxJIz2jvuM6Ow6W0d4jFSrdSlq/fJo61kBvfHqKvtp7jg7mVZHJ5EXJcaF05lyDuk+cU873cfxMLUWE+lNM5NA6rlvd34sfl1B5TScrH1999dXaEWGiYKyvvNo6qC89hVRh4jBBEAR347v/MHlV1XGbcd1111nqIMHzKC8v57YB9GbP4U9BEISxxtTUQt5HTrLSy2233aaFCoIgCNZ4e3uzHsq4WnwBmzdvNg+Cd/eQKfc4eamKWxAEQRgM6kbvvALeh8LLsmXLeF8QXGX27NlmdyPS7gqCMIYY261LL71UTPAKQ4D7kMTERKpv6qbvD4nVl6kIrL1AWQUWWEBTSxc99/YRVjA5VVhPn+0opLAQfwoN8eOtXcV/5aPjVNfYTtERAazc8vu/HqCjp2uorKqFXnw/j1rbu+ntz0/RMRUGMF8YGuyn4ponDqvq2ujZt47Qyx/k0YG8SvL19aaYyEDq6Oqll1RYUIAPpw3rMkj7bGkDJcQEk6+Pif78xmH6bn8JlaprvfzhcZWuL0WpuFCeefzlHE7fmoKSNjpR2MITl3A5KUxM9PrKq6GJTGfMlswEQRDcjVdtPXkVl3ObsWHDBlF68XCSk5PNOy2t5FUnVl8EQRgfvCqq+TM+Pp4/BUEQBNvosvS4K77A7cLq1at531RYytqKgiAIgoHuHvI+fIJM5VXk7+9Pt9xyi3ZAEFwHFoOw2jguLk7aXUEQxgZDuzV37ly68MILtQOCMACUofR+INwdlVZ38L4wdbh6wwwqqWyhI6eq2Y3QW5+doqS4ELpwqXkiKSLMn90TbVYbPmekRhKpeFeun06P3rWUHt66mAqKG/h8I7pLIlt8/M0ZSooNpoVz4lh5JT0pjH525xK64bJMHhS596ZseuT2xfTFriI6fKqG7rl+AT102yL6iQoLDvSlP715mK24mLyIwx+9cyndqM799PtCdrNkDZS62jp6acaMGbRw4UItVJhoGOsr7xNnWAFGEATB3ZhOnSWvtnZuMxYtWqSFCp4K3I+zUmRPL5kKirRQQRCEscVbtRVgwYIF/CkIgiDYBlaFwbgrvoCbbrqJhXqvvj7yPlHAAwmCIAiCGe/jqBcLCPqJV1xxBa+cF4TRkJ2dzcovvt7e0u4KguB29HZrWkoK3XXXXQOrIQXBCihFhYSEUFF5O73/TQV1dfdpR4SpQEpCKF28MpU++KqAGpo72EXRbVfMZQstoK6xQx3L5+PYqmrbOByujuAm6c1tpygsxI+VZZwB57/60Qm6+9r5dMfVWbQrp4wqaloHrajHLr7jelkzomnO9GgOD/D3oQuXpdDhU9XU1dVLff399PqnJ/k+YAVmVlokxzOSc7KRdh2p5/2LLrqIgoODeV+YmOj1lam2npU7yc2uwAVBmNqYyirJu8BsUQptRnh4OO8LngvcSONdAX53HWYLdoIgCGOFV00dW3xBG3HxxRdroYIgCIIjzoviS2ZmJg+KR0ZGkpcSEn325ZKpqFQ7KgiCMHWBKW2fQ8fIq7OL1qxZQ7feeiv7pROE0QCrL3A1uG7dOml3BUFwK8Z268Ybb6QVK1ZoRwRhKHC/t379et7/an8Nb8LUwc/Xm62rfH+wlD7fUUjVde108apU7ShRoL8PZaZH8TZbbbC4AppauyivoJaefDWHrr5oBi2dl8DhRrCyp69P27RVPrDicrq4no6rc3fklLLLpOfeOkK9vUMttUyfFk7l1S3sXgkgTmVNK1uhYbdJ6pSa+nb69Puz9OHXBfTALQvJG2ZgNApKWunlT0qorLqDZXixfDXxMdZXWGmrr7YVBEEYLbAi5bP3MJkam1l2ljZj4gA3hkFBQWSqa2Brl4IgCGMJ5E9YmYIlyenTp2uhgiAIgiPOi+ILWLt2LSu/+Pn5kVdTC/nsO0xeSuAXBEGYqphKys11YXMrmy+88847KTY2VjsqCKMjKiqKbt+6lTtL0u4KguAOjO3Wpk2bZAWSMCwBAQF0/fXXU1ZWFjW39dAbX5TRoZON2lFhKrAkK46iIwLo2beO0pZLZrIbIp3u3j5WLqltMG+wAAMuXJrCFlvWqs/m1i7q7BpqeWPPkQp69u0jvL352WnqUHFgoeXK9TPIz8+HTCYTXXfpLHrloxNUVtWinTXAzZfPZkWcJ/92iN5Q5z2n0vlqzzm6c8s88vfzVud70c2bZ9PtV2VRQkww1TcNuOqqru+ilz8tpWNnmmnp0qU8zpGSkqIdFSYqxvoKyp0+B49xuycIgjAqurpZfjaVVvC4j7QZE4u0tDS2qAs/i7rFHkEQhDGhrYO8z5awdUpYm0J/RhAEQRge739RaPuD6Onpod4xNuWKFTTe3t6Uk5NDXi1tvAq9PziIKERtgiAIUwhocPvk5JGpqpaVXR5++GGaP3++dlQQ3AMsrSUkJNCpU6eosaRM2l1BEEaMsd1asmQJt1uoYwRhOFBOIOscPnyYKqobqaK2k1bMi6QAf28thjCZ0d0M1TV10qN3LKGYKLMMUq++1zS0U1NLFyu8YINrJB8fE126OpUWzomjGdMi6Nv9JTRdfcISC+JsXptBZdUt7CK0sbmLahs62DURXBEdy6+hR+9cShvXpNHqRUm0aG4cnS1ppKyZ0RQe4k/V9e20eV0GBfj5UESoP/n5eFPemVo6XVTPLpEWZMaym6Senj6qb+6kGzdm0tzpUXgIyi+u53vyNpnoufeK6esDNTRnzhz68Y9/THPnzuVnEiY+xvqqrbaOlcf70lOIfH20GIIgCK7hc+AY+Rw5wf3yhx56yKxEIUw4vvvuOx5P6UtLJgoM0EIFQRDcByx1+xw7RTNnzuTFsVDKFgRBEOwDfRN4zzivii8A2u3g6NGjRPBZ19qGu6P+8DBVuw+YDhYEQZiUdHaRd95p8+ShqgP9/f15wFw3qy0I7gYDbBjEP3fuHDXkn5F2VxAE17Bqt5KSkljpRczuCq6QnJzMZuL37NlDlXUdqlj10aLMcLNLGWHSMy0xjBbOjqVZ6ZEWRZjwUH/Kzoyl5fMTLNvsjChaNCeW0pPD2epKZHgAh0WGBVBibAjNmxlDCbHBNDM1gt0fLcmK5y07M4ZCgnxZcWVmaiSfCzdLIcF+NGd6FMVGBVFsZBBl4fyYYLbmgg3pIX5qUigrymy+MIPCQvzY5dK8GdEUGx3E8WamRVBKfBh19xB98F0Vvf9tBcXExNCDDz7IioDC5MJYX1FTC3l191JfSoKSm2XVrSAIruGdl09wO+zV20cPPPAAuyIWJh4RERG0e/duaqqpIQgD/fHR8OeoHRUEQRg9XvVN5MvWdVvohhtuoGXLlmlHBEEQBHt4jOILWLRoEZvqqquro6biElWxN5IXBMfgQKIAfy2WIAjC5MKrpp58jpwkn8Mn2OoVVhPecsstbFJbEMYSmOeF6yNMNhUdUh0paXcFQXAC63YLCuw33XQTrVmzRoshCM4za9YsamxspBMnTtCp4lbq6+unlLhACg4Uyy+TnQB/H4qJDLQovYBALcy4hQT5UXREICuuAMTHd1hrgSIL4nibvCgqPGDQeVCQCQrw5biGS1jOR7q+2vlQZNHBPsKmp0RQUlyI5br6tUxaYj7eJiqp6qLt+2vpna8rOAwTmOLubfJirK9g6Yz6+6gvMkwVDj8thiAIgn3Q3/Y5eop8cvPIq72Trr32Wrrtttt4LFyYeAQGBvInFvH2VKs2Qb1HVogUBEFwB51d5LvzIHkXltDixYt5riAsTMmdgiAIgkM8SvEFwLRjeHg4dXZ2UvmZM+RVWUNebR1E/v7UD61pHzElKwjCJKGvj0wV1eRz8Ch5nzzLCgfz5s1jDW5RehHGi9TUVMrIyKD+/n6qKyml9sJz0u4KgmAbq3bLt5/owgsvpJtvvpnWrl2rRRIE14Hr2z5Vvk6ePElHC5qoraOX4qL8KTJMVs0Knkl3Tz99d7CW3txeTjty6yg6OpoVAFEfCpMbY33lVVZJ1NVN/aEhREHmCVBBEARbmIrLWGmclcd7+2jLli101113WZQnhIlJYmIiVVdXU8GpU+TV0EwUEkj90eL2VRCE0eOdm0feqs3ISE9n5XooYAuCIAjD43GKLwATcCkpKRTgH0AlRUXUXVbJ5rxg2ssL94IVVrISXRCEiUpLK5kqa8l09hz5HC8g76JS8vPxoY0bN/KKnw0bNmgRBWF8gMLpnDlzeOVAXXU11Z8qkHZXEIQBbLRbCXFxtHnzZp7onTt3rhZREEYG/JRD+Rcd05qaGsrJK6eG5m4KD/GhhGjxYS54FmXVHfTlvhp6e3s5FZS28SA06kKswhQmP9b1VcuZQvJqb4e5IuoPC9ViCYIgaMA9KGRoKI4Xl7FLPChJos1AP1yY2KBNgPJLfn4+1ZSVk6m2gfpjIs0KkYIgCCPEVFBEvntzeZHsfffdRxdccIF2RBAEQRgOj1R8AegIYBA9JCSE6uvrqa2iivrLq8hU12h2xaA6Dl496r5gDhITct5iFlIQBA9G1aVwDeFdUkneJwvIO7+IvAvOkUnVZ1ghqrs2yszM1E4QhPEFAzaYuEH729HRQX0NTdRaUCjtriBMVey0W37Nrawoh0neq6++muLi4rQTBGF0oFMK659QwmxoaKADR4qosraT/HxNMDZEIUE+7M5GEM4X5yrb6UhBM328o5I+21NNTW1Ey5cv5wnMSy+9VIslTAWs66vqk6fJq6mF+n28ifpVBH9/JTNLfSUIUxkvKI6X1ygZupCtvJhq62nGjBk89gM5Gv1vYXIQGRnJLsuPHDlCrbV15KX6S31J8aotEDd4giC4jqm0knx2HiSTki0vu+wybjcgewqCIAjOoSu+ePXDx4ENMPkFt0Pnkx07dlBxcTHl5eXRsWPH2KdyX1Ag9UeF84oauGLoD1DCJFwy+PpRv78Pf9KQcQYv6lf/BoINEWzEBYiv46VHciKuHqa5/7aJJbYlzkBk69OGxgWDYxmTsbxNY6AR49chcXUMAdbxh8QFWuBo4gKb8RXWmWk3bY1B8YeJ7OhFWWOJat5xrowA6/jm77YvbTsuo+0OOU0lNORnbJW48ZtVzCFxjeDQoKQdxOWLWCduiW51nv51UNrap3VcgCDEHXLITtxh0SI5E9fRMxvp6yOvji5UnuyzWVWg/IlBD0wgshJBUzP5+PhQUlISzZ8/n81lY/JQEDyF06dP09mzZ+nw4cNUUFBAhYWF1OHj7WK7a6fNHfJTMscz7w0fx4w5gq2fpSWW5ZgWl/+asRdHR//mMJ62iw+uHw2HzBgiAD2xQfGs4gBn0xoSR8OYKfbiDco4B4khXqeqz6AArQRGmwN3llMHvyN+l0OSNQdYt21D36MxnnZw8IeFgStqGBKz7KmwQe3j0AsOxV4cBBsvytGs4tqMA2zEG4KdtBzFtXnMgPFZkA/Wz+ZkuwWlOFhlnD59Oi1ZsoQnewVhrDh48CC9/vrrtHfvXkqODaDUxCCamx5C05ODKDUhiGIjbdRHgjAGtLT30tnSVjpT2kbHzzZTYXk7FZW38eruVatW8WA0ZHlh6mKsr/oilJwcFUH98bHUhxX/kJ1DgrWYgiBMeiBX1zbwAidTaYV5X8nS1N1Ny5Yto2uuuUbcg05iPvnkE/qv//ov8yLiOTOoZ14m9SfEaEcFQRCGxzsvn7xPnWHll5kzZ9K//uu/UkJCgnZUEARBcAY/Pz92J+rRii86MBt49OhRVnzZuXMnT8TBGg38K/dj5bllAk59Yt/G5IGt8X4zWqDVMZvzFjpWCdma+LJ8tXFRmxmu4WWdtvZpEy2qccLQ8jptP+zg8OHiAuv4DuNqn+YbMXwHVudZx9V2zVjHtfqO6FZBgxgUf5jIjp7HGktU886QiT7zjg2s45u/27607biMtjvkNJWQKL4YsBE0FC2SM3EdPbORQROIHepTm0BUnzgWGhrK1qyg8ALFF6wUxGSiIHgiMN+OthdKMFA+xX5bWxtvPfgxOmp31a7t5kILMITrVcDQqAMhXAdZReCvVhfQ07LG2K5yXWnrN60F6XW5pQ62Gdcchr920wN6uF6JOrgu73Ba2teBHTP8dbg4hu+4pNVhZtA92IukQDzIgLD0gxXMWL1sjeVUUXyxYDMOsBFvCHbSchTX5jEDxmexVVaHabewMhUDLnDrAKWXtLQ0Cg6WSTxh7Dl+/Di99dZb3OdDOxQU4E3T4gMoLTGIFswIpcTYAAoN8qGwYF92iSQII6W3r59a23vV1kNtHfg077eq/TMlbVSgKb60tPXQtGnTKD09ndasWcOTmLDcKAjW9VW/ry/1RYZRf3QEr/pnxfEAJTPDdWigWHkQhAlPdw9RVzd5dXWprVvta59NLWTSrZU3NlNERAS3GampqezaGvK0MLl56aWX6MMPP6SqqirqTU2i3gWzqS8teWgfTBAEwQAsB7Jr6Zw88mpt43GYu+++W1wcCYIgjAB/f3+2rjghFF+MQPHlzJkzFsWXlpYWqq2tZaUY7GPTMT4aJr6M3+08tiV8yESZAXvnAlvHHMW3xl5cV6+pM9prG8Os81BnNNfA9yHKPg7Ss44/2rgIg0Y+Pr1V1F4VBefAKsdIcHQ/jhjJecZzXMlDe9g7B2mP9LmssU7H2XcJ3HkfY4VedvQKFi7bsME1RHx8PGVlZbHyiyBMJKD0AkswUHppbW21KMBga29v5zAj+J3a+r0O9x0M9xs3HnclLsB36/uyFccWjs6xZiRp4PtweWYvjo6tcEfpGTGGQ76Cq0m0jeG+3tTY3ctmAuGH3tg2Gs+xd1/OXA8Yv2PfmfJjjXUatnAmTWfiAHvnOnPv9s414mxaRpyJawzDew0KCuINCi3QiMcnvmNlEdoruEGTVUbC+eDcuXM8iXzo0CHu+xUVFXF/LyHan5Kg+BLsQ+HBvhQd7sdKMKHBqp4KgSLmAHpx5w9D2bfsqR3zMbUpkdQS3+ZvR/s0fzB6vEGxjfH4uPodY1/9HUgf9aYeh4PMaWmBrPxn/j8I/XzjQT1o4JgZ8/d+UlU49akOjsmkZFTNE4v1uUA/36J4aIhoTFsP1o6ozVY9pe0oeFf90Z/JmM9AC+JPcxT+Y/5uwHh/ULA0fzcHWl3eHKr+WJ7F/IW/WYKwq/Z7Vd60QNFFU3ZpbevVvvdSZV0n14uweAXFv8WLF7MSIDZBMGKvvuoPC6H+8DCz4kugP/UHB7EysVkJxkqpWC+bXFCNaAHGcJvxFMYfg704wPpHYwun4miflh3tx2V9YZvxHMcZoowOrE5BgGUBEtDu2TqaIYYljs7AN9tpGdGDUFUz1uOlQ0+xj+62QE/Lcq4hEX13SBwdBxe0lZ4tnIk35JAWgA/ODMN3CwNhLM/ajAMGx8OO3aLHccyfRmyVET3LrDHeh620GKtyNCSt7m717q0UX9R31YCwi2C0F5i0NCqOQwlGmBp89NFH9PXXX9OBAweoLzaKeudlUl96srn+FwRBsMJUXUveh0+S6UwxtymwrnvVVVfRhRdeqMUQBEEQXGHCKr5Y09zczIov8K+M/ZEqvlh/d3ayAWGuTkzoOIozkmMIN3cWHccZDltxjGkDR+noce2lY8Q6XeBM2jqjjfvVV1/x6qwAFe2S+GD6trqNmnr62E/runXrKCoqSovpHI7uxxEjOc94jit5aA9759h7lyPBOh1n3yVw532MFbhHTAyjctUVX2DpBQovGDgXhMkAZAOjEsxYKr44m5YRZ+I6m56jeNh3VIfZStNeHD0tR2nYi6NjK9xRekb0cMhQX375JU/aBFEfXZkUSh+VNVNrvxelpKTQxRdfbGkXjWlZ35er19WxFc/ZtICtuM6Wn+HiWKdlLw1nrmfvXCPOpmXEmbjGMF3xBcouusIL2i18wpWH+JIWPAFMHqNOwoZJZcjtqKvQ9kBBz9vbi8Jg/SXEhyI0xRdLKVc7A/sDU2NDjuOPqs71n4ft3472af7gHT1FG9G1MPzB79i8rweZQ82fDIfpoWpfS9CSrhaZv2p/jNccCDejf0ea3b39BsUXPX3+MJ4ycE3+qzAcNB/CH/UsWoDh8KB7Aea0zDdtjs//zX9U8EB883MMrlv5wxxfR33Rr8jxzUGMOT7+GJ9t4LqGD94xHzHH5W+Wg2SpD/EJuT0sLIxleCiwY/JSLDUKwzFcfdVvMhEF6Iov1tZfjGUTaIXTUEbNDC7Dxg8bkQfjKN6QIDtpGYOHpGd1Xzo24zmOMyEUX2Ahz1X0ZNlipkJPy3I5w3X13SFxdLQAh/Gs4tjF2XiKQXmDi1qdxF8HwpCvg94jsHwdHA/fbRzSsHpHWoTBr8r8ZSCednDwh8JGWgMHGf2rMZbxYpCT9TZD36AwjnYDn+g7CVOTY8eO0TvvvEPffPMN9QT6U19GKvXOSKW+6AhuAwRBEGAZzKuukXzyTpOpsIT7HbAqefXVV8uCWUEQhFEwoVwdCcJYsGPHDvrTn/5EFSXn6IrEULp5Whh9WN7Ck3z9gcGsYXvDDTewEowgCIIgTGYwMQPTzG+++Sb1Njey0stViSGD2sUrr7ySbrzxRmkXBUEYd2DpExYVMKGMxQ6YSMYnLI/pFsjwqQNlClvYCh/vuEas4zg6x5W4WBgCi23It4DwYOpoNCupQoEDim22sJW+PlTgyrV1XDlnuGO4D2fSczWuyWTiiUujpUZ9AhOWzmDtBSuGBMEVXK2vgK0y6ghH8V1Ja7i445GWrd+sNY6Oj8c9WlNSUsKWfmIzHSg3ICnjaKv2vfpUCStFwBKIPYZ7XuMw7nBxR8pw57qS9kji2mt/rHF03HhsuHLm7HXQJugKL/jUN3yfPXs2fwoC6ggov+zatYsqq6upNyGG+mKjqS8lgfqjI6k/RMqJIEw5unvIVN/ACi+mkgryqm0gU00du8XbvHkzrV+/nuLi4rTIgiAIwkgQxRdhSrN3715WejlTUECXJYTQ1tQIivE3u3TQJ/n6AoLommuuYeUXMU0qCIIgTFYw+fL+++/TW2+9RT1NDRalF93Vkd4u9voH0pYtW1j5BROCgiAI5xNMHmPDpLL+qWNvAstW+Eji2jsHODoGHKVrjStxAY4dP36cPvnkE1Z8CYwJo8zLllL+lznUVFbL7hcuueQSWrZsmXbG0PSGS9/IWMU1gmO2JixtneNqXF3xBQMj2BeEscJRfQVslVFHOIrvSlrDxbU+rn8fTokAuHIf1jg619V03ZWWMS7q2HfffZeyrl5NsXNsK79YWzrB96pT5yjvvV2sTA6ZWsfTn9cW7kzLiB5XH6oezX0Yjw1XZp29DhQl0W6IZURhOGCZHgsut2/fzi7watX3/thI6o+Oot7UJPUZwda/+mEBapjyJwjCBKO3j13iUZfZNR61dZCpqpZMlTXkVddAXs2tvBgBSvYbN26ktWvXskVeQRAEYXSI4oswZcnJyWGllxMnTtC62CC6Mz2SEgN8tKM0aJKvxy+Arr32WrrpppvY7JwgCIIgTCZ0pZc33niD+lqaBim96Fgrv6BdhFKoKL8IgiB4FujnvP7667Rnzx6KSI2jzE3LKG3VXDq37yQrv9ScLqV58+ZxHb5q1SqewBMEQRBc429/+xs988wzNPfKlTT/+rVa6PDkfbCLjr27k26//Xb60Y9+pIUKgjBZ6e3tZddHsAIGGQ0KMNj6oiKoPybSrPjiDxd4vpipoX61kf8wSlX6LI6uK2NzVkfH6qC9uE6lZYXt6SRzWq6kA+yl5SruSgcMSco6wKisNPS6Xm3t2p4N7CTVHwgX+cM8wzD3ZXTjNsTNnDUOD/cPSmsIhrwe5ioKcwyb6Q3zzoYeHXlaRoxRbeqdDUnKQdrGQ329ZmWXzi7e9H1qbyev2kYK8PZmCy+w+rZ48WK2xgn3eIIgCIJ7EMUXYUpy9OhR+vOf/0yHDx+m1dFBdFd6BE0LGtqpwCTfB2Ut9HF5M3X7+tP1119PN998M5u/FgRBEITJAFYcv/feezxJ2t/azG7/rk4arPSiY2wXoRR63XXXsVJoaGioFkMQBEE4n8Cc/muvvcb9nJhZKWzpJXnJTO0oUWVeMeV/eZDKDhVQamoq+5CHSe2YmBgthiAIguAMUBh/6qmnaPblyyn7pnVa6PAc/3A3HX1nB23dupXuvfdeLVQQhKlAYWEhK8AcPHiQ9ysqKszu7zo6zFZf/P2oX21QgHGMPo1jTynBMM3jYK7ejKO0rE4e17QcMOTcUSQ26FR3pQP6yavVgeKLHfqDA524DasIVtN61paunMbWMxg1Qmwc13FwSMMcYEnPeHyYexx6VEvLUxVfejXFl54e/gqLkrob1WnTprFLPCxCgKWXhIQEjiMIgiC4D1F8EaYcp06dYqWX/fv307LIQLo7I4Iygu13KIyTfF0+fuzaAcovMGsqCIIgCBMZyHnwOw6lF2prcaj0oiNKoYIgCJ4H6nNd6QX9nYQF6TR703KKm5uqxRigobiKTn9xkEoPnqawoFBWfLnqqqt45aEgCILgHG+//TY9/vjjlLlxKS28dYMWOjx5H+ymY+/uoFtvvZXuu+8+LVQQhKlEbW0tK8CUl5dTS0sLNTU1sQIMXODhE5swsamsrOQtJtO2KzwAXQtMyOmfNadKKD4+njdh4gI3eJg3gqILJl4xVoYN32HlBRZesC8IgiCMDaL4Ikwp0Kl49tlnaefOnbQoIoAtvWSG+mtH7WOc5Ov09uXV7RikwI9HEARBECYikO/eeustniQ1dbQ5pfSiY0sp9JZbbpHOuyAIwnmgsbGRtm/fTu+++y6dO3eOUpZl0uxNyyhqeqIWYyhttc10dscRKvz+GPU0d9Dq1atZkXHBggVaDEEQBMERqHMfe+wxmnXJYlq09WItdHh0iy9QHH/ggQe0UEEQpjLd3d2sAKMrv2ATJjafffYZbdu2jbKuWU2x9pRfYGYEU3Lqs/rkOcp7fxdt2rSJLrvsMi2CMBHBhKuu+IJPzB/B6osgCIIwPojiizBlKCkpYaWXb775huaF+dPdGZGUpT6dxTjJ12Hy4UGK2267TXziC4IgCBOOrq4uevPNN+nVV18ln64Ol5RedEQpVBAE4fwDE/mffPIJffrpp1TXUE/TVs5hpZewpGgthn16Orvo3N6TlL/9EFuBWbp0Kd1www20atUqLYYgCIJgjw8//JB++9vf0syLFtHiH1yihQ7P8Y/20NG3v2fZ+cEHH9RCBUEQhMnECy+8wBsUX+ZtWaOF2ufYeztZ8eWuu+7iTRAEQRCEkaErvojKoTCpqaqqohdffJGVXjJD/GhraoRLSi8Ak4FXJYXw5GBAXw+vkP/b3/7Gk4eCIAiCMFHAajJYennllVcsSi9o31xRegHGdtG/t5vdJaFtFIVpQRCE8aGwsJDrcrjbaOpooVmXLqH5117glNIL8PH3o4wLF1DW1aspbs40OnDgAD3//PP05ZdfykpjQRCEYfD2NsvOfX19/OksXljhr3D1PEEQBEEQBEEQBME5RPFFmLTU19ez0svnn39OGcF+tDUtghZFjsxKS4Rhki+wv5dXymPr6enRYgiCIAiC54L26o033qCXXnqJfLs7LUovaN9GgrFdhFIo2kRRChUEQRh7Tpw4QX/961/Z2otXkA/NvWoVzblyJQVGhmgxnCd5yUzK2rKGkpfOotOnT9Nf/vIXduFRWVmpxRAEQRCssSi+9LqowGLWeyE7hrcFQRAEQRAEQRCEEaIvNBDFF2FSAv+omNz76KOPKCXIl7amhtPyqNG5YDBO8gVRH6ePib7e3l4thiAIgiB4HminYJEFyqB+PV2jVnrRsW4XYX0A7SIsywiCIAjuJycnh5Vevv76awpJjKK5V69may++gX5aDNeJzUyhedeuoYx1C6i2qZ6teKGfU1BQoMUQBEEQjJhM5qHUflcVXzR9F1F8EQRBEARBEARBGBtE8UWYdGC1OQZr33nnHUoI8GGllzUxQdrR0WGc5AtRvx4MPGOiT0zVCoIgCJ4I2icoo6C9gmUWdym96IhSqCAIwviwe/dueuGFF/gzemYSZV2zmtIvmKcdHR3hSTE0b8samr15OfUH+dDHH3/M7UZubq4WQxAEQdDRLb70i6sjQRAEQRAEQRAEj0BfYCCKL8KkAgUbk25YqRjt500Lwv3582hjx6BtJOjnlrR1U0awL81XaUP5BQPQL7/8shZLEARBEDwDtIlQzkQ7BaUUdyu96FgrhcKyjCiFCoIguIfOzk628PL888/T4cOHKWF+Os27ZjWlLJ2lxXAPAeHBbD0m6+pVFJmRQN999x23Hzt27JD6XBAEwYCPjw9/9ve5aLlFXB0JgiAIgiAIgiCMKaL4IkwqMIDwt1df4X0spqnq7KVXihuHbMdcVH5BfOP5H5U3U0tPH18DA8EvvfhXGbwQBEEQPAoon2CiFMooUNaE0mZpWze3adbbSDjW1GnZStt7BimF4rq4viAIgjByGhsb6dNPP6W//OUvdOrUKYqZlUxxc1PJ29eHak6VDNlcpeZ06aCt7mwFBUeHUdycaXytQ4cOcX2+bds2ampq0s4SBEGY2ugWX/pcdHUkFl8EQRAEQRAEQRDGFlF8ESYV8LWcvSCbFixYQImZWdQ3bdaQLbehg3LU5gqHVHycZ53WtNlZfK1stemDGIIgCIJwvoEy5l+ff54H1tE8QVkTSpsvFzfa3FxVfkH8V4oaBm1GpVBc/8W/viBKoYIgCKMAdSgsS547d46/m3y8qeJoIR17f5fNDcorzgJFmbz3dg7ZkA4UYHAtUFBQwJZfZKJWEATBDMadQL+Lii8sJCtEPhYEQRAEQRAEQRgbvFSHy2aPq6Ojg80qC8JE4+DBg9reUI4ePcqrFm+dFk53pEdoocPzMib1ihvprrvuYkUXWyxZskTbEwRBEITzz9/94hfU3durfbPPkSNH6LbUcPpBmuvtor02Efj5eNP/+8/fat8EQRCEkfCzn/1M23MM6vJ5W9ZQ1jWrtRDHHIOiy/u7HNbjRn7/+99re86Tm5tLe/bs0b4Nxc/Pj2JjYyksLIxSUlIoISGBAgMDtaOCIAieyb59++gf/uEfKHFBBq199HotdHhObdtPua9/Q5s3b6a///u/10IFQRCEyQQUxrFBJodsPhy6TI45B2yCIAiCIIwMjDFhTEkUX4QpxYsvvsimwm+eFk53uaD48lJRA72qKb6IECoIgiBMBBwpguocO3aM28WbVLt49wjbRUeTpqIUKgiCMDqcqcuh9IIBdlcUXzDAjoH24epxnZHU588++yz9x3/8h/ZtKP7+/hQfH08RERGUmppKM2fOpLVr19KcOXMsrkQEQRA8jZycHPrlL39J8fPSaN0vbtRCh+fUZwco97WvadOmTaw4IwiCIEw+RPFFEARBEM4PuuKLuDoSphQWk7RiWlYQBEGY5GCScrjNx8eH4/b0udYuGptRW+nqmyAIgjA6bNWt1puOK30cY1xbaVpvYwEW2hQXF9Phw4fpww8/pGeeeYaeeOIJOnToEPU6YbFMEAThfKAr5vX3uiY/6+6xZTxKEARBEARBEARhbBDFF2FKoSu+uOqhXsYlBEEQhMmIRfHF1YbOPG4vCIIgeBD6pKozuBLXXURHR9Py5ctp9erVrEyTnJzMK3J02tra6KuvvmJLZGVlZVqoIAiCZ6ErvvT1uTiypFW7ovgiCIIgCIIgCIIwNojiizClsCi+uDq/dx4GhgVBEARhrBlQfOEPp5HhekEQBMFVMjIy6Mc//jE98sgjvD344IN055130vz587UYZr7//nvat2+f65PKgiAI44DFknCva3WUWHwRBEEQBEEQBEEYG/T+lii+CFMKywAF/3WefpniEwRBECYhI3d1JO2iIAiC4BphYWGUnZ3N1l5g9eWGG26ghx56iJVfEhMTtVhmF0hwd9TR0aGFCIIgeA4WV0cuKufp40qi1CcIgiAIgiAIgjA2iOKLMKWwKL64OGEn03uCIAjCZERXfOl1tV2UhlEQBMHjcKWP4ykKjIGBgXTBBRewQoyRiooKdn2k097eTmfPnmVrMO+99x4988wzvL3wwgv0+eef05kzZ6inp0eLbZ+GhgbKyckZlAY2fN+9ezdVVlZqMQcDZZxTp07xtXBN/bzXXnuNvv76ayooKKDe3l4ttiAIkxldfnbZ4ovm60gUXwRBEARBEARBEMYGUXwRphS6qaM+3bmyIAiCIExhRurqSDWo2o4gCIIgjI6goCCKi4vTvpnp6uqi7u5u3i8qKqLnn3+ennrqKXr88cfp97//Pf3Xf/2XZXvsscf42EcffUSNjY18jjVQioHCy1/+8hd64oknhqSB7whHHGuKi4vpzTffpCeffJKvZTzvd7/7Hf3hD3/ga0M5RhCEyY9lQZXrPrT5QywnCoIgCIIgCIIguBe9nyWKL8KUwqL44upAg4xLCIIgCJOQAcUX1xo6l9tRQRAEYczR+zrO4ErcsQZKKa2trdo3M/7+/uTr68v7sLTy9NNP0wcffEC5ublUXl7O4QDKJvn5+fThhx+yYsr27dtZacYIBj+OHj3Kii2w1rJjx45BaQB8379/P5WWlmohZmAB5pVXXqE//vGPtG3bNr6WUcEFFmTy8vLo5MmTFkUdQRAmN7rii6uWW/RqVyy+CIIgCIIgCIIgjA2i+CJMKSwDFPxXEARBEKY2A66O+MNpRO9FEARBcBew6HLixAntm5mUlBQKDg7mfSjGoB8Hd0hXX3013XHHHXTnnXfS7bffThs2bKDw8HCOB8ssL730En8aaWlpYcUYKLzoSiuLFi2iW265hdPBdv3119OKFSv4mA4mp/fs2cNukGpqajgsNTWV70E/79Zbb6WLLrqIAgIC+LggCJMfb29v/nTV1ZGu+SIWXwRBEARBEARBEMYGUXwRphQWk7QuDjT0i8kXQRAEYRIyUldH0ioKgiAIroI+GBRPsLW3t1NFRQUrlsCiSkFBgRaLKDo6mpYtW8ZWX0BISAht3bqVHn74YfrZz35GP//5zy3bT37yE1q7di3HA7C+cuTIEe2bGVht+fbbb7VvxG6VfvCDH9Cjjz5qSQfpPvLII6xco9PR0cFWYGDVRWfTpk1D7uGnP/0pXXbZZZb7FQRhcqPLz32uKr5oiMUXQRAEQRAEQRCEsUEUX4QphVh8EQRBEIQB9BWrPX0uqrJ4jocMQRAEQcMV5f7zYXEAll3gauiZZ57hDe6DHn/8cfroo48sllj8/Pxo48aNrPii991mzpxJ9913H61bt46Sk5MpMDCQLazAIszcuXPpggsu4Hg6sPgCKzE6cKME5RcdpBsWFkahoaGcDjYowyxfvpyWLl2qxSJ2XVRfX699M4NrR0ZGWs5DOnPmzBHFF0GYQlgsvoxQgUUsvgiCIAiCIAiCIIwNovgiTCksii8ujjPIuIQgCIIwGfH19eXPHhcbOmkXBUEQPA8vzY2GM7gS112cOXOGnnvuOXryySdZ6eW1115jiyq60guUSC655BJ2QRQTE8NhIDExkY/BSkxpaSkdPXqULbhAYebZZ5+l3bt3azHNtLW1UW9vr/aNWEEGCjM6sDQDKzPvvvsuHTt2jF0h6ej9RYA2EkouRrZt28bulPbu3UtVVVUWyw3Iz/ORp4IgjD+WcSUXFV/0OkIUXwRBEARBEARBEMYGUXwRphQDii8uDjTIIKYgCIIwCRlwdeSq4osM2AuCIAjuAUotS5Ysodtvv53uv/9+yszMHKREAostO3fuZGsxUJiB4sxjjz1Gv//97+k///M/6f3339di2gbWXNavX8/WZHS+/vprtjbzxBNPsPWZr776impra7WjZmDBZcWKFZSQkKCFEJ08eZKefvpp+sMf/sD3AuWZs2fPDlK0EQRhcmOx+OKiqyO9XhNXR4IgCIIgCIIgCGODKL4IgiAIgiAIgiAIgiAIgiAIgiAIgiAIgiAIExJRfBGmFBbTsvxXEARBEKY2usUXFxesSjsqCILggbhijet8WO6C5ZRNmzbRVVddxds111zDVl5+/OMf08MPP0w//OEPafbs2YPcDcEN0SeffGKxsPLmm2+ydZby8nJuw5YuXUrZ2dlabNuEhobSli1b6NJLL6WoqCgt1OzyCGn96U9/4vSff/55dsekA6sOa9asoZtvvpkyMjK0ULMrJbhoevXVV/m8p556ivbs2UM9PT1aDEEQJjO6/Nzf62I9qhmyEsuJgiAIgiAIgiAIY4MovghTigFXR/zhNDIwIQiCIExGRurqyDJyLwiCIAhOMmPGDHrggQfo0Ucf5e1nP/sZ/eIXv6B77rmHFUygoGIEfbCcnBx67rnn6NChQ9TZ2clukG699Va67777OK1HHnmEbrzxRu0M22DxA86DGyVc65JLLhmkyAKOHz9OL774Irsuam5u1kKJFWVuuukmevDBB1lRB0o2gYGB2lGz8swHH3zAyi9FRUVaqCAIkxmLq6MRuiwSV0eCIAiCIAiCIAjuRTd8IYovwv+fvfcAjOO6zrbP9oLeCwH23nuRRFKURIlU75ItyXL77Th2ZCeOEyefkzj5kjhfXOIeyZZsFatYXZRENYoSRYlNLGLvHQDR+wKLrf99z8wsdpcAuAsSIAich7yYmdvm3juzsztz3zlnSBHxqcx/BUEQBGFo01vhS0hsvgiCIAhJ4nA4qKioiIYNG8ahuLiY3G53jIWXaCB0Wb9+PR0/fpy3s7KyWPTy13/91/Tggw+yEGXhwoVc57nAPiB++cIXvkAPPfQQC1k+97nP0cyZM/Uc2v5gXcbYn0Fubi5bqIFY5y//8i/ZMs2yZcsoPT1dz0FsAWbLli0UDAb1GEEQBiudwpfeCcdF+CIIgiAIgiAIgtA3iPBFGFIYD1WTteAi03uCIAjCYCQifEnywb0YQhMEQRD6Gp/Pxy6NDAoKCmj+/PkxghPkOXDggL7VNdH3fjabjQUwN910E333u99lyzHYNigrK4vZp1EWL1BAYLN06VIWzUA8c+WVV3KawalTp8TdkSAMASKWhJP0Faq/h5X08yhBEARBEARBEAQhMUT4IgwpIg8o+K8gCIIgDG0wAQgCST5/D4skVBAEQehjMDkcbRmhsbExRlwC0cvOnTvpvffe4+3uqK6upg0bNlBDQ0NMfSkpKTR58mQqKSnRYzTsdjsvYQHmk08+YTFMtKAFotHRo0fT2LFj9RgNxHdnvUYQhMFD5IWqZC23GBaIxeKLIAiCIAiCIAhCnyBPZYQhRUT4kuQbNvJCjiAIgjAY6a2rI8NUuyAIgiD0FRBnwr2RQWVlJT377LP06KOP0mOPPcbL3//+93Ts2DE9R9eg3K9//Wv63e9+R08//TS98847LJZZvXo1Pf7447R//349J9GYMWPYDRPwer30+uuv08MPP8z7Qn6UQ/lnnnmGPvzwQ84HYIUGZQ0XKIIgDF5gAQrPlpK13GK43haLL4IgCIIgCIIgCBcW4z5LhC/CkCLyZk6SE3byWEIQBEEYjPTW1ZG8pyoIgiD0NQ6Hg+bOnRvj2mj9+vX0i1/8gn7yk5/Qr371KyovL6dFixbpqV2Dhx87duxgkcvPf/5zLo+AdcQZro0KCwvp7rvvptLSUt4Gra2t9NJLL0XyG2Wx7+3bt3MeWIhZtmwZt1UsvgjC0MAQuSXj7siwmCjCF0EQBEEQBEEQhL5BnsoIQwrjDZtkLb4IgiAIwmCktxZf5IG9IAiC0NdgYhmilltvvTVihcUAYpNZs2bRl770JVqyZIke2zXIa4hZ2tra6Pjx43T06FE6ffo0x0FYM3/+fPrCF75AK1asIJfLxfEQsWRmZka2kR/lUB71oN4JEybQ7bffTg888AAVFxdzPkEQBj+Rl6qSEL5EnkeJqyNBEARBEARBEIQ+wfJDhb4eA3xYB4NBfUsQBgd4I/D999+nIpeNluWn6LHnZnujlw40d9DMmTM5CIIgCMJgAA/e4fYBros+NzxDi0yAzfXtdLTVJ9+LgiAIA4CdO3dyyJtQSvkTO62V9ETNwdMqlPXpdRzPFLKzs1mgggCLKBMnToyILhMhJSWFXQjl5eVRUVERjRw5kiZNmkSXXXYZ3XHHHbR06VIWoCCfsZ958+bRqFGjIhPTENDk5uay+AVlUce4ceNo8uTJ3CYIZ26++Wa22gKhiwHKw+oMBC3IP3r0aBo7diyLXWbPnk0LFy6k66+/nsuOGDFCrL0IwhDiz3/+M/n9fpp4/XwyWxNzcdZUVkPl24/w9eiGG27QYwVBEITBRLK/y/vjN7kgCIIgDAXw7Acus03hbl7ZhT/rjo4OfUsQBgdbtmyh73//+zQ7y0X/d2q+HntuHj3eQK+UNdODDz7IQRAEQRAGA5iUvPbaa9kB4OuLRyTsCPCXh+voncpW+V4UBEEYADzxxBMcJt+8iKbccpke2zN7X9tA+1ZtvGSu43hsASsrjY2NLJyBQAWilGTAdx6eczQ1NXF9eCCSkZHB9RiWGLoCIlE8G2lubuaJbuRFOViCMdydCIIwtIAlKlwTbv3Vt8jmTuxadGrTftr8+9Usnvvf//1fPVYQBEEYTCT7u/xS+00uCIIgCAMVvBSF5zTySpIwpDAeaCbroEE8OgiCIAiDEUzYIeBrLpjEd50YaBcEQRD6E9zHwaoLXB4VFBQkLXoBEMykpqZyHSUlJVyP0+nsUfQCYMkFD0+QH+VQHvWI6EUQhi7G5z+cjNsi/Vojro4EQRAEQRAEQRD6BhG+CEMKw/x0MEkli+heBEEQhMEIJvsMlxOBJL4buzEYKAiCIAiCIAiDHkP4EgomI2LRfj/L72hBEARBEARBEIS+QVwdCUOKzz77jP7mb/6GpmU46L+mF+qx5+Z3xxrotXJxdSQIgiAMPm666SbyeDz050XDKdWamLOjnx2spferPfK9KAiXIHAXg9De3s5LuH8RLm1Wr15Nb731FptUL5wyUo/tmcq9J9is+sqVK+n666/XY4VLFVikcbvdvIQVm95YxBEEIXHuvfdeqq6upht//DVyZafpsT1zassB2vzImzR69Gh69NFH9VhBEARhMCGujgRBEATh4oDnIGzVV4QvwlBi586d9Nd//dc0JcNJ/z29QI89N787Wk+vVbTIj1BBEARh0HHbbbdRU1MTPb2wlDJtiRkD/NmhOnq/qlW+FwXhEuD06dN05MgRFrngHg+f95aWFha8Ifj9fj2ncKlSUVHBoWDKCD0mMar2nqTi4mIOwqUN3EDB/RLELwhpaWm8RPzw4cM5nMulkyAIiXP//ffzdff6//dVSsnN0GN75vSWg7TpkTdo1KhR9Nhjj+mxgiAIwmBChC+CIAiCcHEQ4YswJNm9ezd9+9vfpknpDvrJjCQsvojwRRAEQRik3HXXXVRXV0dPLiihHLtmtv1c/ORgHX1QLcIXQRioQNxSVlbGgpd9+/bR3r17qbW1lYUuwWCQ89htZnI5LJSeaqVUl+byTLh0qWno+d4dmgfjzt/QP2A7L0ssgwwG2rxBFQLU3hGidrVutqjPdWoqpaen05gxY2j27Nk0YsQIKi0t5ThBEM4P/P6FsHTlj75CqfmZemzPlG09RBv/93X+LP7xj3/UYwVBEITBhAhfBEEQBOHiIMIXYUiyZ88eeuihh2hiuoN+moTw5ZGj9bRKhC+CIAjCIMQw1f6HecOowJnY5PePD9bSh+LqSBAGHCdOnGDBC37zHjt2jAUvcGk0LN9JORl2cjss5HKqoJaZaTZKUetZGTbKSLHpNQiXKmdqvfpachTlOvU14VKmtS1ALSpAANPaHqBmD0QwQSqv9tKpynZyp6TT2LFjady4cTR9+nS2AFNUVKSXFgQhWb785S/zd+51//4lSi/K1mN7pnzbYdrw21UsQMOkqCAIgjD4EOGLIAiCIFwcRPgiDEnwxuu3vvUtGp9mp/+ZmfiDvt8da6DXypvlR6ggCIIw6HjggQeovLycfjd3GA1L0OrDjw/U0oc1InwRhIHEli1b6N1332XBCybjYMWlpMBJw/JdNHN8OhVkOyjVDesuFkpRaW5nYhaeBEG49IAIxtMepOMVbbTnSDMdPu2h01Xt1OwJsgAGYcWKFTR16lS9hCAIyfDVr36Vv2+v/dcHKaMkV4/tmbJth2jjb1+nkpISevLJJ/VYQRAEYTAhwhdBEARBuDjY7XZyuVxk1rcFYUhgNmunfIiS82/etTxMEARBEC59LBZt8juQzJddcl+jgiD0IbDosmbNGnabsHbtWvK2nKG5kzLp9quK6L6VJfTlm0vpmvl5NG1sOo0qdrNrGxG9CMLgJs1tpcIcBy2alsXXgfuvL6G7rimmOZPSqbnuJK1evZonZdavX6+XEAQhGaxWTSweDoV4mQgm/Qd0KIkygiAIgiAIgiAIQuKI8EUYUhjCl24MHXVLWP0TBEEQhMGI8eA+EEr8uy6JrIIg9CFVVVX0wgsv0O9//3s6ePAgTR2TRvdeO4y+cEMJ3b28mAUw2el2PbcgCEMRCN2mj02n25cV0YM3lPI1AteKbdu20WOPPUarVq2ihoYGPbcgCIlgCMeTEb6QSRO+JPs8ShAEQRAEQRAEQUgMEb4IQ4qIxRd5ziAIgiAIjM1m42UyFl/kgb0gXHyOHDlCTz/9ND311FPU0FBLS2bn0P3Xl9J1i/Jp3PBUspjFNJMgCLGMKUnhawSuFbhmVFScpkceeYSeffZZdtsiCEJiRIQvwcR/E+u6F7H4IgiCIAiCIAiC0EeI8EUYUkQsviRpwUWm9wRBEITBSqerI14khHwvCsLF5fTp0/Tkk0/SG2+8QbkZVrrtyiL60k3Daca4dD2HIAhC9+BagWsGrh3prhC9+OKLLKLDtWWwAZFBR0dHTPD5fCLiFc6LyEtVvbD4IsIXQRAEQRAEQRCEvkGEL8KQwmQ8aAjLG7CCIAiCAHrj6ijyyupFJrh/m74WS2DjO51hy/sU2LaOgod2UrilUc8hCJcuHo+H/vSnP9HHH39Mk0al0j3XDqMv3lhKhTkOPYcgCMK5wTUD1w5cQ3AtWbduHV9bcI251AkEAnTy5EnuEyxj/fGPfzwrPPPMM5xeU1OjlxKExOm0+JK8iEVEV4IgCIIgCIIgCH2DCF+EIUWnq6PkHjTIcwlBEARhsNIbV0fJfo/2FcGtH8aKXPTgf/u5zvDOnynw7vMUeP9lCqx/k4K7txB52/UahCGJ30fh9kt3YhdWXt577z3KSLXS/StLaOVl+eo3roi6BUFIHlw7cA25T11LcE3BtQXXmEsVCApgtebVV1+lhx9+mH7xi1/QT3/6U15Gh5///Of04x//mNcPHTqklx66wAJJe7v8NkoGQzjeG+stInwRBEEQBEEQBEHoG0T4IgwpDIsvYvBFEARBEDQiFl+SeAg/kJ7Xx4hc9BBDwE9hbxuFKk+x9Rf/+y9S4LOPWfwgDBHUCQtrP8Eje9j6j3/D2xQ8uldPvLTYsWMHPfvss2Qxm+iOq4pp9sRMPUUQBKH3zFHXElxTcG3BNQbXmkuNYDBIu3fvpkceeYR++ctfsvhl//797NqoKxCP9ObmZj1maAGhC6zibNiwgZ577jnauXOnniIkQm8svkSeR4nwRRAEQRAEQRAE4YJi3G+J8EUYUnT6YU7uQUNY/RMEQRCEwYghfAkm8VU3YL8X1fe8KTOHTFl5WkhJ47gIEEA01FDgk7coePqwHikMerxtFNi8hgJrX9as/3zwKoVOH9ETLx1glQDuOTBJO2dSJt1+VZGeIgiCcP7gmoJrC64xuNZcSpZQYHVj79699Nvf/pZeeumls9wXpaenU2lpaSRkZWXpKUMTuILauHEjW8WBSOhnP/sZj5+QOMazpXBSrkK1RW+sxAiCIAiCIAiCIAjnRoQvwpCit66OIk8oBEEQBGGQYbg6Skb4Yhqo34t2B1nnLSPrkhu1cMX1ZJt7pSaAiYKtf+zZgpkHPUYYzMCtUXDHxxQqP87WfwaUyaIEOXPmDD311FO0Z88eGj88hT6/YhhbZhD6GZOVHNnTyV28TIWryFW0hGxpo/TEwY/Zlk5Wd2FscBWQyeLQcwiXMrim4NqCawyuNbjm4NpzKXDixAl6/PHHad26dXqMxvjx4+mWW26hL33pS/S1r30tEr7yla/Q3XffTYsWLYoIgIcSsI6zefNmtooDSy8ez6Xr/u9iYVh8SUbEYryBKMIXQRAEQRAEQRCEvkGEL8KQIiJ8ESGLIAiCIDC9cXU0UB/Xm6x2skyeR9bZS7Rw2QqyXnMnWaYsUD8CtAkKBpZfqsooHBB3R8Klwccff0yffPIJFeY46PMrSmjCiFQ9JXkcObNYtGEEV/GVZEsbracKPWFPH0MpI26i1JF3UOooFUbeTu5h15DFkaPnGHxYHNnqnJlJrsLF5C5ZrsKKuHCdOo+u5nR75kS9lHCpgmsLrjG41uCag2vPQKe1tZXeeOMNWrt2rR6jPqt2O82fP59FLn/7t39LX//61+nOO++MhC9/+cv0ve99jx566CEaNWroiNeEC0dvXB0Zv7TF1ZEgCIIgCIIgCELfYPmhQl+PAaZP8RaIIAwm2tra6MUXXyS31US3DUvXY8/Nlvp2OtLqo5kzZ3IQBEEQhMHChg0b6OjRozQ/201jUu16bM98WO2h8vbARf9eDO7aSOH6an2LyGR3knX2YjK5UvQYhdVGJncqBfd+qn7g+vVIhYqzzriMTLbE+hxDMAA1rb7RC/wdFDy+n8LVFWTOTcBdDYQ6NRUUPLybQicOsZueUNlRCp05QeHmRtVfN/f9LNpa1X4OcNlwbSUHk6oLFnBg9SZ0aCeFVLpRX7i+iscD49Ujfp8qc5iCR/dQ6KRqD9qCUH2ayOdV9avfWPqEUDRoB/ZltCVcX0NmHCuTiYLH9lHoqAqnDnN/TRnZeim12e6hcMVx1feDnB46pff/HPs09heqKqfQkT0xx9+UmsF9jWlH/LnQ23G/wLS0tNDvf/97qq2tpesW5dPNSwr1lN6RNvpuchUtJnvWZC1kTqCQv4X8TT27NYG4w+LIVHlb9ZjBCayaWFx5qp/NekwnruJl5Miaqk4g7fNvMlnIbE+jQOtJCrZXcdxgAVZcHNlTyZm/kFwFl5EjdzYLf6wpw+JCCdkzxvF5ZLI4qaNuh17D0KSn8+dSoSTfRdUNHXTgRCuLSpYsWUIOx8C16rNr1y565JFHqK6uTo8hmj17Nn3zm9/ktqempkYsbRhgG+KYwsJCys7u/L6JB5ZQ8BsJ+4CFlO3bt7OFlIqKCnYJBat5brf6LoirH8Cqx6lTp9hqDq7fCHgeAbdL8fmRdvLkyUi+pqYmzme8uIPnc8eOHaOqqqpIHp/Px3m8Xi+7pYLrok2bNtH+/fupoaGBnE4npaSkxOwL3ydGPVu2bIlxZzVu3DjKycmJ1I/yXR13tA37+PTTT3l/GA/0E33DWKBcPO3t7bxfuKAy6ke7kL+6upp27NjB7ff7/ZSfnx/p90AGorDjx49TyexxlFGSq8f2jKemkU5t2s/nzec//3k9VhAEQRhM4HsRIW9CKeVPLNVju6fm4GkVymTOQRAEQRDOE7zciyDCF2FIgQcuL7zwAjktZrq9RIQvgiAIgoCJnMOHD9PcbBeNS1T4UuOhiktF+KIItzZRaNeGWOFDRg5ZZ6m8vXBxENz+EZmy8roVzUBkEzq6t1OcER3gbsfnpcDHqyl4aCeLaBAfDvrJnHn2xAlEH6G9Wyiw42MKbvuIQge2aUKMI3sodGwfhStPUdjTrPru4D5FE6o6TYH3XqAg8h7fz8FoM/oQ2PI+hfZ9qtWH9kKUosbK5EolU2bXFiwgBAns3EDBresotPMT7kPoiFY+fOIAhWoqNSFKejaZnC69lEbws48psPGdSFvCpw+TubCUxTnBT95Sx2ijassuPn6WMVO4DIQuKBfcqdL2bKbggR0UUnm4/9H77GjT9+nmciCyP7WfcGszC1kiYFzLjnW2o2Q0lzc4n3G/0GzdupVeeuklSk+x0pdvGU7Z6b0Qa0XhzF9AFmf0uRYif/Oxs4QvED5A2GBPH0s2FRx5s9itja/xgJ5jkGBSN8YpRaqPY8ieofqZM53XffW79Qyd2NJHkx3WcXThCwj7PdRRt52C3s5J90sdCJwcufMoZdi1ZM+cTGYbhAMQlnVnNdPE6SFfM3lrNutxQ4Qkzp9LiRSXhdZtq6PqmjqaPHkyDR8+XE8ZWED8AXc9a9as0WOIcnNz2cLL0qVLI1Y5kgXPw/bt28eWZFavXk1vv/02L+FKCYKHvXv30oEDB1jwAREDBCOG60gDiDhQBu2DSAQB9WI849uFCbI//OEPkXwQhkyfPp3FOQCikueee47efffdSB6Xy8WiHcTh5Z5XXnmF1yFGOXjwIAuB0C6MhyF+gbjmN7/5DZdH+yFiMTAENEb9aCfKG6DtcIH1+uuv06pVq3hssD+MB9oPgRBELJmZmZSVlRUjuEF//vSnP9GHH34YqX/YsGH8zPGZZ56hl19+md58800WKc2dO/eScD9lCMeHzRpHGaV5emzPtFY3ifBFEARhkCPCF0EQBEG4OOA+G/daA/81CkG4gBhvDkXPeySCmKIVBEEQBivGRE0yro66n/wcgIRCFDy2n8K+Dj1Cw5w/DJ3XtzRgUSSw6T0V3u0xhNtaVebuBeL+NS+S/+1nuwyBd1TY+A6Fz5yicHV5JD64f7teOgq1n8CnH5D/vRcpuHszi1LCqj8RIJqBRRK0ed0qClWe0hM0wt52ClVX8H6MALGH/6PXKbh5DYUbazvrg3UTVX/ws09YlANRRzyhytMUWP8GBda+QqGTBync4e38UYXyahvxgQ9eZVEN2h9NqLkhti2qbSF1bAIfvkahihMU9vu0emBRRyd4YDu3J3TiALePre0YdLXPjnY9MWp/tZVnHa+wpyWmHRirCOc57hcS/AbFRCEsB8yckEFjS2JFXX2J1V1MKSXXUsrIWyh11O3kKricrCkDc/L7fIArH3fxMkodcbPmukitd+f6qaNhD/ka91PI18SWb4LeWvLW7aCAp1zPceljtqaQM/8ySim9jizuQnW5j7/eq898WH2ewuqziBBx3jE0Seb8uZQYNzyVJo5I42sPrkED9X64sbGRRSjRzJo1ixYuXHheohcIM37729/Sww8/zKKaI0eOUEdH5++I8vJyFg4/+eST9Otf/5o++OADfskmGoxZWVkZlzcCtrsaS/QjOh8EydEvomEdcdF5ILqAIAdtfP/999maCkA7YZEFgpI///nPbP3FAAIalEV7IYKJBmKZ6PqR18AYE4hmHn30URZ9GPsDWEcc0iDgOXHihJ6iAYHS7t27Y+o/ffo0C2iefvppFtTAug7yXSpE3GhH/z44B4YYKJkygiAIgiAIgiAIQuKI8EUYUkQeNPBfQRAEQRCMt2oDSXw5hi6FiU6IIjwtFDiwg4I7P4kRTMAtjmXKPDKZoybFkL+9VROivKWFwMdvUajsOIVqzlDo8G7yr3mJ461LbtRc63RDtBUagLzmkjFkyimksPotArEHrL4A68JrOVhGTuDtaMIQa6h2W6YuiOTjMO8qssy4nEzZ+Xq+EFshCWx8ly2V9ARbnVF5KTWDzKWqTelZeoqOGgeITODCKBoIYQIb3mIhSGQsnW6yTJ6rtWfSbN4G6Ftw64cU3LcVszsc1yWqf8gDt0vdEcbEn2oTj+HIiWSZeTlZZl2h+n8ZmQtK1ODqoma/j63YsKskHZNFnduwcGPtwkIKJkSRZoSoCdKA6iMs0LDQBqjzxDx8XLfjDgs3fQUmJuFaw24z07K5iblSuFDAXYs9cxK7ODKZMYaXkOAtCSyOLK2frgK2ctNTPwMtJ8hT9g61lb+nwhpeb6/4cPC4fzJZyJE7h1yFl7PLnmjCIR8FWk9Re+UG1fe1kdB+5iPyNR3UXPtAEDPESOb8uZSwmE109XztmoNrULxIYqBQX18f464H4G1pWBzpDRClwNILXCdBHGKIXWD5ZM6cObR8+XJasGABFRV1uinctm0bCz6w7E+ryRDewMoLLKxcddVVNG/evJh+o+3oQ7QwCGKgkpISDnCTFA3KGmkI0cIhCH8wJh999BHXi7JwIwWrJffeey+vIw5pEOPAyg1cQfUE2g+LOMYYX2oYv59DyRxz/fIwUIVkgiAIgiAIgiAIlzoifBGGFJG3cpJ80CCPJQRBEITBSkT4ksR344B9Xu/vYNc0bJllowofv0WBD15h9zwGcIVjmbOYzCPG6zE6JhNZJs2JdM6UlknWy64j27V3k+26e8l69e1kGT2F8yWMyUzmUZPIevlKsi27lWxLbmThBAst9P3YVn6OA+87inDNGQru+ZRMLjeZsnLIlJ1HlnlXavlX3MvtQvsoJU3LDxHG/u0UOn2Ut7sj3NJE5uHjyXrF9WRVbcLSMnJiTL9gHQduhKKBRRrUH7F84nCRda5qzzV3cnusagkxEUQiIOxto8C2dV1ajokQClKo9gyZUjPIMn2RJgCau1QTtOiY3KlkmTpfH8PbtONx7T1a/5fcROacAj2n2me7h10hGVgw9mqM4P6K7JiQ7sRUNEJLQ1h4TcTNFMY9AGs4qv0MjuG46drx62bcMZ59BSYt8bb+uNIUmjZG26dwcfG3HKe2ig9Y/OKt2kDBjsHj4siWNpJcRUvIbM/QYzQg7PHWbCXP6beo9cQr1HryVRVe08KJl8lz8g1qK1PjUdf5+RMufWZNzKCsdBtfg3AtGojAhc6ZM2f0LY3i4uJeW3tpaWlhKyQQZRiMHDmS7rvvPvrWt75Ff/3Xf00PPfQQfeUrX6Fp06bpOYgtrDz//PPcnv4C+ywtLaVvfOMb9Dd/8zf0V3/1V3TnnXeyayMDuB6C8MUQ5OTn57MbqK9+9asx7QcQ9CDNCMgLWltb2a2RMSZwvwQB0He+8x36+7//e/r+979P3/72t7k8gJAFbotgQaYn4CIJ7brxxhvpgQceoPvvv5+mTJkSeWYz0DHOsXAw+R/FInwRBEEQBEEQBEHoG0T4IgwpIsIX/isIgiAIQsTVUSjxh/AD9YE93N4EPnpds9jyznNsoQSubFhkAqsdEDvoVlNMdqdeqgsggpkwk6wLrmaLKCa7g8zFo8gyZ4kasFgBhUG4sY5d7UB0Y2DOziPrlTeT9fIVZB47la2V2CCgGT8jIjQx3CcFT8ROEAX3bom1PrN+NZFhzcVqI1NquqrvCm6XQbij/SzBSjwQmdiW3qT6dg1ZxkzlJdoHIUs0LBYyLLuocQ3u2hjjLgrWYiCaMUF4otpjzi1iiyjk7hRnhGvPaOPfHTgurhRuAwtaIOq57l4eewPLmCksruExHDmeLb9ADMNiGVjtUe2IJoT9+f28bh43jWxX3U7WRWcfb1jgQRqHpTeTKSuP4zHu0RZ7eLwWX0/m0ZO7Hfe+5LPPPuPl0jm55Hb2biI3WewZE8iZN49sqSNY+BON2ZbKaVqYS1b3MD2lE1i9sGdOZNdI7qIr2fULgqtoqSozn6ypXfu6R12os7P+edwWWCGBRQ1X4RVcjzN/IZntmXoplCsmR84MtlKCfRj7430WLlFpM9kdTTwQeWAftoxx6Jgeq4E+RLcDeQGs38AiSnQat7EbLI5McmRN4bZFj4XWtsWqrtmaO6Fu6HZMkKaOj7NgUewYqzG3pY/lMesNGFuLC5PdUUK4QDt5a7ZQ2+m3qaN+F4WDce5cQgHytxyjtoq1LATqEtUebq9qP45JzDjgvFD9wDmjWUw5m57GIRpYqcHxjs7nyIqd3O/qGBp5rO4itT0/dkzVcbJnTT6rbb05f6Lp789Jb8jJsNOM8ZpVEONaNNCAUCUelyv2+ywZjh8/zlZNDFJSUlhMAmEG3CeNGjWKZs+eTffccw89+OCDVFDQKb6EMARilP5izJgx9OUvf5muvvpqXofFF7QT7YsG7pUMqypoL/pz6623cplopk6dymlGMPoGaz/vvtv52wblYOll0qRJLIJxOBw0ceJEuvbaa/UcRBUVFey+qCcLOCgLazHf/e536R/+4R84wHJNb0VL/U1E+NKTZbs4xNWRIAiCIAiCIAhC3yLCF2FIYQhf5A0bQRAEQdAwJojag8k/uL+UMOUWkvWKlWRdcn2PbooYi5XM+cM0F0eVpyJB/YIguM8xxCqBTe9FrMnAhZD/7edYpGIASyFwkRMNCzZggUQX0BjCluD+bbzNBPwUhKuhcOcxMWXm4IdMTHvCdZVsESaacJVqZ5Rbp3hMw0aqNo3VtzRMw0axoCMadsXk9/F6qKGawrWVvM7ACkpBCYWb6mLaQ752FgkZwP1QqOq0vtU1lhETyAKBUZo2QQuBSvTxYRdRWXlszSVUfpyCBz/TrPp8ulYb/8bYt+vR7nBAa3fSnMe49xWVldq4Tx3df9ZenAWXU+rI21gcYDJpFqEMLM5cTkNIGXEz2bMm6SkaFncRCwVSht9IqaNuV+HO2IBypSvJkT1dDW7s5CbqQp1G/QjOwsvJmTNLxd+kyt/BIWX4DaodmlAJ9aSUrqDUEbeo/EiP3h+2VRtUne5h15AtbTSXMXCoerEPCA9MljhhlC0tph3ICyBGSEXfotIwXmcBEULGeHIXX6P3qau2qTDyVkopuY770ZXoo7sx0fq9UouL6y/Gx5nTKR5LFAheIJoxxRyXEPlajrE7p95atoHoCCKMlOFGe/W+R4/HSLT7Rj53uhJTdTkOXYw7zk+MZ3Q+17Cr9VSNro4h8kCE4uayt0a1zRjTG1mMYrJ2fu57c/4Y9Pfn5HyYPEq79hjXosEMnhFAuHL6dOf31rhx49i6SWpqqh6jAWt5EMJMn66OkQ5c+8DtUn+5O5o7dy5NmDAh5jdZdnY2x0XT1NREgUD3vwvOxeHDh2PGZPLkyTwesCZjBFi6iR8jiIh6cmMEgc7NN99MhYWF3Ac8q0Edl4rFl8izpSSE4wbyPEoQBEEQBEEQBOHCYtwbi/BFGFJ0Wny59CbsBEEQBKEvyMzUBAeN/sQnagbse6rqe96UkaNZ73BGCRPUD1+T2UJhWAJJZIJCZQke2kWBda/Hhk8/UHV0RMQqsMgCwQsIwUpItODEYiUTRBu6659oTJm5ZIK7o26AyOMsQYenRXPdFNemUMUJPYcGu+jRBStdgX2TJc46gcPFVlSiwaSMMTETrqtW9erWZhS4jwiVHT+rLYEN7xC1Rb19jzpaGvWNLoAVnrFTe7S+E25tZmszgQ1vq32sIv/7L1Hg3T9rIiOM//EDes7zJ9lxty5czqGvwIRhY2MjWSwmysvq2hJGXwCrLnB1g8n7eIsvEGdwmh6iJ/xheSVl2DU8YW9LG6WlRU3ImiCYsqeTI2s6pY64SS0n6ykayB9dN4LFmUPu0hVkSx2umoLPjPosq3oQAFt0gdUUVwG3zYjXwOfexmlOWMEoWa5bM9GAiEHbT7oqF/s5RbnodhiCB5PFzvmj0zBe8aBvKaXXk7NoCVlTSrhtaid6KtDb5sghZ+48FuewOCK+HV2MiVX1QRu/qWS2pkTVq+pU+e0Z41RfV/B+kwHCD/QtmlDASx11O85D9JLDFkwgNOH2qvabzBBTxZ0XanxxzuDcgUgJ51I0XY1DV+OuHbeej09XxxDiHLc6XhB7YTtmTNV5h/MvpeRaFjMZ9Ob8ARfjc3I+5OvXHlyLehIxXCzc7rNFiFVVVfpackAcAksl0UD4Eu06KJq0tDQaPny4vqUBt1DnIzJJBlhkcTpjvz9hhSS+vbAu0luhBfpy6hSEv53AAsyf/vQnevTRR2MC3CFFc66xmDlzJgt1LlUMV6GhXgjHxeKLIAiCIAiCIAhC33D+T0IE4RIiInyRN2wEQRAEgcnIyOBlky/xh/AD9k1Vm4Os85aRdfENmjsj3X0NBBiw1BH44FUKHNiOGQctvjuCfgoe2U3BfVtjQujwbrYKEgHjoI9F2NPMywhmC5lcKfpGLDwZGTMJHgeEK1FuhUC4vuqs9iDEWGJRRAtWEgYufHpy/dTRpsakUxgFs/6hkwfPbs+BHZrwJooeXQBY1Bhl5OgbZwPRTGDzGvK/82cKrH+Trb2Eq8q0fUDkBDdU57LekwxJjjvOLwRYngnu2hR7blwA6uvrye/3U5rbSqnuswVUfUZYHWsjxANrONHpunUcCDBcRVdqVmIwkc+EKNheTR21O8jXeJBC/lYtWp37FlcRuYctP0vgEA+EE/Gud2LgiX2TakqH2leV2s8BFfaTr+kQhXwQXWmfBQgTIOxw5s7lbSa6L3q+TvDZPrufiQAxAyyHxFtPCYfUdaWjgYLeOlVl1HmG8XAXUooaj57cJhnAqonFVajqaFd11VI4EPuZw3iw2Cdvnr6dGBhnTTTRScjXQP7GQ/pWckDs4Sy4jODmSRPUGMdQXT8CHtX2GnVOtGjjq4Nzx5E7i1zFy/Qy/QPEMezaC8dIjal2rkafEybVnkx1/kS5kOnF+XPRPifnQX6Wdk7gWoRr0kADIo+cnNjvEVgoaWuL/1ycG4gR4sU9sIrXnesdCB/gCimagSBogCDnQgHrNR5Pp/AVbN26lZ566qmzwptvvqnn0DiX4AbCnUvFrVFXRFwdJWHhJ+DTfiecjzsuQRAEQRAEQRAEoXtE+CIMKYw3bLp//NI1yeYXBEEQhEsFw+JLQxIWX5LVVfQXsKJimTKPrHOWknXJjZo1jihLJnDNE1y/mkUwPQJXRyVjyDxywjkD6S56kqIXAwiBSFf7PysMG6V+4ffxRBJEJ4XDu95/fMgp0At1hfpd1p0AKBSi4O7NFNz0LoVbm7Qxc7q147voWhWuY4GTZXynm4m+oKdxh3uqSDixP6nJr0SA6whgTDz3F966z6itYi11NOxT4x77tj6EG0jTwofkbznG8XC/4siZzpYuNMIU8JSRp+wdaj35KnlOvU4dtVvVGHm1ZHXcranD2VpLT0CQgDMk4Cmn9qoN5K3ZQv7WU6oebXIa9flbjlJb+ftqX2/zfjwnVTj1BreRhRU6EHXYM9VnVhejQCSDPN7aHZH6DEJ+T1Q/13LehFB1u2DlRfUt+tzGuLVXfkJtZe/ymLRVvE+BNliWMK4FmljFXXzlOQUfEExAKKH1WdWllsH2WAEcLE1ZIeRIAos9UzU59vEARBi9tfYCAZAzf4Fqb9QEbyhAvqbDqs1r9La/p843jL9+XihwDjmyZ6hzaooe0/fAIk/I30ztZ9bp7VpDgZaTKiVKxKDGBlZ0LI4s3uzN+XOxPifnA6xNGWeycU0aSED0MnHiRH1LY/PmzSx+6Q3RboNAT8INCDsgCIomvvxgBON93XXXnTNMmzYtYhWlKy71sTKEL8mInbxNmiArP7/T+pggCIIgCIIgCIJw4RDhizCkiJiWTXK+aaBO8AmCIAjC+WIIX5r8iT+4d1i079P29nZeDkRMFgtZZi8my6Q5LNQwCNeUU2DL++zWplssVrLMuoJsV912zmAuHslFTNGulUAoQOSJcvsTBbv/6cEdESywUJwrJFNeEdmWdd2G6GCdf7UqG+vK6LyBNZgoMQ1+T1kmz+ly//HBMn6GXio5YNUlsGsjhQ0LLOoYWibOJtvyu8h27T1cN/pqyinU0pOlqx93A2zc6+o0wUFeVg/WePoAb9Un1HriVeqo205hnMdRwBoG0hA8J1dFJvQdObNjXMqEA15VzybyVm/iMv6W49RWsY6CHZ0WIzD5D3FEz4RV2RPkOf0WtR5/We33FU3o0aFNwHtrt5Pn1GqV/qba1xbO6289Sf7moyw0wb6jgdUOuLUBcOGDfnirNsQILwAEM0Y/EZA3EWCZw5Y2Wn1GOj8vqNtbs5nFOO2VH/H4ek69yeKKaGGOKsRiFVvaGD2iazC27dUbCUIftJ2XEF+EYifgLY5M7m+imCxnu4wJB3u4Tp0DR/a0s0Q8LPJQxwsCIG/VRj6WnpNvsBjGsIoCzDY3ObKm6Vv9gBo7X90udR6t5jGFIKddHadQIPY7DlZsDBdSvTl/Ltbn5HxIdVvJ7dTOZ+OaNJDIysqiqVOn6lsaEL2sWrXqLLdF5wJChvT02HMWVm66+60DqzJnzpzRtzRQvicrJt0JaQaCG6mu2oa+xLuTmjdvHn3nO9+h7373uz2GW2655SxXTIOJ1lbNOpPZ1r24J56OZhG+CIIgCIIgCIIg9CUifBGGFOLqSBAEQRBiMYQvzf5gwsLQXIc2qVNTU8PLgQrc91jnXxUjjmA3PQe2s9ucbgkGKNzRTubScWQeMaHrMHw8Lw1XOyZYNom2tBJU43l831mucyB4CR7c3ino6ApXCpkytMn5CK3NZMrMObsd0QHtLRxOsPZwIWGXUVHCHnZf5Gkhc/GortthBDVGpsxcvVSSqPFnSy866BPENhH3VUCNYej0UX0jSSBKin9Le4CNu2FdIS+zfy2+JAssYFjd+Ix1vr0PVzbhUJDsmZMiweLMUXGxQgqLM5vMds3dWleEIAyo3sTCAbj2Cfmayd98hAx3MLCOAfGN1V3EFkKceXPJVXA5uQqXqLCYXctEYzJbI8KXvsCeoa4Lcf0JtFeTtxLiiNjJ847a7WyhIxqT1UXWlFJ9q2sgioBbnGggeogXX0AwYXFGfV56Re/umbR+qM9EnKsnb8NuPn7RwOVRR/0u1f7oa6KJz6mezo0LCSy0QJwULR7CeRVW53E0OH86XRQlx8X8nJwvedkOXg5Eiy8Oh4Muu+wyGjZsmB6j8fbbb9Of/vQnOnDgwFlWWQy8Xi+LZMrKyngb1klGjx5NdnvnNXf37t107Jhm2SqeU6dOcboB3B6NHTs2YuUEzx6i6wJdCWmw3d0++pPmZnXexI0V+hI/thAUYdxLS0u7DSUlJVRUVNSjCOhSxzhvnOldu7XsCm+zdk0R4YsgCIIgCIIgCELfIMIXYUiBh094SxmPcJN5jBvu5UNfQRAEQRjouFwunsDwhcLUFkzM6kuOXZvIGOjCF2AuKCXr7MVEdm3iDoTb2ygIqy/11XpMHMEABXduoMCBHWdbhoHYouI4BXdvJPJqb+4Cc0EJmVJjJyaDh3ZRYMd6bT/edna1FPjsYwru+RSzwHqus4HLJggqoi3VhGrPUGDTexSqKlMbUWXVeri5gYKqrcGTB/XICwtEPea8In1LEQ6ze5/A7s2a9ZpoAn4KVZdRcNcmCjeexySp2ocpSqgcVuOFeiOWctRxCOzbSqGyBIQvFqtmzSWK8JkTWlkcl8Y6Xg60cfd4tHMvxT2wJw6tqaVkiheYWBzkLLiMUobfFBMsjhw9hwbcD1mc3U8AhnwNEasyXQGRiAv7KVlBqSNuptSRt1PqqDsodfSdav1Wdh/Un5idOepeI/btfwg7unIXBJGFZpGm8zyHq6FoiyBd0ZX7oWB7VZxwRCPedVFPdFXebEvHwdS3EsfizCWzPbYfEOYE44Q+BsG2ChZsRINzqKdz40ISUvuGa6BoIDAK+Tuv8RomDKq+nhwX83NyvqS5tXPauCYNNCZPnszWRdLS0vQYTWDy/PPP08MPP0zPPvssvf/++7Rt2zbau3cvrV+/noUxTzzxBP3v//4v7d+/Xy9FNGHCBBo/fry+pYlbXn75ZS4HCx8+n48tvaAM4o8e7fwOguUZtMUAoo+8vFjxGYQyGzdupJaWFq6rsbGRPv74Y25Tf4K2xVtj2blzJ/cH1mfQPkOggzGBkMVgx44d9MYbb1B5eTkFo1z8wWIMykBMFD2mgxX0HzjTz7aW1R3eJu0zVFDQv99NgiAIgiAIgiAIgx3DiqkIX4QhBUQvEXdH/FcQBEEQBMPqS6OvcwKjJ3Ic2iTYpSB8wSSlZdpCMpeO1SM0QmdOUWDbum5dDoWryynwwSsU2PA2BTav6Qwb36HAh6+R/8NVFG7rfJvenFtI5jGTMUOpx6g6PM0q7yryr3+T6/GvX63qfO1ssUgXWKbMi3XjE/BTcNtHFFj3OgsxIu3B+seq3jUvUKgnKzbnAdw4WWZcRuRw6TGqb80Nqi2r1L7fim3Pxne5jf73X6JQXZWeuxfA5VDU/mBBJ/jZBq1+Yz9qXMNtXbuTiqELSy7hhhoKfPSGdlxUCOkiqIE07pcKsIABSxjRmG1pZEuD257YgPh4ehJnwBJHtNuXaKypwyml5DoWujjy5rALGljFMFnsBJl7ONDepZijL4GVlXhhRE9tYCstMSK43gkrIK6Jd3WULBBPxN8hwV2S4donGcwWt+pGnGAmHFT/u77eBjsaKRyOdasFkhHu9AUX8vy5WJ+TC0EvTsl+JTU1lW699Va6+uqrY8QcEOq888479LOf/Yx++tOf0q9+9Sv67W9/Sz//+c/pJz/5CS/fekt9hwU6z73i4mK64447YixyQOQBgczjjz/OYhksIaiBOyUD5L/pppuosLDz+wMv3cACDNwxGUBIgzr++Mc/8vIPf/gDPfnkk9TQgM9f/wHhS7wlFwhf0B6jj5WVlRw/atQouv766yPWayAqeu655+j3v/89PfXUU2xZBwHrhphoy5YtnHewAoGPYQHJ0Qvhi1h8EQRBEARBEARB6BtE+CIMOQx3R9351+6KJLIKgiAIwiVHRoZmqaTSe/bEY1dk2bQJTUzURE8YDVRMaZlknXcVmVI1t0RMKMhWXYLHO99KhhgiYhlEffmz+OWjN8i/+unOsPYVCh7cSdQR61aELDayzl5K5qLheoQGhBnB7R+Rf90qCn66lsUy5uKRMRZousKcP4xsi66Nce0T9nkpuHcL+d95rrM9ah1CjFDNmaR+2ySLZfJcss5YFCt+aaylwKZ3yf/WM53tWfMiBfdsoTBcCZ0HJncqmUdNVCudtyvh2jMsqNGOw8sUbq6PdX3UDbDkYhk9WXWic9IZ7pqCh3dpx2X7+oiAZqCN+6VKONDGVkjOHWp6Fhd0M7ZwpeMuWkr27OksKFAxLPzwtxyj9ooPqa3iAxXWkN+juaLoP7pqbw+qAZNFlYhPvzjnU6AL8YzJmkrO/PnczuRIrg8sGOry0cTg/mz19efkQjHQhS8AFkkefPBBWrFixVlWVmDB5Pjx47R582Zau3Yt7du3L2KtIx5YwFu+fDnddtttkXpQHhZjfvOb37CIBgKad999N2IBB2IXiGWuvPLKiJsjg3HjxrErpmggMIE4BHVBPBJS30fLli3TU/sHvAwE6zQQtRign6+//jr9z//8DwuEmpo0d4MQFt144420dOnSiLAI7o7+/Oc/0//7f/+P/uM//oPDj370I/rFL37BYqJoSzCDkTNnzvB4AWeGWHwRBEEQBEEQBEEYKIjwRRhyRCy+DO7nqIIgCIKQMMbEx4GWrt/GjydLd3UEM/3GxMhAxzx2KlkmzVErUUKKlka23AEXRLzt95F15uVkyszFTCzHdYndqYlXHLFuAsylY8i6+AayjJzQKaCJxu4gy/jpZF1wDZlUHT2ifq9YZl5GtituIDPq60koo/pkyswjc37ylhkSxeRK4b5Z5y0jU26R2mcPE+FwGVQ4nExpsa6fksJiJevsJWSBFZ0uxpLFTCrdVDJGj+kBjOW0BTz2bEmmK4zjPcDG/VKArXiEYyc5Q/5m8pStIc/pt3sMbWc+PMttTyJY3cVkz5ygDptxHoYp0HqSPKfepJbjL1LriVe5/pCvWU9PFnW/0AsXPxAyxI+FxZ7WbV0WR7Y65aKuNbCKgjouAv6mI2q8Yq/nsFDiyJpKjuxpSY1HsKNBOy+iMdvIbI8SH0YBqzKagKkTlEc9ScEWdwbCI46zz5+L8Tm5UJh6Em8NEHCPD5c83/jGN+iLX/wiLV68+CyLJvFA2DJ79uyzrG/k5OTQ3XffTQ888ADNmzcvxoVSNMi3aNEi3t8999zD2/Eg7s477+R88fVARDJ//nwuP2vWLD22/xg9ejTdf//9vIwH1l2M5yYAlmswtnApBTGPYf0lHvQRLp9GjBihxwxOyso0UaXN5SCHO8o63TkQiy+CIAiCIAiCIAh9i+WHCn09Bry9O9jf0hCGJs888wyf23cPzyBr1MOcnthY307HPT6aOXMmB0EQBEEYTOB337p168gXCtOKwlQ9tnugHX2lXJtQvvzyyy/em6s+L5my8slcMloLpWPYSojJdrZYwWSxkCk9m0xWG5mHjYqUQZy5oJQtjJhS0lWaik9JY/GLKadAW8/IIXO22k/pWLIMH0fm0ZPZ+ok5rwizbfoeFGrdnFvE1kIgFMES5c1Ylo4jy9ipZF1wNe8r+NnH7EbHwDJ2Gllg4SQas4UtyKA82sbtQR/SMrh9aLd5uGrTyAlkmTSbLBNnkSlaqKF+75jMZhbpGP1FXnNesZ4hivixVPWaVV8xbgYmh4vHQBsT1Q7VHljR4XUIQFAOYzRqkiY0UdsxAhl/h8qf0bmPEhyvSapvXU8qQtxiUuOO/eIYmNxqvxgDNU6WSXM1AZHNFltnF+0GfHxzCnl8+DxAXZnquBaP4nG3jJnCeZjzHfcLBKwCIEwfl87hQuHMV8fGmatvgRD5m4+Rv+mQvq1hTRnGoodo9yyhgIc66rZjRY8BIXJkzyCzLUXfVtcIle6t3ki++l0UaCvvMgR99RTwlKm8mkDCnjGebOljYoQgQW8deWs261ud2NPHkiNnpmqbLooKh1S7dlB7pfpc6aCP7qIlMWILuBbqqNsZIyJAPkfOjBjhRTjUQf6Gfaqbne7MQFdjEt1Gsz2T+xFpFzBZeHxDvlgXZxDvwGqN2dZ5zQ0F29W4bebxAcmMiQt9jXKR01VfewIiDFtKqeqjuj5E7c9scam2FvBxQp1dCXOs7iKyqbZa1VgG26s5jyNLXdNcUZY31DjA/ZSvcZ/aiHoDQcW7Chapfo6N6Weg9QS1n1nH67a0keqYq891lJgkhLoadqk2dVpCceTOJHum+g4wRZ2z/lZ1Xnykb3VzXsflMTjrsxIOqH3uVedtp7WQxM+f/v+cXCjWflpLlXUdA/5eGEINWLCD8AIiGFiBKSoqYtHG8OHDacyYMbw+Y8YMmj59OltZueGGG9jySbyQAwIOxEMUkpuby0IOBGyPHz+ehSqw8ALLMHCxlJ7e9TUabUIbIDCGyyNYhxk5ciRNnDiRLcFAMANRDCyHoQ1oFwIEOdi/TX3HAaTDwgj6ZOSBaKa0tJTTo/H7/T3WZYBt9AniHLQNdWGMkHfBggUxYh30A+MwZcoUdgeF333ohzGu6A/GBL8J4RZp7ty5MW6nYNUGz2AwDka7Fi5ceJZ1nkuFjz/+mHbs2EG5Y4pp1JJpemzPeKob6eA7WyklJYXFTnA3JQiCIAw+jHu4vAmllD/x7O/peGoOnlahTOYcBEEQBOE8wT0W7nNN6ga6S7sXXq83YrpTEAYTeLgFn8wvXlZKLkvnA8Oe+OnBOlpb3crmkxEEQRAEYTBRW1vLD+H93nZ6dO4wynX0/DDeHwrTN7efofJ2P33hC1/gsoONMATg7a2a+yOsQzgDMQzEEVEuc7olHKKwB+WreROiElOKKmsys4scuMrheoGqz37H18gyZZ623Q3hjnYKNzcQGW6EIECBOATuh6IFOP0B+tfuUf2rVSeEj9j6SUYOEQQm3VlV6S3YV0sTu1bCWLHgxpm4a4EYousKhTTRTnpWj8f0Yo37E088weG+lSV0vwoXiswpD7G1FINwOEBtZe+R59QbeowGhCXpYz9PJmvnRH3I30KtJ18lf/NxMlvdFNJdtWRM/LrKj8k/bTzC4SD5GvdTe8UHFGg9rfJpb7mbVV0QClhc6vNgtlN71SccD1KG30jukuVqSDuPha/xIDXu/aW+1Qnc76SNviciNgjrwhfPiVfYSgj24SpczMFk6RQlQXzSfOhJ8jUd1GM0AUrm5L8gs6PTWgMEHm3la8lbt02d2k5Vv5/FDvH7BdFtRL8yxn+JrKmdLs/CoSC3zVu9iYI+dR6p22+LI4tFFY6cWTEiGbhqaj74eESsksyYZM/6AQtQDLrq67mwpY9T/btLE7/EWPkIU6ijkToa9/HxhAAEog0cQwhX7OljyJo+moJtVdS479dcIqV0pWr7tVoenaC3ljxlb/NYQrCCvltTSilF9dHi6hRQIg3We9oq3udtZ9481a671bnY+bnHOdVevoY66vegdWpMc9R4XU+2VFia6Gx7oO0M1e/4d33r7HMHxOcxOOuzos6LlmN/Vsdyix6T3PnT35+TC8U//mY/7TjYdEneC0PY29raSi0t2vXbEMfApVF3VkviwSMzPB9rbGzk+uDOKDMzk4Ud0VZRzgWEH6ijra2N95+dnX2Wa6SLgdG/uro6Xne73TxGPbUtflzRH5TBmCYzJpciGKt/+qd/om3bttG02xfTxBvm6yk9c/DtT2nXCx+xEOknP/mJHisIgiAMNox7uMk3L6Ipt8S6O+yKva9toH2rNsqcgyAIgiCcJ7gvxX16YrP+gjCIMOsuDkKXgMlmQRAEQegP8BYv3oKGoOWzRq8e2z02s4mW5muT4bAU4/Fok3WDCbYQA0sisHACKylqCbFDj6IXCEB8+viZzGwNhcujrFpHXLimnIJ7Pu0UvShQr7nw3G+DscWVvGKtPbrlFhaAXIxJJvTPnaZZz0FbYGUFIpILLXoB2Fd6Fu8D++u16AVE16XaDas85xIyDahx70dguQPClmjM1lRyF19NKaXXkbt0JVvXAN6aLRTy6cIgBSxz2DMmUMrwm8g97GpyFS3lgHWIE1JH3U6O3Nl67uSBRZFwqNNiEqxfwBKGe9i12n5KrmVhSbTopTuC3hoW9ESDchBIpJSs4PZCBJQIGDNv7Va2IGIAd0ywCJIy4matPjV2GJd40QvKdNRsu6gubfzNh6ntzAeqDfV6jIGJzI4schVcRqmj71LH7w5KHXm7Wr+Ttx15c9ltEz5fBh31u8jfckIdrJAeoz5qzhxKHa7GofR6bRzUOZQ64kYWeERQ+f2tJ6ijYbceodrVekqNT6zbKgivcKxTStWYqnFNHXELi2j6m2TOn/7+nFwoLuVLnSFSgTUTBFhMgRWTREUvAEIOl8vFlltQB5bYTlbggbfPYF0FdcDVzUAQvQCjfxgbtA1tPFfb4scV/cFDxsEuegEHDx6kvXv3ktlipoIpibt0OrPzGC/hPksQBEEQBEEQBEHoG0T4Igw5jIcx3Rg76pJwtDluQRAEQRiEwCw92JmA8AVcnuOmLLuFTp48SXv27NFjhzahhloKbHmfgns/pXDtGSKfbj0xBCsjjRQ8uJP8H71JoXJt8oMxmck8ZjK73RGEgQQm9NmlS5RwQf2QZgsXzrwFbAnDcK3ja9hD3tpP4wQfNnZR4y65jq11IGDdnjVVlYNbkN5PkAY8FWylA7/SDdAWuPvBflwFl7OLnuj2dAcENCzQiHHfZGKLG7A0Ys+awi6MEsVb8ylbeIl2CcRjkTqc68PYYVxiRC9wIVW7jbxwI3WR6ajZyhZIYMkn5tgzJnUKWMikxhYupGCNJNrlTjQ4d9oq1qrjVBFVj4nLObKn8ThAEKKNrX4uqHxw69PG+9esZQG0xdd85KxjhLKO3Dk8rnBhFPa1sLWY/iSZ86e/PycXiqEgZhCERFm7di1bfUnJy6SMYdFuA7vHU9dMjaeqWfwkwhdBEARBEARBEIS+Q4QvwpCj0+KLIAiCIAgG06dP5+XuZi+1BM79LTkyxUazszRXEZgEEIjCzfXkX/cG+d99nvwfvUGBje+yWyN2bfTJ2+Rf8yIFd28iCnZOkMLSi3XOlUSWzklwQRgIYEK/vWoDCxEo3GmhKBZNeMJ5z6yj9sqPdcFEtAggnjALPYLeTmFDssAiiRdtg/ili7bB1QxcyMC1TiJ4a7aysCLaikwsiYvgQ75mauOx+ESNhWpfjCAiFuwP44uxg6UVlL3Y8LFUx9FT9g5bbYHrqO6Pv044pB/TWGs1vvrd1Fb2Lh8LTezR3Tiq8v5m3l9bucqvysXjrdrEbpvCQZ8eE4XaP847CIf6W/gCEj1/+vtzcqEQ2YsgaFRWVtKWLZqrs8KpI8ls69k1qEHl7uPk9/qouLiYRo4cqccKgiAIgiAIgiAIFxrLDxX6egzw2QsfxIIw2HjhhRf4DZ3bS9LJaUlM+/VJXRud8Php5syZHARBEARhsJGamkpr1qyhmuZWmp7pomLXuU3w280m2lDbRjX19bR48WJ2HzCUCddXU3DPFqK2FgpXnabQ8f0UOrybQkf2ULjsKJEnalLbbCZz0QiyLr6BLKMn45V6PUEQNHbu3Mlh+rh0DhcKk9VFIW8tBVpPcvAjNB3pcoIdVl/CwTYKBbxQdHAI82R8Dfmbj5OvYS+vg3CgXdWnzvtAq4qrU8s2FqCoDa1MRz0FPWUsXvA17GNxQ8jXwGUBrIdgX4HWU51tazmmlif0HLFw21S97I5JbxuEIwHPKeqo/YyFMUiL7ivq8jUf5XLRhHyNLLwIB9tVUH0MBSJtDrSoMqqtENmYzFZOC3hOR+rsqo1hfyuPK1zgwHVRyO/hvqGNxvihn5oFkK3krd7EeeNJZkxMVjcF2ysj+brra0Kw5ZVyFSpUu5pUvdVq2RrThzCOc3sV5/E1quPZiOO6h0JxbpIwbji3UE+oQ40zymKMcV7heLWVq3PisBrjXSwI8cOySxfgGOF4YL8Qt/AxUnXwuajKe2s2U4c6TibS2x4Zr+MxdXZ9DGPzGJz1WWlRofmwakuTnkMj0fMH9Pfn5ELw4bZaqqjxyr2wMORZvXo1u/h0ZqTQ1FsvJ3d2Yr97D6zeQi1n6mnZsmW0aNEiPVYQBEEYjBj3cHkTSil/4rndcNYcPK1CmfzOEgRBEITzBC55EUzhbvy9QBjQ0dH/b0sJQl9z5513Un19PT21sISyE3xD58cHaunDGg89+OCDHARBEARhMPKf//mfLH5ZWZRG3xybfc63vL3BMP3Lnmra0+yl++67j774xS+yGfehSqjsKPleeJjCTfU8cdwlFvUDPDOXLCPGkXniLLKMn4GZTD1REDp54oknONy3soTuV+FiAtc21pQSsjiysMWT/BA9YJK+OyzuInb3Yra4eTsEoUNHA5fr3jJG8sS0LRygQHs1sZWaXgC3M3CZY3HmqS0ztxmiD7bOcR5YXAWqfdm66xo1Fhg/CBzOs97+JL4ParA1MQrEPbqo41zwsXLnq3py1IZNVeFX41BHgbZqFo0kCo631ZXPdUBQA3dKA8FaTm/On/76nJwP//zwAfp0X6PcCwtDmurqavrnf/5nOnToEI25cgbNfuAaPaVnvM0eeu9fnyJvo4f+9V//lYXigiAIwuDFuIebfPMimnLLZXps9+x9bQPtW7VRfmcJgiAIwnnicDjI6XSKqyNh6GG4Oupa8iUIgiAIQ5fLL7+cXC4XfVrXRsc9555wc1pMdGVBClt+gWDGMP8+VDFl55N14TVknX8VWWZeTpYJM8k8YjxZRk0iy7SFZJm1mKwLriHbkhvIuvwulT4LM6V6aUEYuECUAEsX3potbFmD3Qj1IHoBEEPAWgXycxlYvfCUXfDJ/Ji21W7vtegFoG3+lhOqrk8jbb4Q4hTUgTGLjAXG7xISvYD4PmC8fU2HEha9AD5WLSf5OHEdaontZEQvAMfYqMPXeGBAiF5Ab86f/vqcnA9ikEwY6uDFwDfeeINFL7DyMmrxND3l3FTsOMqil6ysLJo8ebIeKwiCIAiCIAiCIFxIDDsv8qRdGHKY9Cd3oSSEL+Fu/dELgiAIwuBh3rx5NG3aNKr1BWl1RQsFE/j6m5ftolmZLqqqqqInn3yS9u/fr6cMPUzuNLIuuo5sKz9HthX3knX5nWS76nayXn072a67R4tXS8vMKzivIAiCIAx8RPkiDG0++eQTevPNN3m9ZO54yhpZwOvnorW6kY6t28Xrl112GeXk5PC6IAiCIAiCIAiC0DeI8EUYckQsviQhZjHEMoIgCIIwmHG73XTLLbdQSkoKbapvo6Men57SPbl2C91Vmk4j3DY6ePAgm/VtaGjQU4coJjOZXKlkzhtG5pETyFw6lkxpmWRyuPQMgiAIgnBpILfCwlBm79699Oyzz/Jv2+xRhTTysil6Ss/gbcPj63dTw8kqKiwspBtuuEFPEQRBEARBEARBEPoKEb4IQw5D+BIKJ/4ET9wiCYIgCEOF2bNn06xZs6gBVl/OtJA/ARNpk9IddO/wTMq0Wdjd0csvv6ynCIIgCIJwKSPCF2GocvLkSXr88cfp2LFjLHqZfPMiyijN01N7puFEFZ3afIDXly9fThMnTuR1QRAEQRAEQRAEoe8Q4Ysw5OgUvoiaRRAEQRDicTgcdPPNN1NaWhptqW+nQ63ntvoCluS56faSNHaI8Pzzz9P69eu1BEEQBEEQBEG4hIALz6effpq2bdtGGSV5LHopmj5aT+0Zn8dLB9/+lNrqmmnUqFEsfBEEQRAEQRAEQRD6HhG+CEMOw20RTM8mikhkBEEQhKHEzJkzac6cOdTkC9KbZ1qpIwGrL+COkgxampdCfr+fHnnkEVq9ejV5PB49VRAEQRCES43eGHwJhUL06quv0htvvEEHDmhWLwThUmH79u303HPP0Zo1ayglN4Mm37QwYdELqNx9nM7sOsZi8ttvv51KSkr0FEEQBGEwgN823YXzoav6jCAIgiAIQs8Yc/8ifBGGHBGLL/w3MZIRyQiCIAjCpY7VamWrLxkZGbStwatCu55ybr48OouuKUil6jMV9Otf/5pefPFFOnPmjJ4qCIIgCMKlhPHwKFGCwSCtWrWKfvWrX9Evf/VL2rx5s54iCAObtrY2+vDDD+mxxx6j1157jdIKs2ni9fOoZO54Pce58dQ00ZG1n1HQF6Bp06bRFVdcoacIgiAIg4Unnnii29BbkQrKdVWfEQRBEARBSAwRvghDDnF1JAiCIAjnZsaMGbRw4UJq9QfoxdPNtL+5Q0/pmRy7hb42OotuKk6jTArwQ5pnn32WDh48qOcQBEEQBOFSIRndSyAQoNdff52Frza3gwLqN4QgXAqcPn2aBVsPP/ww7d+/n3LHDqNJNyyg0Utn6DnOja+1nQ6v2U51RytYPH7HHXfwUhAEQRg8tLS0sEgFwt7tO3fQoaqTZ4WskYWUPapQL9EzyIf8XdWD+rEf7A/7FQRBEATh3IjwRRhyGG+shZIw2iwSGUEQBGGoge/LW265hcaPH08HWzroqZONdKTVp6f2TIrVTF8dnU13l2bQuFQ7uzqAAGbTpk106tQpnhgTBEEQBGHgk6jFF5/Px8KB3/72t2R12SlvvLh3EQY+ra2tLM5++umn6fHHH6f6pgYqnjmWptx2OY24bLKe69yEQyE6tfkAnfh4DzmdTrr22mvZbaggCIIwuIBb5xtvvJFycnLIZLWQOztNfV9Moim3LIoJibrIQ774sqgP9aJ+7Af7w34FQRAEQTg3InwRhhyGxZewyFkEQRAEoUcmTpxIX/jCF6ioqIh2Nnrp2VNNVOlNXLRyXWEq3Tcik6ZlOFn08rvf/Y4nFt5++23avXs31dfX6zkFQRiqmK1usqaUkNVdTCazQ4/te8y2NLKljiCLq4DIZNFj+w+T1UW29DFkz5jAAeuIE84fizOXj63ZnqnHCOfHue+bOzo62NILrGWYHVYaefkUyhyer6cKwsCjqqqKtm/fzi45Ic5+99131XXYRWOWzaDpdy+h/Imles7EqNx7kg69t438Xh8tXbqUrb3AdaggCIIwuMjOzqZ77rmHbrvtNspKSaeqPSeouaKOUvMzWcRihGSILod6UB/qRf3YD/aH/QqCIAiCcG4sP1To6zHgTVz4ZhaEwcabb77JE20rCtMo257YQ+6P69rpVJufZs6cyUEQBEEQhgqlpaXkcDhoz549dKzRQ/5wmGZkusia4Bvgw1w2KlbBGwpRa3MT7Tl0hD7btZstv1RWVvJkGd4SxxJgX4IgEO3cuZPD9HHpHAYKZnsGWVNHkNWZS2ZHFlHIR2EVgMWRQ7bUUhYeIJisbgr5mzmtKyBMcOYvJGfePLKljyWzxUHBjhpVZ99ahbK4C8ldcBk5c+eq9g6HSQsKtlXqqf2D1VVEKaUryJE9neyZE1j8E/CU9zhewrmxZ4wnV+EV5MiZrs7BPAoH2tQp2qSnCr3h4x11dKqyvdt7Ya/Xy5bdfv/730dELxNWzKP6E5VUc7BM7qGFAQPO1WPHjtGOHTvogw8+oPfee4/ef/99qmmqo/TiXBp3zWwat3wOOdNT9BKJUX/sDO1+YR1PVC5YsIC+8pWvsGhcEARBGJzY7Xa2jItnF6dOnqLTe4+Rv62DRSvJfodE01RWQwdWf0onN+yjooJCuuuuu+jmm28mt9ut5xAEQRAEoTvw4gGCKazQ42LADaExASEIg4lvfOMbbMr25zMLaVxaYpNrPzpQSx/XeOjBBx/kIAiCIAhDDVhree6553j9a2Oy6Jbi5Cbi63wBOtjioz1NXjqkluXtfmr2h6ikpIRGjhxJmZmZlJWVRfn5+ZSSkkKpqamUlpamlxaEoQcmkiHYvm9lCd2vwkAA1llcRUvInjmFxSKBtgrynH6LQh0NnO6CmKRgoVrTxOX+1pPUeux5Xu8KZ958Sh11B5ltqbwd9NZR8+EnyN98lLf7CnfJdSw6MZntaitMgdZT1Lj/dxTyNWoZojFZVL+dFPJ79IjkwbiFQ0EVOu+vYeUlffwXIlZJsO/mQ0+Sr+kgbwu9I3PSN8iepZ2f4XCQvFUbqeXos3qq0Bt+9MfD9NGOui7vhdva2mj16tX02GOPUdhqiohenBkptPe1DbRv1UYus3AhrgudGO6T8DiqK1dKibpXSrZsovUa9GfbDLorF//orrf1g5720VMd56o/0f0bdNeORIjPZ2zjBT48z0Rob2+PWW9oaKC9e/dyaPG0UlphNqXkplP2mCLKHJZHRTOSe0MfNJ+pp53PfUCVe07Q7Nmz6S//8i9p9Ojk6xEEQRAuPUKhEFuzff755/nFnpJ542niyvmUNaJAz5E4DSer6MBbW6js00M0fPhwuvvuu2nFihURy/WCIAiCIPQMBKlwOyvCF2HI8c1vfpP2799PP5tZRBPS8LD73Pzn/hr6pLZNhC+CIAjCkMXj8dCPfvQj2rBhAznNJvrbibm0KCf5N4/agyEWvhxs6WD3SRXtAfKouA4VAupXKZTZhggG/qwFYahSVlbGYcVl+fTtewfAJJrJQq6ChZRSej2LNUL+VvKUvUXtFR/qGYhSht9I7pLlZDJp7h18jQepce8veb0r3MVXUcqIGyMujkL+Fmo58jR11O/m7b4iddTt5C5apvqkPUgOequpaf/vWcgDIFSxuIvZug1cIlE4SO2V6zktUayuQrK4YPUmlSyOTOpoPECBlhN6qghf+oqs6X9LtrRR+laYOmo/o6aDj+rbQm/40eOH6aPtZwtf8LsAopc//vGPFLJQjOgFGMKXaNFLT6KGc4kgsJ6MUKa3ceezj0TLRWOk96asQU91GPSm/p7qRdy5hDIgug7j8WN8ma7qMOKi99FTPgMIX1pbW7sMEL+4c9JZ8JJenE25Y4dRRkkub/eG9oYW2v3Sejq5cT9NmjSJ/uqv/ordhAqCIAhDizVr1vBLQrAqVjxzDE26YQFlj07c8hcsh+1/czNVfHaUxZP33nsvXXPNNXqqIAiCIAiJAItsLpdLhC/C0AMPI/CGz09mFNKk9MQsvvzH/hraIMIXQRAEYYhz+vRp+slPfkK7d++mQqeVvjgykxbn9d6U7+FWTQDT7AuRBxMVgRB5g2HyhsLUgWUwpOcULiqYVIq+ZUh0O3oyqqftROoy6O12V0uDnraxbmCUNYiuqy+WCnxGpo1Np/9+aDJvX0wgJkgb+3myuotU+4Lkrf2MWo+/yGIVg2SFL3Az5Bp2DVlThqk6Q+RvPk5t5e+w5Ze+xJ41iUU3cM0UDgVYaNNW9rZa93M63A+5ipeR1VVAJlsq+ZuO9NiPrkgbfTfZMieQhYUtYWo59jx5q7doiQoRvvQNrqJl5MyfR2aLS41pM7VXfqTO1W16qtAb/uuJI7RuW23MvXBLSwu99dZb9NRTT5GfgmeJXsCZncdo76oN+pYClzV1eeOlTjePo5Cgr3QSiYpcJ3lDi+K/ivhyXdWjLzvLd15zgbam/nZGRdCy4Q86AvRMMXm1jbN2HdnW0ztXFVGZIwmdgxWJikaPjI+OyRyX2Nn+OFTUWTWdlU3lUHExPT+rkxqd0VjR+6HHGfsxqX+8rsd3VVdsFDbi68If9bdzqMhkNpPNZedgdTq0dada5zgHZZbmUfaYYl52JaRJlIYTVXRy4z46vGY7DRs2jJ8zzZ8/X08VBEEQhhrr1q1j8QuszBdOHUmTblxIuePUPc45qD1cTvvf2MSWwyZMmMCil6VLl+qpgiAIgiAkighfhCHLQw89RHv27KEfzyikySJ8EQRBEISk2LlzJz3++OO8zLFb6MGRWXR5rouclvM3wdsegABGhUCYlxDCCBefqPkkJtHt6OmknrYTqcugt9tdLQ162sa6gVHWILquvlgebumgZ041DQzhi8lCaWPuJWf+AjKp9aC3lpoPP0X+5iN6Bo1khS8AllGsqcNVp4Pkbz3R56IXA1vaSLK4CtRuO1hsEg606ym960c82bN+oImEFOGgl1qO/VmEL/2AyWwjmxpbuM8KdtSTv+mQniL0lv96/DCti7L40tzczJZenn766W5FLwYQvxjg0VOUro/hx1HGhQ/oidoiJkHbxBrXg4rwH3/0BBCzqgk19A2d2LzIwwKMmDq0dSw6994ZpyVo+9f+dO4H+fVVLV80alOL0uK5zrgsIDImMWhxiI60CRvqj5ZV+8voq2fVH1nXVngc0ff4fLyB/nX2C2j59DQG2/xfj49C30QZ7IPXEIc6OSVqrPSynVVgRU814ng1ur1aAv/Fn0hlxC4hHGkusqvgSNWCHUtsqwBhzPmC8/roup28LCwspAceeIBWrlyppwqCIAhDlY0bN/Lvo3379lHehBKafNMiyp9Yqr6njO/OKNR3WfWB07Tv9Y1Uc7CMJk+eTPfddx8tWrRIzyAIgiAIQjKI8EUYsnznO9+hXbt20f+bXkBTM5x6bM/8+74a2lgnwhdBEARBABCQvvjii/TRRx+R22Kmu0vTaXlhKmXaLHoOQRDOF4henj7ZOCCELxCmZEz4ClmcuQTLLN6azdR8+E96aifJCkZMVheLQ0wmG2+HQx3k190BmW3pLEwx6e6IjDRYh7E488hkUb/jwwFN3NByUq0H2WWSNW04uycyme2qjI9CSG89zekG8XWHAh4KeMrYAozFmUOO3LnkLFio0rVrGvbrObmK14O+Rgq2V/F6V0BQg3akjf0ctxNAXNNWvob8zUcpHPZToO0M2VKGdyl8CQVaY/oHl1IBT4VaNnO+eNAXHkNbiirjUBX51f82CrSfUX1v0HOdG4yHZp1GA/0MdTTyeFrsGThYLOAJtlWquis5j9mRRTZ3sUpyq3SLai72W6nGp5rTo2H3Uc58dh9lsthYoAILO2hr0FsVI3gyjoM2m62GQZ1zGPPoMUCf0XeDyDGM6UeY6w12aHVbU0pUOwxxhpaGNlhTivmcMfrg95yOjJ3Flc/iLJyrIKyOh79NHY+4sTWOO+iyvV3s22hXX4/9+fLfTx6mD7Zqwpdbb72VLb0888wz5FPnZ0+iF0EYbPg8Xqrae5L2rdpAzWfqady4cXTDDTfQzTffrOcQBEEQhjrbtm1ji3iYe8gZXUSTb15I+RNHqN+anc9KQv4gVR/A98kmqjt2hqZPn84iyjlz5ug5BEEQBEFIFofDQU6nkyw/VOhxMQQCAfaNKwiDjXfeeYeqqqro6oI0KnBqD+XPxUc1bVTW7qeZM2dyEARBEIShTH5+Pk2cOJEaGxvpdMUZ2lbbytOTRS4bpVrP/01aQRCIdjV6aXdTBxVkO2j5Ak1AcbFwFS0he+ZkFopAYAARR1fiD3vGeLKlj4kISjC5D5FMd1hdRZRSupJdC9nhFshVQB11n3GaLWOMSruO7FlTtDR3AcEtkbt4GTkLFpEzZ5aKH88CCAhLKOQjR94ccsPVTd5ccuTMIHv6OJVeyAKYoC4YAPF1Q0Dha9xLztxZ5B52lWpHIVlsqaQ6wvlhIQDiH+TFxQ4Clu5IHXkbOVQ9Fkc2izsYVY/ZlqL2q9qTUkoBTzmnoY0scFGwsMFby256nAWX6f2boPY7gswWB4skkCcaa9oI1df55Cq8QrV9jtbnjAkswjDb0ykM4UxHvZ67Z1yFl6vjvJT3iWAyW3jMI+OZPYOPrcWRSUF/MwtYuIzat0O11ZE9Te13NAsyQr4mDgboszN/PjlU0OqaHtNWiypjiJSALbVEHYflZFd1cnsyxkLZosbtNKdDpOIuuVbVNU9LV+2CSMjfcjyuH+N4zIxy7pIVbLXISAM2VbercLE2fmp/1rRRLNJB+63uYtX/JeTi4zGTHFmTVboaW5Ue7GhQu/RwHcA47qjblj5Kpdeq41mjp5697+h29eXYXwg27Gqg4xVtNGnSJHZ5CDP+HSE/jbxsCk1YKaIXYWjQUtVAJz/ZS/te30Se2maaNWsW3XPPPbR8+XI9hyAIgiAQFRcXc8Dcw7H9h6m5oo4caW5Kyc1QvyEtFOjwU8XOo7Rv1UZ2m4fvky996Uu8FARBEASh91itVg4ifBGGHO+99x5VVlbSVfkpVJig8GVdjYfK2gMifBEEQRAEndTUVJoxYwZbCKyrr6ctFXXkC4UpX323ZtnF8osgnC+7mwaI8MVkoZRhy8nqyudNWBJpK3+PhQrxJC18cRexsADiFEzqQyDSXvkRp0E84Cq4nGBlBmmwbGFPH8siCAgPTGarapqDLYNAoADXNhDFWGHJxeLU0q1OsrjyOA5iFVhP6apuCGfQTogxHLmzyWJP57YY8H5UPhYedNSTr363nnI2sHpjSy1lYYsBxgNCFJSHiMXXsI/jo4UvakC5rRDrxPTPnkGwcsOWX3RrOAACDIiGIHzBGCAv3IDA0g2EERDMoD5YAYE1mXPhzF/IAgqjn6jHkTtTH09Vt2oPW21RxwxtsmeMY+EJ1k0Wu5ZuS9Gsp6CPcDEUCnDdEGm4S67j4xzpmzqv0HeMC4Qx6EOg5SRbvAmHg2TPmsr7gCgGwWRxq2N4mOCSypk3h1x8rPNVWoY6fu3UXrWRhTPR/UDdsK5juDtyD7uazx8tLUO106X6OENtY/yMPqSqsStV7VRpEJVkTeM4HE8EiG6sqSV8vHyNB7heYBx3rlvlR1shcDKI3Xdsu/py7C8EG3XhC96cgqU3b9AnohdhSNF4qpoOvbOVjn6wk+wmKy1cuFDezBcEQRC6paCggIYPH041NTV06vBxajxdTTaXg1Jy06ls62E68OZm8lQ18ffIl7/8ZZo6dapeUhAEQRCE3mIIX8TVkTDk+N73vsdmB//v1HyanaWZrD4X/3dvNW2qbxdXR4IgCIIQB34vvvvuu/Tyyy/TyZMn6YpcN11XmEoj3HbKcYgARhB6C9wcwd3RxXZ1BLc7mVO+xSIRuGjxVm+h5sNPaolxJOvqCBY/ot39QAxQv+PfeR0WQtJG38PiCAAxBLuhaT1FZhUHcQIEAlpiSKX7VXqHSj+piRdSSliooCX7qa3sHfKcfou34+s22gmLHBAUoD1Wd4FK0V0h+ZpZ8AN89XupreJ9Xu+KtLH3sYgDrowM9zik2g4RRCjYzq5yPKffZgFFdN9VB9R/HwVayyik+mmDpRcIcLRErY37fst1oWzqmHsIllMgIEH/IOzB+EHQ4ciapPrm4jHrqNtBLUefY8FIT6DdsGxiwG6IOhpUnRVsAYeFT7qgCWloL0RAsKQD4RFENioDp6Nc06E/Rizj4LxwFS1WeWu5PrbQYzKxkAliDYyzdozeU2PzJpexZ03mY6Sdd+i2l4+ft3YbpY97QJ0741WsiQVBOLZtFWs5X3Q/YPGG6zz1Bm9nTnmILapoqPFW+4RrIFja0cQ32Spe6wP3kUIUbKuioK9BHU91PByd7ojgVgnHw7Cukj3rB2ocingdbW059mf+rBhE7zu+XX059heC/3r8MK3bXse+soPmsIhehCFDa3UjNZXV0smNe6l8+xGeyLzqqqvopptuosLCQj2XIAhC72ltbY0JeBE5LS1NTxUudY4ePUovvfQSW8xzZKbQuOWz6fB726mj0UOlpaV0xx130JgxY/TcwqUOfitDKI6AdZut80UIYfDi9/vV7VnnFDsm3c1m7d5tMID+eTwe/o4ylngRUhgcRF+34CYI4VLGcHUkwhdhyPH3f//39Omnn9K/Tc2nOQkKX/59Xw1trGsT4YsgCIIgdMP7779Pzz//PB0+fJhGp9hpeqaTFmS7aESKjTKi/FkLgpAYA0X4AnEFJuYhJoHooq38fWo9+ZqeGkufCl9Cfuqo2UJtFR+SyZZCqaU3ssuiTqGCj7xVG6n9zDp2+ZI64haCeyKNMHlrtlHzoT/yVnfCF4hGLKotjry57N7J6Ie/6Yjq8yu8DhEMRAfdASECrHCkj/sCwXUTgNADIgd/yzHVzgDBTRRc08QKX2BBZD95ytdQ2Nek9n8lOQsWRsQ9EGc07v01u8+BOCd11J3aMVHAxU/rsRfJ33qChSLpY+9nt0ogUSFEvPgi6GuktlOruU2w4pMy8hY1Nll6qkpXY+A5uYrrhRuslBE3RdqD/raeeDVivYddCKWWqnaeUGN5WBNvKNyqjykjbmSRDoAlnMZ9v+F1kDryVnZDpB2nsNrXMeqo38WWbjhOjaW37jO1r5cjApTEhS+qD22V1HrqdQq0niJH7hxKKbmWLQsZQHjiOfEaW81BOyDeMZm1B0Ehfws1H35KtXkvb19I4cuFHPsLwb88coC27G0ke4pTRC/CkKCtrpmayuuofPthqj5wijw1TTwxeeONN9LKlSvJbtdFl4IgCEnS1NREFRUVVF1dzROItbW1VF9fTw0NDbz0+XyUk5Oj5xYGAzjmR44c4cljV2YqtTe2siBi7NixlJGRoecSBgMQraWkpPASwgC32x2ZVB45ciS7wBqonDp1ijZu3KhvdQ1cnqN/eXl5LABG34YqEClizPDZhmeJUCikpxClp6fThAkTaPTo0ZfkGMELDL6nEFpaWvj7CW7usTTWs7I6702FSxvjemVcs3D+4rzFOq5Zw4YNI1OUNeSBjghfhCHLP/zDP9DmzZvph1PyaV52Yl8+/3dfDW0S4YsgCIIg9Mgnn3xCb7/9Nh07dozOnDlDE9McNCPTyd+3w902SrEOnrceBKGvGSjCF1hBSRt9NwsNIC7xnHw9Yl0jnr4UvgQh4Nj/CAU8p3k7dcSt5B52FakMvA1BSNP+37FYAaDNECoYVlvglqZx7694vTvhi0Gy/eiKcwkh4vsOazYtx14gb42Wx5Y+ljImfCmSDndFzYeeJF/TQRa2wD2OaiAqV2W2qro3cT7gLLic3QFBFBQO6UKIMz0LIeLFFx0Ne6n5wO8jIpWsaX/NbdIIU0fdTmpS6QCWdTKRnjqCtyHuaSt7N2K9BbCrHmc+mR0ZnJ9UsLqK1D4XRcQmsIpT/9l/8jqAqx9YtoFrH7YKo8YR7rM0KzEqf2s5tRx/gfzNR3gbJC58CVF71SZqOfI0b8GKDvpoiJUwrm1n1lHr8Zd4E23JmPyXURZo2qnlqDqmNZ/y9oUUvlzosT9fDOELJmsgehlx2WSyu7XPjiAMJrxNHmoqr6WKHUeo+kAZNVfU8hv5I0aMoGuuuYaWLFmi5xQEQUgO3BtjEnHnzp108OBBtpQKoQsmT512swoWcjkt5HaYyWy+dCaYhMTxBcIUCIbIajGT3SrHeDDi9an7i44gB29HSP1Ot0QmlGfOnMkurSCAKSoqGnCWnd566y36m7/5G32ra9D2zMxMXk6cOJFddY0fP37ICYIxb75161Z64403+OV6XNujgTho/vz5tHz5cv7teKmIGSFowXcVvp/wXXXo0CGqq6uj5uZmsllM5LSZyaWCW31fOeQaNmhox3XL3xksVhtfnwwB19y5c6mkpIRFMLiWDXRE+CIMWf7xH/+RNm3aRP88JZ/fRE8EEb4IgiAIQmLgpg8uBdevX0/Hjx/nB3rTMxw0K9NJM7NcVOy0igBGEBJgoAhfYPkkdcRtBCsmXU3oR9OXwpfoNBC/L4gfGnb/D6+DntoyEIUv0cIWEC/EiE7PnPptVR6ufiCiCFJQjQ0EDwawoKK5xzGdJbLojnjxRXvVhogoBMSIRtjyz1pqPfmqtq3oSdgByztwv2RLG8v9MVkcPPZw04Q2GsQfY+DMnU0po+5gSzyqZi0Sgp5Am6r/TWo786Eep5Go8KWrcYk9ZhAMvUTtlZ/wNujpmF5I4cuFHPsLgeHqCA+1LW67iF+EQUU4FKL2hlby1DXTmc+OUfXBU9RwoorfboTgZfHixTRjxgxxbSQIQtLAAgBeCMH9MSZJMYmIkJdpp6I8J6Wn2MjtNFNGqo1SXVa1rQWLRSYUByPtHSHyB4Jks1rI5ZDnIYOR1rYgtbYHqNnj5/WWtgCLYCrrOqii2ktWu5N/U4wbN46mTJnCAhhMKA8EEhG+RIOJ5UWLFtF9993HIo+h4tYJ13W8UP+LX/yCxSEGsIZjsVjYIgrm1QF+S379619nF5kYr4EKXLFB8LJr167I95TZ30bFGXbKVd9TLruZ0p1WSnNYKM1poQz1feVWccLgoMWrrlXqOtWkrl2tar0Z4j1/kCqafFTW6KPU9EwWwEDsBvEeBDBw/zpQEeGLMGT5wQ9+QBs2bKB/mpxHC3M6TVn3xL/tq6bNde0ifBEEQRCEBIHJzx07drAVGAhgfJ5Wdn80Ps1Bo9XNU7bdSrnqxinbLm6QBKErBo7wZSm7nIHLHYgBWo6/SN6qDXpqLBdT+JKMeOVSEL6A6Dqi07Omf5ddJUUIw7Ryl7f1uhBiDXlOr9ZjuiYZ8UVX4oru0i3OPHY7Zc+eqll6CQdVX5opFGhVq36yppbwuQW6Er5YXPmUMeGrZE0ZpsdowLVR8xG4Gtqvx2hcOOHL2cdsIAhfkhn7C8XPnzlG72yq5oddMOkdtptF/CJc0gR9ARa7tDW0kKemkRpPVVPj6RqqPVzOk1AQvFxxxRU8OYVJC0EQhGRpa2vje+F33nmHJxGbGmqpKNepgoNmjs+gccNTKC/LwUIXu00mEAVhMALhC8KR0x7adbiZjpZ5qKLGS82eALtQhAAGFuVgDcZsvrjXgXjhC9ycjBo1ioXvcNMFQQesfxiiDgOIXvCSOSbGhwKwivLjH/+YXn75Zd6GBQxYvlmwYAGPFVy/f/zxx1ReXs7pEAr85Cc/4d+WA5E9e/bQm2++yd9TJ44fp+JMBw3LsNOMYSk0ocBNpfiewsuLInQZMjRDCOMN0KHqdtpe1kpHatqprMFHLb4Qf84RrrvuugH7mTeEL3LGCkMO44dEmERBLwiCIAh9BXxW33XXXfSVr3yFbrnlFho1fgLt91l4Mv/RYw28fKWsmT6o9tDuJi9VdXRaKxAEYeAQDnjUn6C2YTKzyxrhImMcD6DW/c3H2JVRl6HyYwq0ntAz9z+O7Glkz56si15CbJmnrfw98px+S7VtvTq/2vWcXWCyqPIzyeLQfYhD4MMiH5VkSyVn7txL5nw0mTUR1SWJftuMB7d4OG/yhejgW5/SyQ37yNcW+/BbEAYaoaC67nh95G32sMCl4rOjdGTtDjqwejPteXk97XzuQ6rYdIhcXjNP3tx77730F3/xF3T99deL6EUQhF6BCeLVq1fTo48+Sls2b6C8tHZasSifPnfdMPr/bhtBNy8tpEmj0ig30y6iF0EYxKS5rVSc66Qls3LoSzcPpwduKKXbriyimePTqaX+NLsJ//3vf09r167l68ZAAhYd8PL3Qw89RN/61rf4ud7dd99N06ZN03NobNmyhdatW8fimKFATU0NuzcywP0RBENf/OIX2frNd77zHbr88sv1VE1YUlZWpm9pFmN8Pl8kXKxxw77Rjz/84Q8s0LS3VdJV4zPp/nn59BeLi+mB+QU0f0QaFaXbRfQyxEh3WmhYpoOWqfPhLy4voi8vKqS7ZufSrGFuqi87Sq+++io9/vjjbPloIGLYeRGLL8KQ41/+5V/Y/cI/Tsqjy3MTe1D6r3uraUu9WHwRBEEQhN6Amzm88bZv3z5+AwI3i7W1tfy2RKrVTKVuG41OtdMot51cFpMKZm2p0pxmbenSl8YtV/wP2Mh2dAIm6/Tt6OgwthBhuNiI+jkcnQ/Eb4Nu8xj1oF5e1baj80evM3rEWfGKruJAl/VhxdD0RmXgvkYw6Vt6nFoYqVFDxcSvx6eDyG1ElKsSjEF8PgOO1xMjebqouKvy8XHYddwwM/H9NYgcc17vnq7SYuOwZYyjoodzx4DjjUS0uZuMiI4ejs11bQPC4os9azKlj3uAzLZ01fYQtZ/5kFqPv6SnxjJYLb74m49Sw55fqIMTJTg5B7EWQOA25xUWehicj8WX9PFfJGfeXBULV0ZBrrf1+Mtntc/oHyyQnIu+sjqSPv5Lqq1zVKxqa8injcOZjzifM28BpY6+g8zWFN6OP8a29LGUNuYefQxMFOxo4D5anLmcHvI3q36/Qt6aTssqF83iy8x/jFilCYf8XG9b+RreRpmMSV9n6zcgft8D3uLLs8fonY3VfB+8cuVKeuaZZ+jdd98lk9N6TssvcBkjCP1F0B+goM+vQpCXAbUd8Po4+NvV9ae6gZrL66ilqoHy8vIoNzeXcnJyaOTIkSxyGT9+PL/dLAiC0FvgLuL111/n4LD4ac6kDFq+II/GlaaS0yGTh4IgEB061UoHT7TS2+r39bHyNsrKymILCsuXL79ov0PiLb5Mnz6d/vu//zvGUgme63300Uds8eTkyZN6LNGyZcvo3/7t3/h31WAHQhaIgJqbm3n7c5/7HH3ve98jl8vF23hG9rvf/Y5+/vOf8zb43//9X7ryyit5HXPuEAycOKG9mFJaWspWBmEtpr9oaWmh9957j4/5saNHae6INLpjZi5NyHdRTsrQcFklJM/+yjbaX9VGb+ypZyswuH/CCwOwdpSRkaHnuvjgs4TPowhfhCHHv/7rv7IS9fuT8mhxgsKXH+6tpk9F+CIIgiAI5w38x+ImGQE+z6urq6mqqoqFMCDNaqY0m4XSealC3LY5SqzCQgG1jV+zEcFD9C/bOJGBsRoRQeh1dfNzmLNEp8Rk62xGZx4jg67IiBZhGGudMRrd7JrzRSfFiEz0VdQfyYMVvU1Yj8RH58HEMy/1v50JMSA6Ogn5IrvVEzhPdJsMVJwey5y1rkdE4lE0KhNWI5vGjrFqbOvrWhL6o1a0aCZ270Z/9Xh9IzpHNIjvKs3oJtDq76w3OjG+rLHNS2MD4xifUYEo1G2KbrPKCOH1xRa+WBw5lDHlG2R1aRP+vvrd1Lj/YV6PJ14wEmirovYz7/N6NOFQkPwtx8hizxqQwhd38dWUMuLGiAueUEc9tZ56U7W7Q603qrYf5/ieyJrxd2RL1R4UQpzSUfcZddTuUBuq760neDx7K3xxFS5m90Emq/aALdBeySILtBOiC/TZZE1hgUigrZx8Dfs4X0/0lfgiY+LXyJEzQ4tXbWuv+kSNwzYee3fhErJlTVHt1SaCoo+x2ZFFaaPuIHv2dJVuUQMQYIFLKOjl/rMFGfVpgbWblqPPqLKVXO5iCV8yp36b7BnjeR3t8jUdUuf+Oqyq/k8nR+4cvc1n73ugC19+8dwxenuDJnxBwPf1k08+SWvWrGHxy8Tr59PwRZPOEr80nKyiva917RZNEPqCQLuPrbsYQhesm0JhfgAKs9fp6emUn5/PYhe4GDAEL3BvJAiCcL5gQhSTiRC9lBa66LqF+bR0dg5bdhEEQYjnk5319Nq6Stp7rIVC6vfKVVddRTfddBO7WuxvEhG+gPb2dvrpT39KTz/dea8C4fDPfvYz/m0FgsEgW7AxnvNhHRZGAH6DlZSUsOAD7pR6AmUqKirYbRBenjPqSEtL43oKCwu5rng3UYFAgCorK7ksloZ7Jrg/gfAZ1mywf5steZEHrLf8wz/8A23dupW3Fy9ezC/ZG1YC8XwTro3wPQCKi4tZ+IIxAh6Ph/7rv/6LXnzxRd6G6OU///M/uV39AdqPezi8yOC2htmqy+fm5tO4PO25giCci3VHmuilHbW0+0wrOZxuuu2221i0N3z4cD3HxUWEL8KQ5d///d/ZhNzfTcylpXna24XnQoQvgiAIgnDhwQ3w8ePHWQCDZX19Pf/+xA0tll2twzQogOghmvjteKLTu8ubSJ2J5DGITusuX3we/DSPz5tI2Wji6+yKRPKArtLi4861bZBIXQaJxJ8rT/RYXoj6QHd5DOLTz6dOfB7gR3vpnFz6/oNj9diLgyZemK7WTBRsr6LGvb+mYEe9lhhFvNikOwzRQKijaUAKX+yZkyh93P2RdqmTiUKBVrUMkbfuM2o99rwW3wPp4x/UrbJoD+Jg7STsb6NQsI1ajj6v2mXutfAFgpbUkXeQI2uyqh79Q/vaKeitIXVgVJydLKpek81NbeXvJySC6CvxBY5DyrBrVJs0oUrI30pBdSzhqggWUFjUEi98UXHuYVercur46a6Mgm1V1HxUtScUoLRx96lx6bSu4q36hFrVvuA26WIJXyBEchVfFXFpBLFT2NeklmHV9VTERM63+H0PdOHLL587Rm9FCV8Ark1PPPEET/CZXbYuxS8QvexbtTHyoFcQ+hqIWwyRi7GOB58IKSkpPKkwevRoniRBuiAIwoUC1k2feuop+uyzz9iN0Y2LC+iquYPf+oEgCOfHvmMttHZrLX20vY5a2gI0ZcoU+vKXv0yzZs3Sc/QPiQpfcG8DN24QuhhAQPyb3/yGJk2aRK2trbRp0ya+Fh49epRffINwxRCfQHCCfHPnzmVLMfhN1hUQrcCNEsKBAwf4eaFRB0QvqGfp0qX0hS98IUZAg2cocOGzceNGOnjwIFuchtgE4LcgRM9wbYkx7o2FGrQB7oEefvhhtoADSxeoCy4yIQqC26DnnnuO75VSU1PpgQceoC996Uss1gF4romxw0sEoLtx7gtOnTrFbYOLreIMO62YnE23Ts+hTFfPz24EIZ7dFR5690ADfXCokZq9QRa+4Fzv7vPcn+AeDyI3Eb4IQw6oKKFs/N7EXLoyQeHLv+yppq0NInwRBEEQhL4Cb2Xghhg3pbhhbGtr63Idb48AiAUQosUNoDsRgZHfoLuy0dsGieQB8fHGdnz5aLrKA3oqA7orBxCXSPmu4kF3Zc9nHfSUBuLTEXo6vudajy4bvzToqlwieaLpKd3Y7i4edJcHQm2E+1aW0P0qXEzcxVdRyvCbyGSx84R/68nXIu5qohkswhezLY1SR93BlkoMqy8GsFjScuQZfat7HDmzKHXEzWRx4e2tzmOrCVieUGumXgtfgC19HAtDrOmjyMyWX2LPHzXKLDLxlL1L7RVr9bju6SvxhS19NItCbGkjVRM7zwsIVgKeMrK6CiLiFuMYs4ujsfdGrAxBNITzDW6SQErpDerYXq2OjTZxHepooJYTL1NH7faLJnyBdZ+UUbeRPW1UTD9J7cfvOaPOQ3OnK6S4fQ904cuv/nycVn9Sdda9MNwV/vGPf+QHvBa3/SzxiyF8QRkRvwj9ASY+EDCxAbEL1kXgIghCX4PJRLzBj8nZeVMy6fZlxTRzfLqeKgiC0DPBUJj+/G45bdzdQEdOe2jixIn0j//4j/06iZyo8AXP42DBBEIXA1h6+Z//+R8aN24cXw/R9m3btumpXYPfanATBNEIXD1FAysxf/rTn+jVV19lqzHdAQs5mOcz3KxAdIMyECGiHd1xvmITCHpQHuIaiF9gQQaujOD+CK6g8OwSohq0D26Roi1hYL4dFnPQRgARDr4/+tr6YFNTE/32t7/llxbg0uimaTl0swqC0FsC6rr1p0+r6ZOjTXSwup1WrFhB3/jGNyIir4uFCF+EIcuPfvQjvsh/d4L6AspP1OJLDX1a3ybCF0EQBEEQBKFfgDUFhIEgfLG6i1mkYU0pVVth6qjfSy1H/kQhf4uWQceRPZ3sWZPUmkWL6I6wn7w1n7KFDmfBIjJZNOFDyNdEntNv8jqEEs68eUQmzQRxdBqI31cQ7n6iBB49pcfXHV8WII8jZ6bq+zDdqoqC3e18yi53zgXc2jjzFpA9c7zaTefNf8hbQ56yNQShU3Tfw8E28lZtpEB758M9CDzMdu1BXlfpaKM9c7JqY2HMPkjd4mO8YAGmo2EPBVq7f/Bn4MxfoOrTzFMDf8tR8lZv1rc08ZPFVahvBcnXsF+dB7v07Z7THVnTyJ4znd1mqY6r9oXYPZO/8SALY+KPPwRH9syJKkY7dhCZYMwhlAEQy0SPnSrJ7qfQ3th+xLbjXH2IHm/jHPW3aP7XwbnSuZ/Zk8nizMcJwMch2FFHvsYDZFHlutt3X479heDXzx+nNz8+W/gC8IAXb31C/GJNccSIX6KFL3IPLQiCIAxGMMH5y1/+kp8zjyx20z9+aRyVFojLCEEQkmfzngZ65OWTdKbWy5PIEE3Aukl/kKjwBa6DIDbBNc8Allt++MMfsjtJuDT/u7/7O7buDOEO2m+1avfSuG+AQBDWXADS/vmf/5muueaaiLsiWHiGRRLsA1ZTANwFQQwEl5UAYhOIY7Kzs9nNkCF8gXUY1Ic2AKTDgg6WuPfGy3YQ7oMf/OAHvRa+QPyzfv16FrAcOXJEj+0EVmVuuOEGuvXWW9kFUvQLThDnoG+vvKK90AFLMRi7vhYLQEgESzXpTgv947XD6bLRIs4ULgwbjjXTz9aWUXWrn60b3XPPPWx182IhwhdhyAIV5bvvvkt/PSGXrklQ+PIve6tpq7g6EgRBEARBEPqJgSR8ASml15N72DVksjg0SyInXqH26k166uAFwhdYugHhoI8CbeW8nigQSlgceIsND7wghGhggceFJHYfCghLvDUUDrRp2wMAWHWxOvNYEBIOBVhsBKsvgw0IniBCYZdHA/A49IaehC8AD3B/97vf8UNqW6ozIn45/N52Eb4IgiAIg5o33niD3VZkpNroL+8aSUtmyRv0giD0nrc+qaY/vn6K3R7de++9dN9997F1lL4mXvgybdo0FmjAWgmmjyHyq6mpYcGL4coH2Gw2+va3v80uh7BeVlbG1kzgWhKiE5RHPED5VatWscVIWHUGmCSHUMZwVwQrzxDcYB8GuI/4/Oc/zy4rAeasYdEFllcgEIKVP4hRHnvsMbY8YwBRyde//nUW4EB8AsHMmTNnaO/evbRkyZJeuTpC+1B+w4YNtG7dOtq3b5+e0gncVN1xxx10+eWXszWYaOELRD9/+7d/y+7xACzeYPz6UigAQdC//du/UYe3je6fV0BfWWS8MCEIF4bnt9fQwx+fITJb6J/+6Z9o8eLFekr/YwhfNCmdIAwhIgrSrjVfXZJEVkEQBEEQBEEYdMCNDFu3CIfIbE0hR958sjiTf1h0qQGhC6yJICQregEQuWDctDpOXHDRC4jdhwqtJwec2ALtQbt4HD2nB6XoBWgunE4P2OPQGzof1XYN/Nf/xV/8BV133XXka2mnA6u30KmN+/VUQRAEQRic7N+/n5555hmyWU10/eX5InoRBOG8WamuJcsX5PHv7xdffJHFFbBU0t/U19fTm2++yQIUhCeffJJd5eDFHEP0AubMmcNufgxxC6yy3H///XT33XfT1KlTeRvCFASIYJYvX06FhZ3Ci9OnT1NLS6cVWZ/Px9ZcooFABdZkjHoyMzPZIg0sqmCCG2CM0OZo4EIJ+4KoBuXQlgkTJtBtt93WK0s6aCeEP7/4xS/Y3RNEL7A2s3DhQhbSQOQCIGr51a9+xVZWjh07xlZsDCDWQRzAmI0dOzYydn3BwYMH6ZFHHmGh0aySVHpwgdZGQbiQ3Dkrl64Yk86fQ1wrIA672IjwRRhyGMIXEbMIgiAIgiAIQmLANU37mQ80VzsmIlv6SHIVXE5mq+FuRhCEwUjUS4rdggfK3/zmN/mty47mNha/eGovvMhLEARBEAYC1dXVbLUAbj9mTcigO68u1lMEQRDOj7uXF9PsiRk8iQzRya5dF86FaaKUl5fTww8/TD/60Y/YewLEE/CgAEuPAGINWDaBO6ZRo0ZxHIC4pLS0lMUeEKIcP36cdu7cSR9//DG9/vrr9MEHH8QIeVAfPI8YoF7DdZEBXKq+/PLLPA4Q3RhCElhSMaypWCyWs9wFYZ9//vOfaevWrXzNhlUYEF0uUdBGiJAg/kF9AJZkYNnlu9/9Ln3ve99jyzSzZ8/mPlRVVdHTTz9Njz/+OJ04cYLbDGsxsL7S1KTdI2HcYBUn2bYkCvoMoRKOwdg8F31pYSFZzX2zL2FoY1bn8NcuL6JJhW4Wd8GtFqw/XUwsP4QTsS7ABci4GAjCYGLTpk106NAhmpfjpnGpiZkRW1vtoTPeAM2cOZODIAiCIAiCIPQleECEMH1cOoeBQLC9mi1ahPwtFGg7w9YsYAUlHBQXucKlCd6F8Aft5AvbKBCyDtoQDFvIbAqTSYVk2bq/iQ6ebD3nvTD898+dO5d9+u/fvZc6Wtop4PXJPbQgCIIw6MBE7KuvvkpjS1PoK7eMoKJczeqAIAjC+eK0W2hEkZsOnfLQibI6/m29dOlSFnf0FUeOHOHr2rmAGxG4Mbrsssvoi1/8Is2fPz+mXZhPhtACroA+/PBDFotgCUspcA23fv36iPADwEoKrMDAigvAC+uwrAKRi+EOCQKO7du308mTJ9lVEMQyaAesThqiEZSDOAXPT5qbmzkO+4H1FUzEw8VRY2MjtxXiHOPF+ESB5RRYejl8+DBvo71wvwSxCyzZZGdns3uokSNH8v7RZrQf1l3QxnHjxvG4wBqGYTEHVnGuuuoqvofqCwzBUH6anUUJ80fECoME4UKS7rRSgTrXdpZ76MjJcnbRBnFcf4PPE4IIX4Qhx+bNm/nLal62i8alOfTYnvlAhC+CIAiCIAhCPzIQhS8g4CkjX8Me8tXvJn/zYRG9CJc0zb50Km8rojpvNtX7sqjBlzkoQ5PqJwQ+qba2pMUv2/Y3JiR8AXiYPG/ePH7Dc9/uvbwNU+RyDy0IgiAMFjDp+uijj1JNTQ19+ebhNG9Klp4iCIJwYchOt5PLYaHNexqotraOXQrB3U9fES98gTgEk9YQbMAyCQJcF+F3/o033kh33nknp0WLXmDVBC5OYA0LlmogcsEcHEQgEJrAZVFxcTG7MzKsvHQlfMnLy6OOjg4uZ4hYUAZukSCA2b17N7tDgmUY5DVELHBfhAlviGMgFgKY44bo5bPPPuOysMSCCXnsN1HBCebIDRGJAcbh61//Ou/fAO1A/8aPH8/fE2gvxC+wfIH+QgyEeUkA8dDXvvY1zt8XRH9PrZycRffM7mynIPQVwzIdVN3qp71n2lh4Bjdohjuy/kKEL8KQBSbFDhw4QHOzXTQ+QeHL2qpWqhThiyAIgiAIgtBPDFThiyAMFsJkov2N4+hU6zBq7MikRl/GIA7pvMx2NJHL2mlOPBG2JiF8AXjoC1/3eCA9cdJEmj5tOps8FwRBEITBACwIwH1GYY6DHrxhOLmcfWeFQRCEoUt2uo12HGyi6vp2tnCyYMECPeXCEy98gdDloYceopUrV9IVV1xBixcvpuuuu46WLVtGEyZMYPFIvIseuH779a9/TatXr2a3PrCCAoEIysJiDQK2YbkFYhQQL3wBcKEKYUhWVhYLa+A6CEIOY64aFmEgsIGIBeIco6zdbudyEMCgHCbc0Q6IZgDW4QUCllcmT55MhYWFHH8uIFqBmybs0wDjgrEwRDcGGBO0G+1AHzGu2C+EN1gHEADBWg7GJVHxTbIY31NpDgv9xRVFlJdq01MEoW/JcFrp42NNVFnbQGPGjOHPQn9iXDOSs+kkCIMA40s5FE7ezLMgCIIgCIIgCIJw6RMOm6i6PUfdF5rZ5VEoFKRgEC8A9S6gPOQ0YXWfef51wXf9hajHaJOJ2oMOqmjruzdFo8FDYPi7/863v8Om0AVBEARhMIDv+A8++IC/p5fOyaHsDJlMFAShb8hItdE1CzRLHZs2bYpYMekPICKBNZIRI0ZwgDsfWIGJtvASDyyxwLWRwZIlS+jv//7vOTzwwAO0YsUKtgQJEc+5gCDmnnvuoe9///v0l3/5l+wWCMIfuDcy+OSTT9iCSrTxBrTx5ptvpv/zf/4Pfetb36LPfe5z3A6IcAz27NnD7pcMQcy5wPUeFmiigWAlXvhjgHi4PLr33nt57KJB+2ExB2ORyDj0hujvqdmlqTSp0K2nCELfM6HAFXGrtWbNGl5eDET4Igw5DCUm3vATBEEQBEEQBEEQhh4Qu/hDVsL7EHgw6Pf7yGI2kc1i1oMlwaDlD0OkAsu5KqiNSHzidWl50QY8iA0GVZvUMrpNDXW1VFdTTfW1NWi0Xs5C7Z5WjkcIBwOR/GGVB+1BHxE6gslP0HX3UPdc9LacIAiCIAxU4LJi69at5LCZafHMHD1WEAShb1gwNYuKch1sTQXil4FMeXl5xIURgAVIWHuIvieA+59Tp07pW10D4QZAOViNhKWZv/u7v2NRfbygHtZb4LkERJeDCyK4WfnOd77DwhvUEc3Ro0dj2toTEAHBikw0cOEEN0LdASsvfr+frb9Eg3quueYatvrSVxjfU3armZZP7LSkIwj9xYpJWZTisLAYDteFi4EIX4QhhyF8Scriizy0EwRBEARBEARBGFRot4RhCgWDFPD7aeyo4TRu9AgO48eoMHYETegmIA15xiGo/Hk5WeT3+VmsUlKUT2Pj6umuLqMerkvlHzuylDq87dye+DY111fTnp1bad+u7WQ1Bbj8iNJCOnnsIMcfPrCHCvOyI23K19uEPmoh+ftauRUWBEEQBA28RV9fX0/jhqfS6GHyFr0gCH1LQbaDrpqriSTeeustXg5UNIuVncAVkcfj4XWkwfXPu+++2+NEOMT/27dvZ6GPIWgBsLAyceJEthgTDSzQYK4PVl/gigiiGghODJAG6ytz5szRYzTgCiVRkT72DYs3KGMAV0KrVq2iY8eORdwpwSpMXV0dT/a//PLL9Mgjj7CLo2jgsmnDhg10+PDhSLnGxkaqqKiIsVxzPhjfU2PzXDSrpNNCjiD0FzPUeTe9OIXP8bfffluP7R+Mz7XlhwpeiwMXlgv1YROEgQS+PPFFODPLRZPTEzMptrbaQ5XeQMJ+zQVBEARBEAThfNi5cyeH6ePSOQiCcGGBBdDDjaN4HS6BIH5ZctkCysnOotycbMpVy5xsfZmD9aiQZSwz1TKTstV2OBSm0+WVFA6HaO6s6VRSVMBlc1UdXKe+jKlLleP6VT3ZapnN9WXRzt37NJ/vqq4llxttyqK21hbatWM7VVaUk8thV3E5VF15hj5cu4atvoweNYLfaBxWVKi1KYw2nYk8qE23eagopZrXE2X7wSbaf7xV7oUFQRCEIc/jjz/Ok7n3LB9G44an6LGCIAh9B1wevbu5hs5UqmvPPfdo9wgXmCNHjtA777yjb2muhpYvX06ZmYlbDIEVFYguDFpaWtiqCqyyYC4Oae+//z7HGSKZ+P1AGALByP79+1kMAvdOEMpA0LJt2zZ2nQKLJgBug2644QaaMmUKz2U/99xzLCqBaAYCFAhtYGEGQpT33nuP2wdwX4R9zp8/v0fXTQaYSHe5XOwiCXUDTOhDvFJdXc1xBw4c4HRY5XnzzTfp1VdfpRMnTnBeuFlC/9A3lEPfamtruSzKbdmyhbfHjx9/QY6t8T31uTn5NFOEL8JFwKw+M/5QmD4+2sziLrj36i/wGUIQiy/CkMNQfSVj8MUwlSYIgiAIgiAIgiBcWExmO9nSRpItfZwKY8ni7B/3AWHjH9/vhfleEQEPa0xmbYk3Bc2muKCnafnN2lLFGfWhjFGXVp+2fVZder7IUg9GPfgXXcfixUs4wCf8p59+Sn947FF65pmn+Q3DMWPG0O2330lZmZkqv1FvbF34lzRyKywIgiAIjDHpOWVMGi8FQRD6mhFFbspK00TsPbnXudhMmjSJRowYoW8Ri11++tOf0g9+8AP6l3/5F7aCMnbsWHZD1BMQzDz55JP0b//2b/Rf//Vf9OMf/5j++7//m9cNd08Qr1xxxRUsXsF9FMD90AsvvED/8R//QT/60Y+4HALWo0U9M2bMUPdTi9mFUaKgXw8++CBNnjxZjyEW18DqC9pm7PN3v/sdrV+/nkUuaCPy33333XT//fdz3wHSII4xyv3mN79hyzEXCuN7amaJiDOFi8fkAs0q3sW6ZonwRRhyGF+GIXmAJwiCIAiCIAhCgpht535jymRxchhqmK1uFq/0GrOVHDkzKXXETZQ68hZyFS0lsyPWJ3rfYwhMYpc9BnPstkF0nBEgQukq3qgjen/RRKdVVmkPMvGgFm85ulNSKD0tTbfoYqLa2hry+Tqi6omtqzdwNYIgCIIwxMFby7A+oL62KTfzPH7zCIIgJIlxzYGVkIEKhB2GwMOwNmlQUlLC1lnuvfdeys3VXDd1Bebt0tS9DUT+ANZiYBXl0KFDETHJqFGj2MLlF77wBSotLeV8uO9JUfdFuD8CsPSCcggQqAC0YenSpfTVr341RsCSCLAgsWzZMvrmN7/JSwhh4vtokJGRwVZo0F/kx/4+97nP0de+9jVasGABp8dzoaz4GN9TFvVFlZ8m31PCxSNPnX82i4mamzWrL/2NuDoShhzwrbdr1y6akeGkqSokwvvVHqoSV0eCIAiCIAhCPyGuji4+bIUkZRjZUkdo1kjSRpO/5bie2onFka3yDOc89swJqpyVgt6B+zbehcLiKlB91sbGnjmeQkEfhXxNemqShPwsGHLkziKrexhZXYUqLkABTxlRuNO/+4VEc3U0ktdDwRAFgwGaPmViRDSCELHswuIUw4oLShhLQ1qiPdQ5VXaGrcdMGDOKXE6nnr8zdIpfUJf2kNYoH82OXXvJZrVTOBSKtKm5uYlNeG/cuIEfji5ZupTmz1/AD3/b2jz8YPj4sWNUUlpCRUVFqhZVpqWFTp2uIJtNe/AJV0fFKcmdmzsONtO+4y1yLywIgiAMaeCK4vnnn6dUt5XuW1mixwqCIPQ92w800ckz7TR79uyI5ZALieF+CIIQBFhFmTVrFrndmtWGRMD9Ce5LYNElPT2dCgsLWSACEQhcndx11118j9LW1sYilK72g3seAPdAKAthy/Dhw7le5Ef/ISiBFRVYuzRecDeASyHUjXIII0eO5HJTp06llStXsvAG+0zExVE86B/qQ3n0Df1E24YNG8ZtHTduHO8HlmhuuukmuuOOO9gKDl5YgEgG7YU7I4hzUBblJkyYECmDPsb3J1mM76kMp5W+uLBAjxWE/sduMdFru+uo1Rug66+/PiJK62vwOUUwhbvx4YKLHcxDCcJgA37uYC7t/hGZ9LnhZyssu+IfdlXRriYvmzRDEARBEARBEIS+5IknnuCAB+v3y8P1i4I1dQSllF5HtpRSMtnSWcxSv+Pf9dRO3CXXkTNnluaex2yjtvI15Dn1hp46eEkddSfZMyeShS2zhKnl2PPkrd6iJfaStNF3krPgchYdhTrqqVnV6avfradeWIJhM71xYimvB/x+FXx031236oKUTpGL8QDWkKiwuyD+r/6FtRAKhelkWRmt37hNbYfoxuuuoqyMDL2O6MBVcF2G2yGtDmOp6lLl//Cn58nlcqt6A3T/XbehAH26ZQv9729/w3nwIPfvv/8PlJGRyeKY9R+vpz/+4TF+gWn2nDn07W9/h9t0qqycPtq4lVz6w+RhKdU0N38vryfKH1adohfWVMi9sCAIgjCk2b9/P7+9P7rETb/5u+l6rCAIQt/z6Gsn6aX3z9CXvvQleuCBB/TYgQvmlWFpBfcmWVlZPOlt3FMlAkQ4mJ9ubGwkv7pPQ1mIWmDVpSfRCu6TsG+UM+a2IcKBFRlMhl9IYDTC4/HwvrBfWKlBG7Hsqa8ohxcmENAftC8Zt0s9YXxPjc930aOfH6/HCsLF4S+eO0z7KtvoF7/4BU2bNk2P7Vvw+XM6neLqSBh6GF9yHcEQLwVBEARBEARBEOKxugvInjGBzI5stuLSHchjTS0lk9UNlYQeO/iB6MXqLtJdO12YfrdXb6Zgu2bC22zPJFf+AjLb0ni7T4D2JBI0IYohUNGWWsDbd2z1hS3AGKIYLaDvxhL1oBoVE5On032SmetiSzKoM5Indr94eBppF2pWcWVlZfygF/ezubl5lJ2VrbbNZLVZaeyYMfyQB2nl5eUowWWw5AZF6tIrTALUIgiCIAhDHbxJD/KzNBccgiAI/YVx3ampuTSsiuK+pLi4mC2iQHSi3ZckDu6TYAUGdcCaCuqBQORcllqwH0x6G9ZmECC8udCiF4C2oE1oG/aDfWLf5+oryqFNKAO3TxdK9AKM76mCdHFzJFx8CnR3WxfjuiXCF2HIYZhOawkkLnwx3sYTBEEQBEEQBOHSAxZErO5ismdOJkfODHLmzWO3OvbMSeyyJxoILeDWCC6Moqf9IX6xpY/lgLoQsG6yRD9YMmnlkU/VcZZow2Qha0opObKnqTbMJWfuHHJkTSWLu1DP0InRDmOfcKcEsF+jvCNnJrsaQr2A3TOlj9H7qNKzZ2jl9HSDxOqeRbaM8Wf1gd06qTKxYiCT5vIJdan2aGIYDbPVreJGqXqna33mdk0nO+q2Z+q5NAKtp8nXsJ/dHKkdcH3I11fgPq/zn9qlLhbBEqvwR33ixEnatn0HfbJhI23YuIk+27mLKisrdQ1JZ171V6+l894xkqb+NDTU0979+2nT5i308ScbaMunW+nQocNs7lvbr55f/QNGq4w4401FBLg9qqw8Q+3t7dTU1ERHjx7lMkjLyszSyvB+tdYYdQmCIAiC0DuMiZv8bBG+CILQv+RnafebsKIiCN0R+Z5KtfFSEC4m+WnaeXgxrluWHyr09RhghgpmlwRhsHHixAnasGED5TustCQvRY/tmY9q2uiMN8A+AefMmaPHCoIgCIIgCELfsHPnTg7Tx6VzEHqPxZlLjtzZ5MpfSM78eeyWCNsQvUAkYnXkUjjko2BHg8od5riU0hVkSxlOZgfc1Wjvi5jITNaUErZ0YrankzV1ONcJF0cmizYJwhIFtW5nQcloCnprOQAIQyBycRUtVe1YoIteprC4w+LMU7sOUtjfqtri5/xGO1CGXQq5C1SWDnIXLyNn4eVc3rC6Eg54iVQfIOZxFV9FLgh7clQfM8ar9EJVzkvB9iquFyRaN0QsZouTQv4WtQ8Pl00deZsaw9ncH5NZf6hmUqNjTdH2l1pKAU+FKtPM4+XMm63qvEJrkxp3CGtgJceWPkr1tYMCrae0OnQQh3ExWV1cP9rVUb9LT71whNWxOtQ4gtdhTjsUCtKMaZN06yxmdiG0+dMt9M57a2jdR+tp46bNtH3HZ3Tw0CGqqa2ljIx0ysmBOErVFSZqbGqik6creGPi+NHkcqn2Y1zMJs6/+u13aO2HH7LoZfOWrbRnzz46fvIkBfwBGjt6NOfV6grT9s92k81m5zbMmDaZ24Q3J/fv28dmuxFgWrtO1XtItWfDhk+otbWV81xzzXIaPWY0t6mpuZlOnC7jukC6zUPFqcm9cbXzUBPtPdZCM2fO5CAIgiAIQ5EtW7bwb/N5kzPlt7kgCP1KQ4uf3ttco+49cmjFihV6rCDEYnxPLRyZRrNKUvVYQbg47D3joc/KPDRlypR+e45gvCgkFl+EIYdh8aU5CYsv6XbtDUn47BMEQRAEQRAE4dIB4o2U4TeyKAQiELMNPsbVzbBaQjQCEUrqyFvJlqqJIMx2WEMZqbkvirKUAiEGxBoIKIeAdYhgIphMvA/OB9GIqguYHZnkKlzMohFH9lQW48A6CyyjWFz5bAUldfSdbKnFsM5itMPYpy1jHKWOup3FIxaHJrbBviFQSRlxI7mKrlTLm1l0A0sqnO7IInvWFEopvT7GqkyidWNM3CXLya3qNiy/QMyCMhgPA4wTxovrSh3OVl7QR3fJteRW+2brLiyUUX0223g8rKpuhHj8LccpYIh0TGau12zrmwkmiEwigaUwEJ9o1lKOHDtKL7z0Cm3dtp1aWlqpqLCQUlNSqLyigj78aD29+vrr1NoKMZAmWAFGPUYc6vF42lj0svqtd+jo0eNsArtk2DDydrTT/v0H6JXXVtHuPXs4P6PKsJWWuDbBjPY111xDI0aOZIHL1q1badWqVfTee+9SQ0MD5efn80sa8+cv0CpBHQjqT3Qfk0YX5AiCIAjCUAbfo8AQqgqCIPQX+uVHrj+CIAg9YPxWE+GLMOTAm3egyZe4RaN0q/ZREeGLIAiCIAiCIFxiwGJLOEiBtgry1myj9qoNKnzCAgvEY2Lf4h5GzoJFnD3kayJ/8zEKeE5r6TqwmuJvPsIh4CnngHVYQ+kkxJZVtHzHuC4ACyquwitYTKJqomBbJbehvXoTBTtg+hWugnLIVbSM4G6oKyA8QfA1HuC2w0qNhomsrkJVdrGqOkS+hn3kbz2pVjXLMVy3u5CcOd2/ZQNhCfbvbznB1lUCbWcifTeZHSyIgcAGoG70D+MRAeOrxov7rdoW8reyNRmIfCB2AUFvjdZnFbzVWzh/TB1R4FgZ+zfbM1j80udEaUL8fj+99tobVFVVzT7m58+bQ/fefQfdcvNN/CIFHqjs3buPDh8+rElMIs+gVSVR9YAjR4/S2rUfchmX00m33nSTqusumjF9Gqc3NzfTs889zy6PIhhPt6PqwoPuK5cto5tuupmWLbuKFi5cSLNmzaK5c+fSkiVL+e3Pm2++hTIyMs5u03kgz9cFQRAEAV/N2vepfC8KgiAIAxHje0oQhjoifBGGHJ0WX5IQvthE+CIIgiAIgiAIlyJwNeSt2kie029Ry7E/U8vR5zh4Tr3BAg0A1zZsqcSWSv7W0yrtTRZnhEMBTgcQsbSefI2DF+INFbAebOt0IRQOh6ijYS/How7UZXFkkTN3Npms2n1IyO8hT/kabkPrseepo26nKoj9mNj6iyN7Cuc7C4ha6vdQ64lXVN2vU0DVrSK1NHbHZKKO2s+o9fhL3DeIawxMZququ9PiSzwmVQ9EKyjXcuwFNVZva+ITHbMthexZk3m9vWIt988Q9QCME8aL+132rhrzahbbGKIXtBNCodbjL6t+4xg8y+MDEU9X4JiFDeGNxcHupPoEPBw0QkQgEqby8gratmOHig6T0+GgFddey9ZUVly7nMaPHcu5vN4OleczrVRnUeNPhM927mTXRGDKlMl07fKrafbsmbTsyitZzALg8gj7jCHmwaW2brXaaOaMmXTrrbfS5z9/H91z7+foc2p5r1ouWXol5eXnc86YZnCE+sNBi0oGzeKMIAiCIAgavfgyFQRBOA+M2wKx+CIIgtA9xjVShC/CkMOw+OIJhCmY4L1Khk0zN97U1PlwVxAEQRAEQRCEgQ8sr0D0AiGILW0UOXJmkjNvHrsDip68gDDF4syncKCN/K0nKBSAKKYzHaIW1MXWYNorOWDdEGgYhIMdWj5VB+qyZ0wgs6rXINRRTyFfI9nSx7Krn7C/JWKdRROoFPF6PBDptFV+xAISX+NB3gfEMAYQorRXred2sdWXFpVORrqJrcV0B9ddvoaFKGhfR+1W6qjfg87oOUxqbPJ4TbN0g35Hu44N83jx2LSe4v5wn6LEG2x1pmAR2TPVeKi2dNTvVu3cq6fGwqIaw2KNycwWafoCCFs4YJ2D1t79Bw7yEqSmprIbIS1fmGbN6rScs2//fvVXK4OuajmMetRftThw4BCngyuXLlV/TVxXaUkJW5MxKCsvV3+5Ei4f/Q+gLqxqbSay2x2UlZXF7dMLcRqv6GW0aOTXQiQ+KXpTRhAEQRAGF6GQ9rtHJp4FQRCEgYh2vycIgghfhCGHYfEloL4I2oPRD2u7J0NcHQmCIAiCIAjCJQmsqDjzF1BK6UpKG3UnpY2+h9LGfp7Sx96vi180YPXFZLbpWxcOszNP1evQt9R+rCmqLddT6ohbOECIQyZNaA9RRHcCFbgFgqjEIBwOsKjBAGIRiFIMQuZClnUAAOHNSURBVIE2lSf6fqf7iZqgr5F8TZ0CDRDsqGVLLgYmi1NfSwx/02GuV0Nzx5Q68lYVbiP3sKvJnjW1+74G2iNioP5BF4XgvwpnKs9o0QqHw0Ful4snvBBKhg3TU4iqq2soEAjGHIfoekKhIFVWdVreGTG8lELqmKCezMzMGOELXrLo8lmlXhdWDAELglEPB95GvJaXAwpyOD9kfk8QBEEQ8N2qfaeK8EUQhP5G+10v1x9BEIREEOGLMOQwLL6AFn9iwpd0u/YgGn7XfT7Dl74gCIIgCIIg9A1OpyYy8PoS+70qdA2EFa6ipZrAJHc2WZy5HB/01pG/5SiFg+283ZdATBP9kNLiyCZb2ohIsKaUqHR1vwHrKhx6d8zDoVjLM8kQDnj1tSh4gqf3wglf435qr/yYAp6yiIgFro+sKaXkKlxKaaPvYss7naKfKHTXTX0NHiJr//Rt1WcISVpbPXoMLKvYWKBiCE4cDntEsBIIBMjbocZOVaDV0vkXy44OH7W3a2NrsVjYbZJRj0XVYbN1Cq28Xm8kzfjHNRnbUUtN5BIfQjHbKqtaoma1HfmXPB1+rZRxTRIEQRCEoQh/typk3lkQhP5Gv/yI8EUQBCEBRPgiDDkMiy+gwd/5BmNPpOsWX4BYfREEQRAEQRD6mrw8za1MbYOIrs8HW/oYcubMIZMV4vcwBdrOUHvFB+Qpe5taT7yqudTpa9hdUKfkINhRT+1VG7oNHY1du//pS0wWO/7oWxpsjSUqLlkLLMjfXrGWPKffZgEMu1Hi8Q7xrBFESK7CxWR1dbqBMjBZHKoBVn1LEedO6oKBw8IhzBNaWIUllWCwc38Wq1WzqBLSQueR1AgjDk+juQ5EYB2LcMxLEyyWMcEKjF6X2g/EMAYsZsE/vbxWh76qVgyrLproBZZe9Ho4xIpeYoNWl16R+pMcxjUoJyeHl4IgCIIgCIIgCMLAAvd+giCI8EUYgtjtdvaFDsraEhS+2ET4IgiCIAiCIPQfhvClpqGDl0LvsKWNJJNNF76HQ+RrOkCe8nepo2YruwKiZFwbmSwqe6q+0R0mMkULNhTBjga16877jpCvmcUgLUefiw3HXqDWk6tYmNPfWBxZZEsdoW+pYbFnkj19bExfQqof3YN+2/V1DU1sZKKOuh3UevxFaj3xMrVVvE/BKLGR2Z7GFm/iMdszOvcdClLI32mB5UISjvzTt/GwUP2PFqR0dHTECEt8vo7IQ0Wr1Uo2u01P4yiuy8iLdOPNTIhpYCHGSIOLpA5vp6UdWJLhNH1bW9PyRkJIW2ril9gAAUx8nN6aqH/JY1yDRPgiCIIgDGW071X8shEEQehfItcfsfgiCIJwTkT4IgxJZsyYwcuDLYlNJKRazRzAyZMneSkIgiAIgiAIfYUhfKkW4cv5YbJBksGreFwIQYctbTTZM8aRe9g1mlWTbggH1dhHWRox29zkLLiMHNnTyabKG4SDneIFk8nMrnyQx5E9jSyOHHapBCsvBlZ3EbmLryR75kTVllEc7JmTyZk/nxw5M/Vc/YtJjYO7ZDm3G22BeyhYyzGmd9BHf/MRXjcIh6KsEZmtKv9YrXzWFB5Xe+YkNV6LuD6rexiPp7/5WKyIhQUaZ1tzsbgL1a414Qv2HfBW8foFR9OFcDuw5IfKqsspKSmcDHwdvoj4BaG2tj7y8Dk7O5ssZgtv87+oehDgysjl0lwEoWxdfWOkntbWVl4apKelqTJGWRWhB6MuuEyqr6/vJjRE1hsbGyJlUA+CUReHJDGuQbm5mpswQRAEQRiKGN/ZurdDQRCEfsMQvOD3vSB0h5wfgqAhP9WEIcn06dN5ebAlMdPxVvXjYlK6g9c3bdrES0EQBEEQBEHoKzChDmsRja1+8vo6J8eF5Ai2V1IIAhaFyWQhR+ZkShl5M6WOvI2cubM5rjvgFinoa9a3oO1IYbFM6ph7yF20TI9FvkqiiEUXEwtAkCd11B1qfRQFPOXUUbtdZdEEH7CE4iq6UrXhdkoZcTOH1NF3UNrou1Wb5nKe/gYPUyFYSVVtQFvcRUtVOzst5fhbTlJH/W5tWyfYXq3+aucmj232DK38yFvI4ipk4QvGmesbvpLcJddyX61OQ0ARpmBHnaonVtRisjhZHGQcG1iICapj0eeEtYeFCMOGDdMjidrb21lQgnhYbTlw8JCeQjRx/DiONyywGBj1qE5QcXGxHku0a/dunjhD2pkz6tzUy2D8CwsLO8tFYcSVnT5N69Z9QB9+uJY+/EAtP8AyKnyopX3yycecP75NvQHXHlyDYAEH1yRBEARBGKoY36licUEQhP7G+Ekv1x+hJ8733k8QBgsifBGGJJMnT+Zlebufmv2JTSRclqM9+N21axe/nScIgiAIgiAIfQXcc6anp1MgEBZ3R+eBv+kwWyoJh/y8DdGJPX0cu9cJemt7dKEDYYevYT+FAu16jInFLxZ7Jpksmige+Bv3U6CtgiAQAXDRgzxsTcak3XK3V23Q3Cv5GjifyWxTbRhG9ozxHKyuQpRU7bk49xlw+xTyNZHFkcltMfqHcfO3nKD2yo/UeNVwnEFH/S4VV6fW9Ikgi51dJmGM+KFsOKj6aeH6nDmzyFVwOfcVwhbUG/BUUPuZ9SwMigbuqazOfG1D1RFoPcnuofqCcPy/kOYyaMzo0ZTi1u7/PG1ttH3HZ3SmspIOHT5Me/bu5Xh8RmFJNMbtkPHP2FZ1TZwwIfKQesPGTXT06DGua/uOHZGHk0VFhSoURUQxMXXpbSovL6P1H32kh3X0UVxAHNI+3bKls01x/4xjlSi49uAahGtRtBUcQRAEQRiyyLyiIAj9jHHP0F/CF9yT+P1+8vl8kRBtqVIQBGEgI8IXYUhSWlpKGRkZ5AuF6UhrYhMJs7Kc7O6orq6ODh3qfMtPEARBEARBEPoCw+rE4dPdizOEngm0V1Jb+RryVm0iH4tgjrIQxluzlePbqzeSt3ozh47aHWcJLLxVH7Pow9e4Xy97lOvxNXXeD/iaD1NbxVry1m7juiP5VJlguyYWCfkaqa3sXbVPla9mS1Rb9LwNe9S+NpCvbgfnBxDmoJ2R9tXv0lM0Ap4yFb8lko79RXOu9GgguGmr+IB89Xui2n+AvJWfkOf0W9RR95mesxNf/W7ud0fdLpXf6PcRLgcrLdo4f9ptX9vK3qH2qk/02nRgOSZnFplsqbyJ4xHf7wuGoQOJCoZgpKAgn+bNm8dWl/DQ973319Ibb66ml155hWpqavih8+jRo2n0mNGdQhUVjHqi42ZMn0aZmZkqgai8vJxefvVVemP1avpkw0ZOT01JoZUrVrCwBNsQuTB6XUabUlNTqaSktMvgdLnYGg1CsbpuGPtGMOrhkCRH9GtPQUEBLwVBEARhqMLfqQoxuCAIwmAEwhbc52zdupXefPNNevHFF+mll16KhFfUfdCnn35KlZWVfM8hDDyM7ylBGKoYnwHLDxW8FkcgEJALmDBoga/13bt3U1lZGZW6bTQ1Q/O73hMpVjPtbe6givYAm3meM2eOniIIgiAIgiAIFx48VIK1QX8gRAunZZFN/R4VkifUUU/+poMsBPE3H2IBCAQZsCSC+I76nRx8jfsoFIi1uAL3RFy29TT5WyB6OUC+hr0s+iDdwguAxReIYQKe02p5kPNBLMKWYHTCQa+q4zjvP9IW1Ie8tdtZ5AKhjkGoo4FFIkb70I5o4MYJ7YiktxzTUzR6Soe1GUfWVLZOA0L+Fmo5/AT5W4+rcEJrl+qnt3rTWZZeIqj+YwwDELSoJfe7UZWr28kujHhMGvZ139cu3BfB2ot72NVkhvAlHFDt3k3tZz6KGesLRThsov11mrgsFAqqXQRp6uQJrA8xm8xshaWmtobaPG3U2NhIJ0+eotraOnK73WwRZvk1V9OIEcMjD1cam1roVBms14Rp3JhR5HDCao5mLaWjw8eWY9pUqKys4rogqMnLy6W5c+fQiuuu1XQpqi5U99muPeqeVR2bUEi1aSKnOZ0udps0dtw4GjduPC8RioqL6MTx49Ta2qL26aSV199AOTmaO6mm5mZuE+5/QbqjjUrS6nn9XHT4Q/T0W2VUVu2lK664ghYsWKCnCIIgCMLQY8uWLbR//36aOzmTJo5M02MFQRD6nopaL32wtZZKSkrommuu0WMvHM3qnmHHjh30+uuvs+AF4f3336d169ZFwtq1a+nIkSP8jAL3P1lZWer+5Nxzan0B5q0xfw13rJcyGMeOjg4ym80XxJoPjiHmPGeVpHIQhIvJZ2WtKnho5syZHPoDvLiEIE9OhSGL4e7ocIuPl4mwINvFy82bN5PX6+V1QRAEQRAEQegLrrzySrYCsfNQMx04Ia42zwd2rdN6ivzNx9h1TzjQpqckRqD9jFZWBdRjuE6KBnWibiOf5gbobGLaco68/Q3aYbQJgpVECPoaWdDD5dQS2wbJ9NVsTydX0VIyO7LVVpgCbVXUXrWxy7G+UEBkEhs6LaXk5ubQbbfcQldffRXNnzePZkyfziKVZcuupFtvvYWmTZsayQurLKqhal2vB/9CWprZbKHrrr2Gbrrhelp8+eU0a9ZMmjljBl122SJaueI6DtwWPX8Y9Rht46UWn56eQWPGjqUxY8bSaCxVGDV6NLvhramp5gfAI0eOohEjRnL+ThdMel1cGfaUGEfL2mjn4Wa+Bi1btkyPFQRBEIShCb5TQX+5GhEEQegPqquradWqVfQ///M/9Nhjj9HOnTu7nfeCqOLJJ5+kH//4x1ymtrb2/2fvPQDjuK5z/292tqA39t577029F0uWJavbqrYTO44dJ05eXl5eEidO8l5ekn+KE3fJcpHVLVu9UGKRSIqiSIq9k2ABQILodcvM/O85M7M7u1gACxAgUc5PusROu3Pb3Lkz95tznC29C/W/LS0tOHnyJFukoXOfOHHC2dq/oGc28ihx4MABFhNt3LiRxS89gXufEoTBjghfhEHLzJkz+e+RxghajcxuCguKstnd0fHjx/vtzVUQBEEQBEHoH0yaNAlz5sxBJGpi7dbziGU4ZhWEfoemI2vIEgSLZ0NTv81wHVoqPgC5S+pd6JqyA/3HYhGT/pKIxWJrKjfffBO+8OADeOD++/DFLzyIO26/DVMmT1LHaGwSPHGMJy5HxEJui0jIEggEsWjxItx//734wgP348EH7sMD992Ly9asQV5+fnw/+uuNR61MSpN7Pv6rQl1dLTasX88vp/3+AFauXI1QKBQ/xn756Q2ZQ1+VtoQN7oMoCIIgCIIgCIJw8eEhvaKnhXckwCA3Rj/4wQ9Y1OKFPB6MHDmSA1mw9HL06FH88Ic/xEsvvYTq6sysSV4IkUgEGzZswI9//GP88z//M/72b/+W09AfIfHOL37xC3zve9/Dd7/7Xbz88sucv55AhC+CYCPCF2HQMmXKFPaTXhmOobQ5s5vL6Gw/puWTyWpg+/bt/FcQBEEQBEEQegsyZUwvuLbtr0VpedeslAhCf0HTfIDPj0j1HrSe+wjN5evU383O1t6D3g26gXUmjlgkNYRCQRQXFyE7K4uXWVjSJnjjs4Uq9t/EPkR+fj4KCwvZNLe7PnU/9b8dKFntpImEL/RF5qlTJ9nU92T1fDtt+vQ0+7ppsuPLhIqqMLbureG+h6y9kPltQRAEQRjM0D2VEIMvgiBcbBL9T891QCScJ4sjTz/9NAtgXMid0jXXXIMHH3wQjzzyCIf77ruPrdGSCMaFjiEBBwlSyIVrb0JpJSsv5IKpI4s0/QGy9EKiIXIlRW6jBEHoeeTthTBoKSoqilt92Vad+c1yUZHtu3DTpk2oq6vj34IgCIIgCILQG6xYsQKjR49GXWMUb2+pRDhiOlsE4QJgFYThCZe2XZE7o+Yz76D+8M850O/edHGUgF4i24H+Y2sqruUVDt7fiWCx5RXPNkfkEo9L/abA653t3uOTgx2Xux/9jaeL47DXJ+2v/tbW1GLde++xaWwS0SxfuRI+3ZfYj+LypMmNLxPWfXIe56rD3PcsXbrUWSsIgiAIg5femHgWBEHIBLffcfuhnuDQoUN47rnnktwV0YfiDz/8MP7qr/4KX/3qV/k3hT/6oz/CX/7lX+L+++/HmDFjnL3Bxz7//PM4c+aMs0a4lPRk+xCE/owIX4RBzerVq/nvpqpm1EUN/t0ZS4qzMDSkY9++fdi6dauzVhAEQRAEQRB6HrIOQV9cEZt3VeOTA7X8WxAuBKO1Eq2VH6Pl7GYO4epPnS2DC3o36AZbF5IQrXQU0lt8oQjsuFisYqbfxxu88bi/6a8bj/o/vt0bSPyyY8cnKC09wdZeiktKMHHipDT7uvmyQyYcOtmIjTvsrz6p7xkyZAj/FgRBEITBDN1XCdG9CH0ZX7AAetZQFYZA82c7awcOAz1/7eGO43tKeEcWU95//33s2bPHWQMUFxfjC1/4Au6++26MGDEi6Vz0mwQvJHy54447kJ2dKHvyirBlyxYYRmJurampiV0ReQOtS4WeY8j1j3e/mpoaZyv4N607ceIEmpuTrd9WVlbGjzl+/HjcCgz9pWV3GwU3Topj//79ePfdd/Hb3/4Wr7/+OrZt28bWa9w+3gs9c5WVlSXFRcu0PhU3rW6gfFH+CG8+Kd1eKE2UP/e4c+fOOVuEgYCWXQgtb5gnDAX8QWer0Fvof6NwfidBF6O3sxKEgQiZmCZzbGV1DZicG8REFTqjKKijKmLgQH2YLb6sWrUKWVm2FRhBEARBEARB6GnIp/bhw4dx8vRZlJ9vxbRxeSgplIdlofuYkVpEavapsIdDtO6ws2XwYFka9p0fzb9N0+Awe+Y0+8Wy+of/U7/5JSgtJwX7BbT6FV+ur2/AqbIyOhhTJk1EKBTi9bwX728flByPuy2xH7Fr7z4EAn5KmEoTuS+izWq7s08kHMZvXnoRZ8+e5RevK9Qz6cKFi3mbvY+9X12DStOZMhVXgOMtymrGuILEy+RUTla04Ke/PYl9xxsxY8YMfrlN/v0FQRAEYbBDE7sHDx7EijlFmD4+z1kr9CcC+ZMQLJwGPWckaErfjDbaGwYQ2cNXIzR0AecVZgxG68CaRB/o+WuPM5WtbJGR3BBde+21ztruQxZannjiCX6WcLniiivw0EMP8XxZe9DzDYniyd2Q99icnBysXLkyLogpLS3Fj370I3zyySfxMH369DaCehJ9kNUZcvvj7keiG8onsWvXLnanROIa6n8bGxPXLFm9pHV0DAlHKH76aIiEJb/+9a+xcePGpDj9fj+f59lnn+VzkuskmhckyzfV1dX8zoXS53XxSi6c3njjDbz66qvxuOi85EWCLG56cdPq7kflM3fuXASDwaR80n4knnGhOXhyebRjxw4+jp7bKC/dgUQ8e/fuxaKxeRx6DJ8OLacEWigPWjA3EXT1jBkLOzsJ6QhMuwL+8YuhD1f3HhV8QybBaqnlMNDZebpRhSYsXLiQw8WArnMKYvFFGNSMGjUqbvVlw/lmREznTWMnXDM8l62+7N69G5s3977veUEQBEEQBGHwQiaHH3/8cUyaNAmHTzbhF6+fQm3jxXADIwiDBxKLNDY1oaWlBc0qtLS08m932Rvc9d59mjxfITY0Nnr2SYT240ks07EaT8cA9HiaLk2VledRXlEOzafD7w9g3ryFvN4OnjQ1JX8Z2RFNLQaefusMth+ow7hx4/Doo49y3yMIgiAIgj1OIAaTqyMSF2QNX9FOWI6sYcsQGroYwaKZ0LOHq8JJngjuS/gC+cgddxPyp30BBVMfRPaoq5wtA4tgyTxkj7gMWSNWw58/0Vk7cBjo+Wufnu1/SChCgg8va9aswbBhw5yl9qHnhGXLljlLNmQ5xmvJhKy7vPLKK0khncUXEn2QVwXvfiRCcaHftO7NN99EeXm5s9bm448/jh9DgpFIJMLr6S8tu9sokJUXcsn07//+72zpxnXvRNZhSMTzwx/+EP/5n//JHxu5fT1Bv6msvHHRsncfFzetbqB8uYYlvPmkdHuhfFH+3ONIBNNd0qWr26jnTF/JeOjjFiEwZQ2Cs29EcO4tSSEw83r4J6+CPnYhtJxi50DBiz52AfzTrkyEKZfBV2h/fCP0HiJ8EQY9V111FatRd9e14niTfYPsDLIOc/mwXP5NJtG8N2RBEARBEARB6GmWLFmCL37xi2yCeOveWry6MfGFlSAI3YNeDlKwhSYaDh4+hkNHj3crnCmrgO7Toet+HD9emnafDsMR++/BQ0fsr5ToyzotfZqOnChF0ZDhGDdpCsZPnoaWSKzNPhTOlJVzmtx8dvQu9O0t57D+k/P8bPzggw9i+fLlzhZBEARBENwJxcEkfCFxQcG0h9oN+VNtEUnepLuQO/ZGZA1bCn/e+D4pgPGFSuDPGaXqz6+Sl4VAvkqnIPQTOhrDdxXqy44dOxZ3DUTQOway9ui1dtIeZMGEPsjxcurUqbiYpCchqyojR45kiy1kbcYLpZm2UcjLy+uwb37nnXfY4go95yxdupQDCXi8rF+/Hi+++CLq6+udNT0HpY3OTWmldHuhfFH+3LzQc+Clxleg0jFxOYIL7kBoxUMIrngY/pnXJQs4VAjMvQWh1V9CcNkD8A1NbhPCJcYf5HrUQvnOisGFCF+EQc+cOXPYfFhzzMSGyrbK0/Zwrb6Q+bAPPvjAWSsIgiAIgiAIvQMJtj/3uc/x72ffPoNP9tfxb0EQuofmfD1JL3n9gQBOnDyNI8dOcDh89HhGwd2/tr6Bra9QqKyq8cSTWVzu/qWnyxAMZfGL3vbSRPHPmLMAs+YuxLRZc3HkeGnauChNukqPi6619UdPbNtfi5+/dpp/k/n0G264gX8LgiAIgmATF77wv4MPy4zBijV7Qotaa0LzBeHPGY2s4SuRP/ke5I2/DaGSefAF+pY7KDNSg0j9UXb3abSeR6Q22dqFIAwWyPpIbW2ym5WJEyd2yb1pOsswdXU9/26CxCkPP/wwu19NFapcffXVvI0CPbuQ+KU9yGsD5ZGs6P7pn/4pB/qd6n6FXBGR1ZeehsRC5EqK0krp9kL5ovy5eSE3SpcSErAE5tyM4LIHbUsu2YWk3HG2pkFtYxdI/ixnhXCp0HKKoA+bZlvpmXo5ArNvYqs9gxERvgiDHvKbd+WVV/LvrdUtqIrYJsg6w2v1hXz99YaqVRAEQRAEQRC80EsRctUZMyx8/8UT2LCjCi3hzMavgiAk0DQL+cFW/oKSbL6QpZZAINjtQIIXfvGngj/N9q4E22d8z6SJ0mPP1VkoyU7+0KO+KYb3Pj6P779wAq3qOXjevHl47LHHnK2CIAiCILgkLL7wn0GHGa5Gc8XGpNB6dhNazn2EaMNxWLEmaHoIweJZyJv4OWQNXwVfsMg5+tJjRurRfPodNJe9h+Yzb6Ol7H1niyD0fZzuh8f1FwoJX7zWXggSZnTF0kh+/sWxIjFr1iw88sgjuO+++zB+fPIE/mWXXcbbKNx7770dCnfIfeu3vvUt3HPPPZg/fz4H+v0Hf/AHbGXFhdwOeV0U9RRZWVm4/fbbOa2Ubi+UL8qfm5cVK1Y4Wy4+JJIILvgc/JNXQwvmOGs9WKbqTFXZUKDfQp/CP3EFAovvRmjlwwgufQD6xOW2cGkQIsIXQVDQDWXo0KEoa4nho6rM/aC7Vl8OHjyIdevWOWsFQRAEQRAEoXegCfE//uM/ZvFL+fkw/r9fHcMbH55DZU3Y2UMQhEwgay/ThpxDcVYTcgJhFSIDNuSHWjCuoBrjCmuc3AOnzrbglY0V+H+/OIKyylbMnTsXv//7v4+ior4zSSUIgiAIfQVX+DJYTb4Y4Ro0lf4uKTQcex4NR37Jv5srNiDWeFoVlAE9ayhyxl7PVmDIrVBfIdZchuYza9FS8SGMSLLFC0EYzJDQwzQzFzL0tDCktyGLlvSs4xUO0W9at2zZMmeNTWlpKSKRiLPUv4jfp7qBVjACgXmfgT5yFuDzuquzYLXWwzh7ELGjHyLqBPptnNkFq+GcahBR3k+4tOhj5kEfPhVaVgE1cGft4ESEL4KgGDVqFE8eEOsrm1DdDasv5CuQBDCCIAiCIAiC0JvQ10z0xdL111+PQCgHP365FC+9X47jZZkLuAVhsEPvgqaUVGLeiDLMHFqBmUPODtgwe1g5lo4+iSx/lC1E7T3WwO7Sfvn6aeTm5uLyyy/Hl7/8Zf6qUhAEQRCEtiRcHQ3uyaR0ROoOoan0VTSdfh3R+mMsfvH5c5E9cg2ChdOcvQRB6C4XImhIhT6kIQskXs6ePYumpmTLkB1RX1/v/EqQnZ3t/Op7kPsgsmqTCrlHGjNmjLNkQ26golEScvQ/ut1OfDoC066EPnp+sujFMmHWnkH0wFpEPnkW4c1PIrLlZxzod3jrrxDZ+wZixz6E1VDpHCQIlx4RvgiCAyk/hwwZgj11YXxQmfmN/uphuSyAIf9/TzzxBE6cOOFsEQRBEARBEITegcatf/Znf8Ymc8k878vrKvDLN07j08P1KD/fyq6QBEHoGF2zMLagFjOHnsPMYRUDNkwprkK4tQWHTjaya6Of/rYUa9VfetF722234dvf/ja7ORIEQRAEIT1x4YvoXtolXLULTafehNFiT4DqwWK2+kIimLRoOvy5YxEqWYCsYctUWG7/HboEwcIZ8AU7dtGgZw9HsHgO728fax8fGrpYHT8dvkCes6dNIH+i2n8uH0PHtgcdFyiYyvF40xUasgD+nFGcH0ofx0XpTMkfuXgKFs9O2k55oXVZQ5c68anA+WybzouB5guq8pik8rQwOY8qz5T31DT5c8bY+VEhQGImVXcdESiYEt/fnzPaWZuAy0OVjV13nvOrtkBtorP4Bx1Ox9MTro7IpRF9BO7l1KlTOHPmjLPUMWTt5fjx486SDXlS8LoM6msUFqbvS6gs6CMAL+QGqieFRv0BX9FY+Mcugub3ioMsmHVliO5+VYVXYFa1nfO0GisRO7wekU+eg1F5xFmbDFkf0YdPh3/CUvgnrVRhlRPU74nLoY+eCy1vmLN3W/Shk6GPme8J8+ArGKEqL8jb/OOXeOJdydu17IQFU/pN5yA3QPFzq998XrKMkgZ9xIzkc9K+OcXQQvnQR87kdHvzoY9dAC2//XtKV6CyoDwkpZfyN2EZlyOlwQuli9JH6Wzjnkrzqbodk8iHylc6unrO/oD+NwrndxKxWKzfmawShAthxIgROH/+PPvxq4qYWFiUhYJA54OskqCOISocaozgYOlpVrzOnj27zU1TEARBEARBEHoSevG1ePFifmFD49hd+8tw7EwTKqrDCEdN9Uxnwq9ryFJjVUEQBh+GYXF/cPR0EzbuqMbarZV456PzqG3SMGPGDNx5553sUz4UCjlHCIIgCIKQjg8++ABHjx7F6gVDMHlMyuTSACVUMh+BvHH822itQmvlR/y7I4xwFfTsoeq48ephRYfPn41Y0xl1/DlnDxsSVgSLZiF39NXIHnWFI7pYyOKSYMk8FqmQmyQr2gAz2ugc5aDiJUsyOaOutI8dvgJZQxeziIOEE6HiOZzuWHOFOu955yAgb+LneP9Q8SxYsRZEG5In7wly05Q1fDlyR12F7BFrVLqWxOMNFs+EL1SsnsF8yBl3I4s2AgWTEGs8CTOScCcZLJqpznUHH0fbzUgtl2UuuX8asVIdt4i3cT65nHxcbpZx4a5rqSwoD4DJ1neidYfsDR5IkETnzhlzHXJGqjwOXRovey47Ep74Aqrc67iciKwRq5A77ia7Tai6idUfhRlLqRcHPViEvMn3cFpCqswstV+0ITFpTsIWEkTljLma4/XWHZWdP3sYl4UZrVfZiDlH2WSSv4HI6XOtWL+9CuPHj8c111zjrO0+DQ0NeP/99xEOJ9ociWEWLlRtNhBw1qSH3js8/fTTSR9/k/XIW265JW71paKiAi+++CL/dvn85z/fRhxD51+7dm2SkObGG2/EtGnJlqIy3Y+oq6tjzwxkxcblc5/7XBvLLgTNgW/atAnbtm1z1oDn9aiMyUIMzY9v3rwZn376qbMVWLBgAVatWsXvYLwcOXIEb731lrMETJo0iT+0T7Wuk+l+3WHr1q3Yv38/Fo3N45ApgVk3sHgCvoSdDCvSjNi+txE7stFZ00V8qv8vmYjAZFVWM66Gf+rltrBiwhJbrDJ+MQtG9OHT4MsuZHdJ5FIJZrImIbjkHgSmq+PVvhxUOq1YFL7cIQjMuQn+aVfBP0nFS3GOU3GSqx9d9V9N1WqfYgSmXIbgnJvhV39ZfMP7LeLz0vs0s1Hdm6KtztlsQqseU8etjp9THzkbVksti0D4nFOvVHlZljjniOnwkYgm3ASrudqJxcav4vF5hT2qTyMXUWbNKWeFgyovffgMldcrEZh5HfyT1fndc1BZjZmvynO8yltQlVMdELENN+ijZiO4+B7eR8spUdsT7ZLy58sbDj+JWlQ+SOAUO7bJ2aro5jkzZefpRhWauF+hcDGg65KCWHwRBA90gx43bhxONEXwSlkDImZm6s4VQ3Jw99hCFAZ0HjTQjZ1unIIgCIIgCILQ23z2s5/FI488wg+TLWYh3tpcie+/cAJPvXoKv9twFjsO1qG0ogWVNRE0tcjHDYIw0GiNGKhtiKKiKozS8hYcKm3E7iP12PhpFZ5/pww/fKkUT795GkfLgXETprCbtK985Su4+eabnRgEQRAEQcgEDWJVsTPC1bthRu0JMi2QC3/+BP7tovmzWehCQhQSYGj+LBjhahaikEiGJgbJSkjOmGtUuB56qMQ50iZYMAV5k+5UcaxgEYcVtYUVdLzRWsnuOciiiy+Y/JW6L5Cv4iq2xSv+tuIlOk/26GuQO/ZGleaJ0Hx+GJE6FrbEWspV3fuQNWQRskdeDn/WUI5LDxaq/ZKFAjRJSOIP3q5C1rClyBl9lVqv8tlcjlhzGQtKKH4SgeSMvZ4trVwMyNJK9qjLWJjDbqgoj6rMog3HWChEUN5zx96g8nlF3PIL1Qvlk/JDdUPWa9ojWDKXhUe0L5VZtKHU2WKLXnLH3azq9Vq2nqMaCsfNdafaAAmlqE2wcKh4rnOUkLA41TMmpyZOnMgCDi/r1q3Djh07OjSGQAIUEoLQfi4klKGPcQoK0lvPcElnRYXmz7o7h9YVqywk1kkHuXdKtXRDAqCOPgpo77yRSMT51XUuqYUZEqgMnaQ6wGQhj1mt+r3Sj52lrkMikeCiOxGYewtbZtEC2dSAna2Exn2lL38Ei1eCS++Df4xqk15XSwotKx9a7hBPKIFv2BQV913QR8x0rJw48ar4yXqJf9b1LJYJzP0M/LNvtK2xeONVv2kdbSOrJqloOapfTzmnrtIWmHcrfMXjksQlfM6cEvinXoHAwjvV9rHOhi6g0kOCHi4DVRZsASepPtQ5/CEuR0oDiVS0HNuqDd0/2RoNpTOQIp7SfLxfPB8qX3Eu4Jz9AU1dVGmvKjLp5FX8CcJg4dVXX8X3v/99BGMR/I+ZQ7GgKHO15dMna/H8qXqYquP48z//8x5R4AqCIAiCIAhCJtDXQ2S98OOPP0Z5eXncV/e4kdmYPDoHRfkBDCkMYlhxCDlZPhV05GY7D7fOUyH9odcGqQ+J8eWkx8fkPRP7OH9TaLPaGxe9BFHL7cXRTpTJyXGgWNRjurNkLzs/0tJmtVoRX0c/ElG12TmRYu9Oan2ahLlRxbe03YVJ2i9lH08JKRKxpSsHgta7KWtnl8SxbXa0f6Q9LmVlYtH9ZUeWSFfbPfhHIgttaC9PRCIO+5cdFU1FpT/Ijct915Yu7qR1adKVyQvJ+B7OD/rTQRadc7pbncSl7N3ZaWlzfWMU9U2GCvQ3hsZmCgbO1rSiQa2nryvJwimJ42bNmiUWSgVBEAShi/zjP/4jWxH40y9OxTXLyOLEwCd/6oPIHrGaf0dqD6J273/w784ggUTxvD+Bn63FWGit/AT1h560NyrI4knuxDtBQhPLaEGk7hAiNfsRa6lgcUiwYBqLRUikQZY/mk+/iabTb/Ox5DaoYPrDCBbN5qFTrOm0iv9jxBpPqzOZKs6h8GcPZ3FGy9mNCFfv4eOIojnfUMfNUGOrmIrzHTSdfNXZotDUc9HYG9kKiqaHOF3RuiMqbYdt0YtKV4Dc/QyZr+IfQQdQRtmaS/2hn6v9DtrxKMhiTP7ke/kYy4ioIjAQay5XedyLaLMtIAnkTURIlYMt6rHYekndgZ/YVk4ugA7zqMgZfS1bbiHhjxltUPW6T4VDLH4hsQ5Z4SHLL+72xuMvcvlSmgtn/R5vp/SGq3ag7uDPOG9JqHIsVPXjCnnCVZ+qfP2Yf/sCBcib/Hm27kLjdqPlnNq+E5HGEyqaVlWuo9j6S6BgMpctCWbqDz2h0lbFxxOd5W+gsmlXNf7uJ4dw2WWX4W//9m+dtd2HxCbPP/88/uVf/oXfF7hcccUV+OpXv4qZM2e2sUBCVmK2b9/O82ZeCyj0XPEP//APbE3SZc+ePXjsscf4GJf//u//xtVXX+0s2dC7C3LfTNa0XP71X/+1jTifrLj8xV/8Bd577z1nDUCOTO655x71fOc+Q9mUlpZynLt27XLWgAX/lC9vnujZjvLzv//3/06yJPPXf/3XuPdedf2qeEnM8h//8R/46U9/6mwFu5qmtHjdJ9Fc+o9+9CMuGxeaF6RySXWz9MYbb+CP//iPnSVgxYoV+D//5//0iKuo733ve3jppZfw6MoRKmQWH1kjCV33bfjyvVZJDET3voHIzpecFV2DxB/BZQ+y+CX+AE4YMVhkNcQyoQXVs2iqa6XaM4hs/SWMswlLTlnXf5strsRRfQ5ZfCGrLlbYEViGVFxeYYvCaq4FgjlqP7/ar5GiT7ufWXkErev/C1ZLnbMGyL79u/AVely00TlVmfA5yTpMpEXFne0ITTz5U/vEjm9B5OOn1X6OtayU9NPxlEev5RWyUhNc/pAqN7JK5MQXa4VZV8Hx+MiSS54adzhppzJkF1T73mK3RMHlD7AAhvrNpPImqI923ieY9WVoeeWv+feFnDNTntxSocJZPPzwwxwuBiRao+tchC+CkEJjYyM/zJB6dWlJNv54+lAUBjIzjmSoy+lfD1Vh3bkmFBcX46/+6q/aqGcFQRAEQRAEoTepqqril0h79+7lQAKYlpYWfr6jl1zk/qi4IICSgiCGFtkvG9zHQvrXFhC4OOvdFc5fe7/4IuPu00Zo4jxHt43DXeGeU/3XZp/kv3Hc7Z50u9Aqft5397H/JOKOr7ETlrqe/o0/JtMfz8uD1Mfn+KK7i3uY+hvf09mJ/qUXaPE0x3dwSayP7+fs4+7q/rUjc/7Sn/h+8T0Yjsv9Hf8b39n+425wdowvO9jJSN3J/uP+SByTvJ+73puu+Dr1l4o2cWwyibJ24monjnTEVzs7uPu5L0Yp7vb2oT/eenLxbmd4hVMeDm6siUOT90leby/HV6XibEic193Tjc9eTsQJNslNL3u8gb5aXLZsGb+Unjp1qrOnIAiCIAhdgSYw3333XfzZQ1Nx9VIRvnSGK1AgvMeSmKVg2hfVtplqEGMiXLMHTaW/i1sbIUhkQdZgstS56TdZI6nb/2MWhQTyJ6NgxqO2aMaMovnUa2g6/Y5zZAKyLEKWYIxIrbOmY9GEP3cMCqY/Bn/OSJUugwUzTSeT00WQICd3/GegZ9mTxJ0JXwijuQwNx19S5bCflwnKF8WTPepK/k3unBqO/pqFIBdCR3kkKziFMx63y8aMoPXcR6r83kwqI9tN0d3s0ogG6ixcOfgElwkJZnLG3sTpJdFK7f4fqr/J5aNnj0TRrN/jc5GYheq2uXw9b8seQZZmbofmz4URrlHnfh0tZz1uNxTBwhmq7O6BruqBRE9NJ19Dc9laZ+vgFb58+Gk1vvvTQ+xS6Dvf+Y6z9sIgSyf/7//9PxaTRKNRZy1w5ZVXsusd8opA81tkAaa2tpbfL9C+XmsvJSUl+IM/+AN2Y0TPIS4nT57En/7pnyaJTx588EE8+uijGDZsmKo/C5WVlXjhhRfwwx/+0NnDJp3whQQ0lO/XXnvNWQPccccd+OY3v4khQ4bwew567iHrM+mELyTk+frXv45FixYhPz+f83T69Gn87Gc/S3LJNHr0aD6/O59nmiZ+/vOf4//+3//Ly8TkyZPx7W9/G8uXL+c803sWEgL953/+J3bv3u3s1b7whbxFfO1rX3OWwB8nkPhm9erV8Pl8LLahNHaH7ghf9LELEVr1KFtWcbFiJM74FWJHP3TWdAGfjtCKL8I/eU2SyISEJUb5Xph15SwQIQsk/jFzoeUN577G3slC7PRORDY/aYtVFG2ELwS5C6o8CqNsLy/qo+dAHzZFnS/Zag3tZ1YdR+zMHo6b3DnZ+3nS1dqAsDqfoc7r0kb4QlBcNadgVBxkt0dadhH0UTPhK7bd1bmQq6PwBz+Gcda+J3QmfNFCeQhSeY1fkognFkbs5HbEjm9mAY8+ZBJbp/EVJdJkVp9A6/v/CR9Zo5m0ShVCAH5VDmR9Jo4qZ/PcYRiNlfaySndk528u+JxWc8K1X0eI8EUQ+hh0AyfxC5lB+/rUIbh5VOY+8aoiBv7pwHnsqWvF9OnT+UYoLxgFQRAEQRCEiw29qKEXVBToZVV9fT2LvOk5j16o9MQznyskSEdH2zrjUh2bSlfj6sr+Xd3X++jeW+fpjAuJ60LT0dHxAyGPXT3W3Z/aBb3coZc89JLUG/Ly8ljwQi+EBUEQBEHoPn//93+PtWvX4n88PA1XLRkc99XeEL5kDV+F/El3gdwdmeFq1B/+ZZJoxIVc5RTM/AoLXLyikGDhdLb44gsWsXij6dTrLIDIhI5EE+x+Z+yNtgiltQr1RyhdCasDXvInfR7Zo65QgzG9c4svVhQtZ95DY+nvnK0J7Dz+nspjMYt4KD3NZ951tnaPDvM4/lZ2HUV5JEs59Yd/wX9TITdUJD4hqy9kCaZ273/xXxLMFM78Eot+0olSCLYoo85DVnOijSdRf/AJPpbKgo61BU9kBWirqtNnON+p5E+5X7W7Nap8yWLMTraE4zJYhS8f7KzC3z9xmC2ykKWTnoCeIUiwQVZf6K9X/ELPFiR8mTBhAq8nkYjXKgtRVFSE2267DV/+8pdZzOLF/bCcRBguQ4cOxU033cTzZPSe4tChQ9i2bRtbqvVanUknfKF3F2QxxiuSofjI+gqlkQQvZA2H0pFO+ELQM9FVV13FQhPKE21/++23+Z0IQXGQ+2iyDkPPUC4bN27k+T16l+JCHxWQsCUnJ4et0dAH9JQf+gDJpT3hC72boTKrrq521oDTTnXr9/s5PySC6Q7dEb74J69GcPkXktzkkHWPyJafd8vVEQklQlf9IbswihMLI3p4PaK7XrEtvjgEZlyNwPw7kkU3rfUIb34KxmlbYJVO+GLWlbEwx6iwxYT6yFkIrn4Mvtzke7PZcJbzkdhvttrv0aT9yCpXdPsLiB5I9L3phC98zm3PwChLWBHTx85HaMVDyWITI8qWUSK7X+HFzoQv+thFCK16WJVBwlUYW6H58KewVPpdgovvRmDWDXHRjhVpRuTjX6t4EuKkTKzLED15zo4Q4Ysg9EHIPNkzzzyDKXlB/M+ZwzDKNQOfAUcaI/j3w1U4pv6uWrUK999/P+bOFb+UgiAIgiAIwqWlubmZX0RRoJc3XvPD6fBOrhOpk/MdTda3t297cXnpynlSuZBjU+ns2IuVTtrmfXTv6rFeUuNKpStxdYZ3/86OTU1X6v4dHd/evpm0tVQuJK7OztNRXJke6+KNi3zq0wtaemErCIIgCELPkxC+TMVVS8TiS2ckCV9q9qN23/f4d0LUoLEll8bjv+H16cif+gD8OaOSRCF69ggWUJArIzUKYhdB5AbJaD3HVkg6oiPRBMVJLnhUwhCp3sXWTNojNHQJCqbcZ7sD6kT4Qu6CGo48jbCKMx3FC/4HAnnj06YpUDgNvkAHlh9UuUQbTvA5XDrM4+yvIVQ8R/0iV0W72hXZUBnnTfgMi4vMWJOdfscSTeGMx1Q5LeL6C1fvtkUp5EpDweKW6Y8gWDKX1zWXrUPjCbt+/fkT1bFfskU+5L6q7D3VLvbxtlTITVL2yMuh+fyINpai5tN/craI8KUnhS8EWT7ZtGkTWzUhIYhX3NERZBnluuuuYysu48ePd9YmIGELWWchFz5egYcXen65/vrrceDAAbZS65JO+ELPO2Rxi/KeLr758+fjn/7pn1g0kk74Mm3aNBaltJcWeoZavHgxW6mZM4eukQQVFRUsYCFXd+1B8370AbxX6NOe8IXSQOXyyiu2MCIVEtk8/vjjzlLXIKszv/nNby5c+BJuRJgEIye3OWsyJzDregQW3qn6x5CzRrWHmlNoXf/fSaIKQtMDCF3zLegjZzprFGbMcbNk9x1thC+qLcSObFTp+5mzwibrxj+3XSu50H4ntrD1FS9ZN/wZ9BEp59ujzvdp4l6UztVR9MBaFr6kknXNN6GP8Xr8UOc9thnhD23BXmdilKAqq8CcmxLWatS1Q+mOHlpnLzvoo2ar/W5R5epYViJ3VPvfQmT7C/ayIlPhS0+esyNE+CIIfZBTp06xqyK6Wd4yKh8PjC9EcTBhBqsztla34IXTddhbF+YbJl3cdAMlk2WCIAiCIAiCIAiCIAiCIAhC3+fv/u7v2EXFnz8yFVcuFuFLR5AAomjOHyKQP5GXW89vQ/3BJ/l34eyvIlRsfxxKlkDMSPsT7XrWUHaNlCpyIBdBOeQiyJ+jliwYkTpEaw+wEIOEKLGmMrYGk0pHooniBX+GQN4E9ctEc9n7aDyemMBOhdzxFEx/yBaGdCZ8SbPdS9Hcb7IVm/aEKrStPTjuw79CtP6ws6bjPJYs/J9stYUnhFsqYMWanS1tIcERlS+5K2o49ixaz23l9VkjViFv4p3wsTWYKtTu/z6M5nLeFiicisJpj8AXKlZpq1H5fkrl205baNgSVSb38XFkYSHWXKbSYQtm2uALsOspTdPVfuWo3vFdZ8PgFb5s3FGFf3jyMLsh+uu//mtnbc9A4hcSnrzxxhvYvn07uykia7GpkDiELKqQ0OXqq69mcUqqpRcvJDR54okn8NZbb7FbJS8knCG3TeSu6Mc//jG7UHJJJ3whKL6f/OQnnE5y5eyFXBORO6L2hC8kaKHj33zzTZSVqbbngfIwb948PPTQQ1i6dCl0PXn+j0Q8H3zwAVucOXLkSJJ1GppkJ1ENHUv7/fmf/7mzpX3hixvfv//7v7MVndQ5eErrY4895ix1jW4JXyYsQ3Dlw9CC1J/aWGShhaygHEy26JQJwWUPIjDjGhbHuRilH6N1w/edpWRC6tz+aVeoX+7+qn86nBC2tBG+sDDmTUR2JvfRGe93xVehqzzHyUD4YkVbEPnoF4gd3+KsSRBa9gD8nN/EnK9xZhda3/s3/t2ZGCWk0kN1EIfcE9WeVnWQfA8jkZCveFzc+kpqORGZCl968pwdcSmFL/rftCMRJN/v1OkJwmCFbkq5ubm2efjz9cjSfZicG0TQ1/GXeC5jsgOYkBNETcTApyfLsH//fvZ7SDdTr89DQRAEQRAEQRAEQRAEQRAEoW+yfv16nDhxApcvGoIJoxIThAOZUMl8dsdDkMihtfIj/t0ZgYKJyB6xioUfJG4gaydRRwCRPXw1C1oIn54NPVTUbtB0en9uqf9NROuPxgUeJll28fmhBXLUPtkspiChBFkz0dkSDO0UhRlrtH87ZA1f4Zyb4jum0pRwZZQz+mq2rmLRl/0qrd5tqVAcoSELOH8kDAlXfQojnHBxYqdlLlssSbfdS9aw9tMUKpqt8par4ginDWTpJVKzlwUwLh3lMXvUVbYFGU3jeNOVuRso7Vz2ZozPwUIVWqPOS8ITPVjI+5gkOmo4xtuozoNFs1T0Pq4vsupCdUdQOwqVzONjNJ+Pj093Xg7BAmcK3OI8tlRs5CWio/wNZE6dbWXxCwk7yF1PT0IfaZP7H/pge8qUKezCiNwIjRkzhgMJXWbMmMFWVW644Qbcd999bHmG3Kp2BLkBIisoNMeWnZ2NkSNHclwzZ87ErbfeinvvvZcFMCSyKS4u5n0prFmzhvdNheKbPHkyz9dRGDVqFLtjomMWLVqEJUuWxF0PkXUWrzjm85//PG655Ra2kEmT4nQspWXWrFlsueYLX/gCW21J98E6Wdmkcpg0aRLng+b3KN2UFjonHUuCJHKfRMYk3HwsXLiQyyzVIifFR8dTnDRH6Jb1xIkT2R0T5Z/qmQQ2XZ1D/Oijj9iCzqKxeRwyQg/AP35xkvCF0mi11ME4bVt66gr+CUvhG0IiwgTm+WPtxkVWWvRhk9VJ3bLXYNacjO/vn7IavjyPwEr1Kea5wzDOHnBW2GS6nz56HnwlnvTxfkeS9iPhjtf9EiLN7PYp1WINoQ+bqvIw1ZN+FWVzVVxs0iZdqk8lYQxZwSEC01W/7N2u4tGyi9gdkzdoOUVJ50gtJ6Kzc7n05Dk7YufpRhWa+FqgcDEgd2EUxOKLIHQACcCeeuopVkr6omE8OqEQN43q+KaeSnXEwI+P1WBXbQvM7DweHNANlW5qgiAIgiAIgiAIgiAIgiAIQt/lO9/5Dotf/uKx6bh8YYmzdmDTXYsvuRM+y0ISzRdgYYRt+cO2eOJa7CDI6kis3hZNdIQFE5HqvUnugihucrkTKJzOogo9NASan1x1aGCxyfmdaDr9JluVcenQGsqiv7TdKmVgSaRHLb50kKZgyTzowWJnqS2Uz0jdAXWOhNWcTPLIopGm0zAaT9sbOsAyY2it3Ipow3FnDZA36W7kjLqcJ0Qj1XtQd+hnIOssBTMfU2Uzk9PVVPo7NJevd45ILhMSz0Trj3Db6AxD5a3pZMIlzKC1+LKzGv/wxKFesfiSCk0X07xwTU0NzxGTCIKEKSQq6Y5bVYqvpaUFlZWV/JuEIySacd22dhWKg9w1k8sg+k3CGgqupZZ0Fl9cKzLeY+n8Q4YMYRFNpmkhQxF0LLmNJgENze9diKtZEsucP3+ey5niofjIIs3x48cRiUR4DrEr8ZMVmd/+9rddsvhCVj2ybvhz+IZOctbYmLVnEF7/XzDrK5w1mRFa9Qj8U8mCS4LYkQ8Q3vyEs5RMcMm9CMy6jhLirKH9N6j9O7D4kmKhhch0v9CqR1X6VP/lkma/NhZfWuoQ3vQEjLLdzpoEwaX3ITDz2qT0kzCk9X37ftmZFZY26bZMdb5alS5bNNgRsRNbEdnRdVdHPXnOjriUFl/aStgEQYhD6rC77roLl112GZoNC8+cqsfO2lZna2aUBHX80bQhuG10PgqiLfjRj36EF154gV0pCYIgCIIgCIIgCIIgCIIgCP0AK+03xIKDa3mFhCk0mRZrOhm3CEJ4XRDFGs+g/sivOg0NR36dJHohLDPKgozGY8+i8eSraDn7gTrPCV5P4orQ0MXslidj4vWqqbR3bGVB82fTP85S7xGp3o2Wig3tBsp/R66iUqGy4b8qr9Haw2nLOjWQmyOv6IWI1O6DGSVrOhq7TvLnjUWgYDL8jrWdWMs5hGv28W8XPrdqD/bvCFrKN6Y9X2rwil4GM1RnRHfFIl2BzuFaRSErJ2SJhIQl3RV4UHwkmiErJhRXQUHBBeWDjqU4KC5KHwlpUt0TtYf3WEoPWYDpSlroPOTNgc5L5XMhoheCjnfLeezYsVzuGzduxN///d/jl7/8JT755BNnz97DMqJsxcO9Pl18+cMRmHUDtLyufbxvRVooUmfJRgvletzlJKPlDlH/eLapYzmOvoQetK2fpKLyxJZTktJvwWqqcRYyIJZifMQ0YJTvR3TvG50Goyz5vpiWdO27t8/ZBxDhiyB0Apl3e/DBB9k0WWU4hh8crcbe+q5ZQwrpGu4bX4R7xxVgUm4Qzz33HH71q19h9+7dbH5NEARBEARBEARBEARBEARB6HskJp75j5AGEr3kjrsZeo5tacCI1KGl8uO44IIwW6tUYdoTrHrWEPgCGbrjaAeKmwQijSdeZisjsSayYmKB3CQFC6bZO2WAFWviv+Smx589nMUz7UFij46291XMsD0ZS3lkd0HeydouQO6FXNdHmqq/IFndUUHz56qCNNgFkdfSDmE0n4UZa+bfmh5SbWQ4/xYEIT3l5eV44oknsG9fsoisI9z7VFcxTu2ASRY/vOgB6BOXIzDreviGTFQdX1tBoBbIhm/oZOhjF8YFMmZdeRthha9oTJIFFRdf/gi1jaxQeYi2srWZvoSm8u4rHt9GvKOXTFDpH+ssOZCQqDG5/+sIs+E83cicJQW521L1GDu+BdFD76cPxz5E9MgGGGc7cfWm0qsFVb+cQq+es48gwhdByADyF/ilL30J06ZNw6nmKH5yrBrHmxIK9Uy5ZkQevjChEDMLQnj/3Xfw/e9/Hy+//DIOHTrEJs0EQRAEQRAEQRAEQRAEQRCEvoPpuADw+UT5koovVIxg0SzkjrsVweK5ILc3VqwZ4cqPEalK/jo82nQKpmG/AyfxRWjIwg4FGOTCyBfyuJZS+7LFlTRE6g6xCx13Qq8r4pRo8xnnOA3+vHHsTicd/uwRCBZOg5YyAdofIFGQZZEIifI4BsGCKfaGdtCzh8MXKHCWEpDYKFp3mP9qPj8CeZMRyJ/A9U6WYMgiTCoklDFaaDLYYmtA5C5Kzxpmb0wDWd2x3TIJjKNnuBBLKUL/onDMUBw5coS9R9DfTOhu+zAq9sM4o/rqWPJ8pxbMgX/alQguuguBKZfBP2Ep9DHz4R+3WP1eZm9b/HkEV3wR+vDpfIx5/ijMxvP820XLKUZg5nXwDZsKLX8Yi2R8Q6cgMOcm9Tu5HzAbzsE4d9hZ6iOo/l4fPQf+sQvhKxgVT7+f0p+b7PqQBETmuczFIWbVcVgRWxTIqH5UHzULuipfLT9ZIEjn8qly9k9cwaKhNqTWn+qffcOnsuiI4vKVjOf1PXrOPooIXwQhQ2bPno3HHnsM48ePx6GGCH5VWofz4WSzXZmwckgOHp1UjNXqb33pUTz11FP46U9/ivfWrmUfhN1VZgqCIAiCIAiCIAiCIAiCIAg9y8V0NdIXIbFJsHh2SpiD0JBFyBl9NfKn3ItQyXwWNZjRerSe/wQtFetZHOGFrYE00df8FnyBXGSPuhKh4rnQU8QtJIqgc+SMuYZFNS56sAhZw5bzOhZOqH1dWKgRKnY1ApyOTCGrMYZjEcUXKETOqKsRKJgCH1kxUWh6NgL5E1V6rmOLL/R1fH8jUrvfEZ9QOQ5B7rhb2FqLL1jI6whXcBIqmafyei0CefZEaSrhmr0wI2QhQuP9bRGLxeIasgiTjkjtXlgxcmGiqbKd5sQ/gcvWhcqbyjlr2DLVNq5y1gqDvf8ZjIxZMg3FE0di165dePLJJ3Hy5ElnS/t0d16R3B3FDr0PgwQbZsxZa0PWs/RRcxBc9iCCqx9HaOXDCK56FKE1X0Jwyd3QR8xkyy8uZK0ldnI7rIhtRYsh6zGTVqr970Fgzi0q3IzgYnXs5FUcv4sVbkKs9BNYDWedNX0HX8EIBJfeh8C8zyTSP2YBi2LiqLIzSUR0PuHerzOMigMsRHEFmwSJTYLzb+OyIsGJG8j1VHDJvSxEYis8KZiNCYtqjOov9JGzVZpVXHNvRWD2Tby6J8/ZVxHhiyB0gRUrVrDboxEjRmBzVTN+c6a+W+KXuQUhfGlyMe4eV4D5hVk4+ul2/OCHP2TffVu3bkVFRYWzpyAIgiAIgiAIgiAIgiAIgnCpiE8887+DD3L/kz/l/pTwAAqmP4yc0dew8MGyYix8aCnfgObTb8IIp7jOUBit59BydpPaVs3LJJrIm3QXC0qyhi5BaOhiFrbkjr1RxX8fskasgR4q5n0JshJD+9I22of2DQ1Rx6hjc8fegFDRbLgWZyI1e52jOidSe0DtvxsWWaPRSJgxldOVPfJydY6l6u8a5E28A6FhS2BG6tV+ya48+gPRhuMIV26DGW1I5HHyPSxcipf98JXsrip/6oO8TgvkOEcnQ/UcazzJE6daMJ/dHFGZUJmnip1cwlU7VDkf5O002Z01fAVyJ9zOZcvnVuej8qZyprIn4ZEgDGbm3XUZW37ZvHkzzxt2Nmd4IR/Um9WnEN2n+u2zh2BF03imUH2G5g+x9RYtlMtilvbuiLEjG2Gc/jQpHo3EL8OmIjDtSgSmXw19xPRk0UukRR2zA7Hjm501fQgSiMQi0HKHwD95lSf9VAYOpgGjqhSxox86KzLDaqllV0Jm7Wn7PIwqa3WuwLQrELr89+KBRCj60EmkXHT2S8asOsbiIS9stWfSCgSmXh63+NKT5+yriPBFELrI9ddfj7vvvhslJSV4+Uw9hzMt6Qd0HVES1HHDiDx8ZUoxbh9dgNFaFJvXvY//+I//wHPPPYedO3fixIkTqKmx1eaCIAiCIAiCIAiCIAiCIAiCcDEht0FklSUpsKUQDWa0CdHGUrRWfoymk6+h6dQbaUUvLiSAaClbB6O5ApYZg541hC2/FEx/VIVHUDDtC8gasYrd7BitlTBaPJO9lqGCfQztUzDtQRbf0LFZw8l6QEiduwot57aq82x3DsqMlrOb1TGfsrCF5nPJGknuhNs47ryJn4M/byJiLWfRen67Snf/E74QrZUfoaXiA1Wu5IrEZOFRzpjr42XPlnuGLuYJ6ZiqH6O1yj4wDeGa/ey2ioRGFChOWtce1Caay99HpGYPtxl2eVQ0k8uW612lgco7kD+F20Ws6ZRzpODKGcTiS+dkZ2dj+fLluOGGG+KBPmLvj4yYPQGzb1+FvOFFePfdd/HMM8+gqqr9a/JCMcr3Ibrrt4gd+xBm3RkgRv1cJ2Iada2SkMIruLCaaxDd/xaLWKzGc7xPuxhRmPXliB3diOjeN/nYPodKI7lfssKNzopkSOBD26P73oJRmZlbKi/GqZ0q72/AVMeSAKjDMqfyVmVktba1aGaUk8uqT5PdGCWRiLenztlX0f9G4fxOIhaLwTC6bslCEAYDs2bNQjQaxblz57D1zHk0GyZGZPlRHOy6f086Zk5hCKPV8QE1eKmsq8fHu/fh8JEjOH78OMrLy9HU1IS6ujq+LgOBAAdBEARBEARBEARBEARBEAShd1m7di1Onz6Nq5cOxdjhCbcOAxkSnpAVj1hzWfrQdAaxxlJE6w6i9dwWtFZ8oNaXO0d3gGWy9RHLaGHXN3QOy4zYwWiFGa5S8ZxR8R5G+PwnCFft5GMYzWe7loiFYarjeUKOjo81wGg5q+I9qo7Zjpby9bZlEw/kBonWGSrt0fqj6m9yWsk1EqWfRS0Urxm1Q7SRxTdkFab17CaVvhqEhixkkQ2ll8QyJLZxIZGQ5vOruM6qYLv+MVUc6egsTV2ls/govTEqey5ru+zVAXYZqmUWGjWeRkSlOXxuK+e5PSguEsiQ4IXaQ6R2H4taOoLKjtLG5crnb01Th8dVXPtVe1Jl3cU6HKiUVrTgg53VmDRpEq644gpnrZCOrKwsLF68GNdeey2uu+46DqNGjYKud33e7lLw6aefchg2YxyGzxyHgtFD4A8FUVN6Fns/3c3CnsmTJyMUCjlHJCDLMIcOHcKisXkcuoPVVA2z4oAtcgg3wmquAyLN6hqNAmTBhX6rbVb9WZi1p2CeO8JiC+Os6is8Fl6slnqY54+q/dV1Hm6wxRi0neKhOJqqYNaVsWug2PEtiB1Yq45R50qBXPDQ+ciFEoea0+qch/lYL5nu58suVH2Nun90sF9gxjXQsvKdJerrYip978JqqFAL6l5kGpwXEvyQ1RSjbDdih95Tf9v2f6npsuh8qqwo/154W+N5Fa+6r3FZqb/qvPw33MQCIo7j3CEWrRjl6lxUll5iKk2qXuw0qmPddLaq8q+vYGs+3jT2yDk7YOfpRhWasHDhQg4XA7/fz0Gz2rF/1Nqqbtrh/qlcFYSLxZtvvomXX36ZbygrSrJx97hCzCwItWPkq3NaDRMf17TivbONqAwbqIkYqI0ayMvLw9ixYzFx4kRMnToVo0ePxpAhQ5CTk8M3Obqh018RxAiCIAiCIAiCIAiCIAiCIPQcf/EXf4EtW7bgO783A8vnJFzvCBeOP3cc9Ozh8Plz1ZIFM1zNllVsqyTp0UNF6pgR8IWGsrUREquQBRkSYLTnaqcrUPz+3PHwBYs4PhZaNJbytuxRV7A7Hs1nW5ep2/d9Fsz0N8jiij9nNPSckZwXyzJU2Z9n8UlHFnt6it6uw4HEuk+q8H+fOsxijv/1v/6Xs1YYiDz11FMcyNLLnM+udtYCh97ahgOvb4Vuanj88cdx880385ygl3/913/Fq6++ikdXjlBhpLP2wiC3Rr7CMdDyh8N17cNCtYZKmI3nM7bQ4iuy4/BlF/GySVZiGmxhRV8j+/bvqjyPdpZUfqOtiGz9JWLHNnE+fEMm2MLHSKNKf1mP54HcSfkKRsKnyovFnpapylqVd4Mqb7KgkwFJ6TSiLHwxq0ttAVMaeuKcqTy5pUKFs3j44Yc5XAzcuXIRvgjCBbJ161b84he/wN69ezG7IIQHJhRiZn4WsvXum547F47haGMEJ5qiONIYRnXERE0kpoKJmLpkSfQyZcoU/ltQUIDCwkL+m5ubGxfBuH8FQRAEQRAEQRAEQRAEQRCE7vFv//Zv2L17N/7292di2Wx74k4YhGg68iffw26WSKxBVkdqdv+rs1EQeof3t53HP/38CFauXIkvf/nLzlphILJhw4a0whdi9wsbceS9HSjKL8TXvvY1XH755UmWbP7lX/4Fr732Wo8KXwYjHQlfhMwR4Ysg9HNI9PLjH/8Yu3btwvicAO4YU4DlJdndcn2USmPUwNGmKE40RXCiOYqKlhhq1Lq6qImoaXEgMQxBFl9IBJOfnx8XwwiCIAiCIAiCIAiCIAiCIAjdY8+ePaiursbX75mEWy8b4awVBhJ6qITd6HRkbSRQMAX5Ux6AP2ckYMXQXLYejSdecrYKQu/w3LtlePJ3JzF8+HDMnDnTWSsMVEj8kk74YoSj2P6r91C6aS/Gjx+Pb37zm0kuZP75n/8Zr7/+ughfLhARvvQMl0L44hqDEOGLIPQQhw8fxg9+8AN+EMqFiZtH5eGqYbkYm9Oz7odONkVxrCmCM61qcG2YaI6ZaDUsRBwRTFRd0q4ghoIgCIIgCIIgDCjIsGImw1zvfhfrmEyRY7p3TG8i5St0Ban7vs1Aqx+pUyFTpK30KqXNUVy9dCj+7KGpzhphIJE74TaYreRmqQJmpNZ292MZ6rrSWRSjZw1FzuhrECiaAU3zsVue+qO/ZqsvgtCb/N1PDmHTrmoUjBnqrBlcuLe21FtcumUi033d5Uy2pf516el93b9zbl+FsUunq1/JtNQ24eMn3sTZvScwZ84cfOMb38C0adN4mwhfegYRvvQMYvFFEAYIpaWlePLJJ/HJJ5+gtbkZVw7LwY0j8zA+J4iCgM/Zq+ehi9gWwVhoob+OIIb+CoIgCIIgCMJAQlP/WTwC7hjvfhfrmEyRY7p3TG8i5St0Ban7vs1Aqx+pUyFTpK30HqVNUTx9sg7XLB2KPxXhy4CkZNFfQs8aglhzBWKNpYg2nADI+osvwJZegoXToYeGqAtNgxmpQ/Ppt9Fcvs45WhB6D1f4QlZACgej+EVdc6BpbPevS7plItN93eVMtqX+denpfZ2/6UQvLvVlVdj21NuoOlKGZcuW4atf/SomTpwowpceQoQvPYMIXwRhAFFWVoZnn30W27ZtQ3l5OSbnBbFmSA5WD83BuJyAegQVBEEQBEEQBEEQBEEQBEEQ+gMkevlVaS2uXTYU3/6iCF8GIkVz/pAFLpqvfevtlhmB0XIO4fPb0Vz2XodukQShp/i7nxzEpl017PqGxC+CUHW0DDt+tRY1pedw5ZVX4ktf+hKefvppvPHGGyJ8uUBE+NIzXErhS++ZoBCEQcro0aPx2GOP4f7772dzY+cQ5Iejp0vr8GltC2qihrOnIAiCIAiCIAiCIAiCIAiC0Jdp59thYQDRem6LCh8hUrsfscaTMFrPwwhX819ajtTsRevZzWg6+RqaTr8lohfhouH2PtIPCS5DpozG3DsvR8GoIVi/fj2LXsiYhXDhmDWnYJ4/lghVJ2C11jtbhf6A/jcK53cSsVgMhiET9ILQHUhVNn36dDYxFggEUN/QgN3l53GoMYIWw2K3RwUBHT4x/yIIgiAIgiAIgiAIgiAIgtBn2V3XqkIYk8fmYPX8EmetMJCINZchUrMH0YZjiDWdgtFSgWj9CbV8BOGqHbYw5vwnav1Z5whBuDis316F02dbMWzGOAyfOc5ZKwx28oYXIZSXhZqT57Dv0z3QNA21tbVYNDaPg9A9rMZKmGcPwijfy8Gs2Aez9hRgiNixK+w83ahCExYuXMjhYuD3+zmIxRdB6EVmz56Nxx9/HF/84hf54m4K5eHZk3X4xYlabK1pwZmWKCKmKHUFQRAEQRAEQRAEQRAEQRD6Mpo4sR/wkIWXSO0BtFR8oMJ6/kvLRrjG2UMQLjbS7wjpGbd8JmbevAxZRXkoLS3ldVFD5hsvBLP6JIxzhxKh8giscJOzVegPiPBFEHqZYDCIa6+9Ft/4xjdwxx13YPLkydhWF8GPjtWwCGbD+WYcbYygPmY6RwiCIAiCIAiCIAiCIAiCIAiCIAiCIKRn8pULMO26xfBnB3m5vjXGfwVhsCLCF0G4SJDbI7L88uijj2LFihUIDR2JD+pi+OHRGvz8RC3eKG/AvvowKsNyYxIEQRAEQRAEQRAEQRAEQehTiOEFQRAuNpZY8BA6pmTSCARyQvzbkO/rhUGOCF8E4SKzZs0afP3rX8eDDz7IlmDGTp6CI1aIxS9kBealM/XYXtOKU81RNIkVGEEQBEEQBEEQBEEQBEEQhEuO6F4EQbjYiOxF6IjKg6ex/Zdr0VrdyMu5IZ3/CsJgRYQvgnAJGDlyJG644QYWwHz5y19mF0gLFy5EU/4QvH62Bf95uAq/PlmHtyoasbW6hS3BnGyOoiZiwBCFryAIgiAIgiAIgiAIgiAIgiAIgiAMSs4fPoMdT7+H5nN1GDp0KK/LDcq0vzC4kStAEC4hWVlZWLJkCR566CF84xvfwP3334/LL78c+WMnYEdYx0+P1+D/O1SFHx2txtMn6/BKWQPWnWvCjtpWHGmM4Fw4hoaYiVbDgvpfEARBEARBEARBEARBEARB6AU0MfkyKNB8AejZIxAomIJg0SwEC6fDnzsOmp7l7CEIgnBpqTpahp3PvI+605VYsGABpkyZ4mwRhMGJ5gzSNEvBv1JobW1FOBx2lgRBuFjU19dj79692L9/P44cOcLL3kCMyPJjdHYAY7P9GBL0I1vXkOP3Icunwa9CQF3gAR88v+WpTBAEQRAEQRAEQRAEQRAEoatsrGzijxJvWDkM33pAJhf7E3rWEPhzRgM+Py9b0WZEG0thGa28nISmq31HwZ83DsHCGdCzR8IXyAXMKIyWc2g68w6iDScQyJ+o1heo/dUxlqG2VSLWXG7H0Q/pUhkJF53v/PggtuyuwezbV2HcshnOWmEgUzB6iPMrPdXHK7Dz1++h6mg5Zs+ejW9+85t48cUX8fbbb+PRlSNUGOnsKfQkvsLR0ApGQPPZ7qSsljoY54+pe4TBy0KCJ7dUqHAWDz/8MIeLARmaCIVCInwRhL5MQ0MDTp06xeHMmTM4ceIEamtrWQBTV1fHwYuu2QKYHJ+GbL8KuvqtAgljBEEQBEEQBEEQBEEQBEEQhK7zwflm3LhyGP5okAhfWNwRKnaWbKxYKyJ1h1js0RFkLYUEJF4TOZYRQazhOMxYs7Om99H0EHLH3YzsEZdB82erNRaLVBpLf4dw1Q57Jw+BgmnIHXs9AoXToPmCzlobEoE0HHsWRvM55E25F4HccZw/y4wgfH6nivM3MCP2R6v9ia6WkXDx+c6PDmLLnhqMXTrdWTM4IOsN7UxfD3jmfHZ1u+KX2pPnsPOZdag8eAozZszA17/+dcyZMwf/+I//iHfeeadPCF/00XOhBTqxkGWZdv0aUVjRFlhN1bCaa5yNfQ8tuxDBxfdAn7BE9Zvq/qDSblaXIrL1FzDOH3f2ElwuhfCFRC8kfhHhiyD0IyKRCEpLS3Hy5En+S4KYaDTKIRaLJf1NXT9YcM1ZCT2LlGtmZdDVwbiUa+/Q1XLNtN4Ge31Je+0dpFx7BynX/oPUVc+XAd3XBnu5SrvqHaRck8ugq2P/i430A+nzf6H1JuUq/UBPI2XaO/R0uZaXl/NcycOfGYf7bhjjrB3Y5E2+GzkjL1eFaX/ZThit51G7779htJx11qQnb+IdyB59jaqHxLHRppOoP/CEiqPSWdP7+HPHonDml6BnDXPWEBbCVZ+i7sCPnWUb2id/yv3s1kgl3FmbwBW+kMujnFFXqX18zhbAjDWi4fCvEK7e5azpY6h60ENFKg9RmNFkcU5Xyki4NHzv2eN47cOzyMvLw9ChQ521wkCFPn4n6z4kfkmF3Brten4DKvacwLRp0/DVr34VCxcu5G19SfiSfft32TpKh5gxNS43gXATzKZqmJWHYVQcgNVQCbO+71nQ0sctQmjVo9BCec4ahUp/9MC7iGx7xlkhuIjwRRCEbtPS0oLm5mYO9Dt12f19ofTGg3h/eri/FPnv7gs5Kdf+k//eYrC3gf7EYL8GupvWzvrH/lSug6G+XNLVm5Rr305rap31Rlqlrno+Xqq3wV6u/S3/3R33d4SUa++k1Rtvb9RbTzLY66u9OC+03qRc+0/+e5reyvtAbFNduc76S7n+5Cc/YWvc//YnczFjgmfSawATLJmLgqlfgC+Q76xRdWuE0VT6OzSXr3PWtIUsiBTO+n1bQOJimWiu2IjGY885Ky4O5L6ncObj7LIojkpLa9V21B980llhkzv+M8gZcx00X8BZQ/ltQazxNFup8flz0Fz2LvwFU5E7+hrKqLMXYEbqUH/kV4jU7HXWXHoovb6sIepvnqrDPJXuSYjVH0dr5cfOHjZdKSPh0vDW5nP4t18fw+LFi3Hbbbc5a4WBCIlennrqqbTCl/qyKux+aSPKdhzF5MmT8Xu/93tYtmyZsxX4h3/4B7z77rv9R/jSBgtWuAnGmd2IHV7X51wI6WMWILTqEbb8EseMIbrvbUR2vOCsEFxE+CIIgiAIgiAIgiAIgiAIgiAIgtDH+NrXvoYDBw7g3/9kHqZPyHXWDmxIAFI05+sIFEx11hAWwpWfoO5Q+4KIQMEUFM54DL5gkbMGMKONaDj2DMLnL77rnNwJtyFr2DL49By1ZCHWeh7NZ95Radlu7+BQNPcbCBbOcJYUlolwzR4W+pClG3/eeJjhaviyhiFv3C3Qc0dDg0/tFkGkZh8aT77CApi+QtbQJcgasYoFLb5ggVpjofn0O2g6+aq9g4dMy0i4NLy56Rz+/ZljuPXWW/Enf/InzlphIEKil3TCl4aKGux9+UOc+vggJkyYgC996UtYs2aNs9WmzwtfVJ8KkiOQMJXFqe0IVNU+7EJo50swKvb3GfGLll2E4MI72Y0T/OTqyIRZexrRXa/Y6RSSuJTCl4Q9NkEQBEEQBEEQBEEQBEEQBEEQBCFO/Nth7cKsRvUnLDOKaP1x9cM76aixaxxf0PPFewrBwmnQ/MniIHJvFK0/5ixdXJrPvKfCWrSc3cSh+fSbaQUdXss2BFm3CVftRKy53CmLozDCNYjWHULTqTfQUrHRjq/8fTSdebtPiV6IQNFMBItmQQ8Vw+tyKh2ZlpEgCBefpso67H9tC4texowZg4ceeqiN6IW4UKuGvYppwKw8gtiJrSp8hFjpNhaLWE3n2WpKEpoG35AJCC66C3rxWGflpcdqqUVkz+uIHngHsSMbET20TkQvfRQRvgiCIAiCIAiCIAiCIAiCIAiCIKTBnVDsT66peoJI3QG21uKFrIeEimY5SyloOvy546H5/M4KhWUg2njykglDrFgTWsrXo/HESyr8BuGqT50tqSTXLVlyaS/NkbqDaCp9heMkKypGyzlnS/8k8zISLgWunGGw9T8C0FxVjwOvb0Xppn0YPnw4HnjgAVx99dXO1mT6svDFMqKIHt6A8Ic/RvgDFTZ8H+EtTyG6903ETn8KK5x8n6H+2Fc0Fv7pV0MLZDnrLj1WQ4VK8xuIfPIsoq5FGqHPof+NwvmdRCwWg2H0Hf9ZgiAIgiAIgiAIgiAIgiAIgiAIF5NXXnkF1dXVuOWyESgpCDprBz4k/AgWz4SeNdRZQ5PvOothIjV7nDUJ9OxhyBlzLXweiy9mrAnNZWuTxSEkkMkZxe6D/Llj7N8cRqpzDWE3S2asWe2YPJFLoptA3gQ+D6WJAllqMSO16tgxvM2fOxp+tV0lEpbRqpbH8Tp3fz1UAsuibWE+H1mwofWhIQtVusnVj41lxlSaK1VSQ7xd07NVlPVp0+BuSwflhc5hB29enfyGimkvWJxfG03Psrfz/io/HDzHtFNGlH4/lUH2cHbb5M8e4WwhLHbVRIIeSjO7olLlQ9ZsOiqjdJDFH8pPgPKUkjYqe7aeo8qPzpWOQP4kJx/J59M0P7eJQK5qF/F4R0BX56O42otvoHP4ZCO27q3FjBkzsGrVKmetMBD59NNPOQybMQ75I4px6O1tOPr+TpSUlOC+++7D7bff7uzZlo0bN+L48eNYNDaPw6UkMOMaaFkeK1rUn57ZBbPmlLNCEWmCWXWcLcFomg++wlHQ/CFno0KtQzBHbT8Gq6nKWelBD8JXMha+IROhF6m/RWNUGG3Hk1OiDvfBCjc5O6fBPb5E9efFnuM5jpHQcqlvD8BqbXAOUIcMm8Lx+/JVP0chR/Xf0VbVl0adPRJouUOgU9pKxnvSpuLNLgRiYfgKVDy03o0rb4gdj9rm0uZ8zj6a7ue4fSUq/uKUuA3VT3riuFTsPN2oQhMWLlzI4WLg96t7iAqa1Y4MrLW1FeHwpS8cQRAEQRAEQRAEQRAEQRAEQRCES8FXvvIVHDlyBN/7s/mYMjYhjhgM5I6/DbljrwO0hBWXaMMJ1O37bxa1eMkedQXyJnyWhRsu0fojqN37PRZYELZwZBKyhi9HoGAKfP48FbdjycKyVJyN7Fao5exmPpbEKy6hIQs4PSRGcSFBTVPp75Az7iYEC6aqbdkwjRY0HnsWrZXbUDD9ET6PC4k5mk6+wlZN8ibcgdCwJbyexBokJnGxLANmhMQs9vQZpan+0M/SpsHdloqePYJFHpRXEuZo/mwWDrnQOaxoI5orNqD51Ju8joQwoZL5CBbPhZ4zSqUrT6WLyr5tGbWe24JI3eF4GQXyJyNv0l1cxpovpI71upxSx6lzufVAeWs8/qKqy2MdlpEXV8RDZcBulLKGqXXBpPojcQq5tgpX7UK4ZjdiTWcoQnu7Q9GcP1RlM9xZss/XfOYdbgtZw5epbSPjdcH10Fql6nIrB0P9Hmy8/uFZ/Oezx3HbbbfhW9/6lrNWGIg89dRTHGbfvkpdFxYOvvUx8nJycffdd+PBBx909krPd7/7Xbz33nt4dOUIFUY6ay8N2bd/F77C0c6Suo6jrYhs/SVixzY5a5IhgUlw5cPwT1xOCj5nLfUNUcR2v4LI7ledNTZa3lDow6fDP2U1iz+0QHaiHzJVv9pSx9ZYYkc2wDh/jNd5STq+eBy0oOc+RJBwL9wE4/QOhLf83FkJZF33bfgKEoJCOk942zMs3vFCrpr8k1fDP2YBC2Dgc/p9SltTJaKHN0JX+/iGevrdWBiRHS/BOJVwM9fmfGqf6J7XoYXyVfwroakyprJj3LiPbVblvBlW43l7/SXiyS0VKpzFww8/zOFiEAqFkJWVJa6OBEEQBEEQBEEQBEEQBEEQBEEQOqbvupLoLaJ1B1kw4UXPKkGgYLKzlIBEHl5BCKwYovXHkkQv2SNWI3/KPSyeYMsg3slG9ZvW0bb8yXchVDJXrUsIRdj6SqiYLYR4Q+6E2xAqngeNLLaoOMh6ACgofIGClP2L42nUArnx9V7RC0ECFe+5KB5enyYN7jYvZK0kd+wNKh/3sPUVFrB48kLQMllP0UNDnDWqDAumsLAmWDybz2OnK30Z5U2+W+V7jrNBbVL76qEiJ01e0QthH5dId1E8zx2VURyVVhK7kLAmZ/R1LIDhfVLqj9bRtpxxN7IIitpEKnaevecr4bhzx9+sjh2XVBdcD9nDkTPmemQNX8XpGGy4pgvE1dHggVwcHXlvB0KBIG655ZZORS/9HRa4HN6QZF2FIMsmJO7wouUNQ2DW9QguewD6yNnQgna/H8enQ8stYeFJcOn9bDXFC1miCcy4NnF8KOU+RPjUebMLoeUnBHqElqP6zdwhiZBDfWXyvYOsuAQX3WVbvaHjXdELQWnLH4nAnFvgKx6fEpe6D6W4dWp7viHQR89FYMHtIEs1Sed2456t+tEplyWfd5AhwhdBEARBEARBEARBEARBEARBEIQ0mKbJf32DcN452nAcseYKZ8lG8+fCnyJoIFELueZRW+0VCnaJVLvfXtB0ZA1dipzR16h9i2iFCmSFpIGtjpAVGfpti4s0tiZCYgc7zvYhgQeLK7ojCrBUvZI1ErZIkipqUsve7fQ7Q8h9T864mxEatkxl2ysgsVRUEba2Qnl1BUFJsGhH5UWdjyzqxJrLEW0s5WC0nlOrY+6OLBjJHn2VU56EN81p0tsmP6l5bp9A/kTkjr+V/3rLmvKQyI+bNtpFZ8FP7rhb2PJNh/h0FjmR9RhqMyy0ojR6oHIkSzjk5kkQBjrlu49DMyxcd911eOyxx5y1HdOOc5d+g3HuEMz6s86SiwYSsbiQMCQw8xr4p15hC14IsjTVXAPj7EGY1aWwIo7bONVPkTgkMO92tvDioo+eB//kNYnjFVakhd0wmVXqPkRxkLWUWNddq5FYJjDvVugjZlGn5axVqP7WijSxhRh2VRTKhZbfSb+YBk31lfrYBSrqIIuEWCiUas1GlZF/3CL4chN5Hiy44kARvgiCIAiCIAiCIAiCIAiCIAiCIKTBnVAcjBYXSNhAbnUsK1nUEMgbnyTqCBbOhC9Y7CzZxFrOsnCGIAsoWSNWs2jGxQzXoaViAxqPPY/GEy+itfIjWLEWZ6vGrn6yR6xxltNDVl5oEtCM1CJSewCRmr2INZeB3Od0RqyxFK3nP+FgxRIulQgSqETqDsW3R+oPOVs6h6zasAUaz8QnuQAi6zfknqi5fB1ayjcgXLlVpeGkOrczUUtYJgtJInUHVNl8gKaTr6qyeYlD06k3EWs6xfvY2GUULLGtvhjquHD1Lk5vrDXVzYXJ5eLmh/aj/TPBp+osd8wN7K6JzmljwQhXI3x+WyI/57ertNc52xXqegkUTkXOqCvV7/atD2jkRksFcttE7YECu3BKEQb52NLQVGdJEAYmPl1HpKEFa9aswe///u/D70+4/umI/i58Iaymtu552I2Rgz5iJvwTV6juwr33WDAb1H1m/9uIfPQLRD55DsapndQZ2ptJ/DJsCvyTVtrLCn0UWXnxWMQyDRjlexHZ+ZI6/lmOI7pP9bXHNsOsOunslBkkStHHzKdKdNYoVFpIlBM7tA7RA+8idmIrrFbV93ZnPEEWcFTcFF/00Psc6DeJabywK6cRM5ylwYcIXwRBEARBEARBEARBEARBEARBENIwmIUvBIkwzEiyCwoSspBLG5dUN0cklPG6Ocoatoxd1sRR28M1u9B08nVEG0/yvs1n3mNxhgsLbPIngtwEtY/GAgw6tuHIL1F36CmOkyyldEbL2U2oV/tTMCK1zloby2hB8+m349vpdyaQ9ZVg8RwW47hQWZCIpvH4i2g49qyK6y00nXod9UeeRmPpyyzYcTFaz6O5YqPa73k0lf4O4aqdiNYd4dB67iO0nt+eLELyBeF3LKoYLRV8HKU3Wn+E17lYlolw9e54fmg/2j8TSLziz59AFeKsoeprRkv5OjQcTeSn4ejTaK3cpuo8ITpiyy9FMzu11GKoem888bKqu9c40G8qCy92XpNdjwwGXDmDuDoa+EyYMAFXXX0VlixZgq9//evIzk6IPgYF6cQ7HhGJf9IqaFmFzpIiFkbsyAeI7nsLZl0ZjIr9LFoxG6udHdR14w9BH5YQzGnZRXQxOUt0SoOtvRjl+1lEwnEcfA/hj1Q/uj+zfp9R6fSPnp8k1KH8kHiGBTU7XkR0z2uIfPRzxI5v5bR3B7O2DJHtzyH66csc6LfZWOlstdH8QWgFI52lwYM7VhPhiyAIgiAIgiAIgiAIgiAIgiAIQof0/y/quwOJUgx2d5TIP1luCRZO498+fw78eeNY5OBCQplI7T57Qa1P3W7FwixsCORNiAc9WOS4O0pgu1Aa7yy1hUQg4fM70Vy2Fka4RsXbxO6VjJZzzh4XF7K+4ksReZjhWhaHkLuiVCK1Bzm9LuTyqaXsPbb6Qm6eqIyDxbPZzU9oyEL4s4c5e9pQmWp6706Ok5UVsqzjJdp4iq28eK2y0O+Wsx+oeq1x1thoqg47tNRiGQirMmBrNg702yuCIjTNp/KanA5BGEhcddVV+Mu/+F/41re+heLiZAtanTEQLL6QRZM2ONZMtKwCaMVjqCPgZcJqbYTVXA3fkInxQHGQWyEvWv5waCFbQGlFk617aXoA/onL4J+0gi3KeN0iWS3JgsiO8GUXQStKdvfHwpzSrTCrE5ZjLJWf6CHVxzdVOWu6AFmnKduTFB/9tmrPOEsO1Fd6XDkNNkT4IgiCIAiCIPQO9NAVjQCRcCIYiS+ThA5QZWe1qAe4yjKYp47ALC+FVV+tnmjS+OkWBEEQBEEQBEEQeo3BbvGFIFc/XpGD5vPDnzuOZg3Z2oueVeJsISwWypBghtCDhdBD3u0KVZahknnIm/i5pGC700mg+QLwBTxuKVKwok0I1+xxli49ZJGELJN4Ieszbll0hqZnIVAwBVnDVyB3/G3In3wfCqZ9EQUzHkPhjC8he+QVbeLvbfTQEBbYJLDdJqW6IiJIcEQWeLxoWkC1gfYn8Skeo+Wss5TAtjLkfQeirr9BeA26egax+DJ4GDVqlPNrEOHTbWssKVjNtvjEN3QytFA+/46jq/vQtCsRXHJvUvDlJt9vyOqLj0UpqkepPAwr4nEvp/oVX9FYhJZ/EcGVDyEw52Z2V+TrosUUrXhcG7GJFW6EUZGw6OVi1VfAavG4hcsQEs2Y6thUrJZ69Y/0lS4ifBEEQRAE4aJAE/jGgR0w9n8C4/AuWE3JX/EIA5BIK4y9WxHb+WE8GGdOOBsHD5YqB/PYPrvtq2CWqTLoQMBi1dfAOPQpjG3rEX3/ZUTeeBrRt59DbOt76qHJ/jJhoF1PXS0jQRCEgQL139SPc/+n+nXq3y8UGXMJQjuosQWNMeLjDTX2oDFIf6Y3+hBBENqSEL7wn0FJtPYgWyFJoLG7IxK0+AumQPMn3BGRkIGEMi561jAWsHghCyKBgmkIFCaHJHdITMcTeOSSKNbQd94zkEWSZJGIuv2kWLFpF3VcaMgC5E++B3mT7mJhkJ4zEr5AAcdJLjksQ923kiY4ex8S43ght0mW0b6bDrK6kwRVXzcuHqpbOtdgR4R3wmCAhCZeayuMuv7NRtvlGYtK9JT7SHYR9BEz2gQtJ43QTrPlELETH8M4vTNF/KLQ/ZyGwPSrELrsKwjM+4xtQSZD0qXPMiIwa087S6k4irYegPMifWUcEb4IgiAIQl8iEk68uOwo0KT4kT0wzxznSfK+PkFsNdQiuu53iD73X4g88z1EX/wRjF2b1WhzgFr/SFOP5snDzsbBA72Ij77zAqKv/SIeSAiTKVb1uaQy5HI8leynuj3IWopxcGfysScOXPxrRT14GId2IfLyT7ntR579L0Tfehbm+fS+tCnPsS3vIPqbnyD67guqvD6Gpa5zFoXs+AAgKzAD7XrqYhn1R8yzp5LaYqdB9R9sIUm4JFiN9QnRQHvhwHZut+bRvbZFJnUM3E/xBCFTVL9N/Tf149yfP6f6P9W/Uz/fXQbdmCsNGfW5B9U1rvpa89Rhu7zl+h0U0NiCxhg01uAxhxp7UF/eb18U90IfIghCemTimVzblCLWUq5+Je6ZvmAhgkUzEcgbnyT2IIEMCWU6gq18hGsyCh2KLFTdpLM80qdwJlw7I5A7FrnjbmIXR3Z5WjCjjYjWHUJr1XaEz3+McPUeld+L/azYtXESuSRqi4y1BKE3ce9T/REtkAX/lDVtLL5Y0RaY1W1dxLmQ2yKrqarz0FwTd5lErpGie99A7MgGmFXH2SpL8rOAxiIW/6RVCC66C1qK9Zgu40sWQiYQIVtvIcIXQRAEQehDWI11iL78hP0itr1Ak8Iv/NCeGH/rGcQ2v8Uv8NlCQh+d1DBPHlFp3AbLMHjZammyrVe0qMHlACRdPcbW/87ZKmSKefooIqqte8uRLJ9kIggwSw8h+vwPko6NbVmrNtht8GJhRaMwtq6FVeeY+lUPombpQZgHd9jLXsIt6np+G4YKdI20R3+9nviL6jR9VJfKqJ8S274xqS12Fqj/oH5EuDSYFSfb9D2pIfrsf/O9OKLqyrbItJbFMua5Mxe9nxH6L1ZLg93/OX0+9es8putM5Kn60vasVAy2MVc6Mupzn/s+Ii/+CNHXfgVjy7swj+6J14MwcCHRIo0xaKxB0NiDr8G+LAyjtKoxYrp7S7f7EEEQLoDBPXkfrTuWJDLRfCEEC6bCn+N1CWEh1nyGhTIuJN4gayVerFgzWs99hJYzazsO5etUfCS46R9w+aRMQOvBgjZWU9KRNWIV9BBZPLAnREnw01r5EeqP/hr1B59E/eFfInxejfPMi3vfYiszSWjwBZJderhoegi+VLdWpqnqW93LhG7hNiex+CIMSPQA9DEL4B+/VPUfXospFsy6chjnHOthJFxJGQ+ziOXAu4jue6vjcHgdzCbbcgxh1p5B5JPnOEQPr4dxUj0j1JWpDZ6+VV1vvmFT4B+32FnRCZS+VDE9uerLaSuc0YK50Pyd3xOE7iHCF0EQBEHob6gnHivcwpOiNLkf26QGcC/+ELG3nuWXuVZzHzRn71NDjlSFs9/v/BCE9PjGT4evcIizZGNVVcA838lLL/WgYR7dByvqEcjofugzF6l2l2x2svex2rZ1+vqJrokUzFNH+atdy/Mgp+UVQp++QKV9MXwTZ9jp7y/XE73cqqvmyRe2vvPpZvUgWeVs9JJ5GQlCX4GuUyvcDKtetfFj+1jcGHnhB4i9/zLMI3v6vesM4SJBL7HV/SkJ6vv0lD6exn4tTTDLSmEc2Y3Yni08BkyLjLkyIxYFqEzLSxH94DVEfvukugdvsQUGwsCFJoxSvkLX1Niqz00jGTG2AkjXOVsY263aZmuatplpHyIIwgUjFl9sInX7k90dqfLw509gt0UuJPyI1h9zlmxICGNGkt9VaWq8YrZWorn8/XZDy7lNaKn4AEbLOeeovg+l1TIjzpKNP2c0gkXqeT7FBRJBLqBcUQy5hPLep8xoPZrL1iXlX88ZlZGIpi1atydaY80VqmI97ylUPvy549jiTyqB/EnQQ8luRkyjCdGmU86SIAi9QX+z+EJWXnxFY+CfsBSBebdCy0t5/xtphlG6DVaD3f+RCAYp7ok0PQjz7AFb/NJOiB35gIPVbFtE9PaDxtmDiO54EeEPf4zIp7+FUXWCbmLOVto3pNI41lnqGLOxEogmj9e1rFz4xsxzlhLoo+e1ya/QcyQ/7QmCIAiC0Pfgl5d+J6R/iclf951QA71Xfw7jkw2wmrx+ly89vjHqwXfGImiFQ3giXxs6Cv55K4CcfGcPQWiLVlgC34TpzpKN1dwE8/gBZyk9Vkszuy7wohUWwzd+mrN08dCCWaqtr4Rv5Hi77ReodEyeDX3qXGePBDSZabV6HuLUNe9fsBqBu38fwfu+jsDNDwK5Bf3memK3TZveRPS1XyLy/PfZtYBVox4EU+hKGQ0oqD+P9+1pgnzN1bfw3ovbM1Ubi8LYtw0Ruhfv/Vgm0IXOUX26Pn8l9+Pc/6l+nfp336gUX+KRVhg7P0T07WfZpQlZhSKXl+mQMVcaVH+qZefZ5UFB/eZr2gO5Do2texnGsX3OGmEg4p8+n8cYNNagtkBjD52uj0DQ2aNvYJw+hujG1xB55SlEaQz1/m+Tx4gumfYhgiBcMKbjMtc3yIfoscZTLGJRd057hcIXLFL3WjVGdjAjdYjUtXVzxMd5JxT1XISGL0cgfyJ8AXVvdiAhiJ41FIHCaQiVLHDW9h+iDUdhRJJdzvkChcgZfTWCxbOgZw9nYYgeKoE/bzxCQxYhWOi+90huYJqmyoLEJZrO5eLPHYtQ8Rz1O1He7WFbhUnUE4tVcsaoMMo+d85o+DyCpY6I1h+BGU0WLlE82SMv4zS5+aG6zB6xBlrAO+60YDSVIdZwwlkWBGHQoZ69fMXjoI9d4ISF7NoouPBOBJc/6IhLPP2fEYFxZjdipQl3+WbtaZgNJMLz9Gs5xfDPvhm+kgkspHFhUU3hSOijZkNPEZ7Qsj5qDnwFI9WC/XGkZURhnNoOs1w9C6a6yE+14tIOVu0ZmI0JqzKEFsiGf+IK6MOnq7H6UGi5aqw+fBr8066AFpI5kd5ChC+CIAiC0Mfx5RfypDCHuWqwNGsJ9ClzoZUMVxuTJ9/YnP2GV+0vVh0T930BerkcuPFe+NfcBH3FdQhc/Vn4V9+knt3bmTwUBELT4Js+Hwh4rLSwNZe9PMHcHta5M7Bqkh82fGOnAoUX6Je1m+gL18B/3V3c9v0rb0DwpvuhjRjnbE1gVZ11ftloufnQF6uHoaB6eKNJuzwyj6z3m+vJPHkIsS3v8Nf0iCZ/8ZZKpmU0YFB9tz5pVqJvTwn6rMVAMOTsLPQFbPGAUz9zl7EVJn3yLHU9qn4ldQK9rhqxd16whQkZviQRBifUb1P/Tf0493+qX6f+nfp5L1ZTA2IfvA7z+H5YzeSDvP2v+WTMlQbV5/pUv0rlweW89CoeT5NQwAuVLQnIOxpjCP0bGlvQGIPGGtwWaOyhxiB9DRJRGts3wKos4w8c2iPTPkQQhAtHLL4kIGsuye6OAiyqsLEQJXGMCqmEq3bCCNc4SwpVloGCqcibdDcLKEJDFthh2DLkjL0RBVMfRM6Y652d+w+U90jNXlVGnmdgJ6/5k+9F7rhbkD3mWhWuQ/6kO5E/5V4ES+yJ2VSXQlqwALnjb0HW0MVcLnkT74A/n8SNnbdDM1KdVE8ECVNyx9/K584ddyP0bK+LqvYh4UukRo1DvfWuZyNn9DUqTZ+N54fqMqjqMNEeaP66Hq2V5J5JxleC0Jv0ZYsv5MIoMOMahK74GocsFYLLHoA+bhG0FLdpVrQFxpk97KLItdLiEiv9GFbE456W3q2pOIJL1PPvlMvUb/XMpwL9Dsz/LEKrH2eRiRdaDq35EgLzbod/0koW4ZAYxz9+CXwjZ3KccWIRmI7Fmc4g8QwLZ9QxCTTow6YiuPIhBObcosLNCK74IvQRZAFMxhO9hQhfBEEQBKGPow0bg8DnHrfDnV+2LT+ov4HLb4VOooBQtrOnDblXiG19r3N3MBcZegHrpwmYKz4Dfe4KNdK82C5nhP6Ib+xk+IqHO0s2ZmUZzBRhixeyfkTuwOKotqZPm3fpJv00nzr/fG77NCGhDRvlbEghxVctsnOBnMSXb14G3PWUaRkNFHQ/9FU3Jvr21HDzA9ByC5ydhb4AWQhw6yd41+/Z9+I7Hod/9Y3QJ81scw2S5bXYlrdhNtQ5awShHegepfpx7v9Uv94TE9Yy5kqBXojOWcblweV83V0IqrG0vujytteuGj9bTY3OkjAQoTEGC0To+lBjDxqD9Gt6oQ8RBKEtCeEL/xnUkDUXsuqSDtMII1qfbH3VJVKzD62VW5Msh5BAwhZj3IbCmV/hQIKX7BGrHbc//bPAW89uQaT2ICxVHgk0toqSRcKeUVercCUCBdPgdVsUbTiedAyVT7BoNgqmP8LlEiyaxZYQ1E7OHu0TrT+e7JZKofmCbGHGPvdUFi1lAolWmivWszUb25KMDaWd0hfPj6pLr+jFjDYifH4bwlU7nDWCIPQWfdvVkerLdXLrZge2pJsq4DMNFpnEjm1G5NPfwKwudTYkMI5/BOPUDhbHuFB8+siZLKTJuurrHOg3WVohizBt7iNqWcsuhH/ySoRWPoLQFV+1BTlr1PPh8OmJ/VV6yPWRUZbe0mo6YiptRuWR5Pe7Kj5f4WgEpl/F4h+2bqP6USssz5w9jStO1v9Gwb9SiMViMPrQl+KCIAiCMChoaYKxYyMQSTzo+kqGQ1+w2lmy0YIh+EZNgG/SLFjNDcD5CjX6Szx8kg94LTsX+qR2FMRqXxYPlJ+wrWPQS34KtZVqEBBVx+aoE3fwEpiOP0/Hn4R19nTieI7jPLt30LJUHK7QQMVpVpyCVVfFpuQp0NfKvE8arMY6WGWl9jGVTrx151VWfNBCWTDPlXFa3bgsVV6a14R/mvO5+1jhVljlFHdpctz0H6UnXXl1lQzrMSO6WFf0tTLXSX11PO9kprG9siaBFLmkiZdTY73aN9t5CEkQr5OznjqpVu1O7U8v3NkqSSrpymHsFBahZArFa6n2bZYdd9YoYhE2TU/XQBuiEcTW/Y7r3oWEM/4rbmtTBt3KU0dtq6EW5pljdvnXVsGXX8TXAO9LcXvLmEQtPrVNXb92fdXAOKge3tRfF6oHziPtQ+vda6aL1xNtIwsUVsVJlVd1Lvp6mNLD+T3L8Wshdax38k+1GY678oy63tQx3rbXURmp40zal67P08dglh5yNijoi/tR4/knx93SrMotj6+5jsooLVQGan9T5YnT5tZfVQXHRW2Ey6Odfixtu6fz0bZKu73F86z2IzcjnNaO+sUOYDdWqjzikPBl7nLuFzKhTfk01HFfSJN1VAZkVcdS/aIqSbYU1J12mkRvlS/1Z9y3q3jVPlogxO3chVxhmWWqryPrR1FKL7WP7pX5hUBpN/ZsVRlJPA+36btUu6Uy8I2bAt+YyTCpz61W/bLHwovV2ADfsNHxdt+GC70XEyqNZOGK72t0rbp1RaFGtV26zqjs0wn/1PM+lTn3DanH0r2c2j2Ja1PuBy7ttku1P/c5qi65HdI+1G+o+y+3TzdPlH86t2oT8X4pfr159vPQtWtXnVPlH6qeNH8n5uCpn6R7grofmBWp/aRKE421VL7S3he8JPW3nnuLGw+5olRp8cbTJk/p+kZ1TZgHdvC156IVDYWvsCS57Kkf7+o94gLbAY35+N7iHXc457Na1JjkzHE7PU68aFDb6f5B6e0lMupz1f2FrCea+z7mcXMclTb/wjXxdpVET1yz3eEC++R2r9X27iEeLnhM7sDjb3VN0r2Hxwnea6yz8uvJNpYuLtpX3Y+INmWVSUjNM11T6tqhurLHUCnjLpVmsuqmpbpX8ly75HKLjnehF/rkxozSn3rOjvqQdHCZUT1QH+Vtx5S2RvqqVt3f6JpPd3ya/iU+vrgYz1iCcAl58cUX0djYiDuuHIW8nE7GFQMcElMECqbAn0PWQpKvbaP1HJpPvwMr5vki30Os6YzqDtR9OVSgbkOqL2x3rK/GVGZU7V+GcKW6Vzv4c8cgVDxXHZuoAxJXtFRscJbakjV8BbtOimPF2CILpcVL9qgr4PO46CHrK+GqT2GEE+8WiHRpMFqr0Fr5kbNEaWpQ686q2xr193lq2KH6/HbyalkGi1QitftgqnLTs4dBDxYlxc+o5wxyoRStP6ryMyRpe6zpFCLVu50lGzNcrfYrUWG4PdGcUld2/sgKT1VGZUT1bkTq4PPnqpClzk95audeY0ZgtJzluqO6oXx5SS3r9uqEXEBRW/O2k3R5HegcONGAT/bXYfbs2Vi+fLmzVhCSef/993Hq1CksGpvH4VJCAg8tq+0zQTKW6lhMWFE1hmyoZMFI7OiHiO17U41Xky29xCEr4PUV6vk+Cz4Vv+ZXY/iO7iMqbrPqOItlXPwT1XNhviOsVEGj50J69+jGQ8/00Wb13HcU0QNr1Xg+4bqvTb5U/OQiyXJcHFmt9RzYrRGlL7UfV1gRFXfFfnXjUM9wuUOctQozBuPMLpg1CYtpbc6XZh9CHzmLXSh5y8KsPgnj9E5n6eKz83SjCk1YuHAhh4uB3+/noFntyMBaW9WNL+xVpAqCIAiC0NvQS8vwT/+BXzK76FPnIvjFP3GW2kLujaK/+SmMQ2ow47mta2MmI/TQn9gvGj3wy9TSwzB3b4F56rAakLXYx9Fgjybax01jgYaPXDike3HtHr93qzr+qC28cc/LceSwKMF/yxfgGz6aV9NL0chvn+QXrS7++avgX5litpYmzctLYRxUD9806UgTMTTxSPFmq4fr2Ut5MoIt2lRVOAepMho/FYGbHnCW0p+P9vGvulGV0y7Etm8Ezp5UD/qeuGcuhn/x5WxhxDtQ7A7dqcd0dKeuzNPHEH3nOTVIT0yO6VPmIHD1HTzJk0Qsgshrv+IX3y6+gmIEVN3FvxalSR4Vp3F0LwxV51wnjjiaLagUD4M+Zzn0GQttkYZnwiJtOag6D96cqKtMMFWdhZ//Pk++uVC+g3c81iZPNIET+cW/Jp3Tv/gKBG5/hMuNuZA8tde2Vlyv2tUGGDs3AXTu/EKEHv1zaCoucvcT27XZ2VudIzsPwc8+ymVsqus2su539gaatFDXswtNjGpDRsJyHMm710zG15OC4jNPH4V5eBe7XaEJWZq0iEOTPUNGIEjX68QZ9jrVdmjChSddSg/ZE6Jhp+0pkspo+nz4Rk9KlFG4VbWpn8MkMZ46N7WBOOq60oaOAJwJX9/QkQje+hAQyuqwjJJQaTCrz8JSfY+x/xPOG5rVeRyBAj+s5qjreewU+Ch946dBK/I8SDpE33waxskjzpJ9PrKyAtWvxHZ+CPPYXvt6IwJBFjb4l18L37S5nU98pyHyhjqfymOcQIgthlC/kAltykelKXDd51noFtv0FgsMrGgY/jU3I3D93d1qp0yvlu/9PBEd/WgtrHOnoan+3q/qmPp0gsQbsQ9eg3Fgh7oeY9DHTGLBmm+C6+/+4kHXSuSZ77H4xqWzvouuk8hz32fhhReyMhH8/O+16asu9F5MUD1THRmHPoV5dB/QVBfvywjuQ9T9OHDbw/H7sQtN+pqqjgzVN5jH9icfy2nIgTZK3cvnroCm6tk3dBSv95K2XV7/eb6X0z3cOLCTz0P5on6DxiXkXoSuI548VeeNffw+C7Hi7tDc640s6dD1kSK26Mq1y33VCJUHdW+nuOLtPAWerFVp4PSoPpn7La97NpUmEkiweyt1P+XJZ9V3pkIW9/jaObjDdnNFE9+e+uB4iobydepfdJmzsm2e0vaNKh4SItJfF41Ea04fyWV/473cH3fpHtED7YDafPStZ5PGHXQ+nyorU43neMzlHc8VlECft8Ju38PHOEf0LJn2uTRWCP/s//IkvQulL/T4/+S68tIT12yX6aE+uav3EKaHxuQEi4WO72dXlSx0o2cHdyziLT9qN1R+KRbPerKNpYsreNXt8E23X8amllUmePNMeTPUtUR9MrUTkBCO7iXUVgjVd/iGjVHpW676wnkqfWPt9Yqka1f9JqFqHOpD1XGuiNF7zo76kCRo/EsiITW2M/Zvh1VVzv2fN21aoSo7dZ3oMxbZz0SplkXbG19cpGcsQbiU3H///Th79iye+ptFGF5ii+UGM1nDliI4ZKG61JOv61jjSTSdetNZSg9ZGQnR8QVTQVZdNH+uGrc5ZWqpMU9MPcNGG2FEVJ9Ts5/FGS6BwmnIHnGZ2j8xFiP3SY3HnneW2pI7/jPw5ybGwuSOouXsB4jWJVumyZt8N/RQ4vnTijahuWwdYs3JYox0aSCBTtPJV52lBJS37OHL4c+bwMISFnuwRRRLpUONHWMtLDyJVO1Cq2MVJZA3kYUoJLDxBQt5f9rXVPmM1O5HtOm0Ov+apPOTdZmW8vXOUgLKT5ZKa7BgsopLjR3Zwos6d6xZ5ascTaffgqH+ZlpGhJ49AqGS+SpP49iCDQlh4vFSnlTdxVrVs1HNvqS689KmrNs5X7p21l5eXapqW3DweA2i7XiczcvSMX/6UAQCyc9nF4ppWth3tArV9RGazm9Djjrv3ClDkJ3VdiK8M15eV44fvlSKu+66C3/wB3/grBWEZP7yL/8SmzZtwqMrR6iQmRuz3iK4/EH4cjpxN2+Z6tpX10tLPYzKozDPkvXuxBizI7RQHvyT1fPAkEnQ8tR9JET3EVtUTnEi0qKe1+pgNlbCOP0pDHJB5BCYdQP0YVPURVkCLZjNIhqCrVmF1bNWSw3M+rOInfiIxSNeUvNF6Y3ufwdm7WlnjQ25MtJJYFM0Vj3r5HPaOK+tDerZ6RhiRzcjuOJBlY5pzhEqrkgzIlueYndOLm3OF4sgdng9DFVWXvwTV8I/YbFzf7GhPEcPrnWWLj5PbqlQ4SwefvhhDheDrKwshEIhEb4IgiAIQl+iu4IJmtQOP5csDEBOPkKP/Bl8IzwvVGsqEfvoHcQ+Xpd44ZwGmujwk7nspVcnvTS1mhp4YpJecnd0fOoEQ6YCCPrSP/bWMzDISkS6IYqm2VZuSCBAXyE7pJZRuvP5JkzjybTYRyrt6qG6DRT3uKkI3PV7amDadtKgK3S3Hr10t66shhpEfv4v/DWtC1kcCD78bWj5ySIC+go18tQ/J6dz1mJ7ktavHhiMGE+GRd/7jf3VafphI5edPmE6/DfeB99o8jdtk2m9dwYdz3nyCnTayVNs8zuIqjZED1BMIMj5oQlLpjfyNGkmtJHjYKi2FZ+MyitE6PG/4MnS1Ak47zZj+waeQMgEt+wyLVeyhGDs2oTYxtd4cqsjSGSiL7b93lLb4/i9Ey7poGtGXVOB2x6Bb6Tdz5DQhicRK5K/PkgHlVnokf/BkyIdlZEXs+IkYh++ycK7pAnldPgD8C+5kid7U+OJ/OJf7IlpB5pkI7cHsc1vt5tvLa8AgdtVOc3o+pcKFyp8SXd84KrbEdu2juvLpcM20kk7JXqtfNV5/JfdjNiGV5PaorfdRTe9BeOd5+NpI3zT5yN07x+qc3X95eCF0B3hCxH76F1E31T9jzcPw0Yh9Nj/5Huyy4XeiwmO4+P3YahAgot2SdPWqH3EPn4Pxrb1HR+rIPGIb8Yi+K+8jUWtXtK1S//lt8CkCfry5BdELnQdkTCWRCHcHlqbnS3JkEgleNdX+L7spU3bysljt2HG1rXtX7uUhyVXqWvms22sWZBYL6baO6fFcy2lRfV5Gt17rvmcapsLVKPwtEt1vXA8777IAomOSG1LbfLUQd/YLp56zvge0UPtIO31Mn8VXwfmvk+Sruk4dI+ds1zdPx7idt7TZNrnkmWY6As/5HuXC7W54IPfUuWfSFdPXLPdocf65C7eQ4ieGpMT0befQ2zTm+nj8UBiPV21scCK61QaE9ZQerKNpYvLey/K+JrzQOOC4APf5N8k8Ak//R8qoo6vKU7fzEW2a8NC+7kj3bXbHt5y7qgPicPj392IrXtZtSs1RuusLlSaAleSq7SVyc+CadJ4MZ+xBOFScu+996KyshI//85iDCtO9FHCheHPGQM9ezhbOCFMM8yWQmLNFSyAGUj488bDnzuWrcCoHpUFL0ZrdRthjQuVjT9/Au9PIqBYYymLfLoDCYwC+ZNYpGLB5DKONp664DLmPGWPtMUvTp6o7ozWTsbVvchbHxzHd57ch8bRi9IIUCxM1srwV/eOx5I5I5x1PcORk7X4zq+OYVfLCJhWslCcGNN0EH/z0EysXNh1t86/eb8cP/pNKT7/+c/ja1/7mrNWEJL53//7f+PDDz/sE8KXi4lvyET4CkdCC9nP+la4AWRBhkQrJKprDzpOyx0KX679Xpktz9SVdXpcVyDhi69kLKeN0mVWn2aRjK9oDLKu/iNoeYmxMVmNaV33PZg16d+l9DcuhfCFRC8kfhGpvSAIgiAMALQxk9p+4RkJJ72Ipsml2Oa3eNIz/tKeXCaNnwZ9+gJ7ckktE7zvB6/zhAA8bhvMgzt4oi1+vI8sOIyCb/Js/urSN3Emf2VIL9+7Ck1Yxdb/ru0LdkqjipNfCut+fqHc2aRSOsgFhfHJBpC7A/pimSZivZY86Jz01Tnl8VJzIXWl5RVxPdBLZhdyZ5JuEpIs9rC5dRdVb/rspeqv/SKPvh6lSVwyh851ouKkyUjf1Hlc3/z1PJ1HbaN6i61/RQ3Uk31I9wQkSmBrJJ3lib5kPbGfy8HFVzKCv4R26Y08mfQV+K6P0k+8dAZ9uUSTpxS87ZGgdLjbVOAvuzOFJnN3bLAFPl7RC+U3O8++poqHq6eC5C95GSoXCvR1cWEJW9zg65vCmMnxtkf70DVjbHlbtVPny2lvmtOll75U9uSJ988Qtgjy3sswdm9JngBUeYjnx00boa4dEgWwmMXbztMRjfBX3jT5SW2A20FKP0btIPbJet73gqEv6U8dgXFge9pAbhg6RLVx+gLf28d3RmfttFfLV+1LX4F3KMBqbmibNtW/kfWX/gL1U+xewgPlmUSjLj1xL6a2GN30Jgwqe+/kKt2Tc/OhDVP3OBoTeOvLgdISpfNveTf5WLUv1THfwz39ArUFsjRBbaPTe6+qP2oTZmV5x9fRhlc5X3T+dvcjocH2DarT7rhftcJhGKosrKZ6vldw3slahKc/5Tzs2Ahj3za14Pn0k9ar6y1Ggiuv6IX6voJiFliSUCcel+rzSDAZeetZe6ziwSQRyfu/TSojGmfwuIj6ThonjRqProo8uN93+8tUKF3uNhKHpd5DOqBX24GC+7f924GsbLtOUq4Lvn+QlRm13yVBjZFpDGFsfZ+vszg0DpqxKFn00gPXbHfo1T65k3tIT4/JuR9X8VD7J0F+/Llh0izbso4zFqC2aGx6i0U3ndFbbSzpmksNacY1trWahECP64rKTLUlvpbcPoDCiHF2PLyjSt/BT9lSFY0JmKQxVJrr2d3mhkyh+j5xQI1/f22Pnd06VeegPo77OrIeRWM0B6rX6LsvsgUr6ts7oj89YwnCheB+O9yFxxchA0j0Ea7ageby9zm0nt3ErnwGmuiFiDWe5PzZeV2HcPXudkUvBG1z97ddEnVP9EKQEKW1civHRdZSIrUHeqSMOU9OvG6eLqXohfDrPjQgG9XX/BEqb/1OSvhbHJp8J3748iHUNvTcR/+NzVH86MV9+LjgKpy95W/j5zt/y1+hduUjqJl+A840BXH6XOK5sCu4t25NOiChA9qxcTHgMatOIHZsC1teoUC/yYJMZ+IVOs44uS1x3JGNGR3XGb68YWpcbb/fIJGLmzb6S8taVgH8U69Qz5wpVi4bKweM6OVSk/mbEUEQBEEQ+iw0kc0m773QS2bPy3zziHoA3bkJ8YnFQJBFDsHPPITgPV9D4NYvQp8yL/6ikibr3IlgxjAQo0kjz6QvWdsgFzrBz30JwTu/zF9M+q/6LPQ5S3nyrSsYe7exJY74E52CvljV56/mOP2rb4I+awnYX383BvP8JbhKk77ocvhVmvUV17FJ+KQXszSxQ2nwTjBcAi6ortSDMLmfoa95XcjEOpk1T0LFTeu8kym+4mE8kUNwnDQx6ZkMpBfjgStuRfDzvw/6Ep++7Pe5FldUndCXpORyo8fhPC1om6fjB9SPxMSSSWIYr6URdRyJNlyT+b2VJ5qcorInc/q+GQv5C17f+Kn2RGQn0IQvm+NXwZdf6Ky1oS91qd7j2z2WZzrDOL6fJ4+SrtesHOjT5kNfeiVfU5RvnUzPT57D54pDEyF07ZEbA3XdBW97xL6+VQjc8oCKQ9WFO/lDZaTaq6nKgNB0P/Sp8+z0kjsQL+oYfeLMeH5oP9o/I1R7jW1fz5NY8euf6nfEOHVNX5bIj+ov2BWHA11Dxs4PYRzspA5p4lcF6mMCl9/KgX57J34JcgdhdkFs0i7qQTq27reI/Po/0wae8O8IEnlVnFR1mssTh2TRiFwmaMXJrjm8dNhOe7t8wy2wzpfzfYpEZpzeKardOdcmQaIqcrvF/Zo6N91D9ClzoXkndvs4bIEq9d4Xi6m+J/GC84LvxTSBuXcrjB0fJOJQkOiR6lRfdg3fl8llCbv5IDGOpwzNAzvaHuvca6mO+R5O/cLoCWqDc39UbYLaRkwdR22lXVS7pHRSfx2/jqjvThW1qLZrRcLcFgKX3eLsp+5bKfuZJw+r+DqZwFfXErks0SfPgn+5k3f1lywcJU0Mq30MEl+55aggFzLRdb/jMnbR1DVPwgf/qhvgv+Zztosz1Q69AgMW5ZAo0nOceXxf0r2FBRRqvEHjIu4/1TgpcMM9bFWiK+59qN/n/pIsTaWUjzZ0ZKI/nbNM3UNSxoEd0KvtQEGCCrJ2pC+9iuuE/vKkv7q2XahfMD1WKnoVr9hw/3bEPv0QsXefT+7z+P41V5XBCnvZ4YKv2e6gztWbfXJn95CeHpPTdUV9EY/Br/184rnhc4+rPuBm+Ao85rub6mHsS5j3bo/eamPxay41UH5T+3c1riHrT/qyq50VCrKONGIsH0N1FO8DVPBff7f97OGkkerL3PsxrFanrZCwiPpxdSxd30lQn0L3bic9LHLPELbYSX1dSh9FAiTq47ivU30e59EzHqS2HM3AGlZ/esYSBEEQBj6XLxmL62b4kX1wrbrl+mCRixFPqJl9O9afH8GWYXqKTTvO4KW9Gurn38HngM8PX3Mtcs98ivEn3kHJm/8HS4c24NYrJjtHCELPM1iFL30N/4xr4Cc3R8OnqWf04dCC9kcVWnYRW5nxT79SbV8WF8cwsTCM8v3OgnCheJ5CBEEQBEHot9AkoedFL0OCABK/ENEIYp9s4BfALr5RE3gSRiNXSIEgf4lMriiQ5XnhefY0rMoy+3c0bL/Y9MBfCdKkWkExf93HL8XnreTJAN/Icc5enUP+5Y29HyW/DCVz8atvVHF9keP0r7wOAfo9cxG/aO4yKo/+FSqOm+6DPnc5AmSK/nqV/5xkhTW9SI+/gL4U9EBdaWMm8xe5XmgCkb5wdqGJBZrEj0MTKvTlrWNu3Tx5CGbpQf7NUPnRS/HFV6rBeg5PWOsLL4fP6zbAiMIkkUgnE2LdQRs9ET7Vvrzwl8YtHnHX6aOqjXrMwwdC9mSqc230Zp7I9YP/mjsRvPfr7E4hcNP9bb8+TgNdPzwBpII2LGUyVF1XgVu/EN9OEx0ZQT5faULTMylLeaXjWbxy3ef5mqIJ2KBKZ/COx7l844SybcHLHY/ZLhPoS2q6vsl6wdgp7BIoyey9Oo91vsJeUOcJXPM5Tq9/8eX2OheaVKR4nfzQfrR/JlDfY6S4M6CJssC1qsxVHuL5UX0EuZlImrihL8g/3ZQkAmoDtf8pc+w+ZsmVHOi311oQQROZVtVZZ+kSQi80yCXEwtVcf8H7/5DFW/7Z6uG5A9prp71eviq9Wk4+CxLI9RinV7VFzfOVPE0euoIjDsuu4T7bvX77BZTWlPRapqnun84XQz1xL25q4Iltb3lTHfqXX83iPZ4AnrOcJzN5Yv7WL/K9maB7bWz3luRjVV0G1DUd/MwXuI75Hq7qPED3x0LPZDRN0JKFCHXv6Ah2f0b3Wfc6Ur+9E/MulE++vy+9ytlPtcXU/ZpU35Iy7kiHb6w652cetsUalHcSBdyirt+U+6BVVREvR4LEH0kTuiTOU2OM4O2P2BP7JP678nZe1lVf7a1btl6g7ikuZPGFx10OGvW55F6MLNpQ/0kWZCarPubGe9V1e5mzV+dwv0395fV3I9VaDMXn9qfB2x5WffVoZ0vHXIx2QIJsmkwPXHuX7W5G/Q1ceZtq48lCNotcGHZyf+0RvGLDZ/4T0Vd/AXINw32eqlcS5VG/E1D9ozsOYnrgmu0OF6NPbu8e0htjcnIdSf0R9w0zFiSeG1RZ60uvhkbXlwcWMbvPMO3QW23MveaSwmcfU+Wtrluv+Ey1GxLJ+FfdmHRtcj3ROMhxn0T9rzuG0qfN4z6PJsNcrPpaWHXV/JvGocFbHuRz0vXthc5B/YCbJqqPTCGhu1le6iwpVNrdOqE+zhU6ByjNs5ck1SmN7wzVV3aIug76xTOWIFwgYvFFEPoHwaCObzywAEO3/RKBqrbiFkvzIbLmC3jy7TOoqu3ENWEG1NS14mdvqvvsNV+CkVUAPdKI0PEtGH7oDaxu/giXTc5DSa6O3793AbKzMvzwJxXpdwSh36CPmYfQiocRWv5FBObeytZd9HGLEJh5HYJL7+N1JIKJo55VjMojiJ3c5qwQLhQRvgiCIAjCQIBMZKe+1KWv7ByXNWShIOkFPL2spS/xyB1STWU8sHn/nOSX564FDbLMoHkmuwnz3BkYW9fCPLYPVvXZxEtyehvkfiGcAeQvniakvNBXxvS1uvfNElusWHUTkIGgIBVf0VB+GeuNj8Q5bGHAg9XakiQQYXP4R/bwS9/2QiZm3jOlR+pKlQ9/oe6pAypf83y5s6TOU34yKd32V+4L4+XD1lS8k2L00n7Y6OQ01FcDZKLeA5/D6zagh+A80Rf83jxROlQbZOhr7qP7eHLLhYQyJAJy6bU8BUL8xbI+a7G6TnROI0+cOdffxYasr1hnjjlLNvQVNH2FC8/kmItWWJw00UcTaJQXmpihyTf6KpwnTciyy8GdMM8cT37vQpNTnVlluEDM08dU/XgsrdB1MXMRiyW81zT9JotTqdZx6Jrq8DpVdeVfeFnS5BX3N1NmO0sOPZlXaitkkSJNyMStFYuQrvps3M0dpZddFbRHB+2018uXjpuxCPqaW+ITtHz9efpyShNbyLjnawje+wcs4EjXXvs07dyLXYsrPdG/c9/t6csJmiBlQVqaPocsOFBZEyz8oElgD+yuZeEatWPyPZutQEyd5yzZUB1b5zqYzFd51eevTO5P1G9tdKr1J7Xf7GVt9tM9QijCikVZ6NMh/gD8S65igYkXspbgmzbfWbKhcozfM6JRmIeT3dHQpDNZykltd3Rd0eR80qS3upeYJxJCSl+2asuea4Vd3nz0jjrHpzzhTOd24evvEtLr7UCh0RhuSsrEPVlgS7Fsxm6GvGOuSwCL8kh8ReIhErN46IlrlqAySzd+dANbJfGUQ6/3yYr27iG9MSZnC1803qJrsOqsLRxTzw7GoV2cf3iERQS1C7IK1REXs42xKzNyHUl17eArLIH/ytvalD09V1B+YVpcB3T9mycOcH/DdV2p+m9POWbUz10IZCWMBNxeIZQaD5Dwu02/SWKo5dcl16k6nsfPHYiHuv2MJQj9FHE1Igh9nwljCnD78hJkb3sePqutmLZ5wgocK1mBX7+2H5Fo4nmgq5Ag7rfvHcEn9UPRMmkVAqXbMbx0I5ZXvovrx5m49w+/imAoiGXTcrF0boo1N0EQBi66H77isfBPvRzBJfcg66o/RGDuLdCHq+cVsgrlYkRhVB1HdN9bsOqTn8GE7pP5jJQgCIIgCH0WfkHclDIZS188Ol/p0td6XusPbO7z3BlEN76WFMg0O7xWItRDHH2dx9DXy2RWO2Xih0xgR178MaLrX4GxbxtPinf2lWYq9heAyV9a+MZN4xewqfBXoqmmxjOAvlh2J//iqLykviDX6Esu52suwmqsQ+Q3P0Hk1//RbjCP7nX2vnB6pK4U+vR50LISblqs5iaYpYedBZMn7LyTCtrwMdDGOiIRVX8kdkjCNBHb/kGbdNDEhRdui+EL/2omHWSKPylP4RYYzhf3bMGm3GvBxsdCmfjEei/miSaNNBLl9BFS2xCR6lamQ0hERKK2Azu4nUXffg7RV55C5PkfIPLM9xB97RcX5sKhG7D4yCNqYvcCE5ItMMTxB6GNHO8s2FD90VfV7UGivjbWJhRs6cArQknpH7qNipPdPs1dkTakTqS1gYQD0+fzxGOmdNROe7t8qa+lSdtLPeHf27BLI48VKsKeTO65e7FJliS8E4dUVzPInVDnQjua0E6dYOZJ/HTHqrrXyF2ZRwhBLoUsEge2B4m2PGKWOMGU+Gm/NNZJ3An4rsCuHt17VwpkiSP1+jWddsqWqlLywtZZUiZqXSi95BbGi9f6E5UjuZuKo85F7mYiz/9Q9aHPspUe20rZpbd20OvtQMH9aUp8JLD1WiYhaLLgopjkpnyoc/M4UKUjDvVxapyglYxQP9v2dz01JqNxYrrxYzyocSaNN116vU/u4B7SG2NyGkdR+6frILr+d4i8/iv17PAjRJ77L7bAw+KXLnKx2hiNL0nEZpUlLKbQWJStWqWI6xjDgFl2gp+JYpveROytZxB5+QnVF3yf8xpb9zJb5rtYkMWxVCETC0+pf0wDjxVSxUONqi11IFjp7jOWIPQ33L4kXVcsCELfwqcu1D/8wiLMqt2M0Omdak3b+0/rivvxX2+UY/+x7n3IZhgmdh6oxLPvncbIKVORt+9NTNrza1yTX477v/VHWHjDzdj25hvY8Ztf4M+/tAy6r/udh3v7FOGdIPR9rKh6lvJ8YJMW9axnNVUhdmoHortegVF2kVwADxJE+CIIgiAIAwCTvuxMncDJzoXPnYAiCwUeMQqZTqev/4xP1ieHnR+2mTAnNw0u7kvepJff6gmMXojyy+yXfozom792vt7sgvghJX2Er70JMHrQ68mHvdQXtZeaHqorbfjY5C+X6YvP0gP0dA764jLJ5Q9NqEydG58AoUlV/kLWA3+tvD0lDSrQV6xeevOltjaCvh71fCWjzuNaceEv6j2TTDwpMXOxs9S7eSIXCTT52mfoyvWUBuPMccTWvojICz9A7IPXecKO+5ho2J7IIAHNRRYwpLZ1nsxOsUDlheokCVV/XpcRGUMT3WSFpadRcbLbpzu/lDZ06taKhAPeayEDOmqnvV2+dM/QhiS7KhuIsJWG5mRhA5eVOxHbA/271VDDf+NQW8jJUAxK1ha87ksUXqs7qVC8SWKlTvpCdYT6P5P7c/r9OkpLe1Bfn25Cnklz/cYtr9CLJq8FBIVGAh2vuNcDt+HUa8LT5jWymLLkijbXBlv+OLYfUZro/81PVf1uSLIacUno9XbQDoFgWqHFRYHGOWpMoK+4Fvqiy+Luv7jvUve36FvPqLHr9jb3zp4ak3WVXr/ndXQP6eExOYm9yPUStX+6Dui3xX1lA6eT2l6PtYuebmOqj4jt2AiD3Ee65an6CHINpC+/tm3eVZ0bx/ch+sbT/EwU2/KuWj5gWwaKRW2RLQmFPEKyXkfVZWpfx2JEPX1fx2UYSi7DbouH+tozliBcIHHhC/8rCEJfJy8niIdvmYTc9T+AHkl+F0REiifAvOwhPPm7Q2hq8QiOM+T02Ub8+zMHMOfGu3DlkumYe/4DzBhbiNV33IkDn+zAC0/+Es/+0//B7VeMRUlR++O4TEgI76QHEtqnW+M1occxTn7CbovMyiMwa06xwMVqroZZfxZmVSmMiv2IndiK6N43ENn6Sxhlu50jhZ5ChC+CIAiC0N8Jt8Lcs7XNpD6bmM5rx8KD5uMvm30jxnYavK4z6Etu8i9P5s7JRDpPlHgevOilsHnyMKKv/hzG0QtUK3c0YL+Yg/lAEL4J0+GbPLvd4C2jHqe7dZWVY7t5oMkSB+vsaTXQrma3VOyayoFewvs9IpG0hLLTnrNNoK/4/b0gFFBo2SpPZHXI++X5uTMwVV5IAJNkwWboKBbKdEgP5YlfPvT1FxApk5ztQa6NYmtfgHFwpz3xpfJF7U+fsQD6nOXsCsO/9MrMrcf0FF0s39RJXaav11GX6Hqb67Cd9nb5qm1kKWEgQ1YBjL0fq+vG89JU5ds3dnJbwYRLN/v3ZNT9MNMJ9nR11OG91mz78qyLbaW3sSg57aWJ7gkpk/+u26muQxO/KeXsOS8JQ8jdFLkPYQtbJDxOEYuQ2JJEhWwdJHUi+mIyANtBp6ixELliCVxxG4I33c8urbwWKuj6ja572bZa2BHdHZOp3+nGj/Ggxpk03ozTxfLt+j1PbevKOTpsHx23HRIUUbtn10u0r7oGKb/6rCUs8tSXXc1l0OcgEQu5Y9r0duJ6VWVGfTq7iEojsCE3dNG3nuVnIRbK+HzwDR8DfeYibn/kzk9fsCa5rnubdPXcQZ3Ze6fZ3sU2KQgDkcTEM/8RBKEfcPMVk7G6uAqh/WvVPS75/mapNXWL7sYbx3OwdstJnK9p6VJ476OT8I2eizv++H/gxse/gse++4/Yu3kLXn/ht/jRs+twuNbCgpnD8dDt6tlAOg7hIiDCl74BCVrCG36A8Ec/R2T782r5TXZlFN39O0Q+eQbhD3+K8KafInrwPVjhlA8e2uF8q6/DUNqop13vhnTb2zumP+P2tSJ8EQRBEIT+TCzKL5SNPR8lv8Skl8okZHC/XKa/vsRtXyMT5/NXwn/d5zsPMxY6R9mQG4DArV/goC+9CvqMRbYwwBM/faka2/peh2axk0hJH2G25++ezPNHLt6EEYmHKK/BO7/SbmAxRk/Rg3XlJ+s8HhP0Vl0Nf2VrnjwKqyXh5oAnZr3WGHQdmtt2HMj0uf/qO9Kf1xuu/Ey3vtrPFH1asgsn+jKZXBMZJ/Y7KxSajydRSCgTpw/nqcchN2ep11N1ZUaT4yRYowkbtz9hUdRltyB4z9cQvOsr9nVPXzl3e/K4e/jIYob3ZZFp2F+Lp4MmaSvLnAUHVfeXzNJAP0DK98IgK1qx7RvbWovKyefJ3Tg90L8n9X8KjeqKJpQzgQQ4KRZQzIaEe5VUWCDptfxAx3ZgdeKSQPey1vTug8hlW1L6VXmTSxuG6iKlHyP3ee2NW0gUiBQ3RamWdsgqDAkqgp/7Mvyrb4Q+e5ntQoj6ZAe2GLJ7C8xKlbYLpbsvNgdiO+gKqq9jAcK8lUnlYNWcR2zTW7C8488euGYJGiemGz+6ge6tXrH6Je2TU/JMdHdMTi6XYtvW8V9Gjc/0SbMRvO1he1xxx+MIXHMnfOOm2tv7EGbFKXbjSqIoF5/qP1g0lc6lmyK2+6OkutCKhsF/7V0I3vd1Vc9fRuCm+/njAa27AvFuXPOaauNtrGJRnaW4O3Mh17let1sEW7xK6TMEYTCSEL7IBLYg9Beygjq+9YX5GPrBf8FfV+6sTWD5/PDNWIknXjmCd3e3JIW1e1JDa1L45FgYwydOUEMxu2+gf5tjGja2jkPs+j+AfngzHr99GrJCHjF8N3GHANL/CB0h7aNvYdacZhdG0YNrEd3/DmLHNsM4e5Ctv3SVHVVBvFce4r/pfr95JqvL29s7ZiCQ/DQrCIIgCEL/wIjBrKqAsXcbou+/zEKTOGqgSy+QyXe/C32dimBisoy/QlRPTvqUOWq/Be0HEk6QD32XxNMWfKMnInDtXQjc8zX4r70TvuEetzoK83x50sviDikoSZoYIszSwzyZmAR9fXnigO1r/mJBX/fmFoD81LcXeJKgh+ixulKQmMU3eoKzpDCiLGpgN0eWI4JQaddnLVV/E4NbesHto3R4iYZ5wjDtud0wbR58k2YnxdXTaGTJiIRWDvSVM7nWsuoSDw7s5mjqHGfJpi/nqachcRq5OvNikqClKmHlJwm6rh1RDFkF8lqH0YaOZrcQ3vzTtY3GDK9tL9SWU6/pDNFGTUyuA+oDj+1j8V8qNIFLrq+8+ApL1LU11FkSUukz5avaHrntI7dlcZc0fZloBObZUzA+/RDGpjcTVgEIsjCh+hDf2EnOClXOPdC/66NUn+6558T7wJSJyjh0fTv3bm3IqDYiPvP4/jYW45hwC4zjHpd4ChLC+VSf0JewWptglp1wlhJQeXAb9kL3AdU/EuxexfntYlWfg1lx0lnyoPpH88Sh5Ilicp0zdoqzoHDvqQoaF/hXXs9iQZrg10kA4bH+QmM27msvFKo3z3kzZSC2g67CFnpWXAOf1zKcuk6MI7vV2Hor1znRY2MyEqKkjB2TAllRU+NNl0vaJ/fkmLylKXl8pspdX3xF0jiO8mSeOeYs9A3Y+t3638IqS1gAIiGRvvI6rtv2sKj/cPpbwjdxBlt78dYt9VdxIVBXUG3ACqe5RjuDLFeqsbMXqjPz1BFnKRmrXPWnJPRzoWc+uu9cTCs1gtBHiQtf+F9BEPoL0yeV4MaFRcjd8SJ8ZrI7R8JqbUQkewRODbnSE65qG4ZehdOeEC6egbUvv449G97HkW0fYcPLLyM6ZQUaJ1+O7APv4jL1GHj5kuT3pILQm4jFl4FLjZWFTU0jcMw3ksOGlrFJv8/oI9qs62x7unUVGBiuSkX4IgiCIAh9HIssWhzZEw/G4V0w9mxFbN1vEfndz9hvvBea1PGvvsl+ie5Akzs+r0UPerm/+yO27kC+95Ogicfa87brGK9whV66lx6CSZM1nsk9folNVl+mzHLW2LBbiwzV5r6S4fAVJrtxsE4dVmnczGkhgQKl0zhxCLGt7ydPLvYTUuuxTaAX0KbRM3Xl4g9Cn04TbomvNM2TTh06+IqGwTdhmrOUwDdR1af3687aasS2vQ/zfAWfN45KH02GmGWlME4ddVb2HjTx4Juk0uaZROCJBs+EjEYuBlKEWERfzVNPo9H1lOLmib5ANja/BfM0WftR7YiuqUgr9x/msb0wa9R1Rvs5k30u7D7KFblQudRVw9i1xbaM0BmpX42rPoQs81gqPj43TdSnnK89aNIm6bpQmEf3sksmEkq4+WFB4PaNsKhOXVQafJNnQcvuQ1Z7LJMnv9L2BU5IykMv0yfKN9wK49BORDe9hegHr8P41On/+whkVSWpjg59qq6FzYi9/Rxibz2TLEClMhk9kcUP3snrnujftZHj24j4SMxoUF+m+kIWL6j6ovKkeqJ6pGuOoIlwbdR4/u1ilat+bre6plVfwGIjqmt1XhpnmKc9E6M0+UnWwUpSBISXGjUeiG3/wO7bnLxT+tkCj2fSmvCRC7yhI+0F1T+xexXPPYHq0NihjvOUI687ocp316YkdzIaCQsmznCWVB2QK0Fyb6Lu9VSvjCozjdycLL4MmlfEQFNmHjeEGUH7p1hcsMpPwiTrEpROaiNU7xkwINtBN9CKh8O//Bp2exiH2tNHa9W1Y1vt6NExWRe4lH1yj47JVXlp7vWgoJfxVn0VjwcYslx5bL9taa6vQFZqPlnPz1uJa1mV6ZhJbMGJyoCvE29wx0kkjPLS2pS4N5CA7nw5X1Px/HdAG7dsqr6No/vsdkf9e3tixzT4ps5Ndrnn7TfdMaHq88zTxzjvScIcEvzMWOAsCMLgJj6hKMoXQehX+HUf/vjRpZh0Zi2C5XudtQmik5bD0LOw4JrrsPqu+5xwL1bdmRI+dw9WOmHR9TehoakZlWPX4Mc/fxVPPPkSnvvgGBou/wr8VaUYtv2X+PZDixEKXri1F8IdTYlFD0EYfBzGSGzMXYFtI67Bi4W3ctg86qak32uH3dxmXWfb0617O/9K7IDnA9p+iv43Cud3ErFYTD23pzy0CYIgCILQu9CL5B0bk03tNzfw19zGvm122LUFxt6P7a+FvS9Y6UX3sNHwr74Z+uyl9ETkbFA/6ctNeqFJL5bdY2i5rJT93NJLWavqrAoVPJES2/MRYpvf4Yk7egFO0ER39OWfwnLi4Jf69LK3+hwLD4xdm2F5TOXrI8dBX3i5Oncgbb7oS2mypkGQNQ4yMW+eOZ54yUxfNp48wgIENDXwy9nYxldVvk8l5Y2gNJLp8Djpzpe6jwN93Uvuf1woLf7FKt0pFjO6RCb1mBLIpLp/zjJ7ouIC68oLCUXovPxlOKHGeFZzkypnk8tRn7sC+rwVbcqUXDiQ0MlqqLFX0GRFhWpzVO9U//Tin9JQWQbzxEHEtrwNq+yE7TrApZN67y4ktjL3b098+azyFP/qXV0H+uIr+WvsVHotT+20LZdM25hB15C6nly0vEL4F16mrqGUr2w7u54caxBm6YFEGam80mSuWX4KmlpHbYiWyWpU7MM3VB6G8Re9dJ1RGcVR7YYne+l6PF9mT/jt/JCXvdAXzfxFsBd17Rr7PkmkQUETRCqF6q/qN9T17hs5HvD7Oy0jWibT/BZ9FU71TYRb7euEJmgaau38fLoJxicbVPoS56Sv7gNX3wEtv8hZk6as26kT2ocnqdxrUZE2r52Qmj9ue2rZ2P9Jm77ADVQuOk3MK9ocr6ttc5enveaZLrbTS1W+Xoxj+xD97RO25Qn6Iv7IHpVPcosxU0Vwcb/XSFfvPKFNrgXdOtqlyoIsrVA+3fsWQWLQMZPgv/J2+CZMd1ba9MS9WAtlq/3qbQsJrnCM+q9TR2yrTpFW1YeVs5AhRsKcj97l/oGOZ5cXekCdX13jbttw77U0OavuU9bZM4ipfsHY8g63Ixctv9jO0/AxzprM22Wm+7H44uBOZ0mRZr/UtkVw3ah7KLt9Unmn9JufrOOyiKP6Uf+qG1R7Soh0fXkFPO6w6p17goLyT2ICnghWcVF/GPvgdVjnEoJREs0EVHv20T1b3XMI2ie2+W1odC9S5WbVVnE6eaJbtRce3zivrLXcPPiXXsXu9og210u6vl/do01qb5608nmojsgqi7pnkascOrbTe0QPt4N010t79/qM8toDZNrmSAREoiW65uJQuaprWlfXL/dZF3jNdoce75O7cA+hc/fYmDwa4TqnMmPU9UHWVLRQDosJyaJKdIOKJ+WaTm0XPdnG0sUVv6+rfNL1Glv/u6Trh+5F1ObNc2p8qOogNUC1AxKEmYd32S7WHEgQQ9cbiUostd4gt0+HP02UK9FeXahnKu4P3X3VX2prNAa2KB3nTnEZEJ3lmT6GoLEtHe/Gx2Ne1WZpjMZjQtXWYiSQPu5x2UeWy2YuhL78Gs4Hk65/8da5h9R2l8lYQBD6Mr/+9a9V1xzBPdePRjBwccemgiBcGNlZfkRbmvHxh7sQnn09LM/zZaR4PFoOfISC1rOYtHAxfBkI1He88Tv89o3NaLrzu2ictAa1oxcjMuMqWIEs5G34Ie6e1oDbrp6ihkk9I1TZc7QeOw/VY/78+Vi8eLGzVhCSeffdd3HmzBksGpvHQei/nG/1oSHqQ5lZiH/034VfZd+IitzxOBUYzaEqe1TS77NZbdd1tj3dugOhqTiI0VgcPQD6ELIp5kOroSHH73l+yZCdpxtVaMLChQs5XAx09azk9/vF4osgCIIg9HVo0plfmDrBO4nsQi8QaYLUf/UdtluSNA9X+sI1YPPcnskFelEffed5RH79H4g8/e92ePGHMLa+xy+mU7FiEf4CkizNRJ75HiLPf98OL/yQJwFcaPLFN3+lSleOs6YTVHr9C1bbL509aaf80lfskVeeQvTt5/ilrUYm2L1f5/YTUuuxTaDJSudldE/UVZzCIfEX4wSdy50goQlUeqGdrr3QhJx/5XXJX3Wr4+iLcDpvPA2qHUTffBrsPilFDNFbkDUXsuqSDhK3pBO9EH05Tz2Nb/YSFuwkubOgSROaZKJ2RNfUq7+AQV/2etqPPdHnOYYmrba8bbc7VS6xLe/Y17UjrukI/lLeta7g0tLE7gPo3DGyLuCZeOoQ1Ub1JVewqM/71TK7I9is0ufmZ9cW1Ud6LFIVD4N/xfW2wKYvQXVB13xqP+AN3km33qYPlK9xbK896e5AbcM8tl+1wbb3vEsCTQ566yfNRyI00UwW0PzX3wOvu0EvF9y/0/1yyVVszctrEYDSQxYhom8+w/UVef2X3LdZLc6Es4Nv5iLb1Yinb6D8GNs3cB3TsXTf9VqzoElTnYQeU+c6a/oQum6Lgc6ovs3JO6df5SkOTSyTaxoSeXpgix+X38qWYEg0Sdjtbl88rujaF3ns4U4WIxCArsrBngj2uC+ia1rtF33nBUSe/a/E+Ej9JosccXGm6jvZDU6KxZXOoAljsjbhtRRDaeX7l0oni3M84uPOGHDtoJuQONi/4lr48j0WTlRdkjCCJu1JXNajY7JMuZR9MvUxPTQmp/ZFgpCkeCpOIvLSj+wy+81PYZ0vV88NCZHOpYREb9F1KS5kCdW/Gvu385gpXTAP2YI932Q1/vS0ExrzUB/CeX1O9QV7PgJIkJTBhBr1EVqhKl8PJBaisqf+3Tys2meG0HMi93VjJsX7OmrnZHkuPiZUfZ5JVg7dvk71b/T8wFZESYglCALf6wlN/ScIQv/jnptmYJ5+HKETH9lidQ+R1Q/gN089g4ojno+A2qGxqhK/fVKNw9Z8gZdJRBPT6V5pIXRmF6bXbMY3vrBYDX96rq9w44pbnhKENEj7GDjsqgng7TNZ+FH1TDyP5PcYRHHrOSdUen53P3jZhOn4p4Y1fH4KlJb+hghfBEEQBKE/4tP5JSS7NJk8G/qSKxG4/bE2ll680IRF4Ia77ZfoBcWJF5/p0P388jzpizwVL3856MbvnQR0J6/JdcDwMfak3PxV9roM0UaOg/+q2+EbM5knltqg0usbMRb6imvbvAgeaFxwXXlgV1TTF6QtU3LBoNFL8HagScLAZfaL8g5felPbyMplocPFgN0dTZmbtlx8oyeodpL4Ej2Vvpqnnoby5r/2Lp444y/zOxKq0HXtTKD7xk/lMiIBURvca5C+Is5AfEZfHPPEqmqf7fVL7a5PA09QXv05W9BDE9WeSedUuI2Mn4bAmpt5orYr5xmsXOry9RUNTZ4wVO1NK1HXXwfpuOSotGlZ2WxtjcQA/hXXIfDZx9pYevHSE/07HRe46X6Qxa7OyojEMWxpxoHuCTSRqav7NLlTSXu/daB+hPpK/7Jr4L/s5iShR1+BBZxuWaaBJt7pHhi45nNc9qmQoMF/xWegT5zR7n2UobpWZa3PXobA9XercYhtrcWFx0fOZDaNidzxUVysTO1ZpdE3azFPQHd4/0mHusZYjEBCVtfyQipd6U8HWDu4EHzjp8M3f0VyuZJI88M32Q1gT47JusKl7JN7bExOQq+lqo2RiCZN+qmc9BkLoaVxuXkpIAEdWbvpLr4ZC+wxt9etkAs9I6ny9JMVwfauYQ/akJFqvLWaPyZISxfrmKwQUT/omzqPx2ftHu/0VSTiDFx3Fx8nCIJNXPhy4cNeQRAuAbnZAfzhPXOQ9/a/wN+YfL9vHToN0ZmXY+0vnoDRgRtH2rb+Vz9DWc4ENE9OtnamR5qQ+/738cjNk5Cf63mu7QFcPYO4OhKEwcO5Vh9OWm2ftUiosrL8LSe86fnd/ZAqftnrn8znp9AfEVdHgiAIgtCXUPdfcgXiKxrClhLaDSPH2V/hzV/JkxD6rMWgybfOoBfMvkmzQe6HaJKGvrAk6w00MUQvQTUVt0YTeDTBsWAN9Mkz4U7k8ONVcxNPgNALUYqLQ24Bv5zVho3hrzpp4s+/9Mq4uxUmXb4mTG/zMtWn4vENH81WNjhNKk9abr6drlETEVh9I/Qpc20T256vMX0jxrGZ8Djpzqfy5COXGSlY9dWcN3c/EoPo0xYkfWHbZTKtR0+gLzvpi3TXlPiF1FUqWk4urMY6+Mj6i+ec+szFPNnXLuqhmiYraHKDobqgc4eoXlS9q/g4Dar8SYDFrhvUPnEyrPfuwJYOmhrZvHpSnshcfEfx90ae2mlbLpm2MTJTT+mI75fSJuJkWK50DZJbD56gVfnm/LnXrduG1PXmGzcN/lmLeDu1IV31LSxmownzLNXmaH+6xkdNsq/BmQvZRL73/HRdkhAvFY3KMUgvfXx2+6X48lVbHjpanWcy9KnzeDIs0zLiSe4p6rooKFILKs58lQ+qQ4rXyRMJn0gYFbjqs/CRZYU0k5Rtyrq96z7cAjTWJ7Wz9vLaEan5yyh46rTt8ar8pql0eFxZJNGNdkpc9PL1QHmxmho4PnbZMlr1bcuvUfeFSyA+S1PvbcMotqpAk8000eynCWe6XjsSmTn0RP/OdTVVnY9Eauoa4uPonklxONcY3U99qo+nCUxv2dt9w0xblKZaFh9LQcUZv6dTnalj/ZfdwkLWdPnKtF1m3H7pvt7a3OF+RqpLD5Xm4GceYrdFFvVzbp9F4gOamJ++0Ba9tHfN0j2B+ikSlKjf4D5KjXG4LFXbp3uCKgu6Fv2Lr0Dg8lu4vlLR6AW56je57Cm4Zeker9oK3Z8CV37WFk94yLTvpzri6yEWUelTeXTHSDR2IqECCQhokrxL94gLbwdpr5d27vUZ3+cukK70mdTnkLs/6n9IgBdPG5UxuQFU+eqJa7Y7UFn1SJ/c1XuIoqfG5Dz2pDam2iVZlON4VH7s69MWpfG1Q/s66WvTLnqyjXV0X2/TB2UYnPsrjU19YyfBitA1quooXmbqfjF+qrr+b2NRUfL509cFt0uVP41mutR1F+/b6BmMrkvKvzOGz7gPUfXA40K1np/nqK9y2zHFS22YjlX157/qDo6rDV0YX6S2O073hT5jCcIl5Fe/+pW6BGK474YxCPj750SQIAx2Rg7NxeH9x3G8RkNkPLne0KAbEQRO7kTQbEVB7XEsvv4G+J0Pg1IpO7AHP/irv0XTrf8TRk5iQppcYGbvextrWj7AN7+4qMf7iL3HGrDzUB3mzZsnro6EdnnnnXdQVlYmro4GAMcb/SgIWDicPwf7s5I/ElhYuRGLKj/A0NbyHgst/lyczp/qnEH1lajD52KbMSRkIqhbmJTfda3IpXB1RG6OKKhnqPT2j1pbWxEOX0Tz2oIgCIIgXFzIz35jA8zzZUBU3fM13Z5QoQnHjr5EpuOaG9kfvNVqm8D3FQ8HCks6Pq4rqOGJ1azSRn7yYzE7XTR5pOswThxE9Nf/YX9JTWgaAlfcBj+9OB+odLeuehhyzYK6apg19qSjaxGFXpjThEx/ZCDmqT3YAoG6pvi6zaANsSueilO8P7kEIWsH3f7SPxbl69lqrFVxBHhSXiugL44vrIw5T9XnOF43TzypnG5yVugyF7t82SVc2XFYqr2QQI0m+gY8PdG/e++ZKg77GhvJ4oVM6iq1H+zxe3oPEvnFv8A4ssdZUsWVV4jQ43/Bk9ZJfRYJE6gMupgHdmHVWMfuVywjat8Tho7iCWcab3QGj00aapPvKV04PiOozdRWqTZTQQnm+mLxygVel/2pHVxSLuGY7JLc83pqTO5tt+R3fcQ4e6w1QKFnJfPsKbvMqC8qIhFy98Y83r4NgRBb8mPR44X0KantmOKlsVkexTuwxr+C0FPccsstPF/ym39ehqzghYsbBUG4NNQ2hPHZP12HY7f9ixpKmyiOVmL8ibWYMKYEt37la6g5fx4jxk9ETlGyWD3S1Iin/+E72FSTj/Mrv5x0Hw7Ul2P004/h/2/vPqDkqu48j/8qd3VOCq2IEBKSMAKBkBFBRCHQYsAswgYMtmF21x77zOyZXZ/Z2TA2a3vnbJhxWI/XZhywPYwxYCybYGQjMMIISVYrh24lJLUaqZM6p4r77qtX3dU5SN1dLX0/59zz3rvvvvtuV926XdL7973P/s0KLbms2Mk9f37xu0o9+2qFHnvsMT311FNOLtDTl770JZWWluqz10+zUj8BzJg03jodUGWrV68Wrt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+ ] + }, + { + "cell_type": "markdown", + "id": "84cc8c0c-3251-448f-97d2-e2580a292a15", + "metadata": { + "id": "84cc8c0c-3251-448f-97d2-e2580a292a15" + }, + "source": [ + "As illustrated in the figure, ChatChisel is an LLM-based framework that directly generates Chisel code from natural language. It aims to assist human designers in the front-end design process by converting functional descriptions of circuits into Chisel code. The generation workflow of ChatChisel is as follows: Initially, we provide a module description, including the name, functionality, and interface information, as input to LLM1. LLM1 decomposes the large-scale designs into individual modules, referred to as leaf modules. The descriptions of the leaf modules are used as prompts for LLM2 to generate Chisel code. The generated Chisel code undergoes syntax checking using a linter and functional verification using verification tools. If there exist errors in syntax and verification, LLM3 is employed for error correction. If errors persist after multiple correction attempts, human feedback will be involved to guide the fixing process and regenerate the Chisel code. Once a leaf module passes functional verification, the generation proceeds to the next leaf module. When all leaf modules are generated, LLM4 composes the leaf modules based on the module information retrieved from LLM1, gradually forming the top-level design. Finally, The entire module undergoes design verification. If the verification passes, the design is completed, and the verified Chisel code is the output. Otherwise, error correction and design decomposition will be conducted." + ] + }, + { + "cell_type": "markdown", + "id": "de219e8d-bd93-427e-a392-b9ce5701a172", + "metadata": { + "id": "de219e8d-bd93-427e-a392-b9ce5701a172" + }, + "source": [ + "### A. *Design Decomposition*\n", + "\n", + "To simplify the decomposition of complex and large-scale circuits into easily generated modules, we employ an expert LLM dedicated to design decomposition. We apply in-context learning (ICL) to make the LLM adaptable to this task. Unlike fine-tuning, which requires retraining the LLM on\n", + "specific data and is not cost-effective for large-scale LLMs, ICL allows the model to adapt to new tasks without updating its parameters. The system prompt for the LLM used in design decomposition is illustrated in the figure." + ] + }, + { + "cell_type": "markdown", + "id": "4f616f63-9c1e-48a5-be2e-fdd22001bac0", + "metadata": { + "id": "4f616f63-9c1e-48a5-be2e-fdd22001bac0" + }, + "source": [ + "
\n", + "
\n", + " \n", + "
LLM1 Prompt Example
\n", + "
\n", + "
\n", + " \n", + "
Example of Decomposition
\n", + "
\n", + "
\n" + ] + }, + { + "cell_type": "markdown", + "id": "67c93c83-641f-4c39-8f7d-0033bbebfaba", + "metadata": { + "id": "67c93c83-641f-4c39-8f7d-0033bbebfaba" + }, + "source": [ + "In this prompt, we define specific rules to guide the behavior of LLM and provide an example to regulate the output format. To illustrate the effectiveness of decomposition, we compare the decomposition results of the Hazard unit in a RISC-V CPU. The Hazard unit, responsible for stall or flush operations in the processor pipeline based on input signals, handles tasks like data forwarding, data hazards, control hazards, interrupts, and exceptions, making it a complex module. The figure above demonstrates the results of design decomposition and shows a portion of the generated circuit logic before and after decomposition. It can be observed that the LLM successfully decomposes the complex Hazard handling unit into four simplified modules according to the specified format. In the Chisel code directly generated from the Hazard unit, due to the complexity of the module logic, errors occur in aspects such as treating the module output as an input and considering two forwarding select signals of the ALU as a single signal, resulting in five functional errors. However, in the leaf module DataForwarding decomposed by the LLM, data forwarding is handled correctly without any functional errors. Therefore, it can be inferred that design decomposition through LLMs can reduce the complexity of each module generated by the LLM, improving the pass rate of function verification" + ] + }, + { + "cell_type": "markdown", + "id": "915306cd-4f33-418d-b31c-aa5a8ea380ee", + "metadata": { + "id": "915306cd-4f33-418d-b31c-aa5a8ea380ee" + }, + "source": [ + "### B. HDL Generation\n", + "After the design decomposition, the decomposed modules are used as prompts for the second LLM for Chisel generation.The prompt for this LLM is shown in the figure.Within the input prompt, zero-shot Chain-of-Thought(CoT)is applied to improve the quality of generated Chisel code. By appending the prompt \"Let's think step by step\" to the input of the LLM, it utilizes the CoT to output natural language level analysis and reasoning steps, which are then used to generate Chisel code. This approach enhances the reasoning ability of LLMs." + ] + }, + { + "cell_type": "markdown", + "id": "8ba57f34-e9fe-4c75-911b-fe007383e600", + "metadata": { + "id": "8ba57f34-e9fe-4c75-911b-fe007383e600" + }, + "source": [ + "
\n", + " \n", + "
LLM2 Prompt Example
\n", + "
\n" + ] + }, + { + "cell_type": "markdown", + "id": "4f223dff-6383-4025-924a-5c8eb7515a6b", + "metadata": { + "id": "4f223dff-6383-4025-924a-5c8eb7515a6b" + }, + "source": [ + "After generating the Chisel code, it undergoes syntax checking using the Scala compiler and is transformed into Verilog code. Functional verification is then performed using verification tools. If syntax checking or functional verification fails, the erroneous Chisel code and feedback from the tools\n", + "are forwarded to the third LLM for error correction. The prompt for this LLM is shown in the figure below." + ] + }, + { + "cell_type": "markdown", + "id": "c6ef5b34-c48c-4979-90e6-1bb2f45f21ce", + "metadata": { + "id": "c6ef5b34-c48c-4979-90e6-1bb2f45f21ce" + }, + "source": [ + "
\n", + "
\n", + " \n", + "
LLM3 Prompt Example
\n", + "
\n", + "
\n", + " \n", + "
Debugging Example
\n", + "
\n", + "
\n" + ] + }, + { + "cell_type": "markdown", + "id": "ea771105-906c-4c6b-a46d-f3da88d23c69", + "metadata": { + "id": "ea771105-906c-4c6b-a46d-f3da88d23c69" + }, + "source": [ + "LLM possesses the ability to correct syntax errors and can rectify the majority of them. As shown in the figure above, the LLM can identify and correct errors, such as using character values as module inputs instead of bit vectors. However, when encountering complex issues during function verification, it may get trapped in a \"snowballed hallucination\", wherein it becomes stuck in a loop of errors. Therefore, if the LLM does not pass functional verification after a certain number of error corrections, human feedback is introduced to help the LLM overcome these hallucinations." + ] + }, + { + "cell_type": "markdown", + "id": "a923c01f-d340-4200-ba18-f0a7cf2ec380", + "metadata": { + "id": "a923c01f-d340-4200-ba18-f0a7cf2ec380" + }, + "source": [ + "### C. Design Composition\n", + "After the generation of all leaf modules, the fourth expert\n", + "LLM is introduced to assemble them into the top-level design\n", + "The information of top-level design, leaf modules, and t e\n", + "connection specification is provided as three parts of he\n", + "prompt to the LLM. Notably, if multiple leaf modules con ect\n", + "their output ports to the same output port of the top- evel\n", + "module, the LLM may only connect the output of the firs leaf\n", + "module to the to -level module, ignoring the rest. The efore,\n", + "the information about these port connections, provide by the\n", + "decomposition LLM, is essential for the composition process." + ] + }, + { + "cell_type": "markdown", + "id": "b7b7d41f-b02b-4fdb-b802-9dd7030a44fa", + "metadata": { + "id": "b7b7d41f-b02b-4fdb-b802-9dd7030a44fa" + }, + "source": [ + "### D. Reference Model\n", + "The reference model plays a critical role in design verification. To ensure the accuracy and functionality of the processors generated by the LLMs, we design a reference model design infrastructure featuring a high degree of customizability, scalability, and design agility. To enhance the design agility, we provide a design modeling library consisting of frequently used modules in CPU designs. With a module-level modeling template, we can swiftly craft a reference model to align with the given hardware module for module-level cross-validation. Then we interconnect each modeled module according to the design specification to form the system-level reference model. The infrastructures are exhibited in the figure below.\n", + "Since both module selection and port modification rely onithe outcomes of LLM decomposition, the reference modeleand RTL code can undergo cross-validation at the module level after the RTL module is converted to signals through the interface handler. The system-level reference model will be pre-verified with the Sail model before the cross-validation with composed RTL designs." + ] + }, + { + "cell_type": "markdown", + "id": "43165092-1bc5-4946-9c8e-68dafb4af4f1", + "metadata": { + "id": "43165092-1bc5-4946-9c8e-68dafb4af4f1" + }, + "source": [ + "
\n", + " \n", + "
Reference Model Design
\n", + "
\n" + ] + }, + { + "cell_type": "markdown", + "id": "0ade05bc-c010-470f-947d-8127d89efc5f", + "metadata": { + "id": "0ade05bc-c010-470f-947d-8127d89efc5f" + }, + "source": [ + "Notably, this modeling method improves the reusability of\n", + "the modeled hardware modules and the reference model ca\n", + "thus rapidly scale with a reusable module library. Given t e\n", + "unified interface and design template provided by our refere ce\n", + "model design infrastructure, the customization to model new\n", + "modules is also greatly simplified." + ] + }, + { + "cell_type": "markdown", + "id": "44216903-a0fc-44dc-99b6-d385757b3721", + "metadata": { + "id": "44216903-a0fc-44dc-99b6-d385757b3721" + }, + "source": [ + "## Implementation\n", + "\n", + "### A. Design Objectives\n", + "To evaluate the Chisel generation capabilities of the\n", + "ChatChisel Workflow, we design a typical five-stage RISC-\n", + "RV32I CPU featuring M-mode and dynamic branch predicti n\n", + "support, using the ChatChisel workflow." + ] + }, + { + "cell_type": "markdown", + "id": "1770309a-a3cb-4071-88b9-fbe17fda8be4", + "metadata": { + "id": "1770309a-a3cb-4071-88b9-fbe17fda8be4" + }, + "source": [ + "#### Architecture Diagram\n", + "![CPU.png][CPU_png]\n", + "\n", + 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BiHiZpqr7HRCUXv8AVrkhTaUVXS2Wws3GmrL+OE+yRF6u5jR1bqsJVht3758pQcTk9dbxJwFlFLpDvOEtNLfa3IG/lPkd6Uc0jPWBOTEz5ZY7NSYZ4xAlnCl/LlFPu2IpdVmyqLNVnktYvUraTSmGibuTUcxcu3CtCbJrEjV6lzRUz7e1OU2pPVlHAulvtbkDfynyO9KOaQFSwAAAa0Zpdh1ll4NE7+a11DZca0Zpdh1ll4NE7+a11APocBOwSwq8ErHHzOs0baiPmEOx7Xi18LcQm05c88MW6427i/AKE4G+u5RQekLaEtpEUNNPVUdYSlB8lz6Yqph8vfJKCedsWDZI3YvFjNm1etV0U7QdJ3rW74Xg55WUCev4DeMBo50netbvheDnlZQJ6/h0netbvheDnlZQJ6/gN4wGjnSd61u+F4OeVlAnr+OZAx91OpeFObMs4n5gGI4y0xxSXjwdhTNzEJ1sN3qx+LXZSVWWjRJrPaq9dj93OloFVatrSGrMVUj02RUmkpmUuOnFdUSVw0HQRc7deU8Vqo+lmlipQ49c7sxMZM3ymweasVJkZ80Ryb+57Mm04ysNc2YoUG+tcSrdUrjdeLYViyc6WS57KcoJ6hebbtRkZbtED5A9UR4JnSt+9s4uwphi+0PG8nrSwEcWOmZ6FOuLL2buQ6Fq4yAwVIR7HjQk1lL2Sqi9MiZCxjg5srTGfWPZOVY1cUZl3o4TMzWn3YZlloOggsneC4dNwlrtF/sNeHjSsQ/9IfYxhj5j5j5sEd2Vs4ZjQqysllJjZiZFY4xFH2TLBaUrsCBI5x9eFiJPc8ORy+EldabJNzEqsu7LT5fyajl35JlhwM5OdLhVGewY2Q2vjXOxiMnC3H/X23HlOLhPxDFm0/HFbT5FyJkImdNxrFphxyStILPdUsPA4XPrTUi5HO2Wi3XhIy6qu240kdGtvF1OFZLG10+F4wGjnSd61u+F4OeVlAnr+HSd61u+F4OeVlAnr+A9JsJ7AXOHwQMlvMw9Q17dgLg94IGNPmYZQ0xzs2O68nThDmQ2Gxnlhi43I48VchUFvN5ByihBXXF1cV4jd6ekoyMkp75MH1RVVD5guRTk4iXvnDpy/ZLFrN29dooqYJ7HdeTWwhw3bDnzywxbjkbmKuPSC4W8vZRQgkLiEuJERtBPVkZZSVB8lz6WqpZ8uYIqKceL2DhI5YvFjNm1etV0UhY0BLvILY7hs5YTk9Gx+2g4FR1OJlnq96JnguZNY5uFupcgELHKi1rLrRVR5Hi6gz1dXKFUV32C9qyre9pRVa0FQSluhPUycHNeP3X5jVLamQh/YeyC2K8tFT3veOS4wDB2QscXAtl79shfMGakwy4XhHRc6p3OS5C57pkpoWyVi+tq8hJCbzR7ELuauP7VsO8aXl//AKYxxUsSQ1EPFoyGz86n4wXQ3nsyHlswysczReDTWU9xNh0Nxa94SgjrzfXkkwbS1hHVCN+wcT1JPNGCZwretXy965arpq5reAAIRP3IFPxUz53AZFKLYPve1EOu3Xw8SbKTFRPQz7yWiL1z2tt5plVtW9kmotxyL19NRevB22YLpdJ2o9cKm6S/ua7ti5ZK2G47x3L8yzhXhRNTJaMFPKRk9vMYw78PDcbyM2StpXJtSQJYnaYJni11Q1UlXFa4+Z9Ub8FKMfkWny4SkNvey67qKyQpYA50Y53NqbKlGQm9Lcw49ZgQ81cKcnst+J+w/wAbJ8g2KiShiFwyjcnMCPJNlKash4hy1Tl4k+LiXaekDyOW+Cx7Ms6y5Abt9cdpQu2Nj5qVtgLgwnyTfs9qmIynFEnYJ5MOhajqKmTLrLkyA1pbg5dcTMbduUHTJ8lNHJwgRLGlBnO1z2YuxavXlAqRfKI2eSJ8yx0wLPgIcwtlhkpi62MOrOVp/HpVgWZsS3y80hHiBkSSgyhBKlj5j2gTTcQXK/XZJbpZ+QSUsRqiPcqoutMjnG+8kupFQ+STWWktxG/e9jPFzcTXI74xL4kXKHW3KNWZrtTWfRilixJzacmSmHS6/wBluiQ2AmSi86MmpITcki7TvISZCctr7EgqCaE6RnKnPZDRLrLLKKSVDoSGpWffYJZq+CVkd5nXkNtRqVn5zxxglmrzzzxxxxiTkfzzzz+xxxxxDry6vPPP9zjgB6DDDsPMUPBqgrzXNYbKiTGI+yTXY38UsY0Fez3wtRFxEx7hdIWkVXylg1NVkhWTY3bZJRS1ROOvqycIKJA5ZvFDpI3ZtGSpm1dsX7Vu7bro42E6TvWt3wvBzysoE9fwG8YDRzpO9a3fC8HPKygT1/DpO9a3fC8HPKygT1/AbxgNHOk71rd8Lwc8rOBOP8j/ABzGkPuqRGw1zNlvEfNG9H2U8DNt7V/A3nNiC5mM8r6/FzmoJrTKOyaymmtXGA53QgJaxQhSUrRsrMytHXGyslkiM10xdsV3w6CiXbsXL4rRkelnIIjFHLucDEh3VC7GtFz6mheR95e1m4nxjGihGaU+HVWZce14jeLoJ+YpFiaNi95PLGb6wcqdEhNuxWnJxy0QvnletPSz1EMTcusa819rapNuK8xM6aY0UNXzKTa19pnb3JlFWreUz0Ur7bdreUy6e5WW6Sqcppqgba7tR0VfKkFJOO3062VPlL17ddk64IPYSfjimo7qlYzYxgyuyGzCYNakuNG9dV5MyVv5EX30hvCoqxidB9ipNeS774aSYi22+vkKUlpcLDnXuSCzUvB/iU8mJOO4sTU7VvHiY8T5BOct2G4kTZ9cmNyyecUqzu4UCHYiUUa9jdkNPiL7iuSrIDSRaU1ccDbcKkpX7ZNLTrtBmwd5wXn2yG9GaDqYjdpFPcDUj7Y9iiyGwR59r6pJvNSH5qQUUpz7TasWf9jJpAtZ/wDJWbNv9p+0tW6epRxTR/xqjSOZj28uKS4VKx3IiPJRVJSjJGwmOVZbySvEUFNddk2nHr51DSFlZIvQiWTDKQeodzUa52tRuJxNQSlOZ23F9siMiOup+yQ8mrHzGa+z3HlUcrze7hSGm026mWY4nXi8orriXjhBHSCFrmqni6bUDhcvb5q49nc46vACuoDRzpO9a3fC8HPKygT1/DpO9a3fC8HPKygT1/Aff7EO1/5z+B3k15lXsPfYi9ihjD4PMLebZtCemeWx3Xm6sG8zWw2M8cMnI5XJijkSgt1vIOUMILC4vLixELwT0lFRUlPfJg+qKyofMFyKcnES984dOX7JYtZu3rtFFXt8Wtk2upCxjxzRFvPrCtHWUeCIhSldIVcp4MT1RKU0+P28UPpqkQNvuybInyJuzdKnCZq1aMFjFq5ZvW6LlFVPAVaAaOdJ3rW74Xg55WUCev4dJ3rW74Xg55WUCev4DeMBo50netbvheDnlZQJ6/j8c7Ota3PHPHOwvB3qc8c8fsZZwLxz+z/Bzw/+OeOf4OeOeOeP3eOeqA3kEtErt2L98VpEnpZzWOfFD+6qEbDzMeW8RM27jByehFpvm7YiHOrEJxMl5e+eL3FSUWmMryUyGksXGA5HKlIqxYS5LVItWWrygOBvrSUlRitnaaarlhcSMtcbs09rTrm7FmYWbNMZKWr6KE3lxNA9duXUdas5Ty6omG260FQsEHIzHUUTlRMPnWs7EhFcJMippxwym2ix8pdvBdQAAAABxowxf00omA7bT8hMC7bsySl1XmCHWnIZDWFNaW/ZqyNkmTpRb8VMmHM5DOOrbjmqaXquXEtCjGSUnI1ApbLosE1e3ILW97RtZRw7LgHPes59S3i+n4c4OT/mXgrjBlY2MGYdmbLLIXOlxFna3HI9FCwai+yy4zZZXITFiiTHu7ZAYkmul8yIUl6lOZiQ1Umu+wl6qWENVbWRoL2UTfnhehOOMO1XGdlvhRbWS7uyCnF6JDjyeg5GJ42TnbxoTE2CWfGM0wOryehZFPy4rSlGkqGJbTm604fZ/tCw3nY5n6jXW8FygHKFlRJuW+ekZYLsyXUzFOO7atulm7EKXYQf0ByJkVCkgmYEY+WxePVR/NhbnmJCUsRPxciU09DbDXUZLtO18mYlk9uuRk0RrU3nrmqK5rbarMOFb+ORlEMLNCH8+N3TMNNyDmJZYTUvtuCEzI9pX3yqN4ufOlzshvRMalTukZfsXSdl0PZTWVu2nplB+knYDpTAc7UBbpkiQXfim7XTlhrWdrNy/kVkxqTw5iCTkFTzLxrU5uuVl4Xvvd4pmSMjN+cHEnOG61mDMzDQMfYU95a6/Dq0kPNeJRnfSJC6JQAAABLRB7djKnitIB9LPJUVLETpGyOx6x13RPtVyCniGYKS3Hq/glPbylMcoMiMSC8fJ5W5JmTZFFOPZcRC6ocKl6qb5gsRuX71izVTdu0U0c8Vc7ndJ3rW74Xg55WUCev4DeMBo50netbvheDnlZQJ6/h0netbvheDnlZQJ6/gN4wGjnSd61u+F4OeVlAnr+JP7c907Pxagpo5P4FZiYK5ELcUvpMKzZitcniIXsrzFErzNEUI0tMHhjPW/I6ZIccLvKWoJ1bd4PoNLTXHmvPFsuUs10ouUCsGzvta2wvwHMsvMI/xnrG3sdoD/mWiz6DIQ5cjP3Sjr02Ma5M4I0OOU1jBks58JsoEVPhKZVAlZTna51OCnsTKIsVSmXtEmm+TSiqHSiQgIatZZT/cane4LI7EM8cU3K+o3G3sdoD/AJlos+gyEAzSAAAlnqg+TnMzxpmyX0qn+KmCCevHN3C6D0fNaP5qy8xfiB+EdoOxc+dZMoz7FMfu4mRUspH8ZTjpptux2JKyXKHy/PF8kYvEqLJqzzxdsV3KOfZChPSd61u+F4OeVlAnr+A3jEgW52/OZfFA40emflkNm+k71rd8Lwc8rKBPX8SsQNgGB1nd5LMm3c2cRrUbKGqvHliEJBuZIw3Qxzr4SMuMnnArM0o7KnnwgmXWloK2irai3rJ+tXJJCulqRknaJKBS9eDo2AaOdJ3rW74Xg55WUCev457djn3R1RrozEYKtH8hYzbB8Ep3a9o0eQIJmaM1uc8b5CaNacjPFMKrsfq7jSFVmOZLPJD7ayZKCVZVnG5jr0baE/W23GuWKlQtVso+U/U340tgeiDmeKljmMcG23BPZ069USlitMZFZeyPswj1feMJvEtw0JpYydxiTmATNHVxkHDF/lURU8+qpSYed7LUXWx7SqpEUylzXD5q0Xq6cwAAAAAAAAAAAAAAAAAcz2ozFbN52ax8GnKxdo8sRSzlzG+NlFtxukYvYiOpMZSQZRLNZRvEXI8YsVnStFk63zxZtKC8pHVMxTx7M0YuXOeahuFJOsvMKXFuHXE/ttU3LKvAkqWpqiw1bxVw4S+G5I9mPZCi22vXbCVFRIut2uGPKb4R+UhdtKSNzWsUKXJDlUTUs4TynpD7UVrt8FOKPo/YFTAEtPiabCu/DzT5H2D/ANjYgn90RwXlsgYNEIAd2bE8Z0yjlFKTNY8H4qN/EbGQm5nm5GcrkX04XyTUIhiMpJ6Kjx2hpfs1ZYaRsnzcPONDbC+Zttp0K/FfZuPhVJqdWo2liogSqVrBIwm2FSorY5UbKcbvljRohaO82+TNskZMkiZgwVou8WL18oWvXLdVyxaqoD+dJiPo32tYT629hM1Tzly5cWonPYJ5duFy4Rs5URpWpk2xzjxIVZsjKhNUuLsTRwdUilkuUuOFi2nTJ5dKMG04o44+WLPF+3/Qoib5K40/m/Zv0cTRqBti7Vlss8ADMj0dZGG38TfJXGn837N+jiaAyAAAAAAAMXTHCMP5CsJXi6c4zZEsx6u0c8KbQfzcTHMi3b3Fq9ZsH7BRULmOCCuRpMXa0xaT+SqslGKuDSadKmqKL1M8MVUt0QDsAyAwybssSw98cmhh5jZkRGbGl94XJSWItdcszflXHDnazSk11kjssKMck25CTLoazUfj5elLVu8qthEPFEoyUTSNYBMBlduhyW8WBg96VuwkBTNR/e89/EzX/cViZelHtR+uXwQYR+hSYKaKP73nv4ma/wC4rEy9KPaj9cvggwj9CkwBUAAAAE7tu/aqNk/gJZYeYx8CiIndt37VRsn8BLLDzGPgButFvyZRz/IRo/R9PHux4SLfkyjn+QjR+j6ePdgAlpqL7HeevGQ7QvT6yCFSxLTUX2O89eMh2hen1kEAqWAAAkTMyxl7MmxmRMZoUy+WMYY4jPCjG+dfcqBCELyqbcj3lmdMtWA5L6idk5tKykRL2UGHGZbTyqao2CNi5ZUb1ZK4YP136PcfFF2G8/u7bJA8jXEr1OH4ZXboclvFgYPelbsJFPwGuOIGOqXiLi7AmL6G5lB5okCRc0orRnUrECyWqrySzUqwjJqkpkCd8wULqBgmWs1HaStzgtWZ9tuWLVi1XTYt6g7CeyW08+MSc3oAZvCpglnsJ7JbTz4xJzegBm8AqYAAAAAAAAAAAAAAAAAAACM+15hOST5p1MMVoy2/4JcS/nc/LabK8WlWEdfjRqI4GZiqhi83ysnMuQ2LduKpMkYQj3C8zVq3Slqh6sjQTVKSSiTyd0fOTPfhth34qa/f1IB+M+uyy05eHnJ36PPNYVLAS16PnJnvw2w78VNfv6kAdHzkz34bYd+Kmv39SAVKABLXo+cme/DbDvxU1+/qQDVfN7HiVsYMTp4m2UNr+xF/NJoR8s2K4ysMPX4sH5bcDnooabPh9JRucFT/AArrMrO1cRY/Sk2sibsmzzisWzNistze6l8h+m6XL36rFd+xZvVFr3BgtVdtUXKi5ji3ds8X7HNdPPNq9xZvXrXF23zTX7Xdu2/ZexuVcch/NH0yfc1u1Q9IzLyies1SHrCbpOsuoJqihn1ArlE50MxfIHzKP8G5I+QT2ejLlsrdS3AmzEbKm7NygvUoxW7US9WVvdrmlhNNo2EKkkKC8quk+lZnbIE065160jWFxxmyOwTJYqZXlmy3Ehvt6yqq961WoKNpBQURGtnDF6hLSE0jxYJ2axCWenfsPnZ4cmzL9Ijk6AqYAAAgk6Mf5LnbcFmpbjrL/ITFCpsYTa+61e7AqVACpcfdKzJWdVJG26eJ0hKZKLFDa5SzlSNy2KG7XcqXlXrxUq8UJfCdtH0fOTPfhth34qa/f1IB/mEu3D7BvAj1ueczYGKmAJa9Hzkz34bYd+Kmv39SAOj5yZ78NsO/FTX7+pAKlAAlr0fOTPfhth34qa/f1IBz9/dD2JWRvOKjBxRZ+W+e+wTIHKKUEAvFWNa1HOIqyjkkWM1NLcL6mZ0GYlxKYL5a7YZFpQQmqac6e/maRInpBJVOJUOM6h0JB7tOH6eCxekxWb4sWeDdyzaLXDPFqjgxcL2a7t2zYrvcU+2VWbVwxfuWrVVXNFuu9drop4quV81B/OiiHQZsC196udgU55E5lO2GUJUxCm9WcWEMNuBOe7JeBkzHB0rRam9ZW7K5G1CwmcWqyVVUZIi8v2ifNm62pgb1zk0Vu/0X7P8AarX/ACdH+bwJibre1H7GvBAnD6Eqgp3Z/tVr/k6P83gB+wAABzi61sdcyH5jk8XVE+w94QQwlPMzYpwhxYlY048yEQbNRHPzJNPVK7DufbbUHSq8rauVPuC7wpm7vBC8qXE0l7WnlCtujfz4o2w3vtsgeRriV6nD6/Td2FKh4Z2yv9IvlKKnAJg/FG2G99tkDyNcSvU4fX4XPDJxBzNzQxeyAyQUMlkSHYPwslJiOpZimLYrVUlVndyZfJL1TaiEXoCIUUE+spDDKqJ1K1xQMlTNlQuFrpe0fuWOKnCYEDdtw2Q+CBrB+m2xcBT8AAAAAAAAAAS32oqjlcTJxQxiRHc6GI3s3czY9xllh0sdaONl6F4X5iuaZ1k9tthzptdpVbR+R21B5mMDi8j3yywlIb0VjaUcJqFouatVIEsNkXy0ahfGiofoLZ1ANumHhniLGDSQmHH2MMBNFoNpPLJaIgosSMUqRJEytqizb4444Q+bpgxXTRxWaPG7l88eMc3DR0wYM3bt6v13xcMePmGhj8lzH+oxqQ48qsuXPkxkBAONuMWOT/R8eCMQ3HO+ZwzFkyDFJbUpcZ5t4ESiCzWFhDkaVqIoxUldJm1BQeJIwaMVW67KZbt81ew8rF+y8nJV/AZLoho4hODMOc8nsbJGSjT6pN2IFl7EWNsgHBMCaiqltm2S0ztiiS8eHTH7WdBaiPaFxvKaa/b6amHbZpi2w3h+Lhjx8w0MfkuY/wBRj/NWN2O1dNVFcCQtXRXTzTXRVFrGqpqpq454qpqp5QueKqauOeeOeOeOeOeOeeOeOoMMztlM7YyyUgDF5gxa3H4+MioQy4lJnrbvk1TjhqJDmxmtwVaQ2c5TSLGEnK5ZCkVSm4sXVXoloysoMMi3b54myH2YUraaS1Oaea2xV45KzRiymYRYV2JBguMYRlh2rB/Y9OdpmqLdntXlxFZ5JuKBfV0aWza0mmoYdFxyllNvJBEmXPoFaWorNw0o2koNjIGwhQ8WclJHkHHdQQItxnmRi8G5BxbbaF1sYqbkWnuawZKTnGSWSu2W9Hd53Ms2sNyVmw3EgglvlZIMx3mKCy2iKt9e30E4tkxu5daGLzMMzo/ce21K2ZsPRQ9XvG8jH4odC22Hy3ZETLkZEnylHkxXQTEprHWZhpSm3lFMeaQ4FxHXI8WUCQ0tqr6ZMx9e+6zNMZ4aszJzJpTgNE3AtqEDjkI5OzIoy+VYTy1T5E5Eyli658kyz55nV2IjfkfhEeyYaeckrsoRxedLXKt54IfMdxhw0A6UB551O1qMVCOOh7OZvM5sp1wjaUHE6lpNbyERuqagVSU22cV1YyUTytxQVTxJMI0XzFFRtQOFSRfi4ZMWbdfN2+DWaLwk3MeRYwkGKmMexGm9PiCPHrkHtsyug9jwGxGQ0o9UWOWnTENCxZkqB5hSpnQnEafytJ+SL7kyV5CTZWtmkCR2hw1YzKMT5+ZiekypD2dsyyjktLzQk2HM2IwgBqxjTN7qbUNNNjpso4/KkZxSo43F1xLh96OKeWq8CUjkZHfrGd00VmZOSTrFfyU2Wqx0FvB0Yt96M52HncltZ2NpyqbAcvDLfic311LWTzJeNTcbzwpabuKJxoyYbbl5aTuajp4Qlm2SVOW4528t8Feti0mmjP7jrra6a4kJoKLkQCDsdJFdVGy1zqwnFXE4kxr8pVLmUUJEvmbakrkW7UvIfC6bTyxgukcrKVwoXC/KiT9ugmZkiUZCyYm3Hh2TNL7aheTdyizA7mV2pI0jM50oEZt3UFBGQ7PgyM5ZaDjRXZj2gP2ckutxHD0dOBnqq6pKLtaaApEXFKh80eyv8AkUo2wjBEk2p5neYeYkZeeiIVvOTLSYH2eZii3lzHNfKxVI11NkO3xIpln0P80QP0TvZfcjuNuUMYlKbhetbNZp5MC2gAOXzBB5yewcaNLk/sbJbIjKybs02aoNrJJKl3IOTprbT1bCPhhN8vrSomRotuxUjyMnLAc5xbEkNKkjx+1Gk8XReXlNJm9wP6UpEUnMpB1AXaa67dym3c9quVUV027vsOLntdfNPPFFz2FXPFNfsKueKvYc88cVdTqc89TkTbxz154BYBu1ZlxuNFnk8gJykNVreGT85ryQ5Z7luU5MPqCwsEbMhOekn1qVXyocHjdxgRgQaDYVTJeqok0vbrXVGvmK1t2JWNONuXzDmmS8iMwMm8dWy+liBppzAekfwvkNJjzbLNfcmFWXEsjEpbamM96FDF10GUlq48RUzrzURCh9jSamL1dFtWRtcNnj2zhmrX3l1HuVmuDGpnwGoQc+Fp/Pu7shrVTUdWGelXXeiSQiJXGFNNxVc0fuRDR3e10ix7O+sOBHTkqzZM1nOC90OjkS00t9rcgb+U+R3pRzSOID7n52eb9HC8kSGYBjB2Z+44t5QIozmJT8rqCO1InSaeLF6sol5WrlF4wwzZZJvE7iIzV8xI5K03iJguw4pPnuaKB28aUajNetPH6s7ZsljlbgyIqNlyxis2XsGasn5n5v2bBu4WJ3DVm1d5rotGKyhWu9RTTcqLWKqubVIVSAAABrRml2HWWXg0Tv5rXUNlxrRml2HWWXg0Tv5rXUAwFgjj5Aalg/hqoqMIRAfUD+KePB08eOxqzDRw6cNRE0L5o2bNX0W5fMmTN+5Xev371dd29drruXK6q6ueedrPi347/MLC/5LWP9RDGWAnYJYVeCVjj5nWaNtQGF/i347/MLC/5LWP8AUQfFvx3+YWF/yWsf6iGaAAYX+Lfjv8wsL/ktY/1EOZnn7mRYGYeaktZv7InOlnUB4u/n4J8LsevbGNGsfxM3LfKJH7RkSREWwjLK2tXmzZKKj9TotTmMT5kUy4FxNfziIK13i71nAA5xZg1+wo48uZswDx/bTDxcjWY9JctRCl3Y7jlKqQmYZkbIm02jj0MM5KUmlw71q3WcpVFe8ouIgsOY3aruKjh4NmLh7jokQEvrGhIqL7f7q6zpKcl+6favaPdHW8nZKe3+0+2XvafbvafbPavbbvtfsvYe2V9T2XMy7nbrynitVH0s0sVKAT7dOKeRbHliUJLw3yYjiGUedlm09ZcimfMcXJknHVEplW+3mpVJ0Q2GRkfjE54xXna324mWZMQVRzSAxXYuJac8kZqM54qUgrsgaJ5Y4oMvHiGcCorUXC45vVZB29Y8ybN0ky6Xbqs55qk+SVt+Kr1djuR0ZERmYQImfYkW822a3G4ktNnMhBbLPQ0yyloZb2V8BLXaL/Ya8PGlYh/6Q+wG8Xxb8d/mFhf8lrH+og+Lfjv8wsL/AJLWP9RDNAAML/Fvx3+YWF/yWsf6iD4t+O/zCwv+S1j/AFEM0AA02yCxyQqITk+1jfjzjQano6z1dKiO7IEes1MYiQ/FixylN5zvQwUaKufvNRonzlp0uFNTEs+rLKSjm0hJKXlI8Vo5hTru+5SsH8XVInLmXh67nbkMaO3HCqmJHSOCMFJDiPX750+YT4pvm1P39mLl86bLKChKqu6EZb4oLKxdjtpR45po6nwASn1TJiaipOf6Ojp5JJSErZ9lqmpaWmFLBBOTU4jdYhYkQIEStu0WJkiZa1aLlSpe1bsF7Fui1at0W6KaeKsCWmrj+1bDvGl5f/6YxxUsBPCS9d7FmaVs33nJj1WlFi5t4wQTjQ4mU2k+trOaPykKKc/Kll/NiRba0pVXnMoHJwLKLdp5aZChoLLJIqNwy5LarUSTfByhg/lpkXEklQtkTnWgKbNcEc32kw+YOxRbsWq9l8p682nQx5dnA/JMuZA8Sq5GQ4GYhKNlpxjYx0jV10rL9TXsznAjrjUTmDUsAEinHrUlOfp1SJtzRyWj6aiFvGrJXEVyQtFONChCEQK8LZKprIodRxMLuvIGepHSpSNKrPt2nM6leSHSyVlolWugtSL48caQ5nw+Pa8YW5eOSI3Tj1KOdjdc8L3YJlGC2oWamKKG0ZQdiY9owX4oaLgyZkJfmKQkSTVNkJSyUeijbx7j7EDl6SUiE1A4ZR4/NqsaH6gAA0JfuCTbkyjD9JeTvtLDQxij2T41dTXMNWvixMTblPHRUx5XCl47ac9u4yrXWxWNLdy3bsumszRVUj0XytVXCtT4+EsOcpY+VYOZ8lZyGpCx2xpvXqoxZDHhdShibJNIt5FPsuKULLmcUqb3W0JubjMZincOOpBjeBMekyUJQQ2e+XEWJt5HVo7cdJgABqVn3+zglmr1e5KyP8zryG2o1Kz77BLNXwSsjvM68gGP8O8eYBP4jYsnj0HQ+dOnccoQNnDhuM2WYNGzRiMmxeMGTJi8iV3b5i/drru3r12uu5duV1V11VVVc887G/Fvx3+YWF/yWsf6iHksMOw8xQ8GqCvNc1hsqAwv8W/Hf5hYX/Jax/qIPi347/MLC/5LWP8AUQzQADC/xb8d/mEhfn/5rWN/WhjmUSvuYuPstMypZzi2WOZJWir8edw9GuF+PlV9jRNHEYIVvhDj1kvyQUawhrjlVS7RKJV57FYwTI7ImZB4X3CWeLmKLZmq/wBaYAIvwVBkNY57bzcTwLFzEh+NW7qyZfCOyY7bCS1G8VvXssn/AO6z9aekFSto2qqNyjgwqrBzgwqqxvms6pHDRu5cvV+cyP2N5Fx0ydmJuPEWFCjqxKzVwUxdhZTebLfTpb5hu5W04QFna55QbyHKzIUXetNo5k29DTdLNR0xwRrLIjXJKdBu6XVjyvngl27Fy+K0ZHpZyCJt5eRBMtMf7oVgjCk1uMu8tmWq+WWGRZkPyS+XBJMbxNVrFUJKeMXtZmtddc0nIrILxy/+HEYYKQ4qk4yy3QRvUcHkNRLlwpm8JuzGxEccOuXK9/4vTjAsszTHOPzldMIwHK+Mz0hJ4zQvWGHDzyPJL6ycyvR5ZZrrlxaZcZupOsH4mPx6UeFiRq1h2IyEsoNrzm1RDRXIa1tIjiSEteRVHaLjuWUEhaTyiolny9cbztxXYOJ56zfKGrNfH9lav2a6Kv7tPI8fkjJNWw0rBuOcCxdk8joFrKbGycJ2lWcMSMj8XGbGsU4yTA08i+SyabyojKF1CQnrKDxi9rRY1kGKEmQlJuX3Waez5T0NnIJs6byJs6/f7Wb40vHXzbzuA3j+Lfjv8wsL/ktY/wBRB8W/Hf5hYX/Jax/qIZoABN3YFj7AiZgZm2pJsIRCnqKfiLkkeIHyMaswodInSkNPMwVOEzRdFt3yxotft27xcxZuUXbN2ii5brprppq493ifjxAB3FnGk4cg2HjZw3AENmTRozGbKvmTJm/HTcu3zBi/dRK7t6/eu113Lt25VVcuXKqq66qqqueefR7EO1/5z+B3k15lXsPfYi9ihjD4PMLebZtAPvvi347/ADCwv+S1j/UQfFvx3+YWF/yWsf6iGaAAYX+Lfjv8wsL/AJLWP9RD8c43478cc88QJDHPPHHPPHHEWsbq89T+5x1UPjjq8/ucdXnjj+Hnjj9kZpAByVN77mJjzKvMSWM5NmLlSXBzIL0uqkeYY4/VX2NEEaRqjW6UWPmI+H+i2EJedSknNAokcPCxGabHCecftpecFt1ukquGazFOIFhCHcd9uDiimCIwYkQRs3dWMT0ozJjpsJDTbhO5eyzmnk0c62oxUpYMKahco4MKisapvqaqbquHFE2aN3bl6uzololduxfvitIk9LOawFSwAAAaAtTXrFV7Am7gBNh34YYzVEJ1IrhW7KTcZCmYvrcjrEnN1zNyzYWnEaabvj5znUVeZjkIrJlRRHY10Z1J1wmeLF7Jbf4AEpmvgzluxzEPzG3s1ozXMymrBiXjZO82yRiIpOWK8m4taDocrsjZbeUJNPJ2PHo05iYys5Fc2XfDWyDts5YNPGTK1GLuSjkaRGPMAZAxlJOIr/xrkxkTLlo4ZuT2LkS1JJyTcuF897KYTktHmGRmjK7hi2RMdcWpPa+Q0RKjYfqcQXMTVpm3E2DYaiZDkSGVxUW1N2tYvcuwACE2H2v2YnPBeMrmnSSXUhvqL9o2Rex4vTIDHJ8yPIjHlAxlM1o3acjt1NWm6mQ6+11hTy3n05kAgRWrEbKKZcjK40iJqyY972wcb6v0dlL0an3DK9l7IDHyg2HZDrjZMx3WkF3kj5+KctHFONr522/D9xJsx0SlS+m3XPbsH63tQk1X6EFn1KXFtPqsACZ8L4R5ExZagiJ1XNVVXMUMZDiBXFUfNSK1uPMhXo3mAnXESLY5yVyTKza4G9MEbNJHulrLgQmhAMOLknm2uza5DdC6lWn6iyJTAAAAAAEhVCPWC/8AdVJJZ9sdoPUun6uYEvkLDtbSK5LJK9cyxyVt3LxS0skjtBa7co/aV3LNNFddH7Wrnnj9gUS+Lfjv8wsL/ktY/wBRDRxB7djKnitIB9LPJUVLAYX+Lfjv8wsL/ktY/wBRB8W/Hf5hYX/Jax/qIZoABhf4t+O/zCwv+S1j/UQlHtt1bOrPODWlibjgQgPGRiSM9iKvklPVMbIht+I8Ys68UV0yPoxa7bT0FQWHE+nbUknVk8deTORCbUaawiKJ9TtujrTfuIADmFX9DmuzWhrOzzcMRxNZkeck/BfK+sxkVNNCa9pQtH/gCkLi6YZvNacUbMZWeOL5kra5YKChLBlMuUEXAuOCu1yaudCONvY7QH/MtFn0GQhgXZ32tbYX4DmWXmEf4z1jb2O0B/zLRZ9BkIBmkAABGrWLDUPvNnZoLrwimNnYuX9o+x+xeWXKxWuuqt6yXynf1svZuqKolmjdy1Yt8cUWbdd7mi1Rx7Gjimn9gUt+Lfjv8wsL/ktY/wBRDRvVB8nOZnjTNkvpVP8AFTAGF/i347/MLC/5LWP9RCSjegqEK97UvtyqG4qqb1jUpjgt2EGqPGjyjWVk3mJlQQNK9pL5SOSNtTMkSRMmYP0WODd4oULF7l2qzYtUUXTEgW52/OZfFA40emflkAot8W/Hf5hYX/Jax/qIc+uxbQFXtIzBYi7LLxZuNWC8BNewks6L8fmm3E+ZZufLn5KK8hvZ0uDrEXaMfo9mmw32Y1KFBKkpaoKtdwKBdJa/DtqM3OnIAHPLLevTDbX2q6m2DiTArJiYia2gxuWcTlTyVxWkR7clsRM0Ltu++ZGXbqk9HXzbM13jJMmrrRhLSKr9ywiJ6YT9gVo6GhLTZR8p+pvxpbA9EHM8VLARcl3bQ4oEkSK+ZngeMoohObci0rH+KE2S8nrrEzyfpJVlVMgqzNbWwTckEkLS1EdqR1pHdBown5FX30nQArpUsLDHTHEc+C238THDM94MWTUmJHkUcsp3slttmfeNrdc7mkJUuXIeZ8RsGZJsbZVFTFVKcFSu2iRGKOGQiMwiqtNLbpRe4VCBmuyldZFHVU9qXywKxMowWy4917s89cytjDJKTsySCpIdnJbNpOhnMO1kexm3kA3UrHpIrYEiHEo7evOaXVGdMnSHvpRFlIbkXISNK1S7FG1C9r7yTbKmyJejJSg91S7DGzjKDNxhx8+3y/WRHEgxjkiwpdiY2x3dJTfiV/uaOX4gNWW7zqLKKNF0mN+pwNq02btBpOXa3MiBQWBcm/humvM6HveR72PiiTSw4g98Xvl69fCF79seIgnr3w9aOsCT70+tnwre9TrT1zcvu3rD1965lOunWdO+FnLlo3sIsa3jkQ5UZNWyLfccYMkgXcjyTY0YhJzzHKLOh9mrMoyksEFdLiyKEV2vpFU5Mkg0huOtlssqtLpBrulUJkW6qaUQg42zr9k7LuYdjuUeEOPDkzxnxtTPF7bUsg0tlIpNHjjGfHyHHYyEpdnFOiU7IJ6O1prk0s+8m+hE7LqRlJrvpZaEXqD1pjZs5/X8zsfMrWm74lwTy0135KzobQa1i7DC/N7JmBpvuOiakmkpDa7vR4deLmeDTQXU3lK+0a5JqY8koTEUnAmra5GEjkbNbLWw+MqZoTXE8IveScjcZG0hvP3+xPHuPbXxvn+3kWwcmV6eDjWa0VEWXIzjiSB3Q1Dd2QXFfRn+YecRpzYZ7OI2ZISHS9EQwolEXUXNrMbIpCxczMieWWCl4tZMsmCGzNsXOrHbIp1SyzndGajJbdYy4tsyVVCI8bJKbT+YjprtosgNc/F6alEkF7R+qtl8u+pxuZHZmGqdLK6/mrkz11iXCzFFBkt2YnyBF+EcHFlaeMHTEl4rutYeKtIc0NJ2Qbji2VYxkwirKfB0rtxjwOhXEOPGK3HrU7JCehqyntv1ClqYejqjTKi2z8XdZuDTxl6Ck2Co9jjEtitxQSDftskNGRnbIUtZSJ2IWPsvGyi1W0kBuokLNqLq2MiXGzQ83CtvpwLqDYjEN4ZRzmmgg7MiK8ecWEudYlw8VCqFkU8V2bjsSP5YcpBkoUqPxlYux4Yhl8NKb3gxI2ciEYO25Dl/HpnqkgK5OPST1ovEXMvNz9zlzemWSnqsM7A7HaO8lyrJhyOZifb3l/ItYxnZBmzNrfMPCGY/ipQQsf8AIZWfb9cbNTTTsdvvsRItY7IR3DHXFL4cSk53CnsfTKc9Sd5YmzKF8sXErWNkhxlk+bckFZvzYixCc804ovJaY7YYDqqazYvY2y4Tyij9NONixLDJjV1y5jpwnudTczCOvKttrie4m1smhYr5V4hSC5nNhW2MXJdZ8pwvBUfvNhzg+XJiWRjqQcbI7KRIynzHNjH3GmcGOpsR8x6WQElZhVEjuGW/F52PiN9hr6ojvgygMYPP4n5FZcSns7zWjaTGGksSC2Ni1gg9G3HLjlywsyHDjnlGvJlRUU88zGZGapGy09XcqoC43pbU29PDra7YoimOr0ePOX268Ll9g2DE5YPxwyRjLOWZMiHuowY/mZkXitidHMnu1pH5BjF0oM4YzrWRd1UNMiDFpFlpHMxdICbN6cbTzi3knadTIMN0wimkd78G6XLzRoBLPSH2orXb4KcUfR+wKmCWekPtRWu3wU4o+j9gVMAAAAGgG2LtWWyzwAMyPR1kYbfxN8lcafzfs36OJo1A2xdqy2WeABmR6OsjDb+JvkrjT+b9m/RxNAYUzKy6YuFEKnJpfTMkqSrXDhRGq3Y1hxJbC7KD4Xljk0cvp7QSHk72G2zt1AbCS5Hwv9cnWlcFGi1HCfK8nThQunG/2yzmBEkSRdBUxHeHG8mJkTLuM8OxuqMUojqfutWyufrSj6LnSf68LqDYtMu0ovRGWHEokTCirlED3SaSEJcPUWE0xOnJZZyFn/ZrHjRx4iSEJrZ+vGHz0kSW258mp3QSyqsisvkdxMSLjSK6GfjTk+fcLuirH5oy1dWGtdarYJE0TJVtLZxfNmKklPE6iC5ILDxHhvB+Zm8gM6VME93+tOMU9rNRyqL1aBLHWTM0IfmfFu0x3srMaMFJ7MxlRQ9CkFprrPRyyTqqsQu4KVFvlFIqdquh0yZFzy0MY4aeM4P1Nciu02R73uuqe0CaWfcRj3yupDaBHreUWVhATbvtSkvk75v3SrFPayNozds+3mKLRa99Xkpkgx8WY/QZIkFKdawhuGYIMhQkUZxFIUFa06sgZfZkKs1QNWFtdbxOhvpjpfKSfcxq0evqJJvl1E0lJS0o2SyUb1r21EDhzXTlOcKJ6sp0tZipUhKZNCSzS2r1t6M3q15Dc94ikkeKjp+6UbjYVTnJYnbvGq7div3OXMXuKLFzGG01WQZRxyxdbLAcjadatN2eGuxXiK0iuBJULEjorTyliWdnOuMs2UN3izlRkKGGC9JRUFFGuHSttjtlWcFFy4QLc3agrIJgMrt0OS3iwMHvSt2Ein4hLL0hZUsHcnNV7F/GqPcjT6nrKw1tvAk/8jqseLLUKFcp8+qkY0mHKYamD303Fa9fUbRoryWQutVJCxd9vP8Au72sqFzlH97z38TNf9xWJl6Ue1H65fBBhH6FJg+uM5DbaDBe/Y6MTHKj26zdtey6S+5V7H2yiqj2XsfiUcdXqey6vU6vHV6nU6vH7o1jwltba8PcRMcMWbmvPHCQq4Ah9jxTW+aNiN1q0OupmohVH5XaW3ViC4uUPhR9ze6OEzleV+Sns/aeuBn2PttQXtAS0+MZto72Fjl+cwufqTh8YzbR3sLHL85hc/UnAUmOvRnprqQmKoupup71dCYtLTZaJ5aTijlciO2q0625FRAQzBm2prKe3biwj0rxtNLGbCNyrpPClWW65kfb9E9u/aqNk/gJZYeYx8Dm2+6VZCzDdOvMrI+R+HkP4tOKFZtjV3Y+z9GmwBSfcqtKV1JRvIt5CYrTR8X40W3CYcbKvuc2fIJ7+bdKNw3Sb/MXjvvGskDM08N9i+9zJnVlno15zgm/kdhjxgxlMnnMvptOXonfDYRbUHPkvcNtJ+X0s1cyZvkKbBm3fTKGo4HKcWqrVh2y41ildN6kP6JcW/JlHP8AIRo/R9PHux4SLfkyjn+QjR+j6ePdgAlpqL7HeevGQ7QvT6yCFSxzi6/Jl2CM+P8AJNBgTBqGZsjErsY2WXESRXhm5XC6+sGjWc07mFgsbj3jGOSuEi2lK1w2mFTHvvUOupYraUvaSHur3FYDo6AS0+MZto72Fjl+cwufqTj61ZyT26FUdVMp2r/HO4oF009fI2+Nkd9S5uHLJW7cLUcJ1vDRNuH+ar9NFPBK2okKzXPPtFJ0rVc4v2w++ZXboclvFgYPelbsJFPx/IXxI2cbh1Lbs1H6335L0nZSv2WG5DciQK4F5asNd2MptSCsHDUGuZDtllUg2GIxjK68KktTtIxyuPa1FecxKm+YNq/Cn/Sd+MZto72Fjl+cwufqTgKTIrzaDkVXSgt50t1cXWOqFUR6oiQspyirtBZPpZNdIJToTChi6dQFE+hqKctkCarYKGDqMoEFUrbukDpYxdmxsJ7JbTz4xJzegBm8OKb7o1yRzXxvz4xZycZjHTcCM1HjE55urpbGzLZQndZlmPmw7rBGNVSRmuTg2IEr3DcWlB2tAmQdhR/psjkkEohX0kiUYVFtSsLiJlNtrycdmoFd2Z4oN2FCxXPZVvxzLRq/cjeTpYuXMBc2LV248MbrxI4aZdzkpwYUjLqMGo7IKN2ogWbkZXEs1Wtlg7IAAAH16upWEVJU1g1ReuFklOOqRm2Xporv12CBa6avUWKbly1bqvVW7VVNum5dt0c1808VXKKeeauJSsPbU33ZAzIy1c+EWbUT4hPRjNeU72TL1LYguZkMuKXgTIH0mTnxH8KZfS3kKjskkRVCKq8FcpCynzHLb5VHpIpdqslsutxoVPn7/uFen8k3H/8ASc4Ix4dyrHUJ/c9GMslyuqE0xjIGtSJCqnQaq5qvr6i5IZQmq2GShEbfFZxdd8gupbRGMyWslWDa67Xg4kNsoBBQWlYgSvhcAmcKKBQqfIGi54ieL2DhI6Tv2jJQ4UM2qbxY0VM2aq7JguYs10XbF+1XXau2q6bluqqirjnn5A5w8PcU2TMD6buJ+ymOGfPTixl1a63URhxPkEgpklsBHXTTAkdnZOzSwUl+IV8kckVRk5pJDGfMpWubz8QE1AaCZdPNok5LVlcw/PEeY9ZPvqe0mK0LCPIDHjErECBbdWT+xSYFbNOLsdYUcbClWQ7Ug4uwkZSCt5+WJObTXT0qSsv35nWxHe53CwSvBxQfRHH0u3lsOpwYQsT4z7+SKni7QmuXh/pUIIc+GFioml8M+tnuB+OGPCabZUOFmpaqctpabR80ZJ1t+2l0Jd0pftLN43cvErHOZrqRG3nJfwEj/PputnJli2tM+Mk0wyyckrCXLTUkucVJ9vZn5Iy+oMWQOvqBIUqMBk2Mfm/ckBxIiu82Qkyku1J66WtSw5+uWyjQxSwSyB2DN6OLTRi/KHGKLda7eaccNB5O2nJaGyx9p5fzSxlAgZLPRefzbdjiiBXb6/HLZMOK6tLsR1kXEzUC+3bthRIWw6DgHH7DyLIeRa9r5gB6wTjhmHFbCxSyzPQ5AmdmRLxZsOvJ7RJl0uwNce9CEpYv5g3Z8mLHuAW8wWk11J8ppVUjxmTLIK+mKB487lY4n3Z1TnnVexgXkRwu2OnUjsjInI1gx4UiiQZFl1gRwwGjLDiSEqDmrLUmQlAKzI7dgRUsLUNNpwpbEvN4o2mOjNpOcq/eQDhqkKUgAAJaZ9dllpy8POTv0eeawqWJaZ9dllpy8POTv0eeawqWAAAAAAAAJZ6d+w+dnhybMv0iOToqYJZ6d+w+dnhybMv0iOToCpgAACWcJduH2DeBHrc85mwMVMEs4S7cPsG8CPW55zNgYqYAAA0SzQyvljHVz4sRvB8CtWfpRypl95RS2EB7TaZghsoHDFgiVp8XF5SdxOJJjMGaqm5E6ulEEqhtFaTCmoE6rqoWs03OqG9o+oSXAgr/AFz6xLaQtdZVc6gLPWlSJqXWleTva+uCIp+47173ArkPbrPu1NNe1HCvttv2+zb9nT1Zv85I7Pin+39YsXnep+7719gzSUvZf8n75sd2X7Lq/wBz2z2rq/3fYjh33vZzZq4I7SmNk9BCM7cCMkJ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qHDVp+LT5pRTBgtHVdChbRDCveLpt8LFgICy7m1tbwdcmPsj5qRLg1ImMc35Aw7j4+OMVVic0eV8cVqaluw1W27VpWlk2casyM5PdB0mjqpxEbcZrHF66QqLId2yrXb6LsTk3mvlOu5f84Ba+Y1hVyTaz4iQ50n+bsmFV3UQXBbKeawrIUdNupnRqeTpCkeSX2aQVdRJICctNRJR0IsWU1FdrtHb3CcFRn0/GNF7PcUhSW82pHbAZ6UZXHa+H04khpM9rohKn2ZxYcTmXzieioiUUo/bmVBTOlSlin9tdvUcfsj0CeoEFYgSVUo6UU0xTKFlBNUk8zZOEFAgcs0GSZ0kcLV3C5sobL3Ld8sZsXLlm/ZuUXbVddFdNXPNdnVOmZkhalNwsRZxY7tyJ5XgvH9eS0iYIcuPJRxjyVajtYhZdsPiGj76KW3SgnEBQ4NoT3YK+pOE61FGpPL23Qu3Lp/rdtLH2cU0S7LmPWHGBjZjN7E4WY8SqWfmRMnJjrcMWQIgX2UhGiMFMgk0XQy7j1ydepKq6btJVLlvIMVplm0qvpJUbpylILhbcAHPHnDvjQNW+cxHHHPCGl1KxumFspb+x8yuiQoouGwUR+ebSI9mhLEbnK7qmaWY+dJY2YVV6N1ddVTDVcbEM8RpaNq1y/cDocAYKx3ydx6y1jhNlzGmY2BNcdKnNFu05mA4iK4XInarNsxcRl8nZucKjZcRS3dt9cW24yKUvplyr2lRTSt7jm3xnUAAAAAAAAAAAAAAAAAActO0D7lUwnzmW3pM8DLaviRkg7VBSci6sIBcy74cfzmUb3us8ed0bqKiXNNtQVLtukvyrx0ut5LT6zJ1ZPst0Kd2um71LAA5YtR+jiM43x2WcfdkmEMLOedIOeKghNjIFpr6u4GNkNEi/eNLDMdiYcTlRtqCY4mmY69MNebzlZjVcJdGQWg4lImdvOipRMVT6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv9Zw6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv8AWcOhP1W9xZFP353+s4qUACWvQn6re4sin787/WcOhP1W9xZFP353+s4qUACWvQn6re4sin787/WcOhP1W9xZFP353+s4qUACWvQn6re4sin787/WcOhP1W9xZFP353+s4qUACWvQn6re4sin787/AFnDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nGm+z3A3ELELU1s4cONcEs+I1p44jv5Fcyg2a1qu+sJaeWqPEiZrhVVlG3xaLm7ld+j2qi3X7Orn2VXNP7A6EgAcpG33FFIkBM01ZmSjEswzzixialupmZZRxBCnKSbKKDFeSEMMBrJM1N67CjwaEtVokRvNqo60/k2OTRtfW22botqRUy1E5eKGfO4vMzTBKOc+LaTrkxbn3Lhwx29luSn5lBcyWz0P4/4YqrLbhi8hKTwuz7Iy8x3nLLiNq1DeQ4mLIppbsF1M0fcVaSRt1UXutkAHMlBDqZDD3vbuMdZccV6L35sOjTBG3iUWcqEuWC02I0Q4VyS3pgWWCp+4OERZtRyc93WVuxWqlbnJxMUCBb242VvWqPIYS7R4o1v6/I4wjykZErNTYHifHi5CbbxJQImkl6PjJdzsKpTLx+t45HW22zqFKTKkVL6xqfvoR1iwQbdowrX3Jyikk73Tc6nAAc56g4Zzdu1DRY6smWm02FP7lwjz8X5bY7H65ctVmvVXaeP6grtVJqVlZdULltv3THCSZvGFc/7cdKGbtq/zYrtU05YymaLbkDePhUwnkkFl9oPbW7ns0XWgnebvBNbbbkeMIIy4kG+bFyzf4LKSWdNE7/Nm9au8Wr1ftdyivqVcXYABLXoT9VvcWRT9+d/rOHQn6re4sin787/AFnFSgAS16E/Vb3FkU/fnf6zh0J+q3uLIp+/O/1nFSgAS16E/Vb3FkU/fnf6zh0J+q3uLIp+/O/1nFSgAS16E/Vb3FkU/fnf6zh0J+q3uLIp+/O/1nFSgAS16E/Vb3FkU/fnf6zh0J+q3uLIp+/O/wBZxUoAEtehP1W9xZFP353+s4dCfqt7iyKfvzv9ZxUoAEtehP1W9xZFP353+s4dCfqt7iyKfvzv9ZxUoAEtehP1W9xZFP353+s4dCfqt7iyKfvzv9ZxUoAEtehP1W9xZFP353+s4dCfqt7iyKfvzv8AWcVKABzq7FtOGMSRiXJqFgtr0it55WSOTsRnEB42sHkRtxqsPD20irzE7lt0uvhET0aLmzQtu1PsGyazU4HYntpq2EJXvr1BK7OLXF9x0Y2QrW35J2CyHeybkYnUTUuIfjs0vMmBkFSs82b/AAXVXBR1mkmTaSZ0vbMlDHHMZopizdMJa60l4lVzXc7Rx+q/c9qs3rv+9Wrlz9n9z9pRzV+z/wBADiYhr7mywf2aasMIprLGnLjjlU68WYvNn5oYntjibrvUC7YtEEm7JcWLCkVRV+0TJUWbdR9nq0fuY/XYKVLDiVSxOyS5z7p+0GIeOCLNGLux/EqFJzpaDqpfOOmWLPWllRbsiR45quS7gjlyJdk+2XM03gxF0uVcFiw6m5TbWyb5U01sOBwpLGumrVqdJVv2vUZrnp/vsSIau/s/u883mkRvc8/0+z6v9IqMAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/wBZw6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv9Zw6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv9Zw6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv9Zxo5sj1GQ1HeH7ie2vnFZsp84RBNWN+TFEdsqs9cWZpRMcJYR5BXI2I2XIZcJE4sKTaocRptJVJC5WuOIsmontZjhR9z3Oi0AHHxuP264r5eYQs6I8Z6JTkx2u7JvEI3MJauIJJaZbF1PbGRUVOO6RnxVdraRUhlPFUdlpusNDZ1R86tK6kuVqZGxdQyfXK96/ZdjRjJGe2lWy02MRnL6/gnkNi1H0cp+QkXyXlMz0LHSfojc61RUhTMUxgdrZXkaNn2xFulXT327azLNby+nqHJiym277iXS3WwADmM1vwvrimLI/Ih3678VJvJRimYwOGFUzYrKk3Zgu2P5DV5YWOeHVE0IR9k473HafTZQaWw3nUsys26yqVUdsW0tJrrSldNWnH5bCXaPFGt/X5HGEeUjIlZqbA8T48XITbeJKBE0kvR8ZLudhVKZeP1vHI6222dQpSZUipfWNT99COsWCDbtGFa+5OUUkne6bnU4ADl9kxyTzifnbgpt5zXiBWR27JWuNSwszcuwW0HLIbRxDfKrLCfkEz3YtNVNsvKQrTCsLaotR+8XgmKDkoSjJK0Yu2SpG/VbVvVWpJaG2bb9ryyExPsPd34oa1Y9yrfkg5OmGM5WpEUoSXlEwGxGLKh6JXA8CrdUH0rtss2DD2eq82ERbayWk02UI0rWVNYJ1W+lgAHKprVy/gjTFjk4dYmYBeVGLNWOErZA8Y7t8jErzfjgzUh96Se7pSjh4wCZjpon0yRXWpkXhYbbmbHN8mutFbK2rC8WRUSmz1u0HYuOsr5v/AHP0ZczehV/up/RNtamXMN6Yut10uRnSK9G+xsp5FOS5CieqtZXby5w9E9oO91UJBdNPF12l2NxONNTiy8yjdv2O6MAHEi8I/wBAE/2Y6gzE/DzKjOue5ZfUbtp3Ytn8ntnzDqhNqq7lR77ukDKFZkCTVtqREkRgl0GnHZIugoYMuZeRyJNv3rSZWbdqN0qSDqN1vSq+XfJchYlRq6X2/XGsO54OVRuujg+vORfPXlJYVjnBZwly/Bk+eMXzN7ixYs2vbLlXsLdFPUp4o0ACWvQn6re4sin787/WcOhP1W9xZFP353+s4qUACWvQn6re4sin787/AFnDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nHM5lD9zEPjYFn073M1mdHeu/X1FNKfG7AJohS69ZsnO43zF8w9pQTmVcXDZNqpzvcZhWb7ZWHw70s0UZyCz3MTjVX4VlHk53WgA5FUrQHrCgjNLFHCtPg1QkOKZgwezuX5mWJIe7nU5Akd0syV8DCrPdx1zN0+2LbPW2zypqNSHzGiayE4hdPHr1pP5vn1C6a0Snn7kxc+KGRsc5T4ImUbLmHGK/kpySHhPkGpJDbfzujy4brsPhkMOU7dTdYrlU1duH1JPa3LwtxsZa5gumqVxyOxXs8cXuoyVf8Aym5fCqj933Nr32BmOp/B7dOuABfq/wBPU6gqWAlQm6XdVamnEFK3hJGxS2oEip6gqpWnqnqJag3Yt36S58gZclBgkds8XOLZooYoovFr9NyzdppuUVccfN6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv9Zw6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv9Zw6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv8AWcOhP1W9xZFP353+s4qUACWvQn6re4sin787/WcOhP1W9xZFP353+s4qUACWvQn6re4sin787/WcOhP1W9xZFP353+s4qUACYBDS7q4SzxJTT8M4sKn042WPEjNu87fbC5speoMFr9HsnLVT7Ozet0XKfZU1U+yp46vHPH7A5smjjTrBwzyHzdincM0puit0PTLeZJ4xlyJKTTnkyoYyIg+bF669my3G3cxzk1Pj+qa2YqmHCiOtmXkuw/V2u1YOFSy5SWvmae4wAHNdidkRiBrq11ZWZsRbhJOeK0YPKZV2uHI3mmSprf2QmabytFUyOIVdSaz54XnRI7GOTMfJpqOz2fePqCjy1U+88/cRpJ5KnDuqeH8aZEaUsjIxyXzDcDNWI13Cu6iznMotZiN1oNbEXPh/u17SFEdlGWEq5boIQYuorxU4edV1eOKtPEoI92QLjl9yOMoiU9foAOMOcMa8B8ZtmWfTs23seX2jCGVD9Y894q5btyaczGJC5ng6wkxsyhC0mncbX412oxHu1nYhlbjMMyHbqvOpFVSaWjqROmltoqhnqDMOcccrMG9uqHrnw2mOAEHJaG70GwlkBkjL2S62t5mmGnH7iWmg4UZhZTL668osjBIezrUWg33Ucul+XITV76udIlLyIbQEfrCABzdkN4TJb2JbAhSE4okt17WCsfMGJkbAB2Q5Kxd7tOZyttFYKsvyjUWS0hLR8emmuUGXGuS5ZeJJtHWbZL3U5coWD9olb/TIGSLW15bjZJnXOHhWi2HssMB8cGG0sg0VjvVxwYXnWGn1Il18RKsLjfTXKotByrdt4WFdhEXBbrKrqbSVS7a3fciimJh/pKABzF6kJJom/dNu3npLZr7ZTJmmOdcrxjMpJLXVGO7nBHyPDTwjpCe51luAuRdLWT3rdYx5yN9IdqQhuW23lFLMqyMn3jPFniTuLsVq+V33NERwIixuqz9zd14zLblXIvDM0fesWSha5TM3ZulYvFqkolyyOtIzjkCK7DkUWeabZo2qWnAQTi6ddIOPrbds96wAOIh0tv7n9mdtM6J8ZcPcw8yMm5TcbNaC3hUcyQ2jsR1xgUW3CkEHmsZNqT9lJSaMNtZgJhk8tmVN32TSc6+E2wZa11QbV447EnphkPUvrql54rUjSfifG7tfjnrJmXG4lM26755TNk04ml2Lhi/bXilN+qySIlStF7ktZru27FFy7Rxcqr55osACWvQn6re4sin787/WcOhP1W9xZFP353+s4qUACWvQn6re4sin787/AFnDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/wBZw6E/Vb3FkU/fnf6zipQAOETIL7l9fewLPmQX6UbDC136/Y8OEI4ipsNopW9JymNHaly/S5pNstS6tnElnF5Ec19drbSy/HGUX0VnF2ddNRUpXODtRndVy6BdYEKZU4E4TpUEqDyiWZoB2Ar0yLD6fbsUJFkd0sH4ndLNeCk7EFSbnvYW2wZWDRhFsR4nM1BI3zRuq2i9Q+fpNdcwlpkN+2246yKP7zFzZ0Y6n/JrGBZfq/0e6+p/SA5c5b+5PXTh5k9GOUuF1aRmhj8zH6mrEp4YTudR21KbjjA7euJ75bLDkOzea8fvRfqbagp32hW4+YwNoSuQRr3Jt3nqLlBjqGK6V9VRwqWN28KYwt2zReyYt2zVD2JmrdF+3TdpoMlDTjsmSpiimrim8WM2rV+xc4qtXrdFymqniqIAJa9Cfqt7iyKfvzv9Zw6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv9Zw6E/Vb3FkU/fnf6zipQAJa9Cfqt7iyKfvzv9Zw6E/Vb3FkU/fnf6zipQAJptbTtrLZLnbjzauH8YoroaK8kOdtrJS66+TSSvICgXVUdTLcXnHds8mCCgULmrPF21ct83LVPs7ddPVp51D0w9ihsQ8Zxs688C8L0AA5Ataf/wBhtyN4AG2L6c5kDEE6YvNNy4j/AHOZmZOkQS9OWHMFYAxVEeV7eg1xTeiyVGDVmXF6ELrBm9JKY8uptSstNVoPVsWrEjp7WqO3qm+aJ3Tqco2LVqkp2uAA5QcNmTpvlLPHGy/rcxhnbKG7GvD1lJ05mm8ks7l3HLFxWTW2YQUFP5MT1ILmj6TpSfNtwKKASYaUQvnUgjfNK5+/RaTFfrNQLUB8uu6zxskn+YeAhbwAHNzpB7TlkL/Pdse868njRCLmA9Y8wP8AuavZY241kKX2dr8jp5E5xZEXN/35vVMhLKaEC0ZPGUkVjFSBpadl2LjrfQl44noF3rtYSL6mcKkDd6xbOJfZqADl0y/yKiHdFPutDHrBJQe8ysTHnPOIc8ck8iUWN3w24dh9i42pD1sF40Wng/Uhm2TMuyYvvSw3ERlt+yuORsXSagsOVHJk0o5ZG5+tvtmG+DwmsS/Q6j8W8ABytbpapgxOyt4lzHulV5cO2XFczq7oLI6fWcqQMqjUgJZXG+VOeS5b22wcR41labbqgdNmTJOwjR0VoKkqFOovwoWTOaqsGHVCuN0GSlArSlNqYsRK3Ydie66a17g0jNhCQkBEMV+2ElyzfMHFz3uJ6grGlAyoHDR+m4Zvm71+7evXcUqWHuX877A4/n3KyScdzOJWIj1kGQMNoWh9pv63Iznf76Y1LCRZKyZcT3UTbc98sUt5fkJNZKNGhS0iHT7hJOtSulVNOLp5atACWvQn6re4sin787/WcOhP1W9xZFP353+s4qUACWvQn6re4sin787/AFnDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nDoT9VvcWRT9+d/rOKlAAlr0J+q3uLIp+/O/1nEGNt/3PQbzAlKC8btf2N0LYoQm27RuR8jssXUfWbvCorqFZhDaEVx20KFlYd7sUm6kW1x2uei2moTLVDq6zku+/0dTRFYpR2YgA40GN9z0YPa0pw1cFUml05ASrNGXkgxPMciylfpLIbnjxWwNzGWnIym9F6QY967baqurISKoVcKxh4PIvcT7Njh73SfNZarGGxn7jfh59XleUdaUmfAU9LddxUsQDLyktuuI1A3b55vWyTOkS5aXn8xuOaqaqrZJ1lJLTjhq7aKUKDWSbfPNrozz56lzLbTiX/vs75TM9T+Ka8s1K+r/R7Pj/AACpYCE+I2oTB9/44RI4cm9ccXxJkTw0ySNNrF5UFZRS0+TG7zcQnYqtZVbr4WEBUZTqVE++7GWbS1U/b4bC2lFT12yrFlAmW3miLWHgXAio7F2GsamHHi0+GA5oudCohXF+o0qsN40FKHI3b/Cksny/uJU4IE+b/NNji91S1v2FymnmumrfIAHD7rax2kDOVPzhwimRDWydjWdgDP8Ap4ZjoViZcl74H9LU6S/dTZKbNo4YO2KriTB0I4wFiikYTCRe4p0qyqRLXG2vo9mxvr9zcPSScximTGxyZkJYQ3c8mnirhE00tdJUkbqal4eQehFpkV0gvfNHlUumv7IOQH2s3i6kbqvl60coRMFy6knqXFXUaACIf3PP2s9seE1nJ6Ys2iBEEEVe/wDcceNiwlt9yOIsyJkRpGcxZqt5ZdKsmMiPtszmdz1clSM3ySiq30xstlJU11ZMFyd2kglEDh4z7WWL3rtHdmADkb2UMnErJPLvA/alIaDLGTmsZ+41yVjfIcp48PXJNtcQst0SQceEYzQtocAuZkSrej9XcfDvj97KBAheTCN4oinXeSO3EZmW7WSNfEc6mJN2IRK/tb+J80TW3oBjmWnYo7D3Rkhm44oOh18PVvcRjxEMZImQ71dLJmp5yC0nO6CryqQarZJgk0wkf4rWF8hf96fU4ADkj1i7WsacMWhnfGuXJl7RBYp2j5+HoLdtiKZCerZyAoWZ1WL55hx+uR6zF0orTUlPEwpo9EXKxyl6LCKZQFtuWVNAoUaG5jEqUzsxQ1EZF5RsNkT1ju8dg+2x+5tT8mNJqll/KPEjCvJqU0Im73M2o/ttV8f+tBKjVktQ8pI51OvLDDS32tuBSNIi40r6YQ7KgAcAOePGtN6xri1L2Fch5oZtrLAzPw7d8q5izrNOX8tw3Bsenpvb7eUjTnduQCymRARkl9u1RSEK6hs5s336gk7y+YV6Gi3jB0stXrlaXm7rT235G5T5REnM0MQs2sY8emqj5KkGk4HTG8TzDjWckVPUI7lw61CS0pMSy8mw8yq+03UuJRdtqp2wYRKFOycJm+KOhMAHL/nPmvIWb2srdC+GnGN9tYPszGtRaGMUxu1ovZkvrI1x8Ng+clt+Ijfd1Sdcph1DUqkRDYLj5biffd9+4sHrdz3On+1843Z8SM3RLKGG2VENJSkga9MwY6hTHLO9IPLy0t2YontdIFzUH5jKt49ZPmDPDucjkWY/mZeUFEoXLF1ZFPly5w6YTE8t1kAAnLIGpTW7Lz3dcpSDifGbwfEgryk7nW6j19zVHHCvLpm4oKSwZqJuGwVqvHzN+4ZrqL2bVnmq5zzbopp544HMnsA+5qHdnxnAktfHiMInwCwQg9uJ6AelK+XUHfJU9yCv1FVt9ORjxvaclSjdbDdL8JDBRb79X4+J9dERyulucupFXCfNzuGABJjWLpbwk1Roqvex0a7nXJVd6ASbshTfJDivL78d6YUM21ClLtkCFpJZbVQ6FK3watprUbCVfM+1levqiuGilo4KzgAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAD6xbue0oqvd6vU9qSz9zq/wewKXaur/AEdQfZj4p4naUCJwhf5rpsnipgneqtVcU3abRmzXZuc26qqauKa+KK+eaKuaauOKupzzTzx+xyE0tLdv2rUnrjp6nU6uHEC3Pv0fot3q/wBPs+qKbjC2OMDsnFyA4cxxja+vGY/g6OGlFzLMOg8VU3HdbLLRiiEjVraiRT0ooeU+SJKz7sNl00lbv3vZ3aS1r2XseM0gAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAJaSL/5TdFiVR+77m1s53GP8Ht2SOAZfq/09TqCpYwaqY+MRXyTZGVBu+4OJMYEJybAaEWtKBWhrVMeWHxFMgOm+fSqk+s6YX7a7DjStpShaVS5Yon3VgveIG7p2wYJ5yAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA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+ ] + }, + { + "cell_type": "markdown", + "id": "918cf3df-2127-4270-bb44-7ed7eb428e28", + "metadata": { + "id": "918cf3df-2127-4270-bb44-7ed7eb428e28" + }, + "source": [ + "### B. Chisel Generation\n", + "For Chisel generation, we utilized the GPT-3.5-turbo as th\n", + "LLM and interacted with the model using API. To genera e\n", + "this logically complex CPU, we first divided it into seve al\n", + "modules, including the fetch stage, decode stage, exe ute\n", + "stage, memory stage, writeback stage, hazard unit, and CSR\n", + "(Control and Status Register) unit. We provided func ional\n", + "descriptions and I/O interfaces for each module, spe ifying\n", + "interface names, orientations, bit-widths, and descr ptions.\n", + "These specifications were then transformed into a s ructured\n", + "format to serve as input for the ChatChisel workflow. Once\n", + "we obtained the output files for all the modules, w connected\n", + "the module interfaces using an LLM to create the top module.\n", + "Then, We use functions in the Chisel package t convert the\n", + "Chisel representation into Verilog for subsequent processes." + ] + }, + { + "cell_type": "markdown", + "id": "46c61cab-91b9-4ec0-9711-3e689517628d", + "metadata": { + "id": "46c61cab-91b9-4ec0-9711-3e689517628d" + }, + "source": [ + "### C. Function Verification\n", + "Function verification is a crucial and iterative process in processor design, as initial designs often fail to meet expectations. We adopt a bottom-up approach, starting with the verification of low-level modules (e.g., ALU) and progressing to high-level modules (e.g., EXU and pipeline modules). This culminates in the verification of the entire CPU. Both module-level and system-level simulation and function verification are achieved using the Verilator platform. The verilated RTL will be cross-validated with the respective reference model." + ] + }, + { + "cell_type": "markdown", + "id": "8c41e640-d07f-46f2-b157-911d90186e56", + "metadata": { + "id": "8c41e640-d07f-46f2-b157-911d90186e56" + }, + "source": [ + "We recommend using Google Colab to do this.We only take DataCache module for example here. **The whole program and source code will open source at Github after we tape out at OpenMPW-9.**" + ] + }, + { + "cell_type": "markdown", + "id": "eaf9baf3-1f49-4ef7-81a1-646cd5640620", + "metadata": { + "id": "eaf9baf3-1f49-4ef7-81a1-646cd5640620" + }, + "source": [ + "#### Install Dependencies" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "2f13f648-9cb0-45dd-99e8-1bc5e5843dba", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "2f13f648-9cb0-45dd-99e8-1bc5e5843dba", + "outputId": "97ed0575-7c31-44cf-b85e-857018dc87fe" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Reading package lists... Done\n", + "Building dependency tree... Done\n", + "Reading state information... Done\n", + "autoconf is already the newest version (2.71-2).\n", + "autoconf set to manually installed.\n", + "g++ is already the newest version (4:11.2.0-1ubuntu1).\n", + "g++ set to manually installed.\n", + "make is already the newest version (4.3-4.1build1).\n", + "make set to manually installed.\n", + "git is already the newest version (1:2.34.1-1ubuntu1.10).\n", + "python3 is already the newest version (3.10.6-1~22.04).\n", + "python3 set to manually installed.\n", + "The following additional packages will be installed:\n", + " libfl-dev libfl2 libhiredis0.14 libperl5.34 perl-base perl-modules-5.34\n", + "Suggested packages:\n", + " bison-doc distcc | icecc flex-doc perl-doc libterm-readline-gnu-perl\n", + " | libterm-readline-perl-perl libtap-harness-archive-perl\n", + "Recommended packages:\n", + " netbase\n", + "The following NEW packages will be installed:\n", + " bison ccache flex libfl-dev libfl2 libhiredis0.14\n", + "The following packages will be upgraded:\n", + " libperl5.34 perl perl-base perl-modules-5.34\n", + "4 upgraded, 6 newly installed, 0 to remove and 41 not upgraded.\n", + "Need to get 11.4 MB of archives.\n", + "After this operation, 5,145 kB of additional disk space will be used.\n", + "Get:1 http://archive.ubuntu.com/ubuntu jammy-updates/main amd64 libperl5.34 amd64 5.34.0-3ubuntu1.3 [4,820 kB]\n", + "Get:2 http://archive.ubuntu.com/ubuntu jammy-updates/main amd64 perl amd64 5.34.0-3ubuntu1.3 [232 kB]\n", + "Get:3 http://archive.ubuntu.com/ubuntu jammy-updates/main amd64 perl-base amd64 5.34.0-3ubuntu1.3 [1,762 kB]\n", + "Get:4 http://archive.ubuntu.com/ubuntu jammy-updates/main amd64 perl-modules-5.34 all 5.34.0-3ubuntu1.3 [2,976 kB]\n", + "Get:5 http://archive.ubuntu.com/ubuntu jammy/main amd64 flex amd64 2.6.4-8build2 [307 kB]\n", + "Get:6 http://archive.ubuntu.com/ubuntu jammy/main amd64 bison amd64 2:3.8.2+dfsg-1build1 [748 kB]\n", + "Get:7 http://archive.ubuntu.com/ubuntu jammy/universe amd64 libhiredis0.14 amd64 0.14.1-2 [32.8 kB]\n", + "Get:8 http://archive.ubuntu.com/ubuntu jammy/universe amd64 ccache amd64 4.5.1-1 [495 kB]\n", + "Get:9 http://archive.ubuntu.com/ubuntu jammy/main amd64 libfl2 amd64 2.6.4-8build2 [10.7 kB]\n", + "Get:10 http://archive.ubuntu.com/ubuntu jammy/main amd64 libfl-dev amd64 2.6.4-8build2 [6,236 B]\n", + "Fetched 11.4 MB in 1s (8,294 kB/s)\n", + "debconf: unable to initialize frontend: Dialog\n", + "debconf: (No usable dialog-like program is installed, so the dialog based frontend cannot be used. at /usr/share/perl5/Debconf/FrontEnd/Dialog.pm line 78, <> line 10.)\n", + "debconf: falling back to frontend: Readline\n", + "debconf: unable to initialize frontend: Readline\n", + "debconf: (This frontend requires a controlling tty.)\n", + "debconf: falling back to frontend: Teletype\n", + "dpkg-preconfigure: unable to re-open stdin: \n", + "(Reading database ... 121752 files and directories currently installed.)\n", + "Preparing to unpack .../libperl5.34_5.34.0-3ubuntu1.3_amd64.deb ...\n", + "Unpacking libperl5.34:amd64 (5.34.0-3ubuntu1.3) over (5.34.0-3ubuntu1.2) ...\n", + "Preparing to unpack .../perl_5.34.0-3ubuntu1.3_amd64.deb ...\n", + "Unpacking perl (5.34.0-3ubuntu1.3) over (5.34.0-3ubuntu1.2) ...\n", + "Preparing to unpack .../perl-base_5.34.0-3ubuntu1.3_amd64.deb ...\n", + "Unpacking perl-base (5.34.0-3ubuntu1.3) over (5.34.0-3ubuntu1.2) ...\n", + "Setting up perl-base (5.34.0-3ubuntu1.3) ...\n", + "(Reading database ... 121752 files and directories currently installed.)\n", + "Preparing to unpack .../0-perl-modules-5.34_5.34.0-3ubuntu1.3_all.deb ...\n", + "Unpacking perl-modules-5.34 (5.34.0-3ubuntu1.3) over (5.34.0-3ubuntu1.2) ...\n", + "Selecting previously unselected package flex.\n", + "Preparing to unpack .../1-flex_2.6.4-8build2_amd64.deb ...\n", + "Unpacking flex (2.6.4-8build2) ...\n", + "Selecting previously unselected package bison.\n", + "Preparing to unpack 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(2:3.8.2+dfsg-1build1) ...\n", + "update-alternatives: using /usr/bin/bison.yacc to provide /usr/bin/yacc (yacc) in auto mode\n", + "Setting up libhiredis0.14:amd64 (0.14.1-2) ...\n", + "Setting up libperl5.34:amd64 (5.34.0-3ubuntu1.3) ...\n", + "Setting up ccache (4.5.1-1) ...\n", + "Updating symlinks in /usr/lib/ccache ...\n", + "Setting up libfl-dev:amd64 (2.6.4-8build2) ...\n", + "Setting up perl (5.34.0-3ubuntu1.3) ...\n", + "Processing triggers for man-db (2.10.2-1) ...\n", + "Processing triggers for libc-bin (2.35-0ubuntu3.4) ...\n", + "/sbin/ldconfig.real: /usr/local/lib/libtbb.so.12 is not a symbolic link\n", + "\n", + "/sbin/ldconfig.real: /usr/local/lib/libtbbbind_2_5.so.3 is not a symbolic link\n", + "\n", + "/sbin/ldconfig.real: /usr/local/lib/libtbbbind.so.3 is not a symbolic link\n", + "\n", + "/sbin/ldconfig.real: /usr/local/lib/libtbbmalloc_proxy.so.2 is not a symbolic link\n", + "\n", + "/sbin/ldconfig.real: /usr/local/lib/libtbbmalloc.so.2 is not a symbolic link\n", + "\n", + "/sbin/ldconfig.real: /usr/local/lib/libtbbbind_2_0.so.3 is not a symbolic link\n", + "\n", + "Reading package lists... Done\n", + "Building dependency tree... Done\n", + "Reading state information... Done\n", + "The following additional packages will be installed:\n", + " libunwind-dev\n", + "The following NEW packages will be installed:\n", + " libgoogle-perftools-dev libunwind-dev numactl perl-doc\n", + "0 upgraded, 4 newly installed, 0 to remove and 41 not upgraded.\n", + "Need to get 10.2 MB of archives.\n", + "After this operation, 25.2 MB of additional disk space will be used.\n", + "Get:1 http://archive.ubuntu.com/ubuntu jammy-updates/main amd64 libunwind-dev amd64 1.3.2-2build2.1 [1,883 kB]\n", + "Get:2 http://archive.ubuntu.com/ubuntu jammy/main amd64 libgoogle-perftools-dev amd64 2.9.1-0ubuntu3 [470 kB]\n", + "Get:3 http://archive.ubuntu.com/ubuntu jammy/main amd64 numactl amd64 2.0.14-3ubuntu2 [36.8 kB]\n", + "Get:4 http://archive.ubuntu.com/ubuntu jammy-updates/main amd64 perl-doc all 5.34.0-3ubuntu1.3 [7,816 kB]\n", + "Fetched 10.2 MB in 1s (8,059 kB/s)\n", + "debconf: unable to initialize frontend: Dialog\n", + "debconf: (No usable dialog-like program is installed, so the dialog based frontend cannot be used. at /usr/share/perl5/Debconf/FrontEnd/Dialog.pm line 78, <> line 4.)\n", + "debconf: falling back to frontend: Readline\n", + "debconf: unable to initialize frontend: Readline\n", + "debconf: (This frontend requires a controlling tty.)\n", + "debconf: falling back to frontend: Teletype\n", + "dpkg-preconfigure: unable to re-open stdin: \n", + "Selecting previously unselected package libunwind-dev:amd64.\n", + "(Reading database ... 121979 files and directories currently installed.)\n", + "Preparing to unpack .../libunwind-dev_1.3.2-2build2.1_amd64.deb ...\n", + "Unpacking libunwind-dev:amd64 (1.3.2-2build2.1) ...\n", + "Selecting previously unselected package libgoogle-perftools-dev:amd64.\n", + "Preparing to unpack .../libgoogle-perftools-dev_2.9.1-0ubuntu3_amd64.deb ...\n", + "Unpacking libgoogle-perftools-dev:amd64 (2.9.1-0ubuntu3) ...\n", + "Selecting previously unselected package numactl.\n", + "Preparing to unpack .../numactl_2.0.14-3ubuntu2_amd64.deb ...\n", + "Unpacking numactl (2.0.14-3ubuntu2) ...\n", + "Selecting previously unselected package perl-doc.\n", + "Preparing to unpack .../perl-doc_5.34.0-3ubuntu1.3_all.deb ...\n", + "Adding 'diversion of /usr/bin/perldoc to /usr/bin/perldoc.stub by perl-doc'\n", + "Unpacking perl-doc (5.34.0-3ubuntu1.3) ...\n", + "Setting up libunwind-dev:amd64 (1.3.2-2build2.1) ...\n", + "Setting up numactl (2.0.14-3ubuntu2) ...\n", + "Setting up libgoogle-perftools-dev:amd64 (2.9.1-0ubuntu3) ...\n", + "Setting up perl-doc (5.34.0-3ubuntu1.3) ...\n", + "Processing triggers for man-db (2.10.2-1) ...\n", + "Reading package lists... Done\n", + "Building dependency tree... Done\n", + "Reading state information... Done\n", + "libfl2 is already the newest version (2.6.4-8build2).\n", + "libfl2 set to manually installed.\n", + "0 upgraded, 0 newly installed, 0 to remove and 41 not upgraded.\n", + "Reading package lists... Done\n", + "Building dependency tree... Done\n", + "Reading state information... Done\n", + "libfl-dev is already the newest version (2.6.4-8build2).\n", + "libfl-dev set to manually installed.\n", + "0 upgraded, 0 newly installed, 0 to remove and 41 not upgraded.\n", + "Reading package lists... Done\n", + "Building dependency tree... Done\n", + "Reading state information... Done\n", + "E: Unable to locate package zlibc\n", + "/content\n", + "Cloning into 'verilator'...\n", + "remote: Enumerating objects: 82105, done.\u001b[K\n", + "remote: Counting objects: 100% (17519/17519), done.\u001b[K\n", + "remote: Compressing objects: 100% (669/669), done.\u001b[K\n", + "remote: Total 82105 (delta 17054), reused 16901 (delta 16850), pack-reused 64586\u001b[K\n", + "Receiving objects: 100% (82105/82105), 25.71 MiB | 16.46 MiB/s, done.\n", + "Resolving deltas: 100% (69484/69484), done.\n", + "/content/verilator\n", + "Already up to date.\n", + "Note: switching to 'v4.224'.\n", + "\n", + "You are in 'detached HEAD' state. You can look around, make experimental\n", + "changes and commit them, and you can discard any commits you make in this\n", + "state without impacting any branches by switching back to a branch.\n", + "\n", + "If you want to create a new branch to retain commits you create, you may\n", + "do so (now or later) by using -c with the switch command. Example:\n", + "\n", + " git switch -c \n", + "\n", + "Or undo this operation with:\n", + "\n", + " git switch -\n", + "\n", + "Turn off this advice by setting config variable advice.detachedHead to false\n", + "\n", + "HEAD is now at 7c79f0d43 Version bump (Changes update)\n", + "configuring for Verilator 4.224 2022-06-19\n", + "checking whether to perform partial static linking of Verilator binary... yes\n", + "checking whether to use tcmalloc... check\n", + "checking whether to use -m32... no\n", + "checking whether to build for coverage collection... no\n", + "checking whether to use hardcoded paths... yes\n", + "checking whether to show and stop on compilation warnings... no\n", + "checking whether to run long tests... no\n", + "checking for gcc... gcc\n", + "checking whether the C compiler works... yes\n", + "checking for C compiler default output file name... a.out\n", + "checking for suffix of executables... \n", + "checking whether we are cross compiling... no\n", + "checking for suffix of object files... o\n", + "checking whether the compiler supports GNU C... yes\n", + "checking whether gcc accepts -g... yes\n", + "checking for gcc option to enable C11 features... none needed\n", + "checking for g++... g++\n", + "checking whether the compiler supports GNU C++... yes\n", + "checking whether g++ accepts -g... yes\n", + "checking for g++ option to enable C++11 features... none needed\n", + "checking for a BSD-compatible install... /usr/bin/install -c\n", + "compiler is g++ --version = g++ (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0\n", + "checking that C++ compiler can compile simple program... yes\n", + "checking for ar... ar\n", + "checking for perl... /usr/bin/perl\n", + "checking for python3... /usr/bin/python3\n", + "checking for flex... /usr/bin/flex\n", + "/usr/bin/flex --version = flex 2.6.4\n", + "checking for bison... /usr/bin/bison\n", + "/usr/bin/bison --version = bison (GNU Bison) 3.8.2\n", + "checking for ccache... ccache\n", + "objcache is ccache --version = ccache version 4.5.1\n", + "checking for stdio.h... yes\n", + "checking for stdlib.h... yes\n", + "checking for string.h... yes\n", + "checking for inttypes.h... yes\n", + "checking for stdint.h... yes\n", + "checking for strings.h... yes\n", + "checking for sys/stat.h... yes\n", + "checking for sys/types.h... yes\n", + "checking for unistd.h... yes\n", + "checking for size_t... yes\n", + "checking for size_t... (cached) yes\n", + "checking for inline... inline\n", + "checking whether g++ accepts -pg... yes\n", + "checking whether g++ accepts -std=gnu++17... yes\n", + "checking whether g++ accepts -Wextra... yes\n", + "checking whether g++ accepts -Wfloat-conversion... yes\n", + "checking whether g++ accepts -Wlogical-op... yes\n", + "checking whether g++ accepts -Wthread-safety... no\n", + "checking whether g++ accepts -Qunused-arguments... no\n", + "checking whether g++ accepts -faligned-new... yes\n", + "checking whether g++ accepts -Wno-unused-parameter... yes\n", + "checking whether g++ accepts -Wno-shadow... yes\n", + "checking whether g++ accepts -Wno-char-subscripts... yes\n", + "checking whether g++ accepts -Wno-null-conversion... no\n", + "checking whether g++ accepts -Wno-parentheses-equality... no\n", + "checking whether g++ accepts -Wno-unused... yes\n", + "checking whether g++ accepts -Og... yes\n", + "checking whether g++ accepts -ggdb... yes\n", + "checking whether g++ accepts -gz... yes\n", + "checking whether g++ linker accepts -gz... yes\n", + "checking whether g++ accepts -faligned-new... yes\n", + "checking whether g++ accepts -fbracket-depth=4096... no\n", + "checking whether g++ accepts -fcf-protection=none... yes\n", + "checking whether g++ accepts -mno-cet... no\n", + "checking whether g++ accepts -Qunused-arguments... no\n", + "checking whether g++ accepts -Wno-bool-operation... yes\n", + "checking whether g++ accepts -Wno-tautological-bitwise-compare... no\n", + "checking whether g++ accepts -Wno-parentheses-equality... no\n", + "checking whether g++ accepts -Wno-sign-compare... yes\n", + "checking whether g++ accepts -Wno-uninitialized... yes\n", + "checking whether g++ accepts -Wno-unused-but-set-variable... yes\n", + "checking whether g++ accepts -Wno-unused-parameter... yes\n", + "checking whether g++ accepts -Wno-unused-variable... yes\n", + "checking whether g++ accepts -Wno-shadow... yes\n", + "checking whether g++ linker accepts -mt... no\n", + "checking whether g++ linker accepts -pthread... yes\n", + "checking whether g++ linker accepts -lpthread... yes\n", + "checking whether g++ linker accepts -latomic... yes\n", + "checking whether g++ linker accepts -static-libgcc... yes\n", + "checking whether g++ linker accepts -static-libstdc++... yes\n", + "checking whether g++ linker accepts -Xlinker -gc-sections... yes\n", + "checking whether g++ linker accepts -lpthread... yes\n", + "checking whether g++ linker accepts -lbcrypt... no\n", + "checking whether g++ linker accepts -lpsapi... no\n", + "checking whether g++ linker accepts -l:libtcmalloc_minimal.a... yes\n", + "checking whether g++ accepts -fno-builtin-malloc... yes\n", + "checking whether g++ accepts -fno-builtin-calloc... yes\n", + "checking whether g++ accepts -fno-builtin-realloc... yes\n", + "checking whether g++ accepts -fno-builtin-free... yes\n", + "checking whether g++ supports C++11... yes\n", + "checking for struct stat.st_mtim.tv_nsec... yes\n", + "checking whether SystemC is found (in system path)... no\n", + "configure: creating ./config.status\n", + "config.status: creating Makefile\n", + "config.status: creating src/Makefile\n", + "config.status: creating src/Makefile_obj\n", + "config.status: creating include/verilated.mk\n", + "config.status: creating include/verilated_config.h\n", + "config.status: creating verilator.pc\n", + "config.status: creating verilator-config.cmake\n", + "config.status: creating verilator-config-version.cmake\n", + "config.status: creating src/config_build.h\n", + "\n", + "Now type 'make' (or sometimes 'gmake') to build Verilator.\n", + "\n", + "pod2man bin/verilator verilator.1\n", + "pod2man bin/verilator_coverage verilator_coverage.1\n", + "------------------------------------------------------------\n", + "making verilator in src\n", + "make -C src \n", + "make[1]: Entering directory '/content/verilator/src'\n", + "mkdir -p obj_dbg\n", + "/usr/bin/python3 ./config_rev . >config_rev.h\n", + "mkdir -p obj_opt\n", + "make -C obj_dbg -j 1 TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj serial\n", + "make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj serial_vlcov\n", + "make -C obj_opt -j 1 TGT=../../bin/verilator_bin -f ../Makefile_obj serial\n", + "make[2]: Entering directory '/content/verilator/src'\n", + "make[2]: warning: -j1 forced in submake: resetting jobserver mode.\n", + "/usr/bin/python3 ../astgen -I .. --classes\n", + "make[2]: Entering directory '/content/verilator/src/obj_dbg'\n", + "/usr/bin/python3 ../vlcovgen --srcdir ..\n", + "make[2]: Entering directory '/content/verilator/src'\n", + "make[2]: warning: -j1 forced in submake: resetting jobserver mode.\n", + "/usr/bin/python3 ../astgen -I .. --classes\n", + "touch vlcovgen.d\n", + "make[2]: Leaving directory '/content/verilator/src/obj_dbg'\n", + "make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj\n", + "make[2]: Entering directory '/content/verilator/src/obj_dbg'\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../VlcMain.cpp -o VlcMain.o\n", + " Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\"\" -DDEFENV_SYSTEMC_ARCH=\"\" -DDEFENV_SYSTEMC_INCLUDE=\"\" -DDEFENV_SYSTEMC_LIBDIR=\"\" -DDEFENV_VERILATOR_ROOT=\"/usr/local/share/verilator\"\n", + "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer.\n", + "/usr/bin/python3 ../bisonpre --yacc /usr/bin/bison -d -v -o V3ParseBison.c ../verilog.y\n", + " edit ../verilog.y V3ParseBison_pretmp.y\n", + "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer.\n", + "/usr/bin/python3 ../bisonpre --yacc /usr/bin/bison -d -v -o V3ParseBison.c ../verilog.y\n", + " edit ../verilog.y V3ParseBison_pretmp.y\n", + " /usr/bin/bison -d -v --report=itemset --report=lookahead -b V3ParseBison_pretmp -o V3ParseBison_pretmp.c V3ParseBison_pretmp.y\n", + " /usr/bin/bison -d -v --report=itemset --report=lookahead -b V3ParseBison_pretmp -o V3ParseBison_pretmp.c V3ParseBison_pretmp.y\n", + " edit V3ParseBison_pretmp.output V3ParseBison.output\n", + " edit V3ParseBison_pretmp.output V3ParseBison.output\n", + " Linking ../../bin/verilator_coverage_bin_dbg...\n", + "g++ -gz -static-libgcc -static-libstdc++ -Xlinker -gc-sections -o ../../bin/verilator_coverage_bin_dbg VlcMain.o -l:libtcmalloc_minimal.a -lpthread -lm\n", + "make[2]: Leaving directory '/content/verilator/src/obj_dbg'\n", + " edit V3ParseBison_pretmp.c V3ParseBison.c\n", + " edit V3ParseBison_pretmp.c V3ParseBison.c\n", + " edit V3ParseBison_pretmp.h V3ParseBison.h\n", + "make[2]: Leaving directory '/content/verilator/src/obj_opt'\n", + "make -C obj_opt TGT=../../bin/verilator_bin -f ../Makefile_obj\n", + "make[2]: Entering directory '/content/verilator/src/obj_opt'\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../Verilator.cpp -o Verilator.o\n", + " Compile flags: g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\"\" -DDEFENV_SYSTEMC_ARCH=\"\" -DDEFENV_SYSTEMC_INCLUDE=\"\" -DDEFENV_SYSTEMC_LIBDIR=\"\" -DDEFENV_VERILATOR_ROOT=\"/usr/local/share/verilator\"\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Active.cpp -o V3Active.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3ActiveTop.cpp -o V3ActiveTop.o\n", + " edit V3ParseBison_pretmp.h V3ParseBison.h\n", + "make[2]: Leaving directory '/content/verilator/src/obj_dbg'\n", + "make -C obj_dbg TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj\n", + "make[2]: Entering directory '/content/verilator/src/obj_dbg'\n", + " Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\"\" -DDEFENV_SYSTEMC_ARCH=\"\" -DDEFENV_SYSTEMC_INCLUDE=\"\" -DDEFENV_SYSTEMC_LIBDIR=\"\" -DDEFENV_VERILATOR_ROOT=\"/usr/local/share/verilator\"\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../Verilator.cpp -o Verilator.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Active.cpp -o V3Active.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Assert.cpp -o V3Assert.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3AssertPre.cpp -o V3AssertPre.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3ActiveTop.cpp -o V3ActiveTop.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Ast.cpp -o V3Ast.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3AstNodes.cpp -o V3AstNodes.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Assert.cpp -o V3Assert.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3AssertPre.cpp -o V3AssertPre.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Begin.cpp -o V3Begin.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Ast.cpp -o V3Ast.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3AstNodes.cpp -o V3AstNodes.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Branch.cpp -o V3Branch.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Broken.cpp -o V3Broken.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Begin.cpp -o V3Begin.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3CCtors.cpp -o V3CCtors.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3CUse.cpp -o V3CUse.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Branch.cpp -o V3Branch.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Broken.cpp -o V3Broken.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Case.cpp -o V3Case.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Cast.cpp -o V3Cast.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3CCtors.cpp -o V3CCtors.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Cdc.cpp -o V3Cdc.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3CUse.cpp -o V3CUse.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Changed.cpp -o V3Changed.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Case.cpp -o V3Case.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Class.cpp -o V3Class.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Clean.cpp -o V3Clean.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Cast.cpp -o V3Cast.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Cdc.cpp -o V3Cdc.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Clock.cpp -o V3Clock.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Combine.cpp -o V3Combine.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Changed.cpp -o V3Changed.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Common.cpp -o V3Common.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Config.cpp -o V3Config.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Class.cpp -o V3Class.o\n", + "/usr/bin/python3 ../astgen -I .. V3Const.cpp\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Coverage.cpp -o V3Coverage.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3CoverageJoin.cpp -o V3CoverageJoin.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Clean.cpp -o V3Clean.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Dead.cpp -o V3Dead.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Delayed.cpp -o V3Delayed.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Depth.cpp -o V3Depth.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3DepthBlock.cpp -o V3DepthBlock.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Clock.cpp -o V3Clock.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Descope.cpp -o V3Descope.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3DupFinder.cpp -o V3DupFinder.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCBase.cpp -o V3EmitCBase.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCConstPool.cpp -o V3EmitCConstPool.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCFunc.cpp -o V3EmitCFunc.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Combine.cpp -o V3Combine.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCHeaders.cpp -o V3EmitCHeaders.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCImp.cpp -o V3EmitCImp.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCInlines.cpp -o V3EmitCInlines.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Common.cpp -o V3Common.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCMain.cpp -o V3EmitCMain.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCMake.cpp -o V3EmitCMake.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Config.cpp -o V3Config.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCModel.cpp -o V3EmitCModel.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCSyms.cpp -o V3EmitCSyms.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitMk.cpp -o V3EmitMk.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitV.cpp -o V3EmitV.o\n", + "/usr/bin/python3 ../astgen -I .. V3Const.cpp\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Coverage.cpp -o V3Coverage.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3CoverageJoin.cpp -o V3CoverageJoin.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitXml.cpp -o V3EmitXml.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Error.cpp -o V3Error.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Dead.cpp -o V3Dead.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Expand.cpp -o V3Expand.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Delayed.cpp -o V3Delayed.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3File.cpp -o V3File.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Depth.cpp -o V3Depth.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3FileLine.cpp -o V3FileLine.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Force.cpp -o V3Force.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Gate.cpp -o V3Gate.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3DepthBlock.cpp -o V3DepthBlock.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GenClk.cpp -o V3GenClk.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Global.cpp -o V3Global.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Graph.cpp -o V3Graph.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GraphAlg.cpp -o V3GraphAlg.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GraphAcyc.cpp -o V3GraphAcyc.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Descope.cpp -o V3Descope.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GraphPathChecker.cpp -o V3GraphPathChecker.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GraphTest.cpp -o V3GraphTest.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Hash.cpp -o V3Hash.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Hasher.cpp -o V3Hasher.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3HierBlock.cpp -o V3HierBlock.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Inline.cpp -o V3Inline.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3DupFinder.cpp -o V3DupFinder.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Inst.cpp -o V3Inst.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3InstrCount.cpp -o V3InstrCount.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Life.cpp -o V3Life.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCBase.cpp -o V3EmitCBase.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LifePost.cpp -o V3LifePost.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkCells.cpp -o V3LinkCells.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkDot.cpp -o V3LinkDot.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCConstPool.cpp -o V3EmitCConstPool.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkJump.cpp -o V3LinkJump.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkInc.cpp -o V3LinkInc.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkLValue.cpp -o V3LinkLValue.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCFunc.cpp -o V3EmitCFunc.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCHeaders.cpp -o V3EmitCHeaders.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkLevel.cpp -o V3LinkLevel.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkParse.cpp -o V3LinkParse.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkResolve.cpp -o V3LinkResolve.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCImp.cpp -o V3EmitCImp.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCInlines.cpp -o V3EmitCInlines.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Localize.cpp -o V3Localize.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3MergeCond.cpp -o V3MergeCond.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCMain.cpp -o V3EmitCMain.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Name.cpp -o V3Name.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Number.cpp -o V3Number.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCMake.cpp -o V3EmitCMake.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCModel.cpp -o V3EmitCModel.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3OptionParser.cpp -o V3OptionParser.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Options.cpp -o V3Options.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitCSyms.cpp -o V3EmitCSyms.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Order.cpp -o V3Order.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Os.cpp -o V3Os.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitMk.cpp -o V3EmitMk.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Param.cpp -o V3Param.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Partition.cpp -o V3Partition.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitV.cpp -o V3EmitV.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3EmitXml.cpp -o V3EmitXml.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3PreShell.cpp -o V3PreShell.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Premit.cpp -o V3Premit.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Error.cpp -o V3Error.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Expand.cpp -o V3Expand.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3ProtectLib.cpp -o V3ProtectLib.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Randomize.cpp -o V3Randomize.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3File.cpp -o V3File.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3FileLine.cpp -o V3FileLine.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Reloop.cpp -o V3Reloop.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Scope.cpp -o V3Scope.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Force.cpp -o V3Force.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Scoreboard.cpp -o V3Scoreboard.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Gate.cpp -o V3Gate.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Slice.cpp -o V3Slice.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Split.cpp -o V3Split.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GenClk.cpp -o V3GenClk.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3SplitAs.cpp -o V3SplitAs.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3SplitVar.cpp -o V3SplitVar.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Global.cpp -o V3Global.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Stats.cpp -o V3Stats.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Graph.cpp -o V3Graph.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GraphAlg.cpp -o V3GraphAlg.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GraphAcyc.cpp -o V3GraphAcyc.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3StatsReport.cpp -o V3StatsReport.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3String.cpp -o V3String.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Subst.cpp -o V3Subst.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GraphPathChecker.cpp -o V3GraphPathChecker.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3GraphTest.cpp -o V3GraphTest.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Hash.cpp -o V3Hash.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Table.cpp -o V3Table.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Task.cpp -o V3Task.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Hasher.cpp -o V3Hasher.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Trace.cpp -o V3Trace.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3HierBlock.cpp -o V3HierBlock.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3TraceDecl.cpp -o V3TraceDecl.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Tristate.cpp -o V3Tristate.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3TSP.cpp -o V3TSP.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Undriven.cpp -o V3Undriven.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Unknown.cpp -o V3Unknown.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Inline.cpp -o V3Inline.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Unroll.cpp -o V3Unroll.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3VariableOrder.cpp -o V3VariableOrder.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Inst.cpp -o V3Inst.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Waiver.cpp -o V3Waiver.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Width.cpp -o V3Width.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3WidthSel.cpp -o V3WidthSel.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -Wno-char-subscripts -Wno-unused -c ../V3ParseImp.cpp -o V3ParseImp.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3InstrCount.cpp -o V3InstrCount.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -Wno-char-subscripts -Wno-unused -c ../V3ParseGrammar.cpp -o V3ParseGrammar.o\n", + "/usr/bin/flex --version\n", + "flex 2.6.4\n", + "/usr/bin/flex -d -oV3Lexer_pregen.yy.cpp ../verilog.l\n", + "/usr/bin/flex --version\n", + "flex 2.6.4\n", + "/usr/bin/flex -d -oV3PreLex_pregen.yy.cpp ../V3PreLex.l\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Life.cpp -o V3Life.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LifePost.cpp -o V3LifePost.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c V3Const__gen.cpp -o V3Const__gen.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkCells.cpp -o V3LinkCells.o\n", + "/usr/bin/python3 ../flexfix V3Lexer V3Lexer.yy.cpp\n", + "/usr/bin/python3 ../flexfix V3PreLex V3PreLex.yy.cpp\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -Wno-char-subscripts -Wno-unused -c ../V3ParseLex.cpp -o V3ParseLex.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkDot.cpp -o V3LinkDot.o\n", + "ccache g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -Wno-char-subscripts -Wno-unused -c ../V3PreProc.cpp -o V3PreProc.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkJump.cpp -o V3LinkJump.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkInc.cpp -o V3LinkInc.o\n", + " Linking ../../bin/verilator_bin...\n", + "g++ -static-libgcc -static-libstdc++ -Xlinker -gc-sections -o ../../bin/verilator_bin Verilator.o V3Active.o V3ActiveTop.o V3Assert.o V3AssertPre.o V3Ast.o V3AstNodes.o V3Begin.o V3Branch.o V3Broken.o V3CCtors.o V3CUse.o V3Case.o V3Cast.o V3Cdc.o V3Changed.o V3Class.o V3Clean.o V3Clock.o V3Combine.o V3Common.o V3Config.o V3Const__gen.o V3Coverage.o V3CoverageJoin.o V3Dead.o V3Delayed.o V3Depth.o V3DepthBlock.o V3Descope.o V3DupFinder.o V3EmitCBase.o V3EmitCConstPool.o V3EmitCFunc.o V3EmitCHeaders.o V3EmitCImp.o V3EmitCInlines.o V3EmitCMain.o V3EmitCMake.o V3EmitCModel.o V3EmitCSyms.o V3EmitMk.o V3EmitV.o V3EmitXml.o V3Error.o V3Expand.o V3File.o V3FileLine.o V3Force.o V3Gate.o V3GenClk.o V3Global.o V3Graph.o V3GraphAlg.o V3GraphAcyc.o V3GraphPathChecker.o V3GraphTest.o V3Hash.o V3Hasher.o V3HierBlock.o V3Inline.o V3Inst.o V3InstrCount.o V3Life.o V3LifePost.o V3LinkCells.o V3LinkDot.o V3LinkJump.o V3LinkInc.o V3LinkLValue.o V3LinkLevel.o V3LinkParse.o V3LinkResolve.o V3Localize.o V3MergeCond.o V3Name.o V3Number.o V3OptionParser.o V3Options.o V3Order.o V3Os.o V3Param.o V3Partition.o V3PreShell.o V3Premit.o V3ProtectLib.o V3Randomize.o V3Reloop.o V3Scope.o V3Scoreboard.o V3Slice.o V3Split.o V3SplitAs.o V3SplitVar.o V3Stats.o V3StatsReport.o V3String.o V3Subst.o V3Table.o V3Task.o V3Trace.o V3TraceDecl.o V3Tristate.o V3TSP.o V3Undriven.o V3Unknown.o V3Unroll.o V3VariableOrder.o V3Waiver.o V3Width.o V3WidthSel.o V3ParseImp.o V3ParseGrammar.o V3ParseLex.o V3PreProc.o -l:libtcmalloc_minimal.a -lpthread -lm\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkLValue.cpp -o V3LinkLValue.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkLevel.cpp -o V3LinkLevel.o\n", + "make[2]: Leaving directory '/content/verilator/src/obj_opt'\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkParse.cpp -o V3LinkParse.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3LinkResolve.cpp -o V3LinkResolve.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Localize.cpp -o V3Localize.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3MergeCond.cpp -o V3MergeCond.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Name.cpp -o V3Name.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Number.cpp -o V3Number.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3OptionParser.cpp -o V3OptionParser.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Options.cpp -o V3Options.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Order.cpp -o V3Order.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Os.cpp -o V3Os.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Param.cpp -o V3Param.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Partition.cpp -o V3Partition.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3PreShell.cpp -o V3PreShell.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Premit.cpp -o V3Premit.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3ProtectLib.cpp -o V3ProtectLib.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Randomize.cpp -o V3Randomize.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Reloop.cpp -o V3Reloop.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Scope.cpp -o V3Scope.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Scoreboard.cpp -o V3Scoreboard.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Slice.cpp -o V3Slice.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Split.cpp -o V3Split.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3SplitAs.cpp -o V3SplitAs.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3SplitVar.cpp -o V3SplitVar.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Stats.cpp -o V3Stats.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3StatsReport.cpp -o V3StatsReport.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3String.cpp -o V3String.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Subst.cpp -o V3Subst.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Table.cpp -o V3Table.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Task.cpp -o V3Task.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Trace.cpp -o V3Trace.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3TraceDecl.cpp -o V3TraceDecl.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Tristate.cpp -o V3Tristate.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3TSP.cpp -o V3TSP.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Undriven.cpp -o V3Undriven.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Unknown.cpp -o V3Unknown.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Unroll.cpp -o V3Unroll.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3VariableOrder.cpp -o V3VariableOrder.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Waiver.cpp -o V3Waiver.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3Width.cpp -o V3Width.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c ../V3WidthSel.cpp -o V3WidthSel.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -Wno-char-subscripts -Wno-unused -c ../V3ParseImp.cpp -o V3ParseImp.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -Wno-char-subscripts -Wno-unused -c ../V3ParseGrammar.cpp -o V3ParseGrammar.o\n", + "/usr/bin/flex --version\n", + "flex 2.6.4\n", + "/usr/bin/flex -d -oV3Lexer_pregen.yy.cpp ../verilog.l\n", + "/usr/bin/flex --version\n", + "flex 2.6.4\n", + "/usr/bin/flex -d -oV3PreLex_pregen.yy.cpp ../V3PreLex.l\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -c V3Const__gen.cpp -o V3Const__gen.o\n", + "/usr/bin/python3 ../flexfix V3Lexer V3Lexer.yy.cpp\n", + "/usr/bin/python3 ../flexfix V3PreLex V3PreLex.yy.cpp\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -Wno-char-subscripts -Wno-unused -c ../V3ParseLex.cpp -o V3ParseLex.o\n", + "ccache g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\\\"\\\" -DDEFENV_SYSTEMC_ARCH=\\\"\\\" -DDEFENV_SYSTEMC_INCLUDE=\\\"\\\" -DDEFENV_SYSTEMC_LIBDIR=\\\"\\\" -DDEFENV_VERILATOR_ROOT=\\\"/usr/local/share/verilator\\\" -Wno-char-subscripts -Wno-unused -c ../V3PreProc.cpp -o V3PreProc.o\n", + " Linking ../../bin/verilator_bin_dbg...\n", + "g++ -gz -static-libgcc -static-libstdc++ -Xlinker -gc-sections -o ../../bin/verilator_bin_dbg Verilator.o V3Active.o V3ActiveTop.o V3Assert.o V3AssertPre.o V3Ast.o V3AstNodes.o V3Begin.o V3Branch.o V3Broken.o V3CCtors.o V3CUse.o V3Case.o V3Cast.o V3Cdc.o V3Changed.o V3Class.o V3Clean.o V3Clock.o V3Combine.o V3Common.o V3Config.o V3Const__gen.o V3Coverage.o V3CoverageJoin.o V3Dead.o V3Delayed.o V3Depth.o V3DepthBlock.o V3Descope.o V3DupFinder.o V3EmitCBase.o V3EmitCConstPool.o V3EmitCFunc.o V3EmitCHeaders.o V3EmitCImp.o V3EmitCInlines.o V3EmitCMain.o V3EmitCMake.o V3EmitCModel.o V3EmitCSyms.o V3EmitMk.o V3EmitV.o V3EmitXml.o V3Error.o V3Expand.o V3File.o V3FileLine.o V3Force.o V3Gate.o V3GenClk.o V3Global.o V3Graph.o V3GraphAlg.o V3GraphAcyc.o V3GraphPathChecker.o V3GraphTest.o V3Hash.o V3Hasher.o V3HierBlock.o V3Inline.o V3Inst.o V3InstrCount.o V3Life.o V3LifePost.o V3LinkCells.o V3LinkDot.o V3LinkJump.o V3LinkInc.o V3LinkLValue.o V3LinkLevel.o V3LinkParse.o V3LinkResolve.o V3Localize.o V3MergeCond.o V3Name.o V3Number.o V3OptionParser.o V3Options.o V3Order.o V3Os.o V3Param.o V3Partition.o V3PreShell.o V3Premit.o V3ProtectLib.o V3Randomize.o V3Reloop.o V3Scope.o V3Scoreboard.o V3Slice.o V3Split.o V3SplitAs.o V3SplitVar.o V3Stats.o V3StatsReport.o V3String.o V3Subst.o V3Table.o V3Task.o V3Trace.o V3TraceDecl.o V3Tristate.o V3TSP.o V3Undriven.o V3Unknown.o V3Unroll.o V3VariableOrder.o V3Waiver.o V3Width.o V3WidthSel.o V3ParseImp.o V3ParseGrammar.o V3ParseLex.o V3PreProc.o -l:libtcmalloc_minimal.a -lpthread -lm\n", + "make[2]: Leaving directory '/content/verilator/src/obj_dbg'\n", + "make[1]: Leaving directory '/content/verilator/src'\n", + "Build complete!\n", + "\n", + "Now type 'make test' to test.\n", + "\n", + "------------------------------------------------------------\n", + "making verilator in src\n", + "make -C src \n", + "make[1]: Entering directory '/content/verilator/src'\n", + "make -C obj_dbg -j 1 TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj serial\n", + "make[2]: Entering directory '/content/verilator/src/obj_dbg'\n", + "make[2]: Nothing to be done for 'serial'.\n", + "make[2]: Leaving directory '/content/verilator/src/obj_dbg'\n", + "make -C obj_dbg TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj\n", + "make[2]: Entering directory '/content/verilator/src/obj_dbg'\n", + " Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\"\" -DDEFENV_SYSTEMC_ARCH=\"\" -DDEFENV_SYSTEMC_INCLUDE=\"\" -DDEFENV_SYSTEMC_LIBDIR=\"\" -DDEFENV_VERILATOR_ROOT=\"/usr/local/share/verilator\"\n", + "make[2]: Leaving directory '/content/verilator/src/obj_dbg'\n", + "make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj serial_vlcov\n", + "make[2]: Entering directory '/content/verilator/src/obj_dbg'\n", + "make[2]: Nothing to be done for 'serial_vlcov'.\n", + "make[2]: Leaving directory '/content/verilator/src/obj_dbg'\n", + "make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj\n", + "make[2]: Entering directory '/content/verilator/src/obj_dbg'\n", + " Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\"\" -DDEFENV_SYSTEMC_ARCH=\"\" -DDEFENV_SYSTEMC_INCLUDE=\"\" -DDEFENV_SYSTEMC_LIBDIR=\"\" -DDEFENV_VERILATOR_ROOT=\"/usr/local/share/verilator\"\n", + "make[2]: Leaving directory '/content/verilator/src/obj_dbg'\n", + "make -C obj_opt -j 1 TGT=../../bin/verilator_bin -f ../Makefile_obj serial\n", + "make[2]: Entering directory '/content/verilator/src/obj_opt'\n", + "make[2]: Nothing to be done for 'serial'.\n", + "make[2]: Leaving directory '/content/verilator/src/obj_opt'\n", + "make -C obj_opt TGT=../../bin/verilator_bin -f ../Makefile_obj\n", + "make[2]: Entering directory '/content/verilator/src/obj_opt'\n", + " Compile flags: g++ -O2 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free -DDEFENV_SYSTEMC=\"\" -DDEFENV_SYSTEMC_ARCH=\"\" -DDEFENV_SYSTEMC_INCLUDE=\"\" -DDEFENV_SYSTEMC_LIBDIR=\"\" -DDEFENV_VERILATOR_ROOT=\"/usr/local/share/verilator\"\n", + "make[2]: Leaving directory '/content/verilator/src/obj_opt'\n", + "make[1]: Leaving directory '/content/verilator/src'\n", + "/bin/sh ./src/mkinstalldirs /usr/local/bin\n", + "( cd ./bin ; /usr/bin/install -c verilator /usr/local/bin/verilator )\n", + "( cd ./bin ; /usr/bin/install -c verilator_coverage /usr/local/bin/verilator_coverage )\n", + "( cd ./bin ; /usr/bin/install -c verilator_gantt /usr/local/bin/verilator_gantt )\n", + "( cd ./bin ; /usr/bin/install -c verilator_profcfunc /usr/local/bin/verilator_profcfunc )\n", + "( cd bin ; /usr/bin/install -c verilator_bin /usr/local/bin/verilator_bin )\n", + "( cd bin ; /usr/bin/install -c verilator_bin_dbg /usr/local/bin/verilator_bin_dbg )\n", + "( cd bin ; /usr/bin/install -c verilator_coverage_bin_dbg /usr/local/bin/verilator_coverage_bin_dbg )\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/bin\n", + "mkdir /usr/local/share/verilator\n", + "mkdir /usr/local/share/verilator/bin\n", + "( cd ./bin ; /usr/bin/install -c verilator_includer /usr/local/share/verilator/bin/verilator_includer )\n", + "( cd ./bin ; /usr/bin/install -c verilator_ccache_report /usr/local/share/verilator/bin/verilator_ccache_report )\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/man/man1\n", + "for p in verilator.1 verilator_coverage.1 ; do \\\n", + " /usr/bin/install -c -m 644 $p /usr/local/share/man/man1/$p; \\\n", + "done\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/include/gtkwave\n", + "mkdir /usr/local/share/verilator/include\n", + "mkdir /usr/local/share/verilator/include/gtkwave\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/include/vltstd\n", + "mkdir /usr/local/share/verilator/include/vltstd\n", + "for p in include/verilated_config.h include/verilated.mk ; do \\\n", + " /usr/bin/install -c -m 644 $p /usr/local/share/verilator/$p; \\\n", + "done\n", + "cd . \\\n", + "; for p in include/*.[chv]* include/gtkwave/*.[chv]* include/vltstd/*.[chv]* ; do \\\n", + " /usr/bin/install -c -m 644 $p /usr/local/share/verilator/$p; \\\n", + "done\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/make_hello_c\n", + "mkdir /usr/local/share/verilator/examples\n", + "mkdir /usr/local/share/verilator/examples/make_hello_c\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/make_hello_sc\n", + "mkdir /usr/local/share/verilator/examples/make_hello_sc\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/make_tracing_c\n", + "mkdir /usr/local/share/verilator/examples/make_tracing_c\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/make_tracing_sc\n", + "mkdir /usr/local/share/verilator/examples/make_tracing_sc\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/make_protect_lib\n", + "mkdir /usr/local/share/verilator/examples/make_protect_lib\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/cmake_hello_c\n", + "mkdir /usr/local/share/verilator/examples/cmake_hello_c\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/cmake_hello_sc\n", + "mkdir /usr/local/share/verilator/examples/cmake_hello_sc\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/cmake_tracing_c\n", + "mkdir /usr/local/share/verilator/examples/cmake_tracing_c\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/cmake_tracing_sc\n", + "mkdir /usr/local/share/verilator/examples/cmake_tracing_sc\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/cmake_protect_lib\n", + "mkdir /usr/local/share/verilator/examples/cmake_protect_lib\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/verilator/examples/xml_py\n", + "mkdir /usr/local/share/verilator/examples/xml_py\n", + "cd . \\\n", + "; for p in examples/*/*.[chv]* examples/*/CMakeLists.txt examples/*/Makefile* examples/*/vl_* ; do \\\n", + " /usr/bin/install -c -m 644 $p /usr/local/share/verilator/$p; \\\n", + "done\n", + "/bin/sh ./src/mkinstalldirs /usr/local/share/pkgconfig\n", + "mkdir /usr/local/share/pkgconfig\n", + "/usr/bin/install -c -m 644 verilator.pc /usr/local/share/pkgconfig\n", + "/usr/bin/install -c -m 644 verilator-config.cmake /usr/local/share/verilator\n", + "/usr/bin/install -c -m 644 verilator-config-version.cmake /usr/local/share/verilator\n", + "\n", + "Installed binaries to /usr/local/bin/verilator\n", + "Installed man to /usr/local/share/man/man1\n", + "Installed examples to /usr/local/share/verilator/examples\n", + "\n", + "For documentation see 'man verilator' or 'verilator --help'\n", + "For forums and to report bugs see https://verilator.org\n", + "\n" + ] + } + ], + "source": [ + "!sudo apt-get install git perl python3 make autoconf g++ flex bison ccache\n", + "!sudo apt-get install libgoogle-perftools-dev numactl perl-doc\n", + "!sudo apt-get install libfl2 # Ubuntu only (ignore if gives error)\n", + "!sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error)\n", + "!sudo apt-get install zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error)\n", + "%cd /content\n", + "!git clone https://github.com/verilator/verilator # Only first time\n", + "\n", + "# Every time you need to build:\n", + "%cd verilator\n", + "!git pull # Make sure git repository is up-to-date\n", + "!git checkout v4.224\n", + "\n", + "!autoconf # Create ./configure script\n", + "!./configure # Configure and create Makefile\n", + "!make -j4\n", + "!sudo make install" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "98a35ac1-3198-414a-855d-09776b767223", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "98a35ac1-3198-414a-855d-09776b767223", + "outputId": "5b82d69e-0549-4460-ac19-4a62157d6bc9" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Usage:\n", + " verilator --help\n", + " verilator --version\n", + " verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]\n", + " verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]\n", + " verilator --lint-only -Wall [source_files.v]...\n", + "\n" + ] + } + ], + "source": [ + "!verilator" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "4594739e-1b69-47b2-a5bf-e7ea91821526", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "4594739e-1b69-47b2-a5bf-e7ea91821526", + "outputId": "0de429da-ac23-4cb2-a7c3-f1fc3dbe4ba4" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Reading package lists... Done\n", + "Building dependency tree... Done\n", + "Reading state information... Done\n", + "gtkwave is already the newest version (3.3.104-2build1).\n", + "0 upgraded, 0 newly installed, 0 to remove and 41 not upgraded.\n" + ] + } + ], + "source": [ + "!sudo apt-get install gtkwave" + ] + }, + { + "cell_type": "markdown", + "id": "d00a3449-c918-4bf7-8254-df0bcb2da08c", + "metadata": { + "id": "d00a3449-c918-4bf7-8254-df0bcb2da08c" + }, + "source": [ + "Now that verilator is set up, you can import your design for validation. Here, we take the validation of the ***DataCache*** module as an example to demonstrate its feasibility. We will update more complete verifications in our repo." + ] + }, + { + "cell_type": "code", + "source": [ + "%cd /content/verilator" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "zovfmyYLEMMW", + "outputId": "d1d51db8-a95c-486f-ad37-b62514abd486" + }, + "id": "zovfmyYLEMMW", + "execution_count": null, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "/content/verilator\n" + ] + } + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "c41f0da7-4df8-4080-813f-ac9d982cc299", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "c41f0da7-4df8-4080-813f-ac9d982cc299", + "outputId": "3c73c5b1-7069-4dd7-be29-42a2e8784b7c" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Overwriting DataCache.v\n" + ] + } + ], + "source": [ + "%%writefile DataCache.v\n", + "`timescale 1ns/1ns\n", + "module DataCache(\n", + " input clock,\n", + " input reset,\n", + " input [31:0] io_mem_aluresult,\n", + " input [31:0] io_mem_rs2_data,\n", + " input io_mem_memread,\n", + " input [2:0] io_mem_funct3,\n", + " input io_mem_memwrite,\n", + " output [31:0] io_read_data\n", + ");\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " reg [31:0] _RAND_0;\n", + "`endif // RANDOMIZE_MEM_INIT\n", + " reg [31:0] mem [0:1023]; // @[cmd3.sc 13:16]\n", + " wire [31:0] mem_MPORT_data; // @[cmd3.sc 13:16]\n", + " wire [9:0] mem_MPORT_addr; // @[cmd3.sc 13:16]\n", + " wire [31:0] mem_MPORT_1_data; // @[cmd3.sc 13:16]\n", + " wire [9:0] mem_MPORT_1_addr; // @[cmd3.sc 13:16]\n", + " wire [31:0] mem_MPORT_2_data; // @[cmd3.sc 13:16]\n", + " wire [9:0] mem_MPORT_2_addr; // @[cmd3.sc 13:16]\n", + " wire [31:0] mem_MPORT_3_data; // @[cmd3.sc 13:16]\n", + " wire [9:0] mem_MPORT_3_addr; // @[cmd3.sc 13:16]\n", + " wire mem_MPORT_3_mask; // @[cmd3.sc 13:16]\n", + " wire mem_MPORT_3_en; // @[cmd3.sc 13:16]\n", + " wire [7:0] address = io_mem_aluresult[9:2]; // @[cmd3.sc 15:33]\n", + " wire _T_1 = io_mem_funct3 == 3'h0; // @[cmd3.sc 23:24]\n", + " wire [23:0] _T_4 = mem_MPORT_data[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]\n", + " wire [31:0] _T_6 = {_T_4,mem_MPORT_data[7:0]}; // @[Cat.scala 30:58]\n", + " wire _T_7 = io_mem_funct3 == 3'h1; // @[cmd3.sc 25:30]\n", + " wire [15:0] _T_10 = mem_MPORT_data[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]\n", + " wire [31:0] _T_12 = {_T_10,mem_MPORT_data[15:0]}; // @[Cat.scala 30:58]\n", + " wire _T_13 = io_mem_funct3 == 3'h2; // @[cmd3.sc 27:30]\n", + " wire [31:0] _T_16 = {24'h0,mem_MPORT_data[7:0]}; // @[Cat.scala 30:58]\n", + " wire [31:0] _T_19 = {16'h0,mem_MPORT_data[15:0]}; // @[Cat.scala 30:58]\n", + " wire [31:0] _GEN_0 = io_mem_funct3 == 3'h5 ? _T_19 : 32'h0; // @[cmd3.sc 31:44 cmd3.sc 32:14 cmd3.sc 34:14]\n", + " wire [31:0] _GEN_1 = io_mem_funct3 == 3'h4 ? _T_16 : _GEN_0; // @[cmd3.sc 29:44 cmd3.sc 30:14]\n", + " wire [31:0] _GEN_2 = io_mem_funct3 == 3'h2 ? mem_MPORT_data : _GEN_1; // @[cmd3.sc 27:44 cmd3.sc 28:14]\n", + " wire [31:0] _GEN_3 = io_mem_funct3 == 3'h1 ? _T_12 : _GEN_2; // @[cmd3.sc 25:44 cmd3.sc 26:14]\n", + " wire [31:0] _GEN_4 = io_mem_funct3 == 3'h0 ? _T_6 : _GEN_3; // @[cmd3.sc 23:38 cmd3.sc 24:14]\n", + " wire [31:0] _T_24 = {mem_MPORT_1_data[31:8],io_mem_rs2_data[7:0]}; // @[Cat.scala 30:58]\n", + " wire [31:0] _T_28 = {mem_MPORT_2_data[31:16],io_mem_rs2_data[15:0]}; // @[Cat.scala 30:58]\n", + " wire [31:0] _GEN_5 = _T_13 ? io_mem_rs2_data : 32'h0; // @[cmd3.sc 49:46 cmd3.sc 51:19 cmd3.sc 53:19]\n", + " wire [31:0] _GEN_9 = _T_7 ? _T_28 : _GEN_5; // @[cmd3.sc 46:46 cmd3.sc 48:19]\n", + " wire _GEN_16 = _T_1 ? 1'h0 : _T_7; // @[cmd3.sc 43:40 cmd3.sc 13:16]\n", + " wire _GEN_19 = io_mem_memwrite & _T_1; // @[cmd3.sc 40:35 cmd3.sc 13:16]\n", + " wire _GEN_22 = io_mem_memwrite & _GEN_16; // @[cmd3.sc 40:35 cmd3.sc 13:16]\n", + " assign mem_MPORT_addr = {{2'd0}, address};\n", + " assign mem_MPORT_data = mem[mem_MPORT_addr]; // @[cmd3.sc 13:16]\n", + " assign mem_MPORT_1_addr = {{2'd0}, address};\n", + " assign mem_MPORT_1_data = mem[mem_MPORT_1_addr]; // @[cmd3.sc 13:16]\n", + " assign mem_MPORT_2_addr = {{2'd0}, address};\n", + " assign mem_MPORT_2_data = mem[mem_MPORT_2_addr]; // @[cmd3.sc 13:16]\n", + " assign mem_MPORT_3_data = _T_1 ? _T_24 : _GEN_9;\n", + " assign mem_MPORT_3_addr = {{2'd0}, address};\n", + " assign mem_MPORT_3_mask = 1'h1;\n", + " assign mem_MPORT_3_en = io_mem_memread ? 1'h0 : io_mem_memwrite;\n", + " assign io_read_data = io_mem_memread ? _GEN_4 : 32'h0; // @[cmd3.sc 17:32 cmd3.sc 37:18 cmd3.sc 59:18]\n", + " always @(posedge clock) begin\n", + " if(mem_MPORT_3_en & mem_MPORT_3_mask) begin\n", + " mem[mem_MPORT_3_addr] <= mem_MPORT_3_data; // @[cmd3.sc 13:16]\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " _RAND_0 = {1{`RANDOM}};\n", + " for (initvar = 0; initvar < 1024; initvar = initvar+1)\n", + " mem[initvar] = _RAND_0[31:0];\n", + "`endif // RANDOMIZE_MEM_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "23d89e9a-16eb-4462-8dfa-fd999ea6828f", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "23d89e9a-16eb-4462-8dfa-fd999ea6828f", + "outputId": "707a0574-b026-4bb4-b583-8584e75abd86" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Writing DataCache_tb.v\n" + ] + } + ], + "source": [ + "%%writefile DataCache_tb.v\n", + "`timescale 1ns/1ns\n", + "module DataCache_tb();\n", + "reg clock;\n", + "reg reset;\n", + "reg [31:0] io_mem_aluresult;\n", + "reg [31:0] io_mem_rs2_data;\n", + "reg io_mem_memread;\n", + "reg [2:0] io_mem_funct3;\n", + "reg io_mem_memwrite;\n", + "wire [31:0] io_read_data;\n", + "\n", + "DataCache DataCache0(\n", + ".clock(clock),\n", + ".reset(reset),\n", + ".io_mem_aluresult(io_mem_aluresult),\n", + ".io_mem_rs2_data(io_mem_rs2_data),\n", + ".io_mem_memread(io_mem_memread),\n", + ".io_mem_funct3(io_mem_funct3),\n", + ".io_mem_memwrite(io_mem_memwrite),\n", + ".io_read_data(io_read_data)\n", + ");\n", + "\n", + "initial begin\n", + "clock=1'b0;\n", + "reset=1'b0;\n", + "io_mem_aluresult=32'h00000000;\n", + "io_mem_rs2_data=32'h00000000;\n", + "io_mem_memread=1'b0;\n", + "io_mem_funct3=3'b000;\n", + "io_mem_memwrite=1'b1;\n", + "end\n", + "\n", + "initial begin\n", + "forever #5 clock=~clock;\n", + "end\n", + "\n", + "initial begin\n", + "forever begin\n", + "#10 io_mem_aluresult=32'h00000123; io_mem_rs2_data=32'h01234567;\n", + "#10 io_mem_aluresult=32'h00001234; io_mem_rs2_data=32'h12345678;\n", + "#10 io_mem_aluresult=32'h00002345; io_mem_rs2_data=32'h23456789;\n", + "#10 io_mem_aluresult=32'h00003456; io_mem_rs2_data=32'h3456789a;\n", + "#10 io_mem_aluresult=32'h00004567; io_mem_rs2_data=32'h456789ab;\n", + "end\n", + "end\n", + "\n", + "initial begin\n", + "#10;\n", + "forever begin\n", + "#50 io_mem_memwrite=1'b0;io_mem_memread=1'b1;\n", + "#50 io_mem_memwrite=1'b1;io_mem_memread=1'b0;\n", + "end\n", + "end\n", + "\n", + "initial begin\n", + "#10 ;\n", + "#100 io_mem_funct3=3'b001;\n", + "#100 io_mem_funct3=3'b010;\n", + "#100 io_mem_funct3=3'b010;\n", + "#50 io_mem_funct3=3'b100;\n", + "#50 io_mem_funct3=3'b010;\n", + "#50 io_mem_funct3=3'b101;\n", + "end\n", + "\n", + "initial begin//finish\n", + "\t#510 $finish;\n", + "end\n", + "endmodule" + ] + }, + { + "cell_type": "code", + "source": [ + "%%writefile sim_main.cpp\n", + "#include \n", + "#include \n", + "#include \"VDataCache_tb.h\"\n", + "\n", + "int main(int argc, char** argv){\n", + "//\n", + " VerilatedContext* m_contextp = new VerilatedContext;//\n", + " VerilatedVcdC* m_tracep = new VerilatedVcdC;//\n", + " VDataCache_tb* m_duvp = new VDataCache_tb;//\n", + "//波形配置\n", + " m_contextp->traceEverOn(true);\n", + " m_duvp->trace(m_tracep,3);\n", + "m_tracep->open(\"datacache_wf.vcd\");//打开要存数据的vcd文件\n", + "//写入数据到波形文件里\n", + " while (!m_contextp->gotFinish()){\n", + " //刷新电路状态\n", + " m_duvp->eval();\n", + " //dump数据\n", + " m_tracep->dump(m_contextp->time());\n", + " //增加仿真时间\n", + " m_contextp->timeInc(1);\n", + " }\n", + "//记得关闭trace对象以保存文件里的数据\n", + " m_tracep->close();\n", + "//释放内存\n", + " delete m_duvp;\n", + " return 0;\n", + "}\n" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "jMA7gjefE5BK", + "outputId": "ed74efe9-9c36-4bd4-fc0f-e905223e03c6" + }, + "id": "jMA7gjefE5BK", + "execution_count": null, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Overwriting sim_main.cpp\n" + ] + } + ] + }, + { + "cell_type": "markdown", + "id": "f86f6a1c-11df-476b-ac10-bc642cda77d5", + "metadata": { + "id": "f86f6a1c-11df-476b-ac10-bc642cda77d5" + }, + "source": [ + "#### Simulation" + ] + }, + { + "cell_type": "code", + "source": [ + "!pwd" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "cb0O8OuLRZWT", + "outputId": "cd48f7b3-1b9f-4708-ae57-9c0e4f075fa7" + }, + "id": "cb0O8OuLRZWT", + "execution_count": null, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "/content/verilator\n" + ] + } + ] + }, + { + "cell_type": "code", + "source": [ + "!verilator -Wno-fatal --cc DataCache_tb.v DataCache.v --exe sim_main.cpp --trace" + ], + "metadata": { + "id": "gYHHiSLhN_d9" + }, + "id": "gYHHiSLhN_d9", + "execution_count": null, + "outputs": [] + }, + { + "cell_type": "code", + "source": [ + "!make -j -C obj_dir -f VDataCache_tb.mk VDataCache_tb" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "fqx2AMQ4OY6l", + "outputId": "35b3e125-b7b8-4fd6-ddf2-c7877abcee14" + }, + "id": "fqx2AMQ4OY6l", + "execution_count": null, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "make: Entering directory '/content/verilator/obj_dir'\n", + "ccache g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++17 -Os -c -o sim_main.o ../sim_main.cpp\n", + "ccache g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++17 -Os -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp\n", + "ccache g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++17 -Os -c -o verilated_vcd_c.o /usr/local/share/verilator/include/verilated_vcd_c.cpp\n", + "/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VDataCache_tb.cpp VDataCache_tb___024root__DepSet_h2328711c__0.cpp VDataCache_tb__Trace__0.cpp VDataCache_tb___024root__Slow.cpp VDataCache_tb___024root__DepSet_h2328711c__0__Slow.cpp VDataCache_tb__Syms.cpp VDataCache_tb__Trace__0__Slow.cpp > VDataCache_tb__ALL.cpp\n", + "ccache g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++17 -Os -c -o VDataCache_tb__ALL.o VDataCache_tb__ALL.cpp\n", + "echo \"\" > VDataCache_tb__ALL.verilator_deplist.tmp\n", + "Archive ar -rcs VDataCache_tb__ALL.a VDataCache_tb__ALL.o\n", + "g++ sim_main.o verilated.o verilated_vcd_c.o VDataCache_tb__ALL.a -o VDataCache_tb\n", + "rm VDataCache_tb__ALL.verilator_deplist.tmp\n", + "make: Leaving directory '/content/verilator/obj_dir'\n" + ] + } + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "fc869a66-7a15-4ea1-9bec-9058116630c6", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "fc869a66-7a15-4ea1-9bec-9058116630c6", + "outputId": "88eb3c1f-36f2-45a4-dcc6-81107ae2edf6" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "- DataCache_tb.v:66: Verilog $finish\n", + "^C\n" + ] + } + ], + "source": [ + "!./obj_dir/VDataCache_tb" + ] + }, + { + "cell_type": "markdown", + "source": [ + "You can see the waveform file generated for the corresponding test in the directory." + ], + "metadata": { + "id": "Z2L52XuFR4lN" + }, + "id": "Z2L52XuFR4lN" + }, + { + "cell_type": "code", + "source": [ + "!ls datacache_wf.vcd" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "w-JhzXjvPBSn", + "outputId": "cf9979cb-8b50-4be8-a2bf-7b0ead3ff2eb" + }, + "id": "w-JhzXjvPBSn", + "execution_count": null, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "datacache_wf.vcd\n" + ] + } + ] + }, + { + "cell_type": "markdown", + "id": "cd306c44-40d5-4491-bff4-5997e7921854", + "metadata": { + "id": "cd306c44-40d5-4491-bff4-5997e7921854" + }, + "source": [ + "### D. Physical Hardening\n", + "We completed an end-to-end open-source physical implementation after verification. OpenLane and OpenLane2 were used for automated chip hardening from RTL to GDS, and OpenPDK Skywater 130nm is the technology node.\n", + "For OpenLane, we show the results and reports at: https://github.com/lyaniix/ChatChisel-core.\n", + "\n", + "For OpenLane2, below is the flow. *Please note that OpenLane2 is still under development, so some steps are not supported. We have provided feedback to the official team and proposed modification suggestions as an active participant in promoting the development of the open source ecosystem.*" + ] + }, + { + "cell_type": "markdown", + "id": "570a1dd2-be0d-491b-975a-ef4b46e130c8", + "metadata": { + "id": "570a1dd2-be0d-491b-975a-ef4b46e130c8" + }, + "source": [ + "#### Setup Nix\n", + "We will install OpenLane and its dependencies using Nix. We recommend using Google Colab to do this.If you're not in a Colab, this just sets the environment variables. You will need to install Nix and enable flakes on your own using the Determinate Systems Nix Installer." + ] + }, + { + "cell_type": "code", + "source": [ + "%cd /content" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "w0EzSL-lC2Zd", + "outputId": "c8885179-cc2f-4e37-f01f-39789d7e93e4" + }, + "id": "w0EzSL-lC2Zd", + "execution_count": null, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "/content\n" + ] + } + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "id": "QcixDz2ww3GZ", + "colab": { + "base_uri": "https://localhost:8080/" + }, + "outputId": "fb808f52-0051-4b15-f512-9adf284b9435" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + " % Total % Received % Xferd Average Speed Time Time Time Current\n", + " Dload Upload Total Spent Left Speed\n", + " 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0\n", + "100 4052 100 4052 0 0 8269 0 --:--:-- --:--:-- --:--:-- 96476\n", + "downloading Nix 2.21.1 binary tarball for x86_64-linux from 'https://releases.nixos.org/nix/nix-2.21.1/nix-2.21.1-x86_64-linux.tar.xz' to '/tmp/nix-binary-tarball-unpack.PTFSjEmL1F'...\n", + " % Total % Received % Xferd Average Speed Time Time Time Current\n", + " Dload Upload Total Spent Left Speed\n", + "100 21.8M 100 21.8M 0 0 24.9M 0 --:--:-- --:--:-- --:--:-- 24.9M\n", + "Note: a multi-user installation is possible. See https://nixos.org/manual/nix/stable/installation/installing-binary.html#multi-user-installation\n", + "\u001b[1;31mSwitching to the Multi-user Installer\u001b[0m\n", + "\u001b[32mWelcome to the Multi-User Nix Installation\n", + "\u001b[0m\n", + "This installation tool will set up your computer with the Nix package\n", + "manager. This will happen in a few stages:\n", + "\n", + "1. Make sure your computer doesn't already have Nix. If it does, I\n", + " will show you instructions on how to clean up your old install.\n", + "\n", + "2. Show you what I am going to install and where. Then I will ask\n", + " if you are ready to continue.\n", + "\n", + "3. Create the system users \u001b[34m(uids [30001..30032])\u001b[0m and groups \u001b[34m(gid 30000)\u001b[0m\n", + " that the Nix daemon uses to run builds. To create system users\n", + " in a different range, exit and run this tool again with\n", + " NIX_FIRST_BUILD_UID set.\n", + "\n", + "4. Perform the basic installation of the Nix files daemon.\n", + "\n", + "5. Configure your shell to import special Nix Profile files, so you\n", + " can use Nix.\n", + "\n", + "6. Start the Nix daemon.\n", + "\n", + "\u001b[32m\u001b[4;32mWould you like to see a more detailed list of what I will do?\n", + "\u001b[0mNo TTY, assuming you would say yes :)\n", + "\n", + "I will:\n", + "\n", + " - make sure your computer doesn't already have Nix files\n", + " (if it does, I will tell you how to clean them up.)\n", + " - create local users (see the list above for the users I'll make)\n", + " - create a local group (nixbld)\n", + " - install Nix in to /nix\n", + " - create a configuration file in /etc/nix\n", + " - set up the \"default profile\" by creating some Nix-related files in\n", + " /root\n", + " - back up /etc/bashrc to /etc/bashrc.backup-before-nix\n", + " - update /etc/bashrc to include some Nix configuration\n", + " - back up /etc/profile.d/nix.sh to /etc/profile.d/nix.sh.backup-before-nix\n", + " - update /etc/profile.d/nix.sh to include some Nix configuration\n", + " - back up /etc/zshrc to /etc/zshrc.backup-before-nix\n", + " - update /etc/zshrc to include some Nix configuration\n", + " - back up /etc/bash.bashrc to /etc/bash.bashrc.backup-before-nix\n", + " - update /etc/bash.bashrc to include some Nix configuration\n", + " - load and start a service (at /etc/systemd/system/nix-daemon.service\n", + " and /etc/systemd/system/nix-daemon.socket) for nix-daemon\n", + "\n", + "\u001b[32m\u001b[4;32mReady to continue?\n", + "\u001b[0mNo TTY, assuming you would say yes :)\n", + "\n", + "\u001b[32m~~> Checking for artifacts of previous installs\n", + "\u001b[0mBefore I try to install, I'll check for signs Nix already is or has\n", + "been installed on this system.\n", + "\n", + "\u001b[34m---- oh no! --------------------------------------------------------------------\n", + "\u001b[0m\u001b[31mI back up shell profile/rc scripts before I add Nix to them.\n", + "I need to back up /etc/bash.bashrc to /etc/bash.bashrc.backup-before-nix,\n", + "but the latter already exists.\n", + "\n", + "Here's how to clean up the old backup file:\n", + "\n", + "1. Back up (copy) /etc/bash.bashrc and /etc/bash.bashrc.backup-before-nix\n", + " to another location, just in case.\n", + "\n", + "2. Ensure /etc/bash.bashrc.backup-before-nix does not have anything\n", + " Nix-related in it. If it does, something is probably quite\n", + " wrong. Please open an issue or get in touch immediately.\n", + "\n", + "3. Once you confirm /etc/bash.bashrc is backed up and\n", + " /etc/bash.bashrc.backup-before-nix doesn't mention Nix, run:\n", + " mv /etc/bash.bashrc.backup-before-nix /etc/bash.bashrc\n", + "\u001b[0m\n", + "\u001b[31mWe'd love to help if you need it.\n", + "\n", + "You can open an issue at\n", + "https://github.com/NixOS/nix/issues/new?labels=installer&template=installer.md\n", + "\n", + "Or get in touch with the community: https://nixos.org/community\n", + "\u001b[0mnix-daemon: no process found\n" + ] + } + ], + "source": [ + "# @title Setup Nix {display-mode: \"form\"}\n", + "# @markdown \n", + "# @markdown\n", + "# @markdown Nix is a package manager with an emphasis on reproducible builds,\n", + "# @markdown and it is the primary method for installing OpenLane 2.\n", + "# @markdown\n", + "# @markdown This step installs the Nix package manager and enables the\n", + "# @markdown experimental \"flakes\" feature.\n", + "# @markdown\n", + "# @markdown If you're not in a Colab, this just sets the environment variables.\n", + "# @markdown You will need to install Nix and enable flakes on your own using\n", + "# @markdown the [Determinate Systems Nix Installer](https://github.com/DeterminateSystems/nix-installer).\n", + "import os\n", + "import sys\n", + "import shutil\n", + "\n", + "os.environ[\"LOCALE_ARCHIVE\"] = \"/usr/lib/locale/locale-archive\"\n", + "\n", + "if \"google.colab\" in sys.modules:\n", + " if shutil.which(\"nix-env\") is None:\n", + " !curl -L https://nixos.org/nix/install | bash -s -- --daemon --yes\n", + " !echo \"extra-experimental-features = nix-command flakes\" >> /etc/nix/nix.conf\n", + " !killall nix-daemon\n", + "else:\n", + " if shutil.which(\"nix-env\") is None:\n", + " raise RuntimeError(\"Nix is not installed!\")\n", + "\n", + "os.environ[\"PATH\"] = f\"/nix/var/nix/profiles/default/bin/:{os.getenv('PATH')}\"" + ], + "id": "QcixDz2ww3GZ" + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/", + "height": 320 + }, + "id": "yS2hAP0Bw3Ga", + "outputId": "2901db6b-2229-4d73-aac7-bb8074f7869f" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "text/html": [ + "

Downloading OpenLane…" + ] + }, + "metadata": {} + }, + { + "output_type": "stream", + "name": "stdout", + "text": [ + " % Total % Received % Xferd Average Speed Time Time Time Current\n", + " Dload Upload Total Spent Left Speed\n", + " 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0\n", + "100 13.3M 0 13.3M 0 0 15.3M 0 --:--:-- --:--:-- --:--:-- 15.3M\n" + ] + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "text/html": [ + "

Downloading OpenLane's dependencies…" + ] + }, + "metadata": {} + }, + { + "output_type": "stream", + "name": "stdout", + "text": [ + "\u001b[K\u001b[35;1mwarning:\u001b[0m 'colab-env' is already installed\u001b[0m\n", + "\u001b[K" + ] + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "text/html": [ + "

Downloading Python dependencies using PIP…" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "text/html": [ + "

Downloading PDK…" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [], + "text/html": [ + "
\n"
+            ]
+          },
+          "metadata": {}
+        },
+        {
+          "output_type": "display_data",
+          "data": {
+            "text/plain": [
+              "Version bdc9412b3e468c102d01b7cf6337be06ec6e9c9a enabled for the sky130 PDK.\n"
+            ],
+            "text/html": [
+              "
Version bdc9412b3e468c102d01b7cf6337be06ec6e9c9a enabled for the sky130 PDK.\n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "text/html": [ + "

⭕️ Done." + ] + }, + "metadata": {} + } + ], + "source": [ + "# @title Get OpenLane {display-mode: \"form\"}\n", + "# @markdown Click the ▷ button to download and install OpenLane.\n", + "# @markdown\n", + "# @markdown This will install OpenLane's tool dependencies using Nix,\n", + "# @markdown and OpenLane itself using PIP.\n", + "# @markdown\n", + "# @markdown Note that `python3-tk` may need to be installed using your OS's\n", + "# @markdown package manager.\n", + "import os\n", + "import subprocess\n", + "import IPython\n", + "\n", + "openlane_version = \"latest\" # @param {key:\"OpenLane Version\", type:\"string\"}\n", + "\n", + "if openlane_version == \"latest\":\n", + " openlane_version = \"main\"\n", + "\n", + "pdk_root = \"~/.volare\" # @param {key:\"PDK Root\", type:\"string\"}\n", + "\n", + "pdk_root = os.path.expanduser(pdk_root)\n", + "\n", + "pdk = \"sky130\" # @param {key:\"PDK (without the variant)\", type:\"string\"}\n", + "\n", + "openlane_ipynb_path = os.path.join(os.getcwd(), \"openlane_ipynb\")\n", + "\n", + "display(IPython.display.HTML(\"

Downloading OpenLane…\"))\n", + "\n", + "\n", + "TESTING_LOCALLY = False\n", + "!rm -rf {openlane_ipynb_path}\n", + "!mkdir -p {openlane_ipynb_path}\n", + "if TESTING_LOCALLY:\n", + " !ln -s {os.getcwd()} {openlane_ipynb_path}\n", + "else:\n", + " !curl -L \"https://github.com/efabless/openlane2/tarball/{openlane_version}\" | tar -xzC {openlane_ipynb_path} --strip-components 1\n", + "\n", + "try:\n", + " import tkinter\n", + "except ImportError:\n", + " if \"google.colab\" in sys.modules:\n", + " !sudo apt-get install python-tk\n", + "\n", + "try:\n", + " import tkinter\n", + "except ImportError as e:\n", + " display(\n", + " IPython.display.HTML(\n", + " '

❌ Failed to import the tkinter library for Python, which is required to load PDK configuration values. Make sure python3-tk or equivalent is installed on your system.'\n", + " )\n", + " )\n", + " raise e from None\n", + "\n", + "\n", + "display(IPython.display.HTML(\"

Downloading OpenLane's dependencies…\"))\n", + "\n", + "!cd {openlane_ipynb_path} && nix profile install \".#colab-env\" --accept-flake-config\n", + "\n", + "display(IPython.display.HTML(\"

Downloading Python dependencies using PIP…\"))\n", + "try:\n", + " subprocess.check_output(\n", + " [\n", + " \"pip3\",\n", + " \"install\",\n", + " \"-r\",\n", + " os.path.join(openlane_ipynb_path, \"requirements.txt\"),\n", + " ]\n", + " )\n", + "except subprocess.CalledProcessError as e:\n", + " display(\n", + " IPython.display.HTML(\n", + " '

❌ Failed to install Python dependencies using PIP…

'\n", + " )\n", + " )\n", + " raise e from None\n", + "\n", + "display(IPython.display.HTML(\"

Downloading PDK…\"))\n", + "import volare\n", + "\n", + "volare.enable(\n", + " volare.get_volare_home(pdk_root),\n", + " pdk,\n", + " open(\n", + " os.path.join(openlane_ipynb_path, \"openlane\", \"open_pdks_rev\"),\n", + " encoding=\"utf8\",\n", + " )\n", + " .read()\n", + " .strip(),\n", + ")\n", + "\n", + "sys.path.insert(0, openlane_ipynb_path)\n", + "display(IPython.display.HTML(\"

⭕️ Done.\"))\n", + "\n", + "import logging\n", + "\n", + "# Remove the stupid default colab logging handler\n", + "logging.getLogger().handlers.clear()" + ], + "id": "yS2hAP0Bw3Ga" + }, + { + "cell_type": "markdown", + "id": "0400d347-c256-4948-a9ea-6d1400e02310", + "metadata": { + "id": "0400d347-c256-4948-a9ea-6d1400e02310" + }, + "source": [ + "#### Creating the design\n", + "\n", + "Now that OpenLane is set up, we can write a Verilog file as follows:" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "93bc8f53-bc34-464a-ac07-44cc4f251b14", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "93bc8f53-bc34-464a-ac07-44cc4f251b14", + "outputId": "4742b032-1598-4d45-f2bc-c921ce77ada5" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Overwriting core.v\n" + ] + } + ], + "source": [ + "%%writefile core.v\n", + "module BHT(\n", + " input clock,\n", + " input [31:0] io_pc,\n", + " input [31:0] io_mem_pc,\n", + " input io_pcsrc,\n", + " input [31:0] io_target_pc,\n", + " output io_match,\n", + " output io_valid,\n", + " output [31:0] io_bht_pred_pc\n", + ");\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " reg [31:0] _RAND_0;\n", + " reg [31:0] _RAND_1;\n", + " reg [31:0] _RAND_2;\n", + "`endif // RANDOMIZE_MEM_INIT\n", + " reg [25:0] bhtTable_tag [0:15]; // @[bht.scala 24:21]\n", + " wire bhtTable_tag_bhtEntry_en; // @[bht.scala 24:21]\n", + " wire [3:0] bhtTable_tag_bhtEntry_addr; // @[bht.scala 24:21]\n", + " wire [25:0] bhtTable_tag_bhtEntry_data; // @[bht.scala 24:21]\n", + " wire [25:0] bhtTable_tag_MPORT_data; // @[bht.scala 24:21]\n", + " wire [3:0] bhtTable_tag_MPORT_addr; // @[bht.scala 24:21]\n", + " wire bhtTable_tag_MPORT_mask; // @[bht.scala 24:21]\n", + " wire bhtTable_tag_MPORT_en; // @[bht.scala 24:21]\n", + " reg bhtTable_valid [0:15]; // @[bht.scala 24:21]\n", + " wire bhtTable_valid_bhtEntry_en; // @[bht.scala 24:21]\n", + " wire [3:0] bhtTable_valid_bhtEntry_addr; // @[bht.scala 24:21]\n", + " wire bhtTable_valid_bhtEntry_data; // @[bht.scala 24:21]\n", + " wire bhtTable_valid_MPORT_data; // @[bht.scala 24:21]\n", + " wire [3:0] bhtTable_valid_MPORT_addr; // @[bht.scala 24:21]\n", + " wire bhtTable_valid_MPORT_mask; // @[bht.scala 24:21]\n", + " wire bhtTable_valid_MPORT_en; // @[bht.scala 24:21]\n", + " reg [31:0] bhtTable_target_pc [0:15]; // @[bht.scala 24:21]\n", + " wire bhtTable_target_pc_bhtEntry_en; // @[bht.scala 24:21]\n", + " wire [3:0] bhtTable_target_pc_bhtEntry_addr; // @[bht.scala 24:21]\n", + " wire [31:0] bhtTable_target_pc_bhtEntry_data; // @[bht.scala 24:21]\n", + " wire [31:0] bhtTable_target_pc_MPORT_data; // @[bht.scala 24:21]\n", + " wire [3:0] bhtTable_target_pc_MPORT_addr; // @[bht.scala 24:21]\n", + " wire bhtTable_target_pc_MPORT_mask; // @[bht.scala 24:21]\n", + " wire bhtTable_target_pc_MPORT_en; // @[bht.scala 24:21]\n", + " assign bhtTable_tag_bhtEntry_en = 1'h1;\n", + " assign bhtTable_tag_bhtEntry_addr = io_pc[5:2];\n", + " assign bhtTable_tag_bhtEntry_data = bhtTable_tag[bhtTable_tag_bhtEntry_addr]; // @[bht.scala 24:21]\n", + " assign bhtTable_tag_MPORT_data = io_mem_pc[31:6];\n", + " assign bhtTable_tag_MPORT_addr = io_mem_pc[5:2];\n", + " assign bhtTable_tag_MPORT_mask = 1'h1;\n", + " assign bhtTable_tag_MPORT_en = io_pcsrc;\n", + " assign bhtTable_valid_bhtEntry_en = 1'h1;\n", + " assign bhtTable_valid_bhtEntry_addr = io_pc[5:2];\n", + " assign bhtTable_valid_bhtEntry_data = bhtTable_valid[bhtTable_valid_bhtEntry_addr]; // @[bht.scala 24:21]\n", + " assign bhtTable_valid_MPORT_data = 1'h1;\n", + " assign bhtTable_valid_MPORT_addr = io_mem_pc[5:2];\n", + " assign bhtTable_valid_MPORT_mask = 1'h1;\n", + " assign bhtTable_valid_MPORT_en = io_pcsrc;\n", + " assign bhtTable_target_pc_bhtEntry_en = 1'h1;\n", + " assign bhtTable_target_pc_bhtEntry_addr = io_pc[5:2];\n", + " assign bhtTable_target_pc_bhtEntry_data = bhtTable_target_pc[bhtTable_target_pc_bhtEntry_addr]; // @[bht.scala 24:21]\n", + " assign bhtTable_target_pc_MPORT_data = io_target_pc;\n", + " assign bhtTable_target_pc_MPORT_addr = io_mem_pc[5:2];\n", + " assign bhtTable_target_pc_MPORT_mask = 1'h1;\n", + " assign bhtTable_target_pc_MPORT_en = io_pcsrc;\n", + " assign io_match = bhtTable_tag_bhtEntry_data == io_pc[31:6]; // @[bht.scala 30:30]\n", + " assign io_valid = bhtTable_valid_bhtEntry_data; // @[bht.scala 31:12]\n", + " assign io_bht_pred_pc = bhtTable_target_pc_bhtEntry_data; // @[bht.scala 32:18]\n", + " always @(posedge clock) begin\n", + " if (bhtTable_tag_MPORT_en & bhtTable_tag_MPORT_mask) begin\n", + " bhtTable_tag[bhtTable_tag_MPORT_addr] <= bhtTable_tag_MPORT_data; // @[bht.scala 24:21]\n", + " end\n", + " if (bhtTable_valid_MPORT_en & bhtTable_valid_MPORT_mask) begin\n", + " bhtTable_valid[bhtTable_valid_MPORT_addr] <= bhtTable_valid_MPORT_data; // @[bht.scala 24:21]\n", + " end\n", + " if (bhtTable_target_pc_MPORT_en & bhtTable_target_pc_MPORT_mask) begin\n", + " bhtTable_target_pc[bhtTable_target_pc_MPORT_addr] <= bhtTable_target_pc_MPORT_data; // @[bht.scala 24:21]\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " _RAND_0 = {1{`RANDOM}};\n", + " for (initvar = 0; initvar < 16; initvar = initvar+1)\n", + " bhtTable_tag[initvar] = _RAND_0[25:0];\n", + " _RAND_1 = {1{`RANDOM}};\n", + " for (initvar = 0; initvar < 16; initvar = initvar+1)\n", + " bhtTable_valid[initvar] = _RAND_1[0:0];\n", + " _RAND_2 = {1{`RANDOM}};\n", + " for (initvar = 0; initvar < 16; initvar = initvar+1)\n", + " bhtTable_target_pc[initvar] = _RAND_2[31:0];\n", + "`endif // RANDOMIZE_MEM_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n", + "module BTB(\n", + " input clock,\n", + " input [31:0] io_pc,\n", + " input [31:0] io_mem_pc,\n", + " input io_pcsrc,\n", + " input io_branch,\n", + " output io_btb_taken\n", + ");\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " reg [31:0] _RAND_0;\n", + "`endif // RANDOMIZE_MEM_INIT\n", + " reg [1:0] btbTable [0:15]; // @[btb.scala 14:21]\n", + " wire btbTable_btbEntry_en; // @[btb.scala 14:21]\n", + " wire [3:0] btbTable_btbEntry_addr; // @[btb.scala 14:21]\n", + " wire [1:0] btbTable_btbEntry_data; // @[btb.scala 14:21]\n", + " wire btbTable_MPORT_en; // @[btb.scala 14:21]\n", + " wire [3:0] btbTable_MPORT_addr; // @[btb.scala 14:21]\n", + " wire [1:0] btbTable_MPORT_data; // @[btb.scala 14:21]\n", + " wire btbTable_MPORT_1_en; // @[btb.scala 14:21]\n", + " wire [3:0] btbTable_MPORT_1_addr; // @[btb.scala 14:21]\n", + " wire [1:0] btbTable_MPORT_1_data; // @[btb.scala 14:21]\n", + " wire btbTable_MPORT_3_en; // @[btb.scala 14:21]\n", + " wire [3:0] btbTable_MPORT_3_addr; // @[btb.scala 14:21]\n", + " wire [1:0] btbTable_MPORT_3_data; // @[btb.scala 14:21]\n", + " wire btbTable_MPORT_4_en; // @[btb.scala 14:21]\n", + " wire [3:0] btbTable_MPORT_4_addr; // @[btb.scala 14:21]\n", + " wire [1:0] btbTable_MPORT_4_data; // @[btb.scala 14:21]\n", + " wire [1:0] btbTable_MPORT_2_data; // @[btb.scala 14:21]\n", + " wire [3:0] btbTable_MPORT_2_addr; // @[btb.scala 14:21]\n", + " wire btbTable_MPORT_2_mask; // @[btb.scala 14:21]\n", + " wire btbTable_MPORT_2_en; // @[btb.scala 14:21]\n", + " wire [1:0] btbTable_MPORT_5_data; // @[btb.scala 14:21]\n", + " wire [3:0] btbTable_MPORT_5_addr; // @[btb.scala 14:21]\n", + " wire btbTable_MPORT_5_mask; // @[btb.scala 14:21]\n", + " wire btbTable_MPORT_5_en; // @[btb.scala 14:21]\n", + " wire _T_3 = btbTable_MPORT_data < 2'h3; // @[btb.scala 26:38]\n", + " wire _T_9 = btbTable_MPORT_3_data > 2'h0; // @[btb.scala 31:38]\n", + " wire _GEN_17 = io_pcsrc & _T_3; // @[btb.scala 14:21 24:28]\n", + " wire _GEN_23 = io_pcsrc ? 1'h0 : 1'h1; // @[btb.scala 14:21 24:28 31:20]\n", + " wire _GEN_26 = io_pcsrc ? 1'h0 : _T_9; // @[btb.scala 14:21 24:28]\n", + " assign btbTable_btbEntry_en = 1'h1;\n", + " assign btbTable_btbEntry_addr = io_pc[5:2];\n", + " assign btbTable_btbEntry_data = btbTable[btbTable_btbEntry_addr]; // @[btb.scala 14:21]\n", + " assign btbTable_MPORT_en = io_branch & io_pcsrc;\n", + " assign btbTable_MPORT_addr = io_mem_pc[5:2];\n", + " assign btbTable_MPORT_data = btbTable[btbTable_MPORT_addr]; // @[btb.scala 14:21]\n", + " assign btbTable_MPORT_1_en = io_branch & _GEN_17;\n", + " assign btbTable_MPORT_1_addr = io_mem_pc[5:2];\n", + " assign btbTable_MPORT_1_data = btbTable[btbTable_MPORT_1_addr]; // @[btb.scala 14:21]\n", + " assign btbTable_MPORT_3_en = io_branch & _GEN_23;\n", + " assign btbTable_MPORT_3_addr = io_mem_pc[5:2];\n", + " assign btbTable_MPORT_3_data = btbTable[btbTable_MPORT_3_addr]; // @[btb.scala 14:21]\n", + " assign btbTable_MPORT_4_en = io_branch & _GEN_26;\n", + " assign btbTable_MPORT_4_addr = io_mem_pc[5:2];\n", + " assign btbTable_MPORT_4_data = btbTable[btbTable_MPORT_4_addr]; // @[btb.scala 14:21]\n", + " assign btbTable_MPORT_2_data = btbTable_MPORT_1_data + 2'h1;\n", + " assign btbTable_MPORT_2_addr = io_mem_pc[5:2];\n", + " assign btbTable_MPORT_2_mask = 1'h1;\n", + " assign btbTable_MPORT_2_en = io_branch & _GEN_17;\n", + " assign btbTable_MPORT_5_data = btbTable_MPORT_4_data - 2'h1;\n", + " assign btbTable_MPORT_5_addr = io_mem_pc[5:2];\n", + " assign btbTable_MPORT_5_mask = 1'h1;\n", + " assign btbTable_MPORT_5_en = io_branch & _GEN_26;\n", + " assign io_btb_taken = btbTable_btbEntry_data[1]; // @[btb.scala 20:28]\n", + " always @(posedge clock) begin\n", + " if (btbTable_MPORT_2_en & btbTable_MPORT_2_mask) begin\n", + " btbTable[btbTable_MPORT_2_addr] <= btbTable_MPORT_2_data; // @[btb.scala 14:21]\n", + " end\n", + " if (btbTable_MPORT_5_en & btbTable_MPORT_5_mask) begin\n", + " btbTable[btbTable_MPORT_5_addr] <= btbTable_MPORT_5_data; // @[btb.scala 14:21]\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " _RAND_0 = {1{`RANDOM}};\n", + " for (initvar = 0; initvar < 16; initvar = initvar+1)\n", + " btbTable[initvar] = _RAND_0[1:0];\n", + "`endif // RANDOMIZE_MEM_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n", + "module Fetch(\n", + " input clock,\n", + " input reset,\n", + " input [31:0] io_trap_vector,\n", + " input [31:0] io_mret_vector,\n", + " input [31:0] io_target_pc,\n", + " input [31:0] io_mem_pc,\n", + " input io_pcsrc,\n", + " input io_branch,\n", + " input io_trap,\n", + " input io_mret,\n", + " input io_pc_stall,\n", + " input io_if_id_stall,\n", + " input io_if_id_flush,\n", + " input io_predict,\n", + " output [31:0] io_id_pc,\n", + " output [31:0] io_inst,\n", + " input [31:0] io_fetch_data,\n", + " output [31:0] io_fetch_address\n", + ");\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " reg [31:0] _RAND_0;\n", + " reg [31:0] _RAND_1;\n", + " reg [31:0] _RAND_2;\n", + "`endif // RANDOMIZE_REG_INIT\n", + " wire bht_clock; // @[fetch.scala 32:19]\n", + " wire [31:0] bht_io_pc; // @[fetch.scala 32:19]\n", + " wire [31:0] bht_io_mem_pc; // @[fetch.scala 32:19]\n", + " wire bht_io_pcsrc; // @[fetch.scala 32:19]\n", + " wire [31:0] bht_io_target_pc; // @[fetch.scala 32:19]\n", + " wire bht_io_match; // @[fetch.scala 32:19]\n", + " wire bht_io_valid; // @[fetch.scala 32:19]\n", + " wire [31:0] bht_io_bht_pred_pc; // @[fetch.scala 32:19]\n", + " wire btb_clock; // @[fetch.scala 33:19]\n", + " wire [31:0] btb_io_pc; // @[fetch.scala 33:19]\n", + " wire [31:0] btb_io_mem_pc; // @[fetch.scala 33:19]\n", + " wire btb_io_pcsrc; // @[fetch.scala 33:19]\n", + " wire btb_io_branch; // @[fetch.scala 33:19]\n", + " wire btb_io_btb_taken; // @[fetch.scala 33:19]\n", + " reg [31:0] pcReg; // @[fetch.scala 36:22]\n", + " reg [31:0] idPcReg; // @[fetch.scala 37:24]\n", + " reg [31:0] instReg; // @[fetch.scala 38:24]\n", + " wire [31:0] _pcReg_T_1 = pcReg + 32'h4; // @[fetch.scala 65:20]\n", + " wire [31:0] _GEN_0 = btb_io_btb_taken & bht_io_valid & bht_io_match ? bht_io_bht_pred_pc : _pcReg_T_1; // @[fetch.scala 62:74 63:11 65:11]\n", + " wire [31:0] _GEN_1 = io_pc_stall ? pcReg : _GEN_0; // @[fetch.scala 60:27 61:11]\n", + " BHT bht ( // @[fetch.scala 32:19]\n", + " .clock(bht_clock),\n", + " .io_pc(bht_io_pc),\n", + " .io_mem_pc(bht_io_mem_pc),\n", + " .io_pcsrc(bht_io_pcsrc),\n", + " .io_target_pc(bht_io_target_pc),\n", + " .io_match(bht_io_match),\n", + " .io_valid(bht_io_valid),\n", + " .io_bht_pred_pc(bht_io_bht_pred_pc)\n", + " );\n", + " BTB btb ( // @[fetch.scala 33:19]\n", + " .clock(btb_clock),\n", + " .io_pc(btb_io_pc),\n", + " .io_mem_pc(btb_io_mem_pc),\n", + " .io_pcsrc(btb_io_pcsrc),\n", + " .io_branch(btb_io_branch),\n", + " .io_btb_taken(btb_io_btb_taken)\n", + " );\n", + " assign io_id_pc = idPcReg; // @[fetch.scala 83:12]\n", + " assign io_inst = instReg; // @[fetch.scala 84:11]\n", + " assign io_fetch_address = pcReg; // @[fetch.scala 82:20]\n", + " assign bht_clock = clock;\n", + " assign bht_io_pc = pcReg; // @[fetch.scala 41:13]\n", + " assign bht_io_mem_pc = io_mem_pc; // @[fetch.scala 42:17]\n", + " assign bht_io_pcsrc = io_pcsrc; // @[fetch.scala 43:16]\n", + " assign bht_io_target_pc = io_target_pc; // @[fetch.scala 44:20]\n", + " assign btb_clock = clock;\n", + " assign btb_io_pc = pcReg; // @[fetch.scala 46:13]\n", + " assign btb_io_mem_pc = io_mem_pc; // @[fetch.scala 47:17]\n", + " assign btb_io_pcsrc = io_pcsrc; // @[fetch.scala 48:16]\n", + " assign btb_io_branch = io_branch; // @[fetch.scala 49:17]\n", + " always @(posedge clock) begin\n", + " if (reset) begin // @[fetch.scala 36:22]\n", + " pcReg <= 32'h8; // @[fetch.scala 36:22]\n", + " end else if (io_trap) begin // @[fetch.scala 54:17]\n", + " pcReg <= io_trap_vector; // @[fetch.scala 55:11]\n", + " end else if (io_mret) begin // @[fetch.scala 56:23]\n", + " pcReg <= io_mret_vector; // @[fetch.scala 57:11]\n", + " end else if (io_pcsrc & ~io_predict) begin // @[fetch.scala 58:39]\n", + " pcReg <= io_target_pc; // @[fetch.scala 59:11]\n", + " end else begin\n", + " pcReg <= _GEN_1;\n", + " end\n", + " if (reset) begin // @[fetch.scala 37:24]\n", + " idPcReg <= 32'h0; // @[fetch.scala 37:24]\n", + " end else if (io_if_id_flush) begin // @[fetch.scala 77:24]\n", + " idPcReg <= 32'h0; // @[fetch.scala 78:13]\n", + " end else if (!(io_if_id_stall)) begin // @[fetch.scala 69:24]\n", + " idPcReg <= pcReg; // @[fetch.scala 73:13]\n", + " end\n", + " if (reset) begin // @[fetch.scala 38:24]\n", + " instReg <= 32'h0; // @[fetch.scala 38:24]\n", + " end else if (io_if_id_flush) begin // @[fetch.scala 77:24]\n", + " instReg <= 32'h13; // @[fetch.scala 79:13]\n", + " end else if (!(io_if_id_stall)) begin // @[fetch.scala 69:24]\n", + " instReg <= io_fetch_data; // @[fetch.scala 74:13]\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " _RAND_0 = {1{`RANDOM}};\n", + " pcReg = _RAND_0[31:0];\n", + " _RAND_1 = {1{`RANDOM}};\n", + " idPcReg = _RAND_1[31:0];\n", + " _RAND_2 = {1{`RANDOM}};\n", + " instReg = _RAND_2[31:0];\n", + "`endif // RANDOMIZE_REG_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n", + "module Control(\n", + " input [6:0] io_opcode,\n", + " input [6:0] io_funct7,\n", + " input [2:0] io_funct3,\n", + " output [3:0] io_aluop,\n", + " output io_immsrc,\n", + " output io_isbranch,\n", + " output io_memread,\n", + " output io_memwrite,\n", + " output io_regwrite,\n", + " output [1:0] io_memtoreg,\n", + " output io_pcsel,\n", + " output io_rdsel,\n", + " output io_isjump,\n", + " output io_islui,\n", + " output io_use_rs1,\n", + " output io_use_rs2\n", + ");\n", + " wire [1:0] _io_aluop_T_5 = 7'h4 == io_funct7 ? 2'h2 : {{1'd0}, 7'h20 == io_funct7}; // @[Mux.scala 81:58]\n", + " wire [2:0] _io_aluop_T_9 = 7'h20 == io_funct7 ? 3'h7 : 3'h6; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_aluop_T_11 = 3'h0 == io_funct3 ? _io_aluop_T_5 : 2'h0; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_aluop_T_13 = 3'h6 == io_funct3 ? 2'h3 : _io_aluop_T_11; // @[Mux.scala 81:58]\n", + " wire [2:0] _io_aluop_T_15 = 3'h7 == io_funct3 ? 3'h4 : {{1'd0}, _io_aluop_T_13}; // @[Mux.scala 81:58]\n", + " wire [2:0] _io_aluop_T_17 = 3'h1 == io_funct3 ? 3'h5 : _io_aluop_T_15; // @[Mux.scala 81:58]\n", + " wire [2:0] _io_aluop_T_19 = 3'h5 == io_funct3 ? _io_aluop_T_9 : _io_aluop_T_17; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_21 = 3'h2 == io_funct3 ? 4'h8 : {{1'd0}, _io_aluop_T_19}; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_23 = 3'h3 == io_funct3 ? 4'h9 : _io_aluop_T_21; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_aluop_T_29 = 3'h4 == io_funct3 ? 2'h2 : 2'h0; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_aluop_T_31 = 3'h6 == io_funct3 ? 2'h3 : _io_aluop_T_29; // @[Mux.scala 81:58]\n", + " wire [2:0] _io_aluop_T_33 = 3'h7 == io_funct3 ? 3'h4 : {{1'd0}, _io_aluop_T_31}; // @[Mux.scala 81:58]\n", + " wire [2:0] _io_aluop_T_35 = 3'h1 == io_funct3 ? 3'h5 : _io_aluop_T_33; // @[Mux.scala 81:58]\n", + " wire [2:0] _io_aluop_T_37 = 3'h5 == io_funct3 ? _io_aluop_T_9 : _io_aluop_T_35; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_39 = 3'h2 == io_funct3 ? 4'h8 : {{1'd0}, _io_aluop_T_37}; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_41 = 3'h3 == io_funct3 ? 4'h9 : _io_aluop_T_39; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_51 = 3'h6 == io_funct3 ? 4'h9 : 4'h8; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_53 = 3'h7 == io_funct3 ? 4'h9 : _io_aluop_T_51; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_55 = 7'h33 == io_opcode ? _io_aluop_T_23 : 4'h0; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_57 = 7'h13 == io_opcode ? _io_aluop_T_41 : _io_aluop_T_55; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_59 = 7'h3 == io_opcode ? 4'h0 : _io_aluop_T_57; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_61 = 7'h23 == io_opcode ? 4'h0 : _io_aluop_T_59; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_63 = 7'h63 == io_opcode ? _io_aluop_T_53 : _io_aluop_T_61; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_65 = 7'h6f == io_opcode ? 4'h0 : _io_aluop_T_63; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_67 = 7'h67 == io_opcode ? 4'h0 : _io_aluop_T_65; // @[Mux.scala 81:58]\n", + " wire [3:0] _io_aluop_T_69 = 7'h37 == io_opcode ? 4'h0 : _io_aluop_T_67; // @[Mux.scala 81:58]\n", + " wire _io_immsrc_T_23 = 7'h63 == io_opcode ? 1'h0 : 7'h23 == io_opcode | (7'h3 == io_opcode | 7'h13 == io_opcode); // @[Mux.scala 81:58]\n", + " wire _io_regwrite_T_21 = 7'h23 == io_opcode ? 1'h0 : 7'h3 == io_opcode | (7'h13 == io_opcode | 7'h33 == io_opcode); // @[Mux.scala 81:58]\n", + " wire _io_regwrite_T_23 = 7'h63 == io_opcode ? 1'h0 : _io_regwrite_T_21; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_3 = 3'h1 == io_funct3 ? 2'h3 : 2'h0; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_5 = 3'h2 == io_funct3 ? 2'h3 : _io_memtoreg_T_3; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_7 = 3'h3 == io_funct3 ? 2'h3 : _io_memtoreg_T_5; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_9 = 3'h5 == io_funct3 ? 2'h3 : _io_memtoreg_T_7; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_11 = 3'h6 == io_funct3 ? 2'h3 : _io_memtoreg_T_9; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_13 = 3'h7 == io_funct3 ? 2'h3 : _io_memtoreg_T_11; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_15 = 7'h33 == io_opcode ? 2'h2 : 2'h0; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_17 = 7'h13 == io_opcode ? 2'h2 : _io_memtoreg_T_15; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_19 = 7'h3 == io_opcode ? 2'h1 : _io_memtoreg_T_17; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_21 = 7'h6f == io_opcode ? 2'h0 : _io_memtoreg_T_19; // @[Mux.scala 81:58]\n", + " wire [1:0] _io_memtoreg_T_23 = 7'h37 == io_opcode ? 2'h2 : _io_memtoreg_T_21; // @[Mux.scala 81:58]\n", + " wire _io_use_rs1_T_9 = 3'h5 == io_funct3 ? 1'h0 : 3'h3 == io_funct3 | (3'h2 == io_funct3 | 3'h1 == io_funct3); // @[Mux.scala 81:58]\n", + " wire _io_use_rs1_T_11 = 3'h6 == io_funct3 ? 1'h0 : _io_use_rs1_T_9; // @[Mux.scala 81:58]\n", + " wire _io_use_rs1_T_13 = 3'h7 == io_funct3 ? 1'h0 : _io_use_rs1_T_11; // @[Mux.scala 81:58]\n", + " wire _io_use_rs1_T_25 = 7'h6f == io_opcode ? 1'h0 : 7'h63 == io_opcode | (7'h23 == io_opcode | (7'h3 == io_opcode | (7'h13\n", + " == io_opcode | 7'h33 == io_opcode))); // @[Mux.scala 81:58]\n", + " wire _io_use_rs1_T_29 = 7'h37 == io_opcode ? 1'h0 : 7'h67 == io_opcode | _io_use_rs1_T_25; // @[Mux.scala 81:58]\n", + " wire _io_use_rs1_T_31 = 7'h17 == io_opcode ? 1'h0 : _io_use_rs1_T_29; // @[Mux.scala 81:58]\n", + " wire _io_use_rs2_T_17 = 7'h13 == io_opcode ? 1'h0 : 7'h33 == io_opcode; // @[Mux.scala 81:58]\n", + " wire _io_use_rs2_T_19 = 7'h3 == io_opcode ? 1'h0 : _io_use_rs2_T_17; // @[Mux.scala 81:58]\n", + " wire _io_use_rs2_T_25 = 7'h6f == io_opcode ? 1'h0 : 7'h63 == io_opcode | (7'h23 == io_opcode | _io_use_rs2_T_19); // @[Mux.scala 81:58]\n", + " wire _io_use_rs2_T_27 = 7'h67 == io_opcode ? 1'h0 : _io_use_rs2_T_25; // @[Mux.scala 81:58]\n", + " wire _io_use_rs2_T_29 = 7'h37 == io_opcode ? 1'h0 : _io_use_rs2_T_27; // @[Mux.scala 81:58]\n", + " wire _io_use_rs2_T_31 = 7'h17 == io_opcode ? 1'h0 : _io_use_rs2_T_29; // @[Mux.scala 81:58]\n", + " assign io_aluop = 7'h17 == io_opcode ? 4'h0 : _io_aluop_T_69; // @[Mux.scala 81:58]\n", + " assign io_immsrc = 7'h73 == io_opcode ? 3'h7 == io_funct3 | (3'h6 == io_funct3 | 3'h5 == io_funct3) : 7'h17 ==\n", + " io_opcode | (7'h37 == io_opcode | (7'h67 == io_opcode | (7'h6f == io_opcode | _io_immsrc_T_23))); // @[Mux.scala 81:58]\n", + " assign io_isbranch = 7'h63 == io_opcode; // @[Mux.scala 81:61]\n", + " assign io_memread = 7'h3 == io_opcode; // @[Mux.scala 81:61]\n", + " assign io_memwrite = 7'h23 == io_opcode; // @[Mux.scala 81:61]\n", + " assign io_regwrite = 7'h73 == io_opcode ? 3'h7 == io_funct3 | (3'h6 == io_funct3 | (3'h5 == io_funct3 | (3'h3 ==\n", + " io_funct3 | (3'h2 == io_funct3 | 3'h1 == io_funct3)))) : 7'h17 == io_opcode | (7'h37 == io_opcode | (7'h67 ==\n", + " io_opcode | (7'h6f == io_opcode | _io_regwrite_T_23))); // @[Mux.scala 81:58]\n", + " assign io_memtoreg = 7'h73 == io_opcode ? _io_memtoreg_T_13 : _io_memtoreg_T_23; // @[Mux.scala 81:58]\n", + " assign io_pcsel = 7'h67 == io_opcode; // @[Mux.scala 81:61]\n", + " assign io_rdsel = 7'h17 == io_opcode; // @[Mux.scala 81:61]\n", + " assign io_isjump = 7'h67 == io_opcode | 7'h6f == io_opcode; // @[Mux.scala 81:58]\n", + " assign io_islui = 7'h37 == io_opcode; // @[Mux.scala 81:61]\n", + " assign io_use_rs1 = 7'h73 == io_opcode ? _io_use_rs1_T_13 : _io_use_rs1_T_31; // @[Mux.scala 81:58]\n", + " assign io_use_rs2 = 7'h73 == io_opcode ? 1'h0 : _io_use_rs2_T_31; // @[Mux.scala 81:58]\n", + "endmodule\n", + "module Regfile(\n", + " input clock,\n", + " input reset,\n", + " input [4:0] io_id_rs1,\n", + " input [4:0] io_id_rs2,\n", + " input [4:0] io_wb_rd,\n", + " input [31:0] io_writedata,\n", + " input io_wb_regwrite,\n", + " output [31:0] io_rs1_data,\n", + " output [31:0] io_rs2_data\n", + ");\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " reg [31:0] _RAND_0;\n", + " reg [31:0] _RAND_1;\n", + " reg [31:0] _RAND_2;\n", + " reg [31:0] _RAND_3;\n", + " reg [31:0] _RAND_4;\n", + " reg [31:0] _RAND_5;\n", + " reg [31:0] _RAND_6;\n", + " reg [31:0] _RAND_7;\n", + " reg [31:0] _RAND_8;\n", + " reg [31:0] _RAND_9;\n", + " reg [31:0] _RAND_10;\n", + " reg [31:0] _RAND_11;\n", + " reg [31:0] _RAND_12;\n", + " reg [31:0] _RAND_13;\n", + " reg [31:0] _RAND_14;\n", + " reg [31:0] _RAND_15;\n", + " reg [31:0] _RAND_16;\n", + " reg [31:0] _RAND_17;\n", + " reg [31:0] _RAND_18;\n", + " reg [31:0] _RAND_19;\n", + " reg [31:0] _RAND_20;\n", + " reg [31:0] _RAND_21;\n", + " reg [31:0] _RAND_22;\n", + " reg [31:0] _RAND_23;\n", + " reg [31:0] _RAND_24;\n", + " reg [31:0] _RAND_25;\n", + " reg [31:0] _RAND_26;\n", + " reg [31:0] _RAND_27;\n", + " reg [31:0] _RAND_28;\n", + " reg [31:0] _RAND_29;\n", + " reg [31:0] _RAND_30;\n", + " reg [31:0] _RAND_31;\n", + "`endif // RANDOMIZE_REG_INIT\n", + " reg [31:0] registers_0; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_1; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_2; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_3; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_4; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_5; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_6; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_7; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_8; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_9; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_10; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_11; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_12; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_13; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_14; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_15; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_16; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_17; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_18; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_19; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_20; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_21; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_22; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_23; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_24; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_25; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_26; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_27; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_28; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_29; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_30; // @[regfile.scala 17:26]\n", + " reg [31:0] registers_31; // @[regfile.scala 17:26]\n", + " wire [31:0] _GEN_1 = 5'h1 == io_id_rs1 ? registers_1 : registers_0; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_2 = 5'h2 == io_id_rs1 ? registers_2 : _GEN_1; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_3 = 5'h3 == io_id_rs1 ? registers_3 : _GEN_2; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_4 = 5'h4 == io_id_rs1 ? registers_4 : _GEN_3; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_5 = 5'h5 == io_id_rs1 ? registers_5 : _GEN_4; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_6 = 5'h6 == io_id_rs1 ? registers_6 : _GEN_5; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_7 = 5'h7 == io_id_rs1 ? registers_7 : _GEN_6; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_8 = 5'h8 == io_id_rs1 ? registers_8 : _GEN_7; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_9 = 5'h9 == io_id_rs1 ? registers_9 : _GEN_8; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_10 = 5'ha == io_id_rs1 ? registers_10 : _GEN_9; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_11 = 5'hb == io_id_rs1 ? registers_11 : _GEN_10; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_12 = 5'hc == io_id_rs1 ? registers_12 : _GEN_11; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_13 = 5'hd == io_id_rs1 ? registers_13 : _GEN_12; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_14 = 5'he == io_id_rs1 ? registers_14 : _GEN_13; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_15 = 5'hf == io_id_rs1 ? registers_15 : _GEN_14; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_16 = 5'h10 == io_id_rs1 ? registers_16 : _GEN_15; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_17 = 5'h11 == io_id_rs1 ? registers_17 : _GEN_16; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_18 = 5'h12 == io_id_rs1 ? registers_18 : _GEN_17; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_19 = 5'h13 == io_id_rs1 ? registers_19 : _GEN_18; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_20 = 5'h14 == io_id_rs1 ? registers_20 : _GEN_19; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_21 = 5'h15 == io_id_rs1 ? registers_21 : _GEN_20; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_22 = 5'h16 == io_id_rs1 ? registers_22 : _GEN_21; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_23 = 5'h17 == io_id_rs1 ? registers_23 : _GEN_22; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_24 = 5'h18 == io_id_rs1 ? registers_24 : _GEN_23; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_25 = 5'h19 == io_id_rs1 ? registers_25 : _GEN_24; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_26 = 5'h1a == io_id_rs1 ? registers_26 : _GEN_25; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_27 = 5'h1b == io_id_rs1 ? registers_27 : _GEN_26; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_28 = 5'h1c == io_id_rs1 ? registers_28 : _GEN_27; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_29 = 5'h1d == io_id_rs1 ? registers_29 : _GEN_28; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_30 = 5'h1e == io_id_rs1 ? registers_30 : _GEN_29; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_31 = 5'h1f == io_id_rs1 ? registers_31 : _GEN_30; // @[regfile.scala 20:{21,21}]\n", + " wire [31:0] _GEN_33 = 5'h1 == io_id_rs2 ? registers_1 : registers_0; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_34 = 5'h2 == io_id_rs2 ? registers_2 : _GEN_33; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_35 = 5'h3 == io_id_rs2 ? registers_3 : _GEN_34; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_36 = 5'h4 == io_id_rs2 ? registers_4 : _GEN_35; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_37 = 5'h5 == io_id_rs2 ? registers_5 : _GEN_36; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_38 = 5'h6 == io_id_rs2 ? registers_6 : _GEN_37; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_39 = 5'h7 == io_id_rs2 ? registers_7 : _GEN_38; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_40 = 5'h8 == io_id_rs2 ? registers_8 : _GEN_39; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_41 = 5'h9 == io_id_rs2 ? registers_9 : _GEN_40; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_42 = 5'ha == io_id_rs2 ? registers_10 : _GEN_41; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_43 = 5'hb == io_id_rs2 ? registers_11 : _GEN_42; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_44 = 5'hc == io_id_rs2 ? registers_12 : _GEN_43; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_45 = 5'hd == io_id_rs2 ? registers_13 : _GEN_44; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_46 = 5'he == io_id_rs2 ? registers_14 : _GEN_45; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_47 = 5'hf == io_id_rs2 ? registers_15 : _GEN_46; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_48 = 5'h10 == io_id_rs2 ? registers_16 : _GEN_47; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_49 = 5'h11 == io_id_rs2 ? registers_17 : _GEN_48; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_50 = 5'h12 == io_id_rs2 ? registers_18 : _GEN_49; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_51 = 5'h13 == io_id_rs2 ? registers_19 : _GEN_50; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_52 = 5'h14 == io_id_rs2 ? registers_20 : _GEN_51; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_53 = 5'h15 == io_id_rs2 ? registers_21 : _GEN_52; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_54 = 5'h16 == io_id_rs2 ? registers_22 : _GEN_53; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_55 = 5'h17 == io_id_rs2 ? registers_23 : _GEN_54; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_56 = 5'h18 == io_id_rs2 ? registers_24 : _GEN_55; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_57 = 5'h19 == io_id_rs2 ? registers_25 : _GEN_56; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_58 = 5'h1a == io_id_rs2 ? registers_26 : _GEN_57; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_59 = 5'h1b == io_id_rs2 ? registers_27 : _GEN_58; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_60 = 5'h1c == io_id_rs2 ? registers_28 : _GEN_59; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_61 = 5'h1d == io_id_rs2 ? registers_29 : _GEN_60; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_62 = 5'h1e == io_id_rs2 ? registers_30 : _GEN_61; // @[regfile.scala 21:{21,21}]\n", + " wire [31:0] _GEN_63 = 5'h1f == io_id_rs2 ? registers_31 : _GEN_62; // @[regfile.scala 21:{21,21}]\n", + " assign io_rs1_data = io_id_rs1 == 5'h0 ? 32'h0 : _GEN_31; // @[regfile.scala 20:21]\n", + " assign io_rs2_data = io_id_rs2 == 5'h0 ? 32'h0 : _GEN_63; // @[regfile.scala 21:21]\n", + " always @(posedge clock) begin\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_0 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h0 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_0 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_1 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h1 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_1 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_2 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h2 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_2 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_3 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h3 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_3 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_4 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h4 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_4 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_5 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h5 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_5 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_6 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h6 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_6 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_7 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h7 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_7 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_8 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h8 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_8 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_9 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h9 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_9 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_10 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'ha == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_10 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_11 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'hb == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_11 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_12 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'hc == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_12 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_13 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'hd == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_13 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_14 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'he == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_14 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_15 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'hf == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_15 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_16 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h10 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_16 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_17 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h11 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_17 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_18 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h12 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_18 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_19 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h13 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_19 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_20 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h14 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_20 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_21 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h15 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_21 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_22 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h16 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_22 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_23 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h17 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_23 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_24 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h18 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_24 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_25 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h19 == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_25 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_26 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h1a == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_26 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_27 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h1b == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_27 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_28 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h1c == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_28 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_29 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h1d == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_29 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_30 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h1e == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_30 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " if (reset) begin // @[regfile.scala 17:26]\n", + " registers_31 <= 32'h0; // @[regfile.scala 17:26]\n", + " end else if (io_wb_regwrite & io_wb_rd != 5'h0) begin // @[regfile.scala 24:44]\n", + " if (5'h1f == io_wb_rd) begin // @[regfile.scala 25:25]\n", + " registers_31 <= io_writedata; // @[regfile.scala 25:25]\n", + " end\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " _RAND_0 = {1{`RANDOM}};\n", + " registers_0 = _RAND_0[31:0];\n", + " _RAND_1 = {1{`RANDOM}};\n", + " registers_1 = _RAND_1[31:0];\n", + " _RAND_2 = {1{`RANDOM}};\n", + " registers_2 = _RAND_2[31:0];\n", + " _RAND_3 = {1{`RANDOM}};\n", + " registers_3 = _RAND_3[31:0];\n", + " _RAND_4 = {1{`RANDOM}};\n", + " registers_4 = _RAND_4[31:0];\n", + " _RAND_5 = {1{`RANDOM}};\n", + " registers_5 = _RAND_5[31:0];\n", + " _RAND_6 = {1{`RANDOM}};\n", + " registers_6 = _RAND_6[31:0];\n", + " _RAND_7 = {1{`RANDOM}};\n", + " registers_7 = _RAND_7[31:0];\n", + " _RAND_8 = {1{`RANDOM}};\n", + " registers_8 = _RAND_8[31:0];\n", + " _RAND_9 = {1{`RANDOM}};\n", + " registers_9 = _RAND_9[31:0];\n", + " _RAND_10 = {1{`RANDOM}};\n", + " registers_10 = _RAND_10[31:0];\n", + " _RAND_11 = {1{`RANDOM}};\n", + " registers_11 = _RAND_11[31:0];\n", + " _RAND_12 = {1{`RANDOM}};\n", + " registers_12 = _RAND_12[31:0];\n", + " _RAND_13 = {1{`RANDOM}};\n", + " registers_13 = _RAND_13[31:0];\n", + " _RAND_14 = {1{`RANDOM}};\n", + " registers_14 = _RAND_14[31:0];\n", + " _RAND_15 = {1{`RANDOM}};\n", + " registers_15 = _RAND_15[31:0];\n", + " _RAND_16 = {1{`RANDOM}};\n", + " registers_16 = _RAND_16[31:0];\n", + " _RAND_17 = {1{`RANDOM}};\n", + " registers_17 = _RAND_17[31:0];\n", + " _RAND_18 = {1{`RANDOM}};\n", + " registers_18 = _RAND_18[31:0];\n", + " _RAND_19 = {1{`RANDOM}};\n", + " registers_19 = _RAND_19[31:0];\n", + " _RAND_20 = {1{`RANDOM}};\n", + " registers_20 = _RAND_20[31:0];\n", + " _RAND_21 = {1{`RANDOM}};\n", + " registers_21 = _RAND_21[31:0];\n", + " _RAND_22 = {1{`RANDOM}};\n", + " registers_22 = _RAND_22[31:0];\n", + " _RAND_23 = {1{`RANDOM}};\n", + " registers_23 = _RAND_23[31:0];\n", + " _RAND_24 = {1{`RANDOM}};\n", + " registers_24 = _RAND_24[31:0];\n", + " _RAND_25 = {1{`RANDOM}};\n", + " registers_25 = _RAND_25[31:0];\n", + " _RAND_26 = {1{`RANDOM}};\n", + " registers_26 = _RAND_26[31:0];\n", + " _RAND_27 = {1{`RANDOM}};\n", + " registers_27 = _RAND_27[31:0];\n", + " _RAND_28 = {1{`RANDOM}};\n", + " registers_28 = _RAND_28[31:0];\n", + " _RAND_29 = {1{`RANDOM}};\n", + " registers_29 = _RAND_29[31:0];\n", + " _RAND_30 = {1{`RANDOM}};\n", + " registers_30 = _RAND_30[31:0];\n", + " _RAND_31 = {1{`RANDOM}};\n", + " registers_31 = _RAND_31[31:0];\n", + "`endif // RANDOMIZE_REG_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n", + "module ImmGen(\n", + " input [31:0] io_inst,\n", + " output [31:0] io_imm\n", + ");\n", + " wire [6:0] opcode = io_inst[6:0]; // @[immgen.scala 11:23]\n", + " wire [2:0] _GEN_0 = 7'h17 == opcode ? 3'h7 : 3'h0; // @[immgen.scala 14:19 23:29]\n", + " wire [2:0] _GEN_1 = 7'h37 == opcode ? 3'h6 : _GEN_0; // @[immgen.scala 14:19 22:29]\n", + " wire [2:0] _GEN_2 = 7'h67 == opcode ? 3'h5 : _GEN_1; // @[immgen.scala 14:19 21:29]\n", + " wire [2:0] _GEN_3 = 7'h6f == opcode ? 3'h4 : _GEN_2; // @[immgen.scala 14:19 20:29]\n", + " wire [2:0] _GEN_4 = 7'h63 == opcode ? 3'h3 : _GEN_3; // @[immgen.scala 14:19 19:29]\n", + " wire [2:0] _GEN_5 = 7'h23 == opcode ? 3'h2 : _GEN_4; // @[immgen.scala 14:19 18:29]\n", + " wire [2:0] _GEN_6 = 7'h3 == opcode ? 3'h1 : _GEN_5; // @[immgen.scala 14:19 17:29]\n", + " wire [2:0] _GEN_7 = 7'h13 == opcode ? 3'h1 : _GEN_6; // @[immgen.scala 14:19 16:29]\n", + " wire [2:0] fmt = 7'h33 == opcode ? 3'h0 : _GEN_7; // @[immgen.scala 14:19 15:29]\n", + " wire [19:0] _imm_T_2 = io_inst[31] ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]\n", + " wire [31:0] _imm_T_4 = {_imm_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]\n", + " wire [31:0] _imm_T_10 = {_imm_T_2,io_inst[31:25],io_inst[11:7]}; // @[Cat.scala 31:58]\n", + " wire [18:0] _imm_T_13 = io_inst[31] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 74:12]\n", + " wire [30:0] _imm_T_17 = {_imm_T_13,io_inst[7],io_inst[30:25],io_inst[11:8],1'h0}; // @[Cat.scala 31:58]\n", + " wire [10:0] _imm_T_20 = io_inst[31] ? 11'h7ff : 11'h0; // @[Bitwise.scala 74:12]\n", + " wire [30:0] _imm_T_24 = {_imm_T_20,io_inst[19:12],io_inst[20],io_inst[30:21],1'h0}; // @[Cat.scala 31:58]\n", + " wire [31:0] _imm_T_32 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]\n", + " wire [31:0] _GEN_9 = 3'h7 == fmt ? _imm_T_32 : 32'h0; // @[immgen.scala 28:16 36:25]\n", + " wire [31:0] _GEN_10 = 3'h6 == fmt ? _imm_T_32 : _GEN_9; // @[immgen.scala 28:16 35:25]\n", + " wire [31:0] _GEN_11 = 3'h5 == fmt ? _imm_T_4 : _GEN_10; // @[immgen.scala 28:16 34:25]\n", + " wire [31:0] _GEN_12 = 3'h4 == fmt ? {{1'd0}, _imm_T_24} : _GEN_11; // @[immgen.scala 28:16 33:25]\n", + " wire [31:0] _GEN_13 = 3'h3 == fmt ? {{1'd0}, _imm_T_17} : _GEN_12; // @[immgen.scala 28:16 32:25]\n", + " wire [31:0] _GEN_14 = 3'h2 == fmt ? _imm_T_10 : _GEN_13; // @[immgen.scala 28:16 31:25]\n", + " wire [31:0] _GEN_15 = 3'h1 == fmt ? _imm_T_4 : _GEN_14; // @[immgen.scala 28:16 30:25]\n", + " assign io_imm = 3'h0 == fmt ? 32'h0 : _GEN_15; // @[immgen.scala 28:16 29:25]\n", + "endmodule\n", + "module Decode(\n", + " input clock,\n", + " input reset,\n", + " input [31:0] io_id_pc,\n", + " input [31:0] io_inst,\n", + " output io_csr_read,\n", + " output io_csr_write,\n", + " output [11:0] io_csr_address,\n", + " output [3:0] io_ecause_out,\n", + " output io_exception_out,\n", + " output io_mret_out,\n", + " output io_wfi_out,\n", + " output [31:0] io_ex_pc,\n", + " output [3:0] io_aluop,\n", + " output io_immsrc,\n", + " output io_isbranch,\n", + " output io_memread,\n", + " output io_memwrite,\n", + " output io_regwrite,\n", + " output [1:0] io_memtoreg,\n", + " output io_pcsel,\n", + " output io_rdsel,\n", + " output io_isjump,\n", + " output io_islui,\n", + " output [31:0] io_rs1_data,\n", + " output [31:0] io_rs2_data,\n", + " output [31:0] io_imm,\n", + " output [31:0] io_funct3,\n", + " output [4:0] io_ex_rs1,\n", + " output [4:0] io_ex_rs2,\n", + " output [4:0] io_ex_rd,\n", + " output io_ex_use_rs1,\n", + " output io_ex_use_rs2,\n", + " input [4:0] io_wb_rd,\n", + " input io_wb_regwrite,\n", + " input [31:0] io_writedata,\n", + " input io_id_ex_flush,\n", + " output [4:0] io_id_rs1,\n", + " output [4:0] io_id_rs2,\n", + " output io_use_rs1,\n", + " output io_use_rs2\n", + ");\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " reg [31:0] _RAND_0;\n", + " reg [31:0] _RAND_1;\n", + " reg [31:0] _RAND_2;\n", + " reg [31:0] _RAND_3;\n", + " reg [31:0] _RAND_4;\n", + " reg [31:0] _RAND_5;\n", + " reg [31:0] _RAND_6;\n", + " reg [31:0] _RAND_7;\n", + " reg [31:0] _RAND_8;\n", + " reg [31:0] _RAND_9;\n", + " reg [31:0] _RAND_10;\n", + " reg [31:0] _RAND_11;\n", + " reg [31:0] _RAND_12;\n", + " reg [31:0] _RAND_13;\n", + " reg [31:0] _RAND_14;\n", + " reg [31:0] _RAND_15;\n", + " reg [31:0] _RAND_16;\n", + " reg [31:0] _RAND_17;\n", + " reg [31:0] _RAND_18;\n", + " reg [31:0] _RAND_19;\n", + " reg [31:0] _RAND_20;\n", + " reg [31:0] _RAND_21;\n", + " reg [31:0] _RAND_22;\n", + " reg [31:0] _RAND_23;\n", + " reg [31:0] _RAND_24;\n", + " reg [31:0] _RAND_25;\n", + " reg [31:0] _RAND_26;\n", + " reg [31:0] _RAND_27;\n", + "`endif // RANDOMIZE_REG_INIT\n", + " wire [6:0] control_io_opcode; // @[decode.scala 52:23]\n", + " wire [6:0] control_io_funct7; // @[decode.scala 52:23]\n", + " wire [2:0] control_io_funct3; // @[decode.scala 52:23]\n", + " wire [3:0] control_io_aluop; // @[decode.scala 52:23]\n", + " wire control_io_immsrc; // @[decode.scala 52:23]\n", + " wire control_io_isbranch; // @[decode.scala 52:23]\n", + " wire control_io_memread; // @[decode.scala 52:23]\n", + " wire control_io_memwrite; // @[decode.scala 52:23]\n", + " wire control_io_regwrite; // @[decode.scala 52:23]\n", + " wire [1:0] control_io_memtoreg; // @[decode.scala 52:23]\n", + " wire control_io_pcsel; // @[decode.scala 52:23]\n", + " wire control_io_rdsel; // @[decode.scala 52:23]\n", + " wire control_io_isjump; // @[decode.scala 52:23]\n", + " wire control_io_islui; // @[decode.scala 52:23]\n", + " wire control_io_use_rs1; // @[decode.scala 52:23]\n", + " wire control_io_use_rs2; // @[decode.scala 52:23]\n", + " wire regfile_clock; // @[decode.scala 53:23]\n", + " wire regfile_reset; // @[decode.scala 53:23]\n", + " wire [4:0] regfile_io_id_rs1; // @[decode.scala 53:23]\n", + " wire [4:0] regfile_io_id_rs2; // @[decode.scala 53:23]\n", + " wire [4:0] regfile_io_wb_rd; // @[decode.scala 53:23]\n", + " wire [31:0] regfile_io_writedata; // @[decode.scala 53:23]\n", + " wire regfile_io_wb_regwrite; // @[decode.scala 53:23]\n", + " wire [31:0] regfile_io_rs1_data; // @[decode.scala 53:23]\n", + " wire [31:0] regfile_io_rs2_data; // @[decode.scala 53:23]\n", + " wire [31:0] immGen_io_inst; // @[decode.scala 54:22]\n", + " wire [31:0] immGen_io_imm; // @[decode.scala 54:22]\n", + " reg csr_read_reg; // @[decode.scala 57:29]\n", + " reg csr_write_reg; // @[decode.scala 58:30]\n", + " reg [11:0] csr_address_reg; // @[decode.scala 59:32]\n", + " reg [3:0] ecause_out_reg; // @[decode.scala 60:31]\n", + " reg exception_out_reg; // @[decode.scala 61:34]\n", + " reg mret_out_reg; // @[decode.scala 62:29]\n", + " reg wfi_out_reg; // @[decode.scala 63:28]\n", + " reg [31:0] id_ex_pc_reg; // @[decode.scala 64:29]\n", + " reg [3:0] id_ex_aluop_reg; // @[decode.scala 65:32]\n", + " reg id_ex_immsrc_reg; // @[decode.scala 66:33]\n", + " reg id_ex_isbranch_reg; // @[decode.scala 67:35]\n", + " reg id_ex_memread_reg; // @[decode.scala 68:34]\n", + " reg id_ex_memwrite_reg; // @[decode.scala 69:35]\n", + " reg id_ex_regwrite_reg; // @[decode.scala 70:35]\n", + " reg [1:0] id_ex_memtoreg_reg; // @[decode.scala 71:35]\n", + " reg id_ex_pcsel_reg; // @[decode.scala 72:32]\n", + " reg id_ex_rdsel_reg; // @[decode.scala 73:32]\n", + " reg id_ex_isjump_reg; // @[decode.scala 74:33]\n", + " reg id_ex_islui_reg; // @[decode.scala 75:32]\n", + " reg [31:0] id_ex_rs1_data_reg; // @[decode.scala 76:35]\n", + " reg [31:0] id_ex_rs2_data_reg; // @[decode.scala 77:35]\n", + " reg [31:0] id_ex_imm_reg; // @[decode.scala 78:30]\n", + " reg [2:0] id_ex_funct3_reg; // @[decode.scala 79:33]\n", + " reg [4:0] id_ex_ex_rs1_reg; // @[decode.scala 80:33]\n", + " reg [4:0] id_ex_ex_rs2_reg; // @[decode.scala 81:33]\n", + " reg [4:0] id_ex_ex_rd_reg; // @[decode.scala 82:32]\n", + " reg id_ex_ex_use_rs1_reg; // @[decode.scala 83:37]\n", + " reg id_ex_ex_use_rs2_reg; // @[decode.scala 84:37]\n", + " wire csrInst = io_inst[6:0] == 7'h73; // @[decode.scala 100:38]\n", + " wire _csrrwInst_T_1 = io_inst[14:12] == 3'h1; // @[decode.scala 101:53]\n", + " wire csrrwInst = csrInst & io_inst[14:12] == 3'h1; // @[decode.scala 101:27]\n", + " wire _csrrsInst_T_1 = io_inst[14:12] == 3'h2; // @[decode.scala 102:53]\n", + " wire csrrsInst = csrInst & io_inst[14:12] == 3'h2; // @[decode.scala 102:27]\n", + " wire _csrrcInst_T_1 = io_inst[14:12] == 3'h3; // @[decode.scala 103:53]\n", + " wire csrrcInst = csrInst & io_inst[14:12] == 3'h3; // @[decode.scala 103:27]\n", + " wire _csrrwiInst_T_1 = io_inst[14:12] == 3'h5; // @[decode.scala 104:54]\n", + " wire csrrwiInst = csrInst & io_inst[14:12] == 3'h5; // @[decode.scala 104:28]\n", + " wire _csrrsiInst_T_1 = io_inst[14:12] == 3'h6; // @[decode.scala 105:54]\n", + " wire csrrsiInst = csrInst & io_inst[14:12] == 3'h6; // @[decode.scala 105:28]\n", + " wire _csrrciInst_T_1 = io_inst[14:12] == 3'h7; // @[decode.scala 106:54]\n", + " wire csrrciInst = csrInst & io_inst[14:12] == 3'h7; // @[decode.scala 106:28]\n", + " wire mret_out = io_inst == 32'h30200073; // @[decode.scala 118:26]\n", + " wire wfi_out = io_inst == 32'h10500073; // @[decode.scala 119:25]\n", + " wire _isLegalInstruction_T = io_inst[6:0] == 7'h33; // @[decode.scala 127:13]\n", + " wire _isLegalInstruction_T_1 = io_inst[14:12] == 3'h0; // @[decode.scala 127:40]\n", + " wire _isLegalInstruction_T_2 = io_inst[6:0] == 7'h33 & io_inst[14:12] == 3'h0; // @[decode.scala 127:30]\n", + " wire _isLegalInstruction_T_3 = io_inst[31:25] == 7'h0; // @[decode.scala 127:63]\n", + " wire _isLegalInstruction_T_4 = io_inst[6:0] == 7'h33 & io_inst[14:12] == 3'h0 & io_inst[31:25] == 7'h0; // @[decode.scala 127:53]\n", + " wire _isLegalInstruction_T_8 = io_inst[31:25] == 7'h20; // @[decode.scala 128:63]\n", + " wire _isLegalInstruction_T_9 = _isLegalInstruction_T_2 & io_inst[31:25] == 7'h20; // @[decode.scala 128:53]\n", + " wire _isLegalInstruction_T_14 = _isLegalInstruction_T_2 & io_inst[31:25] == 7'h4; // @[decode.scala 129:53]\n", + " wire _isLegalInstruction_T_19 = _isLegalInstruction_T & _csrrsiInst_T_1 & _isLegalInstruction_T_3; // @[decode.scala 130:53]\n", + " wire _isLegalInstruction_T_24 = _isLegalInstruction_T & _csrrciInst_T_1 & _isLegalInstruction_T_3; // @[decode.scala 131:53]\n", + " wire _isLegalInstruction_T_29 = _isLegalInstruction_T & _csrrwInst_T_1 & _isLegalInstruction_T_3; // @[decode.scala 132:53]\n", + " wire _isLegalInstruction_T_32 = _isLegalInstruction_T & _csrrwiInst_T_1; // @[decode.scala 133:30]\n", + " wire _isLegalInstruction_T_34 = _isLegalInstruction_T & _csrrwiInst_T_1 & _isLegalInstruction_T_3; // @[decode.scala 133:53]\n", + " wire _isLegalInstruction_T_39 = _isLegalInstruction_T_32 & _isLegalInstruction_T_8; // @[decode.scala 134:53]\n", + " wire _isLegalInstruction_T_44 = _isLegalInstruction_T & _csrrsInst_T_1 & _isLegalInstruction_T_3; // @[decode.scala 135:53]\n", + " wire _isLegalInstruction_T_49 = _isLegalInstruction_T & _csrrcInst_T_1 & _isLegalInstruction_T_3; // @[decode.scala 136:53]\n", + " wire _isLegalInstruction_T_50 = io_inst[6:0] == 7'h13; // @[decode.scala 137:13]\n", + " wire _isLegalInstruction_T_52 = io_inst[6:0] == 7'h13 & _isLegalInstruction_T_1; // @[decode.scala 137:30]\n", + " wire _isLegalInstruction_T_54 = io_inst[14:12] == 3'h4; // @[decode.scala 138:40]\n", + " wire _isLegalInstruction_T_55 = _isLegalInstruction_T_50 & io_inst[14:12] == 3'h4; // @[decode.scala 138:30]\n", + " wire _isLegalInstruction_T_58 = _isLegalInstruction_T_50 & _csrrsiInst_T_1; // @[decode.scala 139:30]\n", + " wire _isLegalInstruction_T_61 = _isLegalInstruction_T_50 & _csrrciInst_T_1; // @[decode.scala 140:30]\n", + " wire _isLegalInstruction_T_66 = _isLegalInstruction_T_50 & _csrrwInst_T_1 & _isLegalInstruction_T_3; // @[decode.scala 141:53]\n", + " wire _isLegalInstruction_T_69 = _isLegalInstruction_T_50 & _csrrwiInst_T_1; // @[decode.scala 142:30]\n", + " wire _isLegalInstruction_T_71 = _isLegalInstruction_T_50 & _csrrwiInst_T_1 & _isLegalInstruction_T_3; // @[decode.scala 142:53]\n", + " wire _isLegalInstruction_T_76 = _isLegalInstruction_T_69 & _isLegalInstruction_T_8; // @[decode.scala 143:53]\n", + " wire _isLegalInstruction_T_79 = _isLegalInstruction_T_50 & _csrrsInst_T_1; // @[decode.scala 144:30]\n", + " wire _isLegalInstruction_T_82 = _isLegalInstruction_T_50 & _csrrcInst_T_1; // @[decode.scala 145:30]\n", + " wire _isLegalInstruction_T_83 = io_inst[6:0] == 7'h3; // @[decode.scala 146:13]\n", + " wire _isLegalInstruction_T_85 = io_inst[6:0] == 7'h3 & _isLegalInstruction_T_1; // @[decode.scala 146:30]\n", + " wire _isLegalInstruction_T_88 = _isLegalInstruction_T_83 & _csrrwInst_T_1; // @[decode.scala 147:30]\n", + " wire _isLegalInstruction_T_91 = _isLegalInstruction_T_83 & _csrrsInst_T_1; // @[decode.scala 148:30]\n", + " wire _isLegalInstruction_T_94 = _isLegalInstruction_T_83 & _isLegalInstruction_T_54; // @[decode.scala 149:30]\n", + " wire _isLegalInstruction_T_97 = _isLegalInstruction_T_83 & _csrrwiInst_T_1; // @[decode.scala 150:30]\n", + " wire _isLegalInstruction_T_98 = io_inst[6:0] == 7'h23; // @[decode.scala 151:13]\n", + " wire _isLegalInstruction_T_100 = io_inst[6:0] == 7'h23 & _isLegalInstruction_T_1; // @[decode.scala 151:30]\n", + " wire _isLegalInstruction_T_103 = _isLegalInstruction_T_98 & _csrrwInst_T_1; // @[decode.scala 152:30]\n", + " wire _isLegalInstruction_T_106 = _isLegalInstruction_T_98 & _csrrsInst_T_1; // @[decode.scala 153:30]\n", + " wire _isLegalInstruction_T_107 = io_inst[6:0] == 7'h63; // @[decode.scala 154:13]\n", + " wire _isLegalInstruction_T_109 = io_inst[6:0] == 7'h63 & _isLegalInstruction_T_1; // @[decode.scala 154:30]\n", + " wire _isLegalInstruction_T_112 = _isLegalInstruction_T_107 & _csrrwInst_T_1; // @[decode.scala 155:30]\n", + " wire _isLegalInstruction_T_115 = _isLegalInstruction_T_107 & _isLegalInstruction_T_54; // @[decode.scala 156:30]\n", + " wire _isLegalInstruction_T_118 = _isLegalInstruction_T_107 & _csrrwiInst_T_1; // @[decode.scala 157:30]\n", + " wire _isLegalInstruction_T_121 = _isLegalInstruction_T_107 & _csrrsiInst_T_1; // @[decode.scala 158:30]\n", + " wire _isLegalInstruction_T_124 = _isLegalInstruction_T_107 & _csrrciInst_T_1; // @[decode.scala 159:30]\n", + " wire _isLegalInstruction_T_125 = io_inst[6:0] == 7'h6f; // @[decode.scala 160:13]\n", + " wire _isLegalInstruction_T_128 = io_inst[6:0] == 7'h67 & _isLegalInstruction_T_1; // @[decode.scala 161:30]\n", + " wire _isLegalInstruction_T_129 = io_inst[6:0] == 7'h37; // @[decode.scala 162:13]\n", + " wire _isLegalInstruction_T_130 = io_inst[6:0] == 7'h17; // @[decode.scala 163:13]\n", + " wire _isLegalInstruction_T_133 = csrInst & _isLegalInstruction_T_1; // @[decode.scala 164:30]\n", + " wire _isLegalInstruction_T_135 = csrInst & _isLegalInstruction_T_1 & _isLegalInstruction_T_3; // @[decode.scala 164:53]\n", + " wire _isLegalInstruction_T_140 = _isLegalInstruction_T_133 & io_inst[31:25] == 7'h1; // @[decode.scala 165:53]\n", + " wire _isLegalInstruction_T_145 = _isLegalInstruction_T_133 & io_inst[31:25] == 7'h18; // @[decode.scala 166:53]\n", + " wire _isLegalInstruction_T_150 = _isLegalInstruction_T_133 & io_inst[31:25] == 7'h8; // @[decode.scala 167:53]\n", + " wire _isLegalInstruction_T_199 = _isLegalInstruction_T_76 | (_isLegalInstruction_T_79 | (_isLegalInstruction_T_82 | (\n", + " _isLegalInstruction_T_85 | (_isLegalInstruction_T_88 | (_isLegalInstruction_T_91 | (_isLegalInstruction_T_94 | (\n", + " _isLegalInstruction_T_97 | (_isLegalInstruction_T_100 | (_isLegalInstruction_T_103 | (_isLegalInstruction_T_106 | (\n", + " _isLegalInstruction_T_109 | (_isLegalInstruction_T_112 | (_isLegalInstruction_T_115 | (_isLegalInstruction_T_118 | (\n", + " _isLegalInstruction_T_121 | (_isLegalInstruction_T_124 | (_isLegalInstruction_T_125 | (_isLegalInstruction_T_128 | (\n", + " _isLegalInstruction_T_129 | (_isLegalInstruction_T_130 | (_isLegalInstruction_T_135 | (_isLegalInstruction_T_140 | (\n", + " _isLegalInstruction_T_145 | (_isLegalInstruction_T_150 | (csrrwInst | (csrrsInst | (csrrcInst | (csrrwiInst | (\n", + " csrrsiInst | csrrciInst))))))))))))))))))))))))))))); // @[Mux.scala 101:16]\n", + " wire isLegalInstruction = _isLegalInstruction_T_4 | (_isLegalInstruction_T_9 | (_isLegalInstruction_T_14 | (\n", + " _isLegalInstruction_T_19 | (_isLegalInstruction_T_24 | (_isLegalInstruction_T_29 | (_isLegalInstruction_T_34 | (\n", + " _isLegalInstruction_T_39 | (_isLegalInstruction_T_44 | (_isLegalInstruction_T_49 | (_isLegalInstruction_T_52 | (\n", + " _isLegalInstruction_T_55 | (_isLegalInstruction_T_58 | (_isLegalInstruction_T_61 | (_isLegalInstruction_T_66 | (\n", + " _isLegalInstruction_T_71 | _isLegalInstruction_T_199))))))))))))))); // @[Mux.scala 101:16]\n", + " wire [1:0] ecause_out = isLegalInstruction ? 2'h0 : 2'h2; // @[decode.scala 177:23]\n", + " wire [1:0] _GEN_26 = io_id_ex_flush ? 2'h0 : ecause_out; // @[decode.scala 180:25 205:20 213:20]\n", + " Control control ( // @[decode.scala 52:23]\n", + " .io_opcode(control_io_opcode),\n", + " .io_funct7(control_io_funct7),\n", + " .io_funct3(control_io_funct3),\n", + " .io_aluop(control_io_aluop),\n", + " .io_immsrc(control_io_immsrc),\n", + " .io_isbranch(control_io_isbranch),\n", + " .io_memread(control_io_memread),\n", + " .io_memwrite(control_io_memwrite),\n", + " .io_regwrite(control_io_regwrite),\n", + " .io_memtoreg(control_io_memtoreg),\n", + " .io_pcsel(control_io_pcsel),\n", + " .io_rdsel(control_io_rdsel),\n", + " .io_isjump(control_io_isjump),\n", + " .io_islui(control_io_islui),\n", + " .io_use_rs1(control_io_use_rs1),\n", + " .io_use_rs2(control_io_use_rs2)\n", + " );\n", + " Regfile regfile ( // @[decode.scala 53:23]\n", + " .clock(regfile_clock),\n", + " .reset(regfile_reset),\n", + " .io_id_rs1(regfile_io_id_rs1),\n", + " .io_id_rs2(regfile_io_id_rs2),\n", + " .io_wb_rd(regfile_io_wb_rd),\n", + " .io_writedata(regfile_io_writedata),\n", + " .io_wb_regwrite(regfile_io_wb_regwrite),\n", + " .io_rs1_data(regfile_io_rs1_data),\n", + " .io_rs2_data(regfile_io_rs2_data)\n", + " );\n", + " ImmGen immGen ( // @[decode.scala 54:22]\n", + " .io_inst(immGen_io_inst),\n", + " .io_imm(immGen_io_imm)\n", + " );\n", + " assign io_csr_read = csr_read_reg; // @[decode.scala 244:15]\n", + " assign io_csr_write = csr_write_reg; // @[decode.scala 245:16]\n", + " assign io_csr_address = csr_address_reg; // @[decode.scala 246:18]\n", + " assign io_ecause_out = ecause_out_reg; // @[decode.scala 247:17]\n", + " assign io_exception_out = exception_out_reg; // @[decode.scala 248:20]\n", + " assign io_mret_out = mret_out_reg; // @[decode.scala 249:15]\n", + " assign io_wfi_out = wfi_out_reg; // @[decode.scala 250:14]\n", + " assign io_ex_pc = id_ex_pc_reg; // @[decode.scala 251:12]\n", + " assign io_aluop = id_ex_aluop_reg; // @[decode.scala 252:12]\n", + " assign io_immsrc = id_ex_immsrc_reg; // @[decode.scala 253:13]\n", + " assign io_isbranch = id_ex_isbranch_reg; // @[decode.scala 254:15]\n", + " assign io_memread = id_ex_memread_reg; // @[decode.scala 255:14]\n", + " assign io_memwrite = id_ex_memwrite_reg; // @[decode.scala 256:15]\n", + " assign io_regwrite = id_ex_regwrite_reg; // @[decode.scala 257:15]\n", + " assign io_memtoreg = id_ex_memtoreg_reg; // @[decode.scala 258:15]\n", + " assign io_pcsel = id_ex_pcsel_reg; // @[decode.scala 259:12]\n", + " assign io_rdsel = id_ex_rdsel_reg; // @[decode.scala 260:12]\n", + " assign io_isjump = id_ex_isjump_reg; // @[decode.scala 261:13]\n", + " assign io_islui = id_ex_islui_reg; // @[decode.scala 262:12]\n", + " assign io_rs1_data = id_ex_rs1_data_reg; // @[decode.scala 263:15]\n", + " assign io_rs2_data = id_ex_rs2_data_reg; // @[decode.scala 264:15]\n", + " assign io_imm = id_ex_imm_reg; // @[decode.scala 265:10]\n", + " assign io_funct3 = {{29'd0}, id_ex_funct3_reg}; // @[decode.scala 266:13]\n", + " assign io_ex_rs1 = id_ex_ex_rs1_reg; // @[decode.scala 267:13]\n", + " assign io_ex_rs2 = id_ex_ex_rs2_reg; // @[decode.scala 268:13]\n", + " assign io_ex_rd = id_ex_ex_rd_reg; // @[decode.scala 269:12]\n", + " assign io_ex_use_rs1 = id_ex_ex_use_rs1_reg; // @[decode.scala 270:17]\n", + " assign io_ex_use_rs2 = id_ex_ex_use_rs2_reg; // @[decode.scala 271:17]\n", + " assign io_id_rs1 = io_inst[19:15]; // @[decode.scala 274:23]\n", + " assign io_id_rs2 = io_inst[24:20]; // @[decode.scala 275:23]\n", + " assign io_use_rs1 = control_io_use_rs1; // @[decode.scala 276:14]\n", + " assign io_use_rs2 = control_io_use_rs2; // @[decode.scala 277:14]\n", + " assign control_io_opcode = io_inst[6:0]; // @[decode.scala 87:31]\n", + " assign control_io_funct7 = io_inst[31:25]; // @[decode.scala 88:31]\n", + " assign control_io_funct3 = io_inst[14:12]; // @[decode.scala 89:31]\n", + " assign regfile_clock = clock;\n", + " assign regfile_reset = reset;\n", + " assign regfile_io_id_rs1 = io_inst[19:15]; // @[decode.scala 91:31]\n", + " assign regfile_io_id_rs2 = io_inst[24:20]; // @[decode.scala 92:31]\n", + " assign regfile_io_wb_rd = io_wb_rd; // @[decode.scala 93:20]\n", + " assign regfile_io_writedata = io_writedata; // @[decode.scala 94:24]\n", + " assign regfile_io_wb_regwrite = io_wb_regwrite; // @[decode.scala 95:26]\n", + " assign immGen_io_inst = io_inst; // @[decode.scala 97:18]\n", + " always @(posedge clock) begin\n", + " if (reset) begin // @[decode.scala 57:29]\n", + " csr_read_reg <= 1'h0; // @[decode.scala 57:29]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " csr_read_reg <= 1'h0; // @[decode.scala 202:18]\n", + " end else if ((csrrwInst | csrrwiInst) & io_inst[11:7] == 5'h0) begin // @[decode.scala 111:66]\n", + " csr_read_reg <= 1'h0; // @[decode.scala 112:12]\n", + " end else begin\n", + " csr_read_reg <= csrInst;\n", + " end\n", + " if (reset) begin // @[decode.scala 58:30]\n", + " csr_write_reg <= 1'h0; // @[decode.scala 58:30]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " csr_write_reg <= 1'h0; // @[decode.scala 203:19]\n", + " end else if ((csrrsInst | csrrcInst | csrrsiInst | csrrciInst) & io_inst[19:15] == 5'h0) begin // @[decode.scala 114:94]\n", + " csr_write_reg <= 1'h0; // @[decode.scala 115:13]\n", + " end else begin\n", + " csr_write_reg <= csrInst;\n", + " end\n", + " if (reset) begin // @[decode.scala 59:32]\n", + " csr_address_reg <= 12'h0; // @[decode.scala 59:32]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " csr_address_reg <= 12'h0; // @[decode.scala 204:21]\n", + " end else begin\n", + " csr_address_reg <= io_inst[31:20]; // @[decode.scala 212:21]\n", + " end\n", + " if (reset) begin // @[decode.scala 60:31]\n", + " ecause_out_reg <= 4'h0; // @[decode.scala 60:31]\n", + " end else begin\n", + " ecause_out_reg <= {{2'd0}, _GEN_26};\n", + " end\n", + " if (reset) begin // @[decode.scala 61:34]\n", + " exception_out_reg <= 1'h0; // @[decode.scala 61:34]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " exception_out_reg <= 1'h0; // @[decode.scala 206:23]\n", + " end else if (isLegalInstruction) begin // @[decode.scala 176:26]\n", + " exception_out_reg <= 1'h0;\n", + " end else begin\n", + " exception_out_reg <= 1'h1;\n", + " end\n", + " if (reset) begin // @[decode.scala 62:29]\n", + " mret_out_reg <= 1'h0; // @[decode.scala 62:29]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " mret_out_reg <= 1'h0; // @[decode.scala 207:18]\n", + " end else begin\n", + " mret_out_reg <= mret_out; // @[decode.scala 215:18]\n", + " end\n", + " if (reset) begin // @[decode.scala 63:28]\n", + " wfi_out_reg <= 1'h0; // @[decode.scala 63:28]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " wfi_out_reg <= 1'h0; // @[decode.scala 208:17]\n", + " end else begin\n", + " wfi_out_reg <= wfi_out; // @[decode.scala 216:17]\n", + " end\n", + " if (reset) begin // @[decode.scala 64:29]\n", + " id_ex_pc_reg <= 32'h0; // @[decode.scala 64:29]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_pc_reg <= 32'h0; // @[decode.scala 181:18]\n", + " end else begin\n", + " id_ex_pc_reg <= io_id_pc; // @[decode.scala 217:18]\n", + " end\n", + " if (reset) begin // @[decode.scala 65:32]\n", + " id_ex_aluop_reg <= 4'h0; // @[decode.scala 65:32]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_aluop_reg <= 4'h0; // @[decode.scala 182:21]\n", + " end else begin\n", + " id_ex_aluop_reg <= control_io_aluop; // @[decode.scala 218:21]\n", + " end\n", + " if (reset) begin // @[decode.scala 66:33]\n", + " id_ex_immsrc_reg <= 1'h0; // @[decode.scala 66:33]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_immsrc_reg <= 1'h0; // @[decode.scala 183:22]\n", + " end else begin\n", + " id_ex_immsrc_reg <= control_io_immsrc; // @[decode.scala 219:22]\n", + " end\n", + " if (reset) begin // @[decode.scala 67:35]\n", + " id_ex_isbranch_reg <= 1'h0; // @[decode.scala 67:35]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_isbranch_reg <= 1'h0; // @[decode.scala 184:24]\n", + " end else begin\n", + " id_ex_isbranch_reg <= control_io_isbranch; // @[decode.scala 220:24]\n", + " end\n", + " if (reset) begin // @[decode.scala 68:34]\n", + " id_ex_memread_reg <= 1'h0; // @[decode.scala 68:34]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_memread_reg <= 1'h0; // @[decode.scala 185:23]\n", + " end else begin\n", + " id_ex_memread_reg <= control_io_memread; // @[decode.scala 221:23]\n", + " end\n", + " if (reset) begin // @[decode.scala 69:35]\n", + " id_ex_memwrite_reg <= 1'h0; // @[decode.scala 69:35]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_memwrite_reg <= 1'h0; // @[decode.scala 186:24]\n", + " end else begin\n", + " id_ex_memwrite_reg <= control_io_memwrite; // @[decode.scala 222:24]\n", + " end\n", + " if (reset) begin // @[decode.scala 70:35]\n", + " id_ex_regwrite_reg <= 1'h0; // @[decode.scala 70:35]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_regwrite_reg <= 1'h0; // @[decode.scala 187:24]\n", + " end else begin\n", + " id_ex_regwrite_reg <= control_io_regwrite; // @[decode.scala 223:24]\n", + " end\n", + " if (reset) begin // @[decode.scala 71:35]\n", + " id_ex_memtoreg_reg <= 2'h0; // @[decode.scala 71:35]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_memtoreg_reg <= 2'h0; // @[decode.scala 188:24]\n", + " end else begin\n", + " id_ex_memtoreg_reg <= control_io_memtoreg; // @[decode.scala 224:24]\n", + " end\n", + " if (reset) begin // @[decode.scala 72:32]\n", + " id_ex_pcsel_reg <= 1'h0; // @[decode.scala 72:32]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_pcsel_reg <= 1'h0; // @[decode.scala 189:21]\n", + " end else begin\n", + " id_ex_pcsel_reg <= control_io_pcsel; // @[decode.scala 225:21]\n", + " end\n", + " if (reset) begin // @[decode.scala 73:32]\n", + " id_ex_rdsel_reg <= 1'h0; // @[decode.scala 73:32]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_rdsel_reg <= 1'h0; // @[decode.scala 190:21]\n", + " end else begin\n", + " id_ex_rdsel_reg <= control_io_rdsel; // @[decode.scala 226:21]\n", + " end\n", + " if (reset) begin // @[decode.scala 74:33]\n", + " id_ex_isjump_reg <= 1'h0; // @[decode.scala 74:33]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_isjump_reg <= 1'h0; // @[decode.scala 191:22]\n", + " end else begin\n", + " id_ex_isjump_reg <= control_io_isjump; // @[decode.scala 227:22]\n", + " end\n", + " if (reset) begin // @[decode.scala 75:32]\n", + " id_ex_islui_reg <= 1'h0; // @[decode.scala 75:32]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_islui_reg <= 1'h0; // @[decode.scala 192:21]\n", + " end else begin\n", + " id_ex_islui_reg <= control_io_islui; // @[decode.scala 228:21]\n", + " end\n", + " if (reset) begin // @[decode.scala 76:35]\n", + " id_ex_rs1_data_reg <= 32'h0; // @[decode.scala 76:35]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_rs1_data_reg <= 32'h0; // @[decode.scala 193:24]\n", + " end else begin\n", + " id_ex_rs1_data_reg <= regfile_io_rs1_data; // @[decode.scala 229:24]\n", + " end\n", + " if (reset) begin // @[decode.scala 77:35]\n", + " id_ex_rs2_data_reg <= 32'h0; // @[decode.scala 77:35]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_rs2_data_reg <= 32'h0; // @[decode.scala 194:24]\n", + " end else begin\n", + " id_ex_rs2_data_reg <= regfile_io_rs2_data; // @[decode.scala 230:24]\n", + " end\n", + " if (reset) begin // @[decode.scala 78:30]\n", + " id_ex_imm_reg <= 32'h0; // @[decode.scala 78:30]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_imm_reg <= 32'h0; // @[decode.scala 195:19]\n", + " end else begin\n", + " id_ex_imm_reg <= immGen_io_imm; // @[decode.scala 231:19]\n", + " end\n", + " if (reset) begin // @[decode.scala 79:33]\n", + " id_ex_funct3_reg <= 3'h0; // @[decode.scala 79:33]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_funct3_reg <= 3'h0; // @[decode.scala 196:22]\n", + " end else begin\n", + " id_ex_funct3_reg <= io_inst[14:12]; // @[decode.scala 232:22]\n", + " end\n", + " if (reset) begin // @[decode.scala 80:33]\n", + " id_ex_ex_rs1_reg <= 5'h0; // @[decode.scala 80:33]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_ex_rs1_reg <= 5'h0; // @[decode.scala 197:22]\n", + " end else begin\n", + " id_ex_ex_rs1_reg <= io_inst[19:15]; // @[decode.scala 233:22]\n", + " end\n", + " if (reset) begin // @[decode.scala 81:33]\n", + " id_ex_ex_rs2_reg <= 5'h0; // @[decode.scala 81:33]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_ex_rs2_reg <= 5'h0; // @[decode.scala 198:22]\n", + " end else begin\n", + " id_ex_ex_rs2_reg <= io_inst[24:20]; // @[decode.scala 234:22]\n", + " end\n", + " if (reset) begin // @[decode.scala 82:32]\n", + " id_ex_ex_rd_reg <= 5'h0; // @[decode.scala 82:32]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_ex_rd_reg <= 5'h0; // @[decode.scala 199:21]\n", + " end else begin\n", + " id_ex_ex_rd_reg <= io_inst[11:7]; // @[decode.scala 235:21]\n", + " end\n", + " if (reset) begin // @[decode.scala 83:37]\n", + " id_ex_ex_use_rs1_reg <= 1'h0; // @[decode.scala 83:37]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_ex_use_rs1_reg <= 1'h0; // @[decode.scala 200:26]\n", + " end else begin\n", + " id_ex_ex_use_rs1_reg <= control_io_use_rs1; // @[decode.scala 236:26]\n", + " end\n", + " if (reset) begin // @[decode.scala 84:37]\n", + " id_ex_ex_use_rs2_reg <= 1'h0; // @[decode.scala 84:37]\n", + " end else if (io_id_ex_flush) begin // @[decode.scala 180:25]\n", + " id_ex_ex_use_rs2_reg <= 1'h0; // @[decode.scala 201:26]\n", + " end else begin\n", + " id_ex_ex_use_rs2_reg <= control_io_use_rs2; // @[decode.scala 237:26]\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " _RAND_0 = {1{`RANDOM}};\n", + " csr_read_reg = _RAND_0[0:0];\n", + " _RAND_1 = {1{`RANDOM}};\n", + " csr_write_reg = _RAND_1[0:0];\n", + " _RAND_2 = {1{`RANDOM}};\n", + " csr_address_reg = _RAND_2[11:0];\n", + " _RAND_3 = {1{`RANDOM}};\n", + " ecause_out_reg = _RAND_3[3:0];\n", + " _RAND_4 = {1{`RANDOM}};\n", + " exception_out_reg = _RAND_4[0:0];\n", + " _RAND_5 = {1{`RANDOM}};\n", + " mret_out_reg = _RAND_5[0:0];\n", + " _RAND_6 = {1{`RANDOM}};\n", + " wfi_out_reg = _RAND_6[0:0];\n", + " _RAND_7 = {1{`RANDOM}};\n", + " id_ex_pc_reg = _RAND_7[31:0];\n", + " _RAND_8 = {1{`RANDOM}};\n", + " id_ex_aluop_reg = _RAND_8[3:0];\n", + " _RAND_9 = {1{`RANDOM}};\n", + " id_ex_immsrc_reg = _RAND_9[0:0];\n", + " _RAND_10 = {1{`RANDOM}};\n", + " id_ex_isbranch_reg = _RAND_10[0:0];\n", + " _RAND_11 = {1{`RANDOM}};\n", + " id_ex_memread_reg = _RAND_11[0:0];\n", + " _RAND_12 = {1{`RANDOM}};\n", + " id_ex_memwrite_reg = _RAND_12[0:0];\n", + " _RAND_13 = {1{`RANDOM}};\n", + " id_ex_regwrite_reg = _RAND_13[0:0];\n", + " _RAND_14 = {1{`RANDOM}};\n", + " id_ex_memtoreg_reg = _RAND_14[1:0];\n", + " _RAND_15 = {1{`RANDOM}};\n", + " id_ex_pcsel_reg = _RAND_15[0:0];\n", + " _RAND_16 = {1{`RANDOM}};\n", + " id_ex_rdsel_reg = _RAND_16[0:0];\n", + " _RAND_17 = {1{`RANDOM}};\n", + " id_ex_isjump_reg = _RAND_17[0:0];\n", + " _RAND_18 = {1{`RANDOM}};\n", + " id_ex_islui_reg = _RAND_18[0:0];\n", + " _RAND_19 = {1{`RANDOM}};\n", + " id_ex_rs1_data_reg = _RAND_19[31:0];\n", + " _RAND_20 = {1{`RANDOM}};\n", + " id_ex_rs2_data_reg = _RAND_20[31:0];\n", + " _RAND_21 = {1{`RANDOM}};\n", + " id_ex_imm_reg = _RAND_21[31:0];\n", + " _RAND_22 = {1{`RANDOM}};\n", + " id_ex_funct3_reg = _RAND_22[2:0];\n", + " _RAND_23 = {1{`RANDOM}};\n", + " id_ex_ex_rs1_reg = _RAND_23[4:0];\n", + " _RAND_24 = {1{`RANDOM}};\n", + " id_ex_ex_rs2_reg = _RAND_24[4:0];\n", + " _RAND_25 = {1{`RANDOM}};\n", + " id_ex_ex_rd_reg = _RAND_25[4:0];\n", + " _RAND_26 = {1{`RANDOM}};\n", + " id_ex_ex_use_rs1_reg = _RAND_26[0:0];\n", + " _RAND_27 = {1{`RANDOM}};\n", + " id_ex_ex_use_rs2_reg = _RAND_27[0:0];\n", + "`endif // RANDOMIZE_REG_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n", + "module AluSelect(\n", + " input [31:0] io_rs1_data,\n", + " input [31:0] io_rs2_data,\n", + " input [31:0] io_imm,\n", + " input [31:0] io_mem_aluresult,\n", + " input [31:0] io_writedata,\n", + " input io_immsrc,\n", + " input io_islui,\n", + " input [1:0] io_forward1,\n", + " input [1:0] io_forward2,\n", + " output [31:0] io_alu_in1,\n", + " output [31:0] io_alu_in2\n", + ");\n", + " wire _select1_T = io_forward1 == 2'h0; // @[aluselect.scala 21:18]\n", + " wire _select1_T_1 = io_forward1 == 2'h1; // @[aluselect.scala 22:18]\n", + " wire _select1_T_2 = io_forward1 == 2'h2; // @[aluselect.scala 23:18]\n", + " wire [31:0] _select1_T_3 = _select1_T_2 ? io_writedata : io_rs1_data; // @[Mux.scala 101:16]\n", + " wire [31:0] _select1_T_4 = _select1_T_1 ? io_mem_aluresult : _select1_T_3; // @[Mux.scala 101:16]\n", + " wire [31:0] select1 = _select1_T ? io_rs1_data : _select1_T_4; // @[Mux.scala 101:16]\n", + " wire _select2_T = io_forward2 == 2'h0; // @[aluselect.scala 29:18]\n", + " wire _select2_T_1 = io_forward2 == 2'h1; // @[aluselect.scala 30:18]\n", + " wire _select2_T_2 = io_forward2 == 2'h2; // @[aluselect.scala 31:18]\n", + " wire [31:0] _select2_T_3 = _select2_T_2 ? io_writedata : io_rs2_data; // @[Mux.scala 101:16]\n", + " wire [31:0] _select2_T_4 = _select2_T_1 ? io_mem_aluresult : _select2_T_3; // @[Mux.scala 101:16]\n", + " wire [31:0] select2 = _select2_T ? io_rs2_data : _select2_T_4; // @[Mux.scala 101:16]\n", + " assign io_alu_in1 = io_islui ? 32'h0 : select1; // @[aluselect.scala 25:20]\n", + " assign io_alu_in2 = io_immsrc ? io_imm : select2; // @[aluselect.scala 33:20]\n", + "endmodule\n", + "module ALU(\n", + " input [31:0] io_alu_in1,\n", + " input [31:0] io_alu_in2,\n", + " input [3:0] io_aluop,\n", + " output io_zero,\n", + " output [31:0] io_alu_result\n", + ");\n", + " wire [31:0] add_result = io_alu_in1 + io_alu_in2; // @[alu.scala 13:31]\n", + " wire [31:0] sub_result = io_alu_in1 - io_alu_in2; // @[alu.scala 14:31]\n", + " wire [31:0] xor_result = io_alu_in1 ^ io_alu_in2; // @[alu.scala 15:31]\n", + " wire [31:0] or_result = io_alu_in1 | io_alu_in2; // @[alu.scala 16:30]\n", + " wire [31:0] and_result = io_alu_in1 & io_alu_in2; // @[alu.scala 17:31]\n", + " wire [62:0] _GEN_0 = {{31'd0}, io_alu_in1}; // @[alu.scala 18:31]\n", + " wire [62:0] sll_result = _GEN_0 << io_alu_in2[4:0]; // @[alu.scala 18:31]\n", + " wire [31:0] srl_result = io_alu_in1 >> io_alu_in2[4:0]; // @[alu.scala 19:31]\n", + " wire [31:0] sra_result = $signed(io_alu_in1) >>> io_alu_in2[4:0]; // @[alu.scala 20:60]\n", + " wire slt_result = $signed(io_alu_in1) < $signed(io_alu_in2); // @[alu.scala 21:38]\n", + " wire sltu_result = io_alu_in1 < io_alu_in2; // @[alu.scala 22:32]\n", + " wire [31:0] _io_alu_result_T_1 = 4'h0 == io_aluop ? add_result : 32'h0; // @[Mux.scala 81:58]\n", + " wire [31:0] _io_alu_result_T_3 = 4'h1 == io_aluop ? sub_result : _io_alu_result_T_1; // @[Mux.scala 81:58]\n", + " wire [31:0] _io_alu_result_T_5 = 4'h2 == io_aluop ? xor_result : _io_alu_result_T_3; // @[Mux.scala 81:58]\n", + " wire [31:0] _io_alu_result_T_7 = 4'h3 == io_aluop ? or_result : _io_alu_result_T_5; // @[Mux.scala 81:58]\n", + " wire [31:0] _io_alu_result_T_9 = 4'h4 == io_aluop ? and_result : _io_alu_result_T_7; // @[Mux.scala 81:58]\n", + " wire [62:0] _io_alu_result_T_11 = 4'h5 == io_aluop ? sll_result : {{31'd0}, _io_alu_result_T_9}; // @[Mux.scala 81:58]\n", + " wire [62:0] _io_alu_result_T_13 = 4'h6 == io_aluop ? {{31'd0}, srl_result} : _io_alu_result_T_11; // @[Mux.scala 81:58]\n", + " wire [62:0] _io_alu_result_T_15 = 4'h7 == io_aluop ? {{31'd0}, sra_result} : _io_alu_result_T_13; // @[Mux.scala 81:58]\n", + " wire [62:0] _io_alu_result_T_17 = 4'h8 == io_aluop ? {{62'd0}, slt_result} : _io_alu_result_T_15; // @[Mux.scala 81:58]\n", + " wire [62:0] _io_alu_result_T_19 = 4'h9 == io_aluop ? {{62'd0}, sltu_result} : _io_alu_result_T_17; // @[Mux.scala 81:58]\n", + " assign io_zero = io_alu_in1 == io_alu_in2; // @[alu.scala 24:26]\n", + " assign io_alu_result = _io_alu_result_T_19[31:0]; // @[alu.scala 26:17]\n", + "endmodule\n", + "module TargetGen(\n", + " input [31:0] io_ex_pc,\n", + " input [31:0] io_imm,\n", + " input [31:0] io_alu_result,\n", + " input io_pcsel,\n", + " input io_rdsel,\n", + " output [31:0] io_reg_pc,\n", + " output [31:0] io_target_pc\n", + ");\n", + " wire [31:0] _io_target_pc_T_1 = io_ex_pc + io_imm; // @[targetgen.scala 17:30]\n", + " wire [31:0] _io_reg_pc_T_3 = io_ex_pc + 32'h4; // @[targetgen.scala 23:27]\n", + " assign io_reg_pc = io_rdsel ? _io_target_pc_T_1 : _io_reg_pc_T_3; // @[targetgen.scala 20:26 21:15 23:15]\n", + " assign io_target_pc = io_pcsel ? io_alu_result : _io_target_pc_T_1; // @[targetgen.scala 14:26 15:18 17:18]\n", + "endmodule\n", + "module Execute(\n", + " input clock,\n", + " input reset,\n", + " input io_csr_read,\n", + " input io_csr_write,\n", + " input [11:0] io_csr_address,\n", + " input [3:0] io_ecause_in,\n", + " input io_exception_in,\n", + " input io_mret_in,\n", + " input io_wfi_in,\n", + " input [31:0] io_ex_pc,\n", + " input [3:0] io_aluop,\n", + " input io_immsrc,\n", + " input io_isbranch,\n", + " input io_memread,\n", + " input io_memwrite,\n", + " input io_regwrite,\n", + " input [1:0] io_memtoreg,\n", + " input io_pcsel,\n", + " input io_rdsel,\n", + " input io_isjump,\n", + " input io_islui,\n", + " input [31:0] io_rs1_data,\n", + " input [31:0] io_rs2_data,\n", + " input [31:0] io_imm,\n", + " input [31:0] io_funct3,\n", + " input [4:0] io_ex_rs1,\n", + " input [4:0] io_ex_rd,\n", + " output [31:0] io_mem_pc,\n", + " output [31:0] io_target_pc,\n", + " input [31:0] io_csr_read_data,\n", + " input io_readable,\n", + " input io_writeable,\n", + " output [31:0] io_csr_read_data_out,\n", + " output io_csr_write_enable_out,\n", + " output [11:0] io_csr_write_address_out,\n", + " output [31:0] io_csr_write_data_out,\n", + " output [3:0] io_ecause_out,\n", + " output io_exception_out,\n", + " output io_mret_out,\n", + " output io_wfi_out,\n", + " output [31:0] io_reg_pc,\n", + " output io_mem_isbranch,\n", + " output io_mem_isjump,\n", + " output io_mem_memread,\n", + " output io_mem_memwrite,\n", + " output io_mem_regwrite,\n", + " output [1:0] io_mem_memtoreg,\n", + " output io_mem_zero,\n", + " output [31:0] io_mem_aluresult,\n", + " output [31:0] io_mem_rs2_data,\n", + " output [2:0] io_mem_funct3,\n", + " output [4:0] io_mem_rd,\n", + " input [31:0] io_writedata,\n", + " input [1:0] io_forward1,\n", + " input [1:0] io_forward2,\n", + " input io_ex_mem_flush\n", + ");\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " reg [31:0] _RAND_0;\n", + " reg [31:0] _RAND_1;\n", + " reg [31:0] _RAND_2;\n", + " reg [31:0] _RAND_3;\n", + " reg [31:0] _RAND_4;\n", + " reg [31:0] _RAND_5;\n", + " reg [31:0] _RAND_6;\n", + " reg [31:0] _RAND_7;\n", + " reg [31:0] _RAND_8;\n", + " reg [31:0] _RAND_9;\n", + " reg [31:0] _RAND_10;\n", + " reg [31:0] _RAND_11;\n", + " reg [31:0] _RAND_12;\n", + " reg [31:0] _RAND_13;\n", + " reg [31:0] _RAND_14;\n", + " reg [31:0] _RAND_15;\n", + " reg [31:0] _RAND_16;\n", + " reg [31:0] _RAND_17;\n", + " reg [31:0] _RAND_18;\n", + " reg [31:0] _RAND_19;\n", + " reg [31:0] _RAND_20;\n", + " reg [31:0] _RAND_21;\n", + "`endif // RANDOMIZE_REG_INIT\n", + " wire [31:0] aluSelect_io_rs1_data; // @[execute.scala 69:25]\n", + " wire [31:0] aluSelect_io_rs2_data; // @[execute.scala 69:25]\n", + " wire [31:0] aluSelect_io_imm; // @[execute.scala 69:25]\n", + " wire [31:0] aluSelect_io_mem_aluresult; // @[execute.scala 69:25]\n", + " wire [31:0] aluSelect_io_writedata; // @[execute.scala 69:25]\n", + " wire aluSelect_io_immsrc; // @[execute.scala 69:25]\n", + " wire aluSelect_io_islui; // @[execute.scala 69:25]\n", + " wire [1:0] aluSelect_io_forward1; // @[execute.scala 69:25]\n", + " wire [1:0] aluSelect_io_forward2; // @[execute.scala 69:25]\n", + " wire [31:0] aluSelect_io_alu_in1; // @[execute.scala 69:25]\n", + " wire [31:0] aluSelect_io_alu_in2; // @[execute.scala 69:25]\n", + " wire [31:0] alu_io_alu_in1; // @[execute.scala 70:19]\n", + " wire [31:0] alu_io_alu_in2; // @[execute.scala 70:19]\n", + " wire [3:0] alu_io_aluop; // @[execute.scala 70:19]\n", + " wire alu_io_zero; // @[execute.scala 70:19]\n", + " wire [31:0] alu_io_alu_result; // @[execute.scala 70:19]\n", + " wire [31:0] targetGen_io_ex_pc; // @[execute.scala 71:25]\n", + " wire [31:0] targetGen_io_imm; // @[execute.scala 71:25]\n", + " wire [31:0] targetGen_io_alu_result; // @[execute.scala 71:25]\n", + " wire targetGen_io_pcsel; // @[execute.scala 71:25]\n", + " wire targetGen_io_rdsel; // @[execute.scala 71:25]\n", + " wire [31:0] targetGen_io_reg_pc; // @[execute.scala 71:25]\n", + " wire [31:0] targetGen_io_target_pc; // @[execute.scala 71:25]\n", + " reg mret_out_reg; // @[execute.scala 74:29]\n", + " reg wfi_out_reg; // @[execute.scala 75:28]\n", + " reg [3:0] ecause_out_reg; // @[execute.scala 76:31]\n", + " reg exception_out_reg; // @[execute.scala 77:34]\n", + " reg [31:0] csr_read_data_out_reg; // @[execute.scala 78:38]\n", + " reg csr_write_enable_out_reg; // @[execute.scala 79:41]\n", + " reg [11:0] csr_write_address_out_reg; // @[execute.scala 80:42]\n", + " reg [31:0] csr_write_data_out_reg; // @[execute.scala 81:39]\n", + " reg [31:0] reg_pc_reg; // @[execute.scala 82:27]\n", + " reg [31:0] target_pc_reg; // @[execute.scala 83:30]\n", + " reg [31:0] mem_pc_reg; // @[execute.scala 84:27]\n", + " reg mem_isbranch_reg; // @[execute.scala 85:33]\n", + " reg mem_isjump_reg; // @[execute.scala 86:31]\n", + " reg mem_memread_reg; // @[execute.scala 87:32]\n", + " reg mem_memwrite_reg; // @[execute.scala 88:33]\n", + " reg mem_regwrite_reg; // @[execute.scala 89:33]\n", + " reg [1:0] mem_memtoreg_reg; // @[execute.scala 90:33]\n", + " reg mem_zero_reg; // @[execute.scala 91:29]\n", + " reg [31:0] mem_aluresult_reg; // @[execute.scala 92:34]\n", + " reg [31:0] mem_rs2_data_reg; // @[execute.scala 93:33]\n", + " reg [2:0] mem_funct3_reg; // @[execute.scala 94:31]\n", + " reg [4:0] mem_rd_reg; // @[execute.scala 95:27]\n", + " wire _aluSelect_io_mem_aluresult_T = mem_memtoreg_reg == 2'h0; // @[execute.scala 104:21]\n", + " wire _aluSelect_io_mem_aluresult_T_1 = mem_memtoreg_reg == 2'h3; // @[execute.scala 105:21]\n", + " wire [31:0] _aluSelect_io_mem_aluresult_T_2 = _aluSelect_io_mem_aluresult_T_1 ? csr_read_data_out_reg :\n", + " mem_aluresult_reg; // @[Mux.scala 101:16]\n", + " wire [31:0] _csr_write_temp_T = {27'h0,io_ex_rs1}; // @[Cat.scala 31:58]\n", + " wire [31:0] csr_write_temp = io_immsrc ? _csr_write_temp_T : io_rs1_data; // @[execute.scala 124:27]\n", + " wire [31:0] _csr_write_out_T = io_csr_read_data | csr_write_temp; // @[execute.scala 128:35]\n", + " wire [31:0] _csr_write_out_T_2 = ~csr_write_temp; // @[execute.scala 130:37]\n", + " wire [31:0] _csr_write_out_T_3 = io_csr_read_data & _csr_write_out_T_2; // @[execute.scala 130:35]\n", + " wire [31:0] _csr_write_out_T_11 = 32'h2 == io_funct3 ? _csr_write_out_T : csr_write_temp; // @[Mux.scala 81:58]\n", + " wire [31:0] _csr_write_out_T_13 = 32'h6 == io_funct3 ? _csr_write_out_T : _csr_write_out_T_11; // @[Mux.scala 81:58]\n", + " wire csr_exception = io_csr_read != io_readable | io_csr_write != io_writeable; // @[execute.scala 135:53]\n", + " wire _ecause_out_reg_T_1 = ~io_exception_in & csr_exception; // @[execute.scala 164:48]\n", + " wire [31:0] _GEN_20 = io_ex_mem_flush ? 32'h0 : io_funct3; // @[execute.scala 138:25 159:24 182:24]\n", + " wire [31:0] _GEN_22 = reset ? 32'h0 : _GEN_20; // @[execute.scala 94:{31,31}]\n", + " AluSelect aluSelect ( // @[execute.scala 69:25]\n", + " .io_rs1_data(aluSelect_io_rs1_data),\n", + " .io_rs2_data(aluSelect_io_rs2_data),\n", + " .io_imm(aluSelect_io_imm),\n", + " .io_mem_aluresult(aluSelect_io_mem_aluresult),\n", + " .io_writedata(aluSelect_io_writedata),\n", + " .io_immsrc(aluSelect_io_immsrc),\n", + " .io_islui(aluSelect_io_islui),\n", + " .io_forward1(aluSelect_io_forward1),\n", + " .io_forward2(aluSelect_io_forward2),\n", + " .io_alu_in1(aluSelect_io_alu_in1),\n", + " .io_alu_in2(aluSelect_io_alu_in2)\n", + " );\n", + " ALU alu ( // @[execute.scala 70:19]\n", + " .io_alu_in1(alu_io_alu_in1),\n", + " .io_alu_in2(alu_io_alu_in2),\n", + " .io_aluop(alu_io_aluop),\n", + " .io_zero(alu_io_zero),\n", + " .io_alu_result(alu_io_alu_result)\n", + " );\n", + " TargetGen targetGen ( // @[execute.scala 71:25]\n", + " .io_ex_pc(targetGen_io_ex_pc),\n", + " .io_imm(targetGen_io_imm),\n", + " .io_alu_result(targetGen_io_alu_result),\n", + " .io_pcsel(targetGen_io_pcsel),\n", + " .io_rdsel(targetGen_io_rdsel),\n", + " .io_reg_pc(targetGen_io_reg_pc),\n", + " .io_target_pc(targetGen_io_target_pc)\n", + " );\n", + " assign io_mem_pc = mem_pc_reg; // @[execute.scala 197:19]\n", + " assign io_target_pc = target_pc_reg; // @[execute.scala 196:22]\n", + " assign io_csr_read_data_out = csr_read_data_out_reg; // @[execute.scala 191:30]\n", + " assign io_csr_write_enable_out = csr_write_enable_out_reg; // @[execute.scala 192:33]\n", + " assign io_csr_write_address_out = csr_write_address_out_reg; // @[execute.scala 193:34]\n", + " assign io_csr_write_data_out = csr_write_data_out_reg; // @[execute.scala 194:31]\n", + " assign io_ecause_out = ecause_out_reg; // @[execute.scala 189:23]\n", + " assign io_exception_out = exception_out_reg; // @[execute.scala 190:26]\n", + " assign io_mret_out = mret_out_reg; // @[execute.scala 187:21]\n", + " assign io_wfi_out = wfi_out_reg; // @[execute.scala 188:20]\n", + " assign io_reg_pc = reg_pc_reg; // @[execute.scala 195:19]\n", + " assign io_mem_isbranch = mem_isbranch_reg; // @[execute.scala 198:25]\n", + " assign io_mem_isjump = mem_isjump_reg; // @[execute.scala 199:23]\n", + " assign io_mem_memread = mem_memread_reg; // @[execute.scala 200:24]\n", + " assign io_mem_memwrite = mem_memwrite_reg; // @[execute.scala 201:25]\n", + " assign io_mem_regwrite = mem_regwrite_reg; // @[execute.scala 202:25]\n", + " assign io_mem_memtoreg = mem_memtoreg_reg; // @[execute.scala 203:25]\n", + " assign io_mem_zero = mem_zero_reg; // @[execute.scala 204:21]\n", + " assign io_mem_aluresult = mem_aluresult_reg; // @[execute.scala 205:26]\n", + " assign io_mem_rs2_data = mem_rs2_data_reg; // @[execute.scala 206:25]\n", + " assign io_mem_funct3 = mem_funct3_reg; // @[execute.scala 207:23]\n", + " assign io_mem_rd = mem_rd_reg; // @[execute.scala 208:19]\n", + " assign aluSelect_io_rs1_data = io_rs1_data; // @[execute.scala 100:25]\n", + " assign aluSelect_io_rs2_data = io_rs2_data; // @[execute.scala 101:25]\n", + " assign aluSelect_io_imm = io_imm; // @[execute.scala 102:20]\n", + " assign aluSelect_io_mem_aluresult = _aluSelect_io_mem_aluresult_T ? reg_pc_reg : _aluSelect_io_mem_aluresult_T_2; // @[Mux.scala 101:16]\n", + " assign aluSelect_io_writedata = io_writedata; // @[execute.scala 107:26]\n", + " assign aluSelect_io_immsrc = io_immsrc; // @[execute.scala 108:23]\n", + " assign aluSelect_io_islui = io_islui; // @[execute.scala 109:22]\n", + " assign aluSelect_io_forward1 = io_forward1; // @[execute.scala 110:25]\n", + " assign aluSelect_io_forward2 = io_forward2; // @[execute.scala 111:25]\n", + " assign alu_io_alu_in1 = aluSelect_io_alu_in1; // @[execute.scala 112:18]\n", + " assign alu_io_alu_in2 = aluSelect_io_alu_in2; // @[execute.scala 113:18]\n", + " assign alu_io_aluop = io_aluop; // @[execute.scala 114:16]\n", + " assign targetGen_io_ex_pc = io_ex_pc; // @[execute.scala 115:22]\n", + " assign targetGen_io_imm = io_imm; // @[execute.scala 116:20]\n", + " assign targetGen_io_alu_result = alu_io_alu_result; // @[execute.scala 117:27]\n", + " assign targetGen_io_pcsel = io_pcsel; // @[execute.scala 118:22]\n", + " assign targetGen_io_rdsel = io_rdsel; // @[execute.scala 119:22]\n", + " always @(posedge clock) begin\n", + " if (reset) begin // @[execute.scala 74:29]\n", + " mret_out_reg <= 1'h0; // @[execute.scala 74:29]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mret_out_reg <= 1'h0; // @[execute.scala 139:18]\n", + " end else begin\n", + " mret_out_reg <= io_mret_in; // @[execute.scala 162:22]\n", + " end\n", + " if (reset) begin // @[execute.scala 75:28]\n", + " wfi_out_reg <= 1'h0; // @[execute.scala 75:28]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " wfi_out_reg <= 1'h0; // @[execute.scala 140:17]\n", + " end else begin\n", + " wfi_out_reg <= io_wfi_in; // @[execute.scala 163:21]\n", + " end\n", + " if (reset) begin // @[execute.scala 76:31]\n", + " ecause_out_reg <= 4'h0; // @[execute.scala 76:31]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " ecause_out_reg <= 4'h0; // @[execute.scala 141:24]\n", + " end else if (~io_exception_in & csr_exception) begin // @[execute.scala 164:30]\n", + " ecause_out_reg <= 4'h2;\n", + " end else begin\n", + " ecause_out_reg <= io_ecause_in;\n", + " end\n", + " if (reset) begin // @[execute.scala 77:34]\n", + " exception_out_reg <= 1'h0; // @[execute.scala 77:34]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " exception_out_reg <= 1'h0; // @[execute.scala 142:27]\n", + " end else begin\n", + " exception_out_reg <= _ecause_out_reg_T_1 | io_exception_in; // @[execute.scala 165:27]\n", + " end\n", + " if (reset) begin // @[execute.scala 78:38]\n", + " csr_read_data_out_reg <= 32'h0; // @[execute.scala 78:38]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " csr_read_data_out_reg <= 32'h0; // @[execute.scala 143:31]\n", + " end else begin\n", + " csr_read_data_out_reg <= io_csr_read_data; // @[execute.scala 166:31]\n", + " end\n", + " if (reset) begin // @[execute.scala 79:41]\n", + " csr_write_enable_out_reg <= 1'h0; // @[execute.scala 79:41]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " csr_write_enable_out_reg <= 1'h0; // @[execute.scala 144:34]\n", + " end else begin\n", + " csr_write_enable_out_reg <= io_csr_write; // @[execute.scala 167:34]\n", + " end\n", + " if (reset) begin // @[execute.scala 80:42]\n", + " csr_write_address_out_reg <= 12'h0; // @[execute.scala 80:42]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " csr_write_address_out_reg <= 12'h0; // @[execute.scala 145:35]\n", + " end else begin\n", + " csr_write_address_out_reg <= io_csr_address; // @[execute.scala 168:35]\n", + " end\n", + " if (reset) begin // @[execute.scala 81:39]\n", + " csr_write_data_out_reg <= 32'h0; // @[execute.scala 81:39]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " csr_write_data_out_reg <= 32'h0; // @[execute.scala 146:32]\n", + " end else if (32'h7 == io_funct3) begin // @[Mux.scala 81:58]\n", + " csr_write_data_out_reg <= _csr_write_out_T_3;\n", + " end else if (32'h3 == io_funct3) begin // @[Mux.scala 81:58]\n", + " csr_write_data_out_reg <= _csr_write_out_T_3;\n", + " end else begin\n", + " csr_write_data_out_reg <= _csr_write_out_T_13;\n", + " end\n", + " if (reset) begin // @[execute.scala 82:27]\n", + " reg_pc_reg <= 32'h0; // @[execute.scala 82:27]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " reg_pc_reg <= 32'h0; // @[execute.scala 147:20]\n", + " end else begin\n", + " reg_pc_reg <= targetGen_io_reg_pc; // @[execute.scala 170:20]\n", + " end\n", + " if (reset) begin // @[execute.scala 83:30]\n", + " target_pc_reg <= 32'h0; // @[execute.scala 83:30]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " target_pc_reg <= 32'h0; // @[execute.scala 148:23]\n", + " end else begin\n", + " target_pc_reg <= targetGen_io_target_pc; // @[execute.scala 171:23]\n", + " end\n", + " if (reset) begin // @[execute.scala 84:27]\n", + " mem_pc_reg <= 32'h0; // @[execute.scala 84:27]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_pc_reg <= 32'h0; // @[execute.scala 149:20]\n", + " end else begin\n", + " mem_pc_reg <= io_ex_pc; // @[execute.scala 172:20]\n", + " end\n", + " if (reset) begin // @[execute.scala 85:33]\n", + " mem_isbranch_reg <= 1'h0; // @[execute.scala 85:33]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_isbranch_reg <= 1'h0; // @[execute.scala 150:26]\n", + " end else begin\n", + " mem_isbranch_reg <= io_isbranch; // @[execute.scala 173:26]\n", + " end\n", + " if (reset) begin // @[execute.scala 86:31]\n", + " mem_isjump_reg <= 1'h0; // @[execute.scala 86:31]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_isjump_reg <= 1'h0; // @[execute.scala 151:24]\n", + " end else begin\n", + " mem_isjump_reg <= io_isjump; // @[execute.scala 174:24]\n", + " end\n", + " if (reset) begin // @[execute.scala 87:32]\n", + " mem_memread_reg <= 1'h0; // @[execute.scala 87:32]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_memread_reg <= 1'h0; // @[execute.scala 152:25]\n", + " end else begin\n", + " mem_memread_reg <= io_memread; // @[execute.scala 175:25]\n", + " end\n", + " if (reset) begin // @[execute.scala 88:33]\n", + " mem_memwrite_reg <= 1'h0; // @[execute.scala 88:33]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_memwrite_reg <= 1'h0; // @[execute.scala 153:26]\n", + " end else begin\n", + " mem_memwrite_reg <= io_memwrite; // @[execute.scala 176:26]\n", + " end\n", + " if (reset) begin // @[execute.scala 89:33]\n", + " mem_regwrite_reg <= 1'h0; // @[execute.scala 89:33]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_regwrite_reg <= 1'h0; // @[execute.scala 154:26]\n", + " end else begin\n", + " mem_regwrite_reg <= io_regwrite; // @[execute.scala 177:26]\n", + " end\n", + " if (reset) begin // @[execute.scala 90:33]\n", + " mem_memtoreg_reg <= 2'h0; // @[execute.scala 90:33]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_memtoreg_reg <= 2'h0; // @[execute.scala 155:26]\n", + " end else begin\n", + " mem_memtoreg_reg <= io_memtoreg; // @[execute.scala 178:26]\n", + " end\n", + " if (reset) begin // @[execute.scala 91:29]\n", + " mem_zero_reg <= 1'h0; // @[execute.scala 91:29]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_zero_reg <= 1'h0; // @[execute.scala 156:22]\n", + " end else begin\n", + " mem_zero_reg <= alu_io_zero; // @[execute.scala 179:22]\n", + " end\n", + " if (reset) begin // @[execute.scala 92:34]\n", + " mem_aluresult_reg <= 32'h0; // @[execute.scala 92:34]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_aluresult_reg <= 32'h0; // @[execute.scala 157:27]\n", + " end else begin\n", + " mem_aluresult_reg <= alu_io_alu_result; // @[execute.scala 180:27]\n", + " end\n", + " if (reset) begin // @[execute.scala 93:33]\n", + " mem_rs2_data_reg <= 32'h0; // @[execute.scala 93:33]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_rs2_data_reg <= 32'h0; // @[execute.scala 158:26]\n", + " end else begin\n", + " mem_rs2_data_reg <= io_rs2_data; // @[execute.scala 181:26]\n", + " end\n", + " mem_funct3_reg <= _GEN_22[2:0]; // @[execute.scala 94:{31,31}]\n", + " if (reset) begin // @[execute.scala 95:27]\n", + " mem_rd_reg <= 5'h0; // @[execute.scala 95:27]\n", + " end else if (io_ex_mem_flush) begin // @[execute.scala 138:25]\n", + " mem_rd_reg <= 5'h0; // @[execute.scala 160:20]\n", + " end else begin\n", + " mem_rd_reg <= io_ex_rd; // @[execute.scala 183:20]\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " _RAND_0 = {1{`RANDOM}};\n", + " mret_out_reg = _RAND_0[0:0];\n", + " _RAND_1 = {1{`RANDOM}};\n", + " wfi_out_reg = _RAND_1[0:0];\n", + " _RAND_2 = {1{`RANDOM}};\n", + " ecause_out_reg = _RAND_2[3:0];\n", + " _RAND_3 = {1{`RANDOM}};\n", + " exception_out_reg = _RAND_3[0:0];\n", + " _RAND_4 = {1{`RANDOM}};\n", + " csr_read_data_out_reg = _RAND_4[31:0];\n", + " _RAND_5 = {1{`RANDOM}};\n", + " csr_write_enable_out_reg = _RAND_5[0:0];\n", + " _RAND_6 = {1{`RANDOM}};\n", + " csr_write_address_out_reg = _RAND_6[11:0];\n", + " _RAND_7 = {1{`RANDOM}};\n", + " csr_write_data_out_reg = _RAND_7[31:0];\n", + " _RAND_8 = {1{`RANDOM}};\n", + " reg_pc_reg = _RAND_8[31:0];\n", + " _RAND_9 = {1{`RANDOM}};\n", + " target_pc_reg = _RAND_9[31:0];\n", + " _RAND_10 = {1{`RANDOM}};\n", + " mem_pc_reg = _RAND_10[31:0];\n", + " _RAND_11 = {1{`RANDOM}};\n", + " mem_isbranch_reg = _RAND_11[0:0];\n", + " _RAND_12 = {1{`RANDOM}};\n", + " mem_isjump_reg = _RAND_12[0:0];\n", + " _RAND_13 = {1{`RANDOM}};\n", + " mem_memread_reg = _RAND_13[0:0];\n", + " _RAND_14 = {1{`RANDOM}};\n", + " mem_memwrite_reg = _RAND_14[0:0];\n", + " _RAND_15 = {1{`RANDOM}};\n", + " mem_regwrite_reg = _RAND_15[0:0];\n", + " _RAND_16 = {1{`RANDOM}};\n", + " mem_memtoreg_reg = _RAND_16[1:0];\n", + " _RAND_17 = {1{`RANDOM}};\n", + " mem_zero_reg = _RAND_17[0:0];\n", + " _RAND_18 = {1{`RANDOM}};\n", + " mem_aluresult_reg = _RAND_18[31:0];\n", + " _RAND_19 = {1{`RANDOM}};\n", + " mem_rs2_data_reg = _RAND_19[31:0];\n", + " _RAND_20 = {1{`RANDOM}};\n", + " mem_funct3_reg = _RAND_20[2:0];\n", + " _RAND_21 = {1{`RANDOM}};\n", + " mem_rd_reg = _RAND_21[4:0];\n", + "`endif // RANDOMIZE_REG_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n", + "module Branch(\n", + " input io_mem_zero,\n", + " input [31:0] io_mem_aluresult,\n", + " input [2:0] io_mem_funct3,\n", + " input io_mem_isbranch,\n", + " input io_mem_isjump,\n", + " output io_branch,\n", + " output io_pcsrc\n", + ");\n", + " wire branchEq = io_mem_funct3 == 3'h0 & io_mem_zero; // @[branch.scala 18:41]\n", + " wire branchNe = io_mem_funct3 == 3'h1 & ~io_mem_zero; // @[branch.scala 19:41]\n", + " wire branchLt = io_mem_funct3 == 3'h4 & io_mem_aluresult[0]; // @[branch.scala 20:41]\n", + " wire _branchGe_T_2 = ~io_mem_aluresult[0]; // @[branch.scala 21:44]\n", + " wire branchGe = io_mem_funct3 == 3'h5 & ~io_mem_aluresult[0]; // @[branch.scala 21:41]\n", + " wire branchLtu = io_mem_funct3 == 3'h6 & io_mem_aluresult[0]; // @[branch.scala 22:41]\n", + " wire branchGeu = io_mem_funct3 == 3'h7 & _branchGe_T_2; // @[branch.scala 23:41]\n", + " assign io_branch = io_mem_isbranch; // @[branch.scala 25:13]\n", + " assign io_pcsrc = io_mem_isjump | (branchEq | branchNe | branchLt | branchGe | branchLtu | branchGeu) &\n", + " io_mem_isbranch; // @[branch.scala 26:22]\n", + "endmodule\n", + "module Memory(\n", + " input clock,\n", + " input reset,\n", + " input [31:0] io_csr_read_data_in,\n", + " input io_csr_write_enable_in,\n", + " input [11:0] io_csr_write_address_in,\n", + " input [31:0] io_csr_write_data_in,\n", + " input [3:0] io_ecause_in,\n", + " input io_exception_in,\n", + " input io_mret_in,\n", + " input io_wfi_in,\n", + " input [31:0] io_reg_pc,\n", + " input io_mem_isbranch,\n", + " input io_mem_isjump,\n", + " input io_mem_memread,\n", + " input io_mem_memwrite,\n", + " input io_mem_regwrite,\n", + " input [1:0] io_mem_memtoreg,\n", + " input io_mem_zero,\n", + " input [31:0] io_mem_aluresult,\n", + " input [31:0] io_mem_rs2_data,\n", + " input [2:0] io_mem_funct3,\n", + " input [4:0] io_mem_rd,\n", + " input io_sip,\n", + " input io_tip,\n", + " input io_eip,\n", + " output io_csr_write_enable_out,\n", + " output [11:0] io_csr_write_address_out,\n", + " output [31:0] io_csr_write_data_out,\n", + " output [3:0] io_ecause_out,\n", + " output io_trapped,\n", + " output io_interrupt,\n", + " output io_inst_retired,\n", + " output io_mret_out,\n", + " output [31:0] io_csr_read_data_out,\n", + " output [31:0] io_wb_reg_pc,\n", + " output [31:0] io_wb_readdata,\n", + " output [31:0] io_wb_aluresult,\n", + " output [1:0] io_wb_memtoreg,\n", + " output io_wb_regwrite,\n", + " output [4:0] io_wb_rd,\n", + " output io_pcsrc,\n", + " output io_branch,\n", + " input io_mem_wb_flush,\n", + " input [31:0] io_memory_read_data,\n", + " output io_load_store_unsigned,\n", + " output [1:0] io_memory_size,\n", + " output [31:0] io_memory_address,\n", + " output [31:0] io_memory_write_data,\n", + " output io_memory_read,\n", + " output io_memory_write\n", + ");\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " reg [31:0] _RAND_0;\n", + " reg [31:0] _RAND_1;\n", + " reg [31:0] _RAND_2;\n", + " reg [31:0] _RAND_3;\n", + " reg [31:0] _RAND_4;\n", + " reg [31:0] _RAND_5;\n", + " reg [31:0] _RAND_6;\n", + " reg [31:0] _RAND_7;\n", + " reg [31:0] _RAND_8;\n", + " reg [31:0] _RAND_9;\n", + " reg [31:0] _RAND_10;\n", + " reg [31:0] _RAND_11;\n", + " reg [31:0] _RAND_12;\n", + " reg [31:0] _RAND_13;\n", + " reg [31:0] _RAND_14;\n", + " reg [31:0] _RAND_15;\n", + " reg [31:0] _RAND_16;\n", + "`endif // RANDOMIZE_REG_INIT\n", + " wire branch_io_mem_zero; // @[memory.scala 102:22]\n", + " wire [31:0] branch_io_mem_aluresult; // @[memory.scala 102:22]\n", + " wire [2:0] branch_io_mem_funct3; // @[memory.scala 102:22]\n", + " wire branch_io_mem_isbranch; // @[memory.scala 102:22]\n", + " wire branch_io_mem_isjump; // @[memory.scala 102:22]\n", + " wire branch_io_branch; // @[memory.scala 102:22]\n", + " wire branch_io_pcsrc; // @[memory.scala 102:22]\n", + " wire load_exception = io_mem_memread & io_mem_rd != 5'h0; // @[memory.scala 66:39]\n", + " wire mem_misaligned_exception = (io_mem_memread | io_mem_memwrite) & io_mem_aluresult[1:0] != 2'h0; // @[memory.scala 67:70]\n", + " wire _T = ~io_exception_in; // @[memory.scala 83:14]\n", + " wire [2:0] _ecause_out_T = io_mem_memread ? 3'h4 : 3'h6; // @[memory.scala 89:22]\n", + " wire _GEN_0 = _T & mem_misaligned_exception | io_exception_in; // @[memory.scala 87:60 88:15 92:15]\n", + " wire [3:0] _GEN_1 = _T & mem_misaligned_exception ? {{1'd0}, _ecause_out_T} : io_ecause_in; // @[memory.scala 87:60 89:16 93:16]\n", + " wire _GEN_3 = ~io_exception_in & load_exception | _GEN_0; // @[memory.scala 83:50 84:15]\n", + " wire [3:0] _GEN_4 = ~io_exception_in & load_exception ? 4'h5 : _GEN_1; // @[memory.scala 83:50 85:16]\n", + " wire [3:0] _GEN_6 = io_sip ? 4'h3 : _GEN_4; // @[memory.scala 80:22 81:16]\n", + " wire _GEN_8 = io_sip ? 1'h0 : _GEN_3; // @[memory.scala 80:22]\n", + " wire _GEN_10 = io_tip | io_sip; // @[memory.scala 77:22 79:15]\n", + " wire _GEN_11 = io_tip ? 1'h0 : _GEN_8; // @[memory.scala 77:22]\n", + " wire interrupt = io_eip | _GEN_10; // @[memory.scala 74:16 76:15]\n", + " wire exception = io_eip ? 1'h0 : _GEN_11; // @[memory.scala 74:16]\n", + " wire trapped = io_sip | io_tip | io_eip | exception; // @[memory.scala 97:42]\n", + " wire retired = ~trapped & ~io_wfi_in; // @[memory.scala 98:23]\n", + " reg csr_write_enable_out_reg; // @[memory.scala 118:41]\n", + " reg [11:0] csr_write_address_out_reg; // @[memory.scala 119:42]\n", + " reg [31:0] csr_write_data_out_reg; // @[memory.scala 120:39]\n", + " reg [3:0] ecause_out_reg; // @[memory.scala 121:31]\n", + " reg trapped_reg; // @[memory.scala 122:28]\n", + " reg interrupt_reg; // @[memory.scala 123:30]\n", + " reg inst_retired_reg; // @[memory.scala 124:33]\n", + " reg [31:0] csr_read_data_out_reg; // @[memory.scala 125:38]\n", + " reg mret_out_reg; // @[memory.scala 126:29]\n", + " reg [31:0] wb_reg_pc_reg; // @[memory.scala 128:30]\n", + " reg [31:0] wb_readdata_reg; // @[memory.scala 129:32]\n", + " reg [31:0] wb_aluresult_reg; // @[memory.scala 130:33]\n", + " reg [1:0] wb_memtoreg_reg; // @[memory.scala 131:32]\n", + " reg wb_regwrite_reg; // @[memory.scala 132:32]\n", + " reg [4:0] wb_rd_reg; // @[memory.scala 133:26]\n", + " reg pcsrc_reg; // @[memory.scala 134:26]\n", + " reg branch_reg; // @[memory.scala 135:27]\n", + " wire _T_4 = ~io_mem_wb_flush; // @[memory.scala 139:8]\n", + " wire _GEN_15 = ~io_mem_wb_flush & io_csr_write_enable_in; // @[memory.scala 139:26 140:30 149:30]\n", + " wire _GEN_19 = ~io_mem_wb_flush & trapped; // @[memory.scala 139:26 144:17 153:17]\n", + " wire _GEN_20 = ~io_mem_wb_flush & interrupt; // @[memory.scala 139:26 145:19 154:19]\n", + " wire _GEN_21 = ~io_mem_wb_flush & retired; // @[memory.scala 139:26 146:22 155:22]\n", + " wire _GEN_22 = ~io_mem_wb_flush & io_mret_in; // @[memory.scala 139:26 147:18 156:18]\n", + " wire _GEN_29 = _T_4 & io_mem_regwrite; // @[memory.scala 160:26 167:21 176:21]\n", + " wire _GEN_31 = _T_4 & branch_io_pcsrc; // @[memory.scala 181:26 182:15 185:15]\n", + " wire _GEN_32 = _T_4 & branch_io_branch; // @[memory.scala 181:26 183:16 186:16]\n", + " Branch branch ( // @[memory.scala 102:22]\n", + " .io_mem_zero(branch_io_mem_zero),\n", + " .io_mem_aluresult(branch_io_mem_aluresult),\n", + " .io_mem_funct3(branch_io_mem_funct3),\n", + " .io_mem_isbranch(branch_io_mem_isbranch),\n", + " .io_mem_isjump(branch_io_mem_isjump),\n", + " .io_branch(branch_io_branch),\n", + " .io_pcsrc(branch_io_pcsrc)\n", + " );\n", + " assign io_csr_write_enable_out = csr_write_enable_out_reg; // @[memory.scala 190:27]\n", + " assign io_csr_write_address_out = csr_write_address_out_reg; // @[memory.scala 191:28]\n", + " assign io_csr_write_data_out = csr_write_data_out_reg; // @[memory.scala 192:25]\n", + " assign io_ecause_out = ecause_out_reg; // @[memory.scala 193:17]\n", + " assign io_trapped = trapped_reg; // @[memory.scala 194:14]\n", + " assign io_interrupt = interrupt_reg; // @[memory.scala 195:16]\n", + " assign io_inst_retired = inst_retired_reg; // @[memory.scala 196:19]\n", + " assign io_mret_out = mret_out_reg; // @[memory.scala 198:15]\n", + " assign io_csr_read_data_out = csr_read_data_out_reg; // @[memory.scala 197:24]\n", + " assign io_wb_reg_pc = wb_reg_pc_reg; // @[memory.scala 200:16]\n", + " assign io_wb_readdata = wb_readdata_reg; // @[memory.scala 201:18]\n", + " assign io_wb_aluresult = wb_aluresult_reg; // @[memory.scala 202:19]\n", + " assign io_wb_memtoreg = wb_memtoreg_reg; // @[memory.scala 203:18]\n", + " assign io_wb_regwrite = wb_regwrite_reg; // @[memory.scala 204:18]\n", + " assign io_wb_rd = wb_rd_reg; // @[memory.scala 205:12]\n", + " assign io_pcsrc = pcsrc_reg; // @[memory.scala 206:12]\n", + " assign io_branch = branch_reg; // @[memory.scala 207:13]\n", + " assign io_load_store_unsigned = io_mem_funct3[2]; // @[memory.scala 113:42]\n", + " assign io_memory_size = io_mem_funct3[1:0]; // @[memory.scala 114:34]\n", + " assign io_memory_address = io_mem_aluresult; // @[memory.scala 110:21]\n", + " assign io_memory_write_data = io_mem_rs2_data; // @[memory.scala 111:24]\n", + " assign io_memory_read = io_mem_memread; // @[memory.scala 112:18]\n", + " assign io_memory_write = io_mem_memwrite & trapped; // @[memory.scala 115:38]\n", + " assign branch_io_mem_zero = io_mem_zero; // @[memory.scala 103:22]\n", + " assign branch_io_mem_aluresult = io_mem_aluresult; // @[memory.scala 104:27]\n", + " assign branch_io_mem_funct3 = io_mem_funct3; // @[memory.scala 105:24]\n", + " assign branch_io_mem_isbranch = io_mem_isbranch; // @[memory.scala 106:26]\n", + " assign branch_io_mem_isjump = io_mem_isjump; // @[memory.scala 107:24]\n", + " always @(posedge clock) begin\n", + " if (reset) begin // @[memory.scala 118:41]\n", + " csr_write_enable_out_reg <= 1'h0; // @[memory.scala 118:41]\n", + " end else begin\n", + " csr_write_enable_out_reg <= _GEN_15;\n", + " end\n", + " if (reset) begin // @[memory.scala 119:42]\n", + " csr_write_address_out_reg <= 12'h0; // @[memory.scala 119:42]\n", + " end else if (~io_mem_wb_flush) begin // @[memory.scala 139:26]\n", + " csr_write_address_out_reg <= io_csr_write_address_in; // @[memory.scala 141:31]\n", + " end else begin\n", + " csr_write_address_out_reg <= 12'h0; // @[memory.scala 150:31]\n", + " end\n", + " if (reset) begin // @[memory.scala 120:39]\n", + " csr_write_data_out_reg <= 32'h0; // @[memory.scala 120:39]\n", + " end else if (~io_mem_wb_flush) begin // @[memory.scala 139:26]\n", + " csr_write_data_out_reg <= io_csr_write_data_in; // @[memory.scala 142:28]\n", + " end else begin\n", + " csr_write_data_out_reg <= 32'h0; // @[memory.scala 151:28]\n", + " end\n", + " if (reset) begin // @[memory.scala 121:31]\n", + " ecause_out_reg <= 4'h0; // @[memory.scala 121:31]\n", + " end else if (~io_mem_wb_flush) begin // @[memory.scala 139:26]\n", + " if (io_eip) begin // @[memory.scala 74:16]\n", + " ecause_out_reg <= 4'hb; // @[memory.scala 75:16]\n", + " end else if (io_tip) begin // @[memory.scala 77:22]\n", + " ecause_out_reg <= 4'h7; // @[memory.scala 78:16]\n", + " end else begin\n", + " ecause_out_reg <= _GEN_6;\n", + " end\n", + " end else begin\n", + " ecause_out_reg <= 4'h0; // @[memory.scala 152:20]\n", + " end\n", + " if (reset) begin // @[memory.scala 122:28]\n", + " trapped_reg <= 1'h0; // @[memory.scala 122:28]\n", + " end else begin\n", + " trapped_reg <= _GEN_19;\n", + " end\n", + " if (reset) begin // @[memory.scala 123:30]\n", + " interrupt_reg <= 1'h0; // @[memory.scala 123:30]\n", + " end else begin\n", + " interrupt_reg <= _GEN_20;\n", + " end\n", + " if (reset) begin // @[memory.scala 124:33]\n", + " inst_retired_reg <= 1'h0; // @[memory.scala 124:33]\n", + " end else begin\n", + " inst_retired_reg <= _GEN_21;\n", + " end\n", + " if (reset) begin // @[memory.scala 125:38]\n", + " csr_read_data_out_reg <= 32'h0; // @[memory.scala 125:38]\n", + " end else if (_T_4) begin // @[memory.scala 160:26]\n", + " csr_read_data_out_reg <= io_csr_read_data_in; // @[memory.scala 161:27]\n", + " end else begin\n", + " csr_read_data_out_reg <= 32'h0; // @[memory.scala 170:27]\n", + " end\n", + " if (reset) begin // @[memory.scala 126:29]\n", + " mret_out_reg <= 1'h0; // @[memory.scala 126:29]\n", + " end else begin\n", + " mret_out_reg <= _GEN_22;\n", + " end\n", + " if (reset) begin // @[memory.scala 128:30]\n", + " wb_reg_pc_reg <= 32'h0; // @[memory.scala 128:30]\n", + " end else if (_T_4) begin // @[memory.scala 160:26]\n", + " wb_reg_pc_reg <= io_reg_pc; // @[memory.scala 163:19]\n", + " end else begin\n", + " wb_reg_pc_reg <= 32'h0; // @[memory.scala 172:19]\n", + " end\n", + " if (reset) begin // @[memory.scala 129:32]\n", + " wb_readdata_reg <= 32'h0; // @[memory.scala 129:32]\n", + " end else if (_T_4) begin // @[memory.scala 160:26]\n", + " wb_readdata_reg <= io_memory_read_data; // @[memory.scala 164:21]\n", + " end else begin\n", + " wb_readdata_reg <= 32'h0; // @[memory.scala 173:21]\n", + " end\n", + " if (reset) begin // @[memory.scala 130:33]\n", + " wb_aluresult_reg <= 32'h0; // @[memory.scala 130:33]\n", + " end else if (_T_4) begin // @[memory.scala 160:26]\n", + " wb_aluresult_reg <= io_mem_aluresult; // @[memory.scala 165:22]\n", + " end else begin\n", + " wb_aluresult_reg <= 32'h0; // @[memory.scala 174:22]\n", + " end\n", + " if (reset) begin // @[memory.scala 131:32]\n", + " wb_memtoreg_reg <= 2'h0; // @[memory.scala 131:32]\n", + " end else if (_T_4) begin // @[memory.scala 160:26]\n", + " wb_memtoreg_reg <= io_mem_memtoreg; // @[memory.scala 166:21]\n", + " end else begin\n", + " wb_memtoreg_reg <= 2'h0; // @[memory.scala 175:21]\n", + " end\n", + " if (reset) begin // @[memory.scala 132:32]\n", + " wb_regwrite_reg <= 1'h0; // @[memory.scala 132:32]\n", + " end else begin\n", + " wb_regwrite_reg <= _GEN_29;\n", + " end\n", + " if (reset) begin // @[memory.scala 133:26]\n", + " wb_rd_reg <= 5'h0; // @[memory.scala 133:26]\n", + " end else if (_T_4) begin // @[memory.scala 160:26]\n", + " wb_rd_reg <= io_mem_rd; // @[memory.scala 168:15]\n", + " end else begin\n", + " wb_rd_reg <= 5'h0; // @[memory.scala 177:15]\n", + " end\n", + " if (reset) begin // @[memory.scala 134:26]\n", + " pcsrc_reg <= 1'h0; // @[memory.scala 134:26]\n", + " end else begin\n", + " pcsrc_reg <= _GEN_31;\n", + " end\n", + " if (reset) begin // @[memory.scala 135:27]\n", + " branch_reg <= 1'h0; // @[memory.scala 135:27]\n", + " end else begin\n", + " branch_reg <= _GEN_32;\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " _RAND_0 = {1{`RANDOM}};\n", + " csr_write_enable_out_reg = _RAND_0[0:0];\n", + " _RAND_1 = {1{`RANDOM}};\n", + " csr_write_address_out_reg = _RAND_1[11:0];\n", + " _RAND_2 = {1{`RANDOM}};\n", + " csr_write_data_out_reg = _RAND_2[31:0];\n", + " _RAND_3 = {1{`RANDOM}};\n", + " ecause_out_reg = _RAND_3[3:0];\n", + " _RAND_4 = {1{`RANDOM}};\n", + " trapped_reg = _RAND_4[0:0];\n", + " _RAND_5 = {1{`RANDOM}};\n", + " interrupt_reg = _RAND_5[0:0];\n", + " _RAND_6 = {1{`RANDOM}};\n", + " inst_retired_reg = _RAND_6[0:0];\n", + " _RAND_7 = {1{`RANDOM}};\n", + " csr_read_data_out_reg = _RAND_7[31:0];\n", + " _RAND_8 = {1{`RANDOM}};\n", + " mret_out_reg = _RAND_8[0:0];\n", + " _RAND_9 = {1{`RANDOM}};\n", + " wb_reg_pc_reg = _RAND_9[31:0];\n", + " _RAND_10 = {1{`RANDOM}};\n", + " wb_readdata_reg = _RAND_10[31:0];\n", + " _RAND_11 = {1{`RANDOM}};\n", + " wb_aluresult_reg = _RAND_11[31:0];\n", + " _RAND_12 = {1{`RANDOM}};\n", + " wb_memtoreg_reg = _RAND_12[1:0];\n", + " _RAND_13 = {1{`RANDOM}};\n", + " wb_regwrite_reg = _RAND_13[0:0];\n", + " _RAND_14 = {1{`RANDOM}};\n", + " wb_rd_reg = _RAND_14[4:0];\n", + " _RAND_15 = {1{`RANDOM}};\n", + " pcsrc_reg = _RAND_15[0:0];\n", + " _RAND_16 = {1{`RANDOM}};\n", + " branch_reg = _RAND_16[0:0];\n", + "`endif // RANDOMIZE_REG_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n", + "module Writeback(\n", + " input [31:0] io_csr_read_data_in,\n", + " input [31:0] io_wb_reg_pc,\n", + " input [31:0] io_wb_readdata,\n", + " input [31:0] io_wb_aluresult,\n", + " input [1:0] io_wb_memtoreg,\n", + " output [31:0] io_writedata\n", + ");\n", + " wire [31:0] _io_writedata_T_1 = 2'h1 == io_wb_memtoreg ? io_wb_readdata : io_wb_reg_pc; // @[Mux.scala 81:58]\n", + " wire [31:0] _io_writedata_T_3 = 2'h2 == io_wb_memtoreg ? io_wb_aluresult : _io_writedata_T_1; // @[Mux.scala 81:58]\n", + " assign io_writedata = 2'h3 == io_wb_memtoreg ? io_csr_read_data_in : _io_writedata_T_3; // @[Mux.scala 81:58]\n", + "endmodule\n", + "module CSR(\n", + " input clock,\n", + " input reset,\n", + " input io_meip,\n", + " input [11:0] io_csr_address,\n", + " input [31:0] io_mem_pc,\n", + " output [31:0] io_csr_read_data,\n", + " output io_readable,\n", + " output io_writeable,\n", + " input io_csr_write_enable,\n", + " input [11:0] io_csr_write_address,\n", + " input [31:0] io_csr_write_data,\n", + " input io_inst_retired,\n", + " input io_trapped,\n", + " input io_mret,\n", + " input [2:0] io_ecause,\n", + " input io_interrupt,\n", + " output io_eip,\n", + " output io_tip,\n", + " output io_sip,\n", + " output [31:0] io_trap_vector,\n", + " output [31:0] io_mret_vector\n", + ");\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " reg [63:0] _RAND_0;\n", + " reg [63:0] _RAND_1;\n", + " reg [31:0] _RAND_2;\n", + " reg [31:0] _RAND_3;\n", + " reg [31:0] _RAND_4;\n", + " reg [31:0] _RAND_5;\n", + " reg [31:0] _RAND_6;\n", + " reg [31:0] _RAND_7;\n", + " reg [31:0] _RAND_8;\n", + " reg [31:0] _RAND_9;\n", + " reg [31:0] _RAND_10;\n", + " reg [31:0] _RAND_11;\n", + " reg [31:0] _RAND_12;\n", + " reg [31:0] _RAND_13;\n", + "`endif // RANDOMIZE_REG_INIT\n", + " reg [63:0] mcycle; // @[csr.scala 41:23]\n", + " reg [63:0] minstret; // @[csr.scala 42:25]\n", + " reg [31:0] mepc; // @[csr.scala 44:21]\n", + " reg [31:0] mscratch; // @[csr.scala 45:25]\n", + " reg [31:0] mtvec; // @[csr.scala 46:22]\n", + " reg [3:0] mcause; // @[csr.scala 47:23]\n", + " reg minterrupt; // @[csr.scala 48:27]\n", + " reg pie; // @[csr.scala 50:20]\n", + " reg ie; // @[csr.scala 51:19]\n", + " reg meie; // @[csr.scala 52:21]\n", + " reg msie; // @[csr.scala 53:21]\n", + " reg msip; // @[csr.scala 54:21]\n", + " reg mtie; // @[csr.scala 55:21]\n", + " reg mtip; // @[csr.scala 56:21]\n", + " wire [31:0] _csr_read_data_T_3 = {21'h0,3'h0,pie,2'h0,1'h0,ie,1'h0,2'h0}; // @[Cat.scala 31:58]\n", + " wire [31:0] _csr_read_data_T_5 = {20'h0,io_meip,2'h0,1'h0,mtip,1'h0,2'h0,msip,3'h0}; // @[Cat.scala 31:58]\n", + " wire [31:0] _csr_read_data_T_6 = {20'h0,meie,2'h0,1'h0,mtie,1'h0,2'h0,msie,3'h0}; // @[Cat.scala 31:58]\n", + " wire [31:0] _csr_read_data_T_8 = {mtvec[31:2],2'h0}; // @[Cat.scala 31:58]\n", + " wire [31:0] _csr_read_data_T_9 = {minterrupt,27'h0,mcause}; // @[Cat.scala 31:58]\n", + " wire [31:0] _GEN_0 = 12'hb02 == io_csr_address ? minstret[31:0] : 32'h0; // @[csr.scala 141:21 69:26]\n", + " wire [31:0] _GEN_2 = 12'hb00 == io_csr_address | 12'hb01 == io_csr_address ? mcycle[31:0] : _GEN_0; // @[csr.scala 136:21 69:26]\n", + " wire _GEN_3 = 12'hb00 == io_csr_address | 12'hb01 == io_csr_address | 12'hb02 == io_csr_address; // @[csr.scala 137:16 69:26]\n", + " wire [31:0] _GEN_4 = 12'h343 == io_csr_address ? 32'h0 : _GEN_2; // @[csr.scala 131:21 69:26]\n", + " wire _GEN_5 = 12'h343 == io_csr_address | _GEN_3; // @[csr.scala 132:16 69:26]\n", + " wire [31:0] _GEN_6 = 12'h342 == io_csr_address ? _csr_read_data_T_9 : _GEN_4; // @[csr.scala 126:21 69:26]\n", + " wire _GEN_7 = 12'h342 == io_csr_address | _GEN_5; // @[csr.scala 127:16 69:26]\n", + " wire [31:0] _GEN_8 = 12'h341 == io_csr_address ? mepc : _GEN_6; // @[csr.scala 121:21 69:26]\n", + " wire _GEN_9 = 12'h341 == io_csr_address | _GEN_7; // @[csr.scala 122:16 69:26]\n", + " wire [31:0] _GEN_10 = 12'h340 == io_csr_address ? mscratch : _GEN_8; // @[csr.scala 116:21 69:26]\n", + " wire _GEN_11 = 12'h340 == io_csr_address | _GEN_9; // @[csr.scala 117:16 69:26]\n", + " wire [31:0] _GEN_12 = 12'h305 == io_csr_address ? _csr_read_data_T_8 : _GEN_10; // @[csr.scala 111:21 69:26]\n", + " wire _GEN_13 = 12'h305 == io_csr_address | _GEN_11; // @[csr.scala 112:16 69:26]\n", + " wire [31:0] _GEN_14 = 12'h304 == io_csr_address ? _csr_read_data_T_6 : _GEN_12; // @[csr.scala 106:21 69:26]\n", + " wire _GEN_15 = 12'h304 == io_csr_address | _GEN_13; // @[csr.scala 107:16 69:26]\n", + " wire [31:0] _GEN_16 = 12'h344 == io_csr_address ? _csr_read_data_T_5 : _GEN_14; // @[csr.scala 101:21 69:26]\n", + " wire _GEN_17 = 12'h344 == io_csr_address | _GEN_15; // @[csr.scala 102:16 69:26]\n", + " wire [31:0] _GEN_18 = 12'h301 == io_csr_address ? 32'h40000100 : _GEN_16; // @[csr.scala 69:26 96:21]\n", + " wire _GEN_19 = 12'h301 == io_csr_address | _GEN_17; // @[csr.scala 69:26 97:16]\n", + " wire [31:0] _GEN_20 = 12'h300 == io_csr_address ? _csr_read_data_T_3 : _GEN_18; // @[csr.scala 69:26 91:21]\n", + " wire _GEN_21 = 12'h300 == io_csr_address | _GEN_19; // @[csr.scala 69:26 92:16]\n", + " wire [31:0] _GEN_22 = 12'hf11 == io_csr_address | 12'hf12 == io_csr_address | 12'hf13 == io_csr_address | 12'hf14 ==\n", + " io_csr_address ? 32'h0 : _GEN_20; // @[csr.scala 69:26 86:21]\n", + " wire _GEN_23 = 12'hf11 == io_csr_address | 12'hf12 == io_csr_address | 12'hf13 == io_csr_address | 12'hf14 ==\n", + " io_csr_address | _GEN_21; // @[csr.scala 69:26 87:16]\n", + " wire _GEN_24 = 12'hf11 == io_csr_address | 12'hf12 == io_csr_address | 12'hf13 == io_csr_address | 12'hf14 ==\n", + " io_csr_address ? 1'h0 : _GEN_21; // @[csr.scala 69:26 88:17]\n", + " wire [31:0] _GEN_25 = 12'hc82 == io_csr_address ? minstret[63:32] : _GEN_22; // @[csr.scala 69:26 81:21]\n", + " wire _GEN_26 = 12'hc82 == io_csr_address | _GEN_23; // @[csr.scala 69:26 82:16]\n", + " wire _GEN_27 = 12'hc82 == io_csr_address ? 1'h0 : _GEN_24; // @[csr.scala 69:26 83:17]\n", + " wire [31:0] _GEN_28 = 12'hc02 == io_csr_address ? minstret[31:0] : _GEN_25; // @[csr.scala 69:26 76:21]\n", + " wire _GEN_29 = 12'hc02 == io_csr_address | _GEN_26; // @[csr.scala 69:26 77:16]\n", + " wire _GEN_30 = 12'hc02 == io_csr_address ? 1'h0 : _GEN_27; // @[csr.scala 69:26 78:17]\n", + " wire _GEN_34 = io_mret ? pie : ie; // @[csr.scala 156:24 157:8 51:19]\n", + " wire _GEN_35 = io_mret | pie; // @[csr.scala 156:24 158:9 50:20]\n", + " wire _GEN_36 = io_trapped ? ie : _GEN_35; // @[csr.scala 150:20 151:9]\n", + " wire _GEN_37 = io_trapped ? 1'h0 : _GEN_34; // @[csr.scala 150:20 152:8]\n", + " wire [31:0] _GEN_38 = io_trapped ? io_mem_pc : mepc; // @[csr.scala 150:20 153:10 44:21]\n", + " wire _GEN_39 = io_trapped ? io_interrupt : minterrupt; // @[csr.scala 150:20 154:16 48:27]\n", + " wire [3:0] _GEN_40 = io_trapped ? {{1'd0}, io_ecause} : mcause; // @[csr.scala 150:20 155:12 47:23]\n", + " wire [63:0] _mcycle_T_1 = mcycle + 64'h1; // @[csr.scala 161:20]\n", + " wire [63:0] _minstret_T_1 = minstret + 64'h1; // @[csr.scala 163:26]\n", + " wire [63:0] _GEN_41 = io_inst_retired ? _minstret_T_1 : minstret; // @[csr.scala 162:25 163:14 42:25]\n", + " wire [31:0] _mtvec_T_1 = {io_csr_write_data[31:2],2'h0}; // @[Cat.scala 31:58]\n", + " wire [63:0] _mcycle_T_2 = {32'h0,io_csr_write_data}; // @[Cat.scala 31:58]\n", + " wire [63:0] _mcycle_T_3 = _mcycle_T_2 | mcycle; // @[csr.scala 198:52]\n", + " wire [63:0] _minstret_T_3 = _mcycle_T_2 | minstret; // @[csr.scala 201:54]\n", + " wire [63:0] _GEN_42 = 12'hb02 == io_csr_write_address ? _minstret_T_3 : _GEN_41; // @[csr.scala 168:34 201:18]\n", + " wire [63:0] _GEN_43 = 12'hb00 == io_csr_write_address | 12'hb01 == io_csr_write_address ? _mcycle_T_3 : _mcycle_T_1; // @[csr.scala 161:10 168:34 198:16]\n", + " wire [63:0] _GEN_44 = 12'hb00 == io_csr_write_address | 12'hb01 == io_csr_write_address ? _GEN_41 : _GEN_42; // @[csr.scala 168:34]\n", + " wire [63:0] _GEN_46 = 12'h343 == io_csr_write_address ? _mcycle_T_1 : _GEN_43; // @[csr.scala 161:10 168:34]\n", + " wire [63:0] _GEN_47 = 12'h343 == io_csr_write_address ? _GEN_41 : _GEN_44; // @[csr.scala 168:34]\n", + " wire _GEN_48 = 12'h342 == io_csr_write_address ? io_csr_write_data[31] : _GEN_39; // @[csr.scala 168:34 191:20]\n", + " wire [3:0] _GEN_49 = 12'h342 == io_csr_write_address ? io_csr_write_data[3:0] : _GEN_40; // @[csr.scala 168:34 192:16]\n", + " wire [63:0] _GEN_51 = 12'h342 == io_csr_write_address ? _mcycle_T_1 : _GEN_46; // @[csr.scala 161:10 168:34]\n", + " wire [63:0] _GEN_52 = 12'h342 == io_csr_write_address ? _GEN_41 : _GEN_47; // @[csr.scala 168:34]\n", + " wire [31:0] _GEN_53 = 12'h341 == io_csr_write_address ? io_csr_write_data : _GEN_38; // @[csr.scala 168:34 188:14]\n", + " wire _GEN_54 = 12'h341 == io_csr_write_address ? _GEN_39 : _GEN_48; // @[csr.scala 168:34]\n", + " wire [3:0] _GEN_55 = 12'h341 == io_csr_write_address ? _GEN_40 : _GEN_49; // @[csr.scala 168:34]\n", + " wire [63:0] _GEN_57 = 12'h341 == io_csr_write_address ? _mcycle_T_1 : _GEN_51; // @[csr.scala 161:10 168:34]\n", + " wire [63:0] _GEN_58 = 12'h341 == io_csr_write_address ? _GEN_41 : _GEN_52; // @[csr.scala 168:34]\n", + " wire [31:0] _GEN_59 = 12'h340 == io_csr_write_address ? io_csr_write_data : mscratch; // @[csr.scala 168:34 185:18 45:25]\n", + " wire [31:0] _GEN_60 = 12'h340 == io_csr_write_address ? _GEN_38 : _GEN_53; // @[csr.scala 168:34]\n", + " wire _GEN_61 = 12'h340 == io_csr_write_address ? _GEN_39 : _GEN_54; // @[csr.scala 168:34]\n", + " wire [3:0] _GEN_62 = 12'h340 == io_csr_write_address ? _GEN_40 : _GEN_55; // @[csr.scala 168:34]\n", + " wire [63:0] _GEN_64 = 12'h340 == io_csr_write_address ? _mcycle_T_1 : _GEN_57; // @[csr.scala 161:10 168:34]\n", + " wire [63:0] _GEN_65 = 12'h340 == io_csr_write_address ? _GEN_41 : _GEN_58; // @[csr.scala 168:34]\n", + " wire [31:0] _GEN_66 = 12'h305 == io_csr_write_address ? _mtvec_T_1 : mtvec; // @[csr.scala 168:34 182:15 46:22]\n", + " wire [31:0] _GEN_67 = 12'h305 == io_csr_write_address ? mscratch : _GEN_59; // @[csr.scala 168:34 45:25]\n", + " wire [31:0] _GEN_68 = 12'h305 == io_csr_write_address ? _GEN_38 : _GEN_60; // @[csr.scala 168:34]\n", + " wire _GEN_69 = 12'h305 == io_csr_write_address ? _GEN_39 : _GEN_61; // @[csr.scala 168:34]\n", + " wire [3:0] _GEN_70 = 12'h305 == io_csr_write_address ? _GEN_40 : _GEN_62; // @[csr.scala 168:34]\n", + " wire [63:0] _GEN_72 = 12'h305 == io_csr_write_address ? _mcycle_T_1 : _GEN_64; // @[csr.scala 161:10 168:34]\n", + " wire [63:0] _GEN_73 = 12'h305 == io_csr_write_address ? _GEN_41 : _GEN_65; // @[csr.scala 168:34]\n", + " wire _GEN_74 = 12'h304 == io_csr_write_address ? io_csr_write_data[3] : msie; // @[csr.scala 168:34 177:14 53:21]\n", + " wire _GEN_75 = 12'h304 == io_csr_write_address ? io_csr_write_data[7] : mtie; // @[csr.scala 168:34 178:14 55:21]\n", + " wire _GEN_76 = 12'h304 == io_csr_write_address ? io_csr_write_data[11] : meie; // @[csr.scala 168:34 179:14 52:21]\n", + " wire [31:0] _GEN_77 = 12'h304 == io_csr_write_address ? mtvec : _GEN_66; // @[csr.scala 168:34 46:22]\n", + " wire [31:0] _GEN_78 = 12'h304 == io_csr_write_address ? mscratch : _GEN_67; // @[csr.scala 168:34 45:25]\n", + " wire [31:0] _GEN_79 = 12'h304 == io_csr_write_address ? _GEN_38 : _GEN_68; // @[csr.scala 168:34]\n", + " wire _GEN_80 = 12'h304 == io_csr_write_address ? _GEN_39 : _GEN_69; // @[csr.scala 168:34]\n", + " wire [3:0] _GEN_81 = 12'h304 == io_csr_write_address ? _GEN_40 : _GEN_70; // @[csr.scala 168:34]\n", + " wire [63:0] _GEN_83 = 12'h304 == io_csr_write_address ? _mcycle_T_1 : _GEN_72; // @[csr.scala 161:10 168:34]\n", + " wire [63:0] _GEN_84 = 12'h304 == io_csr_write_address ? _GEN_41 : _GEN_73; // @[csr.scala 168:34]\n", + " assign io_csr_read_data = 12'hc00 == io_csr_address | 12'hc01 == io_csr_address ? mcycle[31:0] : _GEN_28; // @[csr.scala 69:26 71:21]\n", + " assign io_readable = 12'hc00 == io_csr_address | 12'hc01 == io_csr_address | _GEN_29; // @[csr.scala 69:26 72:16]\n", + " assign io_writeable = 12'hc00 == io_csr_address | 12'hc01 == io_csr_address ? 1'h0 : _GEN_30; // @[csr.scala 69:26 73:17]\n", + " assign io_eip = ie & meie & io_meip; // @[csr.scala 58:24]\n", + " assign io_tip = ie & mtie & mtip; // @[csr.scala 59:24]\n", + " assign io_sip = ie & msie & msip; // @[csr.scala 60:24]\n", + " assign io_trap_vector = mtvec; // @[csr.scala 62:18]\n", + " assign io_mret_vector = mepc; // @[csr.scala 63:18]\n", + " always @(posedge clock) begin\n", + " if (reset) begin // @[csr.scala 41:23]\n", + " mcycle <= 64'h0; // @[csr.scala 41:23]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (12'h300 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " mcycle <= _mcycle_T_1; // @[csr.scala 161:10]\n", + " end else if (12'h344 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " mcycle <= _mcycle_T_1; // @[csr.scala 161:10]\n", + " end else begin\n", + " mcycle <= _GEN_83;\n", + " end\n", + " end else begin\n", + " mcycle <= _mcycle_T_1; // @[csr.scala 161:10]\n", + " end\n", + " if (reset) begin // @[csr.scala 42:25]\n", + " minstret <= 64'h0; // @[csr.scala 42:25]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (12'h300 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " minstret <= _GEN_41;\n", + " end else if (12'h344 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " minstret <= _GEN_41;\n", + " end else begin\n", + " minstret <= _GEN_84;\n", + " end\n", + " end else begin\n", + " minstret <= _GEN_41;\n", + " end\n", + " if (reset) begin // @[csr.scala 44:21]\n", + " mepc <= 32'h0; // @[csr.scala 44:21]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (12'h300 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " mepc <= _GEN_38;\n", + " end else if (12'h344 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " mepc <= _GEN_38;\n", + " end else begin\n", + " mepc <= _GEN_79;\n", + " end\n", + " end else begin\n", + " mepc <= _GEN_38;\n", + " end\n", + " if (reset) begin // @[csr.scala 45:25]\n", + " mscratch <= 32'h0; // @[csr.scala 45:25]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (!(12'h300 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " if (!(12'h344 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " mscratch <= _GEN_78;\n", + " end\n", + " end\n", + " end\n", + " if (reset) begin // @[csr.scala 46:22]\n", + " mtvec <= 32'h0; // @[csr.scala 46:22]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (!(12'h300 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " if (!(12'h344 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " mtvec <= _GEN_77;\n", + " end\n", + " end\n", + " end\n", + " if (reset) begin // @[csr.scala 47:23]\n", + " mcause <= 4'h0; // @[csr.scala 47:23]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (12'h300 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " mcause <= _GEN_40;\n", + " end else if (12'h344 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " mcause <= _GEN_40;\n", + " end else begin\n", + " mcause <= _GEN_81;\n", + " end\n", + " end else begin\n", + " mcause <= _GEN_40;\n", + " end\n", + " if (reset) begin // @[csr.scala 48:27]\n", + " minterrupt <= 1'h0; // @[csr.scala 48:27]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (12'h300 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " minterrupt <= _GEN_39;\n", + " end else if (12'h344 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " minterrupt <= _GEN_39;\n", + " end else begin\n", + " minterrupt <= _GEN_80;\n", + " end\n", + " end else begin\n", + " minterrupt <= _GEN_39;\n", + " end\n", + " if (reset) begin // @[csr.scala 50:20]\n", + " pie <= 1'h0; // @[csr.scala 50:20]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (12'h300 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " pie <= io_csr_write_data[7]; // @[csr.scala 171:13]\n", + " end else begin\n", + " pie <= _GEN_36;\n", + " end\n", + " end else begin\n", + " pie <= _GEN_36;\n", + " end\n", + " if (reset) begin // @[csr.scala 51:19]\n", + " ie <= 1'h0; // @[csr.scala 51:19]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (12'h300 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " ie <= io_csr_write_data[3]; // @[csr.scala 170:12]\n", + " end else begin\n", + " ie <= _GEN_37;\n", + " end\n", + " end else begin\n", + " ie <= _GEN_37;\n", + " end\n", + " if (reset) begin // @[csr.scala 52:21]\n", + " meie <= 1'h0; // @[csr.scala 52:21]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (!(12'h300 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " if (!(12'h344 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " meie <= _GEN_76;\n", + " end\n", + " end\n", + " end\n", + " if (reset) begin // @[csr.scala 53:21]\n", + " msie <= 1'h0; // @[csr.scala 53:21]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (!(12'h300 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " if (!(12'h344 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " msie <= _GEN_74;\n", + " end\n", + " end\n", + " end\n", + " if (reset) begin // @[csr.scala 54:21]\n", + " msip <= 1'h0; // @[csr.scala 54:21]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (!(12'h300 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " if (12'h344 == io_csr_write_address) begin // @[csr.scala 168:34]\n", + " msip <= io_csr_write_data[3]; // @[csr.scala 174:14]\n", + " end\n", + " end\n", + " end\n", + " if (reset) begin // @[csr.scala 55:21]\n", + " mtie <= 1'h0; // @[csr.scala 55:21]\n", + " end else if (io_csr_write_enable) begin // @[csr.scala 167:29]\n", + " if (!(12'h300 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " if (!(12'h344 == io_csr_write_address)) begin // @[csr.scala 168:34]\n", + " mtie <= _GEN_75;\n", + " end\n", + " end\n", + " end\n", + " if (reset) begin // @[csr.scala 56:21]\n", + " mtip <= 1'h0; // @[csr.scala 56:21]\n", + " end else begin\n", + " mtip <= mcycle >= 64'h7fffffff; // @[csr.scala 205:8]\n", + " end\n", + " end\n", + "// Register and memory initialization\n", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_INVALID_ASSIGN\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + "`define RANDOMIZE\n", + "`endif\n", + "`ifndef RANDOM\n", + "`define RANDOM $random\n", + "`endif\n", + "`ifdef RANDOMIZE_MEM_INIT\n", + " integer initvar;\n", + "`endif\n", + "`ifndef SYNTHESIS\n", + "`ifdef FIRRTL_BEFORE_INITIAL\n", + "`FIRRTL_BEFORE_INITIAL\n", + "`endif\n", + "initial begin\n", + " `ifdef RANDOMIZE\n", + " `ifdef INIT_RANDOM\n", + " `INIT_RANDOM\n", + " `endif\n", + " `ifndef VERILATOR\n", + " `ifdef RANDOMIZE_DELAY\n", + " #`RANDOMIZE_DELAY begin end\n", + " `else\n", + " #0.002 begin end\n", + " `endif\n", + " `endif\n", + "`ifdef RANDOMIZE_REG_INIT\n", + " _RAND_0 = {2{`RANDOM}};\n", + " mcycle = _RAND_0[63:0];\n", + " _RAND_1 = {2{`RANDOM}};\n", + " minstret = _RAND_1[63:0];\n", + " _RAND_2 = {1{`RANDOM}};\n", + " mepc = _RAND_2[31:0];\n", + " _RAND_3 = {1{`RANDOM}};\n", + " mscratch = _RAND_3[31:0];\n", + " _RAND_4 = {1{`RANDOM}};\n", + " mtvec = _RAND_4[31:0];\n", + " _RAND_5 = {1{`RANDOM}};\n", + " mcause = _RAND_5[3:0];\n", + " _RAND_6 = {1{`RANDOM}};\n", + " minterrupt = _RAND_6[0:0];\n", + " _RAND_7 = {1{`RANDOM}};\n", + " pie = _RAND_7[0:0];\n", + " _RAND_8 = {1{`RANDOM}};\n", + " ie = _RAND_8[0:0];\n", + " _RAND_9 = {1{`RANDOM}};\n", + " meie = _RAND_9[0:0];\n", + " _RAND_10 = {1{`RANDOM}};\n", + " msie = _RAND_10[0:0];\n", + " _RAND_11 = {1{`RANDOM}};\n", + " msip = _RAND_11[0:0];\n", + " _RAND_12 = {1{`RANDOM}};\n", + " mtie = _RAND_12[0:0];\n", + " _RAND_13 = {1{`RANDOM}};\n", + " mtip = _RAND_13[0:0];\n", + "`endif // RANDOMIZE_REG_INIT\n", + " `endif // RANDOMIZE\n", + "end // initial\n", + "`ifdef FIRRTL_AFTER_INITIAL\n", + "`FIRRTL_AFTER_INITIAL\n", + "`endif\n", + "`endif // SYNTHESIS\n", + "endmodule\n", + "module Hazard(\n", + " output io_predict,\n", + " output io_pc_stall,\n", + " output io_if_id_stall,\n", + " output io_if_id_flush,\n", + " input io_memread,\n", + " input io_use_rs1,\n", + " input io_use_rs2,\n", + " input [4:0] io_id_rs1,\n", + " input [4:0] io_id_rs2,\n", + " input [4:0] io_ex_rd,\n", + " input io_ex_use_rs1,\n", + " input io_ex_use_rs2,\n", + " input [4:0] io_ex_rs1,\n", + " input [4:0] io_ex_rs2,\n", + " input [31:0] io_ex_pc,\n", + " output io_id_ex_flush,\n", + " input [4:0] io_mem_rd,\n", + " input io_mem_regwrite,\n", + " input [31:0] io_mem_pc,\n", + " input [31:0] io_target_pc,\n", + " output [1:0] io_forward1,\n", + " output [1:0] io_forward2,\n", + " output io_ex_mem_flush,\n", + " input [4:0] io_wb_rd,\n", + " input io_wb_regwrite,\n", + " input io_pcsrc,\n", + " input io_trapped,\n", + " input io_mret,\n", + " output io_mem_wb_flush\n", + ");\n", + " wire _T_5 = io_mem_rd != 5'h0; // @[hazard.scala 48:97]\n", + " wire _T_12 = io_wb_rd != 5'h0; // @[hazard.scala 50:100]\n", + " wire [1:0] _GEN_0 = io_ex_use_rs1 & io_ex_rs1 == io_wb_rd & io_wb_regwrite & io_wb_rd != 5'h0 ? 2'h2 : 2'h0; // @[hazard.scala 50:109 51:14 53:14]\n", + " wire [1:0] _GEN_2 = io_ex_use_rs2 & io_ex_rs2 == io_wb_rd & io_wb_regwrite & _T_12 ? 2'h2 : 2'h0; // @[hazard.scala 58:109 59:14 61:14]\n", + " wire hazard = io_memread & (io_use_rs1 & io_id_rs1 == io_ex_rd | io_use_rs2 & io_id_rs2 == io_ex_rd); // @[hazard.scala 69:35]\n", + " wire _T_30 = io_pcsrc & io_target_pc != io_ex_pc; // @[hazard.scala 79:25]\n", + " wire [31:0] _T_33 = io_mem_pc + 32'h4; // @[hazard.scala 83:52]\n", + " wire controlHazard = ~io_pcsrc & io_ex_pc != _T_33 | _T_30; // @[hazard.scala 83:60 84:19]\n", + " wire _io_if_id_flush_T_1 = controlHazard | io_trapped; // @[hazard.scala 92:35]\n", + " assign io_predict = io_pcsrc & io_target_pc == io_ex_pc; // @[hazard.scala 87:25]\n", + " assign io_pc_stall = io_memread & (io_use_rs1 & io_id_rs1 == io_ex_rd | io_use_rs2 & io_id_rs2 == io_ex_rd); // @[hazard.scala 69:35]\n", + " assign io_if_id_stall = io_memread & (io_use_rs1 & io_id_rs1 == io_ex_rd | io_use_rs2 & io_id_rs2 == io_ex_rd); // @[hazard.scala 69:35]\n", + " assign io_if_id_flush = controlHazard | io_trapped | io_mret; // @[hazard.scala 92:57]\n", + " assign io_id_ex_flush = hazard | controlHazard | io_trapped | io_mret; // @[hazard.scala 95:67]\n", + " assign io_forward1 = io_ex_use_rs1 & io_ex_rs1 == io_mem_rd & io_mem_regwrite & io_mem_rd != 5'h0 ? 2'h1 : _GEN_0; // @[hazard.scala 48:106 49:14]\n", + " assign io_forward2 = io_ex_use_rs2 & io_ex_rs2 == io_mem_rd & io_mem_regwrite & _T_5 ? 2'h1 : _GEN_2; // @[hazard.scala 56:106 57:14]\n", + " assign io_ex_mem_flush = _io_if_id_flush_T_1 | io_mret; // @[hazard.scala 93:58]\n", + " assign io_mem_wb_flush = io_trapped | io_mret; // @[hazard.scala 96:41]\n", + "endmodule\n", + "module core(\n", + " input clock,\n", + " input reset,\n", + " input io_meip,\n", + " input [31:0] io_fetch_data,\n", + " output [31:0] io_fetch_address,\n", + " output io_load_store_unsigned,\n", + " output [1:0] io_memory_size,\n", + " output [31:0] io_memory_address,\n", + " output [31:0] io_memory_write_data,\n", + " input [31:0] io_memory_read_data,\n", + " output io_memory_read,\n", + " output io_memory_write\n", + ");\n", + " wire fetch_clock; // @[core.scala 18:21]\n", + " wire fetch_reset; // @[core.scala 18:21]\n", + " wire [31:0] fetch_io_trap_vector; // @[core.scala 18:21]\n", + " wire [31:0] fetch_io_mret_vector; // @[core.scala 18:21]\n", + " wire [31:0] fetch_io_target_pc; // @[core.scala 18:21]\n", + " wire [31:0] fetch_io_mem_pc; // @[core.scala 18:21]\n", + " wire fetch_io_pcsrc; // @[core.scala 18:21]\n", + " wire fetch_io_branch; // @[core.scala 18:21]\n", + " wire fetch_io_trap; // @[core.scala 18:21]\n", + " wire fetch_io_mret; // @[core.scala 18:21]\n", + " wire fetch_io_pc_stall; // @[core.scala 18:21]\n", + " wire fetch_io_if_id_stall; // @[core.scala 18:21]\n", + " wire fetch_io_if_id_flush; // @[core.scala 18:21]\n", + " wire fetch_io_predict; // @[core.scala 18:21]\n", + " wire [31:0] fetch_io_id_pc; // @[core.scala 18:21]\n", + " wire [31:0] fetch_io_inst; // @[core.scala 18:21]\n", + " wire [31:0] fetch_io_fetch_data; // @[core.scala 18:21]\n", + " wire [31:0] fetch_io_fetch_address; // @[core.scala 18:21]\n", + " wire decode_clock; // @[core.scala 19:22]\n", + " wire decode_reset; // @[core.scala 19:22]\n", + " wire [31:0] decode_io_id_pc; // @[core.scala 19:22]\n", + " wire [31:0] decode_io_inst; // @[core.scala 19:22]\n", + " wire decode_io_csr_read; // @[core.scala 19:22]\n", + " wire decode_io_csr_write; // @[core.scala 19:22]\n", + " wire [11:0] decode_io_csr_address; // @[core.scala 19:22]\n", + " wire [3:0] decode_io_ecause_out; // @[core.scala 19:22]\n", + " wire decode_io_exception_out; // @[core.scala 19:22]\n", + " wire decode_io_mret_out; // @[core.scala 19:22]\n", + " wire decode_io_wfi_out; // @[core.scala 19:22]\n", + " wire [31:0] decode_io_ex_pc; // @[core.scala 19:22]\n", + " wire [3:0] decode_io_aluop; // @[core.scala 19:22]\n", + " wire decode_io_immsrc; // @[core.scala 19:22]\n", + " wire decode_io_isbranch; // @[core.scala 19:22]\n", + " wire decode_io_memread; // @[core.scala 19:22]\n", + " wire decode_io_memwrite; // @[core.scala 19:22]\n", + " wire decode_io_regwrite; // @[core.scala 19:22]\n", + " wire [1:0] decode_io_memtoreg; // @[core.scala 19:22]\n", + " wire decode_io_pcsel; // @[core.scala 19:22]\n", + " wire decode_io_rdsel; // @[core.scala 19:22]\n", + " wire decode_io_isjump; // @[core.scala 19:22]\n", + " wire decode_io_islui; // @[core.scala 19:22]\n", + " wire [31:0] decode_io_rs1_data; // @[core.scala 19:22]\n", + " wire [31:0] decode_io_rs2_data; // @[core.scala 19:22]\n", + " wire [31:0] decode_io_imm; // @[core.scala 19:22]\n", + " wire [31:0] decode_io_funct3; // @[core.scala 19:22]\n", + " wire [4:0] decode_io_ex_rs1; // @[core.scala 19:22]\n", + " wire [4:0] decode_io_ex_rs2; // @[core.scala 19:22]\n", + " wire [4:0] decode_io_ex_rd; // @[core.scala 19:22]\n", + " wire decode_io_ex_use_rs1; // @[core.scala 19:22]\n", + " wire decode_io_ex_use_rs2; // @[core.scala 19:22]\n", + " wire [4:0] decode_io_wb_rd; // @[core.scala 19:22]\n", + " wire decode_io_wb_regwrite; // @[core.scala 19:22]\n", + " wire [31:0] decode_io_writedata; // @[core.scala 19:22]\n", + " wire decode_io_id_ex_flush; // @[core.scala 19:22]\n", + " wire [4:0] decode_io_id_rs1; // @[core.scala 19:22]\n", + " wire [4:0] decode_io_id_rs2; // @[core.scala 19:22]\n", + " wire decode_io_use_rs1; // @[core.scala 19:22]\n", + " wire decode_io_use_rs2; // @[core.scala 19:22]\n", + " wire execute_clock; // @[core.scala 20:23]\n", + " wire execute_reset; // @[core.scala 20:23]\n", + " wire execute_io_csr_read; // @[core.scala 20:23]\n", + " wire execute_io_csr_write; // @[core.scala 20:23]\n", + " wire [11:0] execute_io_csr_address; // @[core.scala 20:23]\n", + " wire [3:0] execute_io_ecause_in; // @[core.scala 20:23]\n", + " wire execute_io_exception_in; // @[core.scala 20:23]\n", + " wire execute_io_mret_in; // @[core.scala 20:23]\n", + " wire execute_io_wfi_in; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_ex_pc; // @[core.scala 20:23]\n", + " wire [3:0] execute_io_aluop; // @[core.scala 20:23]\n", + " wire execute_io_immsrc; // @[core.scala 20:23]\n", + " wire execute_io_isbranch; // @[core.scala 20:23]\n", + " wire execute_io_memread; // @[core.scala 20:23]\n", + " wire execute_io_memwrite; // @[core.scala 20:23]\n", + " wire execute_io_regwrite; // @[core.scala 20:23]\n", + " wire [1:0] execute_io_memtoreg; // @[core.scala 20:23]\n", + " wire execute_io_pcsel; // @[core.scala 20:23]\n", + " wire execute_io_rdsel; // @[core.scala 20:23]\n", + " wire execute_io_isjump; // @[core.scala 20:23]\n", + " wire execute_io_islui; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_rs1_data; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_rs2_data; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_imm; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_funct3; // @[core.scala 20:23]\n", + " wire [4:0] execute_io_ex_rs1; // @[core.scala 20:23]\n", + " wire [4:0] execute_io_ex_rd; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_mem_pc; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_target_pc; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_csr_read_data; // @[core.scala 20:23]\n", + " wire execute_io_readable; // @[core.scala 20:23]\n", + " wire execute_io_writeable; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_csr_read_data_out; // @[core.scala 20:23]\n", + " wire execute_io_csr_write_enable_out; // @[core.scala 20:23]\n", + " wire [11:0] execute_io_csr_write_address_out; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_csr_write_data_out; // @[core.scala 20:23]\n", + " wire [3:0] execute_io_ecause_out; // @[core.scala 20:23]\n", + " wire execute_io_exception_out; // @[core.scala 20:23]\n", + " wire execute_io_mret_out; // @[core.scala 20:23]\n", + " wire execute_io_wfi_out; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_reg_pc; // @[core.scala 20:23]\n", + " wire execute_io_mem_isbranch; // @[core.scala 20:23]\n", + " wire execute_io_mem_isjump; // @[core.scala 20:23]\n", + " wire execute_io_mem_memread; // @[core.scala 20:23]\n", + " wire execute_io_mem_memwrite; // @[core.scala 20:23]\n", + " wire execute_io_mem_regwrite; // @[core.scala 20:23]\n", + " wire [1:0] execute_io_mem_memtoreg; // @[core.scala 20:23]\n", + " wire execute_io_mem_zero; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_mem_aluresult; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_mem_rs2_data; // @[core.scala 20:23]\n", + " wire [2:0] execute_io_mem_funct3; // @[core.scala 20:23]\n", + " wire [4:0] execute_io_mem_rd; // @[core.scala 20:23]\n", + " wire [31:0] execute_io_writedata; // @[core.scala 20:23]\n", + " wire [1:0] execute_io_forward1; // @[core.scala 20:23]\n", + " wire [1:0] execute_io_forward2; // @[core.scala 20:23]\n", + " wire execute_io_ex_mem_flush; // @[core.scala 20:23]\n", + " wire memory_clock; // @[core.scala 21:22]\n", + " wire memory_reset; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_csr_read_data_in; // @[core.scala 21:22]\n", + " wire memory_io_csr_write_enable_in; // @[core.scala 21:22]\n", + " wire [11:0] memory_io_csr_write_address_in; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_csr_write_data_in; // @[core.scala 21:22]\n", + " wire [3:0] memory_io_ecause_in; // @[core.scala 21:22]\n", + " wire memory_io_exception_in; // @[core.scala 21:22]\n", + " wire memory_io_mret_in; // @[core.scala 21:22]\n", + " wire memory_io_wfi_in; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_reg_pc; // @[core.scala 21:22]\n", + " wire memory_io_mem_isbranch; // @[core.scala 21:22]\n", + " wire memory_io_mem_isjump; // @[core.scala 21:22]\n", + " wire memory_io_mem_memread; // @[core.scala 21:22]\n", + " wire memory_io_mem_memwrite; // @[core.scala 21:22]\n", + " wire memory_io_mem_regwrite; // @[core.scala 21:22]\n", + " wire [1:0] memory_io_mem_memtoreg; // @[core.scala 21:22]\n", + " wire memory_io_mem_zero; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_mem_aluresult; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_mem_rs2_data; // @[core.scala 21:22]\n", + " wire [2:0] memory_io_mem_funct3; // @[core.scala 21:22]\n", + " wire [4:0] memory_io_mem_rd; // @[core.scala 21:22]\n", + " wire memory_io_sip; // @[core.scala 21:22]\n", + " wire memory_io_tip; // @[core.scala 21:22]\n", + " wire memory_io_eip; // @[core.scala 21:22]\n", + " wire memory_io_csr_write_enable_out; // @[core.scala 21:22]\n", + " wire [11:0] memory_io_csr_write_address_out; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_csr_write_data_out; // @[core.scala 21:22]\n", + " wire [3:0] memory_io_ecause_out; // @[core.scala 21:22]\n", + " wire memory_io_trapped; // @[core.scala 21:22]\n", + " wire memory_io_interrupt; // @[core.scala 21:22]\n", + " wire memory_io_inst_retired; // @[core.scala 21:22]\n", + " wire memory_io_mret_out; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_csr_read_data_out; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_wb_reg_pc; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_wb_readdata; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_wb_aluresult; // @[core.scala 21:22]\n", + " wire [1:0] memory_io_wb_memtoreg; // @[core.scala 21:22]\n", + " wire memory_io_wb_regwrite; // @[core.scala 21:22]\n", + " wire [4:0] memory_io_wb_rd; // @[core.scala 21:22]\n", + " wire memory_io_pcsrc; // @[core.scala 21:22]\n", + " wire memory_io_branch; // @[core.scala 21:22]\n", + " wire memory_io_mem_wb_flush; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_memory_read_data; // @[core.scala 21:22]\n", + " wire memory_io_load_store_unsigned; // @[core.scala 21:22]\n", + " wire [1:0] memory_io_memory_size; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_memory_address; // @[core.scala 21:22]\n", + " wire [31:0] memory_io_memory_write_data; // @[core.scala 21:22]\n", + " wire memory_io_memory_read; // @[core.scala 21:22]\n", + " wire memory_io_memory_write; // @[core.scala 21:22]\n", + " wire [31:0] writeback_io_csr_read_data_in; // @[core.scala 22:25]\n", + " wire [31:0] writeback_io_wb_reg_pc; // @[core.scala 22:25]\n", + " wire [31:0] writeback_io_wb_readdata; // @[core.scala 22:25]\n", + " wire [31:0] writeback_io_wb_aluresult; // @[core.scala 22:25]\n", + " wire [1:0] writeback_io_wb_memtoreg; // @[core.scala 22:25]\n", + " wire [31:0] writeback_io_writedata; // @[core.scala 22:25]\n", + " wire csr_clock; // @[core.scala 23:19]\n", + " wire csr_reset; // @[core.scala 23:19]\n", + " wire csr_io_meip; // @[core.scala 23:19]\n", + " wire [11:0] csr_io_csr_address; // @[core.scala 23:19]\n", + " wire [31:0] csr_io_mem_pc; // @[core.scala 23:19]\n", + " wire [31:0] csr_io_csr_read_data; // @[core.scala 23:19]\n", + " wire csr_io_readable; // @[core.scala 23:19]\n", + " wire csr_io_writeable; // @[core.scala 23:19]\n", + " wire csr_io_csr_write_enable; // @[core.scala 23:19]\n", + " wire [11:0] csr_io_csr_write_address; // @[core.scala 23:19]\n", + " wire [31:0] csr_io_csr_write_data; // @[core.scala 23:19]\n", + " wire csr_io_inst_retired; // @[core.scala 23:19]\n", + " wire csr_io_trapped; // @[core.scala 23:19]\n", + " wire csr_io_mret; // @[core.scala 23:19]\n", + " wire [2:0] csr_io_ecause; // @[core.scala 23:19]\n", + " wire csr_io_interrupt; // @[core.scala 23:19]\n", + " wire csr_io_eip; // @[core.scala 23:19]\n", + " wire csr_io_tip; // @[core.scala 23:19]\n", + " wire csr_io_sip; // @[core.scala 23:19]\n", + " wire [31:0] csr_io_trap_vector; // @[core.scala 23:19]\n", + " wire [31:0] csr_io_mret_vector; // @[core.scala 23:19]\n", + " wire hazard_io_predict; // @[core.scala 24:22]\n", + " wire hazard_io_pc_stall; // @[core.scala 24:22]\n", + " wire hazard_io_if_id_stall; // @[core.scala 24:22]\n", + " wire hazard_io_if_id_flush; // @[core.scala 24:22]\n", + " wire hazard_io_memread; // @[core.scala 24:22]\n", + " wire hazard_io_use_rs1; // @[core.scala 24:22]\n", + " wire hazard_io_use_rs2; // @[core.scala 24:22]\n", + " wire [4:0] hazard_io_id_rs1; // @[core.scala 24:22]\n", + " wire [4:0] hazard_io_id_rs2; // @[core.scala 24:22]\n", + " wire [4:0] hazard_io_ex_rd; // @[core.scala 24:22]\n", + " wire hazard_io_ex_use_rs1; // @[core.scala 24:22]\n", + " wire hazard_io_ex_use_rs2; // @[core.scala 24:22]\n", + " wire [4:0] hazard_io_ex_rs1; // @[core.scala 24:22]\n", + " wire [4:0] hazard_io_ex_rs2; // @[core.scala 24:22]\n", + " wire [31:0] hazard_io_ex_pc; // @[core.scala 24:22]\n", + " wire hazard_io_id_ex_flush; // @[core.scala 24:22]\n", + " wire [4:0] hazard_io_mem_rd; // @[core.scala 24:22]\n", + " wire hazard_io_mem_regwrite; // @[core.scala 24:22]\n", + " wire [31:0] hazard_io_mem_pc; // @[core.scala 24:22]\n", + " wire [31:0] hazard_io_target_pc; // @[core.scala 24:22]\n", + " wire [1:0] hazard_io_forward1; // @[core.scala 24:22]\n", + " wire [1:0] hazard_io_forward2; // @[core.scala 24:22]\n", + " wire hazard_io_ex_mem_flush; // @[core.scala 24:22]\n", + " wire [4:0] hazard_io_wb_rd; // @[core.scala 24:22]\n", + " wire hazard_io_wb_regwrite; // @[core.scala 24:22]\n", + " wire hazard_io_pcsrc; // @[core.scala 24:22]\n", + " wire hazard_io_trapped; // @[core.scala 24:22]\n", + " wire hazard_io_mret; // @[core.scala 24:22]\n", + " wire hazard_io_mem_wb_flush; // @[core.scala 24:22]\n", + " Fetch fetch ( // @[core.scala 18:21]\n", + " .clock(fetch_clock),\n", + " .reset(fetch_reset),\n", + " .io_trap_vector(fetch_io_trap_vector),\n", + " .io_mret_vector(fetch_io_mret_vector),\n", + " .io_target_pc(fetch_io_target_pc),\n", + " .io_mem_pc(fetch_io_mem_pc),\n", + " .io_pcsrc(fetch_io_pcsrc),\n", + " .io_branch(fetch_io_branch),\n", + " .io_trap(fetch_io_trap),\n", + " .io_mret(fetch_io_mret),\n", + " .io_pc_stall(fetch_io_pc_stall),\n", + " .io_if_id_stall(fetch_io_if_id_stall),\n", + " .io_if_id_flush(fetch_io_if_id_flush),\n", + " .io_predict(fetch_io_predict),\n", + " .io_id_pc(fetch_io_id_pc),\n", + " .io_inst(fetch_io_inst),\n", + " .io_fetch_data(fetch_io_fetch_data),\n", + " .io_fetch_address(fetch_io_fetch_address)\n", + " );\n", + " Decode decode ( // @[core.scala 19:22]\n", + " .clock(decode_clock),\n", + " .reset(decode_reset),\n", + " .io_id_pc(decode_io_id_pc),\n", + " .io_inst(decode_io_inst),\n", + " .io_csr_read(decode_io_csr_read),\n", + " .io_csr_write(decode_io_csr_write),\n", + " .io_csr_address(decode_io_csr_address),\n", + " .io_ecause_out(decode_io_ecause_out),\n", + " .io_exception_out(decode_io_exception_out),\n", + " .io_mret_out(decode_io_mret_out),\n", + " .io_wfi_out(decode_io_wfi_out),\n", + " .io_ex_pc(decode_io_ex_pc),\n", + " .io_aluop(decode_io_aluop),\n", + " .io_immsrc(decode_io_immsrc),\n", + " .io_isbranch(decode_io_isbranch),\n", + " .io_memread(decode_io_memread),\n", + " .io_memwrite(decode_io_memwrite),\n", + " .io_regwrite(decode_io_regwrite),\n", + " .io_memtoreg(decode_io_memtoreg),\n", + " .io_pcsel(decode_io_pcsel),\n", + " .io_rdsel(decode_io_rdsel),\n", + " .io_isjump(decode_io_isjump),\n", + " .io_islui(decode_io_islui),\n", + " .io_rs1_data(decode_io_rs1_data),\n", + " .io_rs2_data(decode_io_rs2_data),\n", + " .io_imm(decode_io_imm),\n", + " .io_funct3(decode_io_funct3),\n", + " .io_ex_rs1(decode_io_ex_rs1),\n", + " .io_ex_rs2(decode_io_ex_rs2),\n", + " .io_ex_rd(decode_io_ex_rd),\n", + " .io_ex_use_rs1(decode_io_ex_use_rs1),\n", + " .io_ex_use_rs2(decode_io_ex_use_rs2),\n", + " .io_wb_rd(decode_io_wb_rd),\n", + " .io_wb_regwrite(decode_io_wb_regwrite),\n", + " .io_writedata(decode_io_writedata),\n", + " .io_id_ex_flush(decode_io_id_ex_flush),\n", + " .io_id_rs1(decode_io_id_rs1),\n", + " .io_id_rs2(decode_io_id_rs2),\n", + " .io_use_rs1(decode_io_use_rs1),\n", + " .io_use_rs2(decode_io_use_rs2)\n", + " );\n", + " Execute execute ( // @[core.scala 20:23]\n", + " .clock(execute_clock),\n", + " .reset(execute_reset),\n", + " .io_csr_read(execute_io_csr_read),\n", + " .io_csr_write(execute_io_csr_write),\n", + " .io_csr_address(execute_io_csr_address),\n", + " .io_ecause_in(execute_io_ecause_in),\n", + " .io_exception_in(execute_io_exception_in),\n", + " .io_mret_in(execute_io_mret_in),\n", + " .io_wfi_in(execute_io_wfi_in),\n", + " .io_ex_pc(execute_io_ex_pc),\n", + " .io_aluop(execute_io_aluop),\n", + " .io_immsrc(execute_io_immsrc),\n", + " .io_isbranch(execute_io_isbranch),\n", + " .io_memread(execute_io_memread),\n", + " .io_memwrite(execute_io_memwrite),\n", + " .io_regwrite(execute_io_regwrite),\n", + " .io_memtoreg(execute_io_memtoreg),\n", + " .io_pcsel(execute_io_pcsel),\n", + " .io_rdsel(execute_io_rdsel),\n", + " .io_isjump(execute_io_isjump),\n", + " .io_islui(execute_io_islui),\n", + " .io_rs1_data(execute_io_rs1_data),\n", + " .io_rs2_data(execute_io_rs2_data),\n", + " .io_imm(execute_io_imm),\n", + " .io_funct3(execute_io_funct3),\n", + " .io_ex_rs1(execute_io_ex_rs1),\n", + " .io_ex_rd(execute_io_ex_rd),\n", + " .io_mem_pc(execute_io_mem_pc),\n", + " .io_target_pc(execute_io_target_pc),\n", + " .io_csr_read_data(execute_io_csr_read_data),\n", + " .io_readable(execute_io_readable),\n", + " .io_writeable(execute_io_writeable),\n", + " .io_csr_read_data_out(execute_io_csr_read_data_out),\n", + " .io_csr_write_enable_out(execute_io_csr_write_enable_out),\n", + " .io_csr_write_address_out(execute_io_csr_write_address_out),\n", + " .io_csr_write_data_out(execute_io_csr_write_data_out),\n", + " .io_ecause_out(execute_io_ecause_out),\n", + " .io_exception_out(execute_io_exception_out),\n", + " .io_mret_out(execute_io_mret_out),\n", + " .io_wfi_out(execute_io_wfi_out),\n", + " .io_reg_pc(execute_io_reg_pc),\n", + " .io_mem_isbranch(execute_io_mem_isbranch),\n", + " .io_mem_isjump(execute_io_mem_isjump),\n", + " .io_mem_memread(execute_io_mem_memread),\n", + " .io_mem_memwrite(execute_io_mem_memwrite),\n", + " .io_mem_regwrite(execute_io_mem_regwrite),\n", + " .io_mem_memtoreg(execute_io_mem_memtoreg),\n", + " .io_mem_zero(execute_io_mem_zero),\n", + " .io_mem_aluresult(execute_io_mem_aluresult),\n", + " .io_mem_rs2_data(execute_io_mem_rs2_data),\n", + " .io_mem_funct3(execute_io_mem_funct3),\n", + " .io_mem_rd(execute_io_mem_rd),\n", + " .io_writedata(execute_io_writedata),\n", + " .io_forward1(execute_io_forward1),\n", + " .io_forward2(execute_io_forward2),\n", + " .io_ex_mem_flush(execute_io_ex_mem_flush)\n", + " );\n", + " Memory memory ( // @[core.scala 21:22]\n", + " .clock(memory_clock),\n", + " .reset(memory_reset),\n", + " .io_csr_read_data_in(memory_io_csr_read_data_in),\n", + " .io_csr_write_enable_in(memory_io_csr_write_enable_in),\n", + " .io_csr_write_address_in(memory_io_csr_write_address_in),\n", + " .io_csr_write_data_in(memory_io_csr_write_data_in),\n", + " .io_ecause_in(memory_io_ecause_in),\n", + " .io_exception_in(memory_io_exception_in),\n", + " .io_mret_in(memory_io_mret_in),\n", + " .io_wfi_in(memory_io_wfi_in),\n", + " .io_reg_pc(memory_io_reg_pc),\n", + " .io_mem_isbranch(memory_io_mem_isbranch),\n", + " .io_mem_isjump(memory_io_mem_isjump),\n", + " .io_mem_memread(memory_io_mem_memread),\n", + " .io_mem_memwrite(memory_io_mem_memwrite),\n", + " .io_mem_regwrite(memory_io_mem_regwrite),\n", + " .io_mem_memtoreg(memory_io_mem_memtoreg),\n", + " .io_mem_zero(memory_io_mem_zero),\n", + " .io_mem_aluresult(memory_io_mem_aluresult),\n", + " .io_mem_rs2_data(memory_io_mem_rs2_data),\n", + " .io_mem_funct3(memory_io_mem_funct3),\n", + " .io_mem_rd(memory_io_mem_rd),\n", + " .io_sip(memory_io_sip),\n", + " .io_tip(memory_io_tip),\n", + " .io_eip(memory_io_eip),\n", + " .io_csr_write_enable_out(memory_io_csr_write_enable_out),\n", + " .io_csr_write_address_out(memory_io_csr_write_address_out),\n", + " .io_csr_write_data_out(memory_io_csr_write_data_out),\n", + " .io_ecause_out(memory_io_ecause_out),\n", + " .io_trapped(memory_io_trapped),\n", + " .io_interrupt(memory_io_interrupt),\n", + " .io_inst_retired(memory_io_inst_retired),\n", + " .io_mret_out(memory_io_mret_out),\n", + " .io_csr_read_data_out(memory_io_csr_read_data_out),\n", + " .io_wb_reg_pc(memory_io_wb_reg_pc),\n", + " .io_wb_readdata(memory_io_wb_readdata),\n", + " .io_wb_aluresult(memory_io_wb_aluresult),\n", + " .io_wb_memtoreg(memory_io_wb_memtoreg),\n", + " .io_wb_regwrite(memory_io_wb_regwrite),\n", + " .io_wb_rd(memory_io_wb_rd),\n", + " .io_pcsrc(memory_io_pcsrc),\n", + " .io_branch(memory_io_branch),\n", + " .io_mem_wb_flush(memory_io_mem_wb_flush),\n", + " .io_memory_read_data(memory_io_memory_read_data),\n", + " .io_load_store_unsigned(memory_io_load_store_unsigned),\n", + " .io_memory_size(memory_io_memory_size),\n", + " .io_memory_address(memory_io_memory_address),\n", + " .io_memory_write_data(memory_io_memory_write_data),\n", + " .io_memory_read(memory_io_memory_read),\n", + " .io_memory_write(memory_io_memory_write)\n", + " );\n", + " Writeback writeback ( // @[core.scala 22:25]\n", + " .io_csr_read_data_in(writeback_io_csr_read_data_in),\n", + " .io_wb_reg_pc(writeback_io_wb_reg_pc),\n", + " .io_wb_readdata(writeback_io_wb_readdata),\n", + " .io_wb_aluresult(writeback_io_wb_aluresult),\n", + " .io_wb_memtoreg(writeback_io_wb_memtoreg),\n", + " .io_writedata(writeback_io_writedata)\n", + " );\n", + " CSR csr ( // @[core.scala 23:19]\n", + " .clock(csr_clock),\n", + " .reset(csr_reset),\n", + " .io_meip(csr_io_meip),\n", + " .io_csr_address(csr_io_csr_address),\n", + " .io_mem_pc(csr_io_mem_pc),\n", + " .io_csr_read_data(csr_io_csr_read_data),\n", + " .io_readable(csr_io_readable),\n", + " .io_writeable(csr_io_writeable),\n", + " .io_csr_write_enable(csr_io_csr_write_enable),\n", + " .io_csr_write_address(csr_io_csr_write_address),\n", + " .io_csr_write_data(csr_io_csr_write_data),\n", + " .io_inst_retired(csr_io_inst_retired),\n", + " .io_trapped(csr_io_trapped),\n", + " .io_mret(csr_io_mret),\n", + " .io_ecause(csr_io_ecause),\n", + " .io_interrupt(csr_io_interrupt),\n", + " .io_eip(csr_io_eip),\n", + " .io_tip(csr_io_tip),\n", + " .io_sip(csr_io_sip),\n", + " .io_trap_vector(csr_io_trap_vector),\n", + " .io_mret_vector(csr_io_mret_vector)\n", + " );\n", + " Hazard hazard ( // @[core.scala 24:22]\n", + " .io_predict(hazard_io_predict),\n", + " .io_pc_stall(hazard_io_pc_stall),\n", + " .io_if_id_stall(hazard_io_if_id_stall),\n", + " .io_if_id_flush(hazard_io_if_id_flush),\n", + " .io_memread(hazard_io_memread),\n", + " .io_use_rs1(hazard_io_use_rs1),\n", + " .io_use_rs2(hazard_io_use_rs2),\n", + " .io_id_rs1(hazard_io_id_rs1),\n", + " .io_id_rs2(hazard_io_id_rs2),\n", + " .io_ex_rd(hazard_io_ex_rd),\n", + " .io_ex_use_rs1(hazard_io_ex_use_rs1),\n", + " .io_ex_use_rs2(hazard_io_ex_use_rs2),\n", + " .io_ex_rs1(hazard_io_ex_rs1),\n", + " .io_ex_rs2(hazard_io_ex_rs2),\n", + " .io_ex_pc(hazard_io_ex_pc),\n", + " .io_id_ex_flush(hazard_io_id_ex_flush),\n", + " .io_mem_rd(hazard_io_mem_rd),\n", + " .io_mem_regwrite(hazard_io_mem_regwrite),\n", + " .io_mem_pc(hazard_io_mem_pc),\n", + " .io_target_pc(hazard_io_target_pc),\n", + " .io_forward1(hazard_io_forward1),\n", + " .io_forward2(hazard_io_forward2),\n", + " .io_ex_mem_flush(hazard_io_ex_mem_flush),\n", + " .io_wb_rd(hazard_io_wb_rd),\n", + " .io_wb_regwrite(hazard_io_wb_regwrite),\n", + " .io_pcsrc(hazard_io_pcsrc),\n", + " .io_trapped(hazard_io_trapped),\n", + " .io_mret(hazard_io_mret),\n", + " .io_mem_wb_flush(hazard_io_mem_wb_flush)\n", + " );\n", + " assign io_fetch_address = fetch_io_fetch_address; // @[core.scala 146:20]\n", + " assign io_load_store_unsigned = memory_io_load_store_unsigned; // @[core.scala 147:26]\n", + " assign io_memory_size = memory_io_memory_size; // @[core.scala 148:18]\n", + " assign io_memory_address = memory_io_memory_address; // @[core.scala 149:21]\n", + " assign io_memory_write_data = memory_io_memory_write_data; // @[core.scala 150:24]\n", + " assign io_memory_read = memory_io_memory_read; // @[core.scala 151:18]\n", + " assign io_memory_write = memory_io_memory_write; // @[core.scala 152:19]\n", + " assign fetch_clock = clock;\n", + " assign fetch_reset = reset;\n", + " assign fetch_io_trap_vector = csr_io_trap_vector; // @[core.scala 27:24]\n", + " assign fetch_io_mret_vector = csr_io_mret_vector; // @[core.scala 28:24]\n", + " assign fetch_io_target_pc = execute_io_target_pc; // @[core.scala 29:22]\n", + " assign fetch_io_mem_pc = execute_io_mem_pc; // @[core.scala 30:19]\n", + " assign fetch_io_pcsrc = memory_io_pcsrc; // @[core.scala 31:18]\n", + " assign fetch_io_branch = memory_io_branch; // @[core.scala 32:19]\n", + " assign fetch_io_trap = memory_io_trapped; // @[core.scala 33:17]\n", + " assign fetch_io_mret = memory_io_mret_out; // @[core.scala 34:17]\n", + " assign fetch_io_pc_stall = hazard_io_pc_stall; // @[core.scala 35:21]\n", + " assign fetch_io_if_id_stall = hazard_io_if_id_stall; // @[core.scala 36:24]\n", + " assign fetch_io_if_id_flush = hazard_io_if_id_flush; // @[core.scala 37:24]\n", + " assign fetch_io_predict = hazard_io_predict; // @[core.scala 38:20]\n", + " assign fetch_io_fetch_data = io_fetch_data; // @[core.scala 39:23]\n", + " assign decode_clock = clock;\n", + " assign decode_reset = reset;\n", + " assign decode_io_id_pc = fetch_io_id_pc; // @[core.scala 41:19]\n", + " assign decode_io_inst = fetch_io_inst; // @[core.scala 42:18]\n", + " assign decode_io_wb_rd = memory_io_wb_rd; // @[core.scala 43:19]\n", + " assign decode_io_wb_regwrite = memory_io_wb_regwrite; // @[core.scala 44:25]\n", + " assign decode_io_writedata = writeback_io_writedata; // @[core.scala 45:23]\n", + " assign decode_io_id_ex_flush = hazard_io_id_ex_flush; // @[core.scala 46:25]\n", + " assign execute_clock = clock;\n", + " assign execute_reset = reset;\n", + " assign execute_io_csr_read = decode_io_csr_read; // @[core.scala 48:23]\n", + " assign execute_io_csr_write = decode_io_csr_write; // @[core.scala 49:24]\n", + " assign execute_io_csr_address = decode_io_csr_address; // @[core.scala 50:26]\n", + " assign execute_io_ecause_in = decode_io_ecause_out; // @[core.scala 51:24]\n", + " assign execute_io_exception_in = decode_io_exception_out; // @[core.scala 52:27]\n", + " assign execute_io_mret_in = decode_io_mret_out; // @[core.scala 53:22]\n", + " assign execute_io_wfi_in = decode_io_wfi_out; // @[core.scala 54:21]\n", + " assign execute_io_ex_pc = decode_io_ex_pc; // @[core.scala 55:20]\n", + " assign execute_io_aluop = decode_io_aluop; // @[core.scala 56:20]\n", + " assign execute_io_immsrc = decode_io_immsrc; // @[core.scala 57:21]\n", + " assign execute_io_isbranch = decode_io_isbranch; // @[core.scala 58:23]\n", + " assign execute_io_memread = decode_io_memread; // @[core.scala 59:22]\n", + " assign execute_io_memwrite = decode_io_memwrite; // @[core.scala 60:23]\n", + " assign execute_io_regwrite = decode_io_regwrite; // @[core.scala 61:23]\n", + " assign execute_io_memtoreg = decode_io_memtoreg; // @[core.scala 62:23]\n", + " assign execute_io_pcsel = decode_io_pcsel; // @[core.scala 63:20]\n", + " assign execute_io_rdsel = decode_io_rdsel; // @[core.scala 64:20]\n", + " assign execute_io_isjump = decode_io_isjump; // @[core.scala 65:21]\n", + " assign execute_io_islui = decode_io_islui; // @[core.scala 66:20]\n", + " assign execute_io_rs1_data = decode_io_rs1_data; // @[core.scala 67:23]\n", + " assign execute_io_rs2_data = decode_io_rs2_data; // @[core.scala 68:23]\n", + " assign execute_io_imm = decode_io_imm; // @[core.scala 69:18]\n", + " assign execute_io_funct3 = decode_io_funct3; // @[core.scala 70:21]\n", + " assign execute_io_ex_rs1 = decode_io_ex_rs1; // @[core.scala 71:21]\n", + " assign execute_io_ex_rd = decode_io_ex_rd; // @[core.scala 72:20]\n", + " assign execute_io_csr_read_data = csr_io_csr_read_data; // @[core.scala 73:28]\n", + " assign execute_io_readable = csr_io_readable; // @[core.scala 74:23]\n", + " assign execute_io_writeable = csr_io_writeable; // @[core.scala 75:24]\n", + " assign execute_io_writedata = writeback_io_writedata; // @[core.scala 76:24]\n", + " assign execute_io_forward1 = hazard_io_forward1; // @[core.scala 77:23]\n", + " assign execute_io_forward2 = hazard_io_forward2; // @[core.scala 78:23]\n", + " assign execute_io_ex_mem_flush = hazard_io_ex_mem_flush; // @[core.scala 79:27]\n", + " assign memory_clock = clock;\n", + " assign memory_reset = reset;\n", + " assign memory_io_csr_read_data_in = execute_io_csr_read_data_out; // @[core.scala 81:30]\n", + " assign memory_io_csr_write_enable_in = execute_io_csr_write_enable_out; // @[core.scala 82:33]\n", + " assign memory_io_csr_write_address_in = execute_io_csr_write_address_out; // @[core.scala 83:34]\n", + " assign memory_io_csr_write_data_in = execute_io_csr_write_data_out; // @[core.scala 84:31]\n", + " assign memory_io_ecause_in = execute_io_ecause_out; // @[core.scala 85:23]\n", + " assign memory_io_exception_in = execute_io_exception_out; // @[core.scala 86:26]\n", + " assign memory_io_mret_in = execute_io_mret_out; // @[core.scala 87:21]\n", + " assign memory_io_wfi_in = execute_io_wfi_out; // @[core.scala 88:20]\n", + " assign memory_io_reg_pc = execute_io_reg_pc; // @[core.scala 89:20]\n", + " assign memory_io_mem_isbranch = execute_io_mem_isbranch; // @[core.scala 90:26]\n", + " assign memory_io_mem_isjump = execute_io_mem_isjump; // @[core.scala 91:24]\n", + " assign memory_io_mem_memread = execute_io_mem_memread; // @[core.scala 92:25]\n", + " assign memory_io_mem_memwrite = execute_io_mem_memwrite; // @[core.scala 93:26]\n", + " assign memory_io_mem_regwrite = execute_io_mem_regwrite; // @[core.scala 94:26]\n", + " assign memory_io_mem_memtoreg = execute_io_mem_memtoreg; // @[core.scala 95:26]\n", + " assign memory_io_mem_zero = execute_io_mem_zero; // @[core.scala 96:22]\n", + " assign memory_io_mem_aluresult = execute_io_mem_aluresult; // @[core.scala 97:27]\n", + " assign memory_io_mem_rs2_data = execute_io_mem_rs2_data; // @[core.scala 98:26]\n", + " assign memory_io_mem_funct3 = execute_io_mem_funct3; // @[core.scala 99:24]\n", + " assign memory_io_mem_rd = execute_io_mem_rd; // @[core.scala 100:20]\n", + " assign memory_io_sip = csr_io_sip; // @[core.scala 101:17]\n", + " assign memory_io_tip = csr_io_tip; // @[core.scala 102:17]\n", + " assign memory_io_eip = csr_io_eip; // @[core.scala 103:17]\n", + " assign memory_io_mem_wb_flush = hazard_io_mem_wb_flush; // @[core.scala 104:26]\n", + " assign memory_io_memory_read_data = io_memory_read_data; // @[core.scala 105:30]\n", + " assign writeback_io_csr_read_data_in = memory_io_csr_read_data_out; // @[core.scala 107:33]\n", + " assign writeback_io_wb_reg_pc = memory_io_wb_reg_pc; // @[core.scala 108:26]\n", + " assign writeback_io_wb_readdata = memory_io_wb_readdata; // @[core.scala 109:28]\n", + " assign writeback_io_wb_aluresult = memory_io_wb_aluresult; // @[core.scala 110:29]\n", + " assign writeback_io_wb_memtoreg = memory_io_wb_memtoreg; // @[core.scala 111:28]\n", + " assign csr_clock = clock;\n", + " assign csr_reset = reset;\n", + " assign csr_io_meip = io_meip; // @[core.scala 113:15]\n", + " assign csr_io_csr_address = decode_io_csr_address; // @[core.scala 115:22]\n", + " assign csr_io_mem_pc = execute_io_mem_pc; // @[core.scala 114:17]\n", + " assign csr_io_csr_write_enable = memory_io_csr_write_enable_out; // @[core.scala 116:27]\n", + " assign csr_io_csr_write_address = memory_io_csr_write_address_out; // @[core.scala 117:28]\n", + " assign csr_io_csr_write_data = memory_io_csr_write_data_out; // @[core.scala 118:25]\n", + " assign csr_io_inst_retired = memory_io_inst_retired; // @[core.scala 119:23]\n", + " assign csr_io_trapped = memory_io_trapped; // @[core.scala 120:18]\n", + " assign csr_io_mret = memory_io_mret_out; // @[core.scala 122:15]\n", + " assign csr_io_ecause = memory_io_ecause_out[2:0]; // @[core.scala 123:17]\n", + " assign csr_io_interrupt = memory_io_interrupt; // @[core.scala 121:20]\n", + " assign hazard_io_memread = decode_io_memread; // @[core.scala 125:21]\n", + " assign hazard_io_use_rs1 = decode_io_use_rs1; // @[core.scala 126:21]\n", + " assign hazard_io_use_rs2 = decode_io_use_rs2; // @[core.scala 127:21]\n", + " assign hazard_io_id_rs1 = decode_io_id_rs1; // @[core.scala 128:20]\n", + " assign hazard_io_id_rs2 = decode_io_id_rs2; // @[core.scala 129:20]\n", + " assign hazard_io_ex_rd = decode_io_ex_rd; // @[core.scala 130:19]\n", + " assign hazard_io_ex_use_rs1 = decode_io_ex_use_rs1; // @[core.scala 131:24]\n", + " assign hazard_io_ex_use_rs2 = decode_io_ex_use_rs2; // @[core.scala 132:24]\n", + " assign hazard_io_ex_rs1 = decode_io_ex_rs1; // @[core.scala 133:20]\n", + " assign hazard_io_ex_rs2 = decode_io_ex_rs2; // @[core.scala 134:20]\n", + " assign hazard_io_ex_pc = decode_io_ex_pc; // @[core.scala 135:19]\n", + " assign hazard_io_mem_rd = execute_io_mem_rd; // @[core.scala 136:20]\n", + " assign hazard_io_mem_regwrite = execute_io_mem_regwrite; // @[core.scala 137:26]\n", + " assign hazard_io_mem_pc = execute_io_mem_pc; // @[core.scala 138:20]\n", + " assign hazard_io_target_pc = execute_io_target_pc; // @[core.scala 139:23]\n", + " assign hazard_io_wb_rd = memory_io_wb_rd; // @[core.scala 140:19]\n", + " assign hazard_io_wb_regwrite = memory_io_wb_regwrite; // @[core.scala 141:25]\n", + " assign hazard_io_pcsrc = memory_io_pcsrc; // @[core.scala 142:19]\n", + " assign hazard_io_trapped = memory_io_trapped; // @[core.scala 143:21]\n", + " assign hazard_io_mret = memory_io_mret_out; // @[core.scala 144:18]\n", + "endmodule" + ] + }, + { + "cell_type": "markdown", + "id": "fa511a6a-ecc6-46ed-9d0a-313cb173f5a5", + "metadata": { + "id": "fa511a6a-ecc6-46ed-9d0a-313cb173f5a5" + }, + "source": [ + "#### Setting up the configuration" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "b8abd525-bac8-43eb-8440-7800456e71ff", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/", + "height": 1000 + }, + "id": "b8abd525-bac8-43eb-8440-7800456e71ff", + "outputId": "57025a05-f062-498c-bc66-249488b559c1" + }, + "outputs": [ + { + "output_type": "execute_result", + "data": { + "text/plain": [ + "{'STD_CELL_LIBRARY': 'sky130_fd_sc_hd', 'VDD_PIN': 'VPWR', 'VDD_PIN_VOLTAGE': Decimal('1.80'), 'GND_PIN': 'VGND', 'WIRE_LENGTH_THRESHOLD': None, 'TECH_LEFS': {'nom_*': Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef'), 'min_*': Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef'), 'max_*': Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef')}, 'GPIO_PADS_LEF': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef'), Path('/root/.volare/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef')], 'GPIO_PADS_LEF_CORE_SIDE': [Path('/root/.volare/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef'), Path('/root/.volare/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef')], 'GPIO_PADS_VERILOG': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v')], 'GPIO_PAD_CELLS': ['sky130_fd_io*', 'sky130_ef_io*'], 'PRIMARY_GDSII_STREAMOUT_TOOL': 'klayout', 'DEFAULT_MAX_TRAN': None, 'DATA_WIRE_RC_LAYER': 'met2', 'CLOCK_WIRE_RC_LAYER': 'met5', 'DEFAULT_CORNER': 'nom_tt_025C_1v80', 'STA_CORNERS': ['nom_tt_025C_1v80', 'nom_ss_100C_1v60', 'nom_ff_n40C_1v95', 'min_tt_025C_1v80', 'min_ss_100C_1v60', 'min_ff_n40C_1v95', 'max_tt_025C_1v80', 'max_ss_100C_1v60', 'max_ff_n40C_1v95'], 'FP_TRACKS_INFO': Path('/root/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info'), 'FP_TAPCELL_DIST': Decimal('13'), 'FP_IO_HLAYER': 'met3', 'FP_IO_VLAYER': 'met2', 'RT_MIN_LAYER': 'met1', 'RT_MAX_LAYER': 'met5', 'SCL_GROUND_PINS': ['VGND', 'VNB'], 'SCL_POWER_PINS': ['VPWR', 'VPB'], 'TRISTATE_CELLS': ['sky130_fd_sc_hd__ebuf*'], 'FILL_CELL': ['sky130_fd_sc_hd__fill*'], 'DECAP_CELL': ['sky130_ef_sc_hd__decap_12', 'sky130_fd_sc_hd__decap_8', 'sky130_fd_sc_hd__decap_6', 'sky130_fd_sc_hd__decap_4', 'sky130_fd_sc_hd__decap_3'], 'LIB': {'*_tt_025C_1v80': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib')], '*_ss_100C_1v60': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib')], '*_ff_n40C_1v95': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib')]}, 'CELL_LEFS': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef'), Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef')], 'CELL_GDS': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds')], 'CELL_VERILOG_MODELS': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v'), Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v')], 'CELL_BB_VERILOG_MODELS': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox.v'), Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox_pp.v')], 'CELL_SPICE_MODELS': [Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice'), Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice'), Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice'), Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice'), Path('/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice')], 'SYNTH_EXCLUDED_CELL_FILE': Path('/root/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells'), 'PNR_EXCLUDED_CELL_FILE': Path('/root/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells'), 'OUTPUT_CAP_LOAD': Decimal('33.442'), 'MAX_FANOUT_CONSTRAINT': 10, 'MAX_TRANSITION_CONSTRAINT': Decimal('0.75'), 'MAX_CAPACITANCE_CONSTRAINT': Decimal('0.2'), 'CLOCK_UNCERTAINTY_CONSTRAINT': Decimal('0.25'), 'CLOCK_TRANSITION_CONSTRAINT': Decimal('0.1499999999999999944488848768742172978818416595458984375'), 'TIME_DERATING_CONSTRAINT': Decimal('5'), 'IO_DELAY_CONSTRAINT': Decimal('20'), 'SYNTH_DRIVING_CELL': 'sky130_fd_sc_hd__inv_2/Y', 'SYNTH_CLK_DRIVING_CELL': None, 'SYNTH_TIEHI_CELL': 'sky130_fd_sc_hd__conb_1/HI', 'SYNTH_TIELO_CELL': 'sky130_fd_sc_hd__conb_1/LO', 'SYNTH_BUFFER_CELL': 'sky130_fd_sc_hd__buf_2/A/X', 'WELLTAP_CELL': 'sky130_fd_sc_hd__tapvpwrvgnd_1', 'ENDCAP_CELL': 'sky130_fd_sc_hd__decap_3', 'PLACE_SITE': 'unithd', 'CELL_PAD_EXCLUDE': ['sky130_fd_sc_hd__tap*', 'sky130_fd_sc_hd__decap*', 'sky130_ef_sc_hd__decap*', 'sky130_fd_sc_hd__fill*'], 'DIODE_CELL': 'sky130_fd_sc_hd__diode_2/DIODE', 'DESIGN_DIR': Path('.'), 'PDK_ROOT': Path('/root/.volare'), 'DESIGN_NAME': 'core', 'PDK': 'sky130A', 'CLOCK_PERIOD': Decimal('10'), 'CLOCK_PORT': 'clock', 'CLOCK_NET': 'clock', 'VDD_NETS': None, 'GND_NETS': None, 'DIE_AREA': None, 'EXTRA_EXCLUDED_CELLS': None, 'MACROS': None, 'EXTRA_LEFS': None, 'EXTRA_VERILOG_MODELS': None, 'EXTRA_SPICE_MODELS': None, 'EXTRA_LIBS': None, 'EXTRA_GDS_FILES': None, 'FALLBACK_SDC_FILE': Path('/content/openlane_ipynb/openlane/scripts/base.sdc'), 'meta': Meta(version=1, flow=None, step=None, openlane_version='2.0.0rc2')}" + ], + "text/markdown": "\n### Interactive Configuration\n#### Initial Values\n\n
\n\n```yaml\nCELL_BB_VERILOG_MODELS:\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox.v\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox_pp.v\nCELL_GDS:\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds\nCELL_LEFS:\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef\nCELL_PAD_EXCLUDE:\n- sky130_fd_sc_hd__tap*\n- sky130_fd_sc_hd__decap*\n- sky130_ef_sc_hd__decap*\n- sky130_fd_sc_hd__fill*\nCELL_SPICE_MODELS:\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice\nCELL_VERILOG_MODELS:\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v\n- /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v\nCLOCK_NET: clock\nCLOCK_PERIOD: 10\nCLOCK_PORT: clock\nCLOCK_TRANSITION_CONSTRAINT: 0.15\nCLOCK_UNCERTAINTY_CONSTRAINT: 0.25\nCLOCK_WIRE_RC_LAYER: met5\nDATA_WIRE_RC_LAYER: met2\nDECAP_CELL:\n- sky130_ef_sc_hd__decap_12\n- sky130_fd_sc_hd__decap_8\n- sky130_fd_sc_hd__decap_6\n- sky130_fd_sc_hd__decap_4\n- sky130_fd_sc_hd__decap_3\nDEFAULT_CORNER: nom_tt_025C_1v80\nDEFAULT_MAX_TRAN: null\nDESIGN_DIR: .\nDESIGN_NAME: core\nDIE_AREA: null\nDIODE_CELL: sky130_fd_sc_hd__diode_2/DIODE\nENDCAP_CELL: sky130_fd_sc_hd__decap_3\nEXTRA_EXCLUDED_CELLS: null\nEXTRA_GDS_FILES: null\nEXTRA_LEFS: null\nEXTRA_LIBS: null\nEXTRA_SPICE_MODELS: null\nEXTRA_VERILOG_MODELS: null\nFALLBACK_SDC_FILE: /content/openlane_ipynb/openlane/scripts/base.sdc\nFILL_CELL:\n- sky130_fd_sc_hd__fill*\nFP_IO_HLAYER: met3\nFP_IO_VLAYER: met2\nFP_TAPCELL_DIST: 13\nFP_TRACKS_INFO: /root/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info\nGND_NETS: null\nGND_PIN: VGND\nGPIO_PADS_LEF:\n- /root/.volare/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef\n- /root/.volare/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef\nGPIO_PADS_LEF_CORE_SIDE:\n- /root/.volare/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef\n- /root/.volare/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef\nGPIO_PADS_VERILOG:\n- /root/.volare/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v\nGPIO_PAD_CELLS:\n- sky130_fd_io*\n- sky130_ef_io*\nIO_DELAY_CONSTRAINT: 20\nLIB:\n '*_ff_n40C_1v95':\n - /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib\n '*_ss_100C_1v60':\n - /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib\n '*_tt_025C_1v80':\n - /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib\nMACROS: null\nMAX_CAPACITANCE_CONSTRAINT: 0.2\nMAX_FANOUT_CONSTRAINT: 10\nMAX_TRANSITION_CONSTRAINT: 0.75\nOUTPUT_CAP_LOAD: 33.442\nPDK: sky130A\nPDK_ROOT: /root/.volare\nPLACE_SITE: unithd\nPNR_EXCLUDED_CELL_FILE: /root/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells\nPRIMARY_GDSII_STREAMOUT_TOOL: klayout\nRT_MAX_LAYER: met5\nRT_MIN_LAYER: met1\nSCL_GROUND_PINS:\n- VGND\n- VNB\nSCL_POWER_PINS:\n- VPWR\n- VPB\nSTA_CORNERS:\n- nom_tt_025C_1v80\n- nom_ss_100C_1v60\n- nom_ff_n40C_1v95\n- min_tt_025C_1v80\n- min_ss_100C_1v60\n- min_ff_n40C_1v95\n- max_tt_025C_1v80\n- max_ss_100C_1v60\n- max_ff_n40C_1v95\nSTD_CELL_LIBRARY: sky130_fd_sc_hd\nSYNTH_BUFFER_CELL: sky130_fd_sc_hd__buf_2/A/X\nSYNTH_CLK_DRIVING_CELL: null\nSYNTH_DRIVING_CELL: sky130_fd_sc_hd__inv_2/Y\nSYNTH_EXCLUDED_CELL_FILE: /root/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells\nSYNTH_TIEHI_CELL: sky130_fd_sc_hd__conb_1/HI\nSYNTH_TIELO_CELL: sky130_fd_sc_hd__conb_1/LO\nTECH_LEFS:\n max_*: /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef\n min_*: /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef\n nom_*: /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef\nTIME_DERATING_CONSTRAINT: 5\nTRISTATE_CELLS:\n- sky130_fd_sc_hd__ebuf*\nVDD_NETS: null\nVDD_PIN: VPWR\nVDD_PIN_VOLTAGE: 1.8\nWELLTAP_CELL: sky130_fd_sc_hd__tapvpwrvgnd_1\nWIRE_LENGTH_THRESHOLD: null\nmeta:\n flow: null\n openlane_version: 2.0.0rc2\n step: null\n version: 1\n\n```\n" + }, + "metadata": {}, + "execution_count": 27 + } + ], + "source": [ + "from openlane.config import Config\n", + "\n", + "Config.interactive(\n", + " \"core\",\n", + " PDK=\"sky130A\",\n", + " CLOCK_PORT=\"clock\",\n", + " CLOCK_NET=\"clock\",\n", + " CLOCK_PERIOD=10,\n", + " PRIMARY_GDSII_STREAMOUT_TOOL=\"klayout\",\n", + ")" + ] + }, + { + "cell_type": "markdown", + "id": "4d444028-9801-430e-91d9-8b98c18bf6dc", + "metadata": { + "id": "4d444028-9801-430e-91d9-8b98c18bf6dc" + }, + "source": [ + "#### Running implementation steps" + ] + }, + { + "cell_type": "code", + "source": [ + "from openlane.steps import Step" + ], + "metadata": { + "id": "GicQeedTAytp" + }, + "id": "GicQeedTAytp", + "execution_count": null, + "outputs": [] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "043bb059-2391-4feb-890c-494d7d6fce53", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/", + "height": 1000 + }, + "id": "043bb059-2391-4feb-890c-494d7d6fce53", + "outputId": "2bd36869-e3a8-45a9-da22-2819acac3b7f" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "text/markdown": "\n(step-yosys-synthesis)=\n### Synthesis\n\n```{eval-rst}\n\nPerforms synthesis and technology mapping on Verilog RTL files\nusing Yosys and ABC, emitting a netlist.\n\nSome metrics will also be extracted and updated, namely:\n\n* ``design__instance__count``\n* ``design__instance_unmapped__count``\n* ``design__instance__area``\n\n```\n\n#### Importing\n```python\nfrom openlane.steps.yosys import Synthesis\n\n# or\n\nfrom openlane.steps import Step\n\nSynthesis = Step.factory.get(\"Yosys.Synthesis\")\n```\n\n\n#### Inputs and Outputs\n\n| Inputs | Outputs |\n| - | - |\n| | Verilog Netlist (.nl.v) |\n\n(yosys.synthesis-configuration-variables)=\n#### Configuration Variables\n\n| Variable Name | Type | Description | Default | Units |\n| - | - | - | - | - |\n| `SYNTH_LATCH_MAP`{#var-yosys-synthesis-synth_latch_map}PDK | Path? | A path to a file containing the latch mapping for Yosys. | `None` | |\n| `SYNTH_TRISTATE_MAP`{#var-yosys-synthesis-synth_tristate_map}PDK | Path? | A path to a file containing the tri-state buffer mapping for Yosys. | `None` | |\n| `SYNTH_CSA_MAP`{#var-yosys-synthesis-synth_csa_map}PDK | Path? | A path to a file containing the carry-select adder mapping for Yosys. | `None` | |\n| `SYNTH_RCA_MAP`{#var-yosys-synthesis-synth_rca_map}PDK | Path? | A path to a file containing the ripple-carry adder mapping for Yosys. | `None` | |\n| `SYNTH_FA_MAP`{#var-yosys-synthesis-synth_fa_map}PDK | Path? | A path to a file containing the full adder mapping for Yosys. | `None` | |\n| `SYNTH_MUX_MAP`{#var-yosys-synthesis-synth_mux_map}PDK | Path? | A path to a file containing the mux mapping for Yosys. | `None` | |\n| `SYNTH_MUX4_MAP`{#var-yosys-synthesis-synth_mux4_map}PDK | Path? | A path to a file containing the mux4 mapping for Yosys. | `None` | |\n| `USE_LIGHTER`{#var-yosys-synthesis-use_lighter} | bool | Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops. | `False` | |\n| `LIGHTER_DFF_MAP`{#var-yosys-synthesis-lighter_dff_map} | Path? | An override to the custom DFF map file provided for the given SCL by Lighter. | `None` | |\n| `SYNTH_CHECKS_ALLOW_TRISTATE`{#var-yosys-synthesis-synth_checks_allow_tristate} | bool | Ignore multiple-driver warnings if they are connected to tri-state buffers on a best-effort basis. | `True` | |\n| `SYNTH_AUTONAME`{#var-yosys-synthesis-synth_autoname} | bool | Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable. | `False` | |\n| `SYNTH_STRATEGY`{#var-yosys-synthesis-synth_strategy} | 'AREA 0'|
'AREA 1'|
'AREA 2'|
'AREA 3'|
'DELAY 0'|
'DELAY 1'|
'DELAY 2'|
'DELAY 3'|
'DELAY 4' | Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them. | `AREA 0` | |\n| `SYNTH_ABC_BUFFERING`{#var-yosys-synthesis-synth_abc_buffering} | bool | Enables `abc` cell buffering. | `False` | |\n| `SYNTH_ABC_LEGACY_REFACTOR`{#var-yosys-synthesis-synth_abc_legacy_refactor} | bool | Replaces the ABC command `drf -l` with `refactor` which matches older versions of OpenLane but is more unstable. | `False` | |\n| `SYNTH_ABC_LEGACY_REWRITE`{#var-yosys-synthesis-synth_abc_legacy_rewrite} | bool | Replaces the ABC command `drw -l` with `rewrite` which matches older versions of OpenLane but is more unstable. | `False` | |\n| `SYNTH_DIRECT_WIRE_BUFFERING`{#var-yosys-synthesis-synth_direct_wire_buffering} | bool | Enables inserting buffer cells for directly connected wires. | `True` | |\n| `SYNTH_SPLITNETS`{#var-yosys-synthesis-synth_splitnets} | bool | Splits multi-bit nets into single-bit nets. Easier to trace but may not be supported by all tools. | `True` | |\n| `SYNTH_SIZING`{#var-yosys-synthesis-synth_sizing} | bool | Enables `abc` cell sizing (instead of buffering). | `False` | |\n| `SYNTH_NO_FLAT`{#var-yosys-synthesis-synth_no_flat} | bool | A flag that disables flattening the hierarchy during synthesis, only flattening it after synthesis, mapping and optimizations. | `False` | |\n| `SYNTH_SHARE_RESOURCES`{#var-yosys-synthesis-synth_share_resources} | bool | A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them. | `True` | |\n| `SYNTH_ADDER_TYPE`{#var-yosys-synthesis-synth_adder_type} | 'YOSYS'|
'FA'|
'RCA'|
'CSA' | Adder type to which the $add and $sub operators are mapped to. Possible values are `YOSYS/FA/RCA/CSA`; where `YOSYS` refers to using Yosys internal adder definition, `FA` refers to full-adder structure, `RCA` refers to ripple carry adder structure, and `CSA` refers to carry select adder. | `YOSYS` | |\n| `SYNTH_EXTRA_MAPPING_FILE`{#var-yosys-synthesis-synth_extra_mapping_file} | Path? | Points to an extra techmap file for yosys that runs right after yosys `synth` before generic techmap. | `None` | |\n| `SYNTH_PARAMETERS`{#var-yosys-synthesis-synth_parameters} | List[str]? | Key-value pairs to be `chparam`ed in Yosys, in the format `key1=value1`. | `None` | |\n| `SYNTH_ELABORATE_ONLY`{#var-yosys-synthesis-synth_elaborate_only} | bool | \"Elaborate\" the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. | `False` | |\n| `SYNTH_ELABORATE_FLATTEN`{#var-yosys-synthesis-synth_elaborate_flatten} | bool | If `SYNTH_ELABORATE_ONLY` is specified, this variable controls whether or not the top level should be flattened. | `True` | |\n| `VERILOG_FILES`{#var-yosys-synthesis-verilog_files} | List[Path] | The paths of the design's Verilog files. | `None` | |\n| `VERILOG_DEFINES`{#var-yosys-synthesis-verilog_defines} | List[str]? | Preprocessor defines for input Verilog files. | `None` | |\n| `VERILOG_POWER_DEFINE`{#var-yosys-synthesis-verilog_power_define} | str | Specifies the name of the define used to guard power and ground connections in the input RTL. | `USE_POWER_PINS` | |\n| `VERILOG_INCLUDE_DIRS`{#var-yosys-synthesis-verilog_include_dirs} | List[str]? | Specifies the Verilog `include` directories. | `None` | |\n| `USE_SYNLIG`{#var-yosys-synthesis-use_synlig} | bool | Use the Synlig plugin to process files, which has better SystemVerilog parsing capabilities but may not be compatible with all Yosys commands and attributes. | `False` | |\n| `SYNLIG_DEFER`{#var-yosys-synthesis-synlig_defer} | bool | Uses -defer flag when reading files the Synlig plugin, which may improve performance by reading each file separately, but is experimental. | `False` | |\n\n" + }, + "metadata": {} + } + ], + "source": [ + "from openlane.steps import Step\n", + "Synthesis = Step.factory.get(\"Yosys.Synthesis\")\n", + "\n", + "Synthesis.display_help()" + ] + }, + { + "cell_type": "markdown", + "id": "4d01d0f6-059c-494d-94a7-35a890d5edf8", + "metadata": { + "id": "4d01d0f6-059c-494d-94a7-35a890d5edf8" + }, + "source": [ + "#### Synthesis\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "cdcbfc17-9553-488d-9545-5098610f9130", + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/", + "height": 1000 + }, + "id": "cdcbfc17-9553-488d-9545-5098610f9130", + "outputId": "c7514098-87f3-4c6a-fe0e-4d4b5e620e23" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[92m──────────────────────────────────────────────────── \u001b[0mSynthesis\u001b[92m ────────────────────────────────────────────────────\u001b[0m\n" + ], + "text/html": [ + "
──────────────────────────────────────────────────── Synthesis ────────────────────────────────────────────────────\n",
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[11:14:09] VERBOSE  Running 'Yosys.Synthesis'(Log:                                                   step.py:1085\n",
+              "                    ./openlane_run/1-yosys-synthesis/yosys-synthesis.log)                                          \n",
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|  yosys -- Yosys Open SYnthesis Suite                                       |                                     \n",
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|  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |                                     \n",
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+              "
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|  Permission to use, copy, modify, and/or distribute this software for any  |                                     \n",
+              "
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|  purpose with or without fee is hereby granted, provided that the above    |                                     \n",
+              "
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|  copyright notice and this permission notice appear in all copies.         |                                     \n",
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|  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |                                     \n",
+              "
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|  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |                                     \n",
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|  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |                                     \n",
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|  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |                                     \n",
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|  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |                                     \n",
+              "
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|  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |                                     \n",
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|  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |                                     \n",
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|                                                                            |                                     \n",
+              "
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\\----------------------------------------------------------------------------/                                     \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Yosys \u001b[1;36m0.38\u001b[0m \u001b[1m(\u001b[0mgit sha1 543faed9c8c, clang++ \u001b[1;36m16.0\u001b[0m.\u001b[1;36m6\u001b[0m -fPIC -Os\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
Yosys 0.38 (git sha1 543faed9c8c, clang++ 16.0.6 -fPIC -Os)                                                        \n",
+              "
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                                                                                                                   \n",
+              "
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Loaded SDC plugin                                                                                                  \n",
+              "
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[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.                              \n",
+              "
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[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.                            \n",
+              "
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[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.                            \n",
+              "
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[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.                            \n",
+              "
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[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.                           \n",
+              "
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+              "
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1. Executing Liberty frontend: /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib\n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Imported \u001b[1;36m428\u001b[0m cell types from liberty file. \n" + ], + "text/html": [ + "
Imported 428 cell types from liberty file.                                                                         \n",
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2. Executing Verilog-2005 frontend: /content/core.v                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Parsing SystemVerilog input from `\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m' to AST representation. \n" + ], + "text/html": [ + "
Parsing SystemVerilog input from `/content/core.v' to AST representation.                                          \n",
+              "
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Generating RTLIL representation for module `\\BHT'.                                                                 \n",
+              "
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Generating RTLIL representation for module `\\BTB'.                                                                 \n",
+              "
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Generating RTLIL representation for module `\\Fetch'.                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\Control'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\Control'.                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\Regfile'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\Regfile'.                                                             \n",
+              "
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Generating RTLIL representation for module `\\ImmGen'.                                                              \n",
+              "
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Generating RTLIL representation for module `\\Decode'.                                                              \n",
+              "
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Generating RTLIL representation for module `\\AluSelect'.                                                           \n",
+              "
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Generating RTLIL representation for module `\\ALU'.                                                                 \n",
+              "
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Generating RTLIL representation for module `\\TargetGen'.                                                           \n",
+              "
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Generating RTLIL representation for module `\\Execute'.                                                             \n",
+              "
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Generating RTLIL representation for module `\\Branch'.                                                              \n",
+              "
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Generating RTLIL representation for module `\\Memory'.                                                              \n",
+              "
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Generating RTLIL representation for module `\\Writeback'.                                                           \n",
+              "
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Generating RTLIL representation for module `\\CSR'.                                                                 \n",
+              "
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Generating RTLIL representation for module `\\Hazard'.                                                              \n",
+              "
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Generating RTLIL representation for module `\\core'.                                                                \n",
+              "
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Successfully finished Verilog frontend.                                                                            \n",
+              "
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                                                                                                                   \n",
+              "
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3. Generating Graphviz representation of design.                                                                   \n",
+              "
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Writing dot description to `/content/openlane_run/1-yosys-synthesis/hierarchy.dot'.                                \n",
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Dumping module core to page 1.                                                                                     \n",
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4. Executing HIERARCHY pass (managing design hierarchy).                                                           \n",
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4.1. Analyzing design hierarchy..                                                                                  \n",
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Top module:  \\core                                                                                                 \n",
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Used module:     \\Hazard                                                                                           \n",
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Used module:     \\CSR                                                                                              \n",
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Used module:     \\Writeback                                                                                        \n",
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Used module:     \\Memory                                                                                           \n",
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Used module:         \\Branch                                                                                       \n",
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Used module:     \\Execute                                                                                          \n",
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Used module:         \\TargetGen                                                                                    \n",
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Used module:         \\ALU                                                                                          \n",
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Used module:         \\AluSelect                                                                                    \n",
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Used module:     \\Decode                                                                                           \n",
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Used module:         \\ImmGen                                                                                       \n",
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Used module:         \\Regfile                                                                                      \n",
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Used module:         \\Control                                                                                      \n",
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Used module:     \\Fetch                                                                                            \n",
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Used module:         \\BTB                                                                                          \n",
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Used module:         \\BHT                                                                                          \n",
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4.2. Analyzing design hierarchy..                                                                                  \n",
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Top module:  \\core                                                                                                 \n",
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Used module:     \\Hazard                                                                                           \n",
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Used module:     \\CSR                                                                                              \n",
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Used module:     \\Writeback                                                                                        \n",
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Used module:     \\Memory                                                                                           \n",
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Used module:         \\Branch                                                                                       \n",
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Used module:     \\Execute                                                                                          \n",
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Used module:         \\TargetGen                                                                                    \n",
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Used module:         \\ALU                                                                                          \n",
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Used module:         \\AluSelect                                                                                    \n",
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Used module:     \\Decode                                                                                           \n",
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Used module:         \\ImmGen                                                                                       \n",
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Used module:         \\Regfile                                                                                      \n",
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Used module:         \\Control                                                                                      \n",
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Used module:     \\Fetch                                                                                            \n",
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Used module:         \\BTB                                                                                          \n",
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Used module:         \\BHT                                                                                          \n",
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Removed 0 unused modules.                                                                                          \n",
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Renaming module core to core.                                                                                      \n",
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5. Executing TRIBUF pass.                                                                                          \n",
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6. Executing HIERARCHY pass (managing design hierarchy).                                                           \n",
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6.1. Analyzing design hierarchy..                                                                                  \n",
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Top module:  \\core                                                                                                 \n",
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Used module:     \\Hazard                                                                                           \n",
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Used module:     \\CSR                                                                                              \n",
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Used module:     \\Writeback                                                                                        \n",
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Used module:     \\Memory                                                                                           \n",
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Used module:         \\Branch                                                                                       \n",
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Used module:     \\Execute                                                                                          \n",
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Used module:         \\TargetGen                                                                                    \n",
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Used module:         \\ALU                                                                                          \n",
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Used module:         \\AluSelect                                                                                    \n",
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Used module:     \\Decode                                                                                           \n",
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Used module:         \\ImmGen                                                                                       \n",
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Used module:         \\Regfile                                                                                      \n",
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Used module:         \\Control                                                                                      \n",
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Used module:     \\Fetch                                                                                            \n",
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Used module:         \\BTB                                                                                          \n",
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Used module:         \\BHT                                                                                          \n",
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6.2. Analyzing design hierarchy..                                                                                  \n",
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Top module:  \\core                                                                                                 \n",
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Used module:     \\Hazard                                                                                           \n",
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Used module:     \\CSR                                                                                              \n",
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Used module:     \\Writeback                                                                                        \n",
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Used module:     \\Memory                                                                                           \n",
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Used module:         \\Branch                                                                                       \n",
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Used module:     \\Execute                                                                                          \n",
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Used module:         \\TargetGen                                                                                    \n",
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Used module:         \\ALU                                                                                          \n",
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Used module:         \\AluSelect                                                                                    \n",
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Used module:     \\Decode                                                                                           \n",
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Used module:         \\ImmGen                                                                                       \n",
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Used module:         \\Regfile                                                                                      \n",
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Used module:         \\Control                                                                                      \n",
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Used module:     \\Fetch                                                                                            \n",
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Used module:         \\BTB                                                                                          \n",
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Used module:         \\BHT                                                                                          \n",
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Removed 0 unused modules.                                                                                          \n",
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7. Executing PROC_CLEAN pass (remove empty switches from decision trees).                                          \n",
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Cleaned up 0 empty switches.                                                                                       \n",
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8. Executing PROC_RMDEAD pass (remove dead branches from decision trees).                                          \n",
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Removed a total of 0 dead cases.                                                                                   \n",
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9. Executing PROC_PRUNE pass (remove redundant assignments in processes).                                          \n",
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Removed 75 redundant assignments.                                                                                  \n",
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Promoted 16 assignments to connections.                                                                            \n",
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10. Executing PROC_INIT pass (extract init attributes).                                                            \n",
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11. Executing PROC_ARST pass (detect async resets in processes).                                                   \n",
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12. Executing PROC_ROM pass (convert switches to ROMs).                                                            \n",
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Converted 0 switches.                                                                                              \n",
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<suppressed ~293 debug messages>                                                                                   \n",
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13. Executing PROC_MUX pass (convert decision trees to multiplexers).                                              \n",
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1/14: $0\\mtip[0:0]                                                                                                 \n",
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2/14: $0\\ie[0:0]                                                                                                   \n",
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3/14: $0\\pie[0:0]                                                                                                  \n",
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4/14: $0\\minterrupt[0:0]                                                                                           \n",
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5/14: $0\\mcause[3:0]                                                                                               \n",
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6/14: $0\\mepc[31:0]                                                                                                \n",
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7/14: $0\\minstret[63:0]                                                                                            \n",
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8/14: $0\\mcycle[63:0]                                                                                              \n",
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9/14: $0\\mtie[0:0]                                                                                                 \n",
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10/14: $0\\msip[0:0]                                                                                                \n",
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11/14: $0\\msie[0:0]                                                                                                \n",
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12/14: $0\\meie[0:0]                                                                                                \n",
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13/14: $0\\mtvec[31:0]                                                                                              \n",
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14/14: $0\\mscratch[31:0]                                                                                           \n",
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1/17: $0\\branch_reg[0:0]                                                                                           \n",
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2/17: $0\\pcsrc_reg[0:0]                                                                                            \n",
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3/17: $0\\wb_rd_reg[4:0]                                                                                            \n",
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4/17: $0\\wb_regwrite_reg[0:0]                                                                                      \n",
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5/17: $0\\wb_memtoreg_reg[1:0]                                                                                      \n",
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6/17: $0\\wb_aluresult_reg[31:0]                                                                                    \n",
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7/17: $0\\wb_readdata_reg[31:0]                                                                                     \n",
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8/17: $0\\wb_reg_pc_reg[31:0]                                                                                       \n",
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9/17: $0\\mret_out_reg[0:0]                                                                                         \n",
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10/17: $0\\csr_read_data_out_reg[31:0]                                                                              \n",
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11/17: $0\\inst_retired_reg[0:0]                                                                                    \n",
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12/17: $0\\interrupt_reg[0:0]                                                                                       \n",
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13/17: $0\\trapped_reg[0:0]                                                                                         \n",
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14/17: $0\\ecause_out_reg[3:0]                                                                                      \n",
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15/17: $0\\csr_write_data_out_reg[31:0]                                                                             \n",
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16/17: $0\\csr_write_address_out_reg[11:0]                                                                          \n",
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17/17: $0\\csr_write_enable_out_reg[0:0]                                                                            \n",
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1/21: $0\\mem_rd_reg[4:0]                                                                                           \n",
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2/21: $0\\mem_rs2_data_reg[31:0]                                                                                    \n",
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3/21: $0\\mem_aluresult_reg[31:0]                                                                                   \n",
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4/21: $0\\mem_zero_reg[0:0]                                                                                         \n",
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5/21: $0\\mem_memtoreg_reg[1:0]                                                                                     \n",
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6/21: $0\\mem_regwrite_reg[0:0]                                                                                     \n",
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7/21: $0\\mem_memwrite_reg[0:0]                                                                                     \n",
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8/21: $0\\mem_memread_reg[0:0]                                                                                      \n",
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9/21: $0\\mem_isjump_reg[0:0]                                                                                       \n",
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10/21: $0\\mem_isbranch_reg[0:0]                                                                                    \n",
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11/21: $0\\mem_pc_reg[31:0]                                                                                         \n",
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12/21: $0\\target_pc_reg[31:0]                                                                                      \n",
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13/21: $0\\reg_pc_reg[31:0]                                                                                         \n",
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14/21: $0\\csr_write_data_out_reg[31:0]                                                                             \n",
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15/21: $0\\csr_write_address_out_reg[11:0]                                                                          \n",
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16/21: $0\\csr_write_enable_out_reg[0:0]                                                                            \n",
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17/21: $0\\csr_read_data_out_reg[31:0]                                                                              \n",
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18/21: $0\\exception_out_reg[0:0]                                                                                   \n",
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19/21: $0\\ecause_out_reg[3:0]                                                                                      \n",
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20/21: $0\\wfi_out_reg[0:0]                                                                                         \n",
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21/21: $0\\mret_out_reg[0:0]                                                                                        \n",
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1/28: $0\\id_ex_ex_use_rs2_reg[0:0]                                                                                 \n",
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2/28: $0\\id_ex_ex_use_rs1_reg[0:0]                                                                                 \n",
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3/28: $0\\id_ex_ex_rd_reg[4:0]                                                                                      \n",
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4/28: $0\\id_ex_ex_rs2_reg[4:0]                                                                                     \n",
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5/28: $0\\id_ex_ex_rs1_reg[4:0]                                                                                     \n",
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6/28: $0\\id_ex_funct3_reg[2:0]                                                                                     \n",
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7/28: $0\\id_ex_imm_reg[31:0]                                                                                       \n",
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8/28: $0\\id_ex_rs2_data_reg[31:0]                                                                                  \n",
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9/28: $0\\id_ex_rs1_data_reg[31:0]                                                                                  \n",
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10/28: $0\\id_ex_islui_reg[0:0]                                                                                     \n",
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11/28: $0\\id_ex_isjump_reg[0:0]                                                                                    \n",
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12/28: $0\\id_ex_rdsel_reg[0:0]                                                                                     \n",
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13/28: $0\\id_ex_pcsel_reg[0:0]                                                                                     \n",
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14/28: $0\\id_ex_memtoreg_reg[1:0]                                                                                  \n",
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15/28: $0\\id_ex_regwrite_reg[0:0]                                                                                  \n",
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16/28: $0\\id_ex_memwrite_reg[0:0]                                                                                  \n",
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17/28: $0\\id_ex_memread_reg[0:0]                                                                                   \n",
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18/28: $0\\id_ex_isbranch_reg[0:0]                                                                                  \n",
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19/28: $0\\id_ex_immsrc_reg[0:0]                                                                                    \n",
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20/28: $0\\id_ex_aluop_reg[3:0]                                                                                     \n",
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21/28: $0\\id_ex_pc_reg[31:0]                                                                                       \n",
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22/28: $0\\wfi_out_reg[0:0]                                                                                         \n",
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23/28: $0\\mret_out_reg[0:0]                                                                                        \n",
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24/28: $0\\exception_out_reg[0:0]                                                                                   \n",
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25/28: $0\\ecause_out_reg[3:0]                                                                                      \n",
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26/28: $0\\csr_address_reg[11:0]                                                                                    \n",
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27/28: $0\\csr_write_reg[0:0]                                                                                       \n",
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28/28: $0\\csr_read_reg[0:0]                                                                                        \n",
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1/32: $0\\registers_31[31:0]                                                                                        \n",
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2/32: $0\\registers_30[31:0]                                                                                        \n",
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3/32: $0\\registers_29[31:0]                                                                                        \n",
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4/32: $0\\registers_28[31:0]                                                                                        \n",
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5/32: $0\\registers_27[31:0]                                                                                        \n",
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6/32: $0\\registers_26[31:0]                                                                                        \n",
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7/32: $0\\registers_25[31:0]                                                                                        \n",
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8/32: $0\\registers_24[31:0]                                                                                        \n",
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9/32: $0\\registers_23[31:0]                                                                                        \n",
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10/32: $0\\registers_22[31:0]                                                                                       \n",
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11/32: $0\\registers_21[31:0]                                                                                       \n",
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12/32: $0\\registers_20[31:0]                                                                                       \n",
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13/32: $0\\registers_19[31:0]                                                                                       \n",
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14/32: $0\\registers_18[31:0]                                                                                       \n",
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15/32: $0\\registers_17[31:0]                                                                                       \n",
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16/32: $0\\registers_16[31:0]                                                                                       \n",
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17/32: $0\\registers_15[31:0]                                                                                       \n",
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18/32: $0\\registers_14[31:0]                                                                                       \n",
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19/32: $0\\registers_13[31:0]                                                                                       \n",
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20/32: $0\\registers_12[31:0]                                                                                       \n",
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21/32: $0\\registers_11[31:0]                                                                                       \n",
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22/32: $0\\registers_10[31:0]                                                                                       \n",
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23/32: $0\\registers_9[31:0]                                                                                        \n",
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24/32: $0\\registers_8[31:0]                                                                                        \n",
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25/32: $0\\registers_7[31:0]                                                                                        \n",
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26/32: $0\\registers_6[31:0]                                                                                        \n",
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27/32: $0\\registers_5[31:0]                                                                                        \n",
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28/32: $0\\registers_4[31:0]                                                                                        \n",
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29/32: $0\\registers_3[31:0]                                                                                        \n",
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30/32: $0\\registers_2[31:0]                                                                                        \n",
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31/32: $0\\registers_1[31:0]                                                                                        \n",
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32/32: $0\\registers_0[31:0]                                                                                        \n",
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Creating decoders for process `\\Fetch.$proc$/content/core.v:323$70'.                                               \n",
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1/3: $0\\pcReg[31:0]                                                                                                \n",
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2/3: $0\\instReg[31:0]                                                                                              \n",
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3/3: $0\\idPcReg[31:0]                                                                                              \n",
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1/6: $1$memwr$\\btbTable$/content/core.v:197$31_EN[1:0]$64                                                          \n",
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2/6: $1$memwr$\\btbTable$/content/core.v:197$31_DATA[1:0]$63                                                        \n",
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3/6: $1$memwr$\\btbTable$/content/core.v:197$31_ADDR[3:0]$62                                                        \n",
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4/6: $1$memwr$\\btbTable$/content/core.v:194$30_EN[1:0]$60                                                          \n",
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5/6: $1$memwr$\\btbTable$/content/core.v:194$30_DATA[1:0]$59                                                        \n",
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6/6: $1$memwr$\\btbTable$/content/core.v:194$30_ADDR[3:0]$58                                                        \n",
+              "
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Creating decoders for process `\\BHT.$proc$/content/core.v:64$8'.                                                   \n",
+              "
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1/9: $1$memwr$\\bhtTable_target_pc$/content/core.v:72$3_EN[31:0]$29                                                 \n",
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2/9: $1$memwr$\\bhtTable_target_pc$/content/core.v:72$3_DATA[31:0]$28                                               \n",
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3/9: $1$memwr$\\bhtTable_target_pc$/content/core.v:72$3_ADDR[3:0]$27                                                \n",
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4/9: $1$memwr$\\bhtTable_valid$/content/core.v:69$2_EN[0:0]$25                                                      \n",
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5/9: $1$memwr$\\bhtTable_valid$/content/core.v:69$2_DATA[0:0]$24                                                    \n",
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6/9: $1$memwr$\\bhtTable_valid$/content/core.v:69$2_ADDR[3:0]$23                                                    \n",
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7/9: $1$memwr$\\bhtTable_tag$/content/core.v:66$1_EN[25:0]$21                                                       \n",
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8/9: $1$memwr$\\bhtTable_tag$/content/core.v:66$1_DATA[25:0]$20                                                     \n",
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9/9: $1$memwr$\\bhtTable_tag$/content/core.v:66$1_ADDR[3:0]$19                                                      \n",
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                                                                                                                   \n",
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14. Executing PROC_DLATCH pass (convert process syncs to latches).                                                 \n",
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                                                                                                                   \n",
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15. Executing PROC_DFF pass (convert process syncs to FFs).                                                        \n",
+              "
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Creating register for signal `\\CSR.\\mcycle' using process `\\CSR.$proc$/content/core.v:2638$1025'.                  \n",
+              "
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created $dff cell `$procdff$1946' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\CSR.\\minstret' using process `\\CSR.$proc$/content/core.v:2638$1025'.                \n",
+              "
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created $dff cell `$procdff$1947' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\mepc' using process `\\CSR.$proc$/content/core.v:2638$1025'.                    \n",
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created $dff cell `$procdff$1948' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\mscratch' using process `\\CSR.$proc$/content/core.v:2638$1025'.                \n",
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created $dff cell `$procdff$1949' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\mtvec' using process `\\CSR.$proc$/content/core.v:2638$1025'.                   \n",
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created $dff cell `$procdff$1950' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\mcause' using process `\\CSR.$proc$/content/core.v:2638$1025'.                  \n",
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created $dff cell `$procdff$1951' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\minterrupt' using process `\\CSR.$proc$/content/core.v:2638$1025'.              \n",
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created $dff cell `$procdff$1952' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\pie' using process `\\CSR.$proc$/content/core.v:2638$1025'.                     \n",
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created $dff cell `$procdff$1953' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\ie' using process `\\CSR.$proc$/content/core.v:2638$1025'.                      \n",
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created $dff cell `$procdff$1954' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\meie' using process `\\CSR.$proc$/content/core.v:2638$1025'.                    \n",
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created $dff cell `$procdff$1955' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\msie' using process `\\CSR.$proc$/content/core.v:2638$1025'.                    \n",
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created $dff cell `$procdff$1956' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\msip' using process `\\CSR.$proc$/content/core.v:2638$1025'.                    \n",
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created $dff cell `$procdff$1957' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\mtie' using process `\\CSR.$proc$/content/core.v:2638$1025'.                    \n",
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created $dff cell `$procdff$1958' with positive edge clock.                                                        \n",
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Creating register for signal `\\CSR.\\mtip' using process `\\CSR.$proc$/content/core.v:2638$1025'.                    \n",
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created $dff cell `$procdff$1959' with positive edge clock.                                                        \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\ecause_out_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\ecause_out_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1960\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1960' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\mret_out_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\mret_out_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1961\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1961' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\csr_read_data_out_reg' using process \n", + "`\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\csr_read_data_out_reg' using process                                        \n",
+              "`\\Memory.$proc$/content/core.v:2287$824'.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1962\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1962' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\csr_write_enable_out_reg' using process \n", + "`\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\csr_write_enable_out_reg' using process                                     \n",
+              "`\\Memory.$proc$/content/core.v:2287$824'.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1963\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1963' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\csr_write_address_out_reg' using process \n", + "`\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\csr_write_address_out_reg' using process                                    \n",
+              "`\\Memory.$proc$/content/core.v:2287$824'.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1964\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1964' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\csr_write_data_out_reg' using process \n", + "`\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\csr_write_data_out_reg' using process                                       \n",
+              "`\\Memory.$proc$/content/core.v:2287$824'.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1965\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1965' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\trapped_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\trapped_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1966\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1966' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\interrupt_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\interrupt_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1967\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1967' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\inst_retired_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\inst_retired_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1968\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1968' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\wb_reg_pc_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\wb_reg_pc_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1969\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1969' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\wb_readdata_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\wb_readdata_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1970\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1970' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\wb_aluresult_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\wb_aluresult_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1971\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1971' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\wb_memtoreg_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\wb_memtoreg_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1972\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1972' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\wb_regwrite_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\wb_regwrite_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1973\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1973' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\wb_rd_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\wb_rd_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1974\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1974' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\pcsrc_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\pcsrc_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1975\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1975' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Memory.\\branch_reg' using process `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Memory.\\branch_reg' using process `\\Memory.$proc$/content/core.v:2287$824'.         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1976\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1976' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\ecause_out_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\ecause_out_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1977\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1977' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\exception_out_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'.\n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\exception_out_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.\n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1978\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1978' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mret_out_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mret_out_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1979\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1979' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\wfi_out_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\wfi_out_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1980\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1980' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\csr_read_data_out_reg' using process \n", + "`\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\csr_read_data_out_reg' using process                                       \n",
+              "`\\Execute.$proc$/content/core.v:1866$752'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1981\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1981' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\csr_write_enable_out_reg' using process \n", + "`\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\csr_write_enable_out_reg' using process                                    \n",
+              "`\\Execute.$proc$/content/core.v:1866$752'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1982\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1982' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\csr_write_address_out_reg' using process \n", + "`\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\csr_write_address_out_reg' using process                                   \n",
+              "`\\Execute.$proc$/content/core.v:1866$752'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1983\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1983' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\csr_write_data_out_reg' using process \n", + "`\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\csr_write_data_out_reg' using process                                      \n",
+              "`\\Execute.$proc$/content/core.v:1866$752'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1984\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1984' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\reg_pc_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\reg_pc_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1985\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1985' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\target_pc_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\target_pc_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1986\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1986' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_pc_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_pc_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1987\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1987' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_isbranch_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_isbranch_reg' using process `\\Execute.$proc$/content/core.v:1866$752'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1988\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1988' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_isjump_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_isjump_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1989\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1989' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_memread_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_memread_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1990\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1990' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_memwrite_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_memwrite_reg' using process `\\Execute.$proc$/content/core.v:1866$752'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1991\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1991' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_regwrite_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_regwrite_reg' using process `\\Execute.$proc$/content/core.v:1866$752'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1992\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1992' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_memtoreg_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_memtoreg_reg' using process `\\Execute.$proc$/content/core.v:1866$752'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1993\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1993' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_zero_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_zero_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1994\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1994' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_aluresult_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'.\n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_aluresult_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.\n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1995\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1995' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_rs2_data_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_rs2_data_reg' using process `\\Execute.$proc$/content/core.v:1866$752'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1996\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1996' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_funct3_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_funct3_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1997\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1997' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Execute.\\mem_rd_reg' using process `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Execute.\\mem_rd_reg' using process `\\Execute.$proc$/content/core.v:1866$752'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1998\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1998' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\csr_read_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\csr_read_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m1999\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$1999' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\csr_write_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\csr_write_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2000\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2000' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\csr_address_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\csr_address_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2001\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2001' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\ecause_out_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\ecause_out_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2002\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2002' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\exception_out_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\exception_out_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2003\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2003' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\mret_out_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\mret_out_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2004\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2004' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\wfi_out_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\wfi_out_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2005\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2005' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_pc_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_pc_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2006\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2006' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_aluop_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_aluop_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2007\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2007' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_immsrc_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_immsrc_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2008\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2008' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_isbranch_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_isbranch_reg' using process `\\Decode.$proc$/content/core.v:1281$675'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2009\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2009' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_memread_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_memread_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2010\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2010' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Decode.\\id_ex_memwrite_reg' using process `\\Decode.$proc$/content/core.v:1281$675'. \n",
+              "
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created $dff cell `$procdff$2011' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Decode.\\id_ex_regwrite_reg' using process `\\Decode.$proc$/content/core.v:1281$675'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2012\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2012' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Decode.\\id_ex_memtoreg_reg' using process `\\Decode.$proc$/content/core.v:1281$675'. \n",
+              "
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created $dff cell `$procdff$2013' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_pcsel_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_pcsel_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2014\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2014' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_rdsel_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_rdsel_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2015\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2015' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_isjump_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_isjump_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2016\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2016' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_islui_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_islui_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2017\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2017' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_rs1_data_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_rs1_data_reg' using process `\\Decode.$proc$/content/core.v:1281$675'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2018\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2018' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_rs2_data_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_rs2_data_reg' using process `\\Decode.$proc$/content/core.v:1281$675'. \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2019\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2019' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_imm_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_imm_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2020\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2020' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_funct3_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_funct3_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2021\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2021' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_ex_rs1_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_ex_rs1_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2022\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2022' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_ex_rs2_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_ex_rs2_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2023\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2023' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_ex_rd_reg' using process `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_ex_rd_reg' using process `\\Decode.$proc$/content/core.v:1281$675'.    \n",
+              "
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created $dff cell `$procdff$2024' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_ex_use_rs1_reg' using process \n", + "`\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_ex_use_rs1_reg' using process                                         \n",
+              "`\\Decode.$proc$/content/core.v:1281$675'.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2025\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2025' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Decode.\\id_ex_ex_use_rs2_reg' using process \n", + "`\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Decode.\\id_ex_ex_use_rs2_reg' using process                                         \n",
+              "`\\Decode.$proc$/content/core.v:1281$675'.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2026\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2026' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_0' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_0' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
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created $dff cell `$procdff$2027' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_1' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_1' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2028\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2028' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_2' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_2' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2029\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2029' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_3' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_3' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2030\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2030' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_4' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_4' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2031\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2031' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_5' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_5' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2032\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2032' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_6' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_6' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2033\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2033' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_7' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_7' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2034\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2034' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Regfile.\\registers_8' using process `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Regfile.\\registers_8' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
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created $dff cell `$procdff$2035' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_9' using process `\\Regfile.$proc$/content/core.v:629$392'.       \n",
+              "
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created $dff cell `$procdff$2036' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_10' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2037' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_11' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
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created $dff cell `$procdff$2038' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_12' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2039' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_13' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2040' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_14' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2041' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_15' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2042' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_16' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2043' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_17' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2044' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_18' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2045' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_19' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2046' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_20' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2047' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_21' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2048' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_22' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2049' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_23' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2050' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_24' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2051' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_25' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2052' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_26' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2053' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_27' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
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created $dff cell `$procdff$2054' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_28' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2055' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_29' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2056' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_30' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2057' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Regfile.\\registers_31' using process `\\Regfile.$proc$/content/core.v:629$392'.      \n",
+              "
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created $dff cell `$procdff$2058' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Fetch.\\pcReg' using process `\\Fetch.$proc$/content/core.v:323$70'.                  \n",
+              "
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created $dff cell `$procdff$2059' with positive edge clock.                                                        \n",
+              "
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Creating register for signal `\\Fetch.\\idPcReg' using process `\\Fetch.$proc$/content/core.v:323$70'.                \n",
+              "
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created $dff cell `$procdff$2060' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\Fetch.\\instReg' using process `\\Fetch.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m323\u001b[0m$\u001b[1;36m70\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\Fetch.\\instReg' using process `\\Fetch.$proc$/content/core.v:323$70'.                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2061\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2061' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BTB.$memwr$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m194\u001b[0m$30_ADDR' using process \n", + "`\\BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BTB.$memwr$\\btbTable$/content/core.v:194$30_ADDR' using process                     \n",
+              "`\\BTB.$proc$/content/core.v:192$50'.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2062\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2062' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BTB.$memwr$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m194\u001b[0m$30_DATA' using process \n", + "`\\BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BTB.$memwr$\\btbTable$/content/core.v:194$30_DATA' using process                     \n",
+              "`\\BTB.$proc$/content/core.v:192$50'.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2063\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2063' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BTB.$memwr$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m194\u001b[0m$30_EN' using process \n", + "`\\BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BTB.$memwr$\\btbTable$/content/core.v:194$30_EN' using process                       \n",
+              "`\\BTB.$proc$/content/core.v:192$50'.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2064\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2064' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BTB.$memwr$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m197\u001b[0m$31_ADDR' using process \n", + "`\\BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BTB.$memwr$\\btbTable$/content/core.v:197$31_ADDR' using process                     \n",
+              "`\\BTB.$proc$/content/core.v:192$50'.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2065\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2065' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BTB.$memwr$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m197\u001b[0m$31_DATA' using process \n", + "`\\BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BTB.$memwr$\\btbTable$/content/core.v:197$31_DATA' using process                     \n",
+              "`\\BTB.$proc$/content/core.v:192$50'.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2066\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2066' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BTB.$memwr$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m197\u001b[0m$31_EN' using process \n", + "`\\BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BTB.$memwr$\\btbTable$/content/core.v:197$31_EN' using process                       \n",
+              "`\\BTB.$proc$/content/core.v:192$50'.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2067\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2067' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m66\u001b[0m$1_ADDR' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$/content/core.v:66$1_ADDR' using process                   \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2068\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2068' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m66\u001b[0m$1_DATA' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$/content/core.v:66$1_DATA' using process                   \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2069\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2069' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m66\u001b[0m$1_EN' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$/content/core.v:66$1_EN' using process                     \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2070\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2070' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m69\u001b[0m$2_ADDR' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$/content/core.v:69$2_ADDR' using process                 \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2071\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2071' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m69\u001b[0m$2_DATA' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$/content/core.v:69$2_DATA' using process                 \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2072\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2072' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m69\u001b[0m$2_EN' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$/content/core.v:69$2_EN' using process                   \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2073\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2073' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m72\u001b[0m$3_ADDR' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$/content/core.v:72$3_ADDR' using process             \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2074\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2074' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m72\u001b[0m$3_DATA' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$/content/core.v:72$3_DATA' using process             \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2075\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2075' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m72\u001b[0m$3_EN' using process \n", + "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n" + ], + "text/html": [ + "
Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$/content/core.v:72$3_EN' using process               \n",
+              "`\\BHT.$proc$/content/core.v:64$8'.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created $dff cell `$procdff$\u001b[1;36m2076\u001b[0m' with positive edge clock. \n" + ], + "text/html": [ + "
created $dff cell `$procdff$2076' with positive edge clock.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m16\u001b[0m. Executing PROC_MEMWR pass \u001b[1m(\u001b[0mconvert process memory writes to cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
16. Executing PROC_MEMWR pass (convert process memory writes to cells).                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m17\u001b[0m. Executing PROC_CLEAN pass \u001b[1m(\u001b[0mremove empty switches from decision trees\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
17. Executing PROC_CLEAN pass (remove empty switches from decision trees).                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found and cleaned up \u001b[1;36m51\u001b[0m empty switches in `\\CSR.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2638\u001b[0m$\u001b[1;36m1025\u001b[0m'. \n" + ], + "text/html": [ + "
Found and cleaned up 51 empty switches in `\\CSR.$proc$/content/core.v:2638$1025'.                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removing empty process `CSR.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2638\u001b[0m$\u001b[1;36m1025\u001b[0m'. \n" + ], + "text/html": [ + "
Removing empty process `CSR.$proc$/content/core.v:2638$1025'.                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found and cleaned up \u001b[1;36m28\u001b[0m empty switches in `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Found and cleaned up 28 empty switches in `\\Memory.$proc$/content/core.v:2287$824'.                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removing empty process `Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n" + ], + "text/html": [ + "
Removing empty process `Memory.$proc$/content/core.v:2287$824'.                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found and cleaned up \u001b[1;36m45\u001b[0m empty switches in `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Found and cleaned up 45 empty switches in `\\Execute.$proc$/content/core.v:1866$752'.                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removing empty process `Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n" + ], + "text/html": [ + "
Removing empty process `Execute.$proc$/content/core.v:1866$752'.                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found and cleaned up \u001b[1;36m58\u001b[0m empty switches in `\\Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n" + ], + "text/html": [ + "
Found and cleaned up 58 empty switches in `\\Decode.$proc$/content/core.v:1281$675'.                                \n",
+              "
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Removing empty process `Decode.$proc$/content/core.v:1281$675'.                                                    \n",
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Removing empty process `Regfile.$proc$/content/core.v:629$392'.                                                    \n",
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Removing empty process `Fetch.$proc$/content/core.v:323$70'.                                                       \n",
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Removing empty process `BTB.$proc$/content/core.v:192$50'.                                                         \n",
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Removing empty process `BHT.$proc$/content/core.v:64$8'.                                                           \n",
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Cleaned up 293 empty switches.                                                                                     \n",
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18. Executing CHECK pass (checking for obvious problems).                                                          \n",
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Checking module core...                                                                                            \n",
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Checking module Hazard...                                                                                          \n",
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Checking module CSR...                                                                                             \n",
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Checking module Writeback...                                                                                       \n",
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Checking module Memory...                                                                                          \n",
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Checking module Branch...                                                                                          \n",
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Checking module Execute...                                                                                         \n",
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Checking module TargetGen...                                                                                       \n",
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Checking module ALU...                                                                                             \n",
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Checking module AluSelect...                                                                                       \n",
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Checking module Decode...                                                                                          \n",
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Checking module ImmGen...                                                                                          \n",
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Checking module Regfile...                                                                                         \n",
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Checking module Control...                                                                                         \n",
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Checking module Fetch...                                                                                           \n",
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Checking module BTB...                                                                                             \n",
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Checking module BHT...                                                                                             \n",
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Found and reported 0 problems.                                                                                     \n",
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19. Executing OPT_EXPR pass (perform const folding).                                                               \n",
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Optimizing module core.                                                                                            \n",
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Optimizing module Hazard.                                                                                          \n",
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<suppressed ~4 debug messages>                                                                                     \n",
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Optimizing module CSR.                                                                                             \n",
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<suppressed ~11 debug messages>                                                                                    \n",
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Optimizing module Writeback.                                                                                       \n",
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Optimizing module Memory.                                                                                          \n",
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<suppressed ~11 debug messages>                                                                                    \n",
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Optimizing module Branch.                                                                                          \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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Optimizing module Execute.                                                                                         \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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Optimizing module TargetGen.                                                                                       \n",
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Optimizing module ALU.                                                                                             \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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Optimizing module AluSelect.                                                                                       \n",
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<suppressed ~2 debug messages>                                                                                     \n",
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Optimizing module Decode.                                                                                          \n",
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<suppressed ~7 debug messages>                                                                                     \n",
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Optimizing module ImmGen.                                                                                          \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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Optimizing module Regfile.                                                                                         \n",
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<suppressed ~35 debug messages>                                                                                    \n",
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Optimizing module Control.                                                                                         \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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Optimizing module Fetch.                                                                                           \n",
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<suppressed ~2 debug messages>                                                                                     \n",
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Optimizing module BTB.                                                                                             \n",
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<suppressed ~2 debug messages>                                                                                     \n",
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Optimizing module BHT.                                                                                             \n",
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<suppressed ~3 debug messages>                                                                                     \n",
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20. Executing FLATTEN pass (flatten design).                                                                       \n",
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Deleting now unused module Hazard.                                                                                 \n",
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Deleting now unused module CSR.                                                                                    \n",
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Deleting now unused module Writeback.                                                                              \n",
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Deleting now unused module Memory.                                                                                 \n",
+              "
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Deleting now unused module Branch.                                                                                 \n",
+              "
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Deleting now unused module Execute.                                                                                \n",
+              "
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Deleting now unused module TargetGen.                                                                              \n",
+              "
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Deleting now unused module ALU.                                                                                    \n",
+              "
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Deleting now unused module AluSelect.                                                                              \n",
+              "
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Deleting now unused module Decode.                                                                                 \n",
+              "
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Deleting now unused module ImmGen.                                                                                 \n",
+              "
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Deleting now unused module Regfile.                                                                                \n",
+              "
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Deleting now unused module Control.                                                                                \n",
+              "
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Deleting now unused module Fetch.                                                                                  \n",
+              "
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Deleting now unused module BTB.                                                                                    \n",
+              "
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Deleting now unused module BHT.                                                                                    \n",
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<suppressed ~16 debug messages>                                                                                    \n",
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21. Executing OPT_EXPR pass (perform const folding).                                                               \n",
+              "
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Optimizing module core.                                                                                            \n",
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22. Executing OPT_CLEAN pass (remove unused cells and wires).                                                      \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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Removed 36 unused cells and 930 unused wires.                                                                      \n",
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<suppressed ~42 debug messages>                                                                                    \n",
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23. Executing OPT pass (performing simple optimizations).                                                          \n",
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23.1. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
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Optimizing module core.                                                                                            \n",
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23.2. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
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<suppressed ~915 debug messages>                                                                                   \n",
+              "
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Removed a total of 305 cells.                                                                                      \n",
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23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                              \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
+              "
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Evaluating internal representation of mux trees.                                                                   \n",
+              "
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Analyzing evaluation results.                                                                                      \n",
+              "
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Removed 0 multiplexer ports.                                                                                       \n",
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<suppressed ~158 debug messages>                                                                                   \n",
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23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                          \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
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Consolidated identical input bits for $mux cell $flatten\\fetch.\\bht.$procmux$1920:                                 \n",
+              "
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Old ports: A=0, B=32'11111111111111111111111111111111,                                                             \n",
+              "Y=$flatten\\fetch.\\bht.$0$memwr$\\bhtTable_target_pc$/content/core.v:72$3_EN[31:0]$17                                \n",
+              "
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New ports: A=1'0, B=1'1, Y=$flatten\\fetch.\\bht.$0$memwr$\\bhtTable_target_pc$/content/core.v:72$3_EN[31:0]$17 [0]   \n",
+              "
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Consolidated identical input bits for $mux cell $flatten\\fetch.\\bht.$procmux$1938:                                 \n",
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Old ports: A=26'00000000000000000000000000, B=26'11111111111111111111111111,                                       \n",
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New connections: $flatten\\fetch.\\bht.$0$memwr$\\bhtTable_tag$/content/core.v:66$1_EN[25:0]$11 [25:1] = {            \n",
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Consolidated identical input bits for $mux cell $flatten\\fetch.\\btb.$procmux$1902:                                 \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Old ports: \u001b[33mA\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m11\u001b[0m, \u001b[33mY\u001b[0m=$flatten\\fetch.\\btb.$\u001b[1;36m0\u001b[0m$memwr$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m197\u001b[0m$31_EN\u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m56\u001b[0m \n" + ], + "text/html": [ + "
Old ports: A=2'00, B=2'11, Y=$flatten\\fetch.\\btb.$0$memwr$\\btbTable$/content/core.v:197$31_EN[1:0]$56              \n",
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New ports: A=1'0, B=1'1, Y=$flatten\\fetch.\\btb.$0$memwr$\\btbTable$/content/core.v:197$31_EN[1:0]$56 [0]            \n",
+              "
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New connections: $flatten\\fetch.\\btb.$0$memwr$\\btbTable$/content/core.v:197$31_EN[1:0]$56 [1] =                    \n",
+              "$flatten\\fetch.\\btb.$0$memwr$\\btbTable$/content/core.v:197$31_EN[1:0]$56 [0]                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\fetch.\\btb.$procmux$\u001b[1;36m1911\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\fetch.\\btb.$procmux$1911:                                 \n",
+              "
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Old ports: A=2'00, B=2'11, Y=$flatten\\fetch.\\btb.$0$memwr$\\btbTable$/content/core.v:194$30_EN[1:0]$53              \n",
+              "
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New ports: A=1'0, B=1'1, Y=$flatten\\fetch.\\btb.$0$memwr$\\btbTable$/content/core.v:194$30_EN[1:0]$53 [0]            \n",
+              "
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New connections: $flatten\\fetch.\\btb.$0$memwr$\\btbTable$/content/core.v:194$30_EN[1:0]$53 [1] =                    \n",
+              "$flatten\\fetch.\\btb.$0$memwr$\\btbTable$/content/core.v:194$30_EN[1:0]$53 [0]                                       \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
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Performed a total of 4 changes.                                                                                    \n",
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23.5. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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<suppressed ~12 debug messages>                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed a total of \u001b[1;36m4\u001b[0m cells. \n" + ], + "text/html": [ + "
Removed a total of 4 cells.                                                                                        \n",
+              "
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+              "
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23.6. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
+              "
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+              "
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23.7. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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Removed 0 unused cells and 303 unused wires.                                                                       \n",
+              "
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<suppressed ~1 debug messages>                                                                                     \n",
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23.8. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
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Optimizing module core.                                                                                            \n",
+              "
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+              "
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23.9. Rerunning OPT passes. (Maybe there is more to do..)                                                          \n",
+              "
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+              "
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23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
+              "
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Evaluating internal representation of mux trees.                                                                   \n",
+              "
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Analyzing evaluation results.                                                                                      \n",
+              "
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Removed 0 multiplexer ports.                                                                                       \n",
+              "
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<suppressed ~154 debug messages>                                                                                   \n",
+              "
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+              "
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23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Performed a total of \u001b[1;36m0\u001b[0m changes. \n" + ], + "text/html": [ + "
Performed a total of 0 changes.                                                                                    \n",
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23.12. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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Removed a total of 0 cells.                                                                                        \n",
+              "
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23.13. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
+              "
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+              "
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23.14. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
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+              "
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23.15. Executing OPT_EXPR pass (perform const folding).                                                            \n",
+              "
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Optimizing module core.                                                                                            \n",
+              "
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+              "
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23.16. Finished OPT passes. (There is nothing left to do.)                                                         \n",
+              "
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24. Executing FSM pass (extract and optimize FSM).                                                                 \n",
+              "
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24.1. Executing FSM_DETECT pass (finding FSMs in design).                                                          \n",
+              "
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Not marking core.decode.ecause_out_reg as FSM state register:                                                      \n",
+              "
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Users of register don't seem to benefit from recoding.                                                             \n",
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Not marking core.decode.id_ex_memtoreg_reg as FSM state register:                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Users of register don't seem to benefit from recoding. \n" + ], + "text/html": [ + "
Users of register don't seem to benefit from recoding.                                                             \n",
+              "
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+              "
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24.2. Executing FSM_EXTRACT pass (extracting FSM from design).                                                     \n",
+              "
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m24.3\u001b[0m. Executing FSM_OPT pass \u001b[1m(\u001b[0msimple optimizations of FSMs\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
24.3. Executing FSM_OPT pass (simple optimizations of FSMs).                                                       \n",
+              "
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m24.4\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
24.4. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding unused cells or wires in module \\core.. \n" + ], + "text/html": [ + "
Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m24.5\u001b[0m. Executing FSM_OPT pass \u001b[1m(\u001b[0msimple optimizations of FSMs\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
24.5. Executing FSM_OPT pass (simple optimizations of FSMs).                                                       \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m24.6\u001b[0m. Executing FSM_RECODE pass \u001b[1m(\u001b[0mre-assigning FSM state encoding\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).                                                 \n",
+              "
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m24.7\u001b[0m. Executing FSM_INFO pass \u001b[1m(\u001b[0mdumping all available information on FSM cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
24.7. Executing FSM_INFO pass (dumping all available information on FSM cells).                                    \n",
+              "
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+              "
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24.8. Executing FSM_MAP pass (mapping FSMs to basic logic).                                                        \n",
+              "
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m25\u001b[0m. Executing OPT pass \u001b[1m(\u001b[0mperforming simple optimizations\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
25. Executing OPT pass (performing simple optimizations).                                                          \n",
+              "
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m25.1\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
25.1. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing module core. \n" + ], + "text/html": [ + "
Optimizing module core.                                                                                            \n",
+              "
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m25.2\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
25.2. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding identical cells in module `\\core'. \n" + ], + "text/html": [ + "
Finding identical cells in module `\\core'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed a total of \u001b[1;36m0\u001b[0m cells. \n" + ], + "text/html": [ + "
Removed a total of 0 cells.                                                                                        \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m25.3\u001b[0m. Executing OPT_MUXTREE pass \u001b[1m(\u001b[0mdetect dead branches in mux trees\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Running muxtree optimizer on module \\core.. \n" + ], + "text/html": [ + "
Running muxtree optimizer on module \\core..                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating internal representation of mux trees. \n" + ], + "text/html": [ + "
Creating internal representation of mux trees.                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Evaluating internal representation of mux trees. \n" + ], + "text/html": [ + "
Evaluating internal representation of mux trees.                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing evaluation results. \n" + ], + "text/html": [ + "
Analyzing evaluation results.                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed \u001b[1;36m0\u001b[0m multiplexer ports. \n" + ], + "text/html": [ + "
Removed 0 multiplexer ports.                                                                                       \n",
+              "
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<suppressed ~154 debug messages>                                                                                   \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m25.4\u001b[0m. Executing OPT_REDUCE pass \u001b[1m(\u001b[0mconsolidate $*mux and $reduce_* inputs\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing cells in module \\core. \n" + ], + "text/html": [ + "
Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Performed a total of \u001b[1;36m0\u001b[0m changes. \n" + ], + "text/html": [ + "
Performed a total of 0 changes.                                                                                    \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m25.5\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
25.5. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding identical cells in module `\\core'. \n" + ], + "text/html": [ + "
Finding identical cells in module `\\core'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed a total of \u001b[1;36m0\u001b[0m cells. \n" + ], + "text/html": [ + "
Removed a total of 0 cells.                                                                                        \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m25.6\u001b[0m. Executing OPT_DFF pass \u001b[1m(\u001b[0mperform DFF optimizations\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
25.6. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1976\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory._GEN_32, Q = \n", + "\\memory.branch_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1976 ($dff) from module core (D = \\memory._GEN_32, Q =              \n",
+              "\\memory.branch_reg, rval = 1'0).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1975\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory._GEN_31, Q = \n", + "\\memory.pcsrc_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1975 ($dff) from module core (D = \\memory._GEN_31, Q =              \n",
+              "\\memory.pcsrc_reg, rval = 1'0).                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1974\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_rd_reg, Q = \n", + "\\memory.wb_rd_reg, rval = \u001b[1;36m5\u001b[0m'\u001b[1;36m00000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1974 ($dff) from module core (D = \\execute.mem_rd_reg, Q =          \n",
+              "\\memory.wb_rd_reg, rval = 5'00000).                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1973\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory._GEN_29, Q = \n", + "\\memory.wb_regwrite_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1973 ($dff) from module core (D = \\memory._GEN_29, Q =              \n",
+              "\\memory.wb_regwrite_reg, rval = 1'0).                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1972\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_memtoreg_reg, Q = \n", + "\\memory.wb_memtoreg_reg, rval = \u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1972 ($dff) from module core (D = \\execute.mem_memtoreg_reg, Q =    \n",
+              "\\memory.wb_memtoreg_reg, rval = 2'00).                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1971\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_aluresult_reg, Q = \n", + "\\memory.wb_aluresult_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1971 ($dff) from module core (D = \\execute.mem_aluresult_reg, Q =   \n",
+              "\\memory.wb_aluresult_reg, rval = 0).                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1970\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\io_memory_read_data, Q = \n", + "\\memory.wb_readdata_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1970 ($dff) from module core (D = \\io_memory_read_data, Q =         \n",
+              "\\memory.wb_readdata_reg, rval = 0).                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1969\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.reg_pc_reg, Q = \n", + "\\memory.wb_reg_pc_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1969 ($dff) from module core (D = \\execute.reg_pc_reg, Q =          \n",
+              "\\memory.wb_reg_pc_reg, rval = 0).                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1968\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory._GEN_21, Q = \n", + "\\memory.inst_retired_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1968 ($dff) from module core (D = \\memory._GEN_21, Q =              \n",
+              "\\memory.inst_retired_reg, rval = 1'0).                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1967\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory._GEN_20, Q = \n", + "\\memory.interrupt_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1967 ($dff) from module core (D = \\memory._GEN_20, Q =              \n",
+              "\\memory.interrupt_reg, rval = 1'0).                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1966\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory._GEN_19, Q = \n", + "\\memory.trapped_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1966 ($dff) from module core (D = \\memory._GEN_19, Q =              \n",
+              "\\memory.trapped_reg, rval = 1'0).                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1965\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.csr_write_data_out_reg, Q\n", + "= \\memory.csr_write_data_out_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1965 ($dff) from module core (D = \\execute.csr_write_data_out_reg, Q\n",
+              "= \\memory.csr_write_data_out_reg, rval = 0).                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1964\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.csr_write_address_out_reg, Q = \\memory.csr_write_address_out_reg, rval = \u001b[1;36m12\u001b[0m'\u001b[1;36m000000000000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1964 ($dff) from module core (D =                                   \n",
+              "\\execute.csr_write_address_out_reg, Q = \\memory.csr_write_address_out_reg, rval = 12'000000000000).                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1963\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory._GEN_15, Q = \n", + "\\memory.csr_write_enable_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1963 ($dff) from module core (D = \\memory._GEN_15, Q =              \n",
+              "\\memory.csr_write_enable_out_reg, rval = 1'0).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1962\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.csr_read_data_out_reg, Q \n", + "= \\memory.csr_read_data_out_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1962 ($dff) from module core (D = \\execute.csr_read_data_out_reg, Q \n",
+              "= \\memory.csr_read_data_out_reg, rval = 0).                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1961\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory._GEN_22, Q = \n", + "\\memory.mret_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1961 ($dff) from module core (D = \\memory._GEN_22, Q =              \n",
+              "\\memory.mret_out_reg, rval = 1'0).                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1960\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \u001b[1m{\u001b[0m $flatten\\memory.$procmux$1318_Y \n", + "\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m $flatten\\memory.$procmux$1318_Y \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, Q = \u001b[1m{\u001b[0m \\memory.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m \\memory.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, rval \n", + "= \u001b[1;36m3\u001b[0m'\u001b[1;36m000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1960 ($dff) from module core (D = { $flatten\\memory.$procmux$1318_Y \n",
+              "[3] $flatten\\memory.$procmux$1318_Y [1:0] }, Q = { \\memory.ecause_out_reg [3] \\memory.ecause_out_reg [1:0] }, rval \n",
+              "= 3'000).                                                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\memory.$procdff$\u001b[1;36m1960\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\memory.$procmux$1315_Y \n", + "\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m, Q = \\memory.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\memory.$procdff$1960 ($dff) from module core (D = $flatten\\memory.$procmux$1315_Y   \n",
+              "[2], Q = \\memory.ecause_out_reg [2], rval = 1'0).                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\fetch.$procdff$\u001b[1;36m2061\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \u001b[1m{\u001b[0m $flatten\\fetch.$procmux$1888_Y \n", + "\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m $flatten\\fetch.$procmux$1888_Y \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, Q = \u001b[1m{\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, rval = \u001b[1;36m3\u001b[0m'\u001b[1;36m000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\fetch.$procdff$2061 ($dff) from module core (D = { $flatten\\fetch.$procmux$1888_Y   \n",
+              "[4] $flatten\\fetch.$procmux$1888_Y [1:0] }, Q = { \\fetch.instReg [4] \\fetch.instReg [1:0] }, rval = 3'000).        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\fetch.$procdff$\u001b[1;36m2061\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \u001b[1m{\u001b[0m $flatten\\fetch.$procmux$1885_Y \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:5\u001b[0m\u001b[1m]\u001b[0m $flatten\\fetch.$procmux$1885_Y \u001b[1m[\u001b[0m\u001b[1;92m3:2\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, Q = \u001b[1m{\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m31:5\u001b[0m\u001b[1m]\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m3:2\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, rval = \n", + "\u001b[1;36m29\u001b[0m'\u001b[1;36m00000000000000000000000000000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\fetch.$procdff$2061 ($dff) from module core (D = { $flatten\\fetch.$procmux$1885_Y   \n",
+              "[31:5] $flatten\\fetch.$procmux$1885_Y [3:2] }, Q = { \\fetch.instReg [31:5] \\fetch.instReg [3:2] }, rval =          \n",
+              "29'00000000000000000000000000000).                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2121\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \u001b[1m{\u001b[0m \\io_fetch_data \u001b[1m[\u001b[0m\u001b[1;92m31:5\u001b[0m\u001b[1m]\u001b[0m \\io_fetch_data\n", + "\u001b[1m[\u001b[0m\u001b[1;92m3:2\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, Q = \u001b[1m{\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m31:5\u001b[0m\u001b[1m]\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m3:2\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2121 ($sdff) from module core (D = { \\io_fetch_data [31:5] \\io_fetch_data\n",
+              "[3:2] }, Q = { \\fetch.instReg [31:5] \\fetch.instReg [3:2] }).                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2120\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \u001b[1m{\u001b[0m $flatten\\fetch.$procmux$1888_Y \u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m \n", + "$flatten\\fetch.$procmux$1888_Y \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, Q = \u001b[1m{\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2120 ($sdff) from module core (D = { $flatten\\fetch.$procmux$1888_Y [4]  \n",
+              "$flatten\\fetch.$procmux$1888_Y [1:0] }, Q = { \\fetch.instReg [4] \\fetch.instReg [1:0] }).                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\fetch.$procdff$\u001b[1;36m2060\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\fetch.$procmux$1893_Y, Q =\n", + "\\fetch.idPcReg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\fetch.$procdff$2060 ($dff) from module core (D = $flatten\\fetch.$procmux$1893_Y, Q =\n",
+              "\\fetch.idPcReg, rval = 0).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2128\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\fetch.pcReg, Q = \\fetch.idPcReg\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2128 ($sdff) from module core (D = \\fetch.pcReg, Q = \\fetch.idPcReg).    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\fetch.$procdff$\u001b[1;36m2059\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\fetch.$procmux$1880_Y, Q =\n", + "\\fetch.pcReg, rval = \u001b[1;36m8\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\fetch.$procdff$2059 ($dff) from module core (D = $flatten\\fetch.$procmux$1880_Y, Q =\n",
+              "\\fetch.pcReg, rval = 8).                                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2132\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\fetch.$procmux$1880_Y, Q = \n", + "\\fetch.pcReg\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2132 ($sdff) from module core (D = $flatten\\fetch.$procmux$1880_Y, Q =   \n",
+              "\\fetch.pcReg).                                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1998\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_ex_rd_reg, Q = \n", + "\\execute.mem_rd_reg, rval = \u001b[1;36m5\u001b[0m'\u001b[1;36m00000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1998 ($dff) from module core (D = \\decode.id_ex_ex_rd_reg, Q =     \n",
+              "\\execute.mem_rd_reg, rval = 5'00000).                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1997\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_funct3_reg, Q = \n", + "\\execute.mem_funct3_reg, rval = \u001b[1;36m3\u001b[0m'\u001b[1;36m000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1997 ($dff) from module core (D = \\decode.id_ex_funct3_reg, Q =    \n",
+              "\\execute.mem_funct3_reg, rval = 3'000).                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1996\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_rs2_data_reg, Q = \n", + "\\execute.mem_rs2_data_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1996 ($dff) from module core (D = \\decode.id_ex_rs2_data_reg, Q =  \n",
+              "\\execute.mem_rs2_data_reg, rval = 0).                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1995\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.alu._io_alu_result_T_19 \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:0\u001b[0m\u001b[1m]\u001b[0m, Q = \\execute.mem_aluresult_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1995 ($dff) from module core (D = \\execute.alu._io_alu_result_T_19 \n",
+              "[31:0], Q = \\execute.mem_aluresult_reg, rval = 0).                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1994\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.alu_io_zero, Q = \n", + "\\execute.mem_zero_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1994 ($dff) from module core (D = \\execute.alu_io_zero, Q =        \n",
+              "\\execute.mem_zero_reg, rval = 1'0).                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1993\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_memtoreg_reg, Q = \n", + "\\execute.mem_memtoreg_reg, rval = \u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1993 ($dff) from module core (D = \\decode.id_ex_memtoreg_reg, Q =  \n",
+              "\\execute.mem_memtoreg_reg, rval = 2'00).                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1992\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_regwrite_reg, Q = \n", + "\\execute.mem_regwrite_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1992 ($dff) from module core (D = \\decode.id_ex_regwrite_reg, Q =  \n",
+              "\\execute.mem_regwrite_reg, rval = 1'0).                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1991\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_memwrite_reg, Q = \n", + "\\execute.mem_memwrite_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1991 ($dff) from module core (D = \\decode.id_ex_memwrite_reg, Q =  \n",
+              "\\execute.mem_memwrite_reg, rval = 1'0).                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1990\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_memread_reg, Q = \n", + "\\execute.mem_memread_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1990 ($dff) from module core (D = \\decode.id_ex_memread_reg, Q =   \n",
+              "\\execute.mem_memread_reg, rval = 1'0).                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1989\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_isjump_reg, Q = \n", + "\\execute.mem_isjump_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1989 ($dff) from module core (D = \\decode.id_ex_isjump_reg, Q =    \n",
+              "\\execute.mem_isjump_reg, rval = 1'0).                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1988\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_isbranch_reg, Q = \n", + "\\execute.mem_isbranch_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1988 ($dff) from module core (D = \\decode.id_ex_isbranch_reg, Q =  \n",
+              "\\execute.mem_isbranch_reg, rval = 1'0).                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1987\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.id_ex_pc_reg, Q = \n", + "\\execute.mem_pc_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1987 ($dff) from module core (D = \\decode.id_ex_pc_reg, Q =        \n",
+              "\\execute.mem_pc_reg, rval = 0).                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1986\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.targetGen_io_target_pc, \n", + "Q = \\execute.target_pc_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1986 ($dff) from module core (D = \\execute.targetGen_io_target_pc, \n",
+              "Q = \\execute.target_pc_reg, rval = 0).                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1985\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.targetGen_io_reg_pc, Q =\n", + "\\execute.reg_pc_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1985 ($dff) from module core (D = \\execute.targetGen_io_reg_pc, Q =\n",
+              "\\execute.reg_pc_reg, rval = 0).                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1984\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\execute.$procmux$1422_Y,\n", + "Q = \\execute.csr_write_data_out_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1984 ($dff) from module core (D = $flatten\\execute.$procmux$1422_Y,\n",
+              "Q = \\execute.csr_write_data_out_reg, rval = 0).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1983\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.csr_address_reg, Q = \n", + "\\execute.csr_write_address_out_reg, rval = \u001b[1;36m12\u001b[0m'\u001b[1;36m000000000000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1983 ($dff) from module core (D = \\decode.csr_address_reg, Q =     \n",
+              "\\execute.csr_write_address_out_reg, rval = 12'000000000000).                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1982\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.csr_write_reg, Q = \n", + "\\execute.csr_write_enable_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1982 ($dff) from module core (D = \\decode.csr_write_reg, Q =       \n",
+              "\\execute.csr_write_enable_out_reg, rval = 1'0).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1981\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.io_csr_read_data, Q = \n", + "\\execute.csr_read_data_out_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1981 ($dff) from module core (D = \\execute.io_csr_read_data, Q =   \n",
+              "\\execute.csr_read_data_out_reg, rval = 0).                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1980\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.wfi_out_reg, Q = \n", + "\\execute.wfi_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1980 ($dff) from module core (D = \\decode.wfi_out_reg, Q =         \n",
+              "\\execute.wfi_out_reg, rval = 1'0).                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1979\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.mret_out_reg, Q = \n", + "\\execute.mret_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1979 ($dff) from module core (D = \\decode.mret_out_reg, Q =        \n",
+              "\\execute.mret_out_reg, rval = 1'0).                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1978\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\execute.$or$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1895\u001b[0m$755_Y, Q = \\execute.exception_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1978 ($dff) from module core (D =                                  \n",
+              "$flatten\\execute.$or$/content/core.v:1895$755_Y, Q = \\execute.exception_out_reg, rval = 1'0).                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1977\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \u001b[1m{\u001b[0m \\decode.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;92m3:2\u001b[0m\u001b[1m]\u001b[0m \n", + "\\decode.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, Q = \u001b[1m{\u001b[0m \\execute.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;92m3:2\u001b[0m\u001b[1m]\u001b[0m \\execute.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \u001b[1m}\u001b[0m, rval = \u001b[1;36m3\u001b[0m'\u001b[1;36m000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1977 ($dff) from module core (D = { \\decode.ecause_out_reg [3:2]   \n",
+              "\\decode.ecause_out_reg [0] }, Q = { \\execute.ecause_out_reg [3:2] \\execute.ecause_out_reg [0] }, rval = 3'000).    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\execute.$procdff$\u001b[1;36m1977\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\execute.$procmux$1455_Y \n", + "\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m, Q = \\execute.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\execute.$procdff$1977 ($dff) from module core (D = $flatten\\execute.$procmux$1455_Y \n",
+              "[1], Q = \\execute.ecause_out_reg [1], rval = 1'0).                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2058\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1651_Y, Q = \\decode.regfile.registers_31, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2058 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1651_Y, Q = \\decode.regfile.registers_31, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2205\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_31\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2205 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_31).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2057\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1658_Y, Q = \\decode.regfile.registers_30, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2057 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1658_Y, Q = \\decode.regfile.registers_30, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2209\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_30\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2209 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_30).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2056\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1665_Y, Q = \\decode.regfile.registers_29, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2056 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1665_Y, Q = \\decode.regfile.registers_29, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2213\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_29\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2213 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_29).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2055\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1672_Y, Q = \\decode.regfile.registers_28, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2055 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1672_Y, Q = \\decode.regfile.registers_28, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2217\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_28\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2217 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_28).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2054\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1679_Y, Q = \\decode.regfile.registers_27, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2054 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1679_Y, Q = \\decode.regfile.registers_27, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2221\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_27\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2221 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_27).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2053\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1686_Y, Q = \\decode.regfile.registers_26, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2053 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1686_Y, Q = \\decode.regfile.registers_26, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2225\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_26\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2225 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_26).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2052\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1693_Y, Q = \\decode.regfile.registers_25, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2052 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1693_Y, Q = \\decode.regfile.registers_25, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2229\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_25\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2229 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_25).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2051\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1700_Y, Q = \\decode.regfile.registers_24, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2051 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1700_Y, Q = \\decode.regfile.registers_24, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2233\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_24\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2233 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_24).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2050\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1707_Y, Q = \\decode.regfile.registers_23, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2050 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1707_Y, Q = \\decode.regfile.registers_23, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2237\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_23\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2237 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_23).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2049\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1714_Y, Q = \\decode.regfile.registers_22, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2049 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1714_Y, Q = \\decode.regfile.registers_22, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2241\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_22\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2241 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_22).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2048\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1721_Y, Q = \\decode.regfile.registers_21, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2048 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1721_Y, Q = \\decode.regfile.registers_21, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2245\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_21\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2245 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_21).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2047\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1728_Y, Q = \\decode.regfile.registers_20, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2047 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1728_Y, Q = \\decode.regfile.registers_20, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2249\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_20\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2249 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_20).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2046\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1735_Y, Q = \\decode.regfile.registers_19, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2046 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1735_Y, Q = \\decode.regfile.registers_19, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2253\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_19\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2253 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_19).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2045\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1742_Y, Q = \\decode.regfile.registers_18, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2045 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1742_Y, Q = \\decode.regfile.registers_18, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2257\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_18\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2257 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_18).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2044\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1749_Y, Q = \\decode.regfile.registers_17, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2044 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1749_Y, Q = \\decode.regfile.registers_17, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2261\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_17\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2261 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_17).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2043\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1756_Y, Q = \\decode.regfile.registers_16, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2043 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1756_Y, Q = \\decode.regfile.registers_16, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2265\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_16\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2265 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_16).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2042\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1763_Y, Q = \\decode.regfile.registers_15, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2042 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1763_Y, Q = \\decode.regfile.registers_15, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2269\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_15\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2269 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_15).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2041\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1770_Y, Q = \\decode.regfile.registers_14, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2041 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1770_Y, Q = \\decode.regfile.registers_14, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2273\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_14\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2273 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_14).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2040\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1777_Y, Q = \\decode.regfile.registers_13, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2040 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1777_Y, Q = \\decode.regfile.registers_13, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2277\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_13\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2277 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_13).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2039\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1784_Y, Q = \\decode.regfile.registers_12, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2039 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1784_Y, Q = \\decode.regfile.registers_12, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2281\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_12\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2281 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_12).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2038\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1791_Y, Q = \\decode.regfile.registers_11, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2038 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1791_Y, Q = \\decode.regfile.registers_11, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2285\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_11\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2285 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_11).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2037\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1798_Y, Q = \\decode.regfile.registers_10, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2037 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1798_Y, Q = \\decode.regfile.registers_10, rval = 0).                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2289\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_10\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2289 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_10).                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2036\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1805_Y, Q = \\decode.regfile.registers_9, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2036 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1805_Y, Q = \\decode.regfile.registers_9, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2293\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_9\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2293 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_9).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2035\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1812_Y, Q = \\decode.regfile.registers_8, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2035 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1812_Y, Q = \\decode.regfile.registers_8, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2297\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_8\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2297 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_8).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2034\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1819_Y, Q = \\decode.regfile.registers_7, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2034 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1819_Y, Q = \\decode.regfile.registers_7, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2301\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_7\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2301 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_7).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2033\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1826_Y, Q = \\decode.regfile.registers_6, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2033 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1826_Y, Q = \\decode.regfile.registers_6, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2305\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_6\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2305 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_6).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2032\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1833_Y, Q = \\decode.regfile.registers_5, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2032 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1833_Y, Q = \\decode.regfile.registers_5, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2309\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_5\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2309 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_5).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2031\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1840_Y, Q = \\decode.regfile.registers_4, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2031 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1840_Y, Q = \\decode.regfile.registers_4, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2313\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_4\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2313 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_4).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2030\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1847_Y, Q = \\decode.regfile.registers_3, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2030 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1847_Y, Q = \\decode.regfile.registers_3, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2317\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_3\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2317 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_3).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2029\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1854_Y, Q = \\decode.regfile.registers_2, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2029 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1854_Y, Q = \\decode.regfile.registers_2, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2321\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_2\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2321 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_2).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2028\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1861_Y, Q = \\decode.regfile.registers_1, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2028 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1861_Y, Q = \\decode.regfile.registers_1, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2325\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_1\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2325 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_1).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$\u001b[1;36m2027\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\decode.\\regfile.$procmux$1868_Y, Q = \\decode.regfile.registers_0, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2027 ($dff) from module core (D =                          \n",
+              "$flatten\\decode.\\regfile.$procmux$1868_Y, Q = \\decode.regfile.registers_0, rval = 0).                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2329\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile.io_writedata, Q = \n", + "\\decode.regfile.registers_0\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2329 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q =     \n",
+              "\\decode.regfile.registers_0).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2026\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_use_rs2, Q = \n", + "\\decode.id_ex_ex_use_rs2_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2026 ($dff) from module core (D = \\decode.control_io_use_rs2, Q =   \n",
+              "\\decode.id_ex_ex_use_rs2_reg, rval = 1'0).                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2025\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_use_rs1, Q = \n", + "\\decode.id_ex_ex_use_rs1_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2025 ($dff) from module core (D = \\decode.control_io_use_rs1, Q =   \n",
+              "\\decode.id_ex_ex_use_rs1_reg, rval = 1'0).                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2024\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m11:7\u001b[0m\u001b[1m]\u001b[0m, Q = \n", + "\\decode.id_ex_ex_rd_reg, rval = \u001b[1;36m5\u001b[0m'\u001b[1;36m00000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2024 ($dff) from module core (D = \\fetch.instReg [11:7], Q =        \n",
+              "\\decode.id_ex_ex_rd_reg, rval = 5'00000).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2023\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m24:20\u001b[0m\u001b[1m]\u001b[0m, Q = \n", + "\\decode.id_ex_ex_rs2_reg, rval = \u001b[1;36m5\u001b[0m'\u001b[1;36m00000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2023 ($dff) from module core (D = \\fetch.instReg [24:20], Q =       \n",
+              "\\decode.id_ex_ex_rs2_reg, rval = 5'00000).                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2022\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m19:15\u001b[0m\u001b[1m]\u001b[0m, Q = \n", + "\\decode.id_ex_ex_rs1_reg, rval = \u001b[1;36m5\u001b[0m'\u001b[1;36m00000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2022 ($dff) from module core (D = \\fetch.instReg [19:15], Q =       \n",
+              "\\decode.id_ex_ex_rs1_reg, rval = 5'00000).                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2021\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m14:12\u001b[0m\u001b[1m]\u001b[0m, Q = \n", + "\\decode.id_ex_funct3_reg, rval = \u001b[1;36m3\u001b[0m'\u001b[1;36m000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2021 ($dff) from module core (D = \\fetch.instReg [14:12], Q =       \n",
+              "\\decode.id_ex_funct3_reg, rval = 3'000).                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2020\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.immGen._GEN_15, Q = \n", + "\\decode.id_ex_imm_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2020 ($dff) from module core (D = \\decode.immGen._GEN_15, Q =       \n",
+              "\\decode.id_ex_imm_reg, rval = 0).                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2019\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile._GEN_63, Q = \n", + "\\decode.id_ex_rs2_data_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2019 ($dff) from module core (D = \\decode.regfile._GEN_63, Q =      \n",
+              "\\decode.id_ex_rs2_data_reg, rval = 0).                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2018\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.regfile._GEN_31, Q = \n", + "\\decode.id_ex_rs1_data_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2018 ($dff) from module core (D = \\decode.regfile._GEN_31, Q =      \n",
+              "\\decode.id_ex_rs1_data_reg, rval = 0).                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2017\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_islui, Q = \n", + "\\decode.id_ex_islui_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2017 ($dff) from module core (D = \\decode.control_io_islui, Q =     \n",
+              "\\decode.id_ex_islui_reg, rval = 1'0).                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2016\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_isjump, Q = \n", + "\\decode.id_ex_isjump_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2016 ($dff) from module core (D = \\decode.control_io_isjump, Q =    \n",
+              "\\decode.id_ex_isjump_reg, rval = 1'0).                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2015\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_rdsel, Q = \n", + "\\decode.id_ex_rdsel_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2015 ($dff) from module core (D = \\decode.control_io_rdsel, Q =     \n",
+              "\\decode.id_ex_rdsel_reg, rval = 1'0).                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2014\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_pcsel, Q = \n", + "\\decode.id_ex_pcsel_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2014 ($dff) from module core (D = \\decode.control_io_pcsel, Q =     \n",
+              "\\decode.id_ex_pcsel_reg, rval = 1'0).                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2013\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_memtoreg, Q = \n", + "\\decode.id_ex_memtoreg_reg, rval = \u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2013 ($dff) from module core (D = \\decode.control_io_memtoreg, Q =  \n",
+              "\\decode.id_ex_memtoreg_reg, rval = 2'00).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2012\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_regwrite, Q = \n", + "\\decode.id_ex_regwrite_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2012 ($dff) from module core (D = \\decode.control_io_regwrite, Q =  \n",
+              "\\decode.id_ex_regwrite_reg, rval = 1'0).                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2011\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_memwrite, Q = \n", + "\\decode.id_ex_memwrite_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2011 ($dff) from module core (D = \\decode.control_io_memwrite, Q =  \n",
+              "\\decode.id_ex_memwrite_reg, rval = 1'0).                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2010\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_memread, Q = \n", + "\\decode.id_ex_memread_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2010 ($dff) from module core (D = \\decode.control_io_memread, Q =   \n",
+              "\\decode.id_ex_memread_reg, rval = 1'0).                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2009\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_isbranch, Q = \n", + "\\decode.id_ex_isbranch_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2009 ($dff) from module core (D = \\decode.control_io_isbranch, Q =  \n",
+              "\\decode.id_ex_isbranch_reg, rval = 1'0).                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2008\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_immsrc, Q = \n", + "\\decode.id_ex_immsrc_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2008 ($dff) from module core (D = \\decode.control_io_immsrc, Q =    \n",
+              "\\decode.id_ex_immsrc_reg, rval = 1'0).                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2007\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control._io_aluop_T_63, Q \n", + "= \\decode.id_ex_aluop_reg, rval = \u001b[1;36m4\u001b[0m'\u001b[1;36m0000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2007 ($dff) from module core (D = \\decode.control._io_aluop_T_63, Q \n",
+              "= \\decode.id_ex_aluop_reg, rval = 4'0000).                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2006\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\fetch.idPcReg, Q = \n", + "\\decode.id_ex_pc_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2006 ($dff) from module core (D = \\fetch.idPcReg, Q =               \n",
+              "\\decode.id_ex_pc_reg, rval = 0).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2005\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.wfi_out, Q = \n", + "\\decode.wfi_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2005 ($dff) from module core (D = \\decode.wfi_out, Q =              \n",
+              "\\decode.wfi_out_reg, rval = 1'0).                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2004\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.mret_out, Q = \n", + "\\decode.mret_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2004 ($dff) from module core (D = \\decode.mret_out, Q =             \n",
+              "\\decode.mret_out_reg, rval = 1'0).                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2003\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\decode.$procmux$1614_Y, Q\n", + "= \\decode.exception_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2003 ($dff) from module core (D = $flatten\\decode.$procmux$1614_Y, Q\n",
+              "= \\decode.exception_out_reg, rval = 1'0).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2002\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.ecause_out, Q = \n", + "\\decode.ecause_out_reg \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m, rval = \u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2002 ($dff) from module core (D = \\decode.ecause_out, Q =           \n",
+              "\\decode.ecause_out_reg [1:0], rval = 2'00).                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2001\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m31:20\u001b[0m\u001b[1m]\u001b[0m, Q = \n", + "\\decode.csr_address_reg, rval = \u001b[1;36m12\u001b[0m'\u001b[1;36m000000000000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2001 ($dff) from module core (D = \\fetch.instReg [31:20], Q =       \n",
+              "\\decode.csr_address_reg, rval = 12'000000000000).                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2000\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.csrInst, Q = \n", + "\\decode.csr_write_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$2000 ($dff) from module core (D = \\decode.csrInst, Q =              \n",
+              "\\decode.csr_write_reg, rval = 1'0).                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m1999\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.csrInst, Q = \n", + "\\decode.csr_read_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\decode.$procdff$1999 ($dff) from module core (D = \\decode.csrInst, Q =              \n",
+              "\\decode.csr_read_reg, rval = 1'0).                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1959\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "$flatten\\csr.$ge$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2783\u001b[0m$1061_Y, Q = \\csr.mtip, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1959 ($dff) from module core (D =                                      \n",
+              "$flatten\\csr.$ge$/content/core.v:2783$1061_Y, Q = \\csr.mtip, rval = 1'0).                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1958\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1206_Y, Q = \n", + "\\csr.mtie, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1958 ($dff) from module core (D = $flatten\\csr.$procmux$1206_Y, Q =    \n",
+              "\\csr.mtie, rval = 1'0).                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2419\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory.csr_write_data_out_reg \u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m, Q \n", + "= \\csr.mtie\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2419 ($sdff) from module core (D = \\memory.csr_write_data_out_reg [7], Q \n",
+              "= \\csr.mtie).                                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1957\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1215_Y, Q = \n", + "\\csr.msip, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1957 ($dff) from module core (D = $flatten\\csr.$procmux$1215_Y, Q =    \n",
+              "\\csr.msip, rval = 1'0).                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2427\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory.csr_write_data_out_reg \u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m, Q \n", + "= \\csr.msip\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2427 ($sdff) from module core (D = \\memory.csr_write_data_out_reg [3], Q \n",
+              "= \\csr.msip).                                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1956\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1224_Y, Q = \n", + "\\csr.msie, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1956 ($dff) from module core (D = $flatten\\csr.$procmux$1224_Y, Q =    \n",
+              "\\csr.msie, rval = 1'0).                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2433\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory.csr_write_data_out_reg \u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m, Q \n", + "= \\csr.msie\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2433 ($sdff) from module core (D = \\memory.csr_write_data_out_reg [3], Q \n",
+              "= \\csr.msie).                                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1955\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1233_Y, Q = \n", + "\\csr.meie, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1955 ($dff) from module core (D = $flatten\\csr.$procmux$1233_Y, Q =    \n",
+              "\\csr.meie, rval = 1'0).                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2441\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory.csr_write_data_out_reg \u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m, Q\n", + "= \\csr.meie\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2441 ($sdff) from module core (D = \\memory.csr_write_data_out_reg [11], Q\n",
+              "= \\csr.meie).                                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1954\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1128_Y, Q = \n", + "\\csr.ie, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1954 ($dff) from module core (D = $flatten\\csr.$procmux$1128_Y, Q =    \n",
+              "\\csr.ie, rval = 1'0).                                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1953\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1137_Y, Q = \n", + "\\csr.pie, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1953 ($dff) from module core (D = $flatten\\csr.$procmux$1137_Y, Q =    \n",
+              "\\csr.pie, rval = 1'0).                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1952\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1149_Y, Q = \n", + "\\csr.minterrupt, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1952 ($dff) from module core (D = $flatten\\csr.$procmux$1149_Y, Q =    \n",
+              "\\csr.minterrupt, rval = 1'0).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1951\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1161_Y, Q = \n", + "\\csr.mcause, rval = \u001b[1;36m4\u001b[0m'\u001b[1;36m0000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1951 ($dff) from module core (D = $flatten\\csr.$procmux$1161_Y, Q =    \n",
+              "\\csr.mcause, rval = 4'0000).                                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1950\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1242_Y, Q = \n", + "\\csr.mtvec, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1950 ($dff) from module core (D = $flatten\\csr.$procmux$1242_Y, Q =    \n",
+              "\\csr.mtvec, rval = 0).                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2453\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \u001b[1m{\u001b[0m \\memory.csr_write_data_out_reg \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:2\u001b[0m\u001b[1m]\u001b[0m \u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m \u001b[1m}\u001b[0m, Q = \\csr.mtvec\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2453 ($sdff) from module core (D = { \\memory.csr_write_data_out_reg      \n",
+              "[31:2] 2'00 }, Q = \\csr.mtvec).                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1949\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1251_Y, Q = \n", + "\\csr.mscratch, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1949 ($dff) from module core (D = $flatten\\csr.$procmux$1251_Y, Q =    \n",
+              "\\csr.mscratch, rval = 0).                                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2463\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\memory.csr_write_data_out_reg, Q = \n", + "\\csr.mscratch\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2463 ($sdff) from module core (D = \\memory.csr_write_data_out_reg, Q =   \n",
+              "\\csr.mscratch).                                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1948\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1173_Y, Q = \n", + "\\csr.mepc, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1948 ($dff) from module core (D = $flatten\\csr.$procmux$1173_Y, Q =    \n",
+              "\\csr.mepc, rval = 0).                                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1947\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1185_Y, Q = \n", + "\\csr.minstret, rval = \u001b[1;36m64\u001b[0m'\u001b[1;36m0000000000000000000000000000000000000000000000000000000000000000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1947 ($dff) from module core (D = $flatten\\csr.$procmux$1185_Y, Q =    \n",
+              "\\csr.minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $flatten\\csr.$procdff$\u001b[1;36m1946\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1197_Y, Q = \n", + "\\csr.mcycle, rval = \u001b[1;36m64\u001b[0m'\u001b[1;36m0000000000000000000000000000000000000000000000000000000000000000\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $flatten\\csr.$procdff$1946 ($dff) from module core (D = $flatten\\csr.$procmux$1197_Y, Q =    \n",
+              "\\csr.mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Setting constant \u001b[1;36m0\u001b[0m-bit at position \u001b[1;36m0\u001b[0m on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2454\u001b[0m \u001b[1m(\u001b[0m$sdffe\u001b[1m)\u001b[0m from module core. \n" + ], + "text/html": [ + "
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2454 ($sdffe) from module core.                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Setting constant \u001b[1;36m0\u001b[0m-bit at position \u001b[1;36m1\u001b[0m on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2454\u001b[0m \u001b[1m(\u001b[0m$sdffe\u001b[1m)\u001b[0m from module core. \n" + ], + "text/html": [ + "
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2454 ($sdffe) from module core.                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m25.7\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
25.7. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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Removed 274 unused cells and 278 unused wires.                                                                     \n",
+              "
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<suppressed ~296 debug messages>                                                                                   \n",
+              "
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+              "
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25.8. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing module core. \n" + ], + "text/html": [ + "
Optimizing module core.                                                                                            \n",
+              "
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+              "
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25.9. Rerunning OPT passes. (Maybe there is more to do..)                                                          \n",
+              "
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+              "
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25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
+              "
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Evaluating internal representation of mux trees.                                                                   \n",
+              "
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Analyzing evaluation results.                                                                                      \n",
+              "
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Removed 0 multiplexer ports.                                                                                       \n",
+              "
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<suppressed ~63 debug messages>                                                                                    \n",
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25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
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Performed a total of 0 changes.                                                                                    \n",
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+              "
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25.12. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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<suppressed ~192 debug messages>                                                                                   \n",
+              "
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Removed a total of 64 cells.                                                                                       \n",
+              "
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+              "
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25.13. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
+              "
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+              "
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25.14. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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Removed 0 unused cells and 64 unused wires.                                                                        \n",
+              "
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<suppressed ~1 debug messages>                                                                                     \n",
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25.15. Executing OPT_EXPR pass (perform const folding).                                                            \n",
+              "
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Optimizing module core.                                                                                            \n",
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+              "
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25.16. Rerunning OPT passes. (Maybe there is more to do..)                                                         \n",
+              "
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+              "
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25.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
+              "
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Evaluating internal representation of mux trees.                                                                   \n",
+              "
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Analyzing evaluation results.                                                                                      \n",
+              "
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Removed 0 multiplexer ports.                                                                                       \n",
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<suppressed ~63 debug messages>                                                                                    \n",
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25.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
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Performed a total of 0 changes.                                                                                    \n",
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25.19. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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Removed a total of 0 cells.                                                                                        \n",
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25.20. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
+              "
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25.21. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
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25.22. Executing OPT_EXPR pass (perform const folding).                                                            \n",
+              "
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Optimizing module core.                                                                                            \n",
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25.23. Finished OPT passes. (There is nothing left to do.)                                                         \n",
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26. Executing WREDUCE pass (reducing word size of cells).                                                          \n",
+              "
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Removed top 1 bits (of 2) from port B of cell core.$flatten\\fetch.\\btb.$gt$/content/core.v:164$33 ($gt).           \n",
+              "
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Removed top 1 bits (of 2) from port B of cell core.$flatten\\fetch.\\btb.$add$/content/core.v:183$46 ($add).         \n",
+              "
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Removed top 1 bits (of 2) from port B of cell core.$flatten\\fetch.\\btb.$sub$/content/core.v:187$48 ($sub).         \n",
+              "
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Removed top 27 bits (of 32) from mux cell core.$flatten\\fetch.$procmux$1888 ($mux).                                \n",
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Removed top 27 bits (of 32) from mux cell core.$flatten\\fetch.$procmux$1885 ($mux).                                \n",
+              "
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Removed top 29 bits (of 32) from port B of cell core.$flatten\\fetch.$add$/content/core.v:289$65 ($add).            \n",
+              "
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Removed top 1 bits (of 3) from port A of cell core.$flatten\\decode.\\immGen.$eq$/content/core.v:989$518 ($eq).      \n",
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Removed top 1 bits (of 3) from port A of cell core.$flatten\\decode.\\immGen.$eq$/content/core.v:990$520 ($eq).      \n",
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Removed top 2 bits (of 3) from port A of cell core.$flatten\\decode.\\immGen.$eq$/content/core.v:991$522 ($eq).      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m566\u001b[0m$\u001b[1;36m266\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:566$266 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m567\u001b[0m$\u001b[1;36m268\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:567$268 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m568\u001b[0m$\u001b[1;36m270\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:568$270 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m569\u001b[0m$\u001b[1;36m272\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:569$272 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m570\u001b[0m$\u001b[1;36m274\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:570$274 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m571\u001b[0m$\u001b[1;36m276\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:571$276 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m572\u001b[0m$\u001b[1;36m278\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:572$278 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m573\u001b[0m$\u001b[1;36m280\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:573$280 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m574\u001b[0m$\u001b[1;36m282\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:574$282 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m575\u001b[0m$\u001b[1;36m284\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:575$284 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m576\u001b[0m$\u001b[1;36m286\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:576$286 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m577\u001b[0m$\u001b[1;36m288\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:577$288 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m578\u001b[0m$\u001b[1;36m290\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:578$290 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m579\u001b[0m$\u001b[1;36m292\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:579$292 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m4\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m596\u001b[0m$\u001b[1;36m326\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 4 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:596$326 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m597\u001b[0m$\u001b[1;36m328\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:597$328 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m598\u001b[0m$\u001b[1;36m330\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:598$330 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m599\u001b[0m$\u001b[1;36m332\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:599$332 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m600\u001b[0m$\u001b[1;36m334\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:600$334 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m601\u001b[0m$\u001b[1;36m336\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:601$336 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m602\u001b[0m$\u001b[1;36m338\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:602$338 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m603\u001b[0m$\u001b[1;36m340\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:603$340 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m604\u001b[0m$\u001b[1;36m342\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:604$342 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m605\u001b[0m$\u001b[1;36m344\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:605$344 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m606\u001b[0m$\u001b[1;36m346\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:606$346 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m607\u001b[0m$\u001b[1;36m348\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:607$348 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m608\u001b[0m$\u001b[1;36m350\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:608$350 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m609\u001b[0m$\u001b[1;36m352\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:609$352 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m610\u001b[0m$\u001b[1;36m354\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:610$354 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m4\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m640\u001b[0m$\u001b[1;36m398\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 4 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:640$398 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m647\u001b[0m$\u001b[1;36m401\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:647$401 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m654\u001b[0m$\u001b[1;36m404\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:654$404 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m661\u001b[0m$\u001b[1;36m407\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:661$407 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m668\u001b[0m$\u001b[1;36m410\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:668$410 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m675\u001b[0m$\u001b[1;36m413\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:675$413 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m682\u001b[0m$\u001b[1;36m416\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:682$416 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m689\u001b[0m$\u001b[1;36m419\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:689$419 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m696\u001b[0m$\u001b[1;36m422\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:696$422 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m703\u001b[0m$\u001b[1;36m425\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:703$425 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m710\u001b[0m$\u001b[1;36m428\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:710$428 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m717\u001b[0m$\u001b[1;36m431\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:717$431 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m724\u001b[0m$\u001b[1;36m434\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:724$434 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m731\u001b[0m$\u001b[1;36m437\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:731$437 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m738\u001b[0m$\u001b[1;36m440\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:738$440 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m418\u001b[0m$\u001b[1;36m76\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 7) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:418$76 ($eq).      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m419\u001b[0m$\u001b[1;36m79\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 3) from mux cell core.$flatten\\decode.\\control.$ternary$/content/core.v:419$79 ($mux).      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m423\u001b[0m$\u001b[1;36m86\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 3) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:423$86 ($eq).      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m425\u001b[0m$\u001b[1;36m90\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 3) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:425$90 ($eq).      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m426\u001b[0m$\u001b[1;36m92\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 3) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:426$92 ($eq).      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m434\u001b[0m$\u001b[1;36m109\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 4) from mux cell core.$flatten\\decode.\\control.$ternary$/content/core.v:434$109 ($mux).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m435\u001b[0m$\u001b[1;36m111\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 4) from mux cell core.$flatten\\decode.\\control.$ternary$/content/core.v:435$111 ($mux).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m436\u001b[0m$\u001b[1;36m112\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 7) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:436$112 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m437\u001b[0m$\u001b[1;36m114\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 7) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:437$114 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m5\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m438\u001b[0m$\u001b[1;36m116\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 5 bits (of 7) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:438$116 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m439\u001b[0m$\u001b[1;36m118\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 7) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:439$118 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m443\u001b[0m$\u001b[1;36m126\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 7) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:443$126 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m464\u001b[0m$\u001b[1;36m192\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 7) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:464$192 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed cell core.$flatten\\decode.$procmux$\u001b[1;36m1623\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed cell core.$flatten\\decode.$procmux$1623 ($mux).                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m4\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m5\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\regfile.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m565\u001b[0m$\u001b[1;36m264\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 4 bits (of 5) from port A of cell core.$flatten\\decode.\\regfile.$eq$/content/core.v:565$264 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m4\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\decode.\\control.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m418\u001b[0m$\u001b[1;36m75\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 4 bits (of 7) from port A of cell core.$flatten\\decode.\\control.$eq$/content/core.v:418$75 ($eq).      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed cell core.$flatten\\decode.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1204\u001b[0m$\u001b[1;36m674\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed cell core.$flatten\\decode.$ternary$/content/core.v:1204$674 ($mux).                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1189\u001b[0m$\u001b[1;36m625\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1189$625 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1188\u001b[0m$\u001b[1;36m623\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1188$623 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m6\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1187\u001b[0m$\u001b[1;36m621\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 6 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1187$621 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1184\u001b[0m$\u001b[1;36m617\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1184$617 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1183\u001b[0m$\u001b[1;36m616\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1183$616 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1170\u001b[0m$\u001b[1;36m600\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1170$600 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m5\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1164\u001b[0m$\u001b[1;36m593\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 5 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1164$593 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1152\u001b[0m$\u001b[1;36m577\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1152$577 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m4\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1143\u001b[0m$\u001b[1;36m561\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 4 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1143$561 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1141\u001b[0m$\u001b[1;36m558\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1141$558 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m7\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1136\u001b[0m$\u001b[1;36m547\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 7) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1136$547 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m32\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1135\u001b[0m$\u001b[1;36m546\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 32) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1135$546 ($eq).            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m32\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1134\u001b[0m$\u001b[1;36m545\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 32) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1134$545 ($eq).            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1126\u001b[0m$\u001b[1;36m533\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 3) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1126$533 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1124\u001b[0m$\u001b[1;36m530\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 3) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1124$530 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\decode.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1122\u001b[0m$\u001b[1;36m527\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 3) from port B of cell core.$flatten\\decode.$eq$/content/core.v:1122$527 ($eq).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m29\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m32\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\execute.\\targetGen.$add$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1652\u001b[0m$\u001b[1;36m730\u001b[0m \n", + "\u001b[1m(\u001b[0m$add\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 29 bits (of 32) from port B of cell core.$flatten\\execute.\\targetGen.$add$/content/core.v:1652$730     \n",
+              "($add).                                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m31\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m63\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.\\alu.$shl$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1624\u001b[0m$\u001b[1;36m703\u001b[0m \u001b[1m(\u001b[0m$shl\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 31 bits (of 63) from port A of cell core.$flatten\\execute.\\alu.$shl$/content/core.v:1624$703 ($shl).   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m3\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1630\u001b[0m$\u001b[1;36m710\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 3 bits (of 4) from port A of cell core.$flatten\\execute.\\alu.$eq$/content/core.v:1630$710 ($eq).       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1631\u001b[0m$\u001b[1;36m712\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 4) from port A of cell core.$flatten\\execute.\\alu.$eq$/content/core.v:1631$712 ($eq).       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1632\u001b[0m$\u001b[1;36m714\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 4) from port A of cell core.$flatten\\execute.\\alu.$eq$/content/core.v:1632$714 ($eq).       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1633\u001b[0m$\u001b[1;36m716\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 4) from port A of cell core.$flatten\\execute.\\alu.$eq$/content/core.v:1633$716 ($eq).       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1634\u001b[0m$\u001b[1;36m718\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 4) from port A of cell core.$flatten\\execute.\\alu.$eq$/content/core.v:1634$718 ($eq).       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1635\u001b[0m$\u001b[1;36m720\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 4) from port A of cell core.$flatten\\execute.\\alu.$eq$/content/core.v:1635$720 ($eq).       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1636\u001b[0m$\u001b[1;36m722\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 4) from port A of cell core.$flatten\\execute.\\alu.$eq$/content/core.v:1636$722 ($eq).       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m31\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m63\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\execute.\\alu.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1638\u001b[0m$\u001b[1;36m727\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 31 bits (of 63) from mux cell core.$flatten\\execute.\\alu.$ternary$/content/core.v:1638$727 ($mux).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m2\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\execute.\\aluSelect.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1597\u001b[0m$\u001b[1;36m685\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 2) from port B of cell core.$flatten\\execute.\\aluSelect.$eq$/content/core.v:1597$685 ($eq). \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m2\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\execute.\\aluSelect.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1603\u001b[0m$\u001b[1;36m691\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 2) from port B of cell core.$flatten\\execute.\\aluSelect.$eq$/content/core.v:1603$691 ($eq). \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\execute.$procmux$\u001b[1;36m1455\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 4) from mux cell core.$flatten\\execute.$procmux$1455 ($mux).                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1924\u001b[0m$\u001b[1;36m757\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 3) from port A of cell core.$flatten\\execute.$eq$/content/core.v:1924$757 ($eq).            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\execute.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1792\u001b[0m$\u001b[1;36m740\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 3) from port A of cell core.$flatten\\execute.$eq$/content/core.v:1792$740 ($eq).            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m2\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\writeback.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2484\u001b[0m$\u001b[1;36m828\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 2) from port A of cell core.$flatten\\writeback.$eq$/content/core.v:2484$828 ($eq).          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\memory.\\branch.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2120\u001b[0m$\u001b[1;36m760\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 3) from port B of cell core.$flatten\\memory.\\branch.$eq$/content/core.v:2120$760 ($eq).     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from FF cell core.$auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2114\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 3) from FF cell core.$auto$ff.cc:266:slice$2114 ($sdff).                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\memory.$procmux$\u001b[1;36m1318\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 4) from mux cell core.$flatten\\memory.$procmux$1318 ($mux).                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\memory.$procmux$\u001b[1;36m1315\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 4) from mux cell core.$flatten\\memory.$procmux$1315 ($mux).                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\memory.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2216\u001b[0m$\u001b[1;36m797\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 4) from mux cell core.$flatten\\memory.$ternary$/content/core.v:2216$797 ($mux).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\memory.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2215\u001b[0m$\u001b[1;36m796\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 4) from mux cell core.$flatten\\memory.$ternary$/content/core.v:2215$796 ($mux).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\memory.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2213\u001b[0m$\u001b[1;36m790\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 4) from mux cell core.$flatten\\memory.$ternary$/content/core.v:2213$790 ($mux).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m3\u001b[0m\u001b[1m)\u001b[0m from mux cell core.$flatten\\memory.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2211\u001b[0m$\u001b[1;36m786\u001b[0m \u001b[1m(\u001b[0m$mux\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 3) from mux cell core.$flatten\\memory.$ternary$/content/core.v:2211$786 ($mux).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m4\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$auto$opt_dff.\u001b[1;92mcc:195\u001b[0m:make_patterns_logic$\u001b[1;36m2135\u001b[0m \u001b[1m(\u001b[0m$ne\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 4) from port B of cell core.$auto$opt_dff.cc:195:make_patterns_logic$2135 ($ne).            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m1\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m2\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$auto$opt_dff.\u001b[1;92mcc:195\u001b[0m:make_patterns_logic$\u001b[1;36m2127\u001b[0m \u001b[1m(\u001b[0m$ne\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 1 bits (of 2) from port B of cell core.$auto$opt_dff.cc:195:make_patterns_logic$2127 ($ne).            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m33\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m64\u001b[0m\u001b[1m)\u001b[0m from port B of cell core.$flatten\\csr.$ge$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2783\u001b[0m$\u001b[1;36m1061\u001b[0m \u001b[1m(\u001b[0m$ge\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 33 bits (of 64) from port B of cell core.$flatten\\csr.$ge$/content/core.v:2783$1061 ($ge).             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m12\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\csr.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2644\u001b[0m$\u001b[1;36m1027\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2644$1027 ($eq).              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m12\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\csr.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2642\u001b[0m$\u001b[1;36m1026\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2642$1026 ($eq).              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m12\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\csr.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2620\u001b[0m$\u001b[1;36m987\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2620$987 ($eq).               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed top \u001b[1;36m2\u001b[0m bits \u001b[1m(\u001b[0mof \u001b[1;36m12\u001b[0m\u001b[1m)\u001b[0m from port A of cell core.$flatten\\csr.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2613\u001b[0m$\u001b[1;36m973\u001b[0m \u001b[1m(\u001b[0m$eq\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2613$973 ($eq).               \n",
+              "
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2607$961 ($eq).               \n",
+              "
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2602$951 ($eq).               \n",
+              "
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2598$943 ($eq).               \n",
+              "
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2596$939 ($eq).               \n",
+              "
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Removed top 32 bits (of 64) from port A of cell core.$flatten\\csr.$or$/content/core.v:2592$928 ($or).              \n",
+              "
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Removed top 32 bits (of 64) from port A of cell core.$flatten\\csr.$or$/content/core.v:2591$927 ($or).              \n",
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Removed top 63 bits (of 64) from port B of cell core.$flatten\\csr.$add$/content/core.v:2586$924 ($add).            \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2565$877 ($eq).               \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2563$873 ($eq).               \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2561$869 ($eq).               \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2559$865 ($eq).               \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2557$861 ($eq).               \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2555$857 ($eq).               \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2553$853 ($eq).               \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2551$849 ($eq).               \n",
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Removed top 2 bits (of 12) from port A of cell core.$flatten\\csr.$eq$/content/core.v:2549$845 ($eq).               \n",
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Removed top 29 bits (of 32) from port B of cell core.$flatten\\hazard.$add$/content/core.v:2895$1083 ($add).        \n",
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Removed cell core.$auto$ff.cc:266:slice$2408 ($dff).                                                               \n",
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Removed top 2 bits (of 3) from FF cell core.$auto$ff.cc:266:slice$2199 ($sdff).                                    \n",
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Removed top 31 bits (of 63) from mux cell core.$flatten\\execute.\\alu.$ternary$/content/core.v:1636$723 ($mux).     \n",
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Removed top 31 bits (of 63) from mux cell core.$flatten\\execute.\\alu.$ternary$/content/core.v:1635$721 ($mux).     \n",
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Removed top 31 bits (of 63) from mux cell core.$flatten\\execute.\\alu.$ternary$/content/core.v:1634$719 ($mux).     \n",
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Removed top 31 bits (of 63) from port Y of cell core.$flatten\\execute.\\alu.$shl$/content/core.v:1624$703 ($shl).   \n",
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Removed top 2 bits (of 4) from wire core.$flatten\\execute.$procmux$1455_Y.                                         \n",
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Removed top 27 bits (of 32) from wire core.$flatten\\fetch.$procmux$1885_Y.                                         \n",
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Removed top 27 bits (of 32) from wire core.$flatten\\fetch.$procmux$1888_Y.                                         \n",
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Removed top 1 bits (of 4) from wire core.$flatten\\memory.$procmux$1315_Y.                                          \n",
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Removed top 2 bits (of 4) from wire core.$flatten\\memory.$procmux$1318_Y.                                          \n",
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Removed top 2 bits (of 4) from wire core.decode_io_ecause_out.                                                     \n",
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Removed top 2 bits (of 4) from wire core.execute_io_ecause_in.                                                     \n",
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Removed top 2 bits (of 4) from wire core.execute_io_ecause_out.                                                    \n",
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Removed top 2 bits (of 4) from wire core.memory_io_ecause_in.                                                      \n",
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27. Executing PEEPOPT pass (run peephole optimizers).                                                              \n",
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28. Executing OPT_CLEAN pass (remove unused cells and wires).                                                      \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
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Removed 0 unused cells and 10 unused wires.                                                                        \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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29. Executing ALUMACC pass (create $alu and $macc cells).                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting $alu and $macc cells in module core: \n" + ], + "text/html": [ + "
Extracting $alu and $macc cells in module core:                                                                    \n",
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+              "$auto$alumacc.cc:485:replace_alu$2554                                                                              \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "creating $alu cell for $flatten\\execute.\\targetGen.$add$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1652\u001b[0m$\u001b[1;36m730\u001b[0m: \n", + "$auto$alumacc.\u001b[1;92mcc:485\u001b[0m:replace_alu$\u001b[1;36m2557\u001b[0m \n" + ], + "text/html": [ + "
creating $alu cell for $flatten\\execute.\\targetGen.$add$/content/core.v:1652$730:                                  \n",
+              "$auto$alumacc.cc:485:replace_alu$2557                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "creating $alu cell for $flatten\\fetch.$add$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m289\u001b[0m$\u001b[1;36m65\u001b[0m: $auto$alumacc.\u001b[1;92mcc:485\u001b[0m:replace_alu$\u001b[1;36m2560\u001b[0m \n" + ], + "text/html": [ + "
creating $alu cell for $flatten\\fetch.$add$/content/core.v:289$65: $auto$alumacc.cc:485:replace_alu$2560           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "creating $alu cell for $flatten\\fetch.\\btb.$add$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m183\u001b[0m$\u001b[1;36m46\u001b[0m: $auto$alumacc.\u001b[1;92mcc:485\u001b[0m:replace_alu$\u001b[1;36m2563\u001b[0m \n" + ], + "text/html": [ + "
creating $alu cell for $flatten\\fetch.\\btb.$add$/content/core.v:183$46: $auto$alumacc.cc:485:replace_alu$2563      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "creating $alu cell for $flatten\\fetch.\\btb.$sub$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m187\u001b[0m$\u001b[1;36m48\u001b[0m: $auto$alumacc.\u001b[1;92mcc:485\u001b[0m:replace_alu$\u001b[1;36m2566\u001b[0m \n" + ], + "text/html": [ + "
creating $alu cell for $flatten\\fetch.\\btb.$sub$/content/core.v:187$48: $auto$alumacc.cc:485:replace_alu$2566      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "creating $alu cell for $flatten\\hazard.$add$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2895\u001b[0m$\u001b[1;36m1083\u001b[0m: $auto$alumacc.\u001b[1;92mcc:485\u001b[0m:replace_alu$\u001b[1;36m2569\u001b[0m \n" + ], + "text/html": [ + "
creating $alu cell for $flatten\\hazard.$add$/content/core.v:2895$1083: $auto$alumacc.cc:485:replace_alu$2569       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created \u001b[1;36m15\u001b[0m $alu and \u001b[1;36m0\u001b[0m $macc cells. \n" + ], + "text/html": [ + "
created 15 $alu and 0 $macc cells.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m30\u001b[0m. Executing SHARE pass \u001b[1m(\u001b[0mSAT-based resource sharing\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
30. Executing SHARE pass (SAT-based resource sharing).                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found \u001b[1;36m7\u001b[0m cells in module core that may be considered for resource sharing. \n" + ], + "text/html": [ + "
Found 7 cells in module core that may be considered for resource sharing.                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing resource sharing options for $flatten\\fetch.\\btb.$memrd$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m170\u001b[0m$\u001b[1;36m37\u001b[0m \u001b[1m(\u001b[0m$memrd\u001b[1m)\u001b[0m: \n" + ], + "text/html": [ + "
Analyzing resource sharing options for $flatten\\fetch.\\btb.$memrd$\\btbTable$/content/core.v:170$37 ($memrd):       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n", + "$flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m330\u001b[0m$72_Y \u001b[1m}\u001b[0m. \n" + ], + "text/html": [ + "
Found 1 activation_patterns using ctrl signal { \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall     \n",
+              "$flatten\\fetch.$and$/content/core.v:330$72_Y }.                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "No candidates found. \n" + ], + "text/html": [ + "
No candidates found.                                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_valid$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m49\u001b[0m$\u001b[1;36m5\u001b[0m \u001b[1m(\u001b[0m$memrd\u001b[1m)\u001b[0m: \n" + ], + "text/html": [ + "
Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_valid$/content/core.v:49$5 ($memrd):   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n", + "$flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m330\u001b[0m$72_Y \u001b[1m}\u001b[0m. \n" + ], + "text/html": [ + "
Found 1 activation_patterns using ctrl signal { \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall     \n",
+              "$flatten\\fetch.$and$/content/core.v:330$72_Y }.                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "No candidates found. \n" + ], + "text/html": [ + "
No candidates found.                                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_target_pc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m56\u001b[0m$\u001b[1;36m6\u001b[0m \n", + "\u001b[1m(\u001b[0m$memrd\u001b[1m)\u001b[0m: \n" + ], + "text/html": [ + "
Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_target_pc$/content/core.v:56$6         \n",
+              "($memrd):                                                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n", + "$flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m290\u001b[0m$67_Y $flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m330\u001b[0m$72_Y \u001b[1m}\u001b[0m. \n" + ], + "text/html": [ + "
Found 1 activation_patterns using ctrl signal { \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall     \n",
+              "$flatten\\fetch.$and$/content/core.v:290$67_Y $flatten\\fetch.$and$/content/core.v:330$72_Y }.                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "No candidates found. \n" + ], + "text/html": [ + "
No candidates found.                                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_tag$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m42\u001b[0m$\u001b[1;36m4\u001b[0m \u001b[1m(\u001b[0m$memrd\u001b[1m)\u001b[0m: \n" + ], + "text/html": [ + "
Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_tag$/content/core.v:42$4 ($memrd):     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n", + "$flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m330\u001b[0m$72_Y \u001b[1m}\u001b[0m. \n" + ], + "text/html": [ + "
Found 1 activation_patterns using ctrl signal { \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall     \n",
+              "$flatten\\fetch.$and$/content/core.v:330$72_Y }.                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "No candidates found. \n" + ], + "text/html": [ + "
No candidates found.                                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing resource sharing options for $flatten\\execute.\\alu.$sshr$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1626\u001b[0m$\u001b[1;36m705\u001b[0m \u001b[1m(\u001b[0m$sshr\u001b[1m)\u001b[0m: \n" + ], + "text/html": [ + "
Analyzing resource sharing options for $flatten\\execute.\\alu.$sshr$/content/core.v:1626$705 ($sshr):               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1638\u001b[0m$726_Y \n", + "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1637\u001b[0m$724_Y $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1636\u001b[0m$722_Y \u001b[1m}\u001b[0m. \n" + ], + "text/html": [ + "
Found 1 activation_patterns using ctrl signal { $flatten\\execute.\\alu.$eq$/content/core.v:1638$726_Y               \n",
+              "$flatten\\execute.\\alu.$eq$/content/core.v:1637$724_Y $flatten\\execute.\\alu.$eq$/content/core.v:1636$722_Y }.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "No candidates found. \n" + ], + "text/html": [ + "
No candidates found.                                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing resource sharing options for $flatten\\execute.\\alu.$shr$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1625\u001b[0m$\u001b[1;36m704\u001b[0m \u001b[1m(\u001b[0m$shr\u001b[1m)\u001b[0m: \n" + ], + "text/html": [ + "
Analyzing resource sharing options for $flatten\\execute.\\alu.$shr$/content/core.v:1625$704 ($shr):                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1638\u001b[0m$726_Y \n", + "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1637\u001b[0m$724_Y $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1636\u001b[0m$722_Y \n", + "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1635\u001b[0m$720_Y \u001b[1m}\u001b[0m. \n" + ], + "text/html": [ + "
Found 1 activation_patterns using ctrl signal { $flatten\\execute.\\alu.$eq$/content/core.v:1638$726_Y               \n",
+              "$flatten\\execute.\\alu.$eq$/content/core.v:1637$724_Y $flatten\\execute.\\alu.$eq$/content/core.v:1636$722_Y          \n",
+              "$flatten\\execute.\\alu.$eq$/content/core.v:1635$720_Y }.                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "No candidates found. \n" + ], + "text/html": [ + "
No candidates found.                                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing resource sharing options for $flatten\\execute.\\alu.$shl$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1624\u001b[0m$\u001b[1;36m703\u001b[0m \u001b[1m(\u001b[0m$shl\u001b[1m)\u001b[0m: \n" + ], + "text/html": [ + "
Analyzing resource sharing options for $flatten\\execute.\\alu.$shl$/content/core.v:1624$703 ($shl):                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1638\u001b[0m$726_Y \n", + "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1637\u001b[0m$724_Y $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1636\u001b[0m$722_Y \n", + "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1635\u001b[0m$720_Y $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1634\u001b[0m$718_Y \u001b[1m}\u001b[0m. \n" + ], + "text/html": [ + "
Found 1 activation_patterns using ctrl signal { $flatten\\execute.\\alu.$eq$/content/core.v:1638$726_Y               \n",
+              "$flatten\\execute.\\alu.$eq$/content/core.v:1637$724_Y $flatten\\execute.\\alu.$eq$/content/core.v:1636$722_Y          \n",
+              "$flatten\\execute.\\alu.$eq$/content/core.v:1635$720_Y $flatten\\execute.\\alu.$eq$/content/core.v:1634$718_Y }.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "No candidates found. \n" + ], + "text/html": [ + "
No candidates found.                                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m31\u001b[0m. Executing OPT pass \u001b[1m(\u001b[0mperforming simple optimizations\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
31. Executing OPT pass (performing simple optimizations).                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m31.1\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
31.1. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing module core. \n" + ], + "text/html": [ + "
Optimizing module core.                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m31.2\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
31.2. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding identical cells in module `\\core'. \n" + ], + "text/html": [ + "
Finding identical cells in module `\\core'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed a total of \u001b[1;36m0\u001b[0m cells. \n" + ], + "text/html": [ + "
Removed a total of 0 cells.                                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m31.3\u001b[0m. Executing OPT_MUXTREE pass \u001b[1m(\u001b[0mdetect dead branches in mux trees\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
31.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Running muxtree optimizer on module \\core.. \n" + ], + "text/html": [ + "
Running muxtree optimizer on module \\core..                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating internal representation of mux trees. \n" + ], + "text/html": [ + "
Creating internal representation of mux trees.                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Evaluating internal representation of mux trees. \n" + ], + "text/html": [ + "
Evaluating internal representation of mux trees.                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing evaluation results. \n" + ], + "text/html": [ + "
Analyzing evaluation results.                                                                                      \n",
+              "
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Removed 0 multiplexer ports.                                                                                       \n",
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<suppressed ~62 debug messages>                                                                                    \n",
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31.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                          \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
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Performed a total of 0 changes.                                                                                    \n",
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31.5. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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Removed a total of 0 cells.                                                                                        \n",
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31.6. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
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Adding SRST signal on $auto$ff.cc:266:slice$2390 ($sdff) from module core (D = \\decode.control._io_aluop_T_57      \n",
+              "[2:1], Q = \\decode.id_ex_aluop_reg [2:1], rval = 2'00).                                                            \n",
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31.7. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
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Removed 0 unused cells and 6 unused wires.                                                                         \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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31.8. Executing OPT_EXPR pass (perform const folding).                                                             \n",
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Optimizing module core.                                                                                            \n",
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31.9. Rerunning OPT passes. (Maybe there is more to do..)                                                          \n",
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31.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
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Evaluating internal representation of mux trees.                                                                   \n",
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Analyzing evaluation results.                                                                                      \n",
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Removed 0 multiplexer ports.                                                                                       \n",
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<suppressed ~63 debug messages>                                                                                    \n",
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31.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
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New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2574: { \\decode.io_id_ex_flush            \n",
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Optimizing cells in module \\core.                                                                                  \n",
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Performed a total of 1 changes.                                                                                    \n",
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31.12. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
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Finding identical cells in module `\\core'.                                                                         \n",
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Removed a total of 0 cells.                                                                                        \n",
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31.13. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
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31.14. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
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Finding unused cells or wires in module \\core..                                                                    \n",
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31.15. Executing OPT_EXPR pass (perform const folding).                                                            \n",
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Optimizing module core.                                                                                            \n",
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31.16. Rerunning OPT passes. (Maybe there is more to do..)                                                         \n",
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31.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
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Running muxtree optimizer on module \\core..                                                                        \n",
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Creating internal representation of mux trees.                                                                     \n",
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Evaluating internal representation of mux trees.                                                                   \n",
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Analyzing evaluation results.                                                                                      \n",
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Removed 0 multiplexer ports.                                                                                       \n",
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<suppressed ~63 debug messages>                                                                                    \n",
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31.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
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31.19. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
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Finding identical cells in module `\\core'.                                                                         \n",
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Removed a total of 0 cells.                                                                                        \n",
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31.20. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m31.21\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
31.21. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding unused cells or wires in module \\core.. \n" + ], + "text/html": [ + "
Finding unused cells or wires in module \\core..                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m31.22\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
31.22. Executing OPT_EXPR pass (perform const folding).                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing module core. \n" + ], + "text/html": [ + "
Optimizing module core.                                                                                            \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m31.23\u001b[0m. Finished OPT passes. \u001b[1m(\u001b[0mThere is nothing left to do.\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
31.23. Finished OPT passes. (There is nothing left to do.)                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32\u001b[0m. Executing MEMORY pass. \n" + ], + "text/html": [ + "
32. Executing MEMORY pass.                                                                                         \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.1\u001b[0m. Executing OPT_MEM pass \u001b[1m(\u001b[0moptimize memories\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.1. Executing OPT_MEM pass (optimize memories).                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Performed a total of \u001b[1;36m0\u001b[0m transformations. \n" + ], + "text/html": [ + "
Performed a total of 0 transformations.                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.2\u001b[0m. Executing OPT_MEM_PRIORITY pass \u001b[1m(\u001b[0mremoving unnecessary memory write priority relations\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Performed a total of \u001b[1;36m1\u001b[0m transformations. \n" + ], + "text/html": [ + "
Performed a total of 1 transformations.                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.3\u001b[0m. Executing OPT_MEM_FEEDBACK pass \u001b[1m(\u001b[0mfinding memory read-to-write feedback paths\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing core.fetch.bht.bhtTable_tag write port \u001b[1;36m0\u001b[0m. \n" + ], + "text/html": [ + "
Analyzing core.fetch.bht.bhtTable_tag write port 0.                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing core.fetch.bht.bhtTable_target_pc write port \u001b[1;36m0\u001b[0m. \n" + ], + "text/html": [ + "
Analyzing core.fetch.bht.bhtTable_target_pc write port 0.                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing core.fetch.bht.bhtTable_valid write port \u001b[1;36m0\u001b[0m. \n" + ], + "text/html": [ + "
Analyzing core.fetch.bht.bhtTable_valid write port 0.                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing core.fetch.btb.btbTable write port \u001b[1;36m0\u001b[0m. \n" + ], + "text/html": [ + "
Analyzing core.fetch.btb.btbTable write port 0.                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Analyzing core.fetch.btb.btbTable write port \u001b[1;36m1\u001b[0m. \n" + ], + "text/html": [ + "
Analyzing core.fetch.btb.btbTable write port 1.                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.4\u001b[0m. Executing MEMORY_BMUX2ROM pass \u001b[1m(\u001b[0mconverting muxes to ROMs\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.5\u001b[0m. Executing MEMORY_DFF pass \u001b[1m(\u001b[0mmerging $dff cells to $memrd\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port `\\fetch.bht.bhtTable_tag'\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m in module `\\core': no output FF found. \n" + ], + "text/html": [ + "
Checking read port `\\fetch.bht.bhtTable_tag'[0] in module `\\core': no output FF found.                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port `\\fetch.bht.bhtTable_target_pc'\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m in module `\\core': FF found, but with a mux select that \n", + "doesn't seem to correspond to transparency logic. \n" + ], + "text/html": [ + "
Checking read port `\\fetch.bht.bhtTable_target_pc'[0] in module `\\core': FF found, but with a mux select that      \n",
+              "doesn't seem to correspond to transparency logic.                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port `\\fetch.bht.bhtTable_valid'\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m in module `\\core': no output FF found. \n" + ], + "text/html": [ + "
Checking read port `\\fetch.bht.bhtTable_valid'[0] in module `\\core': no output FF found.                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port `\\fetch.btb.btbTable'\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m in module `\\core': no output FF found. \n" + ], + "text/html": [ + "
Checking read port `\\fetch.btb.btbTable'[0] in module `\\core': no output FF found.                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port `\\fetch.btb.btbTable'\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m in module `\\core': no output FF found. \n" + ], + "text/html": [ + "
Checking read port `\\fetch.btb.btbTable'[1] in module `\\core': no output FF found.                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port address `\\fetch.bht.bhtTable_tag'\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m in module `\\core': merged address FF to cell. \n" + ], + "text/html": [ + "
Checking read port address `\\fetch.bht.bhtTable_tag'[0] in module `\\core': merged address FF to cell.              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port address `\\fetch.bht.bhtTable_target_pc'\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m in module `\\core': merged address FF to cell. \n" + ], + "text/html": [ + "
Checking read port address `\\fetch.bht.bhtTable_target_pc'[0] in module `\\core': merged address FF to cell.        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port address `\\fetch.bht.bhtTable_valid'\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m in module `\\core': merged address FF to cell. \n" + ], + "text/html": [ + "
Checking read port address `\\fetch.bht.bhtTable_valid'[0] in module `\\core': merged address FF to cell.            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port address `\\fetch.btb.btbTable'\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m in module `\\core': merged address FF to cell. \n" + ], + "text/html": [ + "
Checking read port address `\\fetch.btb.btbTable'[0] in module `\\core': merged address FF to cell.                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Checking read port address `\\fetch.btb.btbTable'\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m in module `\\core': merged address FF to cell. \n" + ], + "text/html": [ + "
Checking read port address `\\fetch.btb.btbTable'[1] in module `\\core': merged address FF to cell.                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.6\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.6. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding unused cells or wires in module \\core.. \n" + ], + "text/html": [ + "
Finding unused cells or wires in module \\core..                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.7\u001b[0m. Executing MEMORY_SHARE pass \u001b[1m(\u001b[0mconsolidating $memrd/$memwr cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidating read ports of memory core.fetch.btb.btbTable by address: \n" + ], + "text/html": [ + "
Consolidating read ports of memory core.fetch.btb.btbTable by address:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidating write ports of memory core.fetch.btb.btbTable by address: \n" + ], + "text/html": [ + "
Consolidating write ports of memory core.fetch.btb.btbTable by address:                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Merging ports \u001b[1;36m0\u001b[0m, \u001b[1;36m1\u001b[0m \u001b[1m(\u001b[0maddress \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m5:2\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Merging ports 0, 1 (address \\execute.mem_pc_reg [5:2]).                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.8\u001b[0m. Executing OPT_MEM_WIDEN pass \u001b[1m(\u001b[0moptimize memories where all ports are wide\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Performed a total of \u001b[1;36m0\u001b[0m transformations. \n" + ], + "text/html": [ + "
Performed a total of 0 transformations.                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.9\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.9. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding unused cells or wires in module \\core.. \n" + ], + "text/html": [ + "
Finding unused cells or wires in module \\core..                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed \u001b[1;36m2\u001b[0m unused cells and \u001b[1;36m2\u001b[0m unused wires. \n" + ], + "text/html": [ + "
Removed 2 unused cells and 2 unused wires.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m3\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n" + ], + "text/html": [ + "
<suppressed ~3 debug messages>                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m32.10\u001b[0m. Executing MEMORY_COLLECT pass \u001b[1m(\u001b[0mgenerating $mem cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
32.10. Executing MEMORY_COLLECT pass (generating $mem cells).                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
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33. Executing OPT_CLEAN pass (remove unused cells and wires).                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding unused cells or wires in module \\core.. \n" + ], + "text/html": [ + "
Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34\u001b[0m. Executing OPT pass \u001b[1m(\u001b[0mperforming simple optimizations\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34. Executing OPT pass (performing simple optimizations).                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.1\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34.1. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing module core. \n" + ], + "text/html": [ + "
Optimizing module core.                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m65\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n" + ], + "text/html": [ + "
<suppressed ~65 debug messages>                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.2\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34.2. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding identical cells in module `\\core'. \n" + ], + "text/html": [ + "
Finding identical cells in module `\\core'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m18\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n" + ], + "text/html": [ + "
<suppressed ~18 debug messages>                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed a total of \u001b[1;36m6\u001b[0m cells. \n" + ], + "text/html": [ + "
Removed a total of 6 cells.                                                                                        \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.3\u001b[0m. Executing OPT_DFF pass \u001b[1m(\u001b[0mperform DFF optimizations\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34.3. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2477\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1197_Y \u001b[1m[\u001b[0m\u001b[1;92m63:32\u001b[0m\u001b[1m]\u001b[0m, \n", + "Q = \\csr.mcycle \u001b[1m[\u001b[0m\u001b[1;92m63:32\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2477 ($sdff) from module core (D = $flatten\\csr.$procmux$1197_Y [63:32], \n",
+              "Q = \\csr.mcycle [63:32]).                                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2476\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\csr.$procmux$1185_Y \u001b[1m[\u001b[0m\u001b[1;92m63:32\u001b[0m\u001b[1m]\u001b[0m, \n", + "Q = \\csr.minstret \u001b[1m[\u001b[0m\u001b[1;92m63:32\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2476 ($sdff) from module core (D = $flatten\\csr.$procmux$1185_Y [63:32], \n",
+              "Q = \\csr.minstret [63:32]).                                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2133\u001b[0m \u001b[1m(\u001b[0m$sdffe\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $flatten\\fetch.$procmux$1880_Y \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.pcReg \u001b[1m[\u001b[0m\u001b[1;92m1:0\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $auto$ff.cc:266:slice$2133 ($sdffe) from module core (D = $flatten\\fetch.$procmux$1880_Y [1:0],\n",
+              "Q = \\fetch.pcReg [1:0]).                                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.4\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34.4. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding unused cells or wires in module \\core.. \n" + ], + "text/html": [ + "
Finding unused cells or wires in module \\core..                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed \u001b[1;36m33\u001b[0m unused cells and \u001b[1;36m60\u001b[0m unused wires. \n" + ], + "text/html": [ + "
Removed 33 unused cells and 60 unused wires.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m34\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n" + ], + "text/html": [ + "
<suppressed ~34 debug messages>                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.5\u001b[0m. Rerunning OPT passes. \u001b[1m(\u001b[0mRemoved registers in this run.\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
34.5. Rerunning OPT passes. (Removed registers in this run.)                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.6\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34.6. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing module core. \n" + ], + "text/html": [ + "
Optimizing module core.                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m1\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n" + ], + "text/html": [ + "
<suppressed ~1 debug messages>                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.7\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34.7. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding identical cells in module `\\core'. \n" + ], + "text/html": [ + "
Finding identical cells in module `\\core'.                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed a total of \u001b[1;36m0\u001b[0m cells. \n" + ], + "text/html": [ + "
Removed a total of 0 cells.                                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.8\u001b[0m. Executing OPT_DFF pass \u001b[1m(\u001b[0mperform DFF optimizations\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34.8. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.9\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
34.9. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding unused cells or wires in module \\core.. \n" + ], + "text/html": [ + "
Finding unused cells or wires in module \\core..                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m34.10\u001b[0m. Finished fast OPT passes. \n" + ], + "text/html": [ + "
34.10. Finished fast OPT passes.                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m35\u001b[0m. Executing MEMORY_MAP pass \u001b[1m(\u001b[0mconverting memories to logic and flip-flops\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
35. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Mapping memory \\fetch.bht.bhtTable_tag in module \\core: \n" + ], + "text/html": [ + "
Mapping memory \\fetch.bht.bhtTable_tag in module \\core:                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created \u001b[1;36m16\u001b[0m $dff cells and \u001b[1;36m0\u001b[0m static cells of width \u001b[1;36m26\u001b[0m. \n" + ], + "text/html": [ + "
created 16 $dff cells and 0 static cells of width 26.                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracted addr FF from read port \u001b[1;36m0\u001b[0m of core.fetch.bht.bhtTable_tag: $\\fetch.bht.bhtTable_tag$rdreg\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
Extracted addr FF from read port 0 of core.fetch.bht.bhtTable_tag: $\\fetch.bht.bhtTable_tag$rdreg[0]               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "read interface: \u001b[1;36m1\u001b[0m $dff and \u001b[1;36m15\u001b[0m $mux cells. \n" + ], + "text/html": [ + "
read interface: 1 $dff and 15 $mux cells.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "write interface: \u001b[1;36m16\u001b[0m write mux blocks. \n" + ], + "text/html": [ + "
write interface: 16 write mux blocks.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Mapping memory \\fetch.bht.bhtTable_target_pc in module \\core: \n" + ], + "text/html": [ + "
Mapping memory \\fetch.bht.bhtTable_target_pc in module \\core:                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created \u001b[1;36m16\u001b[0m $dff cells and \u001b[1;36m0\u001b[0m static cells of width \u001b[1;36m32\u001b[0m. \n" + ], + "text/html": [ + "
created 16 $dff cells and 0 static cells of width 32.                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracted addr FF from read port \u001b[1;36m0\u001b[0m of core.fetch.bht.bhtTable_target_pc: $\\fetch.bht.bhtTable_target_pc$rdreg\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
Extracted addr FF from read port 0 of core.fetch.bht.bhtTable_target_pc: $\\fetch.bht.bhtTable_target_pc$rdreg[0]   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "read interface: \u001b[1;36m1\u001b[0m $dff and \u001b[1;36m15\u001b[0m $mux cells. \n" + ], + "text/html": [ + "
read interface: 1 $dff and 15 $mux cells.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "write interface: \u001b[1;36m16\u001b[0m write mux blocks. \n" + ], + "text/html": [ + "
write interface: 16 write mux blocks.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Mapping memory \\fetch.bht.bhtTable_valid in module \\core: \n" + ], + "text/html": [ + "
Mapping memory \\fetch.bht.bhtTable_valid in module \\core:                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created \u001b[1;36m16\u001b[0m $dff cells and \u001b[1;36m0\u001b[0m static cells of width \u001b[1;36m1\u001b[0m. \n" + ], + "text/html": [ + "
created 16 $dff cells and 0 static cells of width 1.                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracted addr FF from read port \u001b[1;36m0\u001b[0m of core.fetch.bht.bhtTable_valid: $\\fetch.bht.bhtTable_valid$rdreg\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
Extracted addr FF from read port 0 of core.fetch.bht.bhtTable_valid: $\\fetch.bht.bhtTable_valid$rdreg[0]           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "read interface: \u001b[1;36m1\u001b[0m $dff and \u001b[1;36m15\u001b[0m $mux cells. \n" + ], + "text/html": [ + "
read interface: 1 $dff and 15 $mux cells.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "write interface: \u001b[1;36m16\u001b[0m write mux blocks. \n" + ], + "text/html": [ + "
write interface: 16 write mux blocks.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Mapping memory \\fetch.btb.btbTable in module \\core: \n" + ], + "text/html": [ + "
Mapping memory \\fetch.btb.btbTable in module \\core:                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "created \u001b[1;36m16\u001b[0m $dff cells and \u001b[1;36m0\u001b[0m static cells of width \u001b[1;36m2\u001b[0m. \n" + ], + "text/html": [ + "
created 16 $dff cells and 0 static cells of width 2.                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracted addr FF from read port \u001b[1;36m0\u001b[0m of core.fetch.btb.btbTable: $\\fetch.btb.btbTable$rdreg\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
Extracted addr FF from read port 0 of core.fetch.btb.btbTable: $\\fetch.btb.btbTable$rdreg[0]                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracted addr FF from read port \u001b[1;36m1\u001b[0m of core.fetch.btb.btbTable: $\\fetch.btb.btbTable$rdreg\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
Extracted addr FF from read port 1 of core.fetch.btb.btbTable: $\\fetch.btb.btbTable$rdreg[1]                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "read interface: \u001b[1;36m2\u001b[0m $dff and \u001b[1;36m30\u001b[0m $mux cells. \n" + ], + "text/html": [ + "
read interface: 2 $dff and 30 $mux cells.                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "write interface: \u001b[1;36m16\u001b[0m write mux blocks. \n" + ], + "text/html": [ + "
write interface: 16 write mux blocks.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m36\u001b[0m. Executing OPT pass \u001b[1m(\u001b[0mperforming simple optimizations\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
36. Executing OPT pass (performing simple optimizations).                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m36.1\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
36.1. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing module core. \n" + ], + "text/html": [ + "
Optimizing module core.                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m24\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n" + ], + "text/html": [ + "
<suppressed ~24 debug messages>                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m36.2\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
36.2. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding identical cells in module `\\core'. \n" + ], + "text/html": [ + "
Finding identical cells in module `\\core'.                                                                         \n",
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<suppressed ~105 debug messages>                                                                                   \n",
+              "
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Removed a total of 35 cells.                                                                                       \n",
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36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                              \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
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Evaluating internal representation of mux trees.                                                                   \n",
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Analyzing evaluation results.                                                                                      \n",
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Removed 0 multiplexer ports.                                                                                       \n",
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<suppressed ~105 debug messages>                                                                                   \n",
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36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                          \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
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Consolidated identical input bits for $mux cell $flatten\\decode.$ternary$/content/core.v:1203$673:                 \n",
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Old ports: A=2'10, B=2'00, Y=\\decode.ecause_out                                                                    \n",
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New ports: A=1'1, B=1'0, Y=\\decode.ecause_out [1]                                                                  \n",
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New connections: \\decode.ecause_out [0] = 1'0                                                                      \n",
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Old ports: A=2'00, B=2'10, Y=\\decode.control._io_aluop_T_29                                                        \n",
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New ports: A=1'0, B=1'1, Y=\\decode.control._io_aluop_T_29 [1]                                                      \n",
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New connections: \\decode.control._io_aluop_T_29 [0] = 1'0                                                          \n",
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Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:447$145:         \n",
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Old ports: A=2'00, B=2'11, Y=\\decode.control._io_memtoreg_T_3                                                      \n",
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New ports: A=1'0, B=1'1, Y=\\decode.control._io_memtoreg_T_3 [0]                                                    \n",
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Old ports: A=2'00, B=2'10, Y=\\decode.control._io_memtoreg_T_15                                                     \n",
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New ports: A=1'0, B=1'1, Y=\\decode.control._io_memtoreg_T_15 [1]                                                   \n",
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New connections: \\decode.control._io_memtoreg_T_15 [0] = 1'0                                                       \n",
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Consolidated identical input bits for $mux cell $flatten\\decode.\\immGen.$ternary$/content/core.v:968$490:          \n",
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Old ports: A=3'000, B=3'111, Y=\\decode.immGen._GEN_0                                                               \n",
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New ports: A=1'0, B=1'1, Y=\\decode.immGen._GEN_0 [0]                                                               \n",
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New connections: \\decode.immGen._GEN_0 [2:1] = { \\decode.immGen._GEN_0 [0] \\decode.immGen._GEN_0 [0] }             \n",
+              "
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Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=\\decode.immGen._imm_T_2                         \n",
+              "
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New ports: A=1'0, B=1'1, Y=\\decode.immGen._imm_T_2 [0]                                                             \n",
+              "
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New connections: \\decode.immGen._imm_T_2 [19:1] = { \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0]        \n",
+              "\\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0]    \n",
+              "\\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0]    \n",
+              "\\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0]    \n",
+              "\\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0] \\decode.immGen._imm_T_2 [0]    \n",
+              "\\decode.immGen._imm_T_2 [0] }                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\decode.\\immGen.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m980\u001b[0m$\u001b[1;36m508\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\decode.\\immGen.$ternary$/content/core.v:980$508:          \n",
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Old ports: A=19'0000000000000000000, B=19'1111111111111111111, Y=\\decode.immGen._imm_T_13                          \n",
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New ports: A=1'0, B=1'1, Y=\\decode.immGen._imm_T_13 [0]                                                            \n",
+              "
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New connections: \\decode.immGen._imm_T_13 [18:1] = { \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0]     \n",
+              "\\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0]\n",
+              "\\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0]\n",
+              "\\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0]\n",
+              "\\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0] \\decode.immGen._imm_T_13 [0]\n",
+              "}                                                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\decode.\\immGen.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m982\u001b[0m$\u001b[1;36m509\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\decode.\\immGen.$ternary$/content/core.v:982$509:          \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Old ports: \u001b[33mA\u001b[0m=\u001b[1;36m11\u001b[0m'\u001b[1;36m00000000000\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m11\u001b[0m'\u001b[1;36m11111111111\u001b[0m, \u001b[33mY\u001b[0m=\\decode.immGen._imm_T_20 \n" + ], + "text/html": [ + "
Old ports: A=11'00000000000, B=11'11111111111, Y=\\decode.immGen._imm_T_20                                          \n",
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New ports: A=1'0, B=1'1, Y=\\decode.immGen._imm_T_20 [0]                                                            \n",
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New connections: \\decode.immGen._imm_T_20 [10:1] = { \\decode.immGen._imm_T_20 [0] \\decode.immGen._imm_T_20 [0]     \n",
+              "\\decode.immGen._imm_T_20 [0] \\decode.immGen._imm_T_20 [0] \\decode.immGen._imm_T_20 [0] \\decode.immGen._imm_T_20 [0]\n",
+              "\\decode.immGen._imm_T_20 [0] \\decode.immGen._imm_T_20 [0] \\decode.immGen._imm_T_20 [0] \\decode.immGen._imm_T_20 [0]\n",
+              "}                                                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\decode.\\immGen.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m985\u001b[0m$\u001b[1;36m511\u001b[0m: \n" + ], + "text/html": [ + "
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Old ports: A=0, B={ \\fetch.instReg [31:12] 12'000000000000 }, Y=\\decode.immGen._GEN_9                              \n",
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New ports: A=20'00000000000000000000, B=\\fetch.instReg [31:12], Y=\\decode.immGen._GEN_9 [31:12]                    \n",
+              "
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New connections: \\decode.immGen._GEN_9 [11:0] = 12'000000000000                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\hazard.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2891\u001b[0m$\u001b[1;36m1069\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\hazard.$ternary$/content/core.v:2891$1069:                \n",
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Old ports: A=2'00, B=2'10, Y=\\hazard._GEN_0                                                                        \n",
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New ports: A=1'0, B=1'1, Y=\\hazard._GEN_0 [1]                                                                      \n",
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New connections: \\hazard._GEN_0 [0] = 1'0                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\hazard.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2892\u001b[0m$\u001b[1;36m1074\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\hazard.$ternary$/content/core.v:2892$1074:                \n",
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Old ports: A=2'00, B=2'10, Y=\\hazard._GEN_2                                                                        \n",
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New ports: A=1'0, B=1'1, Y=\\hazard._GEN_2 [1]                                                                      \n",
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New connections: \\hazard._GEN_2 [0] = 1'0                                                                          \n",
+              "
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Old ports: A=2'10, B=2'00, Y=\\memory._ecause_out_T [1:0]                                                           \n",
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New ports: A=1'1, B=1'0, Y=\\memory._ecause_out_T [1]                                                               \n",
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New connections: \\memory._ecause_out_T [0] = 1'0                                                                   \n",
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Optimizing cells in module \\core.                                                                                  \n",
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Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:448$147:         \n",
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Old ports: A=\\decode.control._io_memtoreg_T_3, B=2'11, Y=\\decode.control._io_memtoreg_T_5                          \n",
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Old ports: A=\\decode.control._io_memtoreg_T_15, B=2'10, Y=\\decode.control._io_memtoreg_T_17                        \n",
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New connections: \\decode.control._io_memtoreg_T_17 [0] = 1'0                                                       \n",
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Old ports: A=\\decode.immGen._GEN_0, B=3'110, Y=\\decode.immGen._GEN_1                                               \n",
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New ports: A={ \\decode.immGen._GEN_0 [0] \\decode.immGen._GEN_0 [0] }, B=2'10, Y=\\decode.immGen._GEN_1 [1:0]        \n",
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New connections: \\decode.immGen._GEN_1 [2] = \\decode.immGen._GEN_1 [1]                                             \n",
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Old ports: \u001b[33mA\u001b[0m=\\decode.immGen._GEN_9, \u001b[33mB\u001b[0m=\u001b[1m{\u001b[0m \\fetch.instReg \u001b[1m[\u001b[0m\u001b[1;92m31:12\u001b[0m\u001b[1m]\u001b[0m \u001b[1;36m12\u001b[0m'\u001b[1;36m000000000000\u001b[0m \u001b[1m}\u001b[0m, \u001b[33mY\u001b[0m=\\decode.immGen._GEN_10 \n" + ], + "text/html": [ + "
Old ports: A=\\decode.immGen._GEN_9, B={ \\fetch.instReg [31:12] 12'000000000000 }, Y=\\decode.immGen._GEN_10         \n",
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New ports: A=\\decode.immGen._GEN_9 [31:12], B=\\fetch.instReg [31:12], Y=\\decode.immGen._GEN_10 [31:12]             \n",
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New connections: \\decode.immGen._GEN_10 [11:0] = 12'000000000000                                                   \n",
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Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m449\u001b[0m$\u001b[1;36m149\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:449$149:         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Old ports: \u001b[33mA\u001b[0m=\\decode.control._io_memtoreg_T_5, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m11\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_7 \n" + ], + "text/html": [ + "
Old ports: A=\\decode.control._io_memtoreg_T_5, B=2'11, Y=\\decode.control._io_memtoreg_T_7                          \n",
+              "
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New ports: A=\\decode.control._io_memtoreg_T_5 [0], B=1'1, Y=\\decode.control._io_memtoreg_T_7 [0]                   \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "New connections: \\decode.control._io_memtoreg_T_7 \u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m = \\decode.control._io_memtoreg_T_7 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
New connections: \\decode.control._io_memtoreg_T_7 [1] = \\decode.control._io_memtoreg_T_7 [0]                       \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m450\u001b[0m$\u001b[1;36m151\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:450$151:         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Old ports: \u001b[33mA\u001b[0m=\\decode.control._io_memtoreg_T_7, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m11\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_9 \n" + ], + "text/html": [ + "
Old ports: A=\\decode.control._io_memtoreg_T_7, B=2'11, Y=\\decode.control._io_memtoreg_T_9                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "New ports: \u001b[33mA\u001b[0m=\\decode.control._io_memtoreg_T_7 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m1\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_9 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
New ports: A=\\decode.control._io_memtoreg_T_7 [0], B=1'1, Y=\\decode.control._io_memtoreg_T_9 [0]                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "New connections: \\decode.control._io_memtoreg_T_9 \u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m = \\decode.control._io_memtoreg_T_9 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
New connections: \\decode.control._io_memtoreg_T_9 [1] = \\decode.control._io_memtoreg_T_9 [0]                       \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m451\u001b[0m$\u001b[1;36m153\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:451$153:         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Old ports: \u001b[33mA\u001b[0m=\\decode.control._io_memtoreg_T_9, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m11\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_11 \n" + ], + "text/html": [ + "
Old ports: A=\\decode.control._io_memtoreg_T_9, B=2'11, Y=\\decode.control._io_memtoreg_T_11                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "New ports: \u001b[33mA\u001b[0m=\\decode.control._io_memtoreg_T_9 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m1\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_11 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
New ports: A=\\decode.control._io_memtoreg_T_9 [0], B=1'1, Y=\\decode.control._io_memtoreg_T_11 [0]                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "New connections: \\decode.control._io_memtoreg_T_11 \u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m = \\decode.control._io_memtoreg_T_11 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
New connections: \\decode.control._io_memtoreg_T_11 [1] = \\decode.control._io_memtoreg_T_11 [0]                     \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m452\u001b[0m$\u001b[1;36m155\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:452$155:         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Old ports: \u001b[33mA\u001b[0m=\\decode.control._io_memtoreg_T_11, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m11\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_13 \n" + ], + "text/html": [ + "
Old ports: A=\\decode.control._io_memtoreg_T_11, B=2'11, Y=\\decode.control._io_memtoreg_T_13                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "New ports: \u001b[33mA\u001b[0m=\\decode.control._io_memtoreg_T_11 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m1\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_13 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
New ports: A=\\decode.control._io_memtoreg_T_11 [0], B=1'1, Y=\\decode.control._io_memtoreg_T_13 [0]                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "New connections: \\decode.control._io_memtoreg_T_13 \u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m = \\decode.control._io_memtoreg_T_13 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n" + ], + "text/html": [ + "
New connections: \\decode.control._io_memtoreg_T_13 [1] = \\decode.control._io_memtoreg_T_13 [0]                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Optimizing cells in module \\core. \n" + ], + "text/html": [ + "
Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Performed a total of \u001b[1;36m20\u001b[0m changes. \n" + ], + "text/html": [ + "
Performed a total of 20 changes.                                                                                   \n",
+              "
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+              "
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36.5. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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<suppressed ~6 debug messages>                                                                                     \n",
+              "
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Removed a total of 2 cells.                                                                                        \n",
+              "
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+              "
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36.6. Executing OPT_SHARE pass.                                                                                    \n",
+              "
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Found cells that share an operand and can be merged by moving the $mux                                             \n",
+              "$auto$memory_share.cc:273:consolidate_wr_by_addr$2604 in front of them:                                            \n",
+              "
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$auto$alumacc.cc:485:replace_alu$2566                                                                              \n",
+              "
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$auto$alumacc.cc:485:replace_alu$2563                                                                              \n",
+              "
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+              "
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36.7. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
+              "
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Adding SRST signal on $\\fetch.btb.btbTable$rdreg[0] ($dff) from module core (D = \\decode.id_ex_pc_reg [5:2], Q =   \n",
+              "$\\fetch.btb.btbTable$rdreg[0]$q, rval = 4'0000).                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding SRST signal on $\\fetch.btb.btbTable$rdreg\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2583\u001b[0m, Q = \n", + "$\\fetch.btb.btbTable$rdreg\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m$q, rval = \u001b[1;36m4\u001b[0m'\u001b[1;36m0010\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding SRST signal on $\\fetch.btb.btbTable$rdreg[1] ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2583, Q = \n",
+              "$\\fetch.btb.btbTable$rdreg[1]$q, rval = 4'0010).                                                                   \n",
+              "
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+              "
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36.8. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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Removed 2 unused cells and 191 unused wires.                                                                       \n",
+              "
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<suppressed ~5 debug messages>                                                                                     \n",
+              "
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+              "
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36.9. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
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Optimizing module core.                                                                                            \n",
+              "
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<suppressed ~17 debug messages>                                                                                    \n",
+              "
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+              "
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36.10. Rerunning OPT passes. (Maybe there is more to do..)                                                         \n",
+              "
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+              "
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36.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
+              "
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Evaluating internal representation of mux trees.                                                                   \n",
+              "
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Analyzing evaluation results.                                                                                      \n",
+              "
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Removed 0 multiplexer ports.                                                                                       \n",
+              "
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<suppressed ~102 debug messages>                                                                                   \n",
+              "
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+              "
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36.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Consolidated identical input bits for $mux cell $auto$opt_share.\u001b[1;92mcc:244\u001b[0m:merge_operators$\u001b[1;36m3372\u001b[0m: \n" + ], + "text/html": [ + "
Consolidated identical input bits for $mux cell $auto$opt_share.cc:244:merge_operators$3372:                       \n",
+              "
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Old ports: A=2'11, B=2'01, Y=$auto$rtlil.cc:2573:Mux$3373                                                          \n",
+              "
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New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:2573:Mux$3373 [1]                                                        \n",
+              "
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New connections: $auto$rtlil.cc:2573:Mux$3373 [0] = 1'1                                                            \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Performed a total of \u001b[1;36m1\u001b[0m changes. \n" + ], + "text/html": [ + "
Performed a total of 1 changes.                                                                                    \n",
+              "
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+              "
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36.13. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Finding identical cells in module `\\core'. \n" + ], + "text/html": [ + "
Finding identical cells in module `\\core'.                                                                         \n",
+              "
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<suppressed ~21 debug messages>                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Removed a total of \u001b[1;36m7\u001b[0m cells. \n" + ], + "text/html": [ + "
Removed a total of 7 cells.                                                                                        \n",
+              "
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+              "
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36.14. Executing OPT_SHARE pass.                                                                                   \n",
+              "
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                                                                                                                   \n",
+              "
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36.15. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3201\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[9]$3201 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[9]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m8\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3199\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m8\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[8]$3199 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[8]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3197\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[7]$3197 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[7]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m6\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3195\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m6\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[6]$3195 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[6]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m5\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3193\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m5\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[5]$3193 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[5]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3191\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[4]$3191 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[4]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3189\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[3]$3189 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[3]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3187\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[2]$3187 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[2]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3185\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[1]$3185 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[1]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3213\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, \n", + "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[15]$3213 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, \n",
+              "Q = \\fetch.btb.btbTable[15]).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3211\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, \n", + "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[14]$3211 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, \n",
+              "Q = \\fetch.btb.btbTable[14]).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3209\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, \n", + "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[13]$3209 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, \n",
+              "Q = \\fetch.btb.btbTable[13]).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3207\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, \n", + "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[12]$3207 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, \n",
+              "Q = \\fetch.btb.btbTable[12]).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3205\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, \n", + "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[11]$3205 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, \n",
+              "Q = \\fetch.btb.btbTable[11]).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3203\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, \n", + "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[10]$3203 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, \n",
+              "Q = \\fetch.btb.btbTable[10]).                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m3183\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = $auto$rtlil.\u001b[1;92mcc:2573\u001b[0m:Mux$\u001b[1;36m2605\u001b[0m, Q\n", + "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.btb.btbTable[0]$3183 ($dff) from module core (D = $auto$rtlil.cc:2573:Mux$2605, Q\n",
+              "= \\fetch.btb.btbTable[0]).                                                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2919\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[9]$2919 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[9]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m8\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2917\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m8\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[8]$2917 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[8]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2915\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[7]$2915 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[7]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m6\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2913\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m6\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[6]$2913 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[6]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m5\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2911\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m5\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[5]$2911 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[5]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2909\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[4]$2909 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[4]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2907\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[3]$2907 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[3]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2905\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[2]$2905 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[2]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2903\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[1]$2903 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[1]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2931\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[15]$2931 ($dff) from module core (D =                     \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[15]).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2929\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[14]$2929 ($dff) from module core (D =                     \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[14]).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2927\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[13]$2927 ($dff) from module core (D =                     \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[13]).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2925\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[12]$2925 ($dff) from module core (D =                     \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[12]).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2923\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[11]$2923 ($dff) from module core (D =                     \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[11]).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2921\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[10]$2921 ($dff) from module core (D =                     \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[10]).                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2901\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n", + "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[0]$2901 ($dff) from module core (D =                      \n",
+              "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[0]).                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2714\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[9]$2714 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[9]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m8\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2712\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m8\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[8]$2712 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[8]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2710\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[7]$2710 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[7]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m6\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2708\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m6\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[6]$2708 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[6]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m5\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2706\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m5\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[5]$2706 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[5]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2704\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[4]$2704 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[4]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2702\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[3]$2702 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[3]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2700\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[2]$2700 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[2]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2698\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[1]$2698 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[1]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2726\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[15]$2726 ($dff) from module core (D = \\execute.mem_pc_reg       \n",
+              "[31:6], Q = \\fetch.bht.bhtTable_tag[15]).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2724\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[14]$2724 ($dff) from module core (D = \\execute.mem_pc_reg       \n",
+              "[31:6], Q = \\fetch.bht.bhtTable_tag[14]).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2722\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[13]$2722 ($dff) from module core (D = \\execute.mem_pc_reg       \n",
+              "[31:6], Q = \\fetch.bht.bhtTable_tag[13]).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2720\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[12]$2720 ($dff) from module core (D = \\execute.mem_pc_reg       \n",
+              "[31:6], Q = \\fetch.bht.bhtTable_tag[12]).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2718\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[11]$2718 ($dff) from module core (D = \\execute.mem_pc_reg       \n",
+              "[31:6], Q = \\fetch.bht.bhtTable_tag[11]).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2716\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n", + "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[10]$2716 ($dff) from module core (D = \\execute.mem_pc_reg       \n",
+              "[31:6], Q = \\fetch.bht.bhtTable_tag[10]).                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2696\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n", + "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
Adding EN signal on $memory\\fetch.bht.bhtTable_tag[0]$2696 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+              "Q = \\fetch.bht.bhtTable_tag[0]).                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Setting constant \u001b[1;36m0\u001b[0m-bit at position \u001b[1;36m0\u001b[0m on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2405\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core. \n" + ], + "text/html": [ + "
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2405 ($sdff) from module core.                       \n",
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36.16. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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Removed 48 unused cells and 62 unused wires.                                                                       \n",
+              "
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<suppressed ~49 debug messages>                                                                                    \n",
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36.17. Executing OPT_EXPR pass (perform const folding).                                                            \n",
+              "
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Optimizing module core.                                                                                            \n",
+              "
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<suppressed ~1 debug messages>                                                                                     \n",
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+              "
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36.18. Rerunning OPT passes. (Maybe there is more to do..)                                                         \n",
+              "
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+              "
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36.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
+              "
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Evaluating internal representation of mux trees.                                                                   \n",
+              "
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Analyzing evaluation results.                                                                                      \n",
+              "
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Removed 0 multiplexer ports.                                                                                       \n",
+              "
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<suppressed ~53 debug messages>                                                                                    \n",
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+              "
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36.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
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Consolidated identical input bits for $mux cell $flatten\\execute.$procmux$1455:                                    \n",
+              "
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Old ports: A={ \\decode.ecause_out_reg [1] 1'0 }, B=2'10, Y=$auto$wreduce.cc:461:run$2479 [1:0]                     \n",
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New ports: A=\\decode.ecause_out_reg [1], B=1'1, Y=$auto$wreduce.cc:461:run$2479 [1]                                \n",
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New connections: $auto$wreduce.cc:461:run$2479 [0] = 1'0                                                           \n",
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Optimizing cells in module \\core.                                                                                  \n",
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Performed a total of 1 changes.                                                                                    \n",
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36.21. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
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<suppressed ~3 debug messages>                                                                                     \n",
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Removed a total of 1 cells.                                                                                        \n",
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36.22. Executing OPT_SHARE pass.                                                                                   \n",
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36.23. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
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Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2199 ($sdff) from module core.                       \n",
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36.24. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
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Finding unused cells or wires in module \\core..                                                                    \n",
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Removed 1 unused cells and 1 unused wires.                                                                         \n",
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<suppressed ~2 debug messages>                                                                                     \n",
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36.25. Executing OPT_EXPR pass (perform const folding).                                                            \n",
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Optimizing module core.                                                                                            \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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36.26. Rerunning OPT passes. (Maybe there is more to do..)                                                         \n",
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36.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
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Running muxtree optimizer on module \\core..                                                                        \n",
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Creating internal representation of mux trees.                                                                     \n",
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Evaluating internal representation of mux trees.                                                                   \n",
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Analyzing evaluation results.                                                                                      \n",
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Removed 0 multiplexer ports.                                                                                       \n",
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<suppressed ~52 debug messages>                                                                                    \n",
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36.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
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Consolidated identical input bits for $mux cell $flatten\\memory.$ternary$/content/core.v:2213$790:                 \n",
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Old ports: A={ 1'0 \\execute.ecause_out_reg [1] 1'0 }, B={ 1'1 \\memory._ecause_out_T [1] 1'0 }, Y=\\memory._GEN_1    \n",
+              "[2:0]                                                                                                              \n",
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New ports: A={ 1'0 \\execute.ecause_out_reg [1] }, B={ 1'1 \\memory._ecause_out_T [1] }, Y=\\memory._GEN_1 [2:1]      \n",
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New connections: \\memory._GEN_1 [0] = 1'0                                                                          \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
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Performed a total of 1 changes.                                                                                    \n",
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36.29. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
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<suppressed ~6 debug messages>                                                                                     \n",
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Removed a total of 2 cells.                                                                                        \n",
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36.30. Executing OPT_SHARE pass.                                                                                   \n",
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36.31. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
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36.32. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
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Removed 0 unused cells and 1 unused wires.                                                                         \n",
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<suppressed ~1 debug messages>                                                                                     \n",
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36.33. Executing OPT_EXPR pass (perform const folding).                                                            \n",
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Optimizing module core.                                                                                            \n",
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36.34. Rerunning OPT passes. (Maybe there is more to do..)                                                         \n",
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36.35. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                             \n",
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Running muxtree optimizer on module \\core..                                                                        \n",
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Creating internal representation of mux trees.                                                                     \n",
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Evaluating internal representation of mux trees.                                                                   \n",
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Analyzing evaluation results.                                                                                      \n",
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Removed 0 multiplexer ports.                                                                                       \n",
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<suppressed ~52 debug messages>                                                                                    \n",
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36.36. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                         \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
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Performed a total of 0 changes.                                                                                    \n",
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36.37. Executing OPT_MERGE pass (detect identical cells).                                                          \n",
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Finding identical cells in module `\\core'.                                                                         \n",
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Removed a total of 0 cells.                                                                                        \n",
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36.38. Executing OPT_SHARE pass.                                                                                   \n",
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36.39. Executing OPT_DFF pass (perform DFF optimizations).                                                         \n",
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36.40. Executing OPT_CLEAN pass (remove unused cells and wires).                                                   \n",
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Finding unused cells or wires in module \\core..                                                                    \n",
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36.41. Executing OPT_EXPR pass (perform const folding).                                                            \n",
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Optimizing module core.                                                                                            \n",
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36.42. Finished OPT passes. (There is nothing left to do.)                                                         \n",
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37. Executing TECHMAP pass (map to technology primitives).                                                         \n",
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37.1. Executing Verilog-2005 frontend:                                                                             \n",
+              "/nix/store/vn1kmwhr52wisnfkmn6fk9g15p3klzs0-yosys/bin/../share/yosys/techmap.v                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Parsing Verilog input from `\u001b[35m/nix/store/vn1kmwhr52wisnfkmn6fk9g15p3klzs0-yosys/bin/../share/yosys/\u001b[0m\u001b[95mtechmap.v\u001b[0m' to AST \n", + "representation. \n" + ], + "text/html": [ + "
Parsing Verilog input from `/nix/store/vn1kmwhr52wisnfkmn6fk9g15p3klzs0-yosys/bin/../share/yosys/techmap.v' to AST \n",
+              "representation.                                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_simplemap_various'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_simplemap_various'.                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_simplemap_registers'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_simplemap_registers'.                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_shift_shiftx'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_shift_shiftx'.                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_fa'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_fa'.                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_lcu'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_lcu'.                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_alu'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_alu'.                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_macc'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_macc'.                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_alumacc'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_alumacc'.                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\$__div_mod_u'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\$__div_mod_u'.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\$__div_mod_trunc'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\$__div_mod_trunc'.                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_div'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_div'.                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_mod'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_mod'.                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\$__div_mod_floor'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\$__div_mod_floor'.                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_divfloor'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_divfloor'.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_modfloor'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_modfloor'.                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_pow'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_pow'.                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_pmux'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_pmux'.                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_demux'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_demux'.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Generating RTLIL representation for module `\\_90_lut'. \n" + ], + "text/html": [ + "
Generating RTLIL representation for module `\\_90_lut'.                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Successfully finished Verilog frontend. \n" + ], + "text/html": [ + "
Successfully finished Verilog frontend.                                                                            \n",
+              "
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                                                                                                                   \n",
+              "
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37.2. Continuing TECHMAP pass.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Using extmapper simplemap for cells of type $dffe. \n" + ], + "text/html": [ + "
Using extmapper simplemap for cells of type $dffe.                                                                 \n",
+              "
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Using extmapper simplemap for cells of type $mux.                                                                  \n",
+              "
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Using template $paramod$e3e2a2ae1e4d598b5e0e0be67cc1104653ecf8c1\\_90_alu for cells of type $alu.                   \n",
+              "
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Using extmapper simplemap for cells of type $and.                                                                  \n",
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Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\\_90_alu for cells of type $alu.                   \n",
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Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\\_90_alu for cells of type $alu.                   \n",
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Using extmapper simplemap for cells of type $not.                                                                  \n",
+              "
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Using extmapper simplemap for cells of type $eq.                                                                   \n",
+              "
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Using extmapper simplemap for cells of type $sdffe.                                                                \n",
+              "
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Using extmapper simplemap for cells of type $reduce_and.                                                           \n",
+              "
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Using extmapper simplemap for cells of type $or.                                                                   \n",
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Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\\_90_alu for cells of type $alu.                   \n",
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Using extmapper simplemap for cells of type $reduce_or.                                                            \n",
+              "
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Using extmapper simplemap for cells of type $xor.                                                                  \n",
+              "
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Using extmapper simplemap for cells of type $sdff.                                                                 \n",
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Using extmapper simplemap for cells of type $ne.                                                                   \n",
+              "
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Using extmapper simplemap for cells of type $logic_not.                                                            \n",
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Using extmapper simplemap for cells of type $reduce_bool.                                                          \n",
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Using template                                                                                                     \n",
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+              "ft_ops_shr_shl_sshl_sshr for cells of type $shl.                                                                   \n",
+              "
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Using template                                                                                                     \n",
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+              "ft_ops_shr_shl_sshl_sshr for cells of type $shr.                                                                   \n",
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Using template                                                                                                     \n",
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+              "ft_ops_shr_shl_sshl_sshr for cells of type $sshr.                                                                  \n",
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Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\\_90_alu for cells of type $alu.                   \n",
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Using extmapper simplemap for cells of type $dff.                                                                  \n",
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Using extmapper simplemap for cells of type $pos.                                                                  \n",
+              "
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No more expansions possible.                                                                                       \n",
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<suppressed ~5191 debug messages>                                                                                  \n",
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38. Executing OPT pass (performing simple optimizations).                                                          \n",
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38.1. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
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Optimizing module core.                                                                                            \n",
+              "
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<suppressed ~7701 debug messages>                                                                                  \n",
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38.2. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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<suppressed ~5619 debug messages>                                                                                  \n",
+              "
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Removed a total of 1873 cells.                                                                                     \n",
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38.3. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
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+              "
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38.4. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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Removed 499 unused cells and 2607 unused wires.                                                                    \n",
+              "
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<suppressed ~508 debug messages>                                                                                   \n",
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+              "
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38.5. Finished fast OPT passes.                                                                                    \n",
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+              "
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39. Executing ABC pass (technology mapping using ABC).                                                             \n",
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+              "
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39.1. Extracting gate netlist of module `\\core' to `<abc-temp-dir>/input.blif'..                                   \n",
+              "
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Replacing 69 occurrences of constant undef bits with constant zero bits                                            \n",
+              "
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Extracted 9926 gates and 12771 wires to a netlist network with 2842 inputs and 633 outputs.                        \n",
+              "
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+              "
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39.1.1. Executing ABC.                                                                                             \n",
+              "
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Running ABC command: \"/nix/store/5bgsgwzww9f2z7wl7kga42xrf1vpmnql-yosys-abc/bin/abc\" -s -f                         \n",
+              "<abc-temp-dir>/abc.script 2>&1                                                                                     \n",
+              "
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ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".                                                         \n",
+              "
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ABC:                                                                                                               \n",
+              "
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ABC: + read_blif <abc-temp-dir>/input.blif                                                                         \n",
+              "
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ABC: + read_library <abc-temp-dir>/stdcells.genlib                                                                 \n",
+              "
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ABC: Entered genlib library with 13 gates from file \"<abc-temp-dir>/stdcells.genlib\".                              \n",
+              "
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ABC: + strash                                                                                                      \n",
+              "
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ABC: + dretime                                                                                                     \n",
+              "
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ABC: + map                                                                                                         \n",
+              "
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ABC: + write_blif <abc-temp-dir>/output.blif                                                                       \n",
+              "
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+              "
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39.1.2. Re-integrating ABC results.                                                                                \n",
+              "
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ABC RESULTS:               MUX cells:     6225                                                                     \n",
+              "
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ABC RESULTS:               NOT cells:      534                                                                     \n",
+              "
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ABC RESULTS:              NAND cells:      200                                                                     \n",
+              "
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ABC RESULTS:             ORNOT cells:      188                                                                     \n",
+              "
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ABC RESULTS:               NOR cells:      170                                                                     \n",
+              "
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ABC RESULTS:               AND cells:      230                                                                     \n",
+              "
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ABC RESULTS:              XNOR cells:       51                                                                     \n",
+              "
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ABC RESULTS:               XOR cells:      414                                                                     \n",
+              "
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ABC RESULTS:            ANDNOT cells:     1006                                                                     \n",
+              "
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ABC RESULTS:                OR cells:     1033                                                                     \n",
+              "
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ABC RESULTS:        internal signals:     9296                                                                     \n",
+              "
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ABC RESULTS:           input signals:     2842                                                                     \n",
+              "
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ABC RESULTS:          output signals:      633                                                                     \n",
+              "
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Removing temp directory.                                                                                           \n",
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40. Executing OPT pass (performing simple optimizations).                                                          \n",
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40.1. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
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Optimizing module core.                                                                                            \n",
+              "
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<suppressed ~954 debug messages>                                                                                   \n",
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40.2. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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<suppressed ~9 debug messages>                                                                                     \n",
+              "
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Removed a total of 3 cells.                                                                                        \n",
+              "
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40.3. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
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40.4. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
+              "
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Removed 10 unused cells and 5010 unused wires.                                                                     \n",
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<suppressed ~388 debug messages>                                                                                   \n",
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40.5. Finished fast OPT passes.                                                                                    \n",
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41. Executing HIERARCHY pass (managing design hierarchy).                                                          \n",
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41.1. Analyzing design hierarchy..                                                                                 \n",
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Top module:  \\core                                                                                                 \n",
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41.2. Analyzing design hierarchy..                                                                                 \n",
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Top module:  \\core                                                                                                 \n",
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Removed 0 unused modules.                                                                                          \n",
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42. Printing statistics.                                                                                           \n",
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=== core ===                                                                                                       \n",
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Number of wires:              10554                                                                                \n",
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Number of wire bits:          20129                                                                                \n",
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Number of public wires:         803                                                                                \n",
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Number of public wire bits:   10373                                                                                \n",
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Number of memories:               0                                                                                \n",
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Number of memory bits:            0                                                                                \n",
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Number of processes:              0                                                                                \n",
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Number of cells:              12993                                                                                \n",
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$_ANDNOT_                    1004                                                                                  \n",
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$_AND_                        230                                                                                  \n",
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$_DFFE_PP_                    960                                                                                  \n",
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$_DFF_P_                       16                                                                                  \n",
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$_MUX_                       6225                                                                                  \n",
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$_NAND_                       200                                                                                  \n",
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$_NOR_                        169                                                                                  \n",
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$_NOT_                        524                                                                                  \n",
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$_ORNOT_                      188                                                                                  \n",
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$_OR_                        1033                                                                                  \n",
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$_SDFFE_PP0N_                  90                                                                                  \n",
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$_SDFFE_PP0P_                1159                                                                                  \n",
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$_SDFFE_PP1N_                   1                                                                                  \n",
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$_SDFF_PP0_                   728                                                                                  \n",
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$_SDFF_PP1_                     1                                                                                  \n",
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$_XNOR_                        51                                                                                  \n",
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$_XOR_                        414                                                                                  \n",
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43. Executing CHECK pass (checking for obvious problems).                                                          \n",
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Checking module core...                                                                                            \n",
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Found and reported 0 problems.                                                                                     \n",
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44. Generating Graphviz representation of design.                                                                  \n",
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Writing dot description to `/content/openlane_run/1-yosys-synthesis/post_techmap.dot'.                             \n",
+              "
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Dumping module core to page 1.                                                                                     \n",
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45. Executing SHARE pass (SAT-based resource sharing).                                                             \n",
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46. Executing OPT pass (performing simple optimizations).                                                          \n",
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46.1. Executing OPT_EXPR pass (perform const folding).                                                             \n",
+              "
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Optimizing module core.                                                                                            \n",
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46.2. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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Removed a total of 0 cells.                                                                                        \n",
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46.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).                                              \n",
+              "
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Running muxtree optimizer on module \\core..                                                                        \n",
+              "
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Creating internal representation of mux trees.                                                                     \n",
+              "
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No muxes found in this module.                                                                                     \n",
+              "
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Removed 0 multiplexer ports.                                                                                       \n",
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46.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).                                          \n",
+              "
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Optimizing cells in module \\core.                                                                                  \n",
+              "
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Performed a total of 0 changes.                                                                                    \n",
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+              "
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46.5. Executing OPT_MERGE pass (detect identical cells).                                                           \n",
+              "
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Finding identical cells in module `\\core'.                                                                         \n",
+              "
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Removed a total of 0 cells.                                                                                        \n",
+              "
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46.6. Executing OPT_DFF pass (perform DFF optimizations).                                                          \n",
+              "
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+              "
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46.7. Executing OPT_CLEAN pass (remove unused cells and wires).                                                    \n",
+              "
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Finding unused cells or wires in module \\core..                                                                    \n",
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Optimizing module core.                                                                                            \n",
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46.9. Finished OPT passes. (There is nothing left to do.)                                                          \n",
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47. Executing OPT_CLEAN pass (remove unused cells and wires).                                                      \n",
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Finding unused cells or wires in module \\core..                                                                    \n",
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Removed 0 unused cells and 577 unused wires.                                                                       \n",
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<suppressed ~577 debug messages>                                                                                   \n",
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\"$_XNOR_\": 51,                                                                                                     \n",
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\"$_XOR_\": 414                                                                                                      \n",
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Number of wire bits:          13336                                                                                \n",
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Number of public wire bits:    3580                                                                                \n",
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$_ANDNOT_                    1004                                                                                  \n",
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$_AND_                        230                                                                                  \n",
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$_DFFE_PP_                    960                                                                                  \n",
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$_DFF_P_                       16                                                                                  \n",
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$_MUX_                       6225                                                                                  \n",
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$_NAND_                       200                                                                                  \n",
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$_NOR_                        169                                                                                  \n",
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$_NOT_                        524                                                                                  \n",
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$_ORNOT_                      188                                                                                  \n",
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$_OR_                        1033                                                                                  \n",
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$_SDFFE_PP0N_                  90                                                                                  \n",
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$_SDFFE_PP0P_                1159                                                                                  \n",
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$_SDFFE_PP1N_                   1                                                                                  \n",
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$_SDFF_PP0_                   728                                                                                  \n",
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$_SDFF_PP1_                     1                                                                                  \n",
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$_XNOR_                        51                                                                                  \n",
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$_XOR_                        414                                                                                  \n",
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Area for cell type $_NOT_ is unknown!                                                                              \n",
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Area for cell type $_AND_ is unknown!                                                                              \n",
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Area for cell type $_NAND_ is unknown!                                                                             \n",
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Area for cell type $_OR_ is unknown!                                                                               \n",
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Area for cell type $_NOR_ is unknown!                                                                              \n",
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Area for cell type $_XOR_ is unknown!                                                                              \n",
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Area for cell type $_XNOR_ is unknown!                                                                             \n",
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Area for cell type $_ANDNOT_ is unknown!                                                                           \n",
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Area for cell type $_ORNOT_ is unknown!                                                                            \n",
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Area for cell type $_MUX_ is unknown!                                                                              \n",
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Area for cell type $_DFF_P_ is unknown!                                                                            \n",
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Area for cell type $_DFFE_PP_ is unknown!                                                                          \n",
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Area for cell type $_SDFF_PP0_ is unknown!                                                                         \n",
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Area for cell type $_SDFF_PP1_ is unknown!                                                                         \n",
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Area for cell type $_SDFFE_PP0N_ is unknown!                                                                       \n",
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Area for cell type $_SDFFE_PP0P_ is unknown!                                                                       \n",
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Area for cell type $_SDFFE_PP1N_ is unknown!                                                                       \n",
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mapping tbuf                                                                                                       \n",
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49. Executing TECHMAP pass (map to technology primitives).                                                         \n",
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Generating RTLIL representation for module `\\$_TBUF_'.                                                             \n",
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Successfully finished Verilog frontend.                                                                            \n",
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49.2. Continuing TECHMAP pass.                                                                                     \n",
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<suppressed ~3 debug messages>                                                                                     \n",
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51. Executing TECHMAP pass (map to technology primitives).                                                         \n",
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Generating RTLIL representation for module `\\$_DLATCH_N_'.                                                         \n",
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Successfully finished Verilog frontend.                                                                            \n",
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51.2. Continuing TECHMAP pass.                                                                                     \n",
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No more expansions possible.                                                                                       \n",
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<suppressed ~4 debug messages>                                                                                     \n",
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52. Executing SIMPLEMAP pass (map simple cells to gate primitives).                                                \n",
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53. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).                            \n",
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final dff cell mappings:                                                                                           \n",
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unmapped dff cell: $_DFF_N_                                                                                        \n",
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\\sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));                                                      \n",
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unmapped dff cell: $_DFF_NN0_                                                                                      \n",
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unmapped dff cell: $_DFF_NN1_                                                                                      \n",
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unmapped dff cell: $_DFF_NP0_                                                                                      \n",
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unmapped dff cell: $_DFF_NP1_                                                                                      \n",
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\\sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));                                      \n",
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\\sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));                                        \n",
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unmapped dff cell: $_DFF_PP0_                                                                                      \n",
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unmapped dff cell: $_DFF_PP1_                                                                                      \n",
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\\sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));            \n",
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unmapped dff cell: $_DFFSR_NNP_                                                                                    \n",
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unmapped dff cell: $_DFFSR_NPN_                                                                                    \n",
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unmapped dff cell: $_DFFSR_NPP_                                                                                    \n",
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unmapped dff cell: $_DFFSR_PNN_                                                                                    \n",
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unmapped dff cell: $_DFFSR_PNP_                                                                                    \n",
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unmapped dff cell: $_DFFSR_PPN_                                                                                    \n",
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unmapped dff cell: $_DFFSR_PPP_                                                                                    \n",
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53.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).                                   \n",
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Mapping DFF cells in module `\\core':                                                                               \n",
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mapped 2955 $_DFF_P_ cells to \\sky130_fd_sc_hd__dfxtp_2 cells.                                                     \n",
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\"modules\": {                                                                                                       \n",
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\"\\\\core\": {                                                                                                        \n",
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\"num_wires\":         14166,                                                                                        \n",
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\"num_wire_bits\":     17525,                                                                                        \n",
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\"num_pub_wires\":     226,                                                                                          \n",
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\"num_pub_wire_bits\": 3580,                                                                                         \n",
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\"num_memories\":      0,                                                                                            \n",
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\"num_memory_bits\":   0,                                                                                            \n",
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\"num_processes\":     0,                                                                                            \n",
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\"num_cells\":         17182,                                                                                        \n",
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\"area\":              62854.032000,                                                                                 \n",
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\"num_cells_by_type\": {                                                                                             \n",
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\"$_ANDNOT_\": 1004,                                                                                                 \n",
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\"$_AND_\": 230,                                                                                                     \n",
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\"$_MUX_\": 10414,                                                                                                   \n",
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\"$_NAND_\": 200,                                                                                                    \n",
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\"$_NOR_\": 169,                                                                                                     \n",
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\"$_NOT_\": 524,                                                                                                     \n",
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\"$_ORNOT_\": 188,                                                                                                   \n",
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\"$_OR_\": 1033,                                                                                                     \n",
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\"sky130_fd_sc_hd__dfxtp_2\": 2955                                                                                   \n",
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\"num_wires\":         14166,                                                                                        \n",
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\"num_wire_bits\":     17525,                                                                                        \n",
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\"num_pub_wire_bits\": 3580,                                                                                         \n",
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\"num_memory_bits\":   0,                                                                                            \n",
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\"num_cells\":         17182,                                                                                        \n",
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\"area\":              62854.032000,                                                                                 \n",
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\"$_ANDNOT_\": 1004,                                                                                                 \n",
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\"$_AND_\": 230,                                                                                                     \n",
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\"$_MUX_\": 10414,                                                                                                   \n",
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\"$_NAND_\": 200,                                                                                                    \n",
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\"$_NOR_\": 169,                                                                                                     \n",
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\"$_NOT_\": 524,                                                                                                     \n",
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\"$_ORNOT_\": 188,                                                                                                   \n",
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\"$_OR_\": 1033,                                                                                                     \n",
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\"$_XNOR_\": 51,                                                                                                     \n",
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\"$_XOR_\": 414,                                                                                                     \n",
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\"sky130_fd_sc_hd__dfxtp_2\": 2955                                                                                   \n",
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54. Printing statistics.                                                                                           \n",
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=== core ===                                                                                                       \n",
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Number of wires:              14166                                                                                \n",
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Number of wire bits:          17525                                                                                \n",
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Number of public wires:         226                                                                                \n",
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Number of public wire bits:    3580                                                                                \n",
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Number of memory bits:            0                                                                                \n",
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Number of cells:              17182                                                                                \n",
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$_ANDNOT_                    1004                                                                                  \n",
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$_AND_                        230                                                                                  \n",
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$_MUX_                      10414                                                                                  \n",
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$_NAND_                       200                                                                                  \n",
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$_NOR_                        169                                                                                  \n",
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$_NOT_                        524                                                                                  \n",
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$_ORNOT_                      188                                                                                  \n",
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$_OR_                        1033                                                                                  \n",
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$_XNOR_                        51                                                                                  \n",
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$_XOR_                        414                                                                                  \n",
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sky130_fd_sc_hd__dfxtp_2     2955                                                                                  \n",
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Area for cell type $_NOT_ is unknown!                                                                              \n",
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Area for cell type $_AND_ is unknown!                                                                              \n",
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Area for cell type $_NAND_ is unknown!                                                                             \n",
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Area for cell type $_OR_ is unknown!                                                                               \n",
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Area for cell type $_NOR_ is unknown!                                                                              \n",
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Area for cell type $_XOR_ is unknown!                                                                              \n",
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Area for cell type $_XNOR_ is unknown!                                                                             \n",
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Area for cell type $_ANDNOT_ is unknown!                                                                           \n",
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Area for cell type $_ORNOT_ is unknown!                                                                            \n",
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Area for cell type $_MUX_ is unknown!                                                                              \n",
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Chip area for module '\\core': 62854.032000                                                                         \n",
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[INFO] USING STRATEGY AREA 0                                                                                       \n",
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55. Executing ABC pass (technology mapping using ABC).                                                             \n",
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55.1. Extracting gate netlist of module `\\core' to `/tmp/yosys-abc-QiLN0Z/input.blif'..                            \n",
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Extracted 14227 gates and 17218 wires to a netlist network with 2989 inputs and 2956 outputs.                      \n",
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55.1.1. Executing ABC.                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Running ABC command: \u001b[32m\"/nix/store/5bgsgwzww9f2z7wl7kga42xrf1vpmnql-yosys-abc/bin/abc\"\u001b[0m -s -f \n", + "\u001b[35m/tmp/yosys-abc-QiLN0Z/\u001b[0m\u001b[95mabc.script\u001b[0m \u001b[1;36m2\u001b[0m>&\u001b[1;36m1\u001b[0m \n" + ], + "text/html": [ + "
Running ABC command: \"/nix/store/5bgsgwzww9f2z7wl7kga42xrf1vpmnql-yosys-abc/bin/abc\" -s -f                         \n",
+              "/tmp/yosys-abc-QiLN0Z/abc.script 2>&1                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: ABC command line: \u001b[32m\"source /tmp/yosys-abc-QiLN0Z/abc.script\"\u001b[0m. \n" + ], + "text/html": [ + "
ABC: ABC command line: \"source /tmp/yosys-abc-QiLN0Z/abc.script\".                                                  \n",
+              "
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ABC:                                                                                                               \n",
+              "
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ABC: + read_blif /tmp/yosys-abc-QiLN0Z/input.blif                                                                  \n",
+              "
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ABC: + read_lib -w /content/openlane_run/tmp/a7e4357152ff4ec4922d36fb2dd848f8.lib                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Parsing finished successfully. Parsing time = \u001b[1;36m0.13\u001b[0m sec \n" + ], + "text/html": [ + "
ABC: Parsing finished successfully.  Parsing time =     0.13 sec                                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfbbn_2\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfrbp_2\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfrtp_2\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfrtp_4\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfsbp_2\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfstp_2\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfstp_4\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfxbp_2\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfxtp_2\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dfxtp_4\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dlxtn_1\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dlxtn_2\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dlxtn_4\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped sequential cell \"sky130_fd_sc_hd__dlxtp_1\".                                   \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped three-state cell \"sky130_fd_sc_hd__ebufn_2\".                                  \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped three-state cell \"sky130_fd_sc_hd__ebufn_4\".                                  \n",
+              "
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ABC: Scl_LibertyReadGenlib() skipped three-state cell \"sky130_fd_sc_hd__ebufn_8\".                                  \n",
+              "
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ABC: Library \"sky130_fd_sc_hd__tt_025C_1v80\" from \"/content/openlane_run/tmp/a7e4357152ff4ec4922d36fb2dd848f8.lib\" \n",
+              "has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use).  Time =     0.21 sec                       \n",
+              "
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ABC: Memory =    9.54 MB. Time =     0.21 sec                                                                      \n",
+              "
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ABC: Warning: Detected 2 multi-output gates (for example, \"sky130_fd_sc_hd__fa_1\").                                \n",
+              "
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ABC: + read_constr -v /content/openlane_run/1-yosys-synthesis/synthesis.sdc                                        \n",
+              "
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ABC: Setting driving cell to be \"sky130_fd_sc_hd__inv_2/Y\".                                                        \n",
+              "
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ABC: Setting output load to be 33.442001.                                                                          \n",
+              "
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ABC: + read_constr /content/openlane_run/1-yosys-synthesis/synthesis.sdc                                           \n",
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ABC: + fx                                                                                                          \n",
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ABC: + mfs                                                                                                         \n",
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ABC: + strash                                                                                                      \n",
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ABC: + drf -l                                                                                                      \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drw -l                                                                                                      \n",
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ABC: + drf -l                                                                                                      \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drw -l                                                                                                      \n",
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ABC: + drw -l -z                                                                                                   \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drf -l -z                                                                                                   \n",
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ABC: + drw -l -z                                                                                                   \n",
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ABC: + balance                                                                                                     \n",
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ABC: + retime -D -D 10000 -M 5                                                                                     \n",
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ABC: + scleanup                                                                                                    \n",
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ABC: Error: The network is combinational.                                                                          \n",
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ABC: + fraig_store                                                                                                 \n",
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ABC: + balance                                                                                                     \n",
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ABC: + fraig_store                                                                                                 \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drw -l                                                                                                      \n",
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ABC: + drf -l                                                                                                      \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drw -l                                                                                                      \n",
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ABC: + drw -l -z                                                                                                   \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drf -l -z                                                                                                   \n",
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ABC: + drw -l -z                                                                                                   \n",
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ABC: + balance                                                                                                     \n",
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ABC: + fraig_store                                                                                                 \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drw -l                                                                                                      \n",
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ABC: + drf -l                                                                                                      \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drw -l                                                                                                      \n",
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ABC: + drw -l -z                                                                                                   \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drf -l -z                                                                                                   \n",
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ABC: + drw -l -z                                                                                                   \n",
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ABC: + balance                                                                                                     \n",
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ABC: + fraig_store                                                                                                 \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drw -l                                                                                                      \n",
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ABC: + drf -l                                                                                                      \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drw -l                                                                                                      \n",
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ABC: + drw -l -z                                                                                                   \n",
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ABC: + balance                                                                                                     \n",
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ABC: + drf -l -z                                                                                                   \n",
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ABC: + drw -l -z                                                                                                   \n",
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ABC: + balance                                                                                                     \n",
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ABC: + fraig_store                                                                                                 \n",
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ABC: + fraig_restore                                                                                               \n",
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ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000                                                                          \n",
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ABC: + retime -D -D 10000                                                                                          \n",
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ABC: + &get -n                                                                                                     \n",
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ABC: + &st                                                                                                         \n",
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ABC: + &dch                                                                                                        \n",
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ABC: + &nf                                                                                                         \n",
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ABC: + &put                                                                                                        \n",
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ABC: +                                                                                                             \n",
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ABC: + stime -p                                                                                                    \n",
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ABC: Cannot find the default PI driving cell (sky130_fd_sc_hd__inv_2/Y) in the library.                            \n",
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ABC: WireLoad = \"none\"  Gates =  10116 (  1.9 %)   Cap = 13.7 ff (  6.5 %)   Area =    95003.62 ( 75.4 %)   Delay =\n",
+              "12648.65 ps  (  1.5 %)                                                                                             \n",
+              "
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ABC: Path  0 --    1318 : 0    5 pi                       A =   0.00  Df =   0.0   -0.0 ps  S =   0.0 ps  Cin =    \n",
+              "0.0 ff  Cout =  11.1 ff  Cmax =   0.0 ff  G =    0                                                                 \n",
+              "
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ABC: Path  1 --    6059 : 2   19 sky130_fd_sc_hd__and2_2  A =   7.51  Df = 289.2  -23.4 ps  S = 268.7 ps  Cin =    \n",
+              "1.5 ff  Cout =  51.5 ff  Cmax = 303.0 ff  G = 3368                                                                 \n",
+              "
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ABC: Path  2 --    6099 : 2    5 sky130_fd_sc_hd__and2_2  A =   7.51  Df = 560.0  -19.4 ps  S = 138.8 ps  Cin =    \n",
+              "1.5 ff  Cout =  24.3 ff  Cmax = 303.0 ff  G = 1599                                                                 \n",
+              "
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ABC: Path  3 --    6998 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df = 787.3   -4.2 ps  S =  80.7 ps  Cin =    \n",
+              "1.5 ff  Cout =  10.9 ff  Cmax = 309.5 ff  G =  694                                                                 \n",
+              "
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ABC: Path  4 --    6999 : 2    4 sky130_fd_sc_hd__and2_2  A =   7.51  Df =1009.4  -28.3 ps  S = 101.8 ps  Cin =    \n",
+              "1.5 ff  Cout =  16.7 ff  Cmax = 303.0 ff  G = 1102                                                                 \n",
+              "
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ABC: Path  5 --    7000 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df =1236.2  -50.2 ps  S =  66.8 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.9 ff  Cmax = 309.5 ff  G =  498                                                                 \n",
+              "
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ABC: Path  6 --    7001 : 2    4 sky130_fd_sc_hd__and2_2  A =   7.51  Df =1459.5  -83.7 ps  S = 101.8 ps  Cin =    \n",
+              "1.5 ff  Cout =  16.7 ff  Cmax = 303.0 ff  G = 1102                                                                 \n",
+              "
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ABC: Path  7 --    7002 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df =1686.3 -105.7 ps  S =  66.8 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.9 ff  Cmax = 309.5 ff  G =  498                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m8\u001b[0m -- \u001b[1;36m7003\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m1909.6\u001b[0m \u001b[1;36m-139.2\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path  8 --    7003 : 2    4 sky130_fd_sc_hd__and2_2  A =   7.51  Df =1909.6 -139.2 ps  S = 101.8 ps  Cin =    \n",
+              "1.5 ff  Cout =  16.7 ff  Cmax = 303.0 ff  G = 1102                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m9\u001b[0m -- \u001b[1;36m7004\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m2136.5\u001b[0m \u001b[1;36m-161.2\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path  9 --    7004 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df =2136.5 -161.2 ps  S =  66.8 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.9 ff  Cmax = 309.5 ff  G =  498                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m10\u001b[0m -- \u001b[1;36m7005\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m2359.8\u001b[0m \u001b[1;36m-194.7\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 10 --    7005 : 2    4 sky130_fd_sc_hd__and2_2  A =   7.51  Df =2359.8 -194.7 ps  S = 101.8 ps  Cin =    \n",
+              "1.5 ff  Cout =  16.7 ff  Cmax = 303.0 ff  G = 1102                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m11\u001b[0m -- \u001b[1;36m7006\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m2586.6\u001b[0m \u001b[1;36m-216.7\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 11 --    7006 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df =2586.6 -216.7 ps  S =  66.8 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.9 ff  Cmax = 309.5 ff  G =  498                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m12\u001b[0m -- \u001b[1;36m7007\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m2809.9\u001b[0m \u001b[1;36m-250.3\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 12 --    7007 : 2    4 sky130_fd_sc_hd__and2_2  A =   7.51  Df =2809.9 -250.3 ps  S = 101.8 ps  Cin =    \n",
+              "1.5 ff  Cout =  16.7 ff  Cmax = 303.0 ff  G = 1102                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m13\u001b[0m -- \u001b[1;36m7008\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3036.8\u001b[0m \u001b[1;36m-272.2\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 13 --    7008 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df =3036.8 -272.2 ps  S =  66.8 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.9 ff  Cmax = 309.5 ff  G =  498                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m14\u001b[0m -- \u001b[1;36m7009\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3260.1\u001b[0m \u001b[1;36m-305.8\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 14 --    7009 : 2    4 sky130_fd_sc_hd__and2_2  A =   7.51  Df =3260.1 -305.8 ps  S = 101.8 ps  Cin =    \n",
+              "1.5 ff  Cout =  16.7 ff  Cmax = 303.0 ff  G = 1102                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m15\u001b[0m -- \u001b[1;36m7010\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3486.9\u001b[0m \u001b[1;36m-327.7\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 15 --    7010 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df =3486.9 -327.7 ps  S =  66.8 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.9 ff  Cmax = 309.5 ff  G =  498                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m16\u001b[0m -- \u001b[1;36m7011\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3710.2\u001b[0m \u001b[1;36m-361.3\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 16 --    7011 : 2    4 sky130_fd_sc_hd__and2_2  A =   7.51  Df =3710.2 -361.3 ps  S = 101.8 ps  Cin =    \n",
+              "1.5 ff  Cout =  16.7 ff  Cmax = 303.0 ff  G = 1102                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m17\u001b[0m -- \u001b[1;36m7012\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3937.1\u001b[0m \u001b[1;36m-383.2\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 17 --    7012 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df =3937.1 -383.2 ps  S =  66.8 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.9 ff  Cmax = 309.5 ff  G =  498                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m18\u001b[0m -- \u001b[1;36m7013\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m4137.4\u001b[0m \u001b[1;36m-427.1\u001b[0m ps S = \u001b[1;36m61.4\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m520\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 18 --    7013 : 2    3 sky130_fd_sc_hd__and2_2  A =   7.51  Df =4137.4 -427.1 ps  S =  61.4 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.9 ff  Cmax = 303.0 ff  G =  520                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m19\u001b[0m -- \u001b[1;36m7080\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m2\u001b[0m sky130_fd_sc_hd__or2_2 A = \u001b[1;36m6.26\u001b[0m Df =\u001b[1;36m4443.6\u001b[0m \u001b[1;36m-333.6\u001b[0m ps S = \u001b[1;36m66.9\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.2\u001b[0m ff Cmax = \u001b[1;36m299.4\u001b[0m ff G = \u001b[1;36m469\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 19 --    7080 : 2    2 sky130_fd_sc_hd__or2_2   A =   6.26  Df =4443.6 -333.6 ps  S =  66.9 ps  Cin =    \n",
+              "1.5 ff  Cout =   7.2 ff  Cmax = 299.4 ff  G =  469                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m20\u001b[0m -- \u001b[1;36m7093\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m1\u001b[0m sky130_fd_sc_hd__a21bo_2 A = \u001b[1;36m10.01\u001b[0m Df =\u001b[1;36m4650.7\u001b[0m \u001b[1;36m-430.1\u001b[0m ps S = \u001b[1;36m30.8\u001b[0m ps Cin = \n", + "\u001b[1;36m2.0\u001b[0m ff Cout = \u001b[1;36m1.6\u001b[0m ff Cmax = \u001b[1;36m288.4\u001b[0m ff G = \u001b[1;36m74\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 20 --    7093 : 3    1 sky130_fd_sc_hd__a21bo_2 A =  10.01  Df =4650.7 -430.1 ps  S =  30.8 ps  Cin =    \n",
+              "2.0 ff  Cout =   1.6 ff  Cmax = 288.4 ff  G =   74                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m21\u001b[0m -- \u001b[1;36m7102\u001b[0m : \u001b[1;36m4\u001b[0m \u001b[1;36m1\u001b[0m sky130_fd_sc_hd__or4_2 A = \u001b[1;36m8.76\u001b[0m Df =\u001b[1;36m5241.0\u001b[0m \u001b[1;36m-626.3\u001b[0m ps S = \u001b[1;36m95.5\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m2.5\u001b[0m ff Cmax = \u001b[1;36m310.4\u001b[0m ff G = \u001b[1;36m158\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 21 --    7102 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =5241.0 -626.3 ps  S =  95.5 ps  Cin =    \n",
+              "1.5 ff  Cout =   2.5 ff  Cmax = 310.4 ff  G =  158                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m22\u001b[0m -- \u001b[1;36m7103\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m2\u001b[0m sky130_fd_sc_hd__o21ba_2 A = \u001b[1;36m10.01\u001b[0m Df =\u001b[1;36m5449.5\u001b[0m \u001b[1;36m-656.0\u001b[0m ps S = \u001b[1;36m38.0\u001b[0m ps Cin = \n", + "\u001b[1;36m2.1\u001b[0m ff Cout = \u001b[1;36m3.2\u001b[0m ff Cmax = \u001b[1;36m264.6\u001b[0m ff G = \u001b[1;36m147\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 22 --    7103 : 3    2 sky130_fd_sc_hd__o21ba_2 A =  10.01  Df =5449.5 -656.0 ps  S =  38.0 ps  Cin =    \n",
+              "2.1 ff  Cout =   3.2 ff  Cmax = 264.6 ff  G =  147                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m23\u001b[0m -- \u001b[1;36m7104\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m2\u001b[0m sky130_fd_sc_hd__or2_2 A = \u001b[1;36m6.26\u001b[0m Df =\u001b[1;36m5727.3\u001b[0m \u001b[1;36m-829.2\u001b[0m ps S = \u001b[1;36m67.5\u001b[0m ps Cin = \n", + "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m6.2\u001b[0m ff Cmax = \u001b[1;36m299.4\u001b[0m ff G = \u001b[1;36m403\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 23 --    7104 : 2    2 sky130_fd_sc_hd__or2_2   A =   6.26  Df =5727.3 -829.2 ps  S =  67.5 ps  Cin =    \n",
+              "1.5 ff  Cout =   6.2 ff  Cmax = 299.4 ff  G =  403                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m24\u001b[0m -- \u001b[1;36m7105\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m252\u001b[0m sky130_fd_sc_hd__nor2_2 A = \u001b[1;36m6.26\u001b[0m Df =\u001b[1;36m9384.2\u001b[0m-\u001b[1;36m3709.0\u001b[0m ps S =\u001b[1;36m4983.1\u001b[0m ps Cin = \n", + "\u001b[1;36m4.4\u001b[0m ff Cout = \u001b[1;36m488.5\u001b[0m ff Cmax = \u001b[1;36m141.9\u001b[0m ff G =\u001b[1;36m10674\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 24 --    7105 : 2  252 sky130_fd_sc_hd__nor2_2  A =   6.26  Df =9384.2-3709.0 ps  S =4983.1 ps  Cin =    \n",
+              "4.4 ff  Cout = 488.5 ff  Cmax = 141.9 ff  G =10674                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m25\u001b[0m -- \u001b[1;36m7106\u001b[0m : \u001b[1;36m1\u001b[0m \u001b[1;36m45\u001b[0m sky130_fd_sc_hd__inv_2 A = \u001b[1;36m3.75\u001b[0m Df =\u001b[1;36m11119.0\u001b[0m-\u001b[1;36m4325.9\u001b[0m ps S =\u001b[1;36m1322.2\u001b[0m ps Cin = \n", + "\u001b[1;36m4.5\u001b[0m ff Cout = \u001b[1;36m211.8\u001b[0m ff Cmax = \u001b[1;36m331.4\u001b[0m ff G = \u001b[1;36m4468\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 25 --    7106 : 1   45 sky130_fd_sc_hd__inv_2   A =   3.75  Df =11119.0-4325.9 ps  S =1322.2 ps  Cin =   \n",
+              "4.5 ff  Cout = 211.8 ff  Cmax = 331.4 ff  G = 4468                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m26\u001b[0m -- \u001b[1;36m11086\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m30\u001b[0m sky130_fd_sc_hd__nor2_2 A = \u001b[1;36m6.26\u001b[0m Df =\u001b[1;36m12246.7\u001b[0m-\u001b[1;36m5092.5\u001b[0m ps S = \u001b[1;36m898.2\u001b[0m ps Cin = \n", + "\u001b[1;36m4.4\u001b[0m ff Cout = \u001b[1;36m75.3\u001b[0m ff Cmax = \u001b[1;36m141.9\u001b[0m ff G = \u001b[1;36m1599\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 26 --   11086 : 2   30 sky130_fd_sc_hd__nor2_2  A =   6.26  Df =12246.7-5092.5 ps  S = 898.2 ps  Cin =   \n",
+              "4.4 ff  Cout =  75.3 ff  Cmax = 141.9 ff  G = 1599                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Path \u001b[1;36m27\u001b[0m -- \u001b[1;36m11087\u001b[0m : \u001b[1;36m4\u001b[0m \u001b[1;36m1\u001b[0m sky130_fd_sc_hd__o22a_2 A = \u001b[1;36m10.01\u001b[0m Df =\u001b[1;36m12648.6\u001b[0m-\u001b[1;36m5102.1\u001b[0m ps S = \u001b[1;36m180.7\u001b[0m ps Cin = \n", + "\u001b[1;36m2.4\u001b[0m ff Cout = \u001b[1;36m33.4\u001b[0m ff Cmax = \u001b[1;36m304.9\u001b[0m ff G = \u001b[1;36m1417\u001b[0m \n" + ], + "text/html": [ + "
ABC: Path 27 --   11087 : 4    1 sky130_fd_sc_hd__o22a_2  A =  10.01  Df =12648.6-5102.1 ps  S = 180.7 ps  Cin =   \n",
+              "2.4 ff  Cout =  33.4 ff  Cmax = 304.9 ff  G = 1417                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: Start-point = pi1317 \u001b[1m(\u001b[0m\\csr.io_mem_pc \u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. End-point = po617 \u001b[1m(\u001b[0m$auto$rtlil.\u001b[1;92mcc:2684\u001b[0m:MuxGate$\u001b[1;36m37770\u001b[0m\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
ABC: Start-point = pi1317 (\\csr.io_mem_pc [3]).  End-point = po617 ($auto$rtlil.cc:2684:MuxGate$37770).            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: + print_stats -m \n" + ], + "text/html": [ + "
ABC: + print_stats -m                                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: netlist : i/o = \u001b[1;36m2989\u001b[0m/ \u001b[1;36m2956\u001b[0m lat = \u001b[1;36m0\u001b[0m nd = \u001b[1;36m10116\u001b[0m edge = \u001b[1;36m31670\u001b[0m area =\u001b[1;36m95014.86\u001b[0m delay\n", + "=\u001b[1;36m32.00\u001b[0m lev = \u001b[1;36m32\u001b[0m \n" + ], + "text/html": [ + "
ABC: netlist                       : i/o = 2989/ 2956  lat =    0  nd = 10116  edge =  31670  area =95014.86  delay\n",
+              "=32.00  lev = 32                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ABC: + write_blif \u001b[35m/tmp/yosys-abc-QiLN0Z/\u001b[0m\u001b[95moutput.blif\u001b[0m \n" + ], + "text/html": [ + "
ABC: + write_blif /tmp/yosys-abc-QiLN0Z/output.blif                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
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ABC RESULTS:   sky130_fd_sc_hd__or3_2 cells:       93                                                              \n",
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ABC RESULTS:   sky130_fd_sc_hd__nand2_2 cells:     1029                                                            \n",
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ABC RESULTS:   sky130_fd_sc_hd__or2_2 cells:      804                                                              \n",
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ABC RESULTS:   sky130_fd_sc_hd__a21o_2 cells:      389                                                             \n",
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ABC RESULTS:   sky130_fd_sc_hd__o211a_2 cells:     1599                                                            \n",
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ABC RESULTS:        internal signals:    11273                                                                     \n",
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ABC RESULTS:           input signals:     2989                                                                     \n",
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ABC RESULTS:          output signals:     2956                                                                     \n",
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Warning: Selection \"LO\" did not match any object.                                                                  \n",
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Finding unused cells or wires in module \\core..                                                                    \n",
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Removed 0 unused cells and 17492 unused wires.                                                                     \n",
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<suppressed ~562 debug messages>                                                                                   \n",
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Checking module core...                                                                                            \n",
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\"num_wires\":         12982,                                                                                        \n",
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\"num_wire_bits\":     13138,                                                                                        \n",
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\"num_pub_wire_bits\": 3019,                                                                                         \n",
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\"num_cells\":         13071,                                                                                        \n",
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\"area\":              157857.648000,                                                                                \n",
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\"sky130_fd_sc_hd__a211o_2\": 389,                                                                                   \n",
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\"sky130_fd_sc_hd__xor2_2\": 41                                                                                      \n",
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\"sky130_fd_sc_hd__xor2_2\": 41                                                                                      \n",
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sky130_fd_sc_hd__a2111o_2       2                                                                                  \n",
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sky130_fd_sc_hd__a211o_2      389                                                                                  \n",
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sky130_fd_sc_hd__a211oi_2      28                                                                                  \n",
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sky130_fd_sc_hd__a21bo_2       23                                                                                  \n",
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sky130_fd_sc_hd__a21boi_2      17                                                                                  \n",
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sky130_fd_sc_hd__a21o_2       389                                                                                  \n",
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sky130_fd_sc_hd__a21oi_2      190                                                                                  \n",
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sky130_fd_sc_hd__a221o_2      173                                                                                  \n",
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sky130_fd_sc_hd__a221oi_2       3                                                                                  \n",
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sky130_fd_sc_hd__a22o_2       103                                                                                  \n",
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sky130_fd_sc_hd__a22oi_2       18                                                                                  \n",
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sky130_fd_sc_hd__a2bb2o_2      20                                                                                  \n",
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sky130_fd_sc_hd__a311o_2        9                                                                                  \n",
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sky130_fd_sc_hd__a311oi_2       2                                                                                  \n",
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sky130_fd_sc_hd__a31o_2       106                                                                                  \n",
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sky130_fd_sc_hd__a31oi_2        7                                                                                  \n",
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sky130_fd_sc_hd__a32o_2        16                                                                                  \n",
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sky130_fd_sc_hd__a32oi_2        3                                                                                  \n",
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sky130_fd_sc_hd__a41o_2        13                                                                                  \n",
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sky130_fd_sc_hd__a41oi_2        1                                                                                  \n",
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sky130_fd_sc_hd__and2_2       413                                                                                  \n",
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sky130_fd_sc_hd__and2b_2       33                                                                                  \n",
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sky130_fd_sc_hd__and3_2       430                                                                                  \n",
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sky130_fd_sc_hd__and3b_2        8                                                                                  \n",
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sky130_fd_sc_hd__and4_2        64                                                                                  \n",
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sky130_fd_sc_hd__and4b_2        3                                                                                  \n",
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sky130_fd_sc_hd__and4bb_2       5                                                                                  \n",
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sky130_fd_sc_hd__dfxtp_2     2955                                                                                  \n",
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sky130_fd_sc_hd__inv_2        193                                                                                  \n",
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sky130_fd_sc_hd__mux2_1      2063                                                                                  \n",
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sky130_fd_sc_hd__mux4_2       198                                                                                  \n",
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sky130_fd_sc_hd__nand2_2     1029                                                                                  \n",
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sky130_fd_sc_hd__nand2b_2      37                                                                                  \n",
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sky130_fd_sc_hd__nand3_2       28                                                                                  \n",
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sky130_fd_sc_hd__nand3b_2       4                                                                                  \n",
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sky130_fd_sc_hd__nand4_2        5                                                                                  \n",
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sky130_fd_sc_hd__nand4b_2       1                                                                                  \n",
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sky130_fd_sc_hd__nor2_2       345                                                                                  \n",
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sky130_fd_sc_hd__nor3_2        72                                                                                  \n",
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sky130_fd_sc_hd__nor3b_2        3                                                                                  \n",
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sky130_fd_sc_hd__nor4_2         2                                                                                  \n",
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sky130_fd_sc_hd__nor4b_2        1                                                                                  \n",
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sky130_fd_sc_hd__o2111a_2      11                                                                                  \n",
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sky130_fd_sc_hd__o211a_2     1599                                                                                  \n",
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sky130_fd_sc_hd__o211ai_2       6                                                                                  \n",
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sky130_fd_sc_hd__o21a_2       207                                                                                  \n",
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sky130_fd_sc_hd__o21ai_2      130                                                                                  \n",
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sky130_fd_sc_hd__o21ba_2       13                                                                                  \n",
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sky130_fd_sc_hd__o21bai_2       3                                                                                  \n",
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sky130_fd_sc_hd__o221a_2      350                                                                                  \n",
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sky130_fd_sc_hd__o221ai_2       5                                                                                  \n",
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sky130_fd_sc_hd__o22a_2       112                                                                                  \n",
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sky130_fd_sc_hd__o22ai_2        2                                                                                  \n",
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sky130_fd_sc_hd__o2bb2a_2      29                                                                                  \n",
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sky130_fd_sc_hd__o311a_2       43                                                                                  \n",
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sky130_fd_sc_hd__o31a_2        52                                                                                  \n",
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sky130_fd_sc_hd__o31ai_2        2                                                                                  \n",
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sky130_fd_sc_hd__o32a_2         2                                                                                  \n",
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sky130_fd_sc_hd__o41a_2         2                                                                                  \n",
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sky130_fd_sc_hd__or2_2        804                                                                                  \n",
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sky130_fd_sc_hd__or3_2         93                                                                                  \n",
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sky130_fd_sc_hd__or3b_2        29                                                                                  \n",
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sky130_fd_sc_hd__or4_2         48                                                                                  \n",
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sky130_fd_sc_hd__or4b_2        10                                                                                  \n",
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sky130_fd_sc_hd__or4bb_2        4                                                                                  \n",
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sky130_fd_sc_hd__xnor2_2       70                                                                                  \n",
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sky130_fd_sc_hd__xor2_2        41                                                                                  \n",
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Chip area for module '\\core': 157857.648000                                                                        \n",
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63. Executing Verilog backend.                                                                                     \n",
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Dumping module `\\core'.                                                                                            \n",
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64. Executing JSON backend.                                                                                        \n",
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Yosys 0.38 (git sha1 543faed9c8c, clang++ 16.0.6 -fPIC -Os)                                                        \n",
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Time spent: 72% 2x abc (51 sec), 6% 31x opt_clean (4 sec), ...                                                     \n",
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[11:15:38] VERBOSE  Parsing synthesis checks…                                                           yosys.py:55\n",
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nlopenlane_run/1-yosys-synthesis/core.nl.v
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" + ] + }, + "metadata": {}, + "execution_count": 28 + } + ], + "source": [ + "from openlane.state import State\n", + "path=\"/content\"\n", + "synthesis = Synthesis(\n", + " VERILOG_FILES=[\"/content/core.v\"],\n", + " state_in=State(),\n", + ")\n", + "synthesis.start()" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "80ca8345-e31c-4a74-9416-a7141ec430e9", + "metadata": { + "id": "80ca8345-e31c-4a74-9416-a7141ec430e9", + "colab": { + "base_uri": "https://localhost:8080/", + "height": 118 + }, + "outputId": "c040da31-a54c-4fc4-bf44-90705458a384" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "text/markdown": "#### Time Elapsed: 88.53s\n#### Views updated:\n* Verilog Netlist\n" + }, + "metadata": {} + } + ], + "source": [ + "display(synthesis)" + ] + }, + { + "cell_type": "markdown", + "id": "be98a880-4deb-42fb-8070-13965ec29756", + "metadata": { + "id": "be98a880-4deb-42fb-8070-13965ec29756" + }, + "source": [ + "#### Floorplanning" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "fbe4b979-02c7-4bad-955d-a8622798f1ab", + "metadata": { + "id": "fbe4b979-02c7-4bad-955d-a8622798f1ab", + "colab": { + "base_uri": "https://localhost:8080/", + "height": 988 + }, + "outputId": "606b766f-8222-4007-c849-b0201eb827ab" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[92m──────────────────────────────────────────── \u001b[0mFloorplan Initialization\u001b[92m ─────────────────────────────────────────────\u001b[0m\n" + ], + "text/html": [ + "
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[11:17:43] VERBOSE  Running 'OpenROAD.Floorplan'(Log:                                                step.py:1085\n",
+              "                    ./openlane_run/2-openroad-floorplan/openroad-floorplan.log)                                    \n",
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[INFO ODB-0223]     Created 13 technology layers                                                                   \n",
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[INFO ODB-0224]     Created 25 technology vias                                                                     \n",
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[INFO ODB-0226] Finished LEF file:                                                                                 \n",
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[INFO ODB-0225]     Created 4 library cells                                                                        \n",
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The NOWIREEXTENSIONATPIN statement will be ignored. See file                                                       \n",
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[INFO ODB-0225]     Created 437 library cells                                                                      \n",
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Linking design 'core' from netlist…                                                                                \n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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Using site height: 2.72 and site width: 0.46…                                                                      \n",
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[INFO] Using relative sizing for the floorplan.                                                                    \n",
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[INFO IFP-0001] Added 206 rows of 1221 site unithd.                                                                \n",
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[INFO IFP-0030] Inserted 0 tiecells using sky130_fd_sc_hd__conb_1/LO.                                              \n",
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[INFO IFP-0030] Inserted 0 tiecells using sky130_fd_sc_hd__conb_1/HI.                                              \n",
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[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan                                                        \n",
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[INFO] Floorplanned on a die area of 0.0 0.0 572.925 583.645 (µm).                                                 \n",
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[INFO] Floorplanned on a core area of 5.52 10.88 567.18 571.2 (µm).                                                \n",
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Writing metric design__die__bbox: 0.0 0.0 572.925 583.645                                                          \n",
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Writing metric design__core__bbox: 5.52 10.88 567.18 571.2                                                         \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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─────────────────────────────────────────────── Tap/Decap Insertion ───────────────────────────────────────────────\n",
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[11:17:56] VERBOSE  Running 'OpenROAD.TapEndcapInsertion'(Log:                                       step.py:1085\n",
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Reading OpenROAD database at '/content/openlane_run/2-openroad-floorplan/core.odb'…                                \n",
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Reading design constraints file at '/content/openlane_ipynb/openlane/scripts/base.sdc'…                            \n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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Setting global connections for newly added cells…                                                                  \n",
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────────────────────────────────────────────────── I/O Placement ──────────────────────────────────────────────────\n",
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[11:19:24] VERBOSE  Running 'OpenROAD.IOPlacement'(Log:                                              step.py:1085\n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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[INFO] place_pins args: -min_distance 3                                                                            \n",
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[INFO PPL-0001] Number of slots           700                                                                      \n",
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[INFO PPL-0002] Number of I/O             168                                                                      \n",
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[INFO PPL-0004] Number of I/O w/o sink    0                                                                        \n",
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[INFO PPL-0006] Slots increase factor     0.01                                                                     \n",
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[INFO PPL-0008] Successfully assigned pins to sections.                                                            \n",
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[INFO PPL-0012] I/O nets HPWL: 72116.02 um.                                                                        \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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[11:19:29] VERBOSE  Running 'KLayout.Render'(Log: /tmp/tmpyiugjvpj/klayout-render.log)               step.py:1085\n",
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────────────────────────────────────── Power Distribution Network Generation ──────────────────────────────────────\n",
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[11:19:37] VERBOSE  Running 'OpenROAD.GeneratePDN'(Log:                                              step.py:1085\n",
+              "                    ./openlane_run/5-openroad-generatepdn/openroad-generatepdn.log)                                \n",
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[11:19:37] INFO     'FP_PDN_CFG' not explicitly set, setting it to                                 openroad.py:1085\n",
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Reading OpenROAD database at '/content/openlane_run/4-openroad-ioplacement/core.odb'…                              \n",
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Reading design constraints file at '/content/openlane_ipynb/openlane/scripts/base.sdc'…                            \n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting clock transition to: 0.1499999999999999944488848768742172978818416595458984375                      \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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[INFO] Setting global connections...                                                                               \n",
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[INFO PDN-0001] Inserting grid: stdcell_grid                                                                       \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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Writing OpenROAD database to '/content/openlane_run/5-openroad-generatepdn/core.odb'…                              \n",
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Writing netlist to '/content/openlane_run/5-openroad-generatepdn/core.nl.v'…                                       \n",
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Writing powered netlist to '/content/openlane_run/5-openroad-generatepdn/core.pnl.v'…                              \n",
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Writing layout to '/content/openlane_run/5-openroad-generatepdn/core.def'…                                         \n",
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Writing timing constraints to '/content/openlane_run/5-openroad-generatepdn/core.sdc'…                             \n",
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[INFO PSM-0076] Setting metal node density to be standard cell height times 5.                                     \n",
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[INFO PSM-0031] Number of PDN nodes on net VPWR = 7670.                                                            \n",
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[INFO PSM-0064] Number of voltage sources = 204.                                                                   \n",
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[INFO PSM-0040] All PDN stripes on net VPWR are connected.                                                         \n",
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[INFO PSM-0076] Setting metal node density to be standard cell height times 5.                                     \n",
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[INFO PSM-0031] Number of PDN nodes on net VGND = 7640.                                                            \n",
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[INFO PSM-0064] Number of voltage sources = 204.                                                                   \n",
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[INFO PSM-0040] All PDN stripes on net VGND are connected.                                                         \n",
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[11:19:42] VERBOSE  Running 'KLayout.Render'(Log: /tmp/tmpa44zu9sk/klayout-render.log)               step.py:1085\n",
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──────────────────────────────────────────────── Global Placement ─────────────────────────────────────────────────\n",
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[11:19:48] VERBOSE  Running 'OpenROAD.GlobalPlacement'(Log:                                          step.py:1085\n",
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Reading OpenROAD database at '/content/openlane_run/5-openroad-generatepdn/core.odb'…                              \n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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[INFO] Setting RC values…                                                                                          \n",
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[INFO GPL-0002] DBU: 1000                                                                                          \n",
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[INFO GPL-0003] SiteSize: 460 2720                                                                                 \n",
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[INFO GPL-0004] CoreAreaLxLy: 5520 10880                                                                           \n",
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[INFO GPL-0005] CoreAreaUxUy: 567180 571200                                                                        \n",
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[INFO GPL-0006] NumInstances: 17955                                                                                \n",
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[INFO GPL-0007] NumPlaceInstances: 13071                                                                           \n",
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[INFO GPL-0008] NumFixedInstances: 4884                                                                            \n",
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[INFO GPL-0010] NumNets: 13138                                                                                     \n",
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[INFO GPL-0011] NumPins: 50819                                                                                     \n",
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[INFO GPL-0013] DieAreaUxUy: 572925 583645                                                                         \n",
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[INFO GPL-0014] CoreAreaLxLy: 5520 10880                                                                           \n",
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[INFO GPL-0015] CoreAreaUxUy: 567180 571200                                                                        \n",
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[INFO GPL-0016] CoreArea: 314709331200                                                                             \n",
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[INFO GPL-0017] NonPlaceInstsArea: 7141849600                                                                      \n",
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[INFO GPL-0018] PlaceInstsArea: 157857648000                                                                       \n",
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[INFO GPL-0020] StdInstsArea: 157857648000                                                                         \n",
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[InitialPlace]  Iter: 12 CG residual: 0.00001097 HPWL: 147522321                                                   \n",
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[InitialPlace]  Iter: 13 CG residual: 0.00001621 HPWL: 147412337                                                   \n",
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[InitialPlace]  Iter: 14 CG residual: 0.00000746 HPWL: 147573536                                                   \n",
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[INFO GPL-0023] TargetDensity: 0.62                                                                                \n",
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[INFO GPL-0024] AveragePlaceInstArea: 12076937                                                                     \n",
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[INFO GPL-0025] IdealBinArea: 19498492                                                                             \n",
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[INFO GPL-0026] IdealBinCnt: 16140                                                                                 \n",
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[INFO GPL-0027] TotalBinArea: 314709331200                                                                         \n",
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[INFO GPL-0028] BinCnt: 64 64                                                                                      \n",
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[INFO GPL-0029] BinSize: 8776 8755                                                                                 \n",
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[INFO GPL-0030] NumBins: 4096                                                                                      \n",
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[NesterovSolve] Iter: 1 overflow: 0.990944 HPWL: 59164201                                                          \n",
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[NesterovSolve] Iter: 10 overflow: 0.979738 HPWL: 71693033                                                         \n",
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[NesterovSolve] Iter: 20 overflow: 0.978966 HPWL: 73057082                                                         \n",
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[NesterovSolve] Iter: 30 overflow: 0.979063 HPWL: 73100353                                                         \n",
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[NesterovSolve] Iter: 40 overflow: 0.978934 HPWL: 72941175                                                         \n",
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[NesterovSolve] Iter: 50 overflow: 0.978797 HPWL: 73072813                                                         \n",
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[NesterovSolve] Iter: 60 overflow: 0.978746 HPWL: 73182593                                                         \n",
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[NesterovSolve] Iter: 70 overflow: 0.978726 HPWL: 73208366                                                         \n",
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[NesterovSolve] Iter: 80 overflow: 0.978703 HPWL: 73228814                                                         \n",
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[NesterovSolve] Iter: 90 overflow: 0.978677 HPWL: 73288715                                                         \n",
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[NesterovSolve] Iter: 100 overflow: 0.978633 HPWL: 73393652                                                        \n",
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[NesterovSolve] Iter: 110 overflow: 0.978558 HPWL: 73549788                                                        \n",
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[NesterovSolve] Iter: 120 overflow: 0.978378 HPWL: 73822655                                                        \n",
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[NesterovSolve] Iter: 130 overflow: 0.978062 HPWL: 74314793                                                        \n",
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[NesterovSolve] Iter: 140 overflow: 0.977453 HPWL: 75185670                                                        \n",
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[NesterovSolve] Iter: 150 overflow: 0.976101 HPWL: 76749926                                                        \n",
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[NesterovSolve] Iter: 160 overflow: 0.973958 HPWL: 79307875                                                        \n",
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[NesterovSolve] Iter: 170 overflow: 0.971194 HPWL: 83370741                                                        \n",
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[NesterovSolve] Iter: 180 overflow: 0.965089 HPWL: 89510962                                                        \n",
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[NesterovSolve] Iter: 190 overflow: 0.956489 HPWL: 98324355                                                        \n",
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[NesterovSolve] Iter: 200 overflow: 0.94476 HPWL: 110585156                                                        \n",
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[NesterovSolve] Iter: 210 overflow: 0.929371 HPWL: 125977384                                                       \n",
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[NesterovSolve] Iter: 220 overflow: 0.910246 HPWL: 143255846                                                       \n",
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[NesterovSolve] Iter: 230 overflow: 0.891236 HPWL: 162111732                                                       \n",
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[NesterovSolve] Iter: 240 overflow: 0.866512 HPWL: 181807193                                                       \n",
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[NesterovSolve] Iter: 250 overflow: 0.835995 HPWL: 202593853                                                       \n",
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[NesterovSolve] Iter: 260 overflow: 0.803505 HPWL: 223871627                                                       \n",
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[INFO GPL-0100] worst slack 4.29e-10                                                                               \n",
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[INFO GPL-0103] Weighted 1313 nets.                                                                                \n",
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[NesterovSolve] Iter: 270 overflow: 0.770268 HPWL: 242870779                                                       \n",
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[NesterovSolve] Iter: 280 overflow: 0.736384 HPWL: 255680277                                                       \n",
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[NesterovSolve] Iter: 290 overflow: 0.696044 HPWL: 267467910                                                       \n",
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[NesterovSolve] Iter: 300 overflow: 0.654669 HPWL: 275908511                                                       \n",
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[INFO GPL-0100] worst slack -2.24e-10                                                                              \n",
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[INFO GPL-0103] Weighted 1311 nets.                                                                                \n",
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[NesterovSolve] Iter: 310 overflow: 0.608917 HPWL: 287315803                                                       \n",
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[NesterovSolve] Snapshot saved at iter = 312                                                                       \n",
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[NesterovSolve] Iter: 320 overflow: 0.561677 HPWL: 298559425                                                       \n",
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[NesterovSolve] Iter: 330 overflow: 0.508367 HPWL: 308748658                                                       \n",
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[INFO GPL-0100] worst slack -4.75e-10                                                                              \n",
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[INFO GPL-0103] Weighted 1310 nets.                                                                                \n",
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[NesterovSolve] Iter: 340 overflow: 0.456332 HPWL: 313513702                                                       \n",
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[NesterovSolve] Iter: 350 overflow: 0.400083 HPWL: 314463516                                                       \n",
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[NesterovSolve] Iter: 360 overflow: 0.357077 HPWL: 317671462                                                       \n",
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[NesterovSolve] Iter: 370 overflow: 0.313692 HPWL: 321146407                                                       \n",
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[NesterovSolve] Iter: 380 overflow: 0.281054 HPWL: 322427693                                                       \n",
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[INFO GPL-0100] worst slack -4.34e-10                                                                              \n",
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[INFO GPL-0103] Weighted 1310 nets.                                                                                \n",
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[NesterovSolve] Iter: 390 overflow: 0.24796 HPWL: 324273727                                                        \n",
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[NesterovSolve] Iter: 400 overflow: 0.216412 HPWL: 326450196                                                       \n",
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[INFO GPL-0100] worst slack -5.32e-10                                                                              \n",
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[INFO GPL-0103] Weighted 1313 nets.                                                                                \n",
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[INFO GPL-0036] TileLxLy: 0 0                                                                                      \n",
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[INFO GPL-0037] TileSize: 6900 6900                                                                                \n",
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[INFO GPL-0038] TileCnt: 83 84                                                                                     \n",
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[INFO GPL-0040] NumTiles: 6972                                                                                     \n",
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[INFO GPL-0063] TotalRouteOverflowH2: 15.600001692771912                                                           \n",
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[INFO GPL-0064] TotalRouteOverflowV2: 85.90000522136688                                                            \n",
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[INFO GPL-0065] OverflowTileCnt2: 535                                                                              \n",
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[INFO GPL-0066] 0.5%RC: 1.4082125822703044                                                                         \n",
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[INFO GPL-0067] 1.0%RC: 1.335024172845094                                                                          \n",
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[INFO GPL-0068] 2.0%RC: 1.252294685529626                                                                          \n",
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[INFO GPL-0074] FinalRC: 1.3716184                                                                                 \n",
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[INFO GPL-0045] InflatedAreaDelta: 17075643176                                                                     \n",
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[INFO GPL-0046] TargetDensity: 0.619378                                                                            \n",
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[INFO GPL-0049] WhiteSpaceArea: 307567481600                                                                       \n",
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[INFO GPL-0050] NesterovInstsArea: 157857648000                                                                    \n",
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[INFO GPL-0051] TotalFillerArea: 32642888320                                                                       \n",
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[INFO GPL-0052] TotalGCellsArea: 190500536320                                                                      \n",
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[INFO GPL-0053] ExpectedTotalGCellsArea: 207576179496                                                              \n",
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[INFO GPL-0054] NewTargetDensity: 0.67489636                                                                       \n",
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[INFO GPL-0055] NewWhiteSpaceArea: 307567481600                                                                    \n",
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[INFO GPL-0056] MovableArea: 207576186880                                                                          \n",
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[INFO GPL-0057] NewNesterovInstsArea: 174933291176                                                                 \n",
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[INFO GPL-0058] NewTotalFillerArea: 32642895704                                                                    \n",
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[INFO GPL-0059] NewTotalGCellsArea: 207576186880                                                                   \n",
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[NesterovSolve] Revert back to snapshot coordi                                                                     \n",
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[NesterovSolve] Iter: 410 overflow: 0.583843 HPWL: 299858264                                                       \n",
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[NesterovSolve] Iter: 420 overflow: 0.525353 HPWL: 321033880                                                       \n",
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[NesterovSolve] Iter: 430 overflow: 0.494203 HPWL: 327537988                                                       \n",
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[NesterovSolve] Iter: 440 overflow: 0.443628 HPWL: 325828671                                                       \n",
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[NesterovSolve] Iter: 450 overflow: 0.40703 HPWL: 323199714                                                        \n",
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[NesterovSolve] Iter: 460 overflow: 0.366874 HPWL: 326601211                                                       \n",
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[NesterovSolve] Iter: 470 overflow: 0.329517 HPWL: 328709275                                                       \n",
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[NesterovSolve] Iter: 480 overflow: 0.288525 HPWL: 330952718                                                       \n",
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[NesterovSolve] Iter: 490 overflow: 0.260241 HPWL: 332197076                                                       \n",
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[NesterovSolve] Iter: 500 overflow: 0.233123 HPWL: 334260873                                                       \n",
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[NesterovSolve] Iter: 510 overflow: 0.206634 HPWL: 334627959                                                       \n",
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[INFO GPL-0075] Routability numCall: 2 inflationIterCnt: 2 bloatIterCnt: 0                                         \n",
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[INFO GPL-0036] TileLxLy: 0 0                                                                                      \n",
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[INFO GPL-0037] TileSize: 6900 6900                                                                                \n",
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[INFO GPL-0038] TileCnt: 83 84                                                                                     \n",
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[INFO GPL-0039] numRoutingLayers: 6                                                                                \n",
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[INFO GPL-0040] NumTiles: 6972                                                                                     \n",
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[INFO GPL-0063] TotalRouteOverflowH2: 11.000000596046448                                                           \n",
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[INFO GPL-0064] TotalRouteOverflowV2: 44.533337235450745                                                           \n",
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[INFO GPL-0066] 0.5%RC: 1.2884058192156362                                                                         \n",
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[INFO GPL-0067] 1.0%RC: 1.2275362230729365                                                                         \n",
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[INFO GPL-0068] 2.0%RC: 1.1589372101901234                                                                         \n",
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[INFO GPL-0069] 5.0%RC: 1.064541068457175                                                                          \n",
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[INFO GPL-0074] FinalRC: 1.257971                                                                                  \n",
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[INFO GPL-0045] InflatedAreaDelta: 12603393084                                                                     \n",
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[INFO GPL-0046] TargetDensity: 0.67489636                                                                          \n",
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[INFO GPL-0049] WhiteSpaceArea: 307567481600                                                                       \n",
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[INFO GPL-0050] NesterovInstsArea: 174933291176                                                                    \n",
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[INFO GPL-0051] TotalFillerArea: 32642895704                                                                       \n",
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[INFO GPL-0052] TotalGCellsArea: 207576186880                                                                      \n",
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[INFO GPL-0053] ExpectedTotalGCellsArea: 220179579964                                                              \n",
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[INFO GPL-0054] NewTargetDensity: 0.715874                                                                         \n",
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[INFO GPL-0055] NewWhiteSpaceArea: 307567481600                                                                    \n",
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[INFO GPL-0056] MovableArea: 220179578880                                                                          \n",
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[INFO GPL-0057] NewNesterovInstsArea: 187536684260                                                                 \n",
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[INFO GPL-0058] NewTotalFillerArea: 32642894620                                                                    \n",
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[INFO GPL-0059] NewTotalGCellsArea: 220179578880                                                                   \n",
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[NesterovSolve] Revert back to snapshot coordi                                                                     \n",
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[NesterovSolve] Iter: 520 overflow: 0.543294 HPWL: 321137213                                                       \n",
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[NesterovSolve] Iter: 530 overflow: 0.508546 HPWL: 332518391                                                       \n",
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[NesterovSolve] Iter: 540 overflow: 0.464505 HPWL: 336029309                                                       \n",
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[NesterovSolve] Iter: 550 overflow: 0.425704 HPWL: 332221610                                                       \n",
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[NesterovSolve] Iter: 560 overflow: 0.391016 HPWL: 332749196                                                       \n",
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[NesterovSolve] Iter: 570 overflow: 0.342891 HPWL: 338076670                                                       \n",
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[NesterovSolve] Iter: 580 overflow: 0.309157 HPWL: 339297368                                                       \n",
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[NesterovSolve] Iter: 590 overflow: 0.275884 HPWL: 339898404                                                       \n",
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[NesterovSolve] Iter: 600 overflow: 0.247855 HPWL: 342267930                                                       \n",
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[NesterovSolve] Iter: 610 overflow: 0.217557 HPWL: 343206357                                                       \n",
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[INFO GPL-0036] TileLxLy: 0 0                                                                                      \n",
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[INFO GPL-0037] TileSize: 6900 6900                                                                                \n",
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[INFO GPL-0038] TileCnt: 83 84                                                                                     \n",
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[INFO GPL-0039] numRoutingLayers: 6                                                                                \n",
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[INFO GPL-0040] NumTiles: 6972                                                                                     \n",
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[INFO GPL-0063] TotalRouteOverflowH2: 10.000000715255737                                                           \n",
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[INFO GPL-0064] TotalRouteOverflowV2: 30.93333637714386                                                            \n",
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[INFO GPL-0065] OverflowTileCnt2: 254                                                                              \n",
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[INFO GPL-0066] 0.5%RC: 1.257487922474958                                                                          \n",
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[INFO GPL-0067] 1.0%RC: 1.194202895613684                                                                          \n",
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[INFO GPL-0068] 2.0%RC: 1.1120773057142894                                                                         \n",
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[INFO GPL-0069] 5.0%RC: 1.0448309222857157                                                                         \n",
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[INFO GPL-0074] FinalRC: 1.2258455                                                                                 \n",
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[NesterovSolve] Iter: 620 overflow: 0.191039 HPWL: 343616869                                                       \n",
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[NesterovSolve] Iter: 630 overflow: 0.165627 HPWL: 343490051                                                       \n",
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[INFO GPL-0100] worst slack -4.15e-10                                                                              \n",
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[NesterovSolve] Iter: 640 overflow: 0.142596 HPWL: 343486288                                                       \n",
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[NesterovSolve] Iter: 650 overflow: 0.123887 HPWL: 343755954                                                       \n",
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[NesterovSolve] Iter: 660 overflow: 0.10255 HPWL: 344020493                                                        \n",
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[NesterovSolve] Finished with Overflow: 0.098310                                                                   \n",
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[INFO] Setting RC values…                                                                                          \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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─────────────────────────────────────────────── Detailed Placement ────────────────────────────────────────────────\n",
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[11:23:27] VERBOSE  Running 'OpenROAD.DetailedPlacement'(Log:                                        step.py:1085\n",
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Reading design constraints file at '/content/openlane_ipynb/openlane/scripts/base.sdc'…                            \n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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Placement Analysis                                                                                                 \n",
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total displacement      47580.7 u                                                                                  \n",
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average displacement        2.6 u                                                                                  \n",
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max displacement           14.2 u                                                                                  \n",
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original HPWL          344202.5 u                                                                                  \n",
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legalized HPWL         396857.5 u                                                                                  \n",
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delta HPWL                   15 %                                                                                  \n",
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[INFO DPL-0020] Mirrored 4346 instances                                                                            \n",
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[INFO DPL-0021] HPWL before          396857.5 u                                                                    \n",
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[INFO DPL-0022] HPWL after           387742.4 u                                                                    \n",
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[INFO DPL-0023] HPWL delta               -2.3 %                                                                    \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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────────────────────────────────────────────── Clock Tree Synthesis ───────────────────────────────────────────────\n",
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[11:23:42] VERBOSE  Running 'OpenROAD.CTS'(Log: ./openlane_run/8-openroad-cts/openroad-cts.log)      step.py:1085\n",
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Reading timing models for corner nom_tt_025C_1v80…                                                                 \n",
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Reading timing library for the 'nom_tt_025C_1v80' corner at                                                        \n",
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Reading timing models for corner nom_ff_n40C_1v95…                                                                 \n",
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Reading timing library for the 'nom_ff_n40C_1v95' corner at                                                        \n",
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Reading timing models for corner nom_ss_100C_1v60…                                                                 \n",
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Reading timing library for the 'nom_ss_100C_1v60' corner at                                                        \n",
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Reading OpenROAD database at '/content/openlane_run/7-openroad-detailedplacement/core.odb'…                        \n",
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Reading design constraints file at '/content/openlane_ipynb/openlane/scripts/base.sdc'…                            \n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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[INFO] Setting RC values…                                                                                          \n",
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[INFO] Configuring cts characterization…                                                                           \n",
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[INFO] Performing clock tree synthesis…                                                                            \n",
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[INFO] Looking for the following net(s): clock                                                                     \n",
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[INFO] Running Clock Tree Synthesis…                                                                               \n",
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[INFO CTS-0050] Root buffer is sky130_fd_sc_hd__clkbuf_16.                                                         \n",
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[INFO CTS-0051] Sink buffer is sky130_fd_sc_hd__clkbuf_8.                                                          \n",
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[INFO CTS-0052] The following clock buffers will be used for CTS:                                                  \n",
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sky130_fd_sc_hd__clkbuf_2                                                                                          \n",
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sky130_fd_sc_hd__clkbuf_4                                                                                          \n",
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sky130_fd_sc_hd__clkbuf_8                                                                                          \n",
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[INFO CTS-0049] Characterization buffer is sky130_fd_sc_hd__clkbuf_8.                                              \n",
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[INFO CTS-0007] Net \"clock\" found for clock \"clock\".                                                               \n",
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[INFO CTS-0010]  Clock net \"clock\" has 2955 sinks.                                                                 \n",
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[INFO CTS-0008] TritonCTS found 1 clock nets.                                                                      \n",
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[INFO CTS-0097] Characterization used 3 buffer(s) types.                                                           \n",
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[INFO CTS-0200] 0 placement blockages have been identified.                                                        \n",
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[INFO CTS-0201] 0 placed hard macros will be treated like blockages.                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO CTS-\u001b[1;36m0027\u001b[0m\u001b[1m]\u001b[0m Generating H-Tree topology for net clock. \n" + ], + "text/html": [ + "
[INFO CTS-0027] Generating H-Tree topology for net clock.                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO CTS-\u001b[1;36m0028\u001b[0m\u001b[1m]\u001b[0m Total number of sinks: \u001b[1;36m2955\u001b[0m. \n" + ], + "text/html": [ + "
[INFO CTS-0028]  Total number of sinks: 2955.                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO CTS-\u001b[1;36m0029\u001b[0m\u001b[1m]\u001b[0m Sinks will be clustered in groups of up to \u001b[1;36m25\u001b[0m and with maximum cluster diameter of \u001b[1;36m50.0\u001b[0m um. \n" + ], + "text/html": [ + "
[INFO CTS-0029]  Sinks will be clustered in groups of up to 25 and with maximum cluster diameter of 50.0 um.       \n",
+              "
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[INFO CTS-0030]  Number of static layers: 0.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO CTS-\u001b[1;36m0020\u001b[0m\u001b[1m]\u001b[0m Wire segment unit: \u001b[1;36m13600\u001b[0m dbu \u001b[1m(\u001b[0m\u001b[1;36m13\u001b[0m um\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
[INFO CTS-0020]  Wire segment unit: 13600  dbu (13 um).                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO CTS-\u001b[1;36m0204\u001b[0m\u001b[1m]\u001b[0m A clustering solution was found from clustering size of \u001b[1;36m25\u001b[0m and clustering diameter of \u001b[1;36m50\u001b[0m. \n" + ], + "text/html": [ + "
[INFO CTS-0204] A clustering solution was found from clustering size of 25 and clustering diameter of 50.          \n",
+              "
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[INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or \n",
+              "both options are omitted to enable automatic clustering.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO CTS-\u001b[1;36m0019\u001b[0m\u001b[1m]\u001b[0m Total number of sinks after clustering: \u001b[1;36m308\u001b[0m. \n" + ], + "text/html": [ + "
[INFO CTS-0019]  Total number of sinks after clustering: 308.                                                      \n",
+              "
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[INFO CTS-0024]  Normalized sink region: [(0.95541, 1.47729), (41.2259, 41.3522)].                                 \n",
+              "
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[INFO CTS-0025]     Width:  40.2705.                                                                               \n",
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[INFO CTS-0026]     Height: 39.8749.                                                                               \n",
+              "
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Level 1                                                                                                            \n",
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Direction: Horizontal                                                                                              \n",
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Sinks per sub-region: 154                                                                                          \n",
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Sub-region size: 20.1352 X 39.8749                                                                                 \n",
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[INFO CTS-0034]     Segment length (rounded): 10.                                                                  \n",
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Level 2                                                                                                            \n",
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Direction: Vertical                                                                                                \n",
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Sinks per sub-region: 77                                                                                           \n",
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Sub-region size: 20.1352 X 19.9375                                                                                 \n",
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[INFO CTS-0034]     Segment length (rounded): 10.                                                                  \n",
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Level 3                                                                                                            \n",
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Direction: Horizontal                                                                                              \n",
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Sinks per sub-region: 39                                                                                           \n",
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Sub-region size: 10.0676 X 19.9375                                                                                 \n",
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[INFO CTS-0034]     Segment length (rounded): 6.                                                                   \n",
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Level 4                                                                                                            \n",
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Direction: Vertical                                                                                                \n",
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Sinks per sub-region: 20                                                                                           \n",
+              "
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Sub-region size: 10.0676 X 9.9687                                                                                  \n",
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[INFO CTS-0034]     Segment length (rounded): 4.                                                                   \n",
+              "
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Level 5                                                                                                            \n",
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Direction: Horizontal                                                                                              \n",
+              "
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Sinks per sub-region: 10                                                                                           \n",
+              "
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Sub-region size: 5.0338 X 9.9687                                                                                   \n",
+              "
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[INFO CTS-0034]     Segment length (rounded): 2.                                                                   \n",
+              "
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[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.                                                  \n",
+              "
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[INFO CTS-0035]  Number of sinks covered: 308.                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO CTS-\u001b[1;36m0018\u001b[0m\u001b[1m]\u001b[0m Created \u001b[1;36m342\u001b[0m clock buffers. \n" + ], + "text/html": [ + "
[INFO CTS-0018]     Created 342 clock buffers.                                                                     \n",
+              "
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[INFO CTS-0012]     Minimum number of buffers in the clock path: 3.                                                \n",
+              "
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[INFO CTS-0013]     Maximum number of buffers in the clock path: 4.                                                \n",
+              "
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[INFO CTS-0015]     Created 342 clock nets.                                                                        \n",
+              "
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[INFO CTS-0016]     Fanout distribution for the current clock = 2:1, 3:6, 4:11, 5:14, 6:29, 7:38, 8:42, 9:42,      \n",
+              "10:34, 11:27, 12:22, 13:20, 14:18, 15:9, 16:5, 17:11, 18:3, 19:1, 20:2, 21:1, 23:1..                               \n",
+              "
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[INFO CTS-0017]     Max level of the clock tree: 5.                                                                \n",
+              "
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[INFO CTS-0098] Clock net \"clock\"                                                                                  \n",
+              "
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[INFO CTS-0099]  Sinks 2955                                                                                        \n",
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[INFO CTS-0100]  Leaf buffers 305                                                                                  \n",
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[INFO CTS-0101]  Average sink wire length 1000.16 um                                                               \n",
+              "
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[INFO CTS-0102]  Path depth 3 - 4                                                                                  \n",
+              "
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[INFO] Repairing long wires on clock nets…                                                                         \n",
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[INFO RSZ-0058] Using max wire length 4459um.                                                                      \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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[INFO] Legalizing…                                                                                                 \n",
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Placement Analysis                                                                                                 \n",
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[INFO DPL-0023] HPWL delta               -2.5 %                                                                    \n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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-congestion_iterations 50 -verbose                                                                                 \n",
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[INFO GRT-0020] Min routing layer: met1                                                                            \n",
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[INFO GRT-0021] Max routing layer: met5                                                                            \n",
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[INFO GRT-0022] Global adjustment: 30%                                                                             \n",
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[INFO GRT-0023] Grid origin: (0, 0)                                                                                \n",
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[INFO GRT-0088] Layer li1     Track-Pitch = 0.4600  line-2-Via Pitch: 0.3400                                       \n",
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[INFO GRT-0088] Layer met1    Track-Pitch = 0.3400  line-2-Via Pitch: 0.3400                                       \n",
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[INFO GRT-0088] Layer met2    Track-Pitch = 0.4600  line-2-Via Pitch: 0.3500                                       \n",
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[INFO GRT-0088] Layer met3    Track-Pitch = 0.6800  line-2-Via Pitch: 0.6150                                       \n",
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[INFO GRT-0019] Found 343 clock nets.                                                                              \n",
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[INFO GRT-0001] Minimum degree: 2                                                                                  \n",
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[INFO GRT-0002] Maximum degree: 1387                                                                               \n",
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[INFO GRT-0003] Macros: 0                                                                                          \n",
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[INFO GRT-0004] Blockages: 44895                                                                                   \n",
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[INFO GRT-0053] Routing resources analysis:                                                                        \n",
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Routing      Original      Derated      Resource                                                                   \n",
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---------------------------------------------------------------                                                    \n",
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li1        Vertical            0             0          0.00%                                                      \n",
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met4       Vertical        41922         26341          37.17%                                                     \n",
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met5       Horizontal      14025          6642          52.64%                                                     \n",
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[INFO GRT-0101] Running extra iterations to remove overflow.                                                       \n",
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[INFO GRT-0197] Via related to pin nodes: 90816                                                                    \n",
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[INFO GRT-0198] Via related Steiner nodes: 2660                                                                    \n",
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[INFO GRT-0199] Via filling finished.                                                                              \n",
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[INFO GRT-0111] Final number of vias: 116776                                                                       \n",
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[INFO GRT-0112] Final usage 3D: 430310                                                                             \n",
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[INFO GRT-0096] Final congestion report:                                                                           \n",
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[INFO GRT-0018] Total wirelength: 841910 um                                                                        \n",
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[INFO GRT-0014] Routed nets: 13480                                                                                 \n",
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[INFO] Setting RC values…                                                                                          \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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Writing layout to '/content/openlane_run/9-openroad-globalrouting/core.def'…                                       \n",
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[11:30:58] VERBOSE  Running 'OpenROAD.DetailedRouting'(Log:                                          step.py:1085\n",
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[11:30:58] INFO     Running TritonRoute with 2 threads…                                            openroad.py:1529\n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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[INFO ORD-0030] Using 2 thread(s).                                                                                 \n",
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[INFO DRT-0149] Reading tech and libs.                                                                             \n",
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Units:                1000                                                                                         \n",
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Number of layers:     13                                                                                           \n",
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Number of macros:     441                                                                                          \n",
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Number of vias:       25                                                                                           \n",
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Number of viarulegen: 25                                                                                           \n",
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[INFO DRT-0150] Reading design.                                                                                    \n",
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Design:                   core                                                                                     \n",
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Die area:                 ( 0 0 ) ( 572925 583645 )                                                                \n",
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Number of track patterns: 12                                                                                       \n",
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Number of DEF vias:       0                                                                                        \n",
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Number of components:     18297                                                                                    \n",
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Number of terminals:      170                                                                                      \n",
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Number of snets:          2                                                                                        \n",
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Number of nets:           13480                                                                                    \n",
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[INFO DRT-0167] List of default vias:                                                                              \n",
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Layer via                                                                                                          \n",
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default via: M1M2_PR                                                                                               \n",
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Layer via2                                                                                                         \n",
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default via: M2M3_PR                                                                                               \n",
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Layer via3                                                                                                         \n",
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default via: M3M4_PR                                                                                               \n",
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Layer via4                                                                                                         \n",
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default via: M4M5_PR                                                                                               \n",
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[INFO DRT-0162] Library cell analysis.                                                                             \n",
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[INFO DRT-0163] Instance analysis.                                                                                 \n",
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Complete 10000 instances.                                                                                          \n",
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[INFO DRT-0164] Number of unique instances = 243.                                                                  \n",
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[INFO DRT-0168] Init region query.                                                                                 \n",
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[INFO DRT-0018]   Complete 10000 insts.                                                                            \n",
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[INFO DRT-0024]   Complete FR_MASTERSLICE.                                                                         \n",
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[INFO DRT-0024]   Complete Fr_VIA.                                                                                 \n",
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[INFO DRT-0024]   Complete li1.                                                                                    \n",
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[INFO DRT-0024]   Complete mcon.                                                                                   \n",
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[INFO DRT-0024]   Complete met1.                                                                                   \n",
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[INFO DRT-0024]   Complete via.                                                                                    \n",
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[INFO DRT-0024]   Complete met2.                                                                                   \n",
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[INFO DRT-0024]   Complete via2.                                                                                   \n",
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[INFO DRT-0024]   Complete met3.                                                                                   \n",
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[INFO DRT-0024]   Complete via3.                                                                                   \n",
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[INFO DRT-0024]   Complete met4.                                                                                   \n",
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[INFO DRT-0024]   Complete via4.                                                                                   \n",
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[INFO DRT-0024]   Complete met5.                                                                                   \n",
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[INFO DRT-0033] li1 shape region query size = 488278.                                                              \n",
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[INFO DRT-0033] mcon shape region query size = 291598.                                                             \n",
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[INFO DRT-0033] met2 shape region query size = 2484.                                                               \n",
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[INFO DRT-0033] via2 shape region query size = 3312.                                                               \n",
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[INFO DRT-0033] met3 shape region query size = 2652.                                                               \n",
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[INFO DRT-0033] via3 shape region query size = 3312.                                                               \n",
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[INFO DRT-0033] met4 shape region query size = 876.                                                                \n",
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[INFO DRT-0033] via4 shape region query size = 32.                                                                 \n",
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[INFO DRT-0033] met5 shape region query size = 48.                                                                 \n",
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[INFO DRT-0165] Start pin access.                                                                                  \n",
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[INFO DRT-0076]   Complete 100 pins.                                                                               \n",
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[INFO DRT-0076]   Complete 200 pins.                                                                               \n",
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[INFO DRT-0076]   Complete 300 pins.                                                                               \n",
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[INFO DRT-0076]   Complete 400 pins.                                                                               \n",
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[INFO DRT-0076]   Complete 500 pins.                                                                               \n",
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[INFO DRT-0076]   Complete 600 pins.                                                                               \n",
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[INFO DRT-0076]   Complete 700 pins.                                                                               \n",
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[INFO DRT-0076]   Complete 800 pins.                                                                               \n",
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[INFO DRT-0076]   Complete 900 pins.                                                                               \n",
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[INFO DRT-0077]   Complete 1000 pins.                                                                              \n",
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[INFO DRT-0078]   Complete 1062 pins.                                                                              \n",
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[INFO DRT-0079]   Complete 100 unique inst patterns.                                                               \n",
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[INFO DRT-0079]   Complete 200 unique inst patterns.                                                               \n",
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[INFO DRT-0081]   Complete 237 unique inst patterns.                                                               \n",
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[INFO DRT-0082]   Complete 1000 groups.                                                                            \n",
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[INFO DRT-0082]   Complete 2000 groups.                                                                            \n",
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[INFO DRT-0082]   Complete 3000 groups.                                                                            \n",
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[INFO DRT-0082]   Complete 4000 groups.                                                                            \n",
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[INFO DRT-0082]   Complete 5000 groups.                                                                            \n",
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[INFO DRT-0082]   Complete 6000 groups.                                                                            \n",
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[INFO DRT-0082]   Complete 7000 groups.                                                                            \n",
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[INFO DRT-0082]   Complete 8000 groups.                                                                            \n",
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[INFO DRT-0084]   Complete 8025 groups.                                                                            \n",
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#scanned instances     = 18297                                                                                     \n",
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#unique  instances     = 243                                                                                       \n",
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#stdCellGenAp          = 7449                                                                                      \n",
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#stdCellValidPlanarAp  = 84                                                                                        \n",
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#stdCellValidViaAp     = 5862                                                                                      \n",
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#stdCellPinNoAp        = 0                                                                                         \n",
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#stdCellPinCnt         = 51335                                                                                     \n",
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#instTermValidViaApCnt = 0                                                                                         \n",
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#macroValidPlanarAp    = 0                                                                                         \n",
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#macroValidViaAp       = 0                                                                                         \n",
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[INFO DRT-0156] guideIn read 100000 guides.                                                                        \n",
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[INFO DRT-0176] GCELLGRID X 0 DO 83 STEP 6900 ;                                                                    \n",
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[INFO DRT-0027]   Complete 100000 origin guides.                                                                   \n",
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[INFO DRT-0028]   Complete FR_MASTERSLICE.                                                                         \n",
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[INFO DRT-0028]   Complete Fr_VIA.                                                                                 \n",
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[INFO DRT-0028]   Complete li1.                                                                                    \n",
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[INFO DRT-0028]   Complete mcon.                                                                                   \n",
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[INFO DRT-0028]   Complete met1.                                                                                   \n",
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[INFO DRT-0028]   Complete via.                                                                                    \n",
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[INFO DRT-0028]   Complete met2.                                                                                   \n",
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[INFO DRT-0028]   Complete via2.                                                                                   \n",
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[INFO DRT-0028]   Complete met3.                                                                                   \n",
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[INFO DRT-0028]   Complete via3.                                                                                   \n",
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[INFO DRT-0028]   Complete met4.                                                                                   \n",
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[INFO DRT-0028]   Complete via4.                                                                                   \n",
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[INFO DRT-0028]   Complete met5.                                                                                   \n",
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[INFO DRT-0178] Init guide query.                                                                                  \n",
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[INFO DRT-0029]   Complete 10000 nets (guide).                                                                     \n",
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[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).                                                                 \n",
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[INFO DRT-0035]   Complete Fr_VIA (guide).                                                                         \n",
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[INFO DRT-0035]   Complete li1 (guide).                                                                            \n",
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[INFO DRT-0035]   Complete mcon (guide).                                                                           \n",
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[INFO DRT-0035]   Complete met1 (guide).                                                                           \n",
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[INFO DRT-0035]   Complete via (guide).                                                                            \n",
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[INFO DRT-0035]   Complete met2 (guide).                                                                           \n",
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[INFO DRT-0035]   Complete via2 (guide).                                                                           \n",
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[INFO DRT-0035]   Complete met3 (guide).                                                                           \n",
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[INFO DRT-0035]   Complete via3 (guide).                                                                           \n",
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[INFO DRT-0035]   Complete met4 (guide).                                                                           \n",
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[INFO DRT-0035]   Complete via4 (guide).                                                                           \n",
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[INFO DRT-0035]   Complete met5 (guide).                                                                           \n",
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[INFO DRT-0036] met1 guide region query size = 34826.                                                              \n",
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[INFO DRT-0036] via guide region query size = 0.                                                                   \n",
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[INFO DRT-0036] met2 guide region query size = 19467.                                                              \n",
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[INFO DRT-0036] via2 guide region query size = 0.                                                                  \n",
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[INFO DRT-0036] met3 guide region query size = 1847.                                                               \n",
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[INFO DRT-0036] via3 guide region query size = 0.                                                                  \n",
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[INFO DRT-0036] met4 guide region query size = 578.                                                                \n",
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[INFO DRT-0036] via4 guide region query size = 0.                                                                  \n",
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[INFO DRT-0036] met5 guide region query size = 0.                                                                  \n",
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[INFO DRT-0179] Init gr pin query.                                                                                 \n",
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[INFO DRT-0245] skipped writing guide updates to database.                                                         \n",
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[INFO DRT-0185] Post process initialize RPin region query.                                                         \n",
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[INFO DRT-0181] Start track assignment.                                                                            \n",
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[INFO DRT-0182] Complete track assignment.                                                                         \n",
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[INFO DRT-0187] Start routing data preparation.                                                                    \n",
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[INFO DRT-0194] Start detail routing.                                                                              \n",
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[INFO DRT-0195] Start 0th optimization iteration.                                                                  \n",
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Completing 10% with 0 violations.                                                                                  \n",
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elapsed time = 00:01:23, memory = 554.65 (MB).                                                                     \n",
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Completing 20% with 0 violations.                                                                                  \n",
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elapsed time = 00:02:49, memory = 708.04 (MB).                                                                     \n",
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Completing 30% with 2572 violations.                                                                               \n",
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elapsed time = 00:04:32, memory = 812.70 (MB).                                                                     \n",
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Completing 40% with 2572 violations.                                                                               \n",
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elapsed time = 00:05:54, memory = 840.29 (MB).                                                                     \n",
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Completing 50% with 2572 violations.                                                                               \n",
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elapsed time = 00:08:26, memory = 836.10 (MB).                                                                     \n",
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Completing 60% with 5513 violations.                                                                               \n",
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elapsed time = 00:10:09, memory = 840.73 (MB).                                                                     \n",
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Completing 70% with 5513 violations.                                                                               \n",
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elapsed time = 00:12:09, memory = 842.80 (MB).                                                                     \n",
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Completing 80% with 8159 violations.                                                                               \n",
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elapsed time = 00:14:44, memory = 866.26 (MB).                                                                     \n",
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Completing 90% with 8159 violations.                                                                               \n",
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elapsed time = 00:16:41, memory = 866.26 (MB).                                                                     \n",
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Completing 100% with 11131 violations.                                                                             \n",
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elapsed time = 00:18:58, memory = 873.99 (MB).                                                                     \n",
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[INFO DRT-0199]   Number of violations = 19636.                                                                    \n",
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Viol/Layer         li1   mcon   met1    via   met2   via2   met3   met4                                            \n",
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Cut Spacing          0     22      0      0      0      1      0      0                                            \n",
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Metal Spacing      118      0   2416      0    323      0     76      0                                            \n",
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Min Hole             0      0      7      0      0      0      0      0                                            \n",
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NS Metal             3      0      2      0      0      0      0      0                                            \n",
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Recheck              1      0   5856      0   2428      0    197     23                                            \n",
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Short                0      0   7414      1    738      0      9      1                                            \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0267\u001b[0m\u001b[1m]\u001b[0m cpu time = \u001b[1;92m00:31:34\u001b[0m, elapsed time = \u001b[1;92m00:19:00\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m, peak = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
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+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length = \u001b[1;36m589106\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length = 589106 um.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER li1 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER li1 = 0 um.                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met1 = \u001b[1;36m251236\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met1 = 251236 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met2 = \u001b[1;36m250303\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met2 = 250303 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met3 = \u001b[1;36m52875\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met3 = 52875 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met4 = \u001b[1;36m34690\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met4 = 34690 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met5 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met5 = 0 um.                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total number of vias = \u001b[1;36m115035\u001b[0m. \n" + ], + "text/html": [ + "
Total number of vias = 115035.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Up-via summary \u001b[1m(\u001b[0mtotal \u001b[1;36m115035\u001b[0m\u001b[1m)\u001b[0m:. \n" + ], + "text/html": [ + "
Up-via summary (total 115035):.                                                                                    \n",
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                                                                                                                   \n",
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-------------------------                                                                                          \n",
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FR_MASTERSLICE         0                                                                                           \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "li1 \u001b[1;36m51109\u001b[0m \n" + ], + "text/html": [ + "
li1     51109                                                                                                      \n",
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met1     59873                                                                                                     \n",
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met2      3060                                                                                                     \n",
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met3       993                                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "met4 \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
met4         0                                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "------------------------- \n" + ], + "text/html": [ + "
-------------------------                                                                                          \n",
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115035                                                                                                             \n",
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                                                                                                                   \n",
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                                                                                                                   \n",
+              "
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[INFO DRT-0195] Start 1st optimization iteration.                                                                  \n",
+              "
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Completing 10% with 19636 violations.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:57\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:57, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m20\u001b[0m% with \u001b[1;36m19636\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 20% with 19636 violations.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:02:39\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:02:39, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m30\u001b[0m% with \u001b[1;36m16398\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 30% with 16398 violations.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:03:26\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:03:26, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m40\u001b[0m% with \u001b[1;36m16398\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 40% with 16398 violations.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:04:52\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:04:52, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m50\u001b[0m% with \u001b[1;36m16398\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 50% with 16398 violations.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:06:37\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:06:37, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m60\u001b[0m% with \u001b[1;36m13532\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 60% with 13532 violations.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:07:49\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:07:49, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m70\u001b[0m% with \u001b[1;36m13532\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 70% with 13532 violations.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:09:28\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:09:28, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m80\u001b[0m% with \u001b[1;36m9979\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 80% with 9979 violations.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:11:09\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:11:09, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m90\u001b[0m% with \u001b[1;36m9979\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 90% with 9979 violations.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:12:51\u001b[0m, memory = \u001b[1;36m959.64\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:12:51, memory = 959.64 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m100\u001b[0m% with \u001b[1;36m6562\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 100% with 6562 violations.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:14:58\u001b[0m, memory = \u001b[1;36m961.19\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:14:58, memory = 961.19 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0199\u001b[0m\u001b[1m]\u001b[0m Number of violations = \u001b[1;36m6581\u001b[0m. \n" + ], + "text/html": [ + "
[INFO DRT-0199]   Number of violations = 6581.                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Viol/Layer mcon met1 via met2 met3 met4 \n" + ], + "text/html": [ + "
Viol/Layer        mcon   met1    via   met2   met3   met4                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Cut Spacing \u001b[1;36m6\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
Cut Spacing          6      0      0      0      0      0                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Metal Spacing \u001b[1;36m0\u001b[0m \u001b[1;36m1304\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m202\u001b[0m \u001b[1;36m22\u001b[0m \u001b[1;36m2\u001b[0m \n" + ], + "text/html": [ + "
Metal Spacing        0   1304      0    202     22      2                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Min Hole \u001b[1;36m0\u001b[0m \u001b[1;36m2\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
Min Hole             0      2      0      0      0      0                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "NS Metal \u001b[1;36m0\u001b[0m \u001b[1;36m1\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
NS Metal             0      1      0      0      0      0                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Recheck \u001b[1;36m0\u001b[0m \u001b[1;36m13\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m5\u001b[0m \u001b[1;36m1\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
Recheck              0     13      0      5      1      0                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Short \u001b[1;36m0\u001b[0m \u001b[1;36m4619\u001b[0m \u001b[1;36m1\u001b[0m \u001b[1;36m402\u001b[0m \u001b[1;36m1\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
Short                0   4619      1    402      1      0                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0267\u001b[0m\u001b[1m]\u001b[0m cpu time = \u001b[1;92m00:24:46\u001b[0m, elapsed time = \u001b[1;92m00:15:00\u001b[0m, memory = \u001b[1;36m961.19\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m, peak = \u001b[1;36m961.19\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
[INFO DRT-0267] cpu time = 00:24:46, elapsed time = 00:15:00, memory = 961.19 (MB), peak = 961.19 (MB)             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length = \u001b[1;36m583896\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length = 583896 um.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER li1 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER li1 = 0 um.                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met1 = \u001b[1;36m248526\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met1 = 248526 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met2 = \u001b[1;36m248279\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met2 = 248279 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met3 = \u001b[1;36m52868\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met3 = 52868 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met4 = \u001b[1;36m34222\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met4 = 34222 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met5 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met5 = 0 um.                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total number of vias = \u001b[1;36m114639\u001b[0m. \n" + ], + "text/html": [ + "
Total number of vias = 114639.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Up-via summary \u001b[1m(\u001b[0mtotal \u001b[1;36m114639\u001b[0m\u001b[1m)\u001b[0m:. \n" + ], + "text/html": [ + "
Up-via summary (total 114639):.                                                                                    \n",
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FR_MASTERSLICE         0                                                                                           \n",
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li1     51096                                                                                                      \n",
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met1     59488                                                                                                     \n",
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met2      3099                                                                                                     \n",
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met3       956                                                                                                     \n",
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met4         0                                                                                                     \n",
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114639                                                                                                             \n",
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[INFO DRT-0195] Start 2nd optimization iteration.                                                                  \n",
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Completing 10% with 6581 violations.                                                                               \n",
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elapsed time = 00:00:45, memory = 1008.57 (MB).                                                                    \n",
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Completing 20% with 6581 violations.                                                                               \n",
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elapsed time = 00:02:12, memory = 1010.46 (MB).                                                                    \n",
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Completing 30% with 6678 violations.                                                                               \n",
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elapsed time = 00:03:31, memory = 1016.32 (MB).                                                                    \n",
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Completing 40% with 6678 violations.                                                                               \n",
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elapsed time = 00:04:52, memory = 1016.32 (MB).                                                                    \n",
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Completing 50% with 6678 violations.                                                                               \n",
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elapsed time = 00:06:27, memory = 1016.32 (MB).                                                                    \n",
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Completing 60% with 6589 violations.                                                                               \n",
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elapsed time = 00:07:49, memory = 961.74 (MB).                                                                     \n",
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Completing 70% with 6589 violations.                                                                               \n",
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elapsed time = 00:09:30, memory = 993.35 (MB).                                                                     \n",
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Completing 80% with 6405 violations.                                                                               \n",
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elapsed time = 00:11:18, memory = 1020.36 (MB).                                                                    \n",
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Completing 90% with 6405 violations.                                                                               \n",
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elapsed time = 00:12:58, memory = 1020.55 (MB).                                                                    \n",
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Completing 100% with 6358 violations.                                                                              \n",
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elapsed time = 00:14:43, memory = 1016.63 (MB).                                                                    \n",
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[INFO DRT-0199]   Number of violations = 6373.                                                                     \n",
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Viol/Layer        mcon   met1   met2   met3                                                                        \n",
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Cut Spacing          6      0      0      0                                                                        \n",
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Metal Spacing        0   1282    161     13                                                                        \n",
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Recheck              0     14      1      0                                                                        \n",
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Short                0   4582    314      0                                                                        \n",
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Total wire length = 582213 um.                                                                                     \n",
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Total wire length on LAYER li1 = 0 um.                                                                             \n",
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Total wire length on LAYER met1 = 248369 um.                                                                       \n",
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Total wire length on LAYER met2 = 247023 um.                                                                       \n",
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Total wire length on LAYER met3 = 52526 um.                                                                        \n",
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Total wire length on LAYER met4 = 34292 um.                                                                        \n",
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Total wire length on LAYER met5 = 0 um.                                                                            \n",
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Total number of vias = 114303.                                                                                     \n",
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Up-via summary (total 114303):.                                                                                    \n",
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-------------------------                                                                                          \n",
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FR_MASTERSLICE         0                                                                                           \n",
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li1     51096                                                                                                      \n",
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met1     59214                                                                                                     \n",
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met2      3036                                                                                                     \n",
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met3       957                                                                                                     \n",
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met4         0                                                                                                     \n",
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-------------------------                                                                                          \n",
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114303                                                                                                             \n",
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[INFO DRT-0195] Start 3rd optimization iteration.                                                                  \n",
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Completing 10% with 6373 violations.                                                                               \n",
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elapsed time = 00:00:55, memory = 1016.63 (MB).                                                                    \n",
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Completing 20% with 6373 violations.                                                                               \n",
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elapsed time = 00:02:29, memory = 993.26 (MB).                                                                     \n",
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Completing 30% with 5292 violations.                                                                               \n",
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elapsed time = 00:03:52, memory = 981.00 (MB).                                                                     \n",
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Completing 40% with 5292 violations.                                                                               \n",
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elapsed time = 00:05:59, memory = 1023.89 (MB).                                                                    \n",
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Completing 50% with 5292 violations.                                                                               \n",
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elapsed time = 00:07:59, memory = 963.05 (MB).                                                                     \n",
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Completing 60% with 4103 violations.                                                                               \n",
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elapsed time = 00:09:58, memory = 983.16 (MB).                                                                     \n",
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Completing 70% with 4103 violations.                                                                               \n",
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elapsed time = 00:12:04, memory = 1005.84 (MB).                                                                    \n",
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Completing 80% with 2737 violations.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:14:14\u001b[0m, memory = \u001b[1;36m1031.62\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:14:14, memory = 1031.62 (MB).                                                                    \n",
+              "
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Completing 90% with 2737 violations.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:16:39\u001b[0m, memory = \u001b[1;36m1033.43\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:16:39, memory = 1033.43 (MB).                                                                    \n",
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Completing 100% with 1294 violations.                                                                              \n",
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elapsed time = 00:18:33, memory = 962.89 (MB).                                                                     \n",
+              "
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[INFO DRT-0199]   Number of violations = 1296.                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Viol/Layer mcon met1 via met2 met3 \n" + ], + "text/html": [ + "
Viol/Layer        mcon   met1    via   met2   met3                                                                 \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Cut Spacing \u001b[1;36m5\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m1\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
Cut Spacing          5      0      1      0      0                                                                 \n",
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Metal Spacing        0    444      0     52      4                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Min Hole \u001b[1;36m0\u001b[0m \u001b[1;36m1\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
Min Hole             0      1      0      0      0                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Recheck \u001b[1;36m0\u001b[0m \u001b[1;36m2\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
Recheck              0      2      0      0      0                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Short \u001b[1;36m0\u001b[0m \u001b[1;36m736\u001b[0m \u001b[1;36m0\u001b[0m \u001b[1;36m51\u001b[0m \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
Short                0    736      0     51      0                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0267\u001b[0m\u001b[1m]\u001b[0m cpu time = \u001b[1;92m00:30:59\u001b[0m, elapsed time = \u001b[1;92m00:18:35\u001b[0m, memory = \u001b[1;36m962.89\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m, peak = \u001b[1;36m1077.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
[INFO DRT-0267] cpu time = 00:30:59, elapsed time = 00:18:35, memory = 962.89 (MB), peak = 1077.54 (MB)            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length = \u001b[1;36m580796\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length = 580796 um.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER li1 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER li1 = 0 um.                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met1 = \u001b[1;36m233677\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met1 = 233677 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met2 = \u001b[1;36m248132\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met2 = 248132 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met3 = \u001b[1;36m64709\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met3 = 64709 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met4 = \u001b[1;36m34277\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met4 = 34277 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met5 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met5 = 0 um.                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total number of vias = \u001b[1;36m116593\u001b[0m. \n" + ], + "text/html": [ + "
Total number of vias = 116593.                                                                                     \n",
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Up-via summary (total 116593):.                                                                                    \n",
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-------------------------                                                                                          \n",
+              "
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FR_MASTERSLICE         0                                                                                           \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "li1 \u001b[1;36m51096\u001b[0m \n" + ], + "text/html": [ + "
li1     51096                                                                                                      \n",
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met1     59780                                                                                                     \n",
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met2      4745                                                                                                     \n",
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met3       972                                                                                                     \n",
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met4         0                                                                                                     \n",
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-------------------------                                                                                          \n",
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116593                                                                                                             \n",
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[INFO DRT-0195] Start 4th optimization iteration.                                                                  \n",
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Completing 10% with 1296 violations.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:16\u001b[0m, memory = \u001b[1;36m985.32\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:16, memory = 985.32 (MB).                                                                     \n",
+              "
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Completing 20% with 1296 violations.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:50\u001b[0m, memory = \u001b[1;36m1025.77\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:50, memory = 1025.77 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m30\u001b[0m% with \u001b[1;36m965\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 30% with 965 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:01:25\u001b[0m, memory = \u001b[1;36m984.25\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:01:25, memory = 984.25 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m40\u001b[0m% with \u001b[1;36m965\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 40% with 965 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:02:06\u001b[0m, memory = \u001b[1;36m1036.34\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:02:06, memory = 1036.34 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m50\u001b[0m% with \u001b[1;36m965\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 50% with 965 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:02:36\u001b[0m, memory = \u001b[1;36m1016.40\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:02:36, memory = 1016.40 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m60\u001b[0m% with \u001b[1;36m757\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 60% with 757 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:03:06\u001b[0m, memory = \u001b[1;36m1018.05\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:03:06, memory = 1018.05 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m70\u001b[0m% with \u001b[1;36m757\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 70% with 757 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:04:47\u001b[0m, memory = \u001b[1;36m1081.33\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:04:47, memory = 1081.33 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m80\u001b[0m% with \u001b[1;36m392\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 80% with 392 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:05:03\u001b[0m, memory = \u001b[1;36m1005.59\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:05:03, memory = 1005.59 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m90\u001b[0m% with \u001b[1;36m392\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 90% with 392 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:05:29\u001b[0m, memory = \u001b[1;36m963.05\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:05:29, memory = 963.05 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m100\u001b[0m% with \u001b[1;36m109\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 100% with 109 violations.                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:06:04\u001b[0m, memory = \u001b[1;36m963.05\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:06:04, memory = 963.05 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0199\u001b[0m\u001b[1m]\u001b[0m Number of violations = \u001b[1;36m109\u001b[0m. \n" + ], + "text/html": [ + "
[INFO DRT-0199]   Number of violations = 109.                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Viol/Layer mcon met1 met2 \n" + ], + "text/html": [ + "
Viol/Layer        mcon   met1   met2                                                                               \n",
+              "
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Cut Spacing          1      0      0                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Metal Spacing \u001b[1;36m0\u001b[0m \u001b[1;36m52\u001b[0m \u001b[1;36m6\u001b[0m \n" + ], + "text/html": [ + "
Metal Spacing        0     52      6                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Short \u001b[1;36m0\u001b[0m \u001b[1;36m49\u001b[0m \u001b[1;36m1\u001b[0m \n" + ], + "text/html": [ + "
Short                0     49      1                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0267\u001b[0m\u001b[1m]\u001b[0m cpu time = \u001b[1;92m00:09:50\u001b[0m, elapsed time = \u001b[1;92m00:06:06\u001b[0m, memory = \u001b[1;36m963.05\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m, peak = \u001b[1;36m1081.33\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
[INFO DRT-0267] cpu time = 00:09:50, elapsed time = 00:06:06, memory = 963.05 (MB), peak = 1081.33 (MB)            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length = \u001b[1;36m580731\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length = 580731 um.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER li1 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER li1 = 0 um.                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met1 = \u001b[1;36m232784\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met1 = 232784 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met2 = \u001b[1;36m248238\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met2 = 248238 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met3 = \u001b[1;36m65450\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met3 = 65450 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met4 = \u001b[1;36m34257\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met4 = 34257 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met5 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met5 = 0 um.                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total number of vias = \u001b[1;36m116708\u001b[0m. \n" + ], + "text/html": [ + "
Total number of vias = 116708.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Up-via summary \u001b[1m(\u001b[0mtotal \u001b[1;36m116708\u001b[0m\u001b[1m)\u001b[0m:. \n" + ], + "text/html": [ + "
Up-via summary (total 116708):.                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
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+              "
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-------------------------                                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "FR_MASTERSLICE \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
FR_MASTERSLICE         0                                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "li1 \u001b[1;36m51096\u001b[0m \n" + ], + "text/html": [ + "
li1     51096                                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "met1 \u001b[1;36m59830\u001b[0m \n" + ], + "text/html": [ + "
met1     59830                                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "met2 \u001b[1;36m4811\u001b[0m \n" + ], + "text/html": [ + "
met2      4811                                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "met3 \u001b[1;36m971\u001b[0m \n" + ], + "text/html": [ + "
met3       971                                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "met4 \u001b[1;36m0\u001b[0m \n" + ], + "text/html": [ + "
met4         0                                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "------------------------- \n" + ], + "text/html": [ + "
-------------------------                                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m116708\u001b[0m \n" + ], + "text/html": [ + "
116708                                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + " \n" + ], + "text/html": [ + "
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+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0195\u001b[0m\u001b[1m]\u001b[0m Start 5th optimization iteration. \n" + ], + "text/html": [ + "
[INFO DRT-0195] Start 5th optimization iteration.                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m10\u001b[0m% with \u001b[1;36m109\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 10% with 109 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:00\u001b[0m, memory = \u001b[1;36m963.05\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:00, memory = 963.05 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m20\u001b[0m% with \u001b[1;36m109\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 20% with 109 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:01\u001b[0m, memory = \u001b[1;36m1016.41\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:01, memory = 1016.41 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m30\u001b[0m% with \u001b[1;36m88\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 30% with 88 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:22\u001b[0m, memory = \u001b[1;36m962.93\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:22, memory = 962.93 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m40\u001b[0m% with \u001b[1;36m88\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 40% with 88 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:23\u001b[0m, memory = \u001b[1;36m983.55\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:23, memory = 983.55 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m50\u001b[0m% with \u001b[1;36m88\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 50% with 88 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:26\u001b[0m, memory = \u001b[1;36m1025.18\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:26, memory = 1025.18 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m60\u001b[0m% with \u001b[1;36m78\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 60% with 78 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:34\u001b[0m, memory = \u001b[1;36m962.89\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:34, memory = 962.89 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m70\u001b[0m% with \u001b[1;36m78\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 70% with 78 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:46\u001b[0m, memory = \u001b[1;36m991.11\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:46, memory = 991.11 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m80\u001b[0m% with \u001b[1;36m37\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 80% with 37 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:56\u001b[0m, memory = \u001b[1;36m1013.76\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:56, memory = 1013.76 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m90\u001b[0m% with \u001b[1;36m37\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 90% with 37 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:01:04\u001b[0m, memory = \u001b[1;36m1019.82\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:01:04, memory = 1019.82 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m100\u001b[0m% with \u001b[1;36m25\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 100% with 25 violations.                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:01:19\u001b[0m, memory = \u001b[1;36m964.91\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:01:19, memory = 964.91 (MB).                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0199\u001b[0m\u001b[1m]\u001b[0m Number of violations = \u001b[1;36m25\u001b[0m. \n" + ], + "text/html": [ + "
[INFO DRT-0199]   Number of violations = 25.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Viol/Layer met1 \n" + ], + "text/html": [ + "
Viol/Layer        met1                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Metal Spacing \u001b[1;36m13\u001b[0m \n" + ], + "text/html": [ + "
Metal Spacing       13                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Short \u001b[1;36m12\u001b[0m \n" + ], + "text/html": [ + "
Short               12                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0267\u001b[0m\u001b[1m]\u001b[0m cpu time = \u001b[1;92m00:01:58\u001b[0m, elapsed time = \u001b[1;92m00:01:21\u001b[0m, memory = \u001b[1;36m964.91\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m, peak = \u001b[1;36m1081.33\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
[INFO DRT-0267] cpu time = 00:01:58, elapsed time = 00:01:21, memory = 964.91 (MB), peak = 1081.33 (MB)            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length = \u001b[1;36m580799\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length = 580799 um.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER li1 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER li1 = 0 um.                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met1 = \u001b[1;36m232693\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met1 = 232693 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met2 = \u001b[1;36m248282\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met2 = 248282 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met3 = \u001b[1;36m65562\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met3 = 65562 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met4 = \u001b[1;36m34260\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met4 = 34260 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met5 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met5 = 0 um.                                                                            \n",
+              "
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Total number of vias = 116706.                                                                                     \n",
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Up-via summary (total 116706):.                                                                                    \n",
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-------------------------                                                                                          \n",
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FR_MASTERSLICE         0                                                                                           \n",
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li1     51096                                                                                                      \n",
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met1     59827                                                                                                     \n",
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met2      4814                                                                                                     \n",
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met3       969                                                                                                     \n",
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met4         0                                                                                                     \n",
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-------------------------                                                                                          \n",
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116706                                                                                                             \n",
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+              "
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[INFO DRT-0195] Start 6th optimization iteration.                                                                  \n",
+              "
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Completing 10% with 25 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:00\u001b[0m, memory = \u001b[1;36m964.91\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:00, memory = 964.91 (MB).                                                                     \n",
+              "
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Completing 20% with 25 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:00\u001b[0m, memory = \u001b[1;36m964.91\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:00, memory = 964.91 (MB).                                                                     \n",
+              "
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Completing 30% with 10 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:03\u001b[0m, memory = \u001b[1;36m1019.05\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:03, memory = 1019.05 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m40\u001b[0m% with \u001b[1;36m10\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 40% with 10 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:03\u001b[0m, memory = \u001b[1;36m1019.05\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:03, memory = 1019.05 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m50\u001b[0m% with \u001b[1;36m10\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 50% with 10 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:03\u001b[0m, memory = \u001b[1;36m1019.05\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:03, memory = 1019.05 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m60\u001b[0m% with \u001b[1;36m5\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 60% with 5 violations.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:05\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:05, memory = 1023.54 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m70\u001b[0m% with \u001b[1;36m5\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 70% with 5 violations.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:05\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:05, memory = 1023.54 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m80\u001b[0m% with \u001b[1;36m2\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 80% with 2 violations.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:13\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:13, memory = 1023.54 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m90\u001b[0m% with \u001b[1;36m2\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 90% with 2 violations.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:13\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:13, memory = 1023.54 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m100\u001b[0m% with \u001b[1;36m1\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 100% with 1 violations.                                                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:17\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:17, memory = 1023.54 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0199\u001b[0m\u001b[1m]\u001b[0m Number of violations = \u001b[1;36m1\u001b[0m. \n" + ], + "text/html": [ + "
[INFO DRT-0199]   Number of violations = 1.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Viol/Layer met1 \n" + ], + "text/html": [ + "
Viol/Layer        met1                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Metal Spacing \u001b[1;36m1\u001b[0m \n" + ], + "text/html": [ + "
Metal Spacing        1                                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0267\u001b[0m\u001b[1m]\u001b[0m cpu time = \u001b[1;92m00:00:24\u001b[0m, elapsed time = \u001b[1;92m00:00:19\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m, peak = \u001b[1;36m1081.33\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m \n" + ], + "text/html": [ + "
[INFO DRT-0267] cpu time = 00:00:24, elapsed time = 00:00:19, memory = 1023.54 (MB), peak = 1081.33 (MB)           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length = \u001b[1;36m580768\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length = 580768 um.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER li1 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER li1 = 0 um.                                                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met1 = \u001b[1;36m232639\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met1 = 232639 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met2 = \u001b[1;36m248217\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met2 = 248217 um.                                                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met3 = \u001b[1;36m65620\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met3 = 65620 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met4 = \u001b[1;36m34291\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met4 = 34291 um.                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total wire length on LAYER met5 = \u001b[1;36m0\u001b[0m um. \n" + ], + "text/html": [ + "
Total wire length on LAYER met5 = 0 um.                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Total number of vias = \u001b[1;36m116716\u001b[0m. \n" + ], + "text/html": [ + "
Total number of vias = 116716.                                                                                     \n",
+              "
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Up-via summary (total 116716):.                                                                                    \n",
+              "
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                                                                                                                   \n",
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-------------------------                                                                                          \n",
+              "
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FR_MASTERSLICE         0                                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "li1 \u001b[1;36m51096\u001b[0m \n" + ], + "text/html": [ + "
li1     51096                                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "met1 \u001b[1;36m59824\u001b[0m \n" + ], + "text/html": [ + "
met1     59824                                                                                                     \n",
+              "
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met2      4823                                                                                                     \n",
+              "
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met3       973                                                                                                     \n",
+              "
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met4         0                                                                                                     \n",
+              "
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-------------------------                                                                                          \n",
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116716                                                                                                             \n",
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                                                                                                                   \n",
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[INFO DRT-0195] Start 7th optimization iteration.                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m10\u001b[0m% with \u001b[1;36m1\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 10% with 1 violations.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:00\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:00, memory = 1023.54 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m20\u001b[0m% with \u001b[1;36m1\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 20% with 1 violations.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:00\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:00, memory = 1023.54 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m30\u001b[0m% with \u001b[1;36m1\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 30% with 1 violations.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "elapsed time = \u001b[1;92m00:00:00\u001b[0m, memory = \u001b[1;36m1023.54\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n" + ], + "text/html": [ + "
elapsed time = 00:00:00, memory = 1023.54 (MB).                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Completing \u001b[1;36m40\u001b[0m% with \u001b[1;36m1\u001b[0m violations. \n" + ], + "text/html": [ + "
Completing 40% with 1 violations.                                                                                  \n",
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Completing 50% with 1 violations.                                                                                  \n",
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elapsed time = 00:00:00, memory = 1023.54 (MB).                                                                    \n",
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Completing 60% with 0 violations.                                                                                  \n",
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elapsed time = 00:00:01, memory = 1023.54 (MB).                                                                    \n",
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Completing 70% with 0 violations.                                                                                  \n",
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Completing 80% with 0 violations.                                                                                  \n",
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Completing 90% with 0 violations.                                                                                  \n",
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Completing 100% with 0 violations.                                                                                 \n",
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[INFO DRT-0199]   Number of violations = 0.                                                                        \n",
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Total wire length = 580766 um.                                                                                     \n",
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Total wire length on LAYER li1 = 0 um.                                                                             \n",
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Total wire length on LAYER met2 = 248217 um.                                                                       \n",
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Total wire length on LAYER met4 = 34291 um.                                                                        \n",
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Total wire length on LAYER met5 = 0 um.                                                                            \n",
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Total number of vias = 116716.                                                                                     \n",
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FR_MASTERSLICE         0                                                                                           \n",
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li1     51096                                                                                                      \n",
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met1     59824                                                                                                     \n",
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met2      4823                                                                                                     \n",
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met3       973                                                                                                     \n",
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met4         0                                                                                                     \n",
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116716                                                                                                             \n",
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[INFO DRT-0198] Complete detail routing.                                                                           \n",
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Total wire length = 580766 um.                                                                                     \n",
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Total wire length on LAYER li1 = 0 um.                                                                             \n",
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Total wire length on LAYER met1 = 232637 um.                                                                       \n",
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Total wire length on LAYER met2 = 248217 um.                                                                       \n",
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Total wire length on LAYER met3 = 65620 um.                                                                        \n",
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Total wire length on LAYER met4 = 34291 um.                                                                        \n",
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Total wire length on LAYER met5 = 0 um.                                                                            \n",
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Total number of vias = 116716.                                                                                     \n",
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FR_MASTERSLICE         0                                                                                           \n",
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li1     51096                                                                                                      \n",
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met1     59824                                                                                                     \n",
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met2      4823                                                                                                     \n",
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met3       973                                                                                                     \n",
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met4         0                                                                                                     \n",
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-------------------------                                                                                          \n",
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116716                                                                                                             \n",
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[INFO DRT-0180] Post processing.                                                                                   \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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───────────────────────────────────────────────── Fill Insertion ──────────────────────────────────────────────────\n",
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[12:50:56] VERBOSE  Running 'OpenROAD.FillInsertion'(Log:                                            step.py:1085\n",
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[INFO] Using clock clock…                                                                                          \n",
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[INFO] Setting output delay to: 2                                                                                  \n",
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[INFO] Setting input delay to: 2                                                                                   \n",
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[INFO] Setting load to: 0.033442                                                                                   \n",
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[INFO] Setting clock uncertainty to: 0.25                                                                          \n",
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[INFO] Setting timing derate to: 5%                                                                                \n",
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[INFO DPL-0001] Placed 18542 filler instances.                                                                     \n",
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Setting global connections for newly added cells…                                                                  \n",
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[INFO] Setting global connections...                                                                               \n",
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[12:51:04] VERBOSE  Running 'KLayout.Render'(Log: /tmp/tmpwmrsdbxd/klayout-render.log)               step.py:1085\n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "text/markdown": "#### Time Elapsed: 3.03s\n#### Views updated:\n* Verilog Netlist\n* Powered Verilog Netlist\n* Design Exchange Format\n* OpenDB Database\n* Design Constraints\n#### Preview:\n" + }, + "metadata": {} + } + ], + "source": [ + "display(fill)" + ] + }, + { + "cell_type": "markdown", + "id": "0a4cb2db-d455-4c36-b3a4-7b89ce0514b8", + "metadata": { + "id": "0a4cb2db-d455-4c36-b3a4-7b89ce0514b8" + }, + "source": [ + "#### **Parasitics Extraction a.k.a. Resistance/Capacitance Extraction (RCX)**" + ] + }, + { + "cell_type": "markdown", + "source": [ + "**Dear distinguished jury members, colleagues, and fellow developers,**\n", + "\n", + "We would like to bring to your attention that we have utilized OpenLANE2, the next generation of OpenLANE, which has been rewritten from scratch with a modular architecture. As of the time of our submission, the official version is still under active development, and we have proactively provided feedback on several issues and suggested improvements.\n", + "\n", + "At the time of our submission,** the timing analysis (STA) of the RCX stage was not yet stabilized**, *even for the official SPM examples*. We have already communicated this concern to the development team.\n", + "\n", + "Furthermore, we have made available the results of a complete, end-to-end flow with successful signoff, based on a local OpenLANE Docker implementation, on our GitHub repository**:https://github.com/lyaniix/ChatChisel-core** We welcome everyone to access and review these artifacts.\n", + "\n", + "We appreciate your understanding and consideration of the current state of the OpenLANE2 development, and we look forward to your valuable feedback." + ], + "metadata": { + "id": "x_Q-1O9oqwQ7" + }, + "id": "x_Q-1O9oqwQ7" + }, + { + "cell_type": "code", + "execution_count": null, + "id": "0fa4e2d6-3678-46f6-950c-80033501fba2", + "metadata": { + "id": "0fa4e2d6-3678-46f6-950c-80033501fba2", + "colab": { + "base_uri": "https://localhost:8080/" + }, + "outputId": "fe215dcd-266b-4db2-ec79-ddf13860ffdb" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[92m─────────────────────────────────── \u001b[0mParasitic Resistance/Capacitance Extraction\u001b[92m ───────────────────────────────────\u001b[0m\n" + ], + "text/html": [ + "
─────────────────────────────────── Parasitic Resistance/Capacitance Extraction ───────────────────────────────────\n",
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[12:51:13] VERBOSE  Running 'OpenROAD.RCX'(Log: ./openlane_run/12-openroad-rcx/openroad-rcx.log)     step.py:1085\n",
+              "
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[12:51:13] INFO     Running RCX for corners matching nom_*                                         openroad.py:1653\n",
+              "                    (/content/openlane_run/12-openroad-rcx/nom/rcx.log)                \n",
+              "
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[12:51:13] INFO     Running RCX for corners matching min_*                                         openroad.py:1653\n",
+              "                    (/content/openlane_run/12-openroad-rcx/min/rcx.log)                \n",
+              "
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[12:51:16] ERROR    Failed RCX for the corners matching min_*:                                     openroad.py:1664\n",
+              "
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[12:51:16] ERROR    Failed RCX for the corners matching nom_*:                                     openroad.py:1664\n",
+              "
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[12:51:16] INFO     Running RCX for corners matching max_*                                         openroad.py:1653\n",
+              "                    (/content/openlane_run/12-openroad-rcx/max/rcx.log)                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "error", + "ename": "StepSignalled", + "evalue": "Parasitics (RC) Extraction: Interrupted (SIGSEGV)", + "traceback": [ + "\u001b[0;31m---------------------------------------------------------------------------\u001b[0m", + "\u001b[0;31mStepSignalled\u001b[0m Traceback (most recent call last)", + "\u001b[0;32m\u001b[0m in \u001b[0;36m\u001b[0;34m()\u001b[0m\n\u001b[1;32m 2\u001b[0m \u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m 3\u001b[0m \u001b[0mrcx\u001b[0m \u001b[0;34m=\u001b[0m \u001b[0mRCX\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0mstate_in\u001b[0m\u001b[0;34m=\u001b[0m\u001b[0mfill\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mstate_out\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[0;32m----> 4\u001b[0;31m \u001b[0mrcx\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mstart\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[0m", + "\u001b[0;32m/content/openlane_ipynb/openlane/steps/step.py\u001b[0m in \u001b[0;36mstart\u001b[0;34m(self, toolbox, step_dir, _no_rule, **kwargs)\u001b[0m\n\u001b[1;32m 1113\u001b[0m \u001b[0;32mexcept\u001b[0m \u001b[0msubprocess\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mCalledProcessError\u001b[0m \u001b[0;32mas\u001b[0m \u001b[0me\u001b[0m\u001b[0;34m:\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m 1114\u001b[0m \u001b[0;32mif\u001b[0m \u001b[0me\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mreturncode\u001b[0m \u001b[0;32mis\u001b[0m \u001b[0;32mnot\u001b[0m \u001b[0;32mNone\u001b[0m \u001b[0;32mand\u001b[0m \u001b[0me\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mreturncode\u001b[0m \u001b[0;34m<\u001b[0m \u001b[0;36m0\u001b[0m\u001b[0;34m:\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[0;32m-> 1115\u001b[0;31m raise StepSignalled(\n\u001b[0m\u001b[1;32m 1116\u001b[0m \u001b[0;34mf\"{self.name}: Interrupted ({Signals(-e.returncode).name})\"\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m 1117\u001b[0m ) from None\n", + "\u001b[0;31mStepSignalled\u001b[0m: Parasitics (RC) Extraction: Interrupted (SIGSEGV)" + ] + } + ], + "source": [ + "RCX = Step.factory.get(\"OpenROAD.RCX\")\n", + "\n", + "rcx = RCX(state_in=fill.state_out)\n", + "rcx.start()" + ] + }, + { + "cell_type": "markdown", + "id": "966fe7c7-9e89-4a72-90c9-87b818916d9a", + "metadata": { + "id": "966fe7c7-9e89-4a72-90c9-87b818916d9a" + }, + "source": [ + "#### ***Static Timing Analysis (Post-PnR)***" + ] + }, + { + "cell_type": "markdown", + "source": [ + "**Dear distinguished jury members, colleagues, and fellow developers,**\n", + "\n", + "We would like to bring to your attention that we have utilized OpenLANE2, the next generation of OpenLANE, which has been rewritten from scratch with a modular architecture. As of the time of our submission, the official version is still under active development, and we have proactively provided feedback on several issues and suggested improvements.\n", + "\n", + "At the time of our submission,** the timing analysis (STA) of the post-place-and-route (Post-PnR) stage was not yet stabilized**, *even for the official SPM examples*. We have already communicated this concern to the development team.\n", + "\n", + "Furthermore, we have made available the results of a complete, end-to-end flow with successful signoff, based on a local OpenLANE Docker implementation, on our GitHub repository. We welcome everyone to access and review these artifacts.\n", + "\n", + "We appreciate your understanding and consideration of the current state of the OpenLANE2 development, and we look forward to your valuable feedback." + ], + "metadata": { + "id": "YJfujapJWkNU" + }, + "id": "YJfujapJWkNU" + }, + { + "cell_type": "code", + "execution_count": null, + "id": "7840cb38-88e7-4a03-b42c-fa8ae893a0bc", + "metadata": { + "id": "7840cb38-88e7-4a03-b42c-fa8ae893a0bc" + }, + "outputs": [], + "source": [ + "STAPostPNR = Step.factory.get(\"OpenROAD.STAPostPNR\")\n", + "\n", + "sta_post_pnr = STAPostPNR(state_in=rcx.state_out)\n", + "sta_post_pnr.start()" + ] + }, + { + "cell_type": "markdown", + "id": "5b25e927-ee2f-47f7-a37d-e58d998e1036", + "metadata": { + "id": "5b25e927-ee2f-47f7-a37d-e58d998e1036" + }, + "source": [ + "#### Stream-out" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "f706902d-4d93-4e24-ba7d-3f1e80eb9411", + "metadata": { + "id": "f706902d-4d93-4e24-ba7d-3f1e80eb9411", + "colab": { + "base_uri": "https://localhost:8080/", + "height": 354 + }, + "outputId": "9bf5a3ab-b931-4a21-a065-f7313dcff4c7" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[92m─────────────────────────────────────────── \u001b[0mGDSII Stream Out \u001b[1m(\u001b[0mKLayout\u001b[1m)\u001b[0m\u001b[92m ────────────────────────────────────────────\u001b[0m\n" + ], + "text/html": [ + "
─────────────────────────────────────────── GDSII Stream Out (KLayout) ────────────────────────────────────────────\n",
+              "
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[12:51:45] VERBOSE  Running 'KLayout.StreamOut'(Log:                                                 step.py:1085\n",
+              "                    ./openlane_run/13-klayout-streamout/klayout-streamout.log)                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1m[\u001b[0mINFO\u001b[1m]\u001b[0m Clearing cells… \n" + ], + "text/html": [ + "
[INFO] Clearing cells…                                                                                             \n",
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[INFO] Merging GDS files…                                                                                          \n",
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[INFO] Copying top level cell 'core'…                                                                              \n",
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[INFO] Checking for missing GDS…                                                                                   \n",
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[INFO] All LEF cells have matching GDS cells.                                                                      \n",
+              "
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[INFO] Writing out GDS '/content/openlane_run/13-klayout-streamout/core.klayout.gds'…                              \n",
+              "
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[INFO] Done.                                                                                                       \n",
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[12:51:55] VERBOSE  Running 'KLayout.Render'(Log: /tmp/tmpblf95zrt/klayout-render.log)               step.py:1085\n",
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─────────────────────────────────────────────── Design Rule Checks ────────────────────────────────────────────────\n",
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[12:52:11] VERBOSE  Running 'Magic.DRC'(Log: ./openlane_run/14-magic-drc/magic-drc.log)              step.py:1085\n",
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Magic 8.3 revision 466 - Compiled on Thu Mar 21 17:31:46 UTC 2024.                                                 \n",
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Starting magic under Tcl interpreter                                                                               \n",
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Using the terminal as the console.                                                                                 \n",
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Using NULL graphics device.                                                                                        \n",
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Processing system .magicrc file                                                                                    \n",
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Sourcing design .magicrc for technology sky130A ...                                                                \n",
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2 Magic internal units = 1 Lambda                                                                                  \n",
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Input style sky130(): scaleFactor=2, multiplier=2                                                                  \n",
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The following types are not handled by extraction and will be treated as non-electrical types:                     \n",
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ubm                                                                                                                \n",
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Scaled tech values by 2 / 1 to match internal grid scaling                                                         \n",
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Loading sky130A Device Generator Menu ...                                                                          \n",
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Loading \"/content/openlane_ipynb/openlane/scripts/magic/wrapper.tcl\" from command line.                            \n",
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Warning: Calma reading is not undoable!  I hope that's OK.                                                         \n",
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Library written using GDS-II Release 6.0                                                                           \n",
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Library name: LIB                                                                                                  \n",
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Reading \"VIA_M3M4_PR\".                                                                                             \n",
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Reading \"VIA_M2M3_PR\".                                                                                             \n",
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Reading \"VIA_M1M2_PR_MR\".                                                                                          \n",
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Reading \"VIA_M1M2_PR\".                                                                                             \n",
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Reading \"VIA_L1M1_PR_MR\".                                                                                          \n",
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Reading \"VIA_via2_3_1600_480_1_5_320_320\".                                                                         \n",
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Reading \"VIA_via3_4_1600_480_1_4_400_400\".                                                                         \n",
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Reading \"VIA_via4_5_1600_480_1_4_400_400\".                                                                         \n",
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Reading \"VIA_via5_6_1600_1600_1_1_1600_1600\".                                                                      \n",
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Reading \"sky130_fd_sc_hd__clkbuf_16\".                                                                              \n",
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Reading \"sky130_fd_sc_hd__dfxtp_2\".                                                                                \n",
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Reading \"sky130_fd_sc_hd__o21bai_2\".                                                                               \n",
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Reading \"sky130_fd_sc_hd__o41a_2\".                                                                                 \n",
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Reading \"sky130_fd_sc_hd__o31ai_2\".                                                                                \n",
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Reading \"sky130_fd_sc_hd__a311o_2\".                                                                                \n",
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Reading \"sky130_fd_sc_hd__o22ai_2\".                                                                                \n",
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Reading \"sky130_fd_sc_hd__a32oi_2\".                                                                                \n",
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Reading \"sky130_fd_sc_hd__nor4b_2\".                                                                                \n",
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Reading \"sky130_fd_sc_hd__and4b_2\".                                                                                \n",
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100000 uses                                                                                                        \n",
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135000 uses                                                                                                        \n",
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145000 uses                                                                                                        \n",
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150000 uses                                                                                                        \n",
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155000 uses                                                                                                        \n",
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[INFO] Loading core                                                                                                \n",
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DRC style is now \"drc(full)\"                                                                                       \n",
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Loading DRC CIF style.                                                                                             \n",
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No errors found.                                                                                                   \n",
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[INFO] COUNT: 0                                                                                                    \n",
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[INFO] Should be divided by 3 or 4                                                                                 \n",
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[INFO] DRC Checking DONE (/content/openlane_run/14-magic-drc/reports/drc_violations.magic.rpt)                     \n",
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[INFO] Saving mag view with DRC errors (/content/openlane_run/14-magic-drc/views/core.drc.mag)                     \n",
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[INFO] Saved                                                                                                       \n",
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" + ] + }, + "metadata": {}, + "execution_count": 52 + } + ], + "source": [ + "DRC = Step.factory.get(\"Magic.DRC\")\n", + "\n", + "drc = DRC(state_in=gds.state_out)\n", + "drc.start()" + ] + }, + { + "cell_type": "markdown", + "id": "e6b0c60b-0eb0-498d-b1f4-264bc0c79a48", + "metadata": { + "id": "e6b0c60b-0eb0-498d-b1f4-264bc0c79a48" + }, + "source": [ + "#### SPICE Extraction for Layout vs. Schematic Check" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "1a3ec2f4-585a-4641-9f4a-33521a7fe237", + "metadata": { + "id": "1a3ec2f4-585a-4641-9f4a-33521a7fe237", + "colab": { + "base_uri": "https://localhost:8080/", + "height": 1000 + }, + "outputId": "2f98ee3e-9de2-4618-935e-78b4de6a58d7" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[92m───────────────────────────────────────────── \u001b[0mSPICE Model Extraction\u001b[92m ──────────────────────────────────────────────\u001b[0m\n" + ], + "text/html": [ + "
───────────────────────────────────────────── SPICE Model Extraction ──────────────────────────────────────────────\n",
+              "
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[12:56:07] VERBOSE  Running 'Magic.SpiceExtraction'(Log:                                             step.py:1085\n",
+              "                    ./openlane_run/15-magic-spiceextraction/magic-spiceextraction.log)                             \n",
+              "
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                                                                                                                   \n",
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Magic 8.3 revision 466 - Compiled on Thu Mar 21 17:31:46 UTC 2024.                                                 \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Starting magic under Tcl interpreter \n" + ], + "text/html": [ + "
Starting magic under Tcl interpreter                                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Using the terminal as the console. \n" + ], + "text/html": [ + "
Using the terminal as the console.                                                                                 \n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Using NULL graphics device. \n" + ], + "text/html": [ + "
Using NULL graphics device.                                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Processing system .magicrc file \n" + ], + "text/html": [ + "
Processing system .magicrc file                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Sourcing design .magicrc for technology sky130A \u001b[33m...\u001b[0m \n" + ], + "text/html": [ + "
Sourcing design .magicrc for technology sky130A ...                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[1;36m2\u001b[0m Magic internal units = \u001b[1;36m1\u001b[0m Lambda \n" + ], + "text/html": [ + "
2 Magic internal units = 1 Lambda                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Input style \u001b[1;35msky130\u001b[0m\u001b[1m(\u001b[0m\u001b[1m)\u001b[0m: \u001b[33mscaleFactor\u001b[0m=\u001b[1;36m2\u001b[0m, \u001b[33mmultiplier\u001b[0m=\u001b[1;36m2\u001b[0m \n" + ], + "text/html": [ + "
Input style sky130(): scaleFactor=2, multiplier=2                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "The following types are not handled by extraction and will be treated as non-electrical types: \n" + ], + "text/html": [ + "
The following types are not handled by extraction and will be treated as non-electrical types:                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "ubm \n" + ], + "text/html": [ + "
ubm                                                                                                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Scaled tech values by \u001b[1;36m2\u001b[0m \u001b[35m/\u001b[0m \u001b[1;36m1\u001b[0m to match internal grid scaling \n" + ], + "text/html": [ + "
Scaled tech values by 2 / 1 to match internal grid scaling                                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Loading sky130A Device Generator Menu \u001b[33m...\u001b[0m \n" + ], + "text/html": [ + "
Loading sky130A Device Generator Menu ...                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Loading \u001b[32m\"/content/openlane_ipynb/openlane/scripts/magic/wrapper.tcl\"\u001b[0m from command line. \n" + ], + "text/html": [ + "
Loading \"/content/openlane_ipynb/openlane/scripts/magic/wrapper.tcl\" from command line.                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "> lef read \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/\u001b[0m\u001b[95msky130_fd_sc_hd__nom.tlef\u001b[0m \n" + ], + "text/html": [ + "
> lef read /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading LEF data from file \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/\u001b[0m\u001b[95msky130_fd_sc_hd__nom.tlef.\u001b[0m \n" + ], + "text/html": [ + "
Reading LEF data from file /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "This action cannot be undone. \n" + ], + "text/html": [ + "
This action cannot be undone.                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m78\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 78 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring.                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m79\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNADIFFSIDEAREARATIO\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 79 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring.                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m112\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MINENCLOSEDAREA\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 112 (Message): Unknown keyword \"MINENCLOSEDAREA\" in LEF file; ignoring.                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m114\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 114 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring.                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m115\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNADIFFSIDEAREARATIO\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 115 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring.                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m121\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MAXIMUMDENSITY\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 121 (Message): Unknown keyword \"MAXIMUMDENSITY\" in LEF file; ignoring.                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m122\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKWINDOW\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 122 (Message): Unknown keyword \"DENSITYCHECKWINDOW\" in LEF file; ignoring.                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m123\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKSTEP\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 123 (Message): Unknown keyword \"DENSITYCHECKSTEP\" in LEF file; ignoring.                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m156\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MINENCLOSEDAREA\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 156 (Message): Unknown keyword \"MINENCLOSEDAREA\" in LEF file; ignoring.                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m164\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 164 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring.                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m165\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNADIFFSIDEAREARATIO\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 165 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring.                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m167\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MAXIMUMDENSITY\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 167 (Message): Unknown keyword \"MAXIMUMDENSITY\" in LEF file; ignoring.                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m168\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKWINDOW\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 168 (Message): Unknown keyword \"DENSITYCHECKWINDOW\" in LEF file; ignoring.                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m169\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKSTEP\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 169 (Message): Unknown keyword \"DENSITYCHECKSTEP\" in LEF file; ignoring.                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m206\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 206 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring.                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m207\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNADIFFSIDEAREARATIO\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 207 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring.                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m209\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MAXIMUMDENSITY\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 209 (Message): Unknown keyword \"MAXIMUMDENSITY\" in LEF file; ignoring.                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m210\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKWINDOW\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 210 (Message): Unknown keyword \"DENSITYCHECKWINDOW\" in LEF file; ignoring.                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m211\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKSTEP\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 211 (Message): Unknown keyword \"DENSITYCHECKSTEP\" in LEF file; ignoring.                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m248\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 248 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring.                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m249\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNADIFFSIDEAREARATIO\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 249 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring.                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m251\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MAXIMUMDENSITY\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 251 (Message): Unknown keyword \"MAXIMUMDENSITY\" in LEF file; ignoring.                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m252\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKWINDOW\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 252 (Message): Unknown keyword \"DENSITYCHECKWINDOW\" in LEF file; ignoring.                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m253\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKSTEP\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 253 (Message): Unknown keyword \"DENSITYCHECKSTEP\" in LEF file; ignoring.                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m290\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 290 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring.                                \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read, Line \u001b[1;36m291\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNADIFFSIDEAREARATIO\"\u001b[0m in LEF file; ignoring. \n" + ], + "text/html": [ + "
LEF read, Line 291 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring.                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read: Processed \u001b[1;36m797\u001b[0m lines. \n" + ], + "text/html": [ + "
LEF read: Processed 797 lines.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "> lef read \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/\u001b[0m\u001b[95msky130_ef_sc_hd.lef\u001b[0m \n" + ], + "text/html": [ + "
> lef read /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading LEF data from file \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/\u001b[0m\u001b[95msky130_ef_sc_hd.lef.\u001b[0m \n" + ], + "text/html": [ + "
Reading LEF data from file /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef.                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "This action cannot be undone. \n" + ], + "text/html": [ + "
This action cannot be undone.                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read: Processed \u001b[1;36m278\u001b[0m lines. \n" + ], + "text/html": [ + "
LEF read: Processed 278 lines.                                                                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "> lef read \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/\u001b[0m\u001b[95msky130_fd_sc_hd.lef\u001b[0m \n" + ], + "text/html": [ + "
> lef read /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading LEF data from file \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/\u001b[0m\u001b[95msky130_fd_sc_hd.lef.\u001b[0m \n" + ], + "text/html": [ + "
Reading LEF data from file /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef.                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "This action cannot be undone. \n" + ], + "text/html": [ + "
This action cannot be undone.                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "LEF read: Processed \u001b[1;36m68740\u001b[0m lines. \n" + ], + "text/html": [ + "
LEF read: Processed 68740 lines.                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "> def read \u001b[35m/content/openlane_run/11-openroad-fillinsertion/\u001b[0m\u001b[95mcore.def\u001b[0m -noblockage -labels \n" + ], + "text/html": [ + "
> def read /content/openlane_run/11-openroad-fillinsertion/core.def -noblockage -labels                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading DEF data from file \u001b[35m/content/openlane_run/11-openroad-fillinsertion/\u001b[0m\u001b[95mcore.def.\u001b[0m \n" + ], + "text/html": [ + "
Reading DEF data from file /content/openlane_run/11-openroad-fillinsertion/core.def.                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "This action cannot be undone. \n" + ], + "text/html": [ + "
This action cannot be undone.                                                                                      \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Processed \u001b[1;36m4\u001b[0m vias total. \n" + ], + "text/html": [ + "
Processed 4 vias total.                                                                                            \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Processed \u001b[1;36m36839\u001b[0m subcell instances total. \n" + ], + "text/html": [ + "
Processed 36839 subcell instances total.                                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Processed \u001b[1;36m170\u001b[0m pins total. \n" + ], + "text/html": [ + "
Processed 170 pins total.                                                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Processed \u001b[1;36m2\u001b[0m special nets total. \n" + ], + "text/html": [ + "
Processed 2 special nets total.                                                                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Processed \u001b[1;36m13480\u001b[0m nets total. \n" + ], + "text/html": [ + "
Processed 13480 nets total.                                                                                        \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "DEF read: Processed \u001b[1;36m307174\u001b[0m lines. \n" + ], + "text/html": [ + "
DEF read: Processed 307174 lines.                                                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00011_\"\u001b[0m from metal1 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00011_\" from metal1 to via1 in cell core.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00022_\"\u001b[0m from metal1 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00022_\" from metal1 to via1 in cell core.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00028_\"\u001b[0m from metal1 to viali in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00028_\" from metal1 to viali in cell core.                                                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00033_\"\u001b[0m from metal2 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00033_\" from metal2 to via1 in cell core.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00036_\"\u001b[0m from metal1 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00036_\" from metal1 to via1 in cell core.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00039_\"\u001b[0m from metal1 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00039_\" from metal1 to via1 in cell core.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00070_\"\u001b[0m from metal1 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00070_\" from metal1 to via1 in cell core.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00078_\"\u001b[0m from metal1 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00078_\" from metal1 to via1 in cell core.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00088_\"\u001b[0m from metal1 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00088_\" from metal1 to via1 in cell core.                                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Moving label \u001b[32m\"_00089_\"\u001b[0m from metal1 to via1 in cell core. \n" + ], + "text/html": [ + "
Moving label \"_00089_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00091_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00100_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00105_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00112_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00144_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00146_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00152_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00164_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00188_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00192_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00193_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00194_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00201_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00205_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00236_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00240_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00246_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00255_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00261_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00268_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00273_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00275_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00283_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00301_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00307_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00343_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00367_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00368_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00369_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00371_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00379_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00383_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00386_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00389_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00390_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_00393_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_00401_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00407_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00414_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_00421_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00431_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_00434_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00437_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00440_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00444_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00446_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00449_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00454_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00476_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00484_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00501_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00502_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_00511_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00515_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00534_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_00537_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00540_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00542_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_00549_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00571_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_00574_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00575_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00580_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00586_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00606_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00608_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00611_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00612_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00618_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00622_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_00631_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_00666_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00691_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00707_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_00711_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00724_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00734_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_00748_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_00756_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_00758_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_00763_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00781_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00793_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00796_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00801_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_00830_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00834_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00843_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_00847_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00864_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00871_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00875_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00877_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00882_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00883_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00886_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00887_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_00888_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_00896_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_00902_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00903_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_00906_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00907_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00921_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00923_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00938_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00948_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_00968_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_00980_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01006_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01024_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01033_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01042_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01044_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01075_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01091_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01094_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01098_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01099_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01106_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01112_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01121_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01140_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01149_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01154_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01160_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01171_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01180_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01192_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01194_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_01200_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01205_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01206_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01216_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01236_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01244_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01253_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01265_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01286_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01299_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01302_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01317_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01328_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01331_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01334_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01347_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01352_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01353_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01367_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01371_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01372_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01374_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01399_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01466_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01478_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01480_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01542_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01548_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01570_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01606_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01611_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01612_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01616_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01622_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01630_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01634_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01648_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01662_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01668_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01671_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01672_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01673_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01677_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01682_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01684_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01686_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01687_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01698_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01704_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01705_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01724_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01725_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01731_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01734_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01745_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01747_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01763_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01764_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01775_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01780_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_01787_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01791_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01793_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01806_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01808_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01832_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01860_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01864_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01881_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01907_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01913_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01957_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01958_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01968_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01975_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01977_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01979_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_01980_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02002_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02027_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02032_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02069_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02097_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02102_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02110_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02116_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02122_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02127_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02131_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02134_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_02138_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02142_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02143_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02144_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02145_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02155_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02157_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02163_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02165_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02169_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02177_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02180_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02183_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02190_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02213_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02222_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02224_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02233_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02277_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02284_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02298_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02311_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02319_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02330_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02341_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02364_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02365_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02371_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02374_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02375_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02388_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02389_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02391_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02392_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02402_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02404_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02423_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02446_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02447_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02458_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02477_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02485_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02487_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02493_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02505_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02508_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02514_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02520_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02540_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02542_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02576_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02593_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02598_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02613_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02615_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02618_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02638_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02644_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02655_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02666_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02679_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02682_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02690_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02706_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02716_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02727_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02736_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02759_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02775_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02805_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02810_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02834_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02852_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02856_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02865_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02889_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02903_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02904_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02906_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02909_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02922_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02925_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02935_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_02943_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02955_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02974_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_02984_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_02989_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03045_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_03055_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03118_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03122_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03124_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03204_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03258_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03282_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03291_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03336_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03361_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03404_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03415_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03428_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03451_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_03462_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03463_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03477_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_03479_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_03482_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03513_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03523_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03534_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03552_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03583_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03609_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03648_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03668_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03694_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03697_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03736_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03737_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_03774_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03776_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03781_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03802_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03804_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03811_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_03902_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03914_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_03917_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_03937_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_03968_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04084_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_04123_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04148_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04211_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04231_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04237_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04250_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04254_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_04260_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04292_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04303_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_04321_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04394_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04399_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_04431_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04443_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_04452_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04494_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_04543_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_04634_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04642_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_04663_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_04674_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04733_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04748_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_04910_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05005_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05019_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05035_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05130_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05261_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_05277_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05316_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_05317_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05331_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05333_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_05370_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05372_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_05398_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05406_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_05420_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05459_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05484_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05502_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05526_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05528_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05541_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05543_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05550_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05581_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05590_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05594_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05608_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05621_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05625_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05668_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05714_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05733_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05743_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05749_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05758_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_05906_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05908_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_05935_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05950_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_05973_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_05993_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_06003_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06026_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_06078_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06226_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06239_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_06297_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06401_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_06410_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06458_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06475_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06479_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_06483_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06515_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06546_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06588_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_06591_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06635_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06673_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_06726_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_06739_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_06741_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_06758_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_06878_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_07038_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_07074_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07078_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_07109_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07123_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07157_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_07195_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07261_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_07262_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07344_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07369_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07384_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07398_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_07505_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_07508_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07580_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_07594_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_07613_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07636_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_07697_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_07706_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_07739_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_07784_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_07812_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_07846_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_07874_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07921_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_07981_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08013_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08064_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08068_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08075_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08089_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08092_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_08118_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08172_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08174_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08187_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08230_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08249_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08358_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_08377_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08388_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08415_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08461_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08508_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08542_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08549_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08578_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08582_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08671_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08672_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08679_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_08712_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08736_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08760_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08777_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08837_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08849_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08870_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_08991_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_08994_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_08996_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09014_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_09046_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09168_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09225_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09314_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09336_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09424_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_09430_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09463_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09487_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09510_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09579_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09581_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09611_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09646_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09656_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_09679_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09706_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09756_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_09814_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09823_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09843_\" from metal2 to via1 in cell core.                                                           \n",
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Moving label \"_09888_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09904_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09905_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_09906_\" from metal1 to via1 in cell core.                                                           \n",
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Moving label \"_09921_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_09949_\" from metal3 to via3 in cell core.                                                           \n",
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Moving label \"_09985_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"_10018_\" from metal2 to via2 in cell core.                                                           \n",
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Moving label \"_10027_\" from metal1 to viali in cell core.                                                          \n",
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Moving label \"clknet_0_clock\" from metal2 to via2 in cell core.                                                    \n",
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Moving label \"clknet_2_3_0_clock\" from metal2 to via2 in cell core.                                                \n",
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Moving label \"clknet_5_27__leaf_clock\" from metal2 to via2 in cell core.                                           \n",
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Moving label \"clknet_leaf_10_clock\" from metal1 to via1 in cell core.                                              \n",
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Moving label \"clknet_leaf_198_clock\" from metal1 to via1 in cell core.                                             \n",
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Moving label \"csr.minstret\\[25\\]\" from metal2 to via2 in cell core.                                                \n",
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Moving label \"csr.minstret\\[2\\]\" from metal1 to via1 in cell core.                                                 \n",
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Moving label \"csr.mscratch\\[15\\]\" from metal2 to via2 in cell core.                                                \n",
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Moving label \"csr.mscratch\\[1\\]\" from metal1 to via1 in cell core.                                                 \n",
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Moving label \"csr.mscratch\\[7\\]\" from metal1 to viali in cell core.                                                \n",
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Moving label \"csr.msip\" from metal1 to viali in cell core.                                                         \n",
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Moving label \"decode.id_ex_imm_reg\\[13\\]\" from metal2 to via2 in cell core.                                        \n",
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Moving label \"decode.id_ex_imm_reg\\[8\\]\" from metal1 to via1 in cell core.                                         \n",
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Moving label \"decode.id_ex_pc_reg\\[20\\]\" from metal2 to via2 in cell core.                                         \n",
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Moving label \"decode.id_ex_rs1_data_reg\\[10\\]\" from metal1 to via1 in cell core.                                   \n",
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Moving label \"decode.id_ex_rs1_data_reg\\[14\\]\" from metal1 to via1 in cell core.                                   \n",
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Moving label \"decode.id_ex_rs1_data_reg\\[18\\]\" from metal1 to via1 in cell core.                                   \n",
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Moving label \"decode.id_ex_rs1_data_reg\\[23\\]\" from metal2 to via2 in cell core.                                   \n",
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Moving label \"decode.id_ex_rs1_data_reg\\[26\\]\" from metal2 to via2 in cell core.                                   \n",
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Moving label \"decode.id_ex_rs1_data_reg\\[28\\]\" from metal1 to via1 in cell core.                                   \n",
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Moving label \"decode.id_ex_rs1_data_reg\\[6\\]\" from metal2 to via2 in cell core.                                    \n",
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Moving label \"decode.id_ex_rs2_data_reg\\[12\\]\" from metal2 to via2 in cell core.                                   \n",
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Moving label \"decode.id_ex_rs2_data_reg\\[1\\]\" from metal2 to via2 in cell core.                                    \n",
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Moving label \"decode.id_ex_rs2_data_reg\\[26\\]\" from metal2 to via2 in cell core.                                   \n",
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Moving label \"execute.io_reg_pc\\[7\\]\" from metal2 to via2 in cell core.                                            \n",
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Moving label \"execute.io_target_pc\\[6\\]\" from metal1 to via1 in cell core.                                         \n",
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Moving label \"fetch.bht.bhtTable_target_pc\\[13\\]\\[9\\]\" from metal1 to via1 in cell core.                           \n",
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Moving label \"fetch.bht.bhtTable_target_pc\\[14\\]\\[2\\]\" from metal1 to via1 in cell core.                           \n",
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Moving label \"fetch.bht.bhtTable_target_pc\\[2\\]\\[7\\]\" from metal1 to via1 in cell core.                            \n",
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Moving label \"fetch.bht.bhtTable_valid\\[6\\]\" from metal1 to via1 in cell core.                                     \n",
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Moving label \"fetch.btb.btbTable\\[3\\]\\[1\\]\" from metal1 to via1 in cell core.                                      \n",
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Moving label \"io_fetch_data[15]\" from metal3 to via3 in cell core.                                                 \n",
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Moving label \"io_fetch_data[18]\" from metal3 to via3 in cell core.                                                 \n",
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Moving label \"io_fetch_data[1]\" from metal3 to via3 in cell core.                                                  \n",
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Moving label \"io_memory_address[5]\" from metal2 to via2 in cell core.                                              \n",
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Moving label \"memory.io_wb_readdata\\[28\\]\" from metal3 to via3 in cell core.                                       \n",
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Moving label \"memory.io_wb_readdata\\[2\\]\" from metal3 to via3 in cell core.                                        \n",
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Moving label \"memory.io_wb_reg_pc\\[22\\]\" from metal1 to via1 in cell core.                                         \n",
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Moving label \"memory.io_wb_reg_pc\\[30\\]\" from metal1 to viali in cell core.                                        \n",
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Moving label \"memory.io_wb_reg_pc\\[5\\]\" from metal1 to via1 in cell core.                                          \n",
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Processing core                                                                                                    \n",
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Extracting sky130_ef_sc_hd__decap_12 into sky130_ef_sc_hd__decap_12.ext:                                           \n",
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Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:                                               \n",
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Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__dfxtp_2 into sky130_fd_sc_hd__dfxtp_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__dfxtp_2 into sky130_fd_sc_hd__dfxtp_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__mux2_1 into sky130_fd_sc_hd__mux2_1.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__mux2_1 into sky130_fd_sc_hd__mux2_1.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__mux4_2 into sky130_fd_sc_hd__mux4_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__mux4_2 into sky130_fd_sc_hd__mux4_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__clkbuf_8 into sky130_fd_sc_hd__clkbuf_8.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__clkbuf_8 into sky130_fd_sc_hd__clkbuf_8.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__or2_2 into sky130_fd_sc_hd__or2_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__or2_2 into sky130_fd_sc_hd__or2_2.ext:                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o211a_2 into sky130_fd_sc_hd__o211a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o211a_2 into sky130_fd_sc_hd__o211a_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a21oi_2 into sky130_fd_sc_hd__a21oi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a21oi_2 into sky130_fd_sc_hd__a21oi_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nor2_2 into sky130_fd_sc_hd__nor2_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nor2_2 into sky130_fd_sc_hd__nor2_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__inv_2 into sky130_fd_sc_hd__inv_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__inv_2 into sky130_fd_sc_hd__inv_2.ext:                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o21ai_2 into sky130_fd_sc_hd__o21ai_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o21ai_2 into sky130_fd_sc_hd__o21ai_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o2bb2a_2 into sky130_fd_sc_hd__o2bb2a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o2bb2a_2 into sky130_fd_sc_hd__o2bb2a_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__xnor2_2 into sky130_fd_sc_hd__xnor2_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__xnor2_2 into sky130_fd_sc_hd__xnor2_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a22o_2 into sky130_fd_sc_hd__a22o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a22o_2 into sky130_fd_sc_hd__a22o_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o21a_2 into sky130_fd_sc_hd__o21a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o21a_2 into sky130_fd_sc_hd__o21a_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__and4_2 into sky130_fd_sc_hd__and4_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__and4_2 into sky130_fd_sc_hd__and4_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nand2_2 into sky130_fd_sc_hd__nand2_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nand2_2 into sky130_fd_sc_hd__nand2_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext:                                         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a221o_2 into sky130_fd_sc_hd__a221o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a221o_2 into sky130_fd_sc_hd__a221o_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a311o_2 into sky130_fd_sc_hd__a311o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a311o_2 into sky130_fd_sc_hd__a311o_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a21o_2 into sky130_fd_sc_hd__a21o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a21o_2 into sky130_fd_sc_hd__a21o_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a211o_2 into sky130_fd_sc_hd__a211o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a211o_2 into sky130_fd_sc_hd__a211o_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a2bb2o_2 into sky130_fd_sc_hd__a2bb2o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a2bb2o_2 into sky130_fd_sc_hd__a2bb2o_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a22oi_2 into sky130_fd_sc_hd__a22oi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a22oi_2 into sky130_fd_sc_hd__a22oi_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o221a_2 into sky130_fd_sc_hd__o221a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o221a_2 into sky130_fd_sc_hd__o221a_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a221oi_2 into sky130_fd_sc_hd__a221oi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a221oi_2 into sky130_fd_sc_hd__a221oi_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o2111a_2 into sky130_fd_sc_hd__o2111a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o2111a_2 into sky130_fd_sc_hd__o2111a_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o22a_2 into sky130_fd_sc_hd__o22a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o22a_2 into sky130_fd_sc_hd__o22a_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a31o_2 into sky130_fd_sc_hd__a31o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a31o_2 into sky130_fd_sc_hd__a31o_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o311a_2 into sky130_fd_sc_hd__o311a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o311a_2 into sky130_fd_sc_hd__o311a_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__or3_2 into sky130_fd_sc_hd__or3_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__or3_2 into sky130_fd_sc_hd__or3_2.ext:                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__and2_2 into sky130_fd_sc_hd__and2_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__and2_2 into sky130_fd_sc_hd__and2_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__or3b_2 into sky130_fd_sc_hd__or3b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__or3b_2 into sky130_fd_sc_hd__or3b_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__and3_2 into sky130_fd_sc_hd__and3_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__and3_2 into sky130_fd_sc_hd__and3_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a211oi_2 into sky130_fd_sc_hd__a211oi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a211oi_2 into sky130_fd_sc_hd__a211oi_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__xor2_2 into sky130_fd_sc_hd__xor2_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__xor2_2 into sky130_fd_sc_hd__xor2_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nor3_2 into sky130_fd_sc_hd__nor3_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nor3_2 into sky130_fd_sc_hd__nor3_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nor3b_2 into sky130_fd_sc_hd__nor3b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nor3b_2 into sky130_fd_sc_hd__nor3b_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nand3_2 into sky130_fd_sc_hd__nand3_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nand3_2 into sky130_fd_sc_hd__nand3_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o31a_2 into sky130_fd_sc_hd__o31a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o31a_2 into sky130_fd_sc_hd__o31a_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o21ba_2 into sky130_fd_sc_hd__o21ba_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o21ba_2 into sky130_fd_sc_hd__o21ba_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a21bo_2 into sky130_fd_sc_hd__a21bo_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a21bo_2 into sky130_fd_sc_hd__a21bo_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__or4_2 into sky130_fd_sc_hd__or4_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__or4_2 into sky130_fd_sc_hd__or4_2.ext:                                                 \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o221ai_2 into sky130_fd_sc_hd__o221ai_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o221ai_2 into sky130_fd_sc_hd__o221ai_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a21boi_2 into sky130_fd_sc_hd__a21boi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a21boi_2 into sky130_fd_sc_hd__a21boi_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__and2b_2 into sky130_fd_sc_hd__and2b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__and2b_2 into sky130_fd_sc_hd__and2b_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nand2b_2 into sky130_fd_sc_hd__nand2b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nand2b_2 into sky130_fd_sc_hd__nand2b_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a32o_2 into sky130_fd_sc_hd__a32o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a32o_2 into sky130_fd_sc_hd__a32o_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__and3b_2 into sky130_fd_sc_hd__and3b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__and3b_2 into sky130_fd_sc_hd__and3b_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nand4_2 into sky130_fd_sc_hd__nand4_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nand4_2 into sky130_fd_sc_hd__nand4_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a41o_2 into sky130_fd_sc_hd__a41o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a41o_2 into sky130_fd_sc_hd__a41o_2.ext:                                               \n",
+              "
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Extracting sky130_fd_sc_hd__and4bb_2 into sky130_fd_sc_hd__and4bb_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o211ai_2 into sky130_fd_sc_hd__o211ai_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o211ai_2 into sky130_fd_sc_hd__o211ai_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a31oi_2 into sky130_fd_sc_hd__a31oi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a31oi_2 into sky130_fd_sc_hd__a31oi_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__and4b_2 into sky130_fd_sc_hd__and4b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__and4b_2 into sky130_fd_sc_hd__and4b_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__or4b_2 into sky130_fd_sc_hd__or4b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__or4b_2 into sky130_fd_sc_hd__or4b_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nor4_2 into sky130_fd_sc_hd__nor4_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nor4_2 into sky130_fd_sc_hd__nor4_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nand4b_2 into sky130_fd_sc_hd__nand4b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nand4b_2 into sky130_fd_sc_hd__nand4b_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__or4bb_2 into sky130_fd_sc_hd__or4bb_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__or4bb_2 into sky130_fd_sc_hd__or4bb_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a2111o_2 into sky130_fd_sc_hd__a2111o_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a2111o_2 into sky130_fd_sc_hd__a2111o_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o32a_2 into sky130_fd_sc_hd__o32a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o32a_2 into sky130_fd_sc_hd__o32a_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nand3b_2 into sky130_fd_sc_hd__nand3b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nand3b_2 into sky130_fd_sc_hd__nand3b_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o22ai_2 into sky130_fd_sc_hd__o22ai_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o22ai_2 into sky130_fd_sc_hd__o22ai_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o31ai_2 into sky130_fd_sc_hd__o31ai_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o31ai_2 into sky130_fd_sc_hd__o31ai_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__nor4b_2 into sky130_fd_sc_hd__nor4b_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__nor4b_2 into sky130_fd_sc_hd__nor4b_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a41oi_2 into sky130_fd_sc_hd__a41oi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a41oi_2 into sky130_fd_sc_hd__a41oi_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a32oi_2 into sky130_fd_sc_hd__a32oi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a32oi_2 into sky130_fd_sc_hd__a32oi_2.ext:                                             \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o21bai_2 into sky130_fd_sc_hd__o21bai_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o21bai_2 into sky130_fd_sc_hd__o21bai_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__a311oi_2 into sky130_fd_sc_hd__a311oi_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__a311oi_2 into sky130_fd_sc_hd__a311oi_2.ext:                                           \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting sky130_fd_sc_hd__o41a_2 into sky130_fd_sc_hd__o41a_2.ext: \n" + ], + "text/html": [ + "
Extracting sky130_fd_sc_hd__o41a_2 into sky130_fd_sc_hd__o41a_2.ext:                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Extracting core into core.ext: \n" + ], + "text/html": [ + "
Extracting core into core.ext:                                                                                     \n",
+              "
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exttospice finished.                                                                                               \n",
+              "
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Using technology \"sky130A\", version 1.0.465-2-gbdc9412                                                             \n",
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sdcopenlane_run/11-openroad-fillinsertion/core.sdc
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klayout_gdsopenlane_run/13-klayout-streamout/core.klayout.gds
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" + ] + }, + "metadata": {}, + "execution_count": 53 + } + ], + "source": [ + "SpiceExtraction = Step.factory.get(\"Magic.SpiceExtraction\")\n", + "\n", + "spx = SpiceExtraction(state_in=drc.state_out)\n", + "spx.start()" + ] + }, + { + "cell_type": "markdown", + "id": "bb876fd2-0258-4820-9151-efa37399376a", + "metadata": { + "id": "bb876fd2-0258-4820-9151-efa37399376a" + }, + "source": [ + "#### Layout vs. Schematic (LVS)\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "908db3b2-29a1-4a4d-bf49-cc5ecc68593b", + "metadata": { + "id": "908db3b2-29a1-4a4d-bf49-cc5ecc68593b", + "colab": { + "base_uri": "https://localhost:8080/", + "height": 1000 + }, + "outputId": "5f4a8d85-3882-44a2-c19b-b2e923bd2a28" + }, + "outputs": [ + { + "output_type": "display_data", + "data": { + "text/plain": [ + "\u001b[92m─────────────────────────────────────────────────── \u001b[0mNetgen LVS\u001b[92m ────────────────────────────────────────────────────\u001b[0m\n" + ], + "text/html": [ + "
─────────────────────────────────────────────────── Netgen LVS ────────────────────────────────────────────────────\n",
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[12:57:48] VERBOSE  Running 'Netgen.LVS'(Log: ./openlane_run/16-netgen-lvs/netgen-lvs.log)           step.py:1085\n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Netgen \u001b[1;36m1.5\u001b[0m.\u001b[1;36m255\u001b[0m compiled on Tue Dec \u001b[1;36m5\u001b[0m \u001b[1;92m22:48:12\u001b[0m UTC \u001b[1;36m2023\u001b[0m \n" + ], + "text/html": [ + "
Netgen 1.5.255 compiled on Tue Dec  5 22:48:12 UTC 2023                                                            \n",
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Warning: netgen command 'format' use fully-qualified name '::netgen::format'                                       \n",
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Warning: netgen command 'global' use fully-qualified name '::netgen::global'                                       \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading SPICE netlist file \n", + "\u001b[32m'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice'\u001b[0m\u001b[33m...\u001b[0m \n" + ], + "text/html": [ + "
Reading SPICE netlist file                                                                                         \n",
+              "'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice'...                          \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt \n" + ], + "text/html": [ + "
Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt                                                           \n",
+              "
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Creating placeholder cell definition.                                                                              \n",
+              "
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Call to undefined subcircuit sky130_fd_pr__nfet_01v8                                                               \n",
+              "
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Creating placeholder cell definition.                                                                              \n",
+              "
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Reading SPICE netlist file '/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice'...\n",
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\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading SPICE netlist file \u001b[32m'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice'\u001b[0m\u001b[33m...\u001b[0m \n" + ], + "text/html": [ + "
Reading SPICE netlist file '/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice'... \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading SPICE netlist file \u001b[32m'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice'\u001b[0m\u001b[33m...\u001b[0m \n" + ], + "text/html": [ + "
Reading SPICE netlist file '/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice'... \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading SPICE netlist file \u001b[32m'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice'\u001b[0m\u001b[33m...\u001b[0m \n" + ], + "text/html": [ + "
Reading SPICE netlist file '/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice'...         \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Call to undefined subcircuit sky130_fd_sc_hd__nand2_2 \n" + ], + "text/html": [ + "
Call to undefined subcircuit sky130_fd_sc_hd__nand2_2                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating placeholder cell definition. \n" + ], + "text/html": [ + "
Creating placeholder cell definition.                                                                              \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Call to undefined subcircuit sky130_fd_sc_hd__nor2_2 \n" + ], + "text/html": [ + "
Call to undefined subcircuit sky130_fd_sc_hd__nor2_2                                                               \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Creating placeholder cell definition. \n" + ], + "text/html": [ + "
Creating placeholder cell definition.                                                                              \n",
+              "
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Generating JSON file result                                                                                        \n",
+              "
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Reading netlist file /content/openlane_run/15-magic-spiceextraction/core.spice                                     \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Reading netlist file \u001b[35m/content/openlane_run/11-openroad-fillinsertion/\u001b[0m\u001b[95mcore.pnl.v\u001b[0m \n" + ], + "text/html": [ + "
Reading netlist file /content/openlane_run/11-openroad-fillinsertion/core.pnl.v                                    \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to \n", + "match. \n" + ], + "text/html": [ + "
Warning:  A case-insensitive file has been read and so the      verilog file must be treated case-insensitive to   \n",
+              "match.                                                                                                             \n",
+              "
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                                                                                                                   \n",
+              "
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Reading setup file /content/openlane_ipynb/openlane/scripts/netgen/setup.tcl                                       \n",
+              "
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                                                                                                                   \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Model sky130_fd_pr__res_generic_po pin end_a == end_b \n" + ], + "text/html": [ + "
Model sky130_fd_pr__res_generic_po pin end_a == end_b                                                              \n",
+              "
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No property mult found for device sky130_fd_pr__res_generic_po                                                     \n",
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Model sky130_fd_pr__nfet_01v8 pin 1 == 3                                                                           \n",
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No property mult found for device sky130_fd_pr__nfet_01v8                                                          \n",
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No property sa found for device sky130_fd_pr__nfet_01v8                                                            \n",
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No property sb found for device sky130_fd_pr__nfet_01v8                                                            \n",
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No property sd found for device sky130_fd_pr__nfet_01v8                                                            \n",
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No property nf found for device sky130_fd_pr__nfet_01v8                                                            \n",
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No property nrd found for device sky130_fd_pr__nfet_01v8                                                           \n",
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No property nrs found for device sky130_fd_pr__nfet_01v8                                                           \n",
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No property area found for device sky130_fd_pr__nfet_01v8                                                          \n",
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No property perim found for device sky130_fd_pr__nfet_01v8                                                         \n",
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No property topography found for device sky130_fd_pr__nfet_01v8                                                    \n",
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Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3                                                                       \n",
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No property mult found for device sky130_fd_pr__pfet_01v8_hvt                                                      \n",
+              "
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No property sa found for device sky130_fd_pr__pfet_01v8_hvt                                                        \n",
+              "
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No property sb found for device sky130_fd_pr__pfet_01v8_hvt                                                        \n",
+              "
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No property sd found for device sky130_fd_pr__pfet_01v8_hvt                                                        \n",
+              "
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No property nf found for device sky130_fd_pr__pfet_01v8_hvt                                                        \n",
+              "
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No property nrd found for device sky130_fd_pr__pfet_01v8_hvt                                                       \n",
+              "
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No property nrs found for device sky130_fd_pr__pfet_01v8_hvt                                                       \n",
+              "
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No property area found for device sky130_fd_pr__pfet_01v8_hvt                                                      \n",
+              "
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No property perim found for device sky130_fd_pr__pfet_01v8_hvt                                                     \n",
+              "
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No property topography found for device sky130_fd_pr__pfet_01v8_hvt                                                \n",
+              "
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No property value found for device sky130_fd_pr__diode_pw2nd_05v5                                                  \n",
+              "
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No property mult found for device sky130_fd_pr__diode_pw2nd_05v5                                                   \n",
+              "
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No property perim found for device sky130_fd_pr__diode_pw2nd_05v5                                                  \n",
+              "
\n" + ] + }, + "metadata": {} + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "Comparison output logged to file \u001b[35m/content/openlane_run/16-netgen-lvs/reports/\u001b[0m\u001b[95mlvs.netgen.rpt\u001b[0m \n" + ], + "text/html": [ + "
Comparison output logged to file /content/openlane_run/16-netgen-lvs/reports/lvs.netgen.rpt                        \n",
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Logging to file \"/content/openlane_run/16-netgen-lvs/reports/lvs.netgen.rpt\" enabled                               \n",
+              "
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                                                                                                                   \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__decap_3'                                                        \n",
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Circuit sky130_fd_sc_hd__decap_3 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__decap_3'                                                        \n",
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Circuit sky130_fd_sc_hd__decap_3 contains 2 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   1                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   1                                                                  \n",
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Circuit contains 4 nets.                                                                                           \n",
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                                                                                                                   \n",
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Circuit sky130_fd_sc_hd__decap_3 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'                                                  \n",
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Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.                                                \n",
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Circuit contains 0 nets, and 2 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'                                                  \n",
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Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.                                                \n",
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Circuit contains 0 nets, and 2 disconnected pins.                                                                  \n",
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Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices.                                                        \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand2_2'                                                        \n",
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Circuit sky130_fd_sc_hd__nand2_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand2_2'                                                        \n",
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Circuit sky130_fd_sc_hd__nand2_2 contains 8 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   4                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   4                                                                  \n",
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Circuit contains 8 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__nand2_2 contains no devices.                                                              \n",
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                                                                                                                   \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__fill_2'                                                         \n",
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Circuit sky130_fd_sc_hd__fill_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__fill_2'                                                         \n",
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Circuit sky130_fd_sc_hd__fill_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Circuit sky130_fd_sc_hd__fill_2 contains no devices.                                                               \n",
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                                                                                                                   \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__decap_4'                                                        \n",
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Circuit sky130_fd_sc_hd__decap_4 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__decap_4'                                                        \n",
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Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   1                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   1                                                                  \n",
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Circuit contains 4 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__decap_4 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dfxtp_2'                                                        \n",
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Circuit sky130_fd_sc_hd__dfxtp_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dfxtp_2'                                                        \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  13                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  13                                                                  \n",
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Circuit contains 18 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__dfxtp_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_ef_sc_hd__decap_12'                                                       \n",
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Circuit sky130_ef_sc_hd__decap_12 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_ef_sc_hd__decap_12'                                                       \n",
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Circuit sky130_ef_sc_hd__decap_12 contains 2 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   1                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   1                                                                  \n",
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Circuit contains 4 nets.                                                                                           \n",
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Circuit sky130_ef_sc_hd__decap_12 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__fill_1'                                                         \n",
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Circuit sky130_fd_sc_hd__fill_1 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__fill_1'                                                         \n",
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Circuit sky130_fd_sc_hd__fill_1 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Circuit sky130_fd_sc_hd__fill_1 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__decap_6'                                                        \n",
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Circuit sky130_fd_sc_hd__decap_6 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__decap_6'                                                        \n",
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Circuit sky130_fd_sc_hd__decap_6 contains 2 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   1                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   1                                                                  \n",
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Circuit contains 4 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__decap_6 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__decap_8'                                                        \n",
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Circuit sky130_fd_sc_hd__decap_8 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 4 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__decap_8'                                                        \n",
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Circuit sky130_fd_sc_hd__decap_8 contains 2 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   1                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   1                                                                  \n",
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Circuit contains 4 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__decap_8 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o211a_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o211a_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o211a_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o211a_2 contains 12 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o211a_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a21o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a21o_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a21o_2'                                                         \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   5                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a21o_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__mux2_1'                                                         \n",
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Circuit sky130_fd_sc_hd__mux2_1 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__mux2_1'                                                         \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__mux2_1 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_8'                                                       \n",
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Circuit sky130_fd_sc_hd__clkbuf_8 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 6 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_8'                                                       \n",
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Circuit sky130_fd_sc_hd__clkbuf_8 contains 20 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  10                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  10                                                                  \n",
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Circuit contains 7 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__clkbuf_8 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o221a_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o221a_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o221a_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o221a_2 contains 14 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o221a_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and3_2'                                                         \n",
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Circuit sky130_fd_sc_hd__and3_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and3_2'                                                         \n",
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Circuit sky130_fd_sc_hd__and3_2 contains 10 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   5                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   5                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__and3_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__or2_2'                                                          \n",
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Circuit sky130_fd_sc_hd__or2_2 contains 0 device instances.                                                        \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__or2_2'                                                          \n",
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Circuit sky130_fd_sc_hd__or2_2 contains 8 device instances.                                                        \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   4                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   4                                                                  \n",
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Circuit contains 9 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__or2_2 contains no devices.                                                                \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__or3b_2'                                                         \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__or3b_2'                                                         \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a21oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a21oi_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a21oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a21oi_2 contains 12 device instances.                                                     \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a21oi_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o21a_2'                                                         \n",
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Circuit sky130_fd_sc_hd__o21a_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o21a_2'                                                         \n",
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Circuit sky130_fd_sc_hd__o21a_2 contains 10 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   5                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   5                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o21a_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a22o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a22o_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a22o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a22o_2 contains 12 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a22o_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and4b_2'                                                        \n",
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Circuit sky130_fd_sc_hd__and4b_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and4b_2'                                                        \n",
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Circuit sky130_fd_sc_hd__and4b_2 contains 14 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__and4b_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__mux4_2'                                                         \n",
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Circuit sky130_fd_sc_hd__mux4_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 11 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__mux4_2'                                                         \n",
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Circuit sky130_fd_sc_hd__mux4_2 contains 28 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  14                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  14                                                                  \n",
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Circuit contains 24 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__mux4_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and2_2'                                                         \n",
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Circuit sky130_fd_sc_hd__and2_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and2_2'                                                         \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   4                                                                  \n",
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Circuit contains 9 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__and2_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a211o_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a211o_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a211o_2'                                                        \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a211o_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and4_2'                                                         \n",
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Circuit sky130_fd_sc_hd__and4_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and4_2'                                                         \n",
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Circuit sky130_fd_sc_hd__and4_2 contains 12 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__and4_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__xnor2_2'                                                        \n",
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Circuit sky130_fd_sc_hd__xnor2_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__xnor2_2'                                                        \n",
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Circuit sky130_fd_sc_hd__xnor2_2 contains 20 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  10                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  10                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__xnor2_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o21ai_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o21ai_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o21ai_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o21ai_2 contains 12 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 10 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o21ai_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a221o_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a221o_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a221o_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a221o_2 contains 14 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a221o_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__or3_2'                                                          \n",
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Circuit sky130_fd_sc_hd__or3_2 contains 0 device instances.                                                        \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__or3_2'                                                          \n",
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Circuit sky130_fd_sc_hd__or3_2 contains 10 device instances.                                                       \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   5                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   5                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__or3_2 contains no devices.                                                                \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o21bai_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o21bai_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o21bai_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o21bai_2 contains 14 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o21bai_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o2bb2a_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o2bb2a_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o2bb2a_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o2bb2a_2 contains 14 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o2bb2a_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nor3_2'                                                         \n",
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Circuit sky130_fd_sc_hd__nor3_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nor3_2'                                                         \n",
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Circuit sky130_fd_sc_hd__nor3_2 contains 12 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 10 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__nor3_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nor2_2'                                                         \n",
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Circuit sky130_fd_sc_hd__nor2_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nor2_2'                                                         \n",
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Circuit sky130_fd_sc_hd__nor2_2 contains 8 device instances.                                                       \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   4                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   4                                                                  \n",
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Circuit contains 8 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__nor2_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__inv_2'                                                          \n",
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Circuit sky130_fd_sc_hd__inv_2 contains 0 device instances.                                                        \n",
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Circuit contains 0 nets, and 6 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__inv_2'                                                          \n",
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Circuit sky130_fd_sc_hd__inv_2 contains 4 device instances.                                                        \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   2                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   2                                                                  \n",
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Circuit contains 6 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__inv_2 contains no devices.                                                                \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a31o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a31o_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a31o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a31o_2 contains 12 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a31o_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand2b_2'                                                       \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand2b_2'                                                       \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   5                                                                  \n",
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Circuit contains 9 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__nand2b_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__or4_2'                                                          \n",
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Circuit sky130_fd_sc_hd__or4_2 contains 0 device instances.                                                        \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__or4_2'                                                          \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__or4_2 contains no devices.                                                                \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o31a_2'                                                         \n",
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Circuit sky130_fd_sc_hd__o31a_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o31a_2'                                                         \n",
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Circuit sky130_fd_sc_hd__o31a_2 contains 12 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o31a_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__xor2_2'                                                         \n",
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Circuit sky130_fd_sc_hd__xor2_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__xor2_2'                                                         \n",
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Circuit sky130_fd_sc_hd__xor2_2 contains 20 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  10                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  10                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__xor2_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a21boi_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a21boi_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a21boi_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a21boi_2 contains 14 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a21boi_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_16'                                                      \n",
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Circuit sky130_fd_sc_hd__clkbuf_16 contains 0 device instances.                                                    \n",
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Circuit contains 0 nets, and 6 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_16'                                                      \n",
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Circuit sky130_fd_sc_hd__clkbuf_16 contains 40 device instances.                                                   \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  20                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  20                                                                  \n",
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Circuit contains 7 nets.                                                                                           \n",
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Circuit sky130_fd_sc_hd__clkbuf_16 contains no devices.                                                            \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o22a_2'                                                         \n",
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Circuit sky130_fd_sc_hd__o22a_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o22a_2'                                                         \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o311a_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o311a_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o311a_2'                                                        \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o311a_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a2bb2o_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a2bb2o_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a2bb2o_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a2bb2o_2 contains 14 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a2bb2o_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and2b_2'                                                        \n",
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Circuit sky130_fd_sc_hd__and2b_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 7 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and2b_2'                                                        \n",
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Circuit sky130_fd_sc_hd__and2b_2 contains 10 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   5                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   5                                                                  \n",
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Circuit contains 10 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__and2b_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand3_2'                                                        \n",
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Circuit sky130_fd_sc_hd__nand3_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand3_2'                                                        \n",
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Circuit sky130_fd_sc_hd__nand3_2 contains 12 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 10 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__nand3_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a32o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a32o_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a32o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a32o_2 contains 14 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a32o_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a31oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a31oi_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a31oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a31oi_2 contains 16 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a211oi_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a211oi_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a211oi_2'                                                       \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a41o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a41o_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a41o_2'                                                         \n",
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Circuit sky130_fd_sc_hd__a41o_2 contains 14 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a41o_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o221ai_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o221ai_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o221ai_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o221ai_2 contains 20 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  10                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  10                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o221ai_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a22oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a22oi_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a22oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a22oi_2 contains 16 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a22oi_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a21bo_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a21bo_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a21bo_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a21bo_2 contains 12 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a21bo_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o2111a_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o2111a_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o2111a_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o2111a_2 contains 14 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o2111a_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o22ai_2'                                                        \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o22ai_2'                                                        \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and3b_2'                                                        \n",
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Circuit sky130_fd_sc_hd__and3b_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and3b_2'                                                        \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__and3b_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand3b_2'                                                       \n",
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Circuit sky130_fd_sc_hd__nand3b_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand3b_2'                                                       \n",
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Circuit sky130_fd_sc_hd__nand3b_2 contains 14 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 11 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__nand3b_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__or4b_2'                                                         \n",
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Circuit sky130_fd_sc_hd__or4b_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__or4b_2'                                                         \n",
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Circuit sky130_fd_sc_hd__or4b_2 contains 14 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__or4b_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand4_2'                                                        \n",
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Circuit sky130_fd_sc_hd__nand4_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand4_2'                                                        \n",
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Circuit sky130_fd_sc_hd__nand4_2 contains 16 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__nand4_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a311o_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a311o_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a311o_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a311o_2 contains 14 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a311o_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a2111o_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a2111o_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a2111o_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a2111o_2 contains 14 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a2111o_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o21ba_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o21ba_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o21ba_2'                                                        \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   6                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   6                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o21ba_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nor4_2'                                                         \n",
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Circuit sky130_fd_sc_hd__nor4_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nor4_2'                                                         \n",
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Circuit sky130_fd_sc_hd__nor4_2 contains 16 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__nor4_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o211ai_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o211ai_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o211ai_2'                                                       \n",
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Circuit sky130_fd_sc_hd__o211ai_2 contains 16 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o211ai_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand4b_2'                                                       \n",
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Circuit sky130_fd_sc_hd__nand4b_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand4b_2'                                                       \n",
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Circuit sky130_fd_sc_hd__nand4b_2 contains 18 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   9                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   9                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__nand4b_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and4bb_2'                                                       \n",
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Circuit sky130_fd_sc_hd__and4bb_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and4bb_2'                                                       \n",
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Circuit sky130_fd_sc_hd__and4bb_2 contains 16 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__and4bb_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a221oi_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a221oi_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a221oi_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a221oi_2 contains 20 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  10                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  10                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a32oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a32oi_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a32oi_2'                                                        \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  10                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  10                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o31ai_2'                                                        \n",
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Circuit sky130_fd_sc_hd__o31ai_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o31ai_2'                                                        \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 12 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o31ai_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o41a_2'                                                         \n",
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Circuit sky130_fd_sc_hd__o41a_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o41a_2'                                                         \n",
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Circuit sky130_fd_sc_hd__o41a_2 contains 14 device instances.                                                      \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   7                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   7                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o41a_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__or4bb_2'                                                        \n",
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Circuit sky130_fd_sc_hd__or4bb_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__or4bb_2'                                                        \n",
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Circuit sky130_fd_sc_hd__or4bb_2 contains 16 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   8                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   8                                                                  \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__or4bb_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a311oi_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a311oi_2 contains 0 device instances.                                                     \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a311oi_2'                                                       \n",
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Circuit sky130_fd_sc_hd__a311oi_2 contains 20 device instances.                                                    \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  10                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  10                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a311oi_2 contains no devices.                                                             \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a41oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a41oi_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a41oi_2'                                                        \n",
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Circuit sky130_fd_sc_hd__a41oi_2 contains 20 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:  10                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:  10                                                                  \n",
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Circuit contains 14 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__a41oi_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nor3b_2'                                                        \n",
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Circuit contains 0 nets, and 8 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nor3b_2'                                                        \n",
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Circuit contains 11 nets.                                                                                          \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o32a_2'                                                         \n",
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Circuit sky130_fd_sc_hd__o32a_2 contains 0 device instances.                                                       \n",
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Circuit contains 0 nets, and 10 disconnected pins.                                                                 \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o32a_2'                                                         \n",
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Circuit contains 15 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__o32a_2 contains no devices.                                                               \n",
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Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nor4b_2'                                                        \n",
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Circuit sky130_fd_sc_hd__nor4b_2 contains 0 device instances.                                                      \n",
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Circuit contains 0 nets, and 9 disconnected pins.                                                                  \n",
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Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nor4b_2'                                                        \n",
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Circuit sky130_fd_sc_hd__nor4b_2 contains 18 device instances.                                                     \n",
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Class: sky130_fd_pr__nfet_01v8 instances:   9                                                                      \n",
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Class: sky130_fd_pr__pfet_01v8_hvt instances:   9                                                                  \n",
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Circuit contains 13 nets.                                                                                          \n",
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Circuit sky130_fd_sc_hd__nor4b_2 contains no devices.                                                              \n",
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Contents of circuit 1:  Circuit: 'core'                                                                            \n",
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Circuit core contains 36839 device instances.                                                                      \n",
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Class: sky130_fd_sc_hd__a41o_2 instances:  13                                                                      \n",
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Class: sky130_fd_sc_hd__a31o_2 instances: 106                                                                      \n",
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Class: sky130_fd_sc_hd__a21o_2 instances: 389                                                                      \n",
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Class: sky130_fd_sc_hd__clkbuf_16 instances:  33                                                                   \n",
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Class: sky130_fd_sc_hd__dfxtp_2 instances: 2955                                                                    \n",
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Class: sky130_fd_sc_hd__or4_2 instances:  48                                                                       \n",
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Class: sky130_fd_sc_hd__a2bb2o_2 instances:  20                                                                    \n",
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Class: sky130_fd_sc_hd__and3b_2 instances:   8                                                                     \n",
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Class: sky130_fd_sc_hd__xor2_2 instances:  41                                                                      \n",
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Class: sky130_fd_sc_hd__o221ai_2 instances:   5                                                                    \n",
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Class: sky130_fd_sc_hd__mux4_2 instances: 198                                                                      \n",
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Class: sky130_ef_sc_hd__decap_12 instances: 6039                                                                   \n",
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Class: sky130_fd_sc_hd__and4_2 instances:  64                                                                      \n",
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Class: sky130_fd_sc_hd__inv_2 instances: 193                                                                       \n",
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Class: sky130_fd_sc_hd__clkbuf_8 instances: 309                                                                    \n",
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Class: sky130_fd_sc_hd__nand3_2 instances:  28                                                                     \n",
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Class: sky130_fd_sc_hd__o21ba_2 instances:  13                                                                     \n",
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Class: sky130_fd_sc_hd__and2b_2 instances:  33                                                                     \n",
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Class: sky130_fd_sc_hd__and3_2 instances: 430                                                                      \n",
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Class: sky130_fd_sc_hd__decap_6 instances: 1776                                                                    \n",
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Contents of circuit 2:  Circuit: 'core'                                                                            \n",
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Class: sky130_fd_sc_hd__fill_2 instances: 1720                                                                     \n",
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Circuit was modified by parallel/series device merging.                                                            \n",
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Contents of circuit 1:  Circuit: 'core'                                                                            \n",
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Circuit core contains 13421 device instances.                                                                      \n",
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Class: sky130_fd_sc_hd__a22o_2 instances: 103                                                                      \n",
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Class: sky130_fd_sc_hd__o21a_2 instances: 207                                                                      \n",
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Circuit contains 13482 nets.                                                                                       \n",
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Circuit 1 contains 13421 devices, Circuit 2 contains 13421 devices.                                                \n",
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Circuit 1 contains 13482 nets,    Circuit 2 contains 13482 nets.                                                   \n",
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Final result:                                                                                                      \n",
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Circuits match uniquely.                                                                                           \n",
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LVS Done.                                                                                                          \n",
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" + ] + }, + "metadata": {}, + "execution_count": 54 + } + ], + "source": [ + "LVS = Step.factory.get(\"Netgen.LVS\")\n", + "\n", + "lvs = LVS(state_in=spx.state_out)\n", + "lvs.start()" + ] + }, + { + "cell_type": "markdown", + "id": "2312679b-e124-46da-a9df-cd11f922da79", + "metadata": { + "id": "2312679b-e124-46da-a9df-cd11f922da79" + }, + "source": [ + "The detailed PPA information is illustrated below. We will tape it out in mid-year on the efabless OpenMPW-9 shuttle." + ] + }, + { + "cell_type": "markdown", + "id": "4b2650eb-6c18-49ef-8a9e-5497ec9bd96a", + "metadata": { + "id": "4b2650eb-6c18-49ef-8a9e-5497ec9bd96a" + }, + "source": [ + "\n", + "|$$Feature$$|$$Parameters$$|\n", + "|:--:|:----------:|\n", + "|$$PDK$$
|$$Skywater 130nm$$|\n", + "|$$Gate Count$$
|$$ 66,000$$|\n", + "|$$IO$$
| $$186 Ports$$|\n", + "|$$Frequency$$
| $$125MHz$$|\n", + "|$$Total Power$$
|$$28.7mW$$|\n", + "|$$Core Area$$
|$$0.42{mm}^2$$|\n" + ] + }, + { + "cell_type": "markdown", + "id": "5bae58bb-aa96-4546-ba94-54db44c1422c", + "metadata": { + "id": "5bae58bb-aa96-4546-ba94-54db44c1422c" + }, + "source": [ + "## Evaluation" + ] + }, + { + "cell_type": "markdown", + "id": "615688c5-adcc-4471-ab88-e3cc768ffc36", + "metadata": { + "id": "615688c5-adcc-4471-ab88-e3cc768ffc36" + }, + "source": [ + "### A. Design Capability Analysis\n", + "We performed tests on various modules in our RISC-V CPU to investigate the capability of ChatChisel in hardware designs. We generate Chisel and Verilog using the same prompt and compare the pass rate of the generated design in terms of syntax and function verification, respectively. The generation capability is shown in the figure. The results indicate that the design generation using Chisel outperforms Verilog by 31.86%. This improvement can be attributed to the higher abstraction level, modular design nature, and reusable design libraries of Chisel. As such, the LLM can generate accurate hardware designs with Chisel codes based on the prompt requirements." + ] + }, + { + "cell_type": "markdown", + "id": "5e2e87d5-2ad8-42a7-b865-4841500faab8", + "metadata": { + "id": "5e2e87d5-2ad8-42a7-b865-4841500faab8" + }, + "source": [ + "
\n", + " \n", + "
Comparisons of Chisel & Verilog
\n", + "
" + ] + }, + { + "cell_type": "markdown", + "id": "d3146eed-e854-4ba4-9d41-0ec818d27397", + "metadata": { + "id": "d3146eed-e854-4ba4-9d41-0ec818d27397" + }, + "source": [ + "In addition, we analyzed the power and area for these modules. The results, shown in table, reveal that ChatChisel achieves an average of 11.45% area reduction and 1.80% power decrease as compared to the Verilog generation of the same CPU design, implying the advantages of LLM-based hardware design with Chisel." + ] + }, + { + "cell_type": "markdown", + "id": "857b6ec6-b59f-4839-94a3-3816db14b6b3", + "metadata": { + "id": "857b6ec6-b59f-4839-94a3-3816db14b6b3" + }, + "source": [ + "\n", + "|$Workload$|$HDL$|$Area/{mm^2}$|$Static Power/mW$|\n", + "|:--:|:----------:|:----------:|:----------:|\n", + "|$Control$
|$Chisel$|$2.11\\times 10^{-3}$|$0.014$|\n", + "|
|$Verilog$|$2.84\\times 10^{-3}$|$0.0152$|\n", + "|$ALU$
|$Chisel$|$0.02336$|$0.559$|\n", + "|
|$Verilog$|$0.02058$|$0.445$|\n", + "|$BTB$
|$Chisel$|$5.85\\times 10^{-3}$|$0.633$|\n", + "|
|Verilog|$6.88\\times 10^{-3}$|$0.53$|\n", + "|$BHT$
|$Chisel$|$0.09695$|$10.9$|\n", + "|
|$Verilog$|$0.1127$|$11.2$|\n", + "|$Fetch$
|$Chisel$|$0.1144$|$13.2$|\n", + "|
|$Verilog$|$0.13102$|$13.4$|" + ] + }, + { + "cell_type": "markdown", + "id": "9f8f43e1-2a67-42b6-97c7-ab048d97ee53", + "metadata": { + "id": "9f8f43e1-2a67-42b6-97c7-ab048d97ee53" + }, + "source": [ + "### B. Ablation Studies\n", + "\n", + "We conducted a series of ablation experiments to assess the impact of design decomposition, Tool Enhanced LLM Error Correction, and the utilization of RAG in ChatChisel. We employed GPT-3.5-turbo to test various modules within our CPU, with the results presented in the figure below." + ] + }, + { + "cell_type": "markdown", + "id": "533ff765-56ff-4072-8bf0-2d50a1bb27e7", + "metadata": { + "id": "533ff765-56ff-4072-8bf0-2d50a1bb27e7" + }, + "source": [ + "
\n", + "
\n", + " \n", + "
Design Decomposition Analysis
\n", + "
\n", + "
\n", + " \n", + "
Debugging & RAG Analysis
\n", + "
\n", + "
\n" + ] + }, + { + "cell_type": "markdown", + "id": "a093d5ce-400e-4cb5-8ea0-e8e669f23270", + "metadata": { + "id": "a093d5ce-400e-4cb5-8ea0-e8e669f23270" + }, + "source": [ + "In the first set of experiments, we observed that none of\n", + "the modules were successfully generated without the suppor\n", + "of design decompositio . Specifically, the Control modu e\n", + "failed to generate a complete module due to the limi ed\n", + "output tokens, while the Fetch and Hazard modules were\n", + "unable to be generated due to their high complexity. This\n", + "highlights the rapid decrease in the pass rate of modulegeneration with increasing design complexity. In the second et of\n", + "experiments, ChatChisel demonstrated an average gen ration\n", + "capability improvement of 62.17% over the workflow without\n", + "tool-enhanced LLM error correction. Notably, This ebugging\n", + "stage significantly reduced iteration times and pre ented the\n", + "LLM from e countering recurring errors during ve ification,\n", + "showcasing its importance in the generation pro ess. In the\n", + "third set of experiments, the average design apability of\n", + "ChatChisel was 27.93% higher when RA was employed\n", + "compared. This evaluation provides empirical impacts of RAG\n", + "upon improving the hardware design capability of LLMs." + ] + }, + { + "cell_type": "markdown", + "id": "8f8d7ba0-92a9-4602-a488-709127e2ed47", + "metadata": { + "id": "8f8d7ba0-92a9-4602-a488-709127e2ed47" + }, + "source": [ + "## Conclusion\n", + "This article explored the use of LLMs to generate Chisel code for RTL-level circuit design. Through comparative experiments, it was demonstrated that the ability of GPT-3.5-turbo to generate Chisel surpassed its ability to generate Verilog. We introduced ChatChisel, a framework for directly generating\n", + "agile HDLs from natural language using LLMs. This workflow leverages multiple expert LLMs and addresses certain challenges in LLM generation through techniques such as Design Decomposition, Tool Enhanced LLM Error Correction, and Structured Prompt with RAG. These advancements significantly improve the efficiency of RTL-level agile design. By utilizing the ChatChisel workflow, we successfully generated a RISC-V CPU, showcasing the potential of LLMs in generating complex circuits." + ] + }, + { + "cell_type": "markdown", + "metadata": { + "id": "5oL-i9_0YyAU" + }, + "source": [ + "## Acknowledgement\n", + "\n", + "\n", + "* We would like to express our sincere gratitude to the **VLSI'24 Code-a-Chip Contest** organizing committee for their support and coordination.\n", + "* We are also deeply appreciative of the generous support provided by Amazon Cloud Technology, which has enabled the successful completion of this project.\n", + "* Additionally, *some portions of the work* presented in this project have been accepted as * research papers* at the **61th ACM/IEEE DAC'24** and **ACM/IEEE ISEDA'24** conference. We welcome any citations, suggestions, and potential future collaborations regarding this project.\n", + "* We are thankful for the opportunity to contribute to the VLSI community and look forward to the valuable feedback and discussions that may arise from this endeavor.\n", + "\n", + "\n", + "\n", + "\n", + "\n", + "\n", + "\n", + "\n", + "\n", + "\n" + ], + "id": "5oL-i9_0YyAU" + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.11.7" + }, + "colab": { + "provenance": [], + "collapsed_sections": [ + "0a4cb2db-d455-4c36-b3a4-7b89ce0514b8", + "966fe7c7-9e89-4a72-90c9-87b818916d9a" + ] + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} \ No newline at end of file