"
+ ],
+ "text/markdown": "\n(step-yosys-synthesis)=\n### Synthesis\n\n```{eval-rst}\n\nPerforms synthesis and technology mapping on Verilog RTL files\nusing Yosys and ABC, emitting a netlist.\n\nSome metrics will also be extracted and updated, namely:\n\n* ``design__instance__count``\n* ``design__instance_unmapped__count``\n* ``design__instance__area``\n\n```\n\n#### Importing\n```python\nfrom openlane.steps.yosys import Synthesis\n\n# or\n\nfrom openlane.steps import Step\n\nSynthesis = Step.factory.get(\"Yosys.Synthesis\")\n```\n\n\n#### Inputs and Outputs\n\n| Inputs | Outputs |\n| - | - |\n| | Verilog Netlist (.nl.v) |\n\n(yosys.synthesis-configuration-variables)=\n#### Configuration Variables\n\n| Variable Name | Type | Description | Default | Units |\n| - | - | - | - | - |\n| `SYNTH_LATCH_MAP`{#var-yosys-synthesis-synth_latch_map}PDK | Path? | A path to a file containing the latch mapping for Yosys. | `None` | |\n| `SYNTH_TRISTATE_MAP`{#var-yosys-synthesis-synth_tristate_map}PDK | Path? | A path to a file containing the tri-state buffer mapping for Yosys. | `None` | |\n| `SYNTH_CSA_MAP`{#var-yosys-synthesis-synth_csa_map}PDK | Path? | A path to a file containing the carry-select adder mapping for Yosys. | `None` | |\n| `SYNTH_RCA_MAP`{#var-yosys-synthesis-synth_rca_map}PDK | Path? | A path to a file containing the ripple-carry adder mapping for Yosys. | `None` | |\n| `SYNTH_FA_MAP`{#var-yosys-synthesis-synth_fa_map}PDK | Path? | A path to a file containing the full adder mapping for Yosys. | `None` | |\n| `SYNTH_MUX_MAP`{#var-yosys-synthesis-synth_mux_map}PDK | Path? | A path to a file containing the mux mapping for Yosys. | `None` | |\n| `SYNTH_MUX4_MAP`{#var-yosys-synthesis-synth_mux4_map}PDK | Path? | A path to a file containing the mux4 mapping for Yosys. | `None` | |\n| `USE_LIGHTER`{#var-yosys-synthesis-use_lighter} | bool | Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops. | `False` | |\n| `LIGHTER_DFF_MAP`{#var-yosys-synthesis-lighter_dff_map} | Path? | An override to the custom DFF map file provided for the given SCL by Lighter. | `None` | |\n| `SYNTH_CHECKS_ALLOW_TRISTATE`{#var-yosys-synthesis-synth_checks_allow_tristate} | bool | Ignore multiple-driver warnings if they are connected to tri-state buffers on a best-effort basis. | `True` | |\n| `SYNTH_AUTONAME`{#var-yosys-synthesis-synth_autoname} | bool | Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable. | `False` | |\n| `SYNTH_STRATEGY`{#var-yosys-synthesis-synth_strategy} | 'AREA 0'|
'AREA 1'|
'AREA 2'|
'AREA 3'|
'DELAY 0'|
'DELAY 1'|
'DELAY 2'|
'DELAY 3'|
'DELAY 4' | Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them. | `AREA 0` | |\n| `SYNTH_ABC_BUFFERING`{#var-yosys-synthesis-synth_abc_buffering} | bool | Enables `abc` cell buffering. | `False` | |\n| `SYNTH_ABC_LEGACY_REFACTOR`{#var-yosys-synthesis-synth_abc_legacy_refactor} | bool | Replaces the ABC command `drf -l` with `refactor` which matches older versions of OpenLane but is more unstable. | `False` | |\n| `SYNTH_ABC_LEGACY_REWRITE`{#var-yosys-synthesis-synth_abc_legacy_rewrite} | bool | Replaces the ABC command `drw -l` with `rewrite` which matches older versions of OpenLane but is more unstable. | `False` | |\n| `SYNTH_DIRECT_WIRE_BUFFERING`{#var-yosys-synthesis-synth_direct_wire_buffering} | bool | Enables inserting buffer cells for directly connected wires. | `True` | |\n| `SYNTH_SPLITNETS`{#var-yosys-synthesis-synth_splitnets} | bool | Splits multi-bit nets into single-bit nets. Easier to trace but may not be supported by all tools. | `True` | |\n| `SYNTH_SIZING`{#var-yosys-synthesis-synth_sizing} | bool | Enables `abc` cell sizing (instead of buffering). | `False` | |\n| `SYNTH_NO_FLAT`{#var-yosys-synthesis-synth_no_flat} | bool | A flag that disables flattening the hierarchy during synthesis, only flattening it after synthesis, mapping and optimizations. | `False` | |\n| `SYNTH_SHARE_RESOURCES`{#var-yosys-synthesis-synth_share_resources} | bool | A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them. | `True` | |\n| `SYNTH_ADDER_TYPE`{#var-yosys-synthesis-synth_adder_type} | 'YOSYS'|
'FA'|
'RCA'|
'CSA' | Adder type to which the $add and $sub operators are mapped to. Possible values are `YOSYS/FA/RCA/CSA`; where `YOSYS` refers to using Yosys internal adder definition, `FA` refers to full-adder structure, `RCA` refers to ripple carry adder structure, and `CSA` refers to carry select adder. | `YOSYS` | |\n| `SYNTH_EXTRA_MAPPING_FILE`{#var-yosys-synthesis-synth_extra_mapping_file} | Path? | Points to an extra techmap file for yosys that runs right after yosys `synth` before generic techmap. | `None` | |\n| `SYNTH_PARAMETERS`{#var-yosys-synthesis-synth_parameters} | List[str]? | Key-value pairs to be `chparam`ed in Yosys, in the format `key1=value1`. | `None` | |\n| `SYNTH_ELABORATE_ONLY`{#var-yosys-synthesis-synth_elaborate_only} | bool | \"Elaborate\" the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. | `False` | |\n| `SYNTH_ELABORATE_FLATTEN`{#var-yosys-synthesis-synth_elaborate_flatten} | bool | If `SYNTH_ELABORATE_ONLY` is specified, this variable controls whether or not the top level should be flattened. | `True` | |\n| `VERILOG_FILES`{#var-yosys-synthesis-verilog_files} | List[Path] | The paths of the design's Verilog files. | `None` | |\n| `VERILOG_DEFINES`{#var-yosys-synthesis-verilog_defines} | List[str]? | Preprocessor defines for input Verilog files. | `None` | |\n| `VERILOG_POWER_DEFINE`{#var-yosys-synthesis-verilog_power_define} | str | Specifies the name of the define used to guard power and ground connections in the input RTL. | `USE_POWER_PINS` | |\n| `VERILOG_INCLUDE_DIRS`{#var-yosys-synthesis-verilog_include_dirs} | List[str]? | Specifies the Verilog `include` directories. | `None` | |\n| `USE_SYNLIG`{#var-yosys-synthesis-use_synlig} | bool | Use the Synlig plugin to process files, which has better SystemVerilog parsing capabilities but may not be compatible with all Yosys commands and attributes. | `False` | |\n| `SYNLIG_DEFER`{#var-yosys-synthesis-synlig_defer} | bool | Uses -defer flag when reading files the Synlig plugin, which may improve performance by reading each file separately, but is experimental. | `False` | |\n\n"
+ },
+ "metadata": {}
+ }
+ ],
+ "source": [
+ "from openlane.steps import Step\n",
+ "Synthesis = Step.factory.get(\"Yosys.Synthesis\")\n",
+ "\n",
+ "Synthesis.display_help()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "4d01d0f6-059c-494d-94a7-35a890d5edf8",
+ "metadata": {
+ "id": "4d01d0f6-059c-494d-94a7-35a890d5edf8"
+ },
+ "source": [
+ "#### Synthesis\n"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "cdcbfc17-9553-488d-9545-5098610f9130",
+ "metadata": {
+ "colab": {
+ "base_uri": "https://localhost:8080/",
+ "height": 1000
+ },
+ "id": "cdcbfc17-9553-488d-9545-5098610f9130",
+ "outputId": "c7514098-87f3-4c6a-fe0e-4d4b5e620e23"
+ },
+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m──────────────────────────────────────────────────── \u001b[0mSynthesis\u001b[92m ────────────────────────────────────────────────────\u001b[0m\n"
+ ],
+ "text/html": [
+ "──────────────────────────────────────────────────── Synthesis ────────────────────────────────────────────────────\n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
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+ ],
+ "text/html": [
+ "[11:14:09] VERBOSE Running 'Yosys.Synthesis'… (Log: step.py:1085\n",
+ " ./openlane_run/1-yosys-synthesis/yosys-synthesis.log) \n",
+ "
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+ ]
+ },
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+ "\u001b[35m/\u001b[0m\u001b[95m----------------------------------------------------------------------------\u001b[0m\\ \n"
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+ "| | \n"
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+ "
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+ ]
+ },
+ "metadata": {}
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+ "| yosys -- Yosys Open SYnthesis Suite | \n"
+ ],
+ "text/html": [
+ "| yosys -- Yosys Open SYnthesis Suite | \n",
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+ "| Copyright \u001b[1m(\u001b[0mC\u001b[1m)\u001b[0m \u001b[1;36m2012\u001b[0m - \u001b[1;36m2020\u001b[0m Claire Xenia Wolf \u001b[1m<\u001b[0m\u001b[1;95mclaire\u001b[0m\u001b[39m@yosyshq.com\u001b[0m\u001b[1m>\u001b[0m | \n"
+ ],
+ "text/html": [
+ "| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> | \n",
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+ "| Permission to use, copy, modify, and/or distribute this software for any | \n"
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+ "| Permission to use, copy, modify, and/or distribute this software for any | \n",
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+ "| copyright notice and this permission notice appear in all copies. | \n"
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+ "| THE SOFTWARE IS PROVIDED \u001b[32m\"AS IS\"\u001b[0m AND THE AUTHOR DISCLAIMS ALL WARRANTIES | \n"
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+ "| THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | \n",
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Loaded SDC plugin \n"
+ ],
+ "text/html": [
+ "Loaded SDC plugin \n",
+ "
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+ ]
+ },
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+ "text/html": [
+ "[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. \n",
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+ "\u001b[1;36m1\u001b[0m. Executing Liberty frontend: \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/\u001b[0m\u001b[95msky130_fd_sc_hd__tt_025C_1v80.lib\u001b[0m\n"
+ ],
+ "text/html": [
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+ {
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+ "Imported \u001b[1;36m428\u001b[0m cell types from liberty file. \n"
+ ],
+ "text/html": [
+ "Imported 428 cell types from liberty file. \n",
+ "
\n"
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+ "\u001b[1;36m2\u001b[0m. Executing Verilog-\u001b[1;36m2005\u001b[0m frontend: \u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m \n"
+ ],
+ "text/html": [
+ "2. Executing Verilog-2005 frontend: /content/core.v \n",
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+ "data": {
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+ "Generating RTLIL representation for module `\\BHT'. \n"
+ ],
+ "text/html": [
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+ },
+ "metadata": {}
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+ {
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+ ]
+ },
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+ {
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+ ]
+ },
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+ },
+ {
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+ ]
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+ "data": {
+ "text/plain": [
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+ "`\\BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BTB.$memwr$\\btbTable$/content/core.v:197$31_EN' using process \n",
+ "`\\BTB.$proc$/content/core.v:192$50'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2067\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2067' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m66\u001b[0m$1_ADDR' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$/content/core.v:66$1_ADDR' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2068\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2068' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m66\u001b[0m$1_DATA' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$/content/core.v:66$1_DATA' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2069\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2069' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m66\u001b[0m$1_EN' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_tag$/content/core.v:66$1_EN' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2070\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2070' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m69\u001b[0m$2_ADDR' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$/content/core.v:69$2_ADDR' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2071\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2071' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m69\u001b[0m$2_DATA' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$/content/core.v:69$2_DATA' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2072\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2072' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m69\u001b[0m$2_EN' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_valid$/content/core.v:69$2_EN' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2073\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2073' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m72\u001b[0m$3_ADDR' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$/content/core.v:72$3_ADDR' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2074\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2074' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m72\u001b[0m$3_DATA' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$/content/core.v:72$3_DATA' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2075\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2075' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m72\u001b[0m$3_EN' using process \n",
+ "`\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Creating register for signal `\\BHT.$memwr$\\bhtTable_target_pc$/content/core.v:72$3_EN' using process \n",
+ "`\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created $dff cell `$procdff$\u001b[1;36m2076\u001b[0m' with positive edge clock. \n"
+ ],
+ "text/html": [
+ "created $dff cell `$procdff$2076' with positive edge clock. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m16\u001b[0m. Executing PROC_MEMWR pass \u001b[1m(\u001b[0mconvert process memory writes to cells\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "16. Executing PROC_MEMWR pass (convert process memory writes to cells). \n",
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\n"
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+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
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+ "\u001b[1;36m17\u001b[0m. Executing PROC_CLEAN pass \u001b[1m(\u001b[0mremove empty switches from decision trees\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "17. Executing PROC_CLEAN pass (remove empty switches from decision trees). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ "Found and cleaned up \u001b[1;36m51\u001b[0m empty switches in `\\CSR.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2638\u001b[0m$\u001b[1;36m1025\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Found and cleaned up 51 empty switches in `\\CSR.$proc$/content/core.v:2638$1025'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Removing empty process `CSR.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2638\u001b[0m$\u001b[1;36m1025\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Removing empty process `CSR.$proc$/content/core.v:2638$1025'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found and cleaned up \u001b[1;36m28\u001b[0m empty switches in `\\Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Found and cleaned up 28 empty switches in `\\Memory.$proc$/content/core.v:2287$824'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Removing empty process `Memory.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2287\u001b[0m$\u001b[1;36m824\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Removing empty process `Memory.$proc$/content/core.v:2287$824'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ "Found and cleaned up \u001b[1;36m45\u001b[0m empty switches in `\\Execute.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1866\u001b[0m$\u001b[1;36m752\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Found and cleaned up 45 empty switches in `\\Execute.$proc$/content/core.v:1866$752'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
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+ ],
+ "text/html": [
+ "Removing empty process `Execute.$proc$/content/core.v:1866$752'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ {
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+ "data": {
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+ ],
+ "text/html": [
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+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Removing empty process `Decode.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1281\u001b[0m$\u001b[1;36m675\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Removing empty process `Decode.$proc$/content/core.v:1281$675'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Found and cleaned up \u001b[1;36m96\u001b[0m empty switches in `\\Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Found and cleaned up 96 empty switches in `\\Regfile.$proc$/content/core.v:629$392'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Removing empty process `Regfile.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m629\u001b[0m$\u001b[1;36m392\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Removing empty process `Regfile.$proc$/content/core.v:629$392'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Found and cleaned up \u001b[1;36m10\u001b[0m empty switches in `\\Fetch.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m323\u001b[0m$\u001b[1;36m70\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Found and cleaned up 10 empty switches in `\\Fetch.$proc$/content/core.v:323$70'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Removing empty process `Fetch.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m323\u001b[0m$\u001b[1;36m70\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Removing empty process `Fetch.$proc$/content/core.v:323$70'. \n",
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\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Found and cleaned up \u001b[1;36m2\u001b[0m empty switches in `\\BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Found and cleaned up 2 empty switches in `\\BTB.$proc$/content/core.v:192$50'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Removing empty process `BTB.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m192\u001b[0m$\u001b[1;36m50\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Removing empty process `BTB.$proc$/content/core.v:192$50'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found and cleaned up \u001b[1;36m3\u001b[0m empty switches in `\\BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Found and cleaned up 3 empty switches in `\\BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Removing empty process `BHT.$proc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m64\u001b[0m$\u001b[1;36m8\u001b[0m'. \n"
+ ],
+ "text/html": [
+ "Removing empty process `BHT.$proc$/content/core.v:64$8'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Cleaned up \u001b[1;36m293\u001b[0m empty switches. \n"
+ ],
+ "text/html": [
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+ "24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). \n",
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+ "24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). \n",
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+ "24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). \n",
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+ "\u001b[1;36m25.1\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n"
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+ "Optimizing module core. \n",
+ "
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+ " \n",
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+ "text/html": [
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+ "
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+ ],
+ "text/html": [
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+ "
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+ ]
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+ ],
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+ ],
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+ "Analyzing evaluation results. \n",
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+ },
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+ },
+ {
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+ ],
+ "text/html": [
+ "Removed 0 multiplexer ports. \n",
+ "
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+ ]
+ },
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+ },
+ {
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+ "data": {
+ "text/plain": [
+ "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m154\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n"
+ ],
+ "text/html": [
+ "<suppressed ~154 debug messages> \n",
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+ "text/html": [
+ " \n",
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+ "\u001b[1;36m25.4\u001b[0m. Executing OPT_REDUCE pass \u001b[1m(\u001b[0mconsolidate $*mux and $reduce_* inputs\u001b[1m)\u001b[0m. \n"
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+ "
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+ ],
+ "text/html": [
+ "Performed a total of 0 changes. \n",
+ "
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+ ]
+ },
+ "metadata": {}
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+ {
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+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
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+ ]
+ },
+ "metadata": {}
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+ {
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+ "\u001b[1;36m25.5\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "25.5. Executing OPT_MERGE pass (detect identical cells). \n",
+ "
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+ ]
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+ "
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+ ]
+ },
+ "metadata": {}
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+ "Removed a total of \u001b[1;36m0\u001b[0m cells. \n"
+ ],
+ "text/html": [
+ "Removed a total of 0 cells. \n",
+ "
\n"
+ ]
+ },
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+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
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+ "\u001b[1;36m25.6\u001b[0m. Executing OPT_DFF pass \u001b[1m(\u001b[0mperform DFF optimizations\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "25.6. Executing OPT_DFF pass (perform DFF optimizations). \n",
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+ ]
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+ "text/html": [
+ "Adding SRST signal on $flatten\\memory.$procdff$1976 ($dff) from module core (D = \\memory._GEN_32, Q = \n",
+ "\\memory.branch_reg, rval = 1'0). \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
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+ "data": {
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+ "\\decode.regfile.registers_1\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "\\decode.regfile.registers_1). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ "$flatten\\decode.\\regfile.$procmux$1868_Y, Q = \\decode.regfile.registers_0, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.\\regfile.$procdff$2027 ($dff) from module core (D = \n",
+ "$flatten\\decode.\\regfile.$procmux$1868_Y, Q = \\decode.regfile.registers_0, rval = 0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ {
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+ "\\decode.regfile.registers_0\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $auto$ff.cc:266:slice$2329 ($sdff) from module core (D = \\decode.regfile.io_writedata, Q = \n",
+ "\\decode.regfile.registers_0). \n",
+ "
\n"
+ ]
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+ "\\decode.id_ex_ex_use_rs2_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "
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+ "\\decode.id_ex_ex_use_rs1_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
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\n"
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+ "\\decode.id_ex_ex_rd_reg, rval = \u001b[1;36m5\u001b[0m'\u001b[1;36m00000\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
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+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ "\\decode.id_ex_ex_rs2_reg, rval = \u001b[1;36m5\u001b[0m'\u001b[1;36m00000\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "
\n"
+ ]
+ },
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+ "\\decode.id_ex_ex_rs1_reg, rval = \u001b[1;36m5\u001b[0m'\u001b[1;36m00000\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
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+ "
\n"
+ ]
+ },
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+ "\\decode.id_ex_funct3_reg, rval = \u001b[1;36m3\u001b[0m'\u001b[1;36m000\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "\\decode.id_ex_funct3_reg, rval = 3'000). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ ],
+ "text/html": [
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+ "\\decode.id_ex_imm_reg, rval = 0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ ],
+ "text/html": [
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+ "
\n"
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+ ],
+ "text/html": [
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+ "\\decode.id_ex_rs1_data_reg, rval = 0). \n",
+ "
\n"
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+ },
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+ "\\decode.id_ex_islui_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2017 ($dff) from module core (D = \\decode.control_io_islui, Q = \n",
+ "\\decode.id_ex_islui_reg, rval = 1'0). \n",
+ "
\n"
+ ]
+ },
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+ "\\decode.id_ex_isjump_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "\\decode.id_ex_isjump_reg, rval = 1'0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ "\\decode.id_ex_rdsel_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2015 ($dff) from module core (D = \\decode.control_io_rdsel, Q = \n",
+ "\\decode.id_ex_rdsel_reg, rval = 1'0). \n",
+ "
\n"
+ ]
+ },
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+ "\\decode.id_ex_pcsel_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2014 ($dff) from module core (D = \\decode.control_io_pcsel, Q = \n",
+ "\\decode.id_ex_pcsel_reg, rval = 1'0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ "\\decode.id_ex_memtoreg_reg, rval = \u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "\\decode.id_ex_memtoreg_reg, rval = 2'00). \n",
+ "
\n"
+ ]
+ },
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+ "\\decode.id_ex_regwrite_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2012 ($dff) from module core (D = \\decode.control_io_regwrite, Q = \n",
+ "\\decode.id_ex_regwrite_reg, rval = 1'0). \n",
+ "
\n"
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+ },
+ "metadata": {}
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+ "\\decode.id_ex_memwrite_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "
\n"
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+ },
+ "metadata": {}
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+ "\\decode.id_ex_memread_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2010 ($dff) from module core (D = \\decode.control_io_memread, Q = \n",
+ "\\decode.id_ex_memread_reg, rval = 1'0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ "Adding SRST signal on $flatten\\decode.$procdff$\u001b[1;36m2009\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\decode.control_io_isbranch, Q = \n",
+ "\\decode.id_ex_isbranch_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2009 ($dff) from module core (D = \\decode.control_io_isbranch, Q = \n",
+ "\\decode.id_ex_isbranch_reg, rval = 1'0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ "\\decode.id_ex_immsrc_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2008 ($dff) from module core (D = \\decode.control_io_immsrc, Q = \n",
+ "\\decode.id_ex_immsrc_reg, rval = 1'0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
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+ "= \\decode.id_ex_aluop_reg, rval = \u001b[1;36m4\u001b[0m'\u001b[1;36m0000\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2007 ($dff) from module core (D = \\decode.control._io_aluop_T_63, Q \n",
+ "= \\decode.id_ex_aluop_reg, rval = 4'0000). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "\\decode.id_ex_pc_reg, rval = \u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2006 ($dff) from module core (D = \\fetch.idPcReg, Q = \n",
+ "\\decode.id_ex_pc_reg, rval = 0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ "\\decode.wfi_out_reg, rval = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding SRST signal on $flatten\\decode.$procdff$2005 ($dff) from module core (D = \\decode.wfi_out, Q = \n",
+ "\\decode.wfi_out_reg, rval = 1'0). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "25.21. Executing OPT_CLEAN pass (remove unused cells and wires). \n",
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+ "creating $alu cell for $flatten\\fetch.\\btb.$sub$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m187\u001b[0m$\u001b[1;36m48\u001b[0m: $auto$alumacc.\u001b[1;92mcc:485\u001b[0m:replace_alu$\u001b[1;36m2566\u001b[0m \n"
+ ],
+ "text/html": [
+ "creating $alu cell for $flatten\\fetch.\\btb.$sub$/content/core.v:187$48: $auto$alumacc.cc:485:replace_alu$2566 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "creating $alu cell for $flatten\\hazard.$add$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m2895\u001b[0m$\u001b[1;36m1083\u001b[0m: $auto$alumacc.\u001b[1;92mcc:485\u001b[0m:replace_alu$\u001b[1;36m2569\u001b[0m \n"
+ ],
+ "text/html": [
+ "creating $alu cell for $flatten\\hazard.$add$/content/core.v:2895$1083: $auto$alumacc.cc:485:replace_alu$2569 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created \u001b[1;36m15\u001b[0m $alu and \u001b[1;36m0\u001b[0m $macc cells. \n"
+ ],
+ "text/html": [
+ "created 15 $alu and 0 $macc cells. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m30\u001b[0m. Executing SHARE pass \u001b[1m(\u001b[0mSAT-based resource sharing\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "30. Executing SHARE pass (SAT-based resource sharing). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found \u001b[1;36m7\u001b[0m cells in module core that may be considered for resource sharing. \n"
+ ],
+ "text/html": [
+ "Found 7 cells in module core that may be considered for resource sharing. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing resource sharing options for $flatten\\fetch.\\btb.$memrd$\\btbTable$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m170\u001b[0m$\u001b[1;36m37\u001b[0m \u001b[1m(\u001b[0m$memrd\u001b[1m)\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Analyzing resource sharing options for $flatten\\fetch.\\btb.$memrd$\\btbTable$/content/core.v:170$37 ($memrd): \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n",
+ "$flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m330\u001b[0m$72_Y \u001b[1m}\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Found 1 activation_patterns using ctrl signal { \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n",
+ "$flatten\\fetch.$and$/content/core.v:330$72_Y }. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "No candidates found. \n"
+ ],
+ "text/html": [
+ "No candidates found. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_valid$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m49\u001b[0m$\u001b[1;36m5\u001b[0m \u001b[1m(\u001b[0m$memrd\u001b[1m)\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_valid$/content/core.v:49$5 ($memrd): \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n",
+ "$flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m330\u001b[0m$72_Y \u001b[1m}\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Found 1 activation_patterns using ctrl signal { \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n",
+ "$flatten\\fetch.$and$/content/core.v:330$72_Y }. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "No candidates found. \n"
+ ],
+ "text/html": [
+ "No candidates found. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_target_pc$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m56\u001b[0m$\u001b[1;36m6\u001b[0m \n",
+ "\u001b[1m(\u001b[0m$memrd\u001b[1m)\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_target_pc$/content/core.v:56$6 \n",
+ "($memrd): \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n",
+ "$flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m290\u001b[0m$67_Y $flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m330\u001b[0m$72_Y \u001b[1m}\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Found 1 activation_patterns using ctrl signal { \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n",
+ "$flatten\\fetch.$and$/content/core.v:290$67_Y $flatten\\fetch.$and$/content/core.v:330$72_Y }. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "No candidates found. \n"
+ ],
+ "text/html": [
+ "No candidates found. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_tag$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m42\u001b[0m$\u001b[1;36m4\u001b[0m \u001b[1m(\u001b[0m$memrd\u001b[1m)\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Analyzing resource sharing options for $flatten\\fetch.\\bht.$memrd$\\bhtTable_tag$/content/core.v:42$4 ($memrd): \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n",
+ "$flatten\\fetch.$and$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m330\u001b[0m$72_Y \u001b[1m}\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Found 1 activation_patterns using ctrl signal { \\memory.trapped_reg \\memory.mret_out_reg \\fetch.io_if_id_stall \n",
+ "$flatten\\fetch.$and$/content/core.v:330$72_Y }. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "No candidates found. \n"
+ ],
+ "text/html": [
+ "No candidates found. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing resource sharing options for $flatten\\execute.\\alu.$sshr$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1626\u001b[0m$\u001b[1;36m705\u001b[0m \u001b[1m(\u001b[0m$sshr\u001b[1m)\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Analyzing resource sharing options for $flatten\\execute.\\alu.$sshr$/content/core.v:1626$705 ($sshr): \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1638\u001b[0m$726_Y \n",
+ "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1637\u001b[0m$724_Y $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1636\u001b[0m$722_Y \u001b[1m}\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Found 1 activation_patterns using ctrl signal { $flatten\\execute.\\alu.$eq$/content/core.v:1638$726_Y \n",
+ "$flatten\\execute.\\alu.$eq$/content/core.v:1637$724_Y $flatten\\execute.\\alu.$eq$/content/core.v:1636$722_Y }. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "No candidates found. \n"
+ ],
+ "text/html": [
+ "No candidates found. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing resource sharing options for $flatten\\execute.\\alu.$shr$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1625\u001b[0m$\u001b[1;36m704\u001b[0m \u001b[1m(\u001b[0m$shr\u001b[1m)\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Analyzing resource sharing options for $flatten\\execute.\\alu.$shr$/content/core.v:1625$704 ($shr): \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1638\u001b[0m$726_Y \n",
+ "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1637\u001b[0m$724_Y $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1636\u001b[0m$722_Y \n",
+ "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1635\u001b[0m$720_Y \u001b[1m}\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Found 1 activation_patterns using ctrl signal { $flatten\\execute.\\alu.$eq$/content/core.v:1638$726_Y \n",
+ "$flatten\\execute.\\alu.$eq$/content/core.v:1637$724_Y $flatten\\execute.\\alu.$eq$/content/core.v:1636$722_Y \n",
+ "$flatten\\execute.\\alu.$eq$/content/core.v:1635$720_Y }. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "No candidates found. \n"
+ ],
+ "text/html": [
+ "No candidates found. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing resource sharing options for $flatten\\execute.\\alu.$shl$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1624\u001b[0m$\u001b[1;36m703\u001b[0m \u001b[1m(\u001b[0m$shl\u001b[1m)\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Analyzing resource sharing options for $flatten\\execute.\\alu.$shl$/content/core.v:1624$703 ($shl): \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Found \u001b[1;36m1\u001b[0m activation_patterns using ctrl signal \u001b[1m{\u001b[0m $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1638\u001b[0m$726_Y \n",
+ "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1637\u001b[0m$724_Y $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1636\u001b[0m$722_Y \n",
+ "$flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1635\u001b[0m$720_Y $flatten\\execute.\\alu.$eq$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1634\u001b[0m$718_Y \u001b[1m}\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Found 1 activation_patterns using ctrl signal { $flatten\\execute.\\alu.$eq$/content/core.v:1638$726_Y \n",
+ "$flatten\\execute.\\alu.$eq$/content/core.v:1637$724_Y $flatten\\execute.\\alu.$eq$/content/core.v:1636$722_Y \n",
+ "$flatten\\execute.\\alu.$eq$/content/core.v:1635$720_Y $flatten\\execute.\\alu.$eq$/content/core.v:1634$718_Y }. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "No candidates found. \n"
+ ],
+ "text/html": [
+ "No candidates found. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m31\u001b[0m. Executing OPT pass \u001b[1m(\u001b[0mperforming simple optimizations\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "31. Executing OPT pass (performing simple optimizations). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m31.1\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "31.1. Executing OPT_EXPR pass (perform const folding). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Optimizing module core. \n"
+ ],
+ "text/html": [
+ "Optimizing module core. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m31.2\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "31.2. Executing OPT_MERGE pass (detect identical cells). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Finding identical cells in module `\\core'. \n"
+ ],
+ "text/html": [
+ "Finding identical cells in module `\\core'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Removed a total of \u001b[1;36m0\u001b[0m cells. \n"
+ ],
+ "text/html": [
+ "Removed a total of 0 cells. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m31.3\u001b[0m. Executing OPT_MUXTREE pass \u001b[1m(\u001b[0mdetect dead branches in mux trees\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "31.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Running muxtree optimizer on module \\core.. \n"
+ ],
+ "text/html": [
+ "Running muxtree optimizer on module \\core.. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating internal representation of mux trees. \n"
+ ],
+ "text/html": [
+ "Creating internal representation of mux trees. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Evaluating internal representation of mux trees. \n"
+ ],
+ "text/html": [
+ "Evaluating internal representation of mux trees. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing evaluation results. \n"
+ ],
+ "text/html": [
+ "Analyzing evaluation results. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Removed \u001b[1;36m0\u001b[0m multiplexer ports. \n"
+ ],
+ "text/html": [
+ "Removed 0 multiplexer ports. \n",
+ "
\n"
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+ ],
+ "text/html": [
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+ ],
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+ "Removed 2 unused cells and 2 unused wires. \n",
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+ "text/html": [
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+ "\u001b[1;36m34.7\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n"
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+ "text/html": [
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+ "metadata": {}
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+ ],
+ "text/html": [
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\n"
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+ "text/html": [
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+ {
+ "output_type": "display_data",
+ "data": {
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+ " \n"
+ ],
+ "text/html": [
+ " \n",
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+ {
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+ "text/plain": [
+ "\u001b[1;36m34.9\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n"
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+ "text/html": [
+ "34.9. Executing OPT_CLEAN pass (remove unused cells and wires). \n",
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+ ]
+ },
+ "metadata": {}
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+ ],
+ "text/html": [
+ "Finding unused cells or wires in module \\core.. \n",
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+ },
+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
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+ "\u001b[1;36m34.10\u001b[0m. Finished fast OPT passes. \n"
+ ],
+ "text/html": [
+ "34.10. Finished fast OPT passes. \n",
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+ },
+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
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+ },
+ "metadata": {}
+ },
+ {
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+ "\u001b[1;36m35\u001b[0m. Executing MEMORY_MAP pass \u001b[1m(\u001b[0mconverting memories to logic and flip-flops\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "35. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Mapping memory \\fetch.bht.bhtTable_tag in module \\core: \n"
+ ],
+ "text/html": [
+ "Mapping memory \\fetch.bht.bhtTable_tag in module \\core: \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created \u001b[1;36m16\u001b[0m $dff cells and \u001b[1;36m0\u001b[0m static cells of width \u001b[1;36m26\u001b[0m. \n"
+ ],
+ "text/html": [
+ "created 16 $dff cells and 0 static cells of width 26. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracted addr FF from read port \u001b[1;36m0\u001b[0m of core.fetch.bht.bhtTable_tag: $\\fetch.bht.bhtTable_tag$rdreg\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "Extracted addr FF from read port 0 of core.fetch.bht.bhtTable_tag: $\\fetch.bht.bhtTable_tag$rdreg[0] \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "read interface: \u001b[1;36m1\u001b[0m $dff and \u001b[1;36m15\u001b[0m $mux cells. \n"
+ ],
+ "text/html": [
+ "read interface: 1 $dff and 15 $mux cells. \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "write interface: \u001b[1;36m16\u001b[0m write mux blocks. \n"
+ ],
+ "text/html": [
+ "write interface: 16 write mux blocks. \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Mapping memory \\fetch.bht.bhtTable_target_pc in module \\core: \n"
+ ],
+ "text/html": [
+ "Mapping memory \\fetch.bht.bhtTable_target_pc in module \\core: \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created \u001b[1;36m16\u001b[0m $dff cells and \u001b[1;36m0\u001b[0m static cells of width \u001b[1;36m32\u001b[0m. \n"
+ ],
+ "text/html": [
+ "created 16 $dff cells and 0 static cells of width 32. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracted addr FF from read port \u001b[1;36m0\u001b[0m of core.fetch.bht.bhtTable_target_pc: $\\fetch.bht.bhtTable_target_pc$rdreg\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "Extracted addr FF from read port 0 of core.fetch.bht.bhtTable_target_pc: $\\fetch.bht.bhtTable_target_pc$rdreg[0] \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "read interface: \u001b[1;36m1\u001b[0m $dff and \u001b[1;36m15\u001b[0m $mux cells. \n"
+ ],
+ "text/html": [
+ "read interface: 1 $dff and 15 $mux cells. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "write interface: \u001b[1;36m16\u001b[0m write mux blocks. \n"
+ ],
+ "text/html": [
+ "write interface: 16 write mux blocks. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Mapping memory \\fetch.bht.bhtTable_valid in module \\core: \n"
+ ],
+ "text/html": [
+ "Mapping memory \\fetch.bht.bhtTable_valid in module \\core: \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created \u001b[1;36m16\u001b[0m $dff cells and \u001b[1;36m0\u001b[0m static cells of width \u001b[1;36m1\u001b[0m. \n"
+ ],
+ "text/html": [
+ "created 16 $dff cells and 0 static cells of width 1. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracted addr FF from read port \u001b[1;36m0\u001b[0m of core.fetch.bht.bhtTable_valid: $\\fetch.bht.bhtTable_valid$rdreg\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "Extracted addr FF from read port 0 of core.fetch.bht.bhtTable_valid: $\\fetch.bht.bhtTable_valid$rdreg[0] \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "read interface: \u001b[1;36m1\u001b[0m $dff and \u001b[1;36m15\u001b[0m $mux cells. \n"
+ ],
+ "text/html": [
+ "read interface: 1 $dff and 15 $mux cells. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "write interface: \u001b[1;36m16\u001b[0m write mux blocks. \n"
+ ],
+ "text/html": [
+ "write interface: 16 write mux blocks. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Mapping memory \\fetch.btb.btbTable in module \\core: \n"
+ ],
+ "text/html": [
+ "Mapping memory \\fetch.btb.btbTable in module \\core: \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "created \u001b[1;36m16\u001b[0m $dff cells and \u001b[1;36m0\u001b[0m static cells of width \u001b[1;36m2\u001b[0m. \n"
+ ],
+ "text/html": [
+ "created 16 $dff cells and 0 static cells of width 2. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracted addr FF from read port \u001b[1;36m0\u001b[0m of core.fetch.btb.btbTable: $\\fetch.btb.btbTable$rdreg\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "Extracted addr FF from read port 0 of core.fetch.btb.btbTable: $\\fetch.btb.btbTable$rdreg[0] \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracted addr FF from read port \u001b[1;36m1\u001b[0m of core.fetch.btb.btbTable: $\\fetch.btb.btbTable$rdreg\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "Extracted addr FF from read port 1 of core.fetch.btb.btbTable: $\\fetch.btb.btbTable$rdreg[1] \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "read interface: \u001b[1;36m2\u001b[0m $dff and \u001b[1;36m30\u001b[0m $mux cells. \n"
+ ],
+ "text/html": [
+ "read interface: 2 $dff and 30 $mux cells. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "write interface: \u001b[1;36m16\u001b[0m write mux blocks. \n"
+ ],
+ "text/html": [
+ "write interface: 16 write mux blocks. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m36\u001b[0m. Executing OPT pass \u001b[1m(\u001b[0mperforming simple optimizations\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "36. Executing OPT pass (performing simple optimizations). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m36.1\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "36.1. Executing OPT_EXPR pass (perform const folding). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Optimizing module core. \n"
+ ],
+ "text/html": [
+ "Optimizing module core. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m24\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n"
+ ],
+ "text/html": [
+ "<suppressed ~24 debug messages> \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m36.2\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "36.2. Executing OPT_MERGE pass (detect identical cells). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Finding identical cells in module `\\core'. \n"
+ ],
+ "text/html": [
+ "Finding identical cells in module `\\core'. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m105\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n"
+ ],
+ "text/html": [
+ "<suppressed ~105 debug messages> \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Removed a total of \u001b[1;36m35\u001b[0m cells. \n"
+ ],
+ "text/html": [
+ "Removed a total of 35 cells. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m36.3\u001b[0m. Executing OPT_MUXTREE pass \u001b[1m(\u001b[0mdetect dead branches in mux trees\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Running muxtree optimizer on module \\core.. \n"
+ ],
+ "text/html": [
+ "Running muxtree optimizer on module \\core.. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating internal representation of mux trees. \n"
+ ],
+ "text/html": [
+ "Creating internal representation of mux trees. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Evaluating internal representation of mux trees. \n"
+ ],
+ "text/html": [
+ "Evaluating internal representation of mux trees. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Analyzing evaluation results. \n"
+ ],
+ "text/html": [
+ "Analyzing evaluation results. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Removed \u001b[1;36m0\u001b[0m multiplexer ports. \n"
+ ],
+ "text/html": [
+ "Removed 0 multiplexer ports. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m105\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n"
+ ],
+ "text/html": [
+ "<suppressed ~105 debug messages> \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m36.4\u001b[0m. Executing OPT_REDUCE pass \u001b[1m(\u001b[0mconsolidate $*mux and $reduce_* inputs\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Optimizing cells in module \\core. \n"
+ ],
+ "text/html": [
+ "Optimizing cells in module \\core. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Consolidated identical input bits for $mux cell $flatten\\decode.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m1203\u001b[0m$\u001b[1;36m673\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Consolidated identical input bits for $mux cell $flatten\\decode.$ternary$/content/core.v:1203$673: \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Old ports: \u001b[33mA\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m10\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m, \u001b[33mY\u001b[0m=\\decode.ecause_out \n"
+ ],
+ "text/html": [
+ "Old ports: A=2'10, B=2'00, Y=\\decode.ecause_out \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "New ports: \u001b[33mA\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m1\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m, \u001b[33mY\u001b[0m=\\decode.ecause_out \u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "New ports: A=1'1, B=1'0, Y=\\decode.ecause_out [1] \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "New connections: \\decode.ecause_out \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m \n"
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+ "text/html": [
+ "New connections: \\decode.ecause_out [0] = 1'0 \n",
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+ "text/plain": [
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+ ],
+ "text/html": [
+ "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:427$95: \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Old ports: \u001b[33mA\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m10\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_aluop_T_29 \n"
+ ],
+ "text/html": [
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "New ports: \u001b[33mA\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m1\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_aluop_T_29 \u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "New ports: A=1'0, B=1'1, Y=\\decode.control._io_aluop_T_29 [1] \n",
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\n"
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+ },
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+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "New connections: \\decode.control._io_aluop_T_29 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m = \u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m \n"
+ ],
+ "text/html": [
+ "New connections: \\decode.control._io_aluop_T_29 [0] = 1'0 \n",
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\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m447\u001b[0m$\u001b[1;36m145\u001b[0m: \n"
+ ],
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+ "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:447$145: \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Old ports: \u001b[33mA\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m11\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_3 \n"
+ ],
+ "text/html": [
+ "Old ports: A=2'00, B=2'11, Y=\\decode.control._io_memtoreg_T_3 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "New ports: \u001b[33mA\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m0\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m1\u001b[0m'\u001b[1;36m1\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_3 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "New ports: A=1'0, B=1'1, Y=\\decode.control._io_memtoreg_T_3 [0] \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "New connections: \\decode.control._io_memtoreg_T_3 \u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m = \\decode.control._io_memtoreg_T_3 \u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m \n"
+ ],
+ "text/html": [
+ "New connections: \\decode.control._io_memtoreg_T_3 [1] = \\decode.control._io_memtoreg_T_3 [0] \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$\u001b[35m/content/\u001b[0m\u001b[95mcore.v\u001b[0m:\u001b[1;36m453\u001b[0m$\u001b[1;36m157\u001b[0m: \n"
+ ],
+ "text/html": [
+ "Consolidated identical input bits for $mux cell $flatten\\decode.\\control.$ternary$/content/core.v:453$157: \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Old ports: \u001b[33mA\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m00\u001b[0m, \u001b[33mB\u001b[0m=\u001b[1;36m2\u001b[0m'\u001b[1;36m10\u001b[0m, \u001b[33mY\u001b[0m=\\decode.control._io_memtoreg_T_15 \n"
+ ],
+ "text/html": [
+ "Old ports: A=2'00, B=2'10, Y=\\decode.control._io_memtoreg_T_15 \n",
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\n"
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\n"
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\n"
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\n"
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\n"
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\n"
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+ "\u001b[1;36m36.5\u001b[0m. Executing OPT_MERGE pass \u001b[1m(\u001b[0mdetect identical cells\u001b[1m)\u001b[0m. \n"
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+ "
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+ "
\n"
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+ "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m6\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n"
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+ "text/html": [
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+ "Removed a total of 2 cells. \n",
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+ "\u001b[1;36m36.6\u001b[0m. Executing OPT_SHARE pass. \n"
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+ "36.6. Executing OPT_SHARE pass. \n",
+ "
\n"
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+ "\u001b[1;36m36.7\u001b[0m. Executing OPT_DFF pass \u001b[1m(\u001b[0mperform DFF optimizations\u001b[1m)\u001b[0m. \n"
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+ "Adding SRST signal on $\\fetch.btb.btbTable$rdreg[0] ($dff) from module core (D = \\decode.id_ex_pc_reg [5:2], Q = \n",
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\n"
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+ "\u001b[1;36m36.9\u001b[0m. Executing OPT_EXPR pass \u001b[1m(\u001b[0mperform const folding\u001b[1m)\u001b[0m. \n"
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+ "Removed 0 multiplexer ports. \n",
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+ "Consolidated identical input bits for $mux cell $auto$opt_share.\u001b[1;92mcc:244\u001b[0m:merge_operators$\u001b[1;36m3372\u001b[0m: \n"
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+ "\u001b[1m<\u001b[0m\u001b[1;95msuppressed\u001b[0m\u001b[39m ~\u001b[0m\u001b[1;36m21\u001b[0m\u001b[39m debug messages\u001b[0m\u001b[1m>\u001b[0m \n"
+ ],
+ "text/html": [
+ "<suppressed ~21 debug messages> \n",
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\n"
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+ "Removed a total of \u001b[1;36m7\u001b[0m cells. \n"
+ ],
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+ "Removed a total of 7 cells. \n",
+ "
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+ "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
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+ "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "
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+ "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
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+ "
\n"
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+ "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
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+ "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
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+ "
\n"
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+ "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
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+ "
\n"
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+ "Q = \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "
\n"
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+ "= \\fetch.btb.btbTable\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
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+ "
\n"
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+ "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
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+ "
\n"
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+ ],
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+ ],
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+ "
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+ ],
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+ "
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+ "
\n"
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+ ],
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\n"
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\n"
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+ "data": {
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+ "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2921\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n",
+ "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[10]$2921 ($dff) from module core (D = \n",
+ "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[10]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2901\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \n",
+ "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_target_pc[0]$2901 ($dff) from module core (D = \n",
+ "\\execute.target_pc_reg, Q = \\fetch.bht.bhtTable_target_pc[0]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2714\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m9\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[9]$2714 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[9]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m8\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2712\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m8\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[8]$2712 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[8]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2710\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m7\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[7]$2710 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[7]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m6\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2708\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m6\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[6]$2708 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[6]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m5\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2706\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m5\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[5]$2706 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[5]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2704\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m4\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[4]$2704 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[4]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2702\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m3\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[3]$2702 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[3]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2700\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m2\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[2]$2700 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[2]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2698\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m1\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[1]$2698 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[1]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2726\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n",
+ "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m15\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[15]$2726 ($dff) from module core (D = \\execute.mem_pc_reg \n",
+ "[31:6], Q = \\fetch.bht.bhtTable_tag[15]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2724\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n",
+ "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m14\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[14]$2724 ($dff) from module core (D = \\execute.mem_pc_reg \n",
+ "[31:6], Q = \\fetch.bht.bhtTable_tag[14]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2722\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n",
+ "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m13\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[13]$2722 ($dff) from module core (D = \\execute.mem_pc_reg \n",
+ "[31:6], Q = \\fetch.bht.bhtTable_tag[13]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2720\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n",
+ "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m12\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[12]$2720 ($dff) from module core (D = \\execute.mem_pc_reg \n",
+ "[31:6], Q = \\fetch.bht.bhtTable_tag[12]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2718\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n",
+ "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m11\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[11]$2718 ($dff) from module core (D = \\execute.mem_pc_reg \n",
+ "[31:6], Q = \\fetch.bht.bhtTable_tag[11]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2716\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \n",
+ "\u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m, Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m10\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[10]$2716 ($dff) from module core (D = \\execute.mem_pc_reg \n",
+ "[31:6], Q = \\fetch.bht.bhtTable_tag[10]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m$\u001b[1;36m2696\u001b[0m \u001b[1m(\u001b[0m$dff\u001b[1m)\u001b[0m from module core \u001b[1m(\u001b[0mD = \\execute.mem_pc_reg \u001b[1m[\u001b[0m\u001b[1;92m31:6\u001b[0m\u001b[1m]\u001b[0m,\n",
+ "Q = \\fetch.bht.bhtTable_tag\u001b[1m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1m]\u001b[0m\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Adding EN signal on $memory\\fetch.bht.bhtTable_tag[0]$2696 ($dff) from module core (D = \\execute.mem_pc_reg [31:6],\n",
+ "Q = \\fetch.bht.bhtTable_tag[0]). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Setting constant \u001b[1;36m0\u001b[0m-bit at position \u001b[1;36m0\u001b[0m on $auto$ff.\u001b[1;92mcc:266\u001b[0m:slice$\u001b[1;36m2405\u001b[0m \u001b[1m(\u001b[0m$sdff\u001b[1m)\u001b[0m from module core. \n"
+ ],
+ "text/html": [
+ "Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2405 ($sdff) from module core. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m36.16\u001b[0m. Executing OPT_CLEAN pass \u001b[1m(\u001b[0mremove unused cells and wires\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "36.16. Executing OPT_CLEAN pass (remove unused cells and wires). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Finding unused cells or wires in module \\core.. \n"
+ ],
+ "text/html": [
+ "Finding unused cells or wires in module \\core.. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Removed \u001b[1;36m48\u001b[0m unused cells and \u001b[1;36m62\u001b[0m unused wires. \n"
+ ],
+ "text/html": [
+ "Removed 48 unused cells and 62 unused wires. \n",
+ "
\n"
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\n"
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\n"
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+ "\u001b[1;36m39.1\u001b[0m. Extracting gate netlist of module `\\core' to `\u001b[1m<\u001b[0m\u001b[1;95mabc-temp-dir\u001b[0m\u001b[1m>\u001b[0m\u001b[35m/\u001b[0m\u001b[95minput.blif\u001b[0m'.. \n"
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\n"
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\n"
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+ "data": {
+ "text/plain": [
+ "Extracted \u001b[1;36m9926\u001b[0m gates and \u001b[1;36m12771\u001b[0m wires to a netlist network with \u001b[1;36m2842\u001b[0m inputs and \u001b[1;36m633\u001b[0m outputs. \n"
+ ],
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+ "Extracted 9926 gates and 12771 wires to a netlist network with 2842 inputs and 633 outputs. \n",
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\n"
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+ "text/html": [
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\n"
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+ "\u001b[1m<\u001b[0m\u001b[1;95mabc-temp-dir\u001b[0m\u001b[1m>\u001b[0m\u001b[35m/\u001b[0m\u001b[95mabc.script\u001b[0m \u001b[1;36m2\u001b[0m>&\u001b[1;36m1\u001b[0m \n"
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+ "<abc-temp-dir>/abc.script 2>&1 \n",
+ "
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+ },
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+ "text/html": [
+ "ABC: \n",
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+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: + read_blif \u001b[1m<\u001b[0m\u001b[1;95mabc-temp-dir\u001b[0m\u001b[1m>\u001b[0m\u001b[35m/\u001b[0m\u001b[95minput.blif\u001b[0m \n"
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+ },
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+ "data": {
+ "text/plain": [
+ "ABC: + read_library \u001b[1m<\u001b[0m\u001b[1;95mabc-temp-dir\u001b[0m\u001b[1m>\u001b[0m\u001b[35m/\u001b[0m\u001b[95mstdcells.genlib\u001b[0m \n"
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+ "text/html": [
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Entered genlib library with \u001b[1;36m13\u001b[0m gates from file \u001b[32m\"\u001b[0m\u001b[32m<\u001b[0m\u001b[32mabc-temp-dir\u001b[0m\u001b[32m>\u001b[0m\u001b[32m/stdcells.genlib\"\u001b[0m. \n"
+ ],
+ "text/html": [
+ "ABC: Entered genlib library with 13 gates from file \"<abc-temp-dir>/stdcells.genlib\". \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: + strash \n"
+ ],
+ "text/html": [
+ "ABC: + strash \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: + dretime \n"
+ ],
+ "text/html": [
+ "ABC: + dretime \n",
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+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
+ "text/plain": [
+ "ABC: + map \n"
+ ],
+ "text/html": [
+ "ABC: + map \n",
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: + write_blif \u001b[1m<\u001b[0m\u001b[1;95mabc-temp-dir\u001b[0m\u001b[1m>\u001b[0m\u001b[35m/\u001b[0m\u001b[95moutput.blif\u001b[0m \n"
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+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "ABC RESULTS: MUX cells: 6225 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ "text/html": [
+ "ABC RESULTS: NOT cells: 534 \n",
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+ "text/html": [
+ "ABC RESULTS: NAND cells: 200 \n",
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\n"
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+ "metadata": {}
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+ "text/html": [
+ "ABC RESULTS: ORNOT cells: 188 \n",
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\n"
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+ "text/html": [
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\n"
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+ "metadata": {}
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+ "text/html": [
+ "ABC RESULTS: AND cells: 230 \n",
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\n"
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+ "metadata": {}
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+ {
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+ "text/html": [
+ "ABC RESULTS: XNOR cells: 51 \n",
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\n"
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+ "text/html": [
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\n"
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+ "text/html": [
+ "ABC RESULTS: ANDNOT cells: 1006 \n",
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\n"
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+ "text/html": [
+ "ABC RESULTS: OR cells: 1033 \n",
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\n"
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC RESULTS: internal signals: \u001b[1;36m9296\u001b[0m \n"
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+ "text/html": [
+ "ABC RESULTS: internal signals: 9296 \n",
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\n"
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+ "metadata": {}
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+ {
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+ "text/plain": [
+ "ABC RESULTS: input signals: \u001b[1;36m2842\u001b[0m \n"
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+ "text/html": [
+ "ABC RESULTS: input signals: 2842 \n",
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\n"
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+ "data": {
+ "text/plain": [
+ "ABC RESULTS: output signals: \u001b[1;36m633\u001b[0m \n"
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+ "text/html": [
+ "ABC RESULTS: output signals: 633 \n",
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\n"
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+ },
+ "metadata": {}
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+ "data": {
+ "text/plain": [
+ "Removing temp directory. \n"
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+ "text/html": [
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+ "ABC: Path \u001b[1;36m9\u001b[0m -- \u001b[1;36m7004\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m2136.5\u001b[0m \u001b[1;36m-161.2\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 9 -- 7004 : 3 3 sky130_fd_sc_hd__and3_2 A = 7.51 Df =2136.5 -161.2 ps S = 66.8 ps Cin = \n",
+ "1.5 ff Cout = 7.9 ff Cmax = 309.5 ff G = 498 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m10\u001b[0m -- \u001b[1;36m7005\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m2359.8\u001b[0m \u001b[1;36m-194.7\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 10 -- 7005 : 2 4 sky130_fd_sc_hd__and2_2 A = 7.51 Df =2359.8 -194.7 ps S = 101.8 ps Cin = \n",
+ "1.5 ff Cout = 16.7 ff Cmax = 303.0 ff G = 1102 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m11\u001b[0m -- \u001b[1;36m7006\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m2586.6\u001b[0m \u001b[1;36m-216.7\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 11 -- 7006 : 3 3 sky130_fd_sc_hd__and3_2 A = 7.51 Df =2586.6 -216.7 ps S = 66.8 ps Cin = \n",
+ "1.5 ff Cout = 7.9 ff Cmax = 309.5 ff G = 498 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m12\u001b[0m -- \u001b[1;36m7007\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m2809.9\u001b[0m \u001b[1;36m-250.3\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 12 -- 7007 : 2 4 sky130_fd_sc_hd__and2_2 A = 7.51 Df =2809.9 -250.3 ps S = 101.8 ps Cin = \n",
+ "1.5 ff Cout = 16.7 ff Cmax = 303.0 ff G = 1102 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m13\u001b[0m -- \u001b[1;36m7008\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3036.8\u001b[0m \u001b[1;36m-272.2\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 13 -- 7008 : 3 3 sky130_fd_sc_hd__and3_2 A = 7.51 Df =3036.8 -272.2 ps S = 66.8 ps Cin = \n",
+ "1.5 ff Cout = 7.9 ff Cmax = 309.5 ff G = 498 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m14\u001b[0m -- \u001b[1;36m7009\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3260.1\u001b[0m \u001b[1;36m-305.8\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 14 -- 7009 : 2 4 sky130_fd_sc_hd__and2_2 A = 7.51 Df =3260.1 -305.8 ps S = 101.8 ps Cin = \n",
+ "1.5 ff Cout = 16.7 ff Cmax = 303.0 ff G = 1102 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m15\u001b[0m -- \u001b[1;36m7010\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3486.9\u001b[0m \u001b[1;36m-327.7\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 15 -- 7010 : 3 3 sky130_fd_sc_hd__and3_2 A = 7.51 Df =3486.9 -327.7 ps S = 66.8 ps Cin = \n",
+ "1.5 ff Cout = 7.9 ff Cmax = 309.5 ff G = 498 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m16\u001b[0m -- \u001b[1;36m7011\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m4\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3710.2\u001b[0m \u001b[1;36m-361.3\u001b[0m ps S = \u001b[1;36m101.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m16.7\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m1102\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 16 -- 7011 : 2 4 sky130_fd_sc_hd__and2_2 A = 7.51 Df =3710.2 -361.3 ps S = 101.8 ps Cin = \n",
+ "1.5 ff Cout = 16.7 ff Cmax = 303.0 ff G = 1102 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m17\u001b[0m -- \u001b[1;36m7012\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and3_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m3937.1\u001b[0m \u001b[1;36m-383.2\u001b[0m ps S = \u001b[1;36m66.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m309.5\u001b[0m ff G = \u001b[1;36m498\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 17 -- 7012 : 3 3 sky130_fd_sc_hd__and3_2 A = 7.51 Df =3937.1 -383.2 ps S = 66.8 ps Cin = \n",
+ "1.5 ff Cout = 7.9 ff Cmax = 309.5 ff G = 498 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m18\u001b[0m -- \u001b[1;36m7013\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m3\u001b[0m sky130_fd_sc_hd__and2_2 A = \u001b[1;36m7.51\u001b[0m Df =\u001b[1;36m4137.4\u001b[0m \u001b[1;36m-427.1\u001b[0m ps S = \u001b[1;36m61.4\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.9\u001b[0m ff Cmax = \u001b[1;36m303.0\u001b[0m ff G = \u001b[1;36m520\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 18 -- 7013 : 2 3 sky130_fd_sc_hd__and2_2 A = 7.51 Df =4137.4 -427.1 ps S = 61.4 ps Cin = \n",
+ "1.5 ff Cout = 7.9 ff Cmax = 303.0 ff G = 520 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m19\u001b[0m -- \u001b[1;36m7080\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m2\u001b[0m sky130_fd_sc_hd__or2_2 A = \u001b[1;36m6.26\u001b[0m Df =\u001b[1;36m4443.6\u001b[0m \u001b[1;36m-333.6\u001b[0m ps S = \u001b[1;36m66.9\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m7.2\u001b[0m ff Cmax = \u001b[1;36m299.4\u001b[0m ff G = \u001b[1;36m469\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 19 -- 7080 : 2 2 sky130_fd_sc_hd__or2_2 A = 6.26 Df =4443.6 -333.6 ps S = 66.9 ps Cin = \n",
+ "1.5 ff Cout = 7.2 ff Cmax = 299.4 ff G = 469 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m20\u001b[0m -- \u001b[1;36m7093\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m1\u001b[0m sky130_fd_sc_hd__a21bo_2 A = \u001b[1;36m10.01\u001b[0m Df =\u001b[1;36m4650.7\u001b[0m \u001b[1;36m-430.1\u001b[0m ps S = \u001b[1;36m30.8\u001b[0m ps Cin = \n",
+ "\u001b[1;36m2.0\u001b[0m ff Cout = \u001b[1;36m1.6\u001b[0m ff Cmax = \u001b[1;36m288.4\u001b[0m ff G = \u001b[1;36m74\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 20 -- 7093 : 3 1 sky130_fd_sc_hd__a21bo_2 A = 10.01 Df =4650.7 -430.1 ps S = 30.8 ps Cin = \n",
+ "2.0 ff Cout = 1.6 ff Cmax = 288.4 ff G = 74 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m21\u001b[0m -- \u001b[1;36m7102\u001b[0m : \u001b[1;36m4\u001b[0m \u001b[1;36m1\u001b[0m sky130_fd_sc_hd__or4_2 A = \u001b[1;36m8.76\u001b[0m Df =\u001b[1;36m5241.0\u001b[0m \u001b[1;36m-626.3\u001b[0m ps S = \u001b[1;36m95.5\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m2.5\u001b[0m ff Cmax = \u001b[1;36m310.4\u001b[0m ff G = \u001b[1;36m158\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 21 -- 7102 : 4 1 sky130_fd_sc_hd__or4_2 A = 8.76 Df =5241.0 -626.3 ps S = 95.5 ps Cin = \n",
+ "1.5 ff Cout = 2.5 ff Cmax = 310.4 ff G = 158 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m22\u001b[0m -- \u001b[1;36m7103\u001b[0m : \u001b[1;36m3\u001b[0m \u001b[1;36m2\u001b[0m sky130_fd_sc_hd__o21ba_2 A = \u001b[1;36m10.01\u001b[0m Df =\u001b[1;36m5449.5\u001b[0m \u001b[1;36m-656.0\u001b[0m ps S = \u001b[1;36m38.0\u001b[0m ps Cin = \n",
+ "\u001b[1;36m2.1\u001b[0m ff Cout = \u001b[1;36m3.2\u001b[0m ff Cmax = \u001b[1;36m264.6\u001b[0m ff G = \u001b[1;36m147\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 22 -- 7103 : 3 2 sky130_fd_sc_hd__o21ba_2 A = 10.01 Df =5449.5 -656.0 ps S = 38.0 ps Cin = \n",
+ "2.1 ff Cout = 3.2 ff Cmax = 264.6 ff G = 147 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m23\u001b[0m -- \u001b[1;36m7104\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m2\u001b[0m sky130_fd_sc_hd__or2_2 A = \u001b[1;36m6.26\u001b[0m Df =\u001b[1;36m5727.3\u001b[0m \u001b[1;36m-829.2\u001b[0m ps S = \u001b[1;36m67.5\u001b[0m ps Cin = \n",
+ "\u001b[1;36m1.5\u001b[0m ff Cout = \u001b[1;36m6.2\u001b[0m ff Cmax = \u001b[1;36m299.4\u001b[0m ff G = \u001b[1;36m403\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 23 -- 7104 : 2 2 sky130_fd_sc_hd__or2_2 A = 6.26 Df =5727.3 -829.2 ps S = 67.5 ps Cin = \n",
+ "1.5 ff Cout = 6.2 ff Cmax = 299.4 ff G = 403 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m24\u001b[0m -- \u001b[1;36m7105\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m252\u001b[0m sky130_fd_sc_hd__nor2_2 A = \u001b[1;36m6.26\u001b[0m Df =\u001b[1;36m9384.2\u001b[0m-\u001b[1;36m3709.0\u001b[0m ps S =\u001b[1;36m4983.1\u001b[0m ps Cin = \n",
+ "\u001b[1;36m4.4\u001b[0m ff Cout = \u001b[1;36m488.5\u001b[0m ff Cmax = \u001b[1;36m141.9\u001b[0m ff G =\u001b[1;36m10674\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 24 -- 7105 : 2 252 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =9384.2-3709.0 ps S =4983.1 ps Cin = \n",
+ "4.4 ff Cout = 488.5 ff Cmax = 141.9 ff G =10674 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m25\u001b[0m -- \u001b[1;36m7106\u001b[0m : \u001b[1;36m1\u001b[0m \u001b[1;36m45\u001b[0m sky130_fd_sc_hd__inv_2 A = \u001b[1;36m3.75\u001b[0m Df =\u001b[1;36m11119.0\u001b[0m-\u001b[1;36m4325.9\u001b[0m ps S =\u001b[1;36m1322.2\u001b[0m ps Cin = \n",
+ "\u001b[1;36m4.5\u001b[0m ff Cout = \u001b[1;36m211.8\u001b[0m ff Cmax = \u001b[1;36m331.4\u001b[0m ff G = \u001b[1;36m4468\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 25 -- 7106 : 1 45 sky130_fd_sc_hd__inv_2 A = 3.75 Df =11119.0-4325.9 ps S =1322.2 ps Cin = \n",
+ "4.5 ff Cout = 211.8 ff Cmax = 331.4 ff G = 4468 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m26\u001b[0m -- \u001b[1;36m11086\u001b[0m : \u001b[1;36m2\u001b[0m \u001b[1;36m30\u001b[0m sky130_fd_sc_hd__nor2_2 A = \u001b[1;36m6.26\u001b[0m Df =\u001b[1;36m12246.7\u001b[0m-\u001b[1;36m5092.5\u001b[0m ps S = \u001b[1;36m898.2\u001b[0m ps Cin = \n",
+ "\u001b[1;36m4.4\u001b[0m ff Cout = \u001b[1;36m75.3\u001b[0m ff Cmax = \u001b[1;36m141.9\u001b[0m ff G = \u001b[1;36m1599\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 26 -- 11086 : 2 30 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =12246.7-5092.5 ps S = 898.2 ps Cin = \n",
+ "4.4 ff Cout = 75.3 ff Cmax = 141.9 ff G = 1599 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ABC: Path \u001b[1;36m27\u001b[0m -- \u001b[1;36m11087\u001b[0m : \u001b[1;36m4\u001b[0m \u001b[1;36m1\u001b[0m sky130_fd_sc_hd__o22a_2 A = \u001b[1;36m10.01\u001b[0m Df =\u001b[1;36m12648.6\u001b[0m-\u001b[1;36m5102.1\u001b[0m ps S = \u001b[1;36m180.7\u001b[0m ps Cin = \n",
+ "\u001b[1;36m2.4\u001b[0m ff Cout = \u001b[1;36m33.4\u001b[0m ff Cmax = \u001b[1;36m304.9\u001b[0m ff G = \u001b[1;36m1417\u001b[0m \n"
+ ],
+ "text/html": [
+ "ABC: Path 27 -- 11087 : 4 1 sky130_fd_sc_hd__o22a_2 A = 10.01 Df =12648.6-5102.1 ps S = 180.7 ps Cin = \n",
+ "2.4 ff Cout = 33.4 ff Cmax = 304.9 ff G = 1417 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
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+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Time spent: \u001b[1;36m72\u001b[0m% 2x abc \u001b[1m(\u001b[0m\u001b[1;36m51\u001b[0m sec\u001b[1m)\u001b[0m, \u001b[1;36m6\u001b[0m% 31x opt_clean \u001b[1m(\u001b[0m\u001b[1;36m4\u001b[0m sec\u001b[1m)\u001b[0m, \u001b[33m...\u001b[0m \n"
+ ],
+ "text/html": [
+ "Time spent: 72% 2x abc (51 sec), 6% 31x opt_clean (4 sec), ... \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[2;36m[11:15:38]\u001b[0m\u001b[2;36m \u001b[0mVERBOSE Parsing synthesis checks… \u001b]8;id=588160;file:///content/openlane_ipynb/openlane/steps/yosys.py\u001b\\\u001b[2myosys.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=130001;file:///content/openlane_ipynb/openlane/steps/yosys.py#55\u001b\\\u001b[2m55\u001b[0m\u001b]8;;\u001b\\\n"
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+ "
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+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
+ "text/plain": [
+ "{'nl': Path('/content/openlane_run/1-yosys-synthesis/core.nl.v'), 'pnl': None, 'pnl-sdf-friendly': None, 'pnl-npc': None, 'def': None, 'lef': None, 'openroad-lef': None, 'odb': None, 'sdc': None, 'sdf': None, 'spef': None, 'lib': None, 'spice': None, 'mag': None, 'gds': None, 'mag_gds': None, 'klayout_gds': None, 'json_h': None, 'vh': None, 'metrics': {'design__instance__count': 13071, 'design__instance__area': Decimal('157857.648000'), 'design__instance_unmapped__count': 0, 'synthesis__check_error__count': 0}}"
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+ "\n",
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\n",
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+ " \n",
+ " nl | \n",
+ " openlane_run/1-yosys-synthesis/core.nl.v | \n",
+ "
\n",
+ " \n",
+ "
\n",
+ "
"
+ ]
+ },
+ "metadata": {},
+ "execution_count": 28
+ }
+ ],
+ "source": [
+ "from openlane.state import State\n",
+ "path=\"/content\"\n",
+ "synthesis = Synthesis(\n",
+ " VERILOG_FILES=[\"/content/core.v\"],\n",
+ " state_in=State(),\n",
+ ")\n",
+ "synthesis.start()"
+ ]
+ },
+ {
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+ "execution_count": null,
+ "id": "80ca8345-e31c-4a74-9416-a7141ec430e9",
+ "metadata": {
+ "id": "80ca8345-e31c-4a74-9416-a7141ec430e9",
+ "colab": {
+ "base_uri": "https://localhost:8080/",
+ "height": 118
+ },
+ "outputId": "c040da31-a54c-4fc4-bf44-90705458a384"
+ },
+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ ""
+ ],
+ "text/markdown": "#### Time Elapsed: 88.53s\n#### Views updated:\n* Verilog Netlist\n"
+ },
+ "metadata": {}
+ }
+ ],
+ "source": [
+ "display(synthesis)"
+ ]
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+ "metadata": {
+ "id": "be98a880-4deb-42fb-8070-13965ec29756"
+ },
+ "source": [
+ "#### Floorplanning"
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+ },
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+ "height": 988
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+ "outputId": "606b766f-8222-4007-c849-b0201eb827ab"
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+ {
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+ "text/plain": [
+ "\u001b[92m──────────────────────────────────────────── \u001b[0mFloorplan Initialization\u001b[92m ─────────────────────────────────────────────\u001b[0m\n"
+ ],
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+ "
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+ ]
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+ "metadata": {},
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+ ],
+ "source": [
+ "Floorplan = Step.factory.get(\"OpenROAD.Floorplan\")\n",
+ "\n",
+ "floorplan = Floorplan(state_in=synthesis.state_out)\n",
+ "floorplan.start()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "46e18e61-528f-45dc-8d83-784671efe404",
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+ "id": "46e18e61-528f-45dc-8d83-784671efe404",
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+ "base_uri": "https://localhost:8080/",
+ "height": 1000
+ },
+ "outputId": "283c933f-de2e-48cb-9fce-0df6418f104c"
+ },
+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m──────────────────────────────────────────── \u001b[0mRender Image \u001b[1m(\u001b[0mw/ KLayout\u001b[1m)\u001b[0m\u001b[92m ────────────────────────────────────────────\u001b[0m\n"
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+ "text/html": [
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+ },
+ "metadata": {}
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+ {
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+ "data": {
+ "text/plain": [
+ ""
+ ],
+ "text/markdown": "#### Time Elapsed: 2.84s\n#### Views updated:\n* Verilog Netlist\n* Powered Verilog Netlist\n* Design Exchange Format\n* OpenDB Database\n* Design Constraints\n#### Preview:\n"
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+ "metadata": {}
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+ "id": "b66d2e9e-a64a-4b82-895c-70748d016b33"
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+ "source": [
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+ ]
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+ "height": 510
+ },
+ "outputId": "33d0ff76-6e2f-442e-f183-42fe760d711a"
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+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m─────────────────────────────────────────────── \u001b[0mTap/Decap Insertion\u001b[92m ───────────────────────────────────────────────\u001b[0m\n"
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+ "text/html": [
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+ },
+ "metadata": {}
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+ "data": {
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+ ""
+ ],
+ "text/markdown": "#### Time Elapsed: 1.82s\n#### Views updated:\n* Verilog Netlist\n* Powered Verilog Netlist\n* Design Exchange Format\n* OpenDB Database\n* Design Constraints\n#### Preview:\n"
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+ "metadata": {}
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+ "text/plain": [
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+ ],
+ "source": [
+ "IOPlacement = Step.factory.get(\"OpenROAD.IOPlacement\")\n",
+ "\n",
+ "ioplace = IOPlacement(state_in=tdi.state_out)\n",
+ "ioplace.start()"
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+ },
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+ "data": {
+ "text/plain": [
+ "\u001b[92m──────────────────────────────────────────── \u001b[0mRender Image \u001b[1m(\u001b[0mw/ KLayout\u001b[1m)\u001b[0m\u001b[92m ────────────────────────────────────────────\u001b[0m\n"
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+ },
+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ ""
+ ],
+ "text/markdown": "#### Time Elapsed: 1.63s\n#### Views updated:\n* Verilog Netlist\n* Powered Verilog Netlist\n* Design Exchange Format\n* OpenDB Database\n* Design Constraints\n#### Preview:\n"
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+ "metadata": {}
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+ ]
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m────────────────────────────────────── \u001b[0mPower Distribution Network Generation\u001b[92m ──────────────────────────────────────\u001b[0m\n"
+ ],
+ "text/html": [
+ "────────────────────────────────────── Power Distribution Network Generation ──────────────────────────────────────\n",
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+ "metadata": {},
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+ "source": [
+ "GeneratePDN = Step.factory.get(\"OpenROAD.GeneratePDN\")\n",
+ "\n",
+ "pdn = GeneratePDN(\n",
+ " state_in=ioplace.state_out,\n",
+ " FP_PDN_VWIDTH=1.6,\n",
+ " FP_PDN_HWIDTH=1.6,\n",
+ " FP_PDN_VPITCH=153.6,\n",
+ " FP_PDN_HPITCH=153.18,\n",
+ ")\n",
+ "pdn.start()"
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+ "id": "d626c1ff-3f23-4988-9611-15d4f0750ecf",
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+ "height": 1000
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+ "outputId": "e95b28de-1c6a-4e8e-8256-a590bc25faa2"
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+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m──────────────────────────────────────────── \u001b[0mRender Image \u001b[1m(\u001b[0mw/ KLayout\u001b[1m)\u001b[0m\u001b[92m ────────────────────────────────────────────\u001b[0m\n"
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ ""
+ ],
+ "text/markdown": "#### Time Elapsed: 2.44s\n#### Views updated:\n* Verilog Netlist\n* Powered Verilog Netlist\n* Design Exchange Format\n* OpenDB Database\n* Design Constraints\n#### Preview:\n"
+ },
+ "metadata": {}
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+ "source": [
+ "display(pdn)"
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+ "metadata": {
+ "id": "37f1f3be-b056-4bd4-bcab-8eae7c37983f"
+ },
+ "source": [
+ "#### Global Placement"
+ ]
+ },
+ {
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+ "id": "88785e2a-5a1e-489a-8885-eaf105b4d707",
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+ "outputId": "a5da09ee-711a-49f8-daf6-bb8202f83e01"
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+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m──────────────────────────────────────────────── \u001b[0mGlobal Placement\u001b[92m ─────────────────────────────────────────────────\u001b[0m\n"
+ ],
+ "text/html": [
+ "──────────────────────────────────────────────── Global Placement ─────────────────────────────────────────────────\n",
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+ "source": [
+ "#### Clock Tree Synthesis (CTS)\n"
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+ "id": "5f9c24e9-1a6b-4995-ad90-fe77d50b3eca",
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+ "\u001b[92m────────────────────────────────────────────── \u001b[0mClock Tree Synthesis\u001b[92m ───────────────────────────────────────────────\u001b[0m\n"
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+ "text/html": [
+ "────────────────────────────────────────────── Clock Tree Synthesis ───────────────────────────────────────────────\n",
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\n"
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+ "metadata": {}
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+ "Reading timing models for corner nom_tt_025C_1v80… \n"
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+ "Reading timing models for corner nom_tt_025C_1v80… \n",
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+ "\u001b[32m'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib'\u001b[0m… \n"
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+ "Reading timing models for corner nom_ss_100C_1v60… \n"
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\n"
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+ "[INFO] Configuring cts characterization… \n",
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+ ],
+ "text/markdown": "#### Time Elapsed: 23.08s\n#### Views updated:\n* Verilog Netlist\n* Powered Verilog Netlist\n* Design Exchange Format\n* OpenDB Database\n* Design Constraints\n#### Preview:\n"
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+ "text/html": [
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\n"
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\n"
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+ "text/html": [
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\n"
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+ "text/html": [
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\n"
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+ "text/plain": [
+ "\u001b[1;36m114303\u001b[0m \n"
+ ],
+ "text/html": [
+ "114303 \n",
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\n"
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+ ],
+ "text/html": [
+ "Completing 10% with 6373 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "Completing 20% with 6373 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ "metadata": {}
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+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "Completing 30% with 5292 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 40% with 5292 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:05:59\u001b[0m, memory = \u001b[1;36m1023.89\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 50% with 5292 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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\n"
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 60% with 4103 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ "data": {
+ "text/plain": [
+ "Completing \u001b[1;36m70\u001b[0m% with \u001b[1;36m4103\u001b[0m violations. \n"
+ ],
+ "text/html": [
+ "Completing 70% with 4103 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:12:04\u001b[0m, memory = \u001b[1;36m1005.84\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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\n"
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 80% with 2737 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:14:14\u001b[0m, memory = \u001b[1;36m1031.62\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ ],
+ "text/html": [
+ "Completing 90% with 2737 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
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+ "elapsed time = \u001b[1;92m00:16:39\u001b[0m, memory = \u001b[1;36m1033.43\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ ],
+ "text/html": [
+ "Completing 100% with 1294 violations. \n",
+ "
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+ },
+ "metadata": {}
+ },
+ {
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+ "text/html": [
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+ },
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+ {
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+ },
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+ {
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+ },
+ "metadata": {}
+ },
+ {
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+ },
+ "metadata": {}
+ },
+ {
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+ "text/html": [
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+ },
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+ {
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+ "text/html": [
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+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ "text/html": [
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+ ]
+ },
+ "metadata": {}
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+ {
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+ "text/html": [
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+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ ],
+ "text/html": [
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+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ ],
+ "text/html": [
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\n"
+ ]
+ },
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+ },
+ {
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+ "text/html": [
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+ ],
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+ ],
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+ "text/html": [
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\n"
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+ },
+ "metadata": {}
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+ {
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+ "text/html": [
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\n"
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+ },
+ "metadata": {}
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+ {
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+ "met1 \u001b[1;36m59780\u001b[0m \n"
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\n"
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+ },
+ "metadata": {}
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+ {
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+ "text/plain": [
+ "met2 \u001b[1;36m4745\u001b[0m \n"
+ ],
+ "text/html": [
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\n"
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+ },
+ "metadata": {}
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+ "met3 \u001b[1;36m972\u001b[0m \n"
+ ],
+ "text/html": [
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\n"
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+ },
+ "metadata": {}
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+ ],
+ "text/html": [
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+ "text/html": [
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+ ],
+ "text/html": [
+ "Completing 10% with 1296 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
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+ ],
+ "text/html": [
+ "Completing 20% with 1296 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 30% with 965 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "Completing 40% with 965 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ },
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 50% with 965 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "Completing 60% with 757 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "Completing 70% with 757 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 80% with 392 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 90% with 392 violations. \n",
+ "
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+ },
+ "metadata": {}
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+ {
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+ "text/html": [
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\n"
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+ },
+ "metadata": {}
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+ {
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+ "data": {
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+ "text/html": [
+ "[INFO DRT-0199] Number of violations = 109. \n",
+ "
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+ },
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+ "text/html": [
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+ },
+ "metadata": {}
+ },
+ {
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+ "text/html": [
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+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ ],
+ "text/html": [
+ "Total wire length on LAYER li1 = 0 um. \n",
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+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ "Total wire length on LAYER met1 = \u001b[1;36m232784\u001b[0m um. \n"
+ ],
+ "text/html": [
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+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ ],
+ "text/html": [
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ ],
+ "text/html": [
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+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ ],
+ "text/html": [
+ "Total wire length on LAYER met4 = 34257 um. \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ ],
+ "text/html": [
+ "Total wire length on LAYER met5 = 0 um. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ ],
+ "text/html": [
+ "Total number of vias = 116708. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ ],
+ "text/html": [
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+ "
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+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
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+ "
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+ {
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+ ],
+ "text/html": [
+ "------------------------- \n",
+ "
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+ ]
+ },
+ "metadata": {}
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+ {
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+ ],
+ "text/html": [
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+ "
\n"
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+ },
+ "metadata": {}
+ },
+ {
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+ "text/plain": [
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+ ],
+ "text/html": [
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\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "text/plain": [
+ "met1 \u001b[1;36m59830\u001b[0m \n"
+ ],
+ "text/html": [
+ "met1 59830 \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
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+ "text/plain": [
+ "met2 \u001b[1;36m4811\u001b[0m \n"
+ ],
+ "text/html": [
+ "met2 4811 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "met3 \u001b[1;36m971\u001b[0m \n"
+ ],
+ "text/html": [
+ "met3 971 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
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+ "text/plain": [
+ "met4 \u001b[1;36m0\u001b[0m \n"
+ ],
+ "text/html": [
+ "met4 0 \n",
+ "
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+ },
+ "metadata": {}
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+ {
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+ ],
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+ "
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+ "text/plain": [
+ "\u001b[1;36m116708\u001b[0m \n"
+ ],
+ "text/html": [
+ "116708 \n",
+ "
\n"
+ ]
+ },
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+ },
+ {
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+ "text/plain": [
+ " \n"
+ ],
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\n"
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+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "[INFO DRT-0195] Start 5th optimization iteration. \n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
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+ ],
+ "text/html": [
+ "Completing 10% with 109 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ },
+ "metadata": {}
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+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "Completing 20% with 109 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:00:01\u001b[0m, memory = \u001b[1;36m1016.41\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ },
+ "metadata": {}
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+ {
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+ "data": {
+ "text/plain": [
+ "Completing \u001b[1;36m30\u001b[0m% with \u001b[1;36m88\u001b[0m violations. \n"
+ ],
+ "text/html": [
+ "Completing 30% with 88 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:00:22\u001b[0m, memory = \u001b[1;36m962.93\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ "elapsed time = 00:00:22, memory = 962.93 (MB). \n",
+ "
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+ },
+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "Completing 40% with 88 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:00:23\u001b[0m, memory = \u001b[1;36m983.55\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ "elapsed time = 00:00:23, memory = 983.55 (MB). \n",
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\n"
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+ },
+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Completing \u001b[1;36m50\u001b[0m% with \u001b[1;36m88\u001b[0m violations. \n"
+ ],
+ "text/html": [
+ "Completing 50% with 88 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:00:26\u001b[0m, memory = \u001b[1;36m1025.18\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ "text/html": [
+ "elapsed time = 00:00:26, memory = 1025.18 (MB). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Completing \u001b[1;36m60\u001b[0m% with \u001b[1;36m78\u001b[0m violations. \n"
+ ],
+ "text/html": [
+ "Completing 60% with 78 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:00:34\u001b[0m, memory = \u001b[1;36m962.89\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ "text/html": [
+ "elapsed time = 00:00:34, memory = 962.89 (MB). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Completing \u001b[1;36m70\u001b[0m% with \u001b[1;36m78\u001b[0m violations. \n"
+ ],
+ "text/html": [
+ "Completing 70% with 78 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:00:46\u001b[0m, memory = \u001b[1;36m991.11\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "elapsed time = 00:00:46, memory = 991.11 (MB). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Completing \u001b[1;36m80\u001b[0m% with \u001b[1;36m37\u001b[0m violations. \n"
+ ],
+ "text/html": [
+ "Completing 80% with 37 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:00:56\u001b[0m, memory = \u001b[1;36m1013.76\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "elapsed time = 00:00:56, memory = 1013.76 (MB). \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Completing \u001b[1;36m90\u001b[0m% with \u001b[1;36m37\u001b[0m violations. \n"
+ ],
+ "text/html": [
+ "Completing 90% with 37 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:01:04\u001b[0m, memory = \u001b[1;36m1019.82\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
+ ],
+ "text/html": [
+ "elapsed time = 00:01:04, memory = 1019.82 (MB). \n",
+ "
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ ],
+ "text/html": [
+ "Completing 100% with 25 violations. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "elapsed time = \u001b[1;92m00:01:19\u001b[0m, memory = \u001b[1;36m964.91\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m. \n"
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+ "text/html": [
+ "elapsed time = 00:01:19, memory = 964.91 (MB). \n",
+ "
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+ ]
+ },
+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0199\u001b[0m\u001b[1m]\u001b[0m Number of violations = \u001b[1;36m25\u001b[0m. \n"
+ ],
+ "text/html": [
+ "[INFO DRT-0199] Number of violations = 25. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Viol/Layer met1 \n"
+ ],
+ "text/html": [
+ "Viol/Layer met1 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Metal Spacing \u001b[1;36m13\u001b[0m \n"
+ ],
+ "text/html": [
+ "Metal Spacing 13 \n",
+ "
\n"
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Short \u001b[1;36m12\u001b[0m \n"
+ ],
+ "text/html": [
+ "Short 12 \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1m[\u001b[0mINFO DRT-\u001b[1;36m0267\u001b[0m\u001b[1m]\u001b[0m cpu time = \u001b[1;92m00:01:58\u001b[0m, elapsed time = \u001b[1;92m00:01:21\u001b[0m, memory = \u001b[1;36m964.91\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m, peak = \u001b[1;36m1081.33\u001b[0m \u001b[1m(\u001b[0mMB\u001b[1m)\u001b[0m \n"
+ ],
+ "text/html": [
+ "[INFO DRT-0267] cpu time = 00:01:58, elapsed time = 00:01:21, memory = 964.91 (MB), peak = 1081.33 (MB) \n",
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Total wire length = \u001b[1;36m580799\u001b[0m um. \n"
+ ],
+ "text/html": [
+ "Total wire length = 580799 um. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Total wire length on LAYER li1 = \u001b[1;36m0\u001b[0m um. \n"
+ ],
+ "text/html": [
+ "Total wire length on LAYER li1 = 0 um. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Total wire length on LAYER met1 = \u001b[1;36m232693\u001b[0m um. \n"
+ ],
+ "text/html": [
+ "Total wire length on LAYER met1 = 232693 um. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Total wire length on LAYER met2 = \u001b[1;36m248282\u001b[0m um. \n"
+ ],
+ "text/html": [
+ "Total wire length on LAYER met2 = 248282 um. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Total wire length on LAYER met3 = \u001b[1;36m65562\u001b[0m um. \n"
+ ],
+ "text/html": [
+ "Total wire length on LAYER met3 = 65562 um. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Total wire length on LAYER met4 = \u001b[1;36m34260\u001b[0m um. \n"
+ ],
+ "text/html": [
+ "Total wire length on LAYER met4 = 34260 um. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Total wire length on LAYER met5 = \u001b[1;36m0\u001b[0m um. \n"
+ ],
+ "text/html": [
+ "Total wire length on LAYER met5 = 0 um. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Total number of vias = \u001b[1;36m116706\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Total number of vias = 116706. \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
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+ },
+ "metadata": {},
+ "execution_count": 47
+ }
+ ],
+ "source": [
+ "FillInsertion = Step.factory.get(\"OpenROAD.FillInsertion\")\n",
+ "\n",
+ "fill = FillInsertion(state_in=drt.state_out)\n",
+ "fill.start()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "a76d0e47-b9d1-4bfc-9e44-8aaa11d8955f",
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+ "height": 1000
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+ "data": {
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+ "text/html": [
+ "──────────────────────────────────────────── Render Image (w/ KLayout) ────────────────────────────────────────────\n",
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+ "metadata": {}
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+ "text/html": [
+ "[12:51:04] VERBOSE Running 'KLayout.Render'… (Log: /tmp/tmpwmrsdbxd/klayout-render.log) step.py:1085\n",
+ "
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+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ ""
+ ],
+ "text/markdown": "#### Time Elapsed: 3.03s\n#### Views updated:\n* Verilog Netlist\n* Powered Verilog Netlist\n* Design Exchange Format\n* OpenDB Database\n* Design Constraints\n#### Preview:\n"
+ },
+ "metadata": {}
+ }
+ ],
+ "source": [
+ "display(fill)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "0a4cb2db-d455-4c36-b3a4-7b89ce0514b8",
+ "metadata": {
+ "id": "0a4cb2db-d455-4c36-b3a4-7b89ce0514b8"
+ },
+ "source": [
+ "#### **Parasitics Extraction a.k.a. Resistance/Capacitance Extraction (RCX)**"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "source": [
+ "**Dear distinguished jury members, colleagues, and fellow developers,**\n",
+ "\n",
+ "We would like to bring to your attention that we have utilized OpenLANE2, the next generation of OpenLANE, which has been rewritten from scratch with a modular architecture. As of the time of our submission, the official version is still under active development, and we have proactively provided feedback on several issues and suggested improvements.\n",
+ "\n",
+ "At the time of our submission,** the timing analysis (STA) of the RCX stage was not yet stabilized**, *even for the official SPM examples*. We have already communicated this concern to the development team.\n",
+ "\n",
+ "Furthermore, we have made available the results of a complete, end-to-end flow with successful signoff, based on a local OpenLANE Docker implementation, on our GitHub repository**:https://github.com/lyaniix/ChatChisel-core** We welcome everyone to access and review these artifacts.\n",
+ "\n",
+ "We appreciate your understanding and consideration of the current state of the OpenLANE2 development, and we look forward to your valuable feedback."
+ ],
+ "metadata": {
+ "id": "x_Q-1O9oqwQ7"
+ },
+ "id": "x_Q-1O9oqwQ7"
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "0fa4e2d6-3678-46f6-950c-80033501fba2",
+ "metadata": {
+ "id": "0fa4e2d6-3678-46f6-950c-80033501fba2",
+ "colab": {
+ "base_uri": "https://localhost:8080/"
+ },
+ "outputId": "fe215dcd-266b-4db2-ec79-ddf13860ffdb"
+ },
+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m─────────────────────────────────── \u001b[0mParasitic Resistance/Capacitance Extraction\u001b[92m ───────────────────────────────────\u001b[0m\n"
+ ],
+ "text/html": [
+ "─────────────────────────────────── Parasitic Resistance/Capacitance Extraction ───────────────────────────────────\n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[2;36m[12:51:13]\u001b[0m\u001b[2;36m \u001b[0mVERBOSE Running \u001b[32m'OpenROAD.RCX'\u001b[0m… \u001b[1m(\u001b[0mLog: \u001b]8;id=981606;file:///content/openlane_run/12-openroad-rcx/openroad-rcx.log\u001b\\.\u001b]8;;\u001b\\\u001b]8;id=898767;file:///content/openlane_run/12-openroad-rcx/openroad-rcx.log\u001b\\\u001b[35m/openlane_run/12-openroad-rcx/\u001b[0m\u001b]8;;\u001b\\\u001b]8;id=961908;file:///content/openlane_run/12-openroad-rcx/openroad-rcx.log\u001b\\\u001b[95mopenroad-rcx.log\u001b[0m\u001b]8;;\u001b\\\u001b[1m)\u001b[0m \u001b]8;id=384226;file:///content/openlane_ipynb/openlane/steps/step.py\u001b\\\u001b[2mstep.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=809849;file:///content/openlane_ipynb/openlane/steps/step.py#1085\u001b\\\u001b[2m1085\u001b[0m\u001b]8;;\u001b\\\n"
+ ],
+ "text/html": [
+ "[12:51:13] VERBOSE Running 'OpenROAD.RCX'… (Log: ./openlane_run/12-openroad-rcx/openroad-rcx.log) step.py:1085\n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[2;36m[12:51:13]\u001b[0m\u001b[2;36m \u001b[0m\u001b[34mINFO \u001b[0m Running RCX for corners matching nom_* \u001b]8;id=277309;file:///content/openlane_ipynb/openlane/steps/openroad.py\u001b\\\u001b[2mopenroad.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=996305;file:///content/openlane_ipynb/openlane/steps/openroad.py#1653\u001b\\\u001b[2m1653\u001b[0m\u001b]8;;\u001b\\\n",
+ "\u001b[2;36m \u001b[0m \u001b[1m(\u001b[0m\u001b[35m/content/openlane_run/12-openroad-rcx/nom/\u001b[0m\u001b[95mrcx.log\u001b[0m\u001b[1m)\u001b[0m… \u001b[2m \u001b[0m\n"
+ ],
+ "text/html": [
+ "[12:51:13] INFO Running RCX for corners matching nom_* openroad.py:1653\n",
+ " (/content/openlane_run/12-openroad-rcx/nom/rcx.log)… \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[2;36m[12:51:13]\u001b[0m\u001b[2;36m \u001b[0m\u001b[34mINFO \u001b[0m Running RCX for corners matching min_* \u001b]8;id=847682;file:///content/openlane_ipynb/openlane/steps/openroad.py\u001b\\\u001b[2mopenroad.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=68924;file:///content/openlane_ipynb/openlane/steps/openroad.py#1653\u001b\\\u001b[2m1653\u001b[0m\u001b]8;;\u001b\\\n",
+ "\u001b[2;36m \u001b[0m \u001b[1m(\u001b[0m\u001b[35m/content/openlane_run/12-openroad-rcx/min/\u001b[0m\u001b[95mrcx.log\u001b[0m\u001b[1m)\u001b[0m… \u001b[2m \u001b[0m\n"
+ ],
+ "text/html": [
+ "[12:51:13] INFO Running RCX for corners matching min_* openroad.py:1653\n",
+ " (/content/openlane_run/12-openroad-rcx/min/rcx.log)… \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[2;36m[12:51:16]\u001b[0m\u001b[2;36m \u001b[0m\u001b[1;31mERROR \u001b[0m \u001b[31mFailed RCX for the corners matching min_*:\u001b[0m \u001b]8;id=89217;file:///content/openlane_ipynb/openlane/steps/openroad.py\u001b\\\u001b[2mopenroad.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=497998;file:///content/openlane_ipynb/openlane/steps/openroad.py#1664\u001b\\\u001b[2m1664\u001b[0m\u001b]8;;\u001b\\\n"
+ ],
+ "text/html": [
+ "[12:51:16] ERROR Failed RCX for the corners matching min_*: openroad.py:1664\n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "\u001b[2;36m[12:51:16]\u001b[0m\u001b[2;36m \u001b[0m\u001b[1;31mERROR \u001b[0m \u001b[31mFailed RCX for the corners matching nom_*:\u001b[0m \u001b]8;id=752702;file:///content/openlane_ipynb/openlane/steps/openroad.py\u001b\\\u001b[2mopenroad.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=337222;file:///content/openlane_ipynb/openlane/steps/openroad.py#1664\u001b\\\u001b[2m1664\u001b[0m\u001b]8;;\u001b\\\n"
+ ],
+ "text/html": [
+ "[12:51:16] ERROR Failed RCX for the corners matching nom_*: openroad.py:1664\n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[2;36m[12:51:16]\u001b[0m\u001b[2;36m \u001b[0m\u001b[34mINFO \u001b[0m Running RCX for corners matching max_* \u001b]8;id=317251;file:///content/openlane_ipynb/openlane/steps/openroad.py\u001b\\\u001b[2mopenroad.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=154380;file:///content/openlane_ipynb/openlane/steps/openroad.py#1653\u001b\\\u001b[2m1653\u001b[0m\u001b]8;;\u001b\\\n",
+ "\u001b[2;36m \u001b[0m \u001b[1m(\u001b[0m\u001b[35m/content/openlane_run/12-openroad-rcx/max/\u001b[0m\u001b[95mrcx.log\u001b[0m\u001b[1m)\u001b[0m… \u001b[2m \u001b[0m\n"
+ ],
+ "text/html": [
+ "[12:51:16] INFO Running RCX for corners matching max_* openroad.py:1653\n",
+ " (/content/openlane_run/12-openroad-rcx/max/rcx.log)… \n",
+ "
\n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "error",
+ "ename": "StepSignalled",
+ "evalue": "Parasitics (RC) Extraction: Interrupted (SIGSEGV)",
+ "traceback": [
+ "\u001b[0;31m---------------------------------------------------------------------------\u001b[0m",
+ "\u001b[0;31mStepSignalled\u001b[0m Traceback (most recent call last)",
+ "\u001b[0;32m\u001b[0m in \u001b[0;36m\u001b[0;34m()\u001b[0m\n\u001b[1;32m 2\u001b[0m \u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m 3\u001b[0m \u001b[0mrcx\u001b[0m \u001b[0;34m=\u001b[0m \u001b[0mRCX\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0mstate_in\u001b[0m\u001b[0;34m=\u001b[0m\u001b[0mfill\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mstate_out\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[0;32m----> 4\u001b[0;31m \u001b[0mrcx\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mstart\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[0m",
+ "\u001b[0;32m/content/openlane_ipynb/openlane/steps/step.py\u001b[0m in \u001b[0;36mstart\u001b[0;34m(self, toolbox, step_dir, _no_rule, **kwargs)\u001b[0m\n\u001b[1;32m 1113\u001b[0m \u001b[0;32mexcept\u001b[0m \u001b[0msubprocess\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mCalledProcessError\u001b[0m \u001b[0;32mas\u001b[0m \u001b[0me\u001b[0m\u001b[0;34m:\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m 1114\u001b[0m \u001b[0;32mif\u001b[0m \u001b[0me\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mreturncode\u001b[0m \u001b[0;32mis\u001b[0m \u001b[0;32mnot\u001b[0m \u001b[0;32mNone\u001b[0m \u001b[0;32mand\u001b[0m \u001b[0me\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mreturncode\u001b[0m \u001b[0;34m<\u001b[0m \u001b[0;36m0\u001b[0m\u001b[0;34m:\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[0;32m-> 1115\u001b[0;31m raise StepSignalled(\n\u001b[0m\u001b[1;32m 1116\u001b[0m \u001b[0;34mf\"{self.name}: Interrupted ({Signals(-e.returncode).name})\"\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m 1117\u001b[0m ) from None\n",
+ "\u001b[0;31mStepSignalled\u001b[0m: Parasitics (RC) Extraction: Interrupted (SIGSEGV)"
+ ]
+ }
+ ],
+ "source": [
+ "RCX = Step.factory.get(\"OpenROAD.RCX\")\n",
+ "\n",
+ "rcx = RCX(state_in=fill.state_out)\n",
+ "rcx.start()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "966fe7c7-9e89-4a72-90c9-87b818916d9a",
+ "metadata": {
+ "id": "966fe7c7-9e89-4a72-90c9-87b818916d9a"
+ },
+ "source": [
+ "#### ***Static Timing Analysis (Post-PnR)***"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "source": [
+ "**Dear distinguished jury members, colleagues, and fellow developers,**\n",
+ "\n",
+ "We would like to bring to your attention that we have utilized OpenLANE2, the next generation of OpenLANE, which has been rewritten from scratch with a modular architecture. As of the time of our submission, the official version is still under active development, and we have proactively provided feedback on several issues and suggested improvements.\n",
+ "\n",
+ "At the time of our submission,** the timing analysis (STA) of the post-place-and-route (Post-PnR) stage was not yet stabilized**, *even for the official SPM examples*. We have already communicated this concern to the development team.\n",
+ "\n",
+ "Furthermore, we have made available the results of a complete, end-to-end flow with successful signoff, based on a local OpenLANE Docker implementation, on our GitHub repository. We welcome everyone to access and review these artifacts.\n",
+ "\n",
+ "We appreciate your understanding and consideration of the current state of the OpenLANE2 development, and we look forward to your valuable feedback."
+ ],
+ "metadata": {
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+ "id": "7840cb38-88e7-4a03-b42c-fa8ae893a0bc"
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+ "outputs": [],
+ "source": [
+ "STAPostPNR = Step.factory.get(\"OpenROAD.STAPostPNR\")\n",
+ "\n",
+ "sta_post_pnr = STAPostPNR(state_in=rcx.state_out)\n",
+ "sta_post_pnr.start()"
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+ " openlane_run/11-openroad-fillinsertion/core.nl.v | \n",
+ " \n",
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+ " \n",
+ " pnl | \n",
+ " openlane_run/11-openroad-fillinsertion/core.pnl.v | \n",
+ " \n",
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+ " \n",
+ " def | \n",
+ " openlane_run/11-openroad-fillinsertion/core.def | \n",
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+ " openlane_run/11-openroad-fillinsertion/core.odb | \n",
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+ " \n",
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+ " \n",
+ " gds | \n",
+ " openlane_run/13-klayout-streamout/core.gds | \n",
+ " \n",
+ " \n",
+ " \n",
+ " klayout_gds | \n",
+ " openlane_run/13-klayout-streamout/core.klayout.gds | \n",
+ " \n",
+ " \n",
+ " \n",
+ " "
+ ]
+ },
+ "metadata": {},
+ "execution_count": 50
+ }
+ ],
+ "source": [
+ "StreamOut = Step.factory.get(\"KLayout.StreamOut\")\n",
+ "\n",
+ "gds = StreamOut(state_in=fill.state_out)\n",
+ "gds.start()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "bfe32077-4588-4d79-9c2a-ba032521ff59",
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+ "id": "bfe32077-4588-4d79-9c2a-ba032521ff59",
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+ "height": 1000
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+ "outputId": "ee6db5f9-3d20-41c2-b1e2-8cc203f1d4cb"
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+ "text/plain": [
+ "\u001b[92m──────────────────────────────────────────── \u001b[0mRender Image \u001b[1m(\u001b[0mw/ KLayout\u001b[1m)\u001b[0m\u001b[92m ────────────────────────────────────────────\u001b[0m\n"
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+ },
+ "metadata": {}
+ },
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+ "data": {
+ "text/plain": [
+ ""
+ ],
+ "text/markdown": "#### Time Elapsed: 3.75s\n#### Views updated:\n* GDSII Stream\n* GDSII Stream (KLayout)\n#### Preview:\n"
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+ "metadata": {
+ "id": "c9f9e561-9e2c-4b4d-bfed-7e35051ed612"
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+ "source": [
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+ "text/plain": [
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+ "text/html": [
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+ ],
+ "text/html": [
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+ "Scaled tech values by \u001b[1;36m2\u001b[0m \u001b[35m/\u001b[0m \u001b[1;36m1\u001b[0m to match internal grid scaling \n"
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+ "{'nl': Path('/content/openlane_run/11-openroad-fillinsertion/core.nl.v'), 'pnl': Path('/content/openlane_run/11-openroad-fillinsertion/core.pnl.v'), 'pnl-sdf-friendly': None, 'pnl-npc': None, 'def': Path('/content/openlane_run/11-openroad-fillinsertion/core.def'), 'lef': None, 'openroad-lef': None, 'odb': Path('/content/openlane_run/11-openroad-fillinsertion/core.odb'), 'sdc': Path('/content/openlane_run/11-openroad-fillinsertion/core.sdc'), 'sdf': None, 'spef': None, 'lib': None, 'spice': None, 'mag': None, 'gds': Path('/content/openlane_run/13-klayout-streamout/core.gds'), 'mag_gds': None, 'klayout_gds': Path('/content/openlane_run/13-klayout-streamout/core.klayout.gds'), 'json_h': None, 'vh': None, 'metrics': {'design__instance__count': 17885, 'design__instance__area': 168532, 'design__instance_unmapped__count': 0, 'synthesis__check_error__count': 0, 'design__die__bbox': '0.0 0.0 572.925 583.645', 'design__core__bbox': '5.52 10.88 567.18 571.2', 'design__io': 170, 'design__die__area': 334385, 'design__core__area': 314709, 'design__instance__count__stdcell': 17885, 'design__instance__area__stdcell': 168532, 'design__instance__count__macros': 0, 'design__instance__area__macros': 0, 'design__instance__utilization': Decimal('0.535515'), 'design__instance__utilization__stdcell': Decimal('0.535515'), 'floorplan__design__io': 168, 'design__io__hpwl': 72116016, 'design__power_grid_violation__count__net:VGND': 0, 'design__power_grid_violation__count__net:VPWR': 0, 'design__power_grid_violation__count': 0, 'design__instance__displacement__total': Decimal('3228.12'), 'design__instance__displacement__mean': Decimal('0.176'), 'design__instance__displacement__max': Decimal('12.42'), 'route__wirelength__estimated': 421851, 'design__violations': 0, 'antenna__violating__nets': 83, 'antenna__violating__pins': 100, 'route__net': 13480, 'route__net__special': 2, 'route__drc_errors__iter:1': 19636, 'route__wirelength__iter:1': 589106, 'route__drc_errors__iter:2': 6581, 'route__wirelength__iter:2': 583896, 'route__drc_errors__iter:3': 6373, 'route__wirelength__iter:3': 582213, 'route__drc_errors__iter:4': 1296, 'route__wirelength__iter:4': 580796, 'route__drc_errors__iter:5': 109, 'route__wirelength__iter:5': 580731, 'route__drc_errors__iter:6': 25, 'route__wirelength__iter:6': 580799, 'route__drc_errors__iter:7': 1, 'route__wirelength__iter:7': 580768, 'route__drc_errors__iter:8': 0, 'route__wirelength__iter:8': 580766, 'route__drc_errors': 0, 'route__wirelength': 580766, 'route__vias': 116716, 'route__vias__singlecut': 116716, 'route__vias__multicut': 0, 'magic__drc_error__count': 0}}"
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+ "text/html": [
+ "\n",
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+ " \n",
+ " \n",
+ " Format | \n",
+ " Path | \n",
+ " \n",
+ " \n",
+ " \n",
+ " nl | \n",
+ " openlane_run/11-openroad-fillinsertion/core.nl.v | \n",
+ " \n",
+ " \n",
+ " \n",
+ " pnl | \n",
+ " openlane_run/11-openroad-fillinsertion/core.pnl.v | \n",
+ " \n",
+ " \n",
+ " \n",
+ " def | \n",
+ " openlane_run/11-openroad-fillinsertion/core.def | \n",
+ " \n",
+ " \n",
+ " \n",
+ " odb | \n",
+ " openlane_run/11-openroad-fillinsertion/core.odb | \n",
+ " \n",
+ " \n",
+ " \n",
+ " sdc | \n",
+ " openlane_run/11-openroad-fillinsertion/core.sdc | \n",
+ " \n",
+ " \n",
+ " \n",
+ " gds | \n",
+ " openlane_run/13-klayout-streamout/core.gds | \n",
+ " \n",
+ " \n",
+ " \n",
+ " klayout_gds | \n",
+ " openlane_run/13-klayout-streamout/core.klayout.gds | \n",
+ " \n",
+ " \n",
+ " \n",
+ " "
+ ]
+ },
+ "metadata": {},
+ "execution_count": 52
+ }
+ ],
+ "source": [
+ "DRC = Step.factory.get(\"Magic.DRC\")\n",
+ "\n",
+ "drc = DRC(state_in=gds.state_out)\n",
+ "drc.start()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "e6b0c60b-0eb0-498d-b1f4-264bc0c79a48",
+ "metadata": {
+ "id": "e6b0c60b-0eb0-498d-b1f4-264bc0c79a48"
+ },
+ "source": [
+ "#### SPICE Extraction for Layout vs. Schematic Check"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "1a3ec2f4-585a-4641-9f4a-33521a7fe237",
+ "metadata": {
+ "id": "1a3ec2f4-585a-4641-9f4a-33521a7fe237",
+ "colab": {
+ "base_uri": "https://localhost:8080/",
+ "height": 1000
+ },
+ "outputId": "2f98ee3e-9de2-4618-935e-78b4de6a58d7"
+ },
+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m───────────────────────────────────────────── \u001b[0mSPICE Model Extraction\u001b[92m ──────────────────────────────────────────────\u001b[0m\n"
+ ],
+ "text/html": [
+ "───────────────────────────────────────────── SPICE Model Extraction ──────────────────────────────────────────────\n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[2;36m[12:56:07]\u001b[0m\u001b[2;36m \u001b[0mVERBOSE Running \u001b[32m'Magic.SpiceExtraction'\u001b[0m… \u001b[1m(\u001b[0mLog: \u001b]8;id=181280;file:///content/openlane_ipynb/openlane/steps/step.py\u001b\\\u001b[2mstep.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=374638;file:///content/openlane_ipynb/openlane/steps/step.py#1085\u001b\\\u001b[2m1085\u001b[0m\u001b]8;;\u001b\\\n",
+ "\u001b[2;36m \u001b[0m \u001b]8;id=465733;file:///content/openlane_run/15-magic-spiceextraction/magic-spiceextraction.log\u001b\\.\u001b]8;;\u001b\\\u001b]8;id=187213;file:///content/openlane_run/15-magic-spiceextraction/magic-spiceextraction.log\u001b\\\u001b[35m/openlane_run/15-magic-spiceextraction/\u001b[0m\u001b]8;;\u001b\\\u001b]8;id=564231;file:///content/openlane_run/15-magic-spiceextraction/magic-spiceextraction.log\u001b\\\u001b[95mmagic-spiceextraction.log\u001b[0m\u001b]8;;\u001b\\\u001b[1m)\u001b[0m \u001b[2m \u001b[0m\n"
+ ],
+ "text/html": [
+ "[12:56:07] VERBOSE Running 'Magic.SpiceExtraction'… (Log: step.py:1085\n",
+ " ./openlane_run/15-magic-spiceextraction/magic-spiceextraction.log) \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ " \n"
+ ],
+ "text/html": [
+ " \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Magic \u001b[1;36m8.3\u001b[0m revision \u001b[1;36m466\u001b[0m - Compiled on Thu Mar \u001b[1;36m21\u001b[0m \u001b[1;92m17:31:46\u001b[0m UTC \u001b[1;36m2024\u001b[0m. \n"
+ ],
+ "text/html": [
+ "Magic 8.3 revision 466 - Compiled on Thu Mar 21 17:31:46 UTC 2024. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Starting magic under Tcl interpreter \n"
+ ],
+ "text/html": [
+ "Starting magic under Tcl interpreter \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Using the terminal as the console. \n"
+ ],
+ "text/html": [
+ "Using the terminal as the console. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Using NULL graphics device. \n"
+ ],
+ "text/html": [
+ "Using NULL graphics device. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Processing system .magicrc file \n"
+ ],
+ "text/html": [
+ "Processing system .magicrc file \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Sourcing design .magicrc for technology sky130A \u001b[33m...\u001b[0m \n"
+ ],
+ "text/html": [
+ "Sourcing design .magicrc for technology sky130A ... \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[1;36m2\u001b[0m Magic internal units = \u001b[1;36m1\u001b[0m Lambda \n"
+ ],
+ "text/html": [
+ "2 Magic internal units = 1 Lambda \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Input style \u001b[1;35msky130\u001b[0m\u001b[1m(\u001b[0m\u001b[1m)\u001b[0m: \u001b[33mscaleFactor\u001b[0m=\u001b[1;36m2\u001b[0m, \u001b[33mmultiplier\u001b[0m=\u001b[1;36m2\u001b[0m \n"
+ ],
+ "text/html": [
+ "Input style sky130(): scaleFactor=2, multiplier=2 \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "The following types are not handled by extraction and will be treated as non-electrical types: \n"
+ ],
+ "text/html": [
+ "The following types are not handled by extraction and will be treated as non-electrical types: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "ubm \n"
+ ],
+ "text/html": [
+ "ubm \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Scaled tech values by \u001b[1;36m2\u001b[0m \u001b[35m/\u001b[0m \u001b[1;36m1\u001b[0m to match internal grid scaling \n"
+ ],
+ "text/html": [
+ "Scaled tech values by 2 / 1 to match internal grid scaling \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Loading sky130A Device Generator Menu \u001b[33m...\u001b[0m \n"
+ ],
+ "text/html": [
+ "Loading sky130A Device Generator Menu ... \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Loading \u001b[32m\"/content/openlane_ipynb/openlane/scripts/magic/wrapper.tcl\"\u001b[0m from command line. \n"
+ ],
+ "text/html": [
+ "Loading \"/content/openlane_ipynb/openlane/scripts/magic/wrapper.tcl\" from command line. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "> lef read \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/\u001b[0m\u001b[95msky130_fd_sc_hd__nom.tlef\u001b[0m \n"
+ ],
+ "text/html": [
+ "> lef read /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Reading LEF data from file \u001b[35m/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/\u001b[0m\u001b[95msky130_fd_sc_hd__nom.tlef.\u001b[0m \n"
+ ],
+ "text/html": [
+ "Reading LEF data from file /root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "This action cannot be undone. \n"
+ ],
+ "text/html": [
+ "This action cannot be undone. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
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+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m78\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 78 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m79\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNADIFFSIDEAREARATIO\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 79 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m112\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MINENCLOSEDAREA\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 112 (Message): Unknown keyword \"MINENCLOSEDAREA\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m114\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 114 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m115\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNADIFFSIDEAREARATIO\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 115 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m121\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MAXIMUMDENSITY\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 121 (Message): Unknown keyword \"MAXIMUMDENSITY\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
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+ ],
+ "text/html": [
+ "LEF read, Line 122 (Message): Unknown keyword \"DENSITYCHECKWINDOW\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m123\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKSTEP\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 123 (Message): Unknown keyword \"DENSITYCHECKSTEP\" in LEF file; ignoring. \n",
+ " \n"
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+ },
+ "metadata": {}
+ },
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m156\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MINENCLOSEDAREA\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 156 (Message): Unknown keyword \"MINENCLOSEDAREA\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m164\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n"
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+ "text/html": [
+ "LEF read, Line 164 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring. \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
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+ ],
+ "text/html": [
+ "LEF read, Line 165 (Message): Unknown keyword \"ANTENNADIFFSIDEAREARATIO\" in LEF file; ignoring. \n",
+ " \n"
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m167\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"MAXIMUMDENSITY\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 167 (Message): Unknown keyword \"MAXIMUMDENSITY\" in LEF file; ignoring. \n",
+ " \n"
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m168\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKWINDOW\"\u001b[0m in LEF file; ignoring. \n"
+ ],
+ "text/html": [
+ "LEF read, Line 168 (Message): Unknown keyword \"DENSITYCHECKWINDOW\" in LEF file; ignoring. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m169\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"DENSITYCHECKSTEP\"\u001b[0m in LEF file; ignoring. \n"
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+ "text/html": [
+ "LEF read, Line 169 (Message): Unknown keyword \"DENSITYCHECKSTEP\" in LEF file; ignoring. \n",
+ " \n"
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+ },
+ "metadata": {}
+ },
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "LEF read, Line \u001b[1;36m206\u001b[0m \u001b[1m(\u001b[0mMessage\u001b[1m)\u001b[0m: Unknown keyword \u001b[32m\"ANTENNAMODEL\"\u001b[0m in LEF file; ignoring. \n"
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+ "text/html": [
+ "LEF read, Line 206 (Message): Unknown keyword \"ANTENNAMODEL\" in LEF file; ignoring. \n",
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
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+ {
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+ "text/html": [
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+ " \n"
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+ },
+ "metadata": {}
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+ {
+ "output_type": "display_data",
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+ "text/html": [
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+ "text/html": [
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+ " \n"
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext: \n",
+ " \n"
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+ },
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+ "output_type": "display_data",
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__dfxtp_2 into sky130_fd_sc_hd__dfxtp_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__dfxtp_2 into sky130_fd_sc_hd__dfxtp_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext: \n",
+ " \n"
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+ "output_type": "display_data",
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext: \n",
+ " \n"
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext: \n"
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+ "Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext: \n",
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+ "metadata": {}
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__mux2_1 into sky130_fd_sc_hd__mux2_1.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__mux2_1 into sky130_fd_sc_hd__mux2_1.ext: \n",
+ " \n"
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+ "Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext: \n",
+ " \n"
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+ "Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext: \n"
+ ],
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+ "Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "Extracting sky130_fd_sc_hd__mux4_2 into sky130_fd_sc_hd__mux4_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__mux4_2 into sky130_fd_sc_hd__mux4_2.ext: \n",
+ " \n"
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+ "Extracting sky130_fd_sc_hd__clkbuf_8 into sky130_fd_sc_hd__clkbuf_8.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__clkbuf_8 into sky130_fd_sc_hd__clkbuf_8.ext: \n",
+ " \n"
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+ "Extracting sky130_fd_sc_hd__or2_2 into sky130_fd_sc_hd__or2_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__or2_2 into sky130_fd_sc_hd__or2_2.ext: \n",
+ " \n"
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o211a_2 into sky130_fd_sc_hd__o211a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o211a_2 into sky130_fd_sc_hd__o211a_2.ext: \n",
+ " \n"
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a21oi_2 into sky130_fd_sc_hd__a21oi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a21oi_2 into sky130_fd_sc_hd__a21oi_2.ext: \n",
+ " \n"
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nor2_2 into sky130_fd_sc_hd__nor2_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nor2_2 into sky130_fd_sc_hd__nor2_2.ext: \n",
+ " \n"
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+ "Extracting sky130_fd_sc_hd__inv_2 into sky130_fd_sc_hd__inv_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__inv_2 into sky130_fd_sc_hd__inv_2.ext: \n",
+ " \n"
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+ "Extracting sky130_fd_sc_hd__o21ai_2 into sky130_fd_sc_hd__o21ai_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o21ai_2 into sky130_fd_sc_hd__o21ai_2.ext: \n",
+ " \n"
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o2bb2a_2 into sky130_fd_sc_hd__o2bb2a_2.ext: \n"
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+ "Extracting sky130_fd_sc_hd__o2bb2a_2 into sky130_fd_sc_hd__o2bb2a_2.ext: \n",
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+ "metadata": {}
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__xnor2_2 into sky130_fd_sc_hd__xnor2_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__xnor2_2 into sky130_fd_sc_hd__xnor2_2.ext: \n",
+ " \n"
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a22o_2 into sky130_fd_sc_hd__a22o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a22o_2 into sky130_fd_sc_hd__a22o_2.ext: \n",
+ " \n"
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+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o21a_2 into sky130_fd_sc_hd__o21a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o21a_2 into sky130_fd_sc_hd__o21a_2.ext: \n",
+ " \n"
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+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__and4_2 into sky130_fd_sc_hd__and4_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__and4_2 into sky130_fd_sc_hd__and4_2.ext: \n",
+ " \n"
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+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nand2_2 into sky130_fd_sc_hd__nand2_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nand2_2 into sky130_fd_sc_hd__nand2_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a221o_2 into sky130_fd_sc_hd__a221o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a221o_2 into sky130_fd_sc_hd__a221o_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a311o_2 into sky130_fd_sc_hd__a311o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a311o_2 into sky130_fd_sc_hd__a311o_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a21o_2 into sky130_fd_sc_hd__a21o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a21o_2 into sky130_fd_sc_hd__a21o_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a211o_2 into sky130_fd_sc_hd__a211o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a211o_2 into sky130_fd_sc_hd__a211o_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a2bb2o_2 into sky130_fd_sc_hd__a2bb2o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a2bb2o_2 into sky130_fd_sc_hd__a2bb2o_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a22oi_2 into sky130_fd_sc_hd__a22oi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a22oi_2 into sky130_fd_sc_hd__a22oi_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o221a_2 into sky130_fd_sc_hd__o221a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o221a_2 into sky130_fd_sc_hd__o221a_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a221oi_2 into sky130_fd_sc_hd__a221oi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a221oi_2 into sky130_fd_sc_hd__a221oi_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o2111a_2 into sky130_fd_sc_hd__o2111a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o2111a_2 into sky130_fd_sc_hd__o2111a_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o22a_2 into sky130_fd_sc_hd__o22a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o22a_2 into sky130_fd_sc_hd__o22a_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a31o_2 into sky130_fd_sc_hd__a31o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a31o_2 into sky130_fd_sc_hd__a31o_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o311a_2 into sky130_fd_sc_hd__o311a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o311a_2 into sky130_fd_sc_hd__o311a_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__or3_2 into sky130_fd_sc_hd__or3_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__or3_2 into sky130_fd_sc_hd__or3_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__and2_2 into sky130_fd_sc_hd__and2_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__and2_2 into sky130_fd_sc_hd__and2_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__or3b_2 into sky130_fd_sc_hd__or3b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__or3b_2 into sky130_fd_sc_hd__or3b_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__and3_2 into sky130_fd_sc_hd__and3_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__and3_2 into sky130_fd_sc_hd__and3_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a211oi_2 into sky130_fd_sc_hd__a211oi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a211oi_2 into sky130_fd_sc_hd__a211oi_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__xor2_2 into sky130_fd_sc_hd__xor2_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__xor2_2 into sky130_fd_sc_hd__xor2_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nor3_2 into sky130_fd_sc_hd__nor3_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nor3_2 into sky130_fd_sc_hd__nor3_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nor3b_2 into sky130_fd_sc_hd__nor3b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nor3b_2 into sky130_fd_sc_hd__nor3b_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nand3_2 into sky130_fd_sc_hd__nand3_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nand3_2 into sky130_fd_sc_hd__nand3_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o31a_2 into sky130_fd_sc_hd__o31a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o31a_2 into sky130_fd_sc_hd__o31a_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o21ba_2 into sky130_fd_sc_hd__o21ba_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o21ba_2 into sky130_fd_sc_hd__o21ba_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a21bo_2 into sky130_fd_sc_hd__a21bo_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a21bo_2 into sky130_fd_sc_hd__a21bo_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__or4_2 into sky130_fd_sc_hd__or4_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__or4_2 into sky130_fd_sc_hd__or4_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o221ai_2 into sky130_fd_sc_hd__o221ai_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o221ai_2 into sky130_fd_sc_hd__o221ai_2.ext: \n",
+ " \n"
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+ "metadata": {}
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a21boi_2 into sky130_fd_sc_hd__a21boi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a21boi_2 into sky130_fd_sc_hd__a21boi_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__and2b_2 into sky130_fd_sc_hd__and2b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__and2b_2 into sky130_fd_sc_hd__and2b_2.ext: \n",
+ " \n"
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+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nand2b_2 into sky130_fd_sc_hd__nand2b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nand2b_2 into sky130_fd_sc_hd__nand2b_2.ext: \n",
+ " \n"
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+ },
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+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a32o_2 into sky130_fd_sc_hd__a32o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a32o_2 into sky130_fd_sc_hd__a32o_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__and3b_2 into sky130_fd_sc_hd__and3b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__and3b_2 into sky130_fd_sc_hd__and3b_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nand4_2 into sky130_fd_sc_hd__nand4_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nand4_2 into sky130_fd_sc_hd__nand4_2.ext: \n",
+ " \n"
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+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
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+ "Extracting sky130_fd_sc_hd__a41o_2 into sky130_fd_sc_hd__a41o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a41o_2 into sky130_fd_sc_hd__a41o_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__and4bb_2 into sky130_fd_sc_hd__and4bb_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__and4bb_2 into sky130_fd_sc_hd__and4bb_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o211ai_2 into sky130_fd_sc_hd__o211ai_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o211ai_2 into sky130_fd_sc_hd__o211ai_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a31oi_2 into sky130_fd_sc_hd__a31oi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a31oi_2 into sky130_fd_sc_hd__a31oi_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__and4b_2 into sky130_fd_sc_hd__and4b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__and4b_2 into sky130_fd_sc_hd__and4b_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__or4b_2 into sky130_fd_sc_hd__or4b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__or4b_2 into sky130_fd_sc_hd__or4b_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nor4_2 into sky130_fd_sc_hd__nor4_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nor4_2 into sky130_fd_sc_hd__nor4_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nand4b_2 into sky130_fd_sc_hd__nand4b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nand4b_2 into sky130_fd_sc_hd__nand4b_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__or4bb_2 into sky130_fd_sc_hd__or4bb_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__or4bb_2 into sky130_fd_sc_hd__or4bb_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a2111o_2 into sky130_fd_sc_hd__a2111o_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a2111o_2 into sky130_fd_sc_hd__a2111o_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o32a_2 into sky130_fd_sc_hd__o32a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o32a_2 into sky130_fd_sc_hd__o32a_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nand3b_2 into sky130_fd_sc_hd__nand3b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nand3b_2 into sky130_fd_sc_hd__nand3b_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o22ai_2 into sky130_fd_sc_hd__o22ai_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o22ai_2 into sky130_fd_sc_hd__o22ai_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o31ai_2 into sky130_fd_sc_hd__o31ai_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o31ai_2 into sky130_fd_sc_hd__o31ai_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__nor4b_2 into sky130_fd_sc_hd__nor4b_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__nor4b_2 into sky130_fd_sc_hd__nor4b_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a41oi_2 into sky130_fd_sc_hd__a41oi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a41oi_2 into sky130_fd_sc_hd__a41oi_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a32oi_2 into sky130_fd_sc_hd__a32oi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a32oi_2 into sky130_fd_sc_hd__a32oi_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o21bai_2 into sky130_fd_sc_hd__o21bai_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o21bai_2 into sky130_fd_sc_hd__o21bai_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__a311oi_2 into sky130_fd_sc_hd__a311oi_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__a311oi_2 into sky130_fd_sc_hd__a311oi_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting sky130_fd_sc_hd__o41a_2 into sky130_fd_sc_hd__o41a_2.ext: \n"
+ ],
+ "text/html": [
+ "Extracting sky130_fd_sc_hd__o41a_2 into sky130_fd_sc_hd__o41a_2.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Extracting core into core.ext: \n"
+ ],
+ "text/html": [
+ "Extracting core into core.ext: \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "exttospice finished. \n"
+ ],
+ "text/html": [
+ "exttospice finished. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Using technology \u001b[32m\"sky130A\"\u001b[0m, version \u001b[1;36m1.0\u001b[0m.\u001b[1;36m465\u001b[0m-\u001b[1;36m2\u001b[0m-gbdc9412 \n"
+ ],
+ "text/html": [
+ "Using technology \"sky130A\", version 1.0.465-2-gbdc9412 \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "execute_result",
+ "data": {
+ "text/plain": [
+ "{'nl': Path('/content/openlane_run/11-openroad-fillinsertion/core.nl.v'), 'pnl': Path('/content/openlane_run/11-openroad-fillinsertion/core.pnl.v'), 'pnl-sdf-friendly': None, 'pnl-npc': None, 'def': Path('/content/openlane_run/11-openroad-fillinsertion/core.def'), 'lef': None, 'openroad-lef': None, 'odb': Path('/content/openlane_run/11-openroad-fillinsertion/core.odb'), 'sdc': Path('/content/openlane_run/11-openroad-fillinsertion/core.sdc'), 'sdf': None, 'spef': None, 'lib': None, 'spice': Path('/content/openlane_run/15-magic-spiceextraction/core.spice'), 'mag': None, 'gds': Path('/content/openlane_run/13-klayout-streamout/core.gds'), 'mag_gds': None, 'klayout_gds': Path('/content/openlane_run/13-klayout-streamout/core.klayout.gds'), 'json_h': None, 'vh': None, 'metrics': {'design__instance__count': 17885, 'design__instance__area': 168532, 'design__instance_unmapped__count': 0, 'synthesis__check_error__count': 0, 'design__die__bbox': '0.0 0.0 572.925 583.645', 'design__core__bbox': '5.52 10.88 567.18 571.2', 'design__io': 170, 'design__die__area': 334385, 'design__core__area': 314709, 'design__instance__count__stdcell': 17885, 'design__instance__area__stdcell': 168532, 'design__instance__count__macros': 0, 'design__instance__area__macros': 0, 'design__instance__utilization': Decimal('0.535515'), 'design__instance__utilization__stdcell': Decimal('0.535515'), 'floorplan__design__io': 168, 'design__io__hpwl': 72116016, 'design__power_grid_violation__count__net:VGND': 0, 'design__power_grid_violation__count__net:VPWR': 0, 'design__power_grid_violation__count': 0, 'design__instance__displacement__total': Decimal('3228.12'), 'design__instance__displacement__mean': Decimal('0.176'), 'design__instance__displacement__max': Decimal('12.42'), 'route__wirelength__estimated': 421851, 'design__violations': 0, 'antenna__violating__nets': 83, 'antenna__violating__pins': 100, 'route__net': 13480, 'route__net__special': 2, 'route__drc_errors__iter:1': 19636, 'route__wirelength__iter:1': 589106, 'route__drc_errors__iter:2': 6581, 'route__wirelength__iter:2': 583896, 'route__drc_errors__iter:3': 6373, 'route__wirelength__iter:3': 582213, 'route__drc_errors__iter:4': 1296, 'route__wirelength__iter:4': 580796, 'route__drc_errors__iter:5': 109, 'route__wirelength__iter:5': 580731, 'route__drc_errors__iter:6': 25, 'route__wirelength__iter:6': 580799, 'route__drc_errors__iter:7': 1, 'route__wirelength__iter:7': 580768, 'route__drc_errors__iter:8': 0, 'route__wirelength__iter:8': 580766, 'route__drc_errors': 0, 'route__wirelength': 580766, 'route__vias': 116716, 'route__vias__singlecut': 116716, 'route__vias__multicut': 0, 'magic__drc_error__count': 0, 'magic__illegal_overlap__count': 0}}"
+ ],
+ "text/html": [
+ "\n",
+ " \n",
+ " \n",
+ " \n",
+ " Format | \n",
+ " Path | \n",
+ " \n",
+ " \n",
+ " \n",
+ " nl | \n",
+ " openlane_run/11-openroad-fillinsertion/core.nl.v | \n",
+ " \n",
+ " \n",
+ " \n",
+ " pnl | \n",
+ " openlane_run/11-openroad-fillinsertion/core.pnl.v | \n",
+ " \n",
+ " \n",
+ " \n",
+ " def | \n",
+ " openlane_run/11-openroad-fillinsertion/core.def | \n",
+ " \n",
+ " \n",
+ " \n",
+ " odb | \n",
+ " openlane_run/11-openroad-fillinsertion/core.odb | \n",
+ " \n",
+ " \n",
+ " \n",
+ " sdc | \n",
+ " openlane_run/11-openroad-fillinsertion/core.sdc | \n",
+ " \n",
+ " \n",
+ " \n",
+ " spice | \n",
+ " openlane_run/15-magic-spiceextraction/core.spice | \n",
+ " \n",
+ " \n",
+ " \n",
+ " gds | \n",
+ " openlane_run/13-klayout-streamout/core.gds | \n",
+ " \n",
+ " \n",
+ " \n",
+ " klayout_gds | \n",
+ " openlane_run/13-klayout-streamout/core.klayout.gds | \n",
+ " \n",
+ " \n",
+ " \n",
+ " "
+ ]
+ },
+ "metadata": {},
+ "execution_count": 53
+ }
+ ],
+ "source": [
+ "SpiceExtraction = Step.factory.get(\"Magic.SpiceExtraction\")\n",
+ "\n",
+ "spx = SpiceExtraction(state_in=drc.state_out)\n",
+ "spx.start()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "bb876fd2-0258-4820-9151-efa37399376a",
+ "metadata": {
+ "id": "bb876fd2-0258-4820-9151-efa37399376a"
+ },
+ "source": [
+ "#### Layout vs. Schematic (LVS)\n"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "908db3b2-29a1-4a4d-bf49-cc5ecc68593b",
+ "metadata": {
+ "id": "908db3b2-29a1-4a4d-bf49-cc5ecc68593b",
+ "colab": {
+ "base_uri": "https://localhost:8080/",
+ "height": 1000
+ },
+ "outputId": "5f4a8d85-3882-44a2-c19b-b2e923bd2a28"
+ },
+ "outputs": [
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[92m─────────────────────────────────────────────────── \u001b[0mNetgen LVS\u001b[92m ────────────────────────────────────────────────────\u001b[0m\n"
+ ],
+ "text/html": [
+ "─────────────────────────────────────────────────── Netgen LVS ────────────────────────────────────────────────────\n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "\u001b[2;36m[12:57:48]\u001b[0m\u001b[2;36m \u001b[0mVERBOSE Running \u001b[32m'Netgen.LVS'\u001b[0m… \u001b[1m(\u001b[0mLog: \u001b]8;id=863386;file:///content/openlane_run/16-netgen-lvs/netgen-lvs.log\u001b\\.\u001b]8;;\u001b\\\u001b]8;id=859725;file:///content/openlane_run/16-netgen-lvs/netgen-lvs.log\u001b\\\u001b[35m/openlane_run/16-netgen-lvs/\u001b[0m\u001b]8;;\u001b\\\u001b]8;id=346161;file:///content/openlane_run/16-netgen-lvs/netgen-lvs.log\u001b\\\u001b[95mnetgen-lvs.log\u001b[0m\u001b]8;;\u001b\\\u001b[1m)\u001b[0m \u001b]8;id=751966;file:///content/openlane_ipynb/openlane/steps/step.py\u001b\\\u001b[2mstep.py\u001b[0m\u001b]8;;\u001b\\\u001b[2m:\u001b[0m\u001b]8;id=713302;file:///content/openlane_ipynb/openlane/steps/step.py#1085\u001b\\\u001b[2m1085\u001b[0m\u001b]8;;\u001b\\\n"
+ ],
+ "text/html": [
+ "[12:57:48] VERBOSE Running 'Netgen.LVS'… (Log: ./openlane_run/16-netgen-lvs/netgen-lvs.log) step.py:1085\n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Netgen \u001b[1;36m1.5\u001b[0m.\u001b[1;36m255\u001b[0m compiled on Tue Dec \u001b[1;36m5\u001b[0m \u001b[1;92m22:48:12\u001b[0m UTC \u001b[1;36m2023\u001b[0m \n"
+ ],
+ "text/html": [
+ "Netgen 1.5.255 compiled on Tue Dec 5 22:48:12 UTC 2023 \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Warning: netgen command \u001b[32m'format'\u001b[0m use fully-qualified name \u001b[32m'::netgen::format'\u001b[0m \n"
+ ],
+ "text/html": [
+ "Warning: netgen command 'format' use fully-qualified name '::netgen::format' \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Warning: netgen command \u001b[32m'global'\u001b[0m use fully-qualified name \u001b[32m'::netgen::global'\u001b[0m \n"
+ ],
+ "text/html": [
+ "Warning: netgen command 'global' use fully-qualified name '::netgen::global' \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Reading SPICE netlist file \n",
+ "\u001b[32m'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice'\u001b[0m\u001b[33m...\u001b[0m \n"
+ ],
+ "text/html": [
+ "Reading SPICE netlist file \n",
+ "'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice'... \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt \n"
+ ],
+ "text/html": [
+ "Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating placeholder cell definition. \n"
+ ],
+ "text/html": [
+ "Creating placeholder cell definition. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Call to undefined subcircuit sky130_fd_pr__nfet_01v8 \n"
+ ],
+ "text/html": [
+ "Call to undefined subcircuit sky130_fd_pr__nfet_01v8 \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Creating placeholder cell definition. \n"
+ ],
+ "text/html": [
+ "Creating placeholder cell definition. \n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Reading SPICE netlist file \u001b[32m'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice'\u001b[0m\u001b[33m...\u001b[0m\n"
+ ],
+ "text/html": [
+ "Reading SPICE netlist file '/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice'...\n",
+ " \n"
+ ]
+ },
+ "metadata": {}
+ },
+ {
+ "output_type": "display_data",
+ "data": {
+ "text/plain": [
+ "Reading SPICE netlist file \u001b[32m'/root/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice'\u001b[0m\u001b[33m...\u001b[0m \n"
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+ "text/html": [
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+ " Format | \n",
+ " Path | \n",
+ " \n",
+ " \n",
+ " \n",
+ " nl | \n",
+ " openlane_run/11-openroad-fillinsertion/core.nl.v | \n",
+ " \n",
+ " \n",
+ " \n",
+ " pnl | \n",
+ " openlane_run/11-openroad-fillinsertion/core.pnl.v | \n",
+ " \n",
+ " \n",
+ " \n",
+ " def | \n",
+ " openlane_run/11-openroad-fillinsertion/core.def | \n",
+ " \n",
+ " \n",
+ " \n",
+ " odb | \n",
+ " openlane_run/11-openroad-fillinsertion/core.odb | \n",
+ " \n",
+ " \n",
+ " \n",
+ " sdc | \n",
+ " openlane_run/11-openroad-fillinsertion/core.sdc | \n",
+ " \n",
+ " \n",
+ " \n",
+ " spice | \n",
+ " openlane_run/15-magic-spiceextraction/core.spice | \n",
+ " \n",
+ " \n",
+ " \n",
+ " gds | \n",
+ " openlane_run/13-klayout-streamout/core.gds | \n",
+ " \n",
+ " \n",
+ " \n",
+ " klayout_gds | \n",
+ " openlane_run/13-klayout-streamout/core.klayout.gds | \n",
+ " \n",
+ " \n",
+ " \n",
+ " "
+ ]
+ },
+ "metadata": {},
+ "execution_count": 54
+ }
+ ],
+ "source": [
+ "LVS = Step.factory.get(\"Netgen.LVS\")\n",
+ "\n",
+ "lvs = LVS(state_in=spx.state_out)\n",
+ "lvs.start()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "2312679b-e124-46da-a9df-cd11f922da79",
+ "metadata": {
+ "id": "2312679b-e124-46da-a9df-cd11f922da79"
+ },
+ "source": [
+ "The detailed PPA information is illustrated below. We will tape it out in mid-year on the efabless OpenMPW-9 shuttle."
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "4b2650eb-6c18-49ef-8a9e-5497ec9bd96a",
+ "metadata": {
+ "id": "4b2650eb-6c18-49ef-8a9e-5497ec9bd96a"
+ },
+ "source": [
+ "\n",
+ "|$$Feature$$|$$Parameters$$|\n",
+ "|:--:|:----------:|\n",
+ "|$$PDK$$ |$$Skywater 130nm$$|\n",
+ "|$$Gate Count$$ |$$ 66,000$$|\n",
+ "|$$IO$$ | $$186 Ports$$|\n",
+ "|$$Frequency$$ | $$125MHz$$|\n",
+ "|$$Total Power$$ |$$28.7mW$$|\n",
+ "|$$Core Area$$ |$$0.42{mm}^2$$|\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "5bae58bb-aa96-4546-ba94-54db44c1422c",
+ "metadata": {
+ "id": "5bae58bb-aa96-4546-ba94-54db44c1422c"
+ },
+ "source": [
+ "## Evaluation"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "615688c5-adcc-4471-ab88-e3cc768ffc36",
+ "metadata": {
+ "id": "615688c5-adcc-4471-ab88-e3cc768ffc36"
+ },
+ "source": [
+ "### A. Design Capability Analysis\n",
+ "We performed tests on various modules in our RISC-V CPU to investigate the capability of ChatChisel in hardware designs. We generate Chisel and Verilog using the same prompt and compare the pass rate of the generated design in terms of syntax and function verification, respectively. The generation capability is shown in the figure. The results indicate that the design generation using Chisel outperforms Verilog by 31.86%. This improvement can be attributed to the higher abstraction level, modular design nature, and reusable design libraries of Chisel. As such, the LLM can generate accurate hardware designs with Chisel codes based on the prompt requirements."
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "5e2e87d5-2ad8-42a7-b865-4841500faab8",
+ "metadata": {
+ "id": "5e2e87d5-2ad8-42a7-b865-4841500faab8"
+ },
+ "source": [
+ "\n",
+ " \n",
+ " Comparisons of Chisel & Verilog \n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "d3146eed-e854-4ba4-9d41-0ec818d27397",
+ "metadata": {
+ "id": "d3146eed-e854-4ba4-9d41-0ec818d27397"
+ },
+ "source": [
+ "In addition, we analyzed the power and area for these modules. The results, shown in table, reveal that ChatChisel achieves an average of 11.45% area reduction and 1.80% power decrease as compared to the Verilog generation of the same CPU design, implying the advantages of LLM-based hardware design with Chisel."
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "857b6ec6-b59f-4839-94a3-3816db14b6b3",
+ "metadata": {
+ "id": "857b6ec6-b59f-4839-94a3-3816db14b6b3"
+ },
+ "source": [
+ "\n",
+ "|$Workload$|$HDL$|$Area/{mm^2}$|$Static Power/mW$|\n",
+ "|:--:|:----------:|:----------:|:----------:|\n",
+ "|$Control$ |$Chisel$|$2.11\\times 10^{-3}$|$0.014$|\n",
+ "| |$Verilog$|$2.84\\times 10^{-3}$|$0.0152$|\n",
+ "|$ALU$ |$Chisel$|$0.02336$|$0.559$|\n",
+ "| |$Verilog$|$0.02058$|$0.445$|\n",
+ "|$BTB$ |$Chisel$|$5.85\\times 10^{-3}$|$0.633$|\n",
+ "| |Verilog|$6.88\\times 10^{-3}$|$0.53$|\n",
+ "|$BHT$ |$Chisel$|$0.09695$|$10.9$|\n",
+ "| |$Verilog$|$0.1127$|$11.2$|\n",
+ "|$Fetch$ |$Chisel$|$0.1144$|$13.2$|\n",
+ "| |$Verilog$|$0.13102$|$13.4$|"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "9f8f43e1-2a67-42b6-97c7-ab048d97ee53",
+ "metadata": {
+ "id": "9f8f43e1-2a67-42b6-97c7-ab048d97ee53"
+ },
+ "source": [
+ "### B. Ablation Studies\n",
+ "\n",
+ "We conducted a series of ablation experiments to assess the impact of design decomposition, Tool Enhanced LLM Error Correction, and the utilization of RAG in ChatChisel. We employed GPT-3.5-turbo to test various modules within our CPU, with the results presented in the figure below."
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "533ff765-56ff-4072-8bf0-2d50a1bb27e7",
+ "metadata": {
+ "id": "533ff765-56ff-4072-8bf0-2d50a1bb27e7"
+ },
+ "source": [
+ "\n",
+ " \n",
+ " \n",
+ " Design Decomposition Analysis \n",
+ " \n",
+ " \n",
+ " \n",
+ " Debugging & RAG Analysis \n",
+ " \n",
+ " \n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "a093d5ce-400e-4cb5-8ea0-e8e669f23270",
+ "metadata": {
+ "id": "a093d5ce-400e-4cb5-8ea0-e8e669f23270"
+ },
+ "source": [
+ "In the first set of experiments, we observed that none of\n",
+ "the modules were successfully generated without the suppor\n",
+ "of design decompositio . Specifically, the Control modu e\n",
+ "failed to generate a complete module due to the limi ed\n",
+ "output tokens, while the Fetch and Hazard modules were\n",
+ "unable to be generated due to their high complexity. This\n",
+ "highlights the rapid decrease in the pass rate of modulegeneration with increasing design complexity. In the second et of\n",
+ "experiments, ChatChisel demonstrated an average gen ration\n",
+ "capability improvement of 62.17% over the workflow without\n",
+ "tool-enhanced LLM error correction. Notably, This ebugging\n",
+ "stage significantly reduced iteration times and pre ented the\n",
+ "LLM from e countering recurring errors during ve ification,\n",
+ "showcasing its importance in the generation pro ess. In the\n",
+ "third set of experiments, the average design apability of\n",
+ "ChatChisel was 27.93% higher when RA was employed\n",
+ "compared. This evaluation provides empirical impacts of RAG\n",
+ "upon improving the hardware design capability of LLMs."
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "id": "8f8d7ba0-92a9-4602-a488-709127e2ed47",
+ "metadata": {
+ "id": "8f8d7ba0-92a9-4602-a488-709127e2ed47"
+ },
+ "source": [
+ "## Conclusion\n",
+ "This article explored the use of LLMs to generate Chisel code for RTL-level circuit design. Through comparative experiments, it was demonstrated that the ability of GPT-3.5-turbo to generate Chisel surpassed its ability to generate Verilog. We introduced ChatChisel, a framework for directly generating\n",
+ "agile HDLs from natural language using LLMs. This workflow leverages multiple expert LLMs and addresses certain challenges in LLM generation through techniques such as Design Decomposition, Tool Enhanced LLM Error Correction, and Structured Prompt with RAG. These advancements significantly improve the efficiency of RTL-level agile design. By utilizing the ChatChisel workflow, we successfully generated a RISC-V CPU, showcasing the potential of LLMs in generating complex circuits."
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {
+ "id": "5oL-i9_0YyAU"
+ },
+ "source": [
+ "## Acknowledgement\n",
+ "\n",
+ "\n",
+ "* We would like to express our sincere gratitude to the **VLSI'24 Code-a-Chip Contest** organizing committee for their support and coordination.\n",
+ "* We are also deeply appreciative of the generous support provided by Amazon Cloud Technology, which has enabled the successful completion of this project.\n",
+ "* Additionally, *some portions of the work* presented in this project have been accepted as * research papers* at the **61th ACM/IEEE DAC'24** and **ACM/IEEE ISEDA'24** conference. We welcome any citations, suggestions, and potential future collaborations regarding this project.\n",
+ "* We are thankful for the opportunity to contribute to the VLSI community and look forward to the valuable feedback and discussions that may arise from this endeavor.\n",
+ "\n",
+ "\n",
+ "\n",
+ "\n",
+ "\n",
+ "\n",
+ "\n",
+ "\n",
+ "\n",
+ "\n"
+ ],
+ "id": "5oL-i9_0YyAU"
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3 (ipykernel)",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.11.7"
+ },
+ "colab": {
+ "provenance": [],
+ "collapsed_sections": [
+ "0a4cb2db-d455-4c36-b3a4-7b89ce0514b8",
+ "966fe7c7-9e89-4a72-90c9-87b818916d9a"
+ ]
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 5
+}
\ No newline at end of file
|