A simple Risc V CPU supporting a 5 stage pipeline and in conformance with RISC V 32I Instruction set.
A single core capable of handling every RV32I Instruction. Minimal verification has been conducted thusfar, however the framework to run simulations and view waveforms are in place.
To Do: Verify Cache,
Add a Memory Controller,
Verify rest of RV32I,
Get synthesis to run,
This project was started to gain experience in digital design and brush up on chip architecture while becoming equipped with RISC V ISA. RTL is described in Verilog 2012 and EDA tools consist of Icarus Verilog & Yosys. I also found the open source risc v assembler python package provided by _ very useful when testing in my Test Bench.
The RV32 Processor is architected as a single core standard 5 stage pipeline. Only Fetch and Decode stages will stall in two cases: Failed Branch Prediction and sequential data conflict when the first instruction must write from data memory.
The cache is currently being testbenchs. likely not useable at the moment.
These instructions will get you a copy of the project up and running on your local machine for development and testing purposes.
Verify iverilog and gtkwave are installed and run the following commands from root:
cd run
source run_spek.csh
What things you need to install the software and how to install them.
- Icarus Verilog - Compiler
- GTKWave - Waveform Simulator
- YoSys - Synthesis Suite
- [Risc V Assembler Python Package] (https://github.com/celebi-pkg/riscv-assembler) - Assembler helper
- Verilog 2012 - Language
- Icarus Verilog - Compiler
- GTKWave - Waveform Simulator
- Risc V Manual - Instruction Set Architecture
- @sprsr - Idea & Initial work
- Open Source EDA Tools
- Risc V Organization
- Onur Mutlu (Computer Architecture lectures on Youtube)