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dram.html
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<!-- dram overview -->
<!doctype html>
<html lang="en">
<head>
<meta charset="utf-8">
<title>dram</title>
<meta content="width=device-width,initial-scale=1,user-scalable=no" name=viewport>
<script src="style.js" defer></script>
</head><body>
         Dynamic Random Access Memory
   <em>This is a brief summary describing dram, or a
   1T1C memory cell, and its role during the aquisition
   of a 32 bits.
     We'll discuss how it reads, writes
   and refreshes said address.</em>
    <em>NOTE: the angular position of this diagram
    should be 90 degrees rotated for the proper
    orientation and illustration</em>
    wl
    -|-----.-------
    | |
    bl | _|_
    |___| T |____|
    | |
    | __|__
    | c _____
    |
    _|_
    -
  <em>1a</em> <em>bitline[row], transistor = 1 or 0, wline[column], capacitor</em>
   [read][write][refresh]
   .dram= is a dual inline memory module. It is a physical hardware component with a viscious amount of cycles to maintain.
   Its purpose is to prefetch, move data before it is needed. It is connected to the cpu via channels along the motherboard
   i.e. memory controller to physical channel.
   Channel A Channel B (two memory channels)
   They can accept 32 bits, divided into 4 integrated circuits, so they only read and write 8 of those bits at a time.
   Power goes through the motherboard to its power controller.
   During the Address Input process, the cpu send a 31 bit address.
   3 of those bits go to the bank group.
   2 go to the bank, and 16 to the row decoder.
   The remaining 10 are for the column multiplexer.
   PAUSE!: <em>Remember, there's no such thing as an address, however what is real is a bit, if you consider the
   ramifications of voltage in this context as a bit</em>
   Therefore we might say this is all in attempt to describe a bit.
   The wordline comes first. It lies on the bottom layer, directly connected to the transistor and capacitor.
   Applying a voltage to the wordline turns on the transistor and channels to the bitline, but not always as
   in the case of (see below: <em>When a wordline is active</em>).
   This voltage is so that a capacitor can retain a charge of 1 or remain a 0, uncharged. When the wordline
   is off the transistor is off, thus the capacitor is uncharged. When a wordline is active, capacitors of
   that row are active as well. However the bitline remains inactive or else everything in every row and
   column would be active, which would defeat the purpose.
   It is this quilted-pattern cell made of metal-oxide (MOS), a metal-oxide semiconductor that makes this
   process so. The full term for this kind of transistor used is MOSFET (plus the help of the capacitor)
   During the read process, a 31 bit address is sent from cpu to dram.
   5 bits select a specific bank. Next, all the wordlines must be turned off in that bank, to isolate
   capacitors and precharge ALL the bitlines to 0.5v. Next, the 16 bit row address turns on a row and then
   all of the capacitors in that row are connected to their bitline.
   If an individual capacitor holds a 1 ~ charged to 1.0v, then some charge flows from the capacitor to these
   0.5v bitlines, and the voltage on the bitline increases. The sense amplifier then detects the slight change
   on the bitline and amplifies it by pushing the voltage on the bitline up to 1.0v.
   However if a 0 is stored in the capacitor, charge flows from the bitline into the capacitor, and the 0.5v
   bitline decreases. The sense amplifier then detects this change, amplifies it, and drives the bitline voltage
   down to 0 volts (or ground).
   Now the bitlines are 1 or 0 volts corresponding to the stored charge of the capacitors in the active row!
   The state of this row is considered to be "open".
   During the write process,
   {write command} {address} {8 bits to be written} are sent from the cpu to dram.
   And like before the bank is selected, the capacitors are isolated, and the bitlines are precharged to 0.5v.
   Using a 16 bit address, a single row is activated. The capacitors perturb the bitline, and the sense amplifier
   detects this, driving the bitlines to a 1 or 0 (thus opening the row).
   Next, the column address goes to the column multiplexer. Because the write command was sent, the multiplexer
   connects the specific 8 bitines to the write driver, which contains the 8 bits the cpu had sent along the
   data wires and requested to write. These drivers will override whatever was previously happening on said
   bitlines ~ driving each of the 8 bitlines to 1.0v for 1, or 0 volts for 0
   This new bitline voltage overrides the previously stored charges in each of the 8 capacitors in the open row,
   thereby writing 8 bits of data to the memory cells corresponding to the 31 bit address.
   Note that writing and reading happens concurrently.
   During the refresh process, all the rows are sequentially closed, the bitlines are precharged to 0.5v,
   and a row is "opened".
   For this, again, the capacitors perturb the bitlines and the sense amplifiers drive the bitlines and capacitors
   to an "open" row, 1.0v (or down to 0 depending on the stored value of the capacitor).
   This process of row close, pre-charging, opening and sense ampliying happens row after row until ALL of the rows are refreshed.
   When the cpu sends a read or write command to a row that is already open it's called a "page hit".
   This can happen over and over. A page hit skips all of the steps required to open a row, and just uses the 10 bit
   column address to multiplex a different set of 8 columns aka bitlines. This connects them back to the read or
   write driver thereby saving alot of time!... A "row miss" is when the next address is for a different row
   which results in the dram closing and isolating the currently open row, and opening a new row.
   Lastly, there's a couple other optimizations native to dram. By having multiple bank groups the cpu can refresh
   one bank in each bank group at a time, while utilizing the other three. This reduces the overall impact of refreshing.
   For a 'burst buffer', 128 wires connect to 128 bit buffer locations.
   10 bit column address becomes two different parts.
   6 bits used for the multiplexer.
   4 bits for the burst buffer.
   [for a read command], 128 memory cells, bitlines, are connected to the burst buffer using the 6 column bits,
   thereby temporarily loading or caching 128 values into the burst buffer. Using the 4 bits for the buffer,
&meps;  8 data locations in the burst buffer are connected to the read drivers, and the data is sent to the cpu.
   By cycling through these 4 bits, all 16 sets of 8 bits are read out, and thus the burst length is 16.
   A new set of 128 bitlines are connected and loaded into the burst buffer.
   For the sense amplifier's design optimization
   (see; <em>cross coupled inverter</em>)
</body></html>