C-based memory model for RTL simulation

[paulmnt]

Bare metal applications with large memory footprints cannot be easily simulated.
Increasing the size of ahbram_sim beyond a few MB slows down the RTL simulator.
Furthermore, when RISC-V is selected, accelerators operate on a memory region with high base address. This region is not represented in the current memory model.
Simulations still work in most cases, because addresses wrap around, as long the result of wrap around does not conflict with the location of the program, or its data.

Proposed solution
Any access to the DRAM model in ahbram_sim should not access an RTL array. Instead, operations should be redirected to a C-based model. Allocated memory regions should be represented as a hash table for quick access to the entire address space, with little memory footprint for the host.