2020-12-10: OpenHW formally decalres RTL Freeze for CV32E40P
2020-10-15: Aldec's Riviera-PRO SystemVerilog simulator is now supported by core-v-verif. Check out the README in mk/uvmt for more information.
2020-09-04: a new (and much better) method of specifying and organizating test-programs and simulations is now merged in. See slide "Test Specification Updates" in the 2020-08-31 CV32E40P project update.
2020-06-12: a new "Board Support Package" for CV32E40P simulations is installed at cv32/bsp. This BSP should be used to compile/assemble your test-programs. The Makefiles for both the CORE testbench and UVM verification environment have been updated to use this BSP.
2020-06-02: The Imperas OVPsim Instruction Set Generator has been integrated into the UVM environment as the Referenece Model for the CV32E40(P). You will need to obtain a license from Imperas to use it.
2020-02-28: The OpenHW Group CV32E40P is now live!
This repository no longer contains a local copy of the RTL. The RTL is cloned from the appropriate core-v-cores repository as needed. The specific branch and hash of the RTL is controlled by a set of variables in cv32e40p/sim/Common.mk.
2020-02-10: The core-v-verif repository now supports multiple cores. The previously named cv32 directory is now cv32e40p to represent the testbench for the CV32E40P core. Future cores will be verified in respectively named directories in core-v-verif as siblings to cva6 and cv32e40p.