From a2787b02ebe4f57777ebc740b1ca7ba628ca498f Mon Sep 17 00:00:00 2001 From: Scott Nellenbach Date: Thu, 20 Jul 2023 13:52:13 -0400 Subject: [PATCH] fixes to cheader output --- .vscode/launch.json | 3 +- .vscode/tasks.json | 19 + src/ordt/output/cheader/CHeaderBuilder.java | 206 +- test/basic_tests/js_basic_01/golden/output.h | 108 + test/basic_tests/rdl_basic_01/golden/output.h | 110 + .../rdl_c_header/golden/ordt_pio.cpp | 286 ++ .../rdl_c_header/golden/ordt_pio.hpp | 209 + .../rdl_c_header/golden/ordt_pio_common.cpp | 111 + .../rdl_c_header/golden/ordt_pio_common.hpp | 95 + .../rdl_c_header/golden/ordt_pio_drv.cpp | 204 + .../rdl_c_header/golden/ordt_pio_drv.hpp | 86 + test/basic_tests/rdl_c_header/golden/output.h | 43 +- .../basic_tests/rdl_c_header/golden/output.js | 42 +- .../basic_tests/rdl_c_header/golden/output.py | 294 ++ .../rdl_c_header/golden/output.reglist | 9 +- .../basic_tests/rdl_c_header/golden/output.sv | 113 +- test/basic_tests/rdl_c_header/golden/output.v | 128 +- .../rdl_c_header/golden/output.xml | 67 +- .../rdl_c_header/golden/uvm_reg_jrdl_pkg.sv | 4 +- .../rdl_c_header/golden/uvmregs.sv | 48 +- test/basic_tests/rdl_c_header/golden/vbench.v | 353 -- test/basic_tests/rdl_c_header/output.h | 73 - .../rdl_fieldstruct/golden/output.h | 49 + test/basic_tests/rdl_hello/golden/output.h | 28 + test/basic_tests/rdl_hier_01/golden/output.h | 744 ++++ test/basic_tests/rdl_hier_02/golden/output.h | 1159 +++++ test/basic_tests/rdl_hwload/golden/output.h | 58 + test/basic_tests/rdl_intr_01/golden/output.h | 73 + test/basic_tests/rdl_iwrap/golden/output.h | 50 + test/basic_tests/rdl_sec_if/golden/output.h | 96 + .../rdl_uvmmem_default/golden/output.h | 3743 +++++++++++++++++ .../rdl_uvmmem_lite/golden/output.h | 3743 +++++++++++++++++ .../rdl_uvmmem_mimic/golden/output.h | 3743 +++++++++++++++++ .../rdl_uvmmem_nums/golden/output.h | 3743 +++++++++++++++++ .../rdl_write_enable/golden/output.h | 63 + test/scripts/makeallgold | 2 +- test/scripts/makegold | 2 +- 37 files changed, 19286 insertions(+), 621 deletions(-) create mode 100644 .vscode/tasks.json create mode 100644 test/basic_tests/js_basic_01/golden/output.h create mode 100644 test/basic_tests/rdl_basic_01/golden/output.h create mode 100644 test/basic_tests/rdl_c_header/golden/ordt_pio.cpp create mode 100644 test/basic_tests/rdl_c_header/golden/ordt_pio.hpp create mode 100644 test/basic_tests/rdl_c_header/golden/ordt_pio_common.cpp create mode 100644 test/basic_tests/rdl_c_header/golden/ordt_pio_common.hpp create mode 100644 test/basic_tests/rdl_c_header/golden/ordt_pio_drv.cpp create mode 100644 test/basic_tests/rdl_c_header/golden/ordt_pio_drv.hpp create mode 100644 test/basic_tests/rdl_c_header/golden/output.py delete mode 100644 test/basic_tests/rdl_c_header/golden/vbench.v delete mode 100644 test/basic_tests/rdl_c_header/output.h create mode 100644 test/basic_tests/rdl_fieldstruct/golden/output.h create mode 100644 test/basic_tests/rdl_hello/golden/output.h create mode 100644 test/basic_tests/rdl_hier_01/golden/output.h create mode 100644 test/basic_tests/rdl_hier_02/golden/output.h create mode 100644 test/basic_tests/rdl_hwload/golden/output.h create mode 100644 test/basic_tests/rdl_intr_01/golden/output.h create mode 100644 test/basic_tests/rdl_iwrap/golden/output.h create mode 100644 test/basic_tests/rdl_sec_if/golden/output.h create mode 100644 test/basic_tests/rdl_uvmmem_default/golden/output.h create mode 100644 test/basic_tests/rdl_uvmmem_lite/golden/output.h create mode 100644 test/basic_tests/rdl_uvmmem_mimic/golden/output.h create mode 100644 test/basic_tests/rdl_uvmmem_nums/golden/output.h create mode 100644 test/basic_tests/rdl_write_enable/golden/output.h diff --git a/.vscode/launch.json b/.vscode/launch.json index 6a42703..73bbdd0 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -8,9 +8,8 @@ "type": "java", "name": "Ordt", "request": "launch", - "mainClass": "Ordt", + "mainClass": "ordt.extract.Ordt", "projectName": "ordt" } - ] } \ No newline at end of file diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..e1ac11e --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,19 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "type": "java (build)", + "paths": [ + "${workspace}" + ], + "isFullBuild": true, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [], + "label": "java (build): Build Workspace", + "detail": "$(tools) Build all the Java projects in workspace." + } + ] +} \ No newline at end of file diff --git a/src/ordt/output/cheader/CHeaderBuilder.java b/src/ordt/output/cheader/CHeaderBuilder.java index 5aa8aed..6d35baa 100644 --- a/src/ordt/output/cheader/CHeaderBuilder.java +++ b/src/ordt/output/cheader/CHeaderBuilder.java @@ -1,5 +1,6 @@ package ordt.output.cheader; +import ordt.extract.RegNumber; import ordt.output.FieldProperties; import ordt.output.OutputBuilder; import ordt.output.common.OutputLine; @@ -7,25 +8,14 @@ import java.io.BufferedWriter; import java.util.ArrayList; +import java.util.Iterator; import java.util.List; public class CHeaderBuilder extends OutputBuilder { - private List memoryMapOutputList = new ArrayList(); private List bitfieldOutputList = new ArrayList(); - private List commonOutputList = new ArrayList(); - private List explicitFunctionOutputList = new ArrayList(); - private int indentLvl = 0; private final int noIndent = 0; - /******************************************************************************************************************* - * User configurable parameters - ******************************************************************************************************************/ - - /******************************************************************************************************************* - * Internal variables - ******************************************************************************************************************/ - public CHeaderBuilder(ordt.extract.RegModelIntf model) { setBaseBuilderID(); // set unique ID of this instance this.model = model; @@ -37,21 +27,72 @@ public CHeaderBuilder(ordt.extract.RegModelIntf model) { model.getRoot().generateOutput(null, this); // generate output structures recursively starting at model root } + public class MemoryMapEntry { + public RegNumber address; + public String regName; + public MemoryMapEntry(RegNumber address, String regName) { + this.address = address; + this.regName = regName; + } + } + private List memoryMapEntryList = new ArrayList(); + + String explicitFunctionString = + "/*\n" + + " * bits.h\n" + + " *\n" + + " * Struct and function declarations for dealing with bit assignment.\n" + + " */\n" + + "\n" + + "#ifndef _BITS_H\n" + + "#define _BITS_H\n" + + "\n" + + "#define BITS_PER_LONG 32\n" + + "\n" + + "// ## allows token concatenation\n" + + "//X = 1 and Y = 10 would return 110\n" + + "#define __AC(X,Y)\t(X##Y)\n" + + "#define _AC(X,Y)\t__AC(X,Y)\n" + + "\n" + + "#define _UL(x)\t\t(_AC(x, UL))\n" + + "#define UL(x)\t\t(_UL(x))\n" + + "\n" + + "#define BIT(nr) (1UL << (nr))\n" + + "// BIT defines a bit mask for the specified bit number from 0 to whatever fits into an unsigned long\n" + + "// so BIT(10) should evaluate to decimal 1024 (which is binary 1 left shifted by 10 bits)\n" + + "\n" + + "#define GENMASK_INPUT_CHECK(h, l) 0\n" + + "\n" + + "// h is high index, l is low index in a bitfield\n" + + "// __GENMASK returns 32 bit number with 1s in the h-to-l field\n" + + "// if h = 4 and l = 1, __GENMASK would return 00000000000000000000000000011110\n" + + "#define __GENMASK(h, l) \\\n" + + "\t(((~UL(0)) - (UL(1) << (l)) + 1) & \\\n" + + "\t (~UL(0) >> (BITS_PER_LONG - 1 - (h))))\n" + + "\n" + + "#define GENMASK(h, l) \\\n" + + "\t(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))\n" + + "\n" + + "#endif /* _BITS_H */\n"; + + /******************************************************************************************************************* + * Builder override methods + ******************************************************************************************************************/ + @Override public void addField() { - while (fieldList.size() > 0){ - FieldProperties field = fieldList.remove(); - int lowIndex = field.getLowIndex(); - int highIndex = field.getLowIndex() + field.getFieldWidth() - 1; - - if (lowIndex == highIndex) { - String bitIndices = String.format("%d", lowIndex); - bitfieldOutputList.add(new OutputLine(noIndent, String.format("#define %s BIT(%s)", field.getTextName(), bitIndices))); - } - if (lowIndex != highIndex) { - String bitIndices = String.format("%d, %d", highIndex, lowIndex); - bitfieldOutputList.add(new OutputLine(noIndent, String.format("#define %s GENMASK(%s)", field.getTextName(), bitIndices))); - } + int lowIndex = fieldProperties.getLowIndex(); + int highIndex = fieldProperties.getLowIndex() + fieldProperties.getFieldWidth() - 1; + String fieldName = fieldProperties.getBaseName().toUpperCase(); + String textNameComment = (fieldProperties.getTextName() == null) ? "" : " /* " + fieldProperties.getTextName() + " */"; + + if (lowIndex == highIndex) { + String bitIndices = String.format("%d", lowIndex); + bitfieldOutputList.add(new OutputLine(noIndent, String.format("#define %s BIT(%s)%s", fieldName, bitIndices, textNameComment))); + } + else { + String bitIndices = String.format("%d, %d", highIndex, lowIndex); + bitfieldOutputList.add(new OutputLine(noIndent, String.format("#define %s GENMASK(%s)%s", fieldName, bitIndices, textNameComment))); } } @Override @@ -60,14 +101,15 @@ public void addAliasField() { @Override public void addRegister() { - String regAddress = regProperties.getExtractInstance().getAddress().toString(); - String regName = regProperties.getTextName(); - - if (ExtParameters.cheaderAddMemoryMap()) - memoryMapOutputList.add(new OutputLine(indentLvl, String.format("%s = %s,", regName, regAddress))); - - if (ExtParameters.cheaderAddBitfields()) - bitfieldOutputList.add(new OutputLine(noIndent, String.format("\n/* %s registers */", regName))); + String regName = regProperties.getBaseName().toUpperCase(); + + if (ExtParameters.cheaderAddMemoryMap()) + memoryMapEntryList.add(new MemoryMapEntry(regProperties.getBaseAddress(), regName)); + + if (ExtParameters.cheaderAddBitfields()) { + String textName = (regProperties.getTextName() == null) ? "" : " (" + regProperties.getTextName() + ")"; + bitfieldOutputList.add(new OutputLine(noIndent, "\n/* " + regName + textName + " register fields */")); + } } @Override @@ -83,41 +125,35 @@ public void finishRegSet() { @Override public void addRegMap() { - if (ExtParameters.cheaderAddMemoryMap()) - addHeader(); } @Override public void finishRegMap() { - if (ExtParameters.cheaderAddMemoryMap()) - endEnum(); } @Override public void write(BufferedWriter bw) { bufferedWriter = bw; - // Comments about auto generated file with name and date - addComments(); - for (OutputLine jsLine : commonOutputList){ - writeStmt(jsLine.getIndent(), jsLine.getLine()); - } + writeStmt(0, String.format("#ifndef __%s_REGISTER_MAP__", getAddressMapName().toUpperCase())); + writeStmt(0, String.format("#define __%s_REGISTER_MAP__\n", getAddressMapName().toUpperCase())); // Explicitly declare all functions in the same header file - if (ExtParameters.cheaderExplicitFunctions()){ - explicitFunctions(); - for (OutputLine jsLine : explicitFunctionOutputList){ - writeStmt(jsLine.getIndent(), jsLine.getLine()); - } - } - else writeStmt(noIndent,"#include \n"); + if (ExtParameters.cheaderExplicitFunctions()) + writeStmt(noIndent, explicitFunctionString); + else writeStmt(noIndent, "#include \n"); // Write memory map (enum) - if (ExtParameters.cheaderAddMemoryMap()) - // sherlock: memoryMapOutputList is array, OutputLine is datatype for temp variable jsLine - // sherlock: loop iterates over array and jsline becomes each element - for (OutputLine jsLine : memoryMapOutputList) { - writeStmt(jsLine.getIndent(), jsLine.getLine()); + if (ExtParameters.cheaderAddMemoryMap()) { + writeStmt(0, String.format("/* %s_REGISTERS memory map */", getAddressMapName().toUpperCase())); + writeStmt(0, String.format("enum %s_REGS {", getAddressMapName().toUpperCase())); + Iterator mapIter = memoryMapEntryList.iterator(); + while (mapIter.hasNext()) { + MemoryMapEntry mapEntry = mapIter.next(); + String suffix = (mapIter.hasNext())? "," : ""; + writeStmt(1, mapEntry.regName + " = " + mapEntry.address.toString() + suffix); } + writeStmt(0, "};"); + } // Write bitfields (#define) if (ExtParameters.cheaderAddBitfields()) @@ -125,67 +161,7 @@ public void write(BufferedWriter bw) { writeStmt(jsLine.getIndent(), jsLine.getLine()); } - endComments(); - } - - /******************************************************************************************************************* - * Builder specific methods - ******************************************************************************************************************/ - void addComments() { - commonOutputList.add(new OutputLine(indentLvl, String.format("#ifndef __%s_REGISTER_MAP__", getAddressMapName().toUpperCase()))); - commonOutputList.add(new OutputLine(indentLvl, String.format("#define __%s_REGISTER_MAP__\n", getAddressMapName().toUpperCase()))); - } - - void addHeader() { - memoryMapOutputList.add(new OutputLine(indentLvl, String.format("/* %s_REGISTERS memory map */", getAddressMapName().toUpperCase()))); - memoryMapOutputList.add(new OutputLine(indentLvl++, String.format("enum %s_REGS {", getAddressMapName().toUpperCase()))); - } - - void endEnum(){ - memoryMapOutputList.add(new OutputLine(--indentLvl, "};")); - } - - void endComments() { - commonOutputList.add(new OutputLine(indentLvl, "#endif")); writeStmt(noIndent, "\n#endif"); } - - void explicitFunctions(){ - explicitFunctionOutputList.add(new OutputLine(indentLvl, String.format("/*\n" + - " * bits.h\n" + - " *\n" + - " * Struct and function declarations for dealing with bit assignment.\n" + - " */\n" + - "\n" + - "#ifndef _BITS_H\n" + - "#define _BITS_H\n" + - "\n" + - "#define BITS_PER_LONG 32\n" + - "\n" + - "// ## allows token concatenation\n" + - "//X = 1 and Y = 10 would return 110\n" + - "#define __AC(X,Y)\t(X##Y)\n" + - "#define _AC(X,Y)\t__AC(X,Y)\n" + - "\n" + - "#define _UL(x)\t\t(_AC(x, UL))\n" + - "#define UL(x)\t\t(_UL(x))\n" + - "\n" + - "#define BIT(nr) (1UL << (nr))\n" + - "// BIT defines a bit mask for the specified bit number from 0 to whatever fits into an unsigned long\n" + - "// so BIT(10) should evaluate to decimal 1024 (which is binary 1 left shifted by 10 bits)\n" + - "\n" + - "#define GENMASK_INPUT_CHECK(h, l) 0\n" + - "\n" + - "// h is high index, l is low index in a bitfield\n" + - "// __GENMASK returns 32 bit number with 1s in the h-to-l field\n" + - "// if h = 4 and l = 1, __GENMASK would return 00000000000000000000000000011110\n" + - "#define __GENMASK(h, l) \\\n" + - "\t(((~UL(0)) - (UL(1) << (l)) + 1) & \\\n" + - "\t (~UL(0) >> (BITS_PER_LONG - 1 - (h))))\n" + - "\n" + - "#define GENMASK(h, l) \\\n" + - "\t(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))\n" + - "\n" + - "#endif /* _BITS_H */"))); - } + } \ No newline at end of file diff --git a/test/basic_tests/js_basic_01/golden/output.h b/test/basic_tests/js_basic_01/golden/output.h new file mode 100644 index 0000000..615126d --- /dev/null +++ b/test/basic_tests/js_basic_01/golden/output.h @@ -0,0 +1,108 @@ +// Ordt 230719.01 autogenerated file +// Input: ./js_basic_01/test.js +// Parms: ./js_basic_01/test.parms +// Date: Thu Jul 20 13:46:38 EDT 2023 +// + +#ifndef __SIMPLE1_REGISTER_MAP__ +#define __SIMPLE1_REGISTER_MAP__ + +#include + +/* SIMPLE1_REGISTERS memory map */ +enum SIMPLE1_REGS { + STATS_DISABLE_CHECK_0 = 0x1000, + STATS_DISABLE_CHECK_1 = 0x1004, + STATS_FEATURES = 0x1100, + STATS_LOG_ADDRESS1 = 0x1104, + STATS_LOG_ADDRESS2 = 0x1110, + STATS_WIDE_REG = 0x1120, + RDR_REORDER_WINDOW = 0x4000, + RDR_STREAM_RECONF = 0x4004, + RDR_CP_FP_WR_BUFFER_0 = 0x61c0, + RDR_CP_FP_WR_BUFFER_1 = 0x61c4, + RDR_CP_FP_WR_BUFFER_2 = 0x61c8, + RDR_CP_FP_WR_BUFFER_3 = 0x61cc, + RDR_ROLL32_COUNTER_REG = 0x61d0, + RDR_SAT32_COUNTER_REG = 0x61d4, + RDR_RCNT_SAT_LOG = 0x61d8, + EXTRA_REG = 0x61dc +}; + +/* STATS_DISABLE_CHECK_0 (disable_check register) register fields */ +#define STATS_DISABLE_CHECK_0_L0_B3 BIT(6) /* l0_b3 field */ +#define STATS_DISABLE_CHECK_0_L0_B2 BIT(5) /* l0_b2 field */ +#define STATS_DISABLE_CHECK_0_L0_B1 BIT(4) /* l0_b1 field */ +#define STATS_DISABLE_CHECK_0_L0_B0 BIT(3) /* l0_b0 field */ +#define STATS_DISABLE_CHECK_0_LUT_ST BIT(2) /* lut_st field */ +#define STATS_DISABLE_CHECK_0_CBUF_FIFO BIT(1) /* cbuf_fifo field */ +#define STATS_DISABLE_CHECK_0_TIMER_SRAM BIT(0) /* timer_sram field */ + +/* STATS_DISABLE_CHECK_1 (disable_check register) register fields */ +#define STATS_DISABLE_CHECK_1_L0_B3 BIT(6) /* l0_b3 field */ +#define STATS_DISABLE_CHECK_1_L0_B2 BIT(5) /* l0_b2 field */ +#define STATS_DISABLE_CHECK_1_L0_B1 BIT(4) /* l0_b1 field */ +#define STATS_DISABLE_CHECK_1_L0_B0 BIT(3) /* l0_b0 field */ +#define STATS_DISABLE_CHECK_1_LUT_ST BIT(2) /* lut_st field */ +#define STATS_DISABLE_CHECK_1_CBUF_FIFO BIT(1) /* cbuf_fifo field */ +#define STATS_DISABLE_CHECK_1_TIMER_SRAM BIT(0) /* timer_sram field */ + +/* STATS_FEATURES (features register) register fields */ +#define STATS_FEATURES_VERSION GENMASK(31, 30) /* version field */ +#define STATS_FEATURES_SYN_LOGGED BIT(9) /* syn_logged field */ +#define STATS_FEATURES_WDTH GENMASK(8, 4) /* wdth field */ +#define STATS_FEATURES_GENERATOR BIT(3) /* generator field */ +#define STATS_FEATURES_CHECKER BIT(2) /* checker field */ +#define STATS_FEATURES_CORRECTABLE BIT(1) /* correctable field */ +#define STATS_FEATURES_ADR_LOGGED BIT(0) /* adr_logged field */ + +/* STATS_LOG_ADDRESS1 (log_address1 register) register fields */ +#define STATS_LOG_ADDRESS1_VALUE GENMASK(9, 0) /* value field */ + +/* STATS_LOG_ADDRESS2 (log_address2 register) register fields */ +#define STATS_LOG_ADDRESS2_VALUE GENMASK(9, 0) /* value field */ + +/* STATS_WIDE_REG (wide_reg register) register fields */ +#define STATS_WIDE_REG_VALUE GENMASK(95, 0) /* value field */ + +/* RDR_REORDER_WINDOW (reorder_window register) register fields */ +#define RDR_REORDER_WINDOW_WS_ENABLE BIT(31) /* ws_enable field */ +#define RDR_REORDER_WINDOW_SET_BACK GENMASK(26, 16) /* set_back field */ +#define RDR_REORDER_WINDOW_SIZE GENMASK(10, 0) /* size field */ + +/* RDR_STREAM_RECONF (stream_reconf register) register fields */ +#define RDR_STREAM_RECONF_BUSY BIT(16) /* busy field */ +#define RDR_STREAM_RECONF_STREAM GENMASK(9, 0) /* stream field */ + +/* RDR_CP_FP_WR_BUFFER_0 (buffer register) register fields */ +#define RDR_CP_FP_WR_BUFFER_0_ADDR0 GENMASK(26, 16) /* addr0 field */ +#define RDR_CP_FP_WR_BUFFER_0_ADDR1 GENMASK(10, 0) /* addr1 field */ + +/* RDR_CP_FP_WR_BUFFER_1 (buffer register) register fields */ +#define RDR_CP_FP_WR_BUFFER_1_ADDR0 GENMASK(26, 16) /* addr0 field */ +#define RDR_CP_FP_WR_BUFFER_1_ADDR1 GENMASK(10, 0) /* addr1 field */ + +/* RDR_CP_FP_WR_BUFFER_2 (buffer register) register fields */ +#define RDR_CP_FP_WR_BUFFER_2_ADDR0 GENMASK(26, 16) /* addr0 field */ +#define RDR_CP_FP_WR_BUFFER_2_ADDR1 GENMASK(10, 0) /* addr1 field */ + +/* RDR_CP_FP_WR_BUFFER_3 (buffer register) register fields */ +#define RDR_CP_FP_WR_BUFFER_3_ADDR0 GENMASK(26, 16) /* addr0 field */ +#define RDR_CP_FP_WR_BUFFER_3_ADDR1 GENMASK(10, 0) /* addr1 field */ + +/* RDR_ROLL32_COUNTER_REG (roll32_counter_reg register) register fields */ +#define RDR_ROLL32_COUNTER_REG_COUNT GENMASK(3, 0) /* count field */ + +/* RDR_SAT32_COUNTER_REG (sat32_counter_reg register) register fields */ +#define RDR_SAT32_COUNTER_REG_COUNT GENMASK(3, 0) /* count field */ + +/* RDR_RCNT_SAT_LOG (rcnt_sat_log register) register fields */ +#define RDR_RCNT_SAT_LOG_EN BIT(31) /* en field */ +#define RDR_RCNT_SAT_LOG_SUBCH GENMASK(30, 26) /* subch field */ +#define RDR_RCNT_SAT_LOG_STR GENMASK(25, 16) /* str field */ +#define RDR_RCNT_SAT_LOG_COUNT GENMASK(15, 0) /* count field */ + +/* EXTRA_REG (extra_reg name) register fields */ +#define EXTRA_REG_VALUE GENMASK(31, 0) /* value field */ + +#endif diff --git a/test/basic_tests/rdl_basic_01/golden/output.h b/test/basic_tests/rdl_basic_01/golden/output.h new file mode 100644 index 0000000..600ec2a --- /dev/null +++ b/test/basic_tests/rdl_basic_01/golden/output.h @@ -0,0 +1,110 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_basic_01/test.rdl +// Parms: ./rdl_basic_01/test.parms +// Date: Thu Jul 20 13:46:40 EDT 2023 +// + +#ifndef __SIMPLE1_REGISTER_MAP__ +#define __SIMPLE1_REGISTER_MAP__ + +#include + +/* SIMPLE1_REGISTERS memory map */ +enum SIMPLE1_REGS { + STATS_DISABLE_CHECK_0 = 0x1000, + STATS_DISABLE_CHECK_1 = 0x1080, + STATS_FEATURES = 0x1100, + STATS_LOG_ADDRESS1 = 0x1104, + STATS_LOG_ADDRESS2 = 0x1110, + STATS_WIDE_REG = 0x1120, + RDR_REORDER_WINDOW = 0x4000, + RDR_STREAM_RECONF = 0x4004, + RDR_CP_FP_WR_BUFFER_0 = 0x61c0, + RDR_CP_FP_WR_BUFFER_1 = 0x61c4, + RDR_CP_FP_WR_BUFFER_2 = 0x61c8, + RDR_CP_FP_WR_BUFFER_3 = 0x61cc, + RDR_ROLL32_COUNTER_REG = 0x61d0, + RDR_SAT32_COUNTER_REG = 0x61d4, + RDR_RCNT_SAT_LOG = 0x61d8, + EXTRA_REG = 0x61dc +}; + +/* STATS_DISABLE_CHECK_0 register fields */ +#define STATS_DISABLE_CHECK_0_TIMER_SRAM BIT(0) +#define STATS_DISABLE_CHECK_0_CBUF_FIFO BIT(1) +#define STATS_DISABLE_CHECK_0_LUT_ST BIT(2) +#define STATS_DISABLE_CHECK_0_L0_B0 BIT(3) +#define STATS_DISABLE_CHECK_0_L0_B1 BIT(4) +#define STATS_DISABLE_CHECK_0_L0_B2 BIT(5) +#define STATS_DISABLE_CHECK_0_L0_B3 BIT(6) + +/* STATS_DISABLE_CHECK_1 register fields */ +#define STATS_DISABLE_CHECK_1_TIMER_SRAM BIT(0) +#define STATS_DISABLE_CHECK_1_CBUF_FIFO BIT(1) +#define STATS_DISABLE_CHECK_1_LUT_ST BIT(2) +#define STATS_DISABLE_CHECK_1_L0_B0 BIT(3) +#define STATS_DISABLE_CHECK_1_L0_B1 BIT(4) +#define STATS_DISABLE_CHECK_1_L0_B2 BIT(5) +#define STATS_DISABLE_CHECK_1_L0_B3 BIT(6) + +/* STATS_FEATURES register fields */ +#define STATS_FEATURES_VERSION GENMASK(31, 30) +#define STATS_FEATURES_DEFAULT_RST_FLD GENMASK(17, 16) +#define STATS_FEATURES_ALT_RST_FLD GENMASK(15, 14) +#define STATS_FEATURES_SYN_LOGGED BIT(9) +#define STATS_FEATURES_WDTH GENMASK(8, 4) +#define STATS_FEATURES_GENERATOR BIT(3) +#define STATS_FEATURES_CHECKER BIT(2) +#define STATS_FEATURES_CORRECTABLE BIT(1) +#define STATS_FEATURES_ADR_LOGGED BIT(0) + +/* STATS_LOG_ADDRESS1 register fields */ +#define STATS_LOG_ADDRESS1_VALUE GENMASK(9, 0) + +/* STATS_LOG_ADDRESS2 register fields */ +#define STATS_LOG_ADDRESS2_VALUE GENMASK(9, 0) + +/* STATS_WIDE_REG register fields */ +#define STATS_WIDE_REG_VALUE GENMASK(95, 0) + +/* RDR_REORDER_WINDOW register fields */ +#define RDR_REORDER_WINDOW_WS_ENABLE BIT(31) +#define RDR_REORDER_WINDOW_SET_BACK GENMASK(26, 16) +#define RDR_REORDER_WINDOW_SIZE GENMASK(10, 0) + +/* RDR_STREAM_RECONF register fields */ +#define RDR_STREAM_RECONF_BUSY BIT(16) +#define RDR_STREAM_RECONF_STREAM GENMASK(9, 0) + +/* RDR_CP_FP_WR_BUFFER_0 register fields */ +#define RDR_CP_FP_WR_BUFFER_0_ADDR0 GENMASK(26, 16) +#define RDR_CP_FP_WR_BUFFER_0_ADDR1 GENMASK(10, 0) + +/* RDR_CP_FP_WR_BUFFER_1 register fields */ +#define RDR_CP_FP_WR_BUFFER_1_ADDR0 GENMASK(26, 16) +#define RDR_CP_FP_WR_BUFFER_1_ADDR1 GENMASK(10, 0) + +/* RDR_CP_FP_WR_BUFFER_2 register fields */ +#define RDR_CP_FP_WR_BUFFER_2_ADDR0 GENMASK(26, 16) +#define RDR_CP_FP_WR_BUFFER_2_ADDR1 GENMASK(10, 0) + +/* RDR_CP_FP_WR_BUFFER_3 register fields */ +#define RDR_CP_FP_WR_BUFFER_3_ADDR0 GENMASK(26, 16) +#define RDR_CP_FP_WR_BUFFER_3_ADDR1 GENMASK(10, 0) + +/* RDR_ROLL32_COUNTER_REG register fields */ +#define RDR_ROLL32_COUNTER_REG_COUNT GENMASK(3, 0) + +/* RDR_SAT32_COUNTER_REG register fields */ +#define RDR_SAT32_COUNTER_REG_COUNT GENMASK(3, 0) + +/* RDR_RCNT_SAT_LOG register fields */ +#define RDR_RCNT_SAT_LOG_EN BIT(31) +#define RDR_RCNT_SAT_LOG_SUBCH GENMASK(30, 26) +#define RDR_RCNT_SAT_LOG_STR GENMASK(25, 16) +#define RDR_RCNT_SAT_LOG_COUNT GENMASK(15, 0) + +/* EXTRA_REG (extra_reg name) register fields */ +#define EXTRA_REG_VALUE GENMASK(31, 0) + +#endif diff --git a/test/basic_tests/rdl_c_header/golden/ordt_pio.cpp b/test/basic_tests/rdl_c_header/golden/ordt_pio.cpp new file mode 100644 index 0000000..251727f --- /dev/null +++ b/test/basic_tests/rdl_c_header/golden/ordt_pio.cpp @@ -0,0 +1,286 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:13 EDT 2023 +// + +#include "ordt_pio_common.hpp" +#include "ordt_pio.hpp" + +// ------------------ ordt_addr_elem methods ------------------ + +ordt_addr_elem::ordt_addr_elem(uint64_t _m_startaddress, uint64_t _m_endaddress) + : m_startaddress(_m_startaddress), + m_endaddress(_m_endaddress) { +} + +bool ordt_addr_elem::containsAddress(const uint64_t &addr) { + return ((addr >= m_startaddress) && (addr <= m_endaddress)); +} + +bool ordt_addr_elem::isBelowAddress(const uint64_t &addr) { + return (addr > m_endaddress); +} + +bool ordt_addr_elem::isAboveAddress(const uint64_t &addr) { + return (addr < m_startaddress); +} + +bool ordt_addr_elem::hasStartAddress(const uint64_t &addr) { + return (addr == m_startaddress); +} + +void ordt_addr_elem::update_child_ptrs() { +} + +// ------------------ ordt_regset methods ------------------ + +ordt_addr_elem* ordt_regset::findAddrElem(const uint64_t &addr) { + int lo = 0; + int hi = m_children.size()-1; + int mid = 0; + while (lo <= hi) { + mid = (lo + hi) / 2; + if (m_children[mid]->containsAddress(addr)) { + //outElem = m_children[mid]; + return m_children[mid]; + } + else if (m_children[mid]->isAboveAddress(addr)) + hi = mid - 1; + else + lo = mid + 1; + } + return nullptr; +} + +ordt_regset::ordt_regset(uint64_t _m_startaddress, uint64_t _m_endaddress) + : ordt_addr_elem(_m_startaddress, _m_endaddress) { +} + +int ordt_regset::write(const uint64_t &addr, const ordt_data &wdata) { + if (this->containsAddress(addr)) { + childElem = this->findAddrElem(addr); + if (childElem != nullptr) { return childElem->write(addr, wdata); } + } + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> write to invalid address " << addr << " in regset\n"; + #endif + return 8; +} + +int ordt_regset::read(const uint64_t &addr, ordt_data &rdata) { + if (this->containsAddress(addr)) { + childElem = this->findAddrElem(addr); + if (childElem != nullptr) { return childElem->read(addr, rdata); } + } + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> read to invalid address " << addr << " in regset\n"; + #endif + rdata.clear(); + return 8; +} + +// ------------------ ordt_reg methods ------------------ + +ordt_reg::ordt_reg(uint64_t _m_startaddress, uint64_t _m_endaddress) + : ordt_addr_elem(_m_startaddress, _m_endaddress) { +} + +ordt_reg::ordt_reg(const ordt_reg &_old) + : ordt_addr_elem(_old), + m_mutex() { +} + +void ordt_reg::write(const ordt_data &wdata) { +} + +int ordt_reg::write(const uint64_t &addr, const ordt_data &wdata) { + return 0; +} + +void ordt_reg::read(ordt_data &rdata) { +} + +int ordt_reg::read(const uint64_t &addr, ordt_data &rdata) { + return 0; +} + +// ------------------ ordt_rg_r0 methods ------------------ + +ordt_rg_r0::ordt_rg_r0(uint64_t _m_startaddress, uint64_t _m_endaddress) + : ordt_reg(_m_startaddress, _m_endaddress), + f0(0, 8, 0x2, r_std, w_std), + f1(8, 8, 0x4, r_std, w_std), + f2(16, 16, 0xa0b, r_std, w_std) { +} + +int ordt_rg_r0::write(const uint64_t &addr, const ordt_data &wdata) { + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> write of reg ordt_rg_r0 at addr="<< addr << ", data=" << wdata.to_string() << "\n"; + #endif + if (this->hasStartAddress(addr)) { + this->write(wdata); + return 0; + } + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> write to invalid address " << addr << " in reg ordt_rg_r0\n"; + #endif + return 8; +} + +void ordt_rg_r0::write(const ordt_data &wdata) { + std::lock_guard m_guard(m_mutex); + f0.write(wdata); + f1.write(wdata); + f2.write(wdata); +} + +int ordt_rg_r0::read(const uint64_t &addr, ordt_data &rdata) { + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> read of reg ordt_rg_r0 at addr="<< addr << "\n"; + #endif + if (this->hasStartAddress(addr)) { + this->read(rdata); + return 0; + } + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> read to invalid address " << addr << " in reg ordt_rg_r0\n"; + #endif + rdata.clear(); + return 8; +} + +void ordt_rg_r0::read(ordt_data &rdata) { + rdata.clear(); + for (uint64_t widx=0; widx<((m_endaddress - m_startaddress + 1)/4); widx++) rdata.push_back(0); + f0.read(rdata); + f1.read(rdata); + f2.read(rdata); +} + +// ------------------ ordt_rg_r1 methods ------------------ + +ordt_rg_r1::ordt_rg_r1(uint64_t _m_startaddress, uint64_t _m_endaddress) + : ordt_reg(_m_startaddress, _m_endaddress), + f0(0, 4, 0x1, r_std, w_std), + f1(4, 4, 0x0, r_std, w_std) { +} + +int ordt_rg_r1::write(const uint64_t &addr, const ordt_data &wdata) { + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> write of reg ordt_rg_r1 at addr="<< addr << ", data=" << wdata.to_string() << "\n"; + #endif + if (this->hasStartAddress(addr)) { + this->write(wdata); + return 0; + } + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> write to invalid address " << addr << " in reg ordt_rg_r1\n"; + #endif + return 8; +} + +void ordt_rg_r1::write(const ordt_data &wdata) { + std::lock_guard m_guard(m_mutex); + f0.write(wdata); + f1.write(wdata); +} + +int ordt_rg_r1::read(const uint64_t &addr, ordt_data &rdata) { + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> read of reg ordt_rg_r1 at addr="<< addr << "\n"; + #endif + if (this->hasStartAddress(addr)) { + this->read(rdata); + return 0; + } + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> read to invalid address " << addr << " in reg ordt_rg_r1\n"; + #endif + rdata.clear(); + return 8; +} + +void ordt_rg_r1::read(ordt_data &rdata) { + rdata.clear(); + for (uint64_t widx=0; widx<((m_endaddress - m_startaddress + 1)/4); widx++) rdata.push_back(0); + f0.read(rdata); + f1.read(rdata); +} + +// ------------------ ordt_rg_r2 methods ------------------ + +ordt_rg_r2::ordt_rg_r2(uint64_t _m_startaddress, uint64_t _m_endaddress) + : ordt_reg(_m_startaddress, _m_endaddress), + f2(0, 2, 0x1, r_std, w_std), + f0(2, 2, 0x1, r_std, w_std), + f3(4, 4, 0x0, r_std, w_std) { +} + +int ordt_rg_r2::write(const uint64_t &addr, const ordt_data &wdata) { + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> write of reg ordt_rg_r2 at addr="<< addr << ", data=" << wdata.to_string() << "\n"; + #endif + if (this->hasStartAddress(addr)) { + this->write(wdata); + return 0; + } + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> write to invalid address " << addr << " in reg ordt_rg_r2\n"; + #endif + return 8; +} + +void ordt_rg_r2::write(const ordt_data &wdata) { + std::lock_guard m_guard(m_mutex); + f2.write(wdata); + f0.write(wdata); + f3.write(wdata); +} + +int ordt_rg_r2::read(const uint64_t &addr, ordt_data &rdata) { + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> read of reg ordt_rg_r2 at addr="<< addr << "\n"; + #endif + if (this->hasStartAddress(addr)) { + this->read(rdata); + return 0; + } + #ifdef ORDT_PIO_VERBOSE + std::cout << "--> read to invalid address " << addr << " in reg ordt_rg_r2\n"; + #endif + rdata.clear(); + return 8; +} + +void ordt_rg_r2::read(ordt_data &rdata) { + rdata.clear(); + for (uint64_t widx=0; widx<((m_endaddress - m_startaddress + 1)/4); widx++) rdata.push_back(0); + f2.read(rdata); + f0.read(rdata); + f3.read(rdata); +} + +// ------------------ ordt_root methods ------------------ + +ordt_root::ordt_root() + : ordt_root(0x0, 0xb) { +} + +ordt_root::ordt_root(uint64_t _m_startaddress, uint64_t _m_endaddress) + : ordt_regset(_m_startaddress, _m_endaddress), + r0(_m_startaddress + 0x0, _m_startaddress + 0x3), + r1(_m_startaddress + 0x4, _m_startaddress + 0x7), + r2(_m_startaddress + 0x8, _m_startaddress + 0xb) { + m_children.push_back(&r0); + m_children.push_back(&r1); + m_children.push_back(&r2); +} + +void ordt_root::update_child_ptrs() { + m_children.clear(); + m_children.push_back(&r0); + m_children.push_back(&r1); + m_children.push_back(&r2); +} + diff --git a/test/basic_tests/rdl_c_header/golden/ordt_pio.hpp b/test/basic_tests/rdl_c_header/golden/ordt_pio.hpp new file mode 100644 index 0000000..70b6a06 --- /dev/null +++ b/test/basic_tests/rdl_c_header/golden/ordt_pio.hpp @@ -0,0 +1,209 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:13 EDT 2023 +// + +#ifndef __ORDT_PIO_HPP_INCLUDED__ +#define __ORDT_PIO_HPP_INCLUDED__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define quote(x) #x + +enum ordt_read_mode_t : uint8_t {r_none, r_std, r_clr}; +enum ordt_write_mode_t : uint8_t {w_none, w_std, w_1clr, w_1set}; +class ordt_addr_elem { + protected: + uint64_t m_startaddress; + uint64_t m_endaddress; + public: + ordt_addr_elem(uint64_t _m_startaddress, uint64_t _m_endaddress); + virtual int write(const uint64_t &addr, const ordt_data &wdata) = 0; + virtual int read(const uint64_t &addr, ordt_data &rdata) = 0; + bool containsAddress(const uint64_t &addr); + bool isBelowAddress(const uint64_t &addr); + bool isAboveAddress(const uint64_t &addr); + bool hasStartAddress(const uint64_t &addr); + virtual void update_child_ptrs(); +}; + +class ordt_regset : public ordt_addr_elem { + private: + ordt_addr_elem* childElem; + ordt_addr_elem* findAddrElem(const uint64_t &addr); + protected: + std::vector m_children; + public: + ordt_regset(uint64_t _m_startaddress, uint64_t _m_endaddress); + virtual int write(const uint64_t &addr, const ordt_data &wdata); + virtual int read(const uint64_t &addr, ordt_data &rdata); +}; + + +template +class ordt_addr_elem_array : public std::vector, public ordt_addr_elem { + protected: + std::vector vec; + uint64_t m_stride; + public: + ordt_addr_elem_array(uint64_t _m_startaddress, uint64_t _m_endaddress, int _reps, uint64_t _m_stride); + virtual int write(const uint64_t &addr, const ordt_data &wdata); + virtual int read(const uint64_t &addr, ordt_data &rdata); +}; + +template +ordt_addr_elem_array::ordt_addr_elem_array(uint64_t _m_startaddress, uint64_t _m_endaddress, int _reps, uint64_t _m_stride) + : ordt_addr_elem(_m_startaddress, _m_endaddress + (_m_stride * (_reps - 1))), m_stride(_m_stride) { + this->reserve(_reps); + uint64_t el_startaddress = _m_startaddress; + uint64_t el_endaddress = _m_endaddress; + for(int idx=0; idx<_reps; idx++) { + std::unique_ptr new_elem(new T(el_startaddress, el_endaddress)); + this->push_back(*new_elem); + this->back().update_child_ptrs(); + el_startaddress += _m_stride; + el_endaddress += _m_stride; + } +} + +template +int ordt_addr_elem_array::write(const uint64_t &addr, const ordt_data &wdata) { + if (this->containsAddress(addr)) { + uint64_t idx = (addr - m_startaddress) / m_stride; + if (idx < this->size()) return this->at(idx).write(addr, wdata); + } +#ifdef ORDT_PIO_VERBOSE + std::cout << "--> write to invalid address " << addr << " in arrayed regset\n"; +#endif + return 8; +} + +template +int ordt_addr_elem_array::read(const uint64_t &addr, ordt_data &rdata) { + if (this->containsAddress(addr)) { + uint64_t idx = (addr - m_startaddress) / m_stride; + if (idx < this->size()) return this->at(idx).read(addr, rdata); + } +#ifdef ORDT_PIO_VERBOSE + std::cout << "--> read to invalid address " << addr << " in arrayed regset\n"; +#endif + rdata.clear(); + return 8; +} + +class ordt_reg : public ordt_addr_elem { + public: + std::mutex m_mutex; + ordt_reg(uint64_t _m_startaddress, uint64_t _m_endaddress); + ordt_reg(const ordt_reg &_old); + virtual void write(const ordt_data &wdata); + virtual int write(const uint64_t &addr, const ordt_data &wdata); + virtual void read(ordt_data &rdata); + virtual int read(const uint64_t &addr, ordt_data &rdata); +}; + + +template +class ordt_field { + public: + int lobit, size; + T data; + ordt_read_mode_t r_mode; + ordt_write_mode_t w_mode; + ordt_field(int _lobit, int _size, int _vsize, uint32_t _data, ordt_read_mode_t _r_mode, ordt_write_mode_t _w_mode); + ordt_field(int _lobit, int _size, T _init_data, ordt_read_mode_t _r_mode, ordt_write_mode_t _w_mode); + void write(const ordt_data &wdata); + void read(ordt_data &rdata); + void clear(); +}; + +template +ordt_field::ordt_field(int _lobit, int _size, int _vsize, uint32_t _data, ordt_read_mode_t _r_mode, ordt_write_mode_t _w_mode) + : lobit(_lobit), size(_size), data(_vsize, _data), r_mode(_r_mode), w_mode(_w_mode) { +} + +template +ordt_field::ordt_field(int _lobit, int _size, T _init_data, ordt_read_mode_t _r_mode, ordt_write_mode_t _w_mode) + : lobit(_lobit), size(_size), data(_init_data), r_mode(_r_mode), w_mode(_w_mode) { +} + +template +void ordt_field::write(const ordt_data &wdata) { + if (w_mode == w_std) wdata.get_slice(lobit, size, data); + else if (w_mode == w_1set) { + T mask_data; + wdata.get_slice(lobit, size, mask_data); + data = data | mask_data; + } + else if (w_mode == w_1clr) { + T mask_data; + wdata.get_slice(lobit, size, mask_data); + data = data & ~mask_data; + } +} + +template +void ordt_field::read(ordt_data &rdata) { + rdata.set_slice(lobit, size, data); + if (r_mode == r_clr) clear(); +} + +template +void ordt_field::clear() { + data = 0; +} + +class ordt_rg_r0 : public ordt_reg { + public: + ordt_field f0; + ordt_field f1; + ordt_field f2; + ordt_rg_r0(uint64_t _m_startaddress, uint64_t _m_endaddress); + virtual int write(const uint64_t &addr, const ordt_data &wdata); + virtual void write(const ordt_data &wdata); + virtual int read(const uint64_t &addr, ordt_data &rdata); + virtual void read(ordt_data &rdata); +}; + +class ordt_rg_r1 : public ordt_reg { + public: + ordt_field f0; + ordt_field f1; + ordt_rg_r1(uint64_t _m_startaddress, uint64_t _m_endaddress); + virtual int write(const uint64_t &addr, const ordt_data &wdata); + virtual void write(const ordt_data &wdata); + virtual int read(const uint64_t &addr, ordt_data &rdata); + virtual void read(ordt_data &rdata); +}; + +class ordt_rg_r2 : public ordt_reg { + public: + ordt_field f2; + ordt_field f0; + ordt_field f3; + ordt_rg_r2(uint64_t _m_startaddress, uint64_t _m_endaddress); + virtual int write(const uint64_t &addr, const ordt_data &wdata); + virtual void write(const ordt_data &wdata); + virtual int read(const uint64_t &addr, ordt_data &rdata); + virtual void read(ordt_data &rdata); +}; + +class ordt_root : public ordt_regset { + public: + ordt_rg_r0 r0; + ordt_rg_r1 r1; + ordt_rg_r2 r2; + ordt_root(); + ordt_root(uint64_t _m_startaddress, uint64_t _m_endaddress); + virtual void update_child_ptrs(); +}; + +#endif // __ORDT_PIO_HPP_INCLUDED__ diff --git a/test/basic_tests/rdl_c_header/golden/ordt_pio_common.cpp b/test/basic_tests/rdl_c_header/golden/ordt_pio_common.cpp new file mode 100644 index 0000000..409b620 --- /dev/null +++ b/test/basic_tests/rdl_c_header/golden/ordt_pio_common.cpp @@ -0,0 +1,111 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:14 EDT 2023 +// + +#include "ordt_pio_common.hpp" + +// ------------------ ordt_data methods ------------------ + +ordt_data::ordt_data() + : std::vector() { +} + +ordt_data::ordt_data(int _size, uint32_t _data) + : std::vector(_size, _data) { +} + +ordt_data::ordt_data(const ordt_data& _data) + : std::vector(_data) { +} + +void ordt_data::set_slice(int lobit, int size, const ordt_data& update) { + int data_size = this->size() * 32; + if ((lobit % 32) > 0) { + std::cout << "ERROR set_slice: non 32b aligned slices are not supported" << "\n"; + return; + } + int hibit = lobit + size - 1; + int loword = lobit / 32; + int hiword = hibit / 32; + if (hibit > data_size - 1) { + std::cout << "ERROR set_slice: specified slice is not contained in data" << "\n"; + return; + } + int update_idx=0; + for (int idx=loword; idx < hiword + 1; idx++) { + if (idx == hiword) { + int modsize = hibit - hiword*32 + 1; + uint32_t mask = (modsize == 32)? 0xffffffff : (1 << modsize) - 1; + this->at(idx) = (this->at(idx) & ~mask) ^ (update.at(update_idx) & mask); + } + else this->at(idx) = update.at(update_idx); + update_idx++; + } +} + +void ordt_data::get_slice(int lobit, int size, ordt_data& slice_out) const { + int data_size = this->size() * 32; + if ((lobit % 32) > 0) { + std::cout << "ERROR set_slice: non 32b aligned large fields are not supported" << "\n"; + return; + } + slice_out.clear(); + int hibit = lobit + size - 1; + int loword = lobit / 32; + int hiword = hibit / 32; + if (hibit > data_size - 1) { + std::cout << "ERROR set_slice: specified slice is not contained in data" << "\n"; + return; + } + int out_idx=0; + for (int idx=loword; idx < hiword + 1; idx++) { + if (idx == hiword) { + int modsize = hibit - hiword*32 + 1; + uint32_t mask = (modsize == 32)? 0xffffffff : (1 << modsize) - 1; + slice_out.at(out_idx) = (this->at(idx) & mask); + } + else slice_out.at(out_idx) = this->at(idx); + out_idx++; + } + return; +} + +std::string ordt_data::to_string() const { + std::stringstream ss; + ss << "{" << std::hex << std::showbase; + for (size_t idx=this->size() - 1; idx >= 0; idx--) + ss << " " << this->at(idx); + ss << " }"; + return ss.str(); +} + +ordt_data& ordt_data::operator=(const uint32_t rhs) { + this->assign(this->size(), rhs); + return *this; +} + +ordt_data ordt_data::operator~() { + ordt_data temp; + for (size_t idx=0; idxsize(); idx++) + temp.at(idx) = ~ this->at(idx); + return temp; +} + +ordt_data ordt_data::operator&(const ordt_data& rhs) { + ordt_data temp; + for (size_t idx=0; idxsize(); idx++) + if (idx < rhs.size()) temp.at(idx) = this->at(idx) & rhs.at(idx); + else temp.at(idx) = 0; + return temp; +} + +ordt_data ordt_data::operator|(const ordt_data& rhs) { + ordt_data temp; + for (size_t idx=0; idxsize(); idx++) + if (idx < rhs.size()) temp.at(idx) = this->at(idx) | rhs.at(idx); + else temp.at(idx) = this->at(idx); + return temp; +} + diff --git a/test/basic_tests/rdl_c_header/golden/ordt_pio_common.hpp b/test/basic_tests/rdl_c_header/golden/ordt_pio_common.hpp new file mode 100644 index 0000000..9c1a500 --- /dev/null +++ b/test/basic_tests/rdl_c_header/golden/ordt_pio_common.hpp @@ -0,0 +1,95 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:14 EDT 2023 +// + +#ifndef __ORDT_PIO_COMMON_HPP_INCLUDED__ +#define __ORDT_PIO_COMMON_HPP_INCLUDED__ + +#include +#include +#include +#include +#include +#include +#include +#define quote(x) #x + +class ordt_data : public std::vector { + public: + ordt_data(); + ordt_data(int _size, uint32_t _data); + ordt_data(const ordt_data& _data); + void set_slice(int lobit, int size, const ordt_data& update); + template + void set_slice(int lobit, int size, const T& update); + void get_slice(int lobit, int size, ordt_data& slice_out) const; + template + void get_slice(int lobit, int size, T& slice_out) const; + std::string to_string() const; + ordt_data& operator=(const uint32_t rhs); + ordt_data operator~(); + ordt_data operator&(const ordt_data& rhs); + ordt_data operator|(const ordt_data& rhs); +}; + +// ------------------ ordt_data methods ------------------ + +template +void ordt_data::set_slice(int lobit, int size, const T& update) { + int data_size = this->size() * 32; + if (sizeof(T) > 8) { + std::cout << "ERROR set_slice: size of update type is greater than 64b" << "\n"; + return; + } + int hibit = lobit + size - 1; + int loword = lobit / 32; + int hiword = hibit / 32; + if (hibit > data_size - 1) { + std::cout << "ERROR set_slice: specified slice is not contained in data" << "\n"; + return; + } + int update_rshift=0; + for (int idx=loword; idx < hiword + 1; idx++) { + int offset=idx*32; + int lo_modbit = std::max(0, lobit - offset); + int hi_modbit = std::min(31, hibit - offset); + int modsize = hi_modbit - lo_modbit + 1; + uint32_t mask = (modsize == 32)? 0xffffffff : (1 << modsize) - 1; + uint32_t shifted_mask = mask << lo_modbit; + this->at(idx) = (this->at(idx) & ~shifted_mask) ^ (((update >> update_rshift) & mask) << lo_modbit); + update_rshift += modsize; + } +} + +template +void ordt_data::get_slice(int lobit, int size, T& slice_out) const { + int data_size = this->size() * 32; + slice_out = 0; + if (sizeof(T) > 8) { + std::cout << "ERROR get_slice: size of return type is greater than 64b" << "\n"; + return; + } + int hibit = lobit + size - 1; + int loword = lobit / 32; + int hiword = hibit / 32; + if (hibit > data_size - 1) { + std::cout << "ERROR set_slice: specified slice is not contained in data" << "\n"; + return; + } + int ret_lshift=0; + for (int idx=loword; idx < hiword + 1; idx++) { + int offset=idx*32; + int lo_modbit = std::max(0, lobit - offset); + int hi_modbit = std::min(31, hibit - offset); + int modsize = hi_modbit - lo_modbit + 1; + uint32_t mask = (modsize == 32)? 0xffffffff : (1 << modsize) - 1; + uint32_t shifted_mask = mask << lo_modbit; + slice_out |= ((this->at(idx) & shifted_mask) >> lo_modbit) << ret_lshift; + ret_lshift += modsize; + } + return; +} + +#endif // __ORDT_PIO_COMMON_HPP_INCLUDED__ diff --git a/test/basic_tests/rdl_c_header/golden/ordt_pio_drv.cpp b/test/basic_tests/rdl_c_header/golden/ordt_pio_drv.cpp new file mode 100644 index 0000000..e1dc07b --- /dev/null +++ b/test/basic_tests/rdl_c_header/golden/ordt_pio_drv.cpp @@ -0,0 +1,204 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:14 EDT 2023 +// + +#include "ordt_pio_common.hpp" +#include "ordt_pio_drv.hpp" + +// ------------------ ordt_drv_path_element methods ------------------ + +ordt_drv_path_element::ordt_drv_path_element(std::string _m_name, int _m_idx) + : m_name(_m_name), + m_idx(_m_idx) { +} + +// ------------------ ordt_drv_field methods ------------------ + +ordt_drv_field::ordt_drv_field(std::string _m_name, int _m_loidx, int _m_width, bool _m_readable, bool _m_writeable) + : m_name(_m_name), + m_loidx(_m_loidx), + m_width(_m_width), + m_readable(_m_readable), + m_writeable(_m_writeable) { +} + +// ------------------ ordt_drv_element methods ------------------ + +std::list ordt_drv_element::split(const std::string &text, char sep, bool trim_rb) { + std::list tokens; + std::size_t start = 0, end = 0, end_adj = 0; + while ((end = text.find(sep, start)) != std::string::npos) { + if (trim_rb && ((end_adj = text.find(']', start)) != std::string::npos) && (end_adj ordt_drv_element::get_path(const std::string pathstr) { + std::list pathlist; + std::list lst = split(pathstr, '.', true); + for(auto const& str_elem: lst) { + std::list sub_lst = split(str_elem, '[', false); + if (sub_lst.size()==2) { + pathlist.emplace_back(sub_lst.front(), std::stoi(sub_lst.back())); + } + else { + pathlist.emplace_back(sub_lst.front(), 1); + } + } + return pathlist; +} + +ordt_drv_element::ordt_drv_element(std::string _m_name) + : m_name(_m_name) { +} + +int ordt_drv_element::get_address_using_version(const int version, const std::string pathstr, uint64_t &address, std::list &fields) { + std::list path = get_path(pathstr); + if (path.size()>0) return get_address_using_list(version, path, false, address, fields); + #ifdef ORDT_PIO_DRV_VERBOSE + std::cout << "--> invalid path: " << pathstr << "\n"; + #endif + return 4; +} + +std::vector ordt_drv_element::get_tags() { + std::vector tags; + tags.push_back("example_addr_map"); + return tags; +} + +int ordt_drv_element::get_address(const std::string tag, const std::string pathstr, uint64_t &address, std::list &fields) { + int version = get_version(tag); + if (version<0) { + #ifdef ORDT_PIO_DRV_VERBOSE + std::cout << "--> invalid tag: " << tag << "\n"; + #endif + return 2; + } + return get_address_using_version(version, pathstr, address, fields); +} + +// ------------------ ordt_drv_regset_child methods ------------------ + +ordt_drv_regset_child::ordt_drv_regset_child(int _m_map, std::shared_ptr _m_child, int _m_reps, uint64_t _m_offset, uint64_t _m_stride) + : m_map(_m_map), + m_child(_m_child), + m_reps(_m_reps), + m_offset(_m_offset), + m_stride(_m_stride) { +} + +// ------------------ ordt_drv_regset methods ------------------ + +ordt_drv_regset::ordt_drv_regset(std::string _m_name) + : ordt_drv_element(_m_name), + m_children() { +} + +int ordt_drv_regset::get_address_using_list(const int version, std::list &path, const bool bypass_names, uint64_t &address, std::list &fields) { + if (path.empty()) + return 8; + ordt_drv_path_element pelem = path.front(); + if (!bypass_names) { + path.pop_front(); + if (path.empty()) + return 0; + pelem = path.front(); + } + for (auto const &child: m_children) { + if (((1<m_name))) { + address += child.m_offset; + if (child.m_reps>1) address += (child.m_stride*pelem.m_idx); + return child.m_child->get_address_using_list(version, path, false, address, fields); + } + } + #ifdef ORDT_PIO_DRV_VERBOSE + std::cout << "--> unable to find child " << pelem.m_name << " in regset " << m_name << "\n"; + #endif + return 8; +} + +void ordt_drv_regset::add_child(int _m_map, std::shared_ptr _m_child, int _m_reps, uint64_t _m_offset, uint64_t _m_stride) { + ordt_drv_regset_child new_child(_m_map, _m_child, _m_reps, _m_offset, _m_stride); + m_children.push_back(new_child); +} + +// ------------------ ordt_drv_reg methods ------------------ + +ordt_drv_reg::ordt_drv_reg(std::string _m_name) + : ordt_drv_element(_m_name), + m_fields() { +} + +int ordt_drv_reg::get_address_using_list(const int version, std::list &path, const bool bypass_names, uint64_t &address, std::list &fields) { + if (path.empty()) + return 8; + path.pop_front(); + if (path.empty()) { + fields = m_fields; + return 0; + } + #ifdef ORDT_PIO_DRV_VERBOSE + ordt_drv_path_element pelem = path.front(); + std::cout << "--> invalid child " << pelem.m_name << " specified in reg " << m_name << "\n"; + #endif + return 8; +} + +void ordt_drv_reg::add_field(std::string _m_name, int _m_loidx, int _width, bool _m_readable, bool _m_writeable) { + ordt_drv_field new_field(_m_name, _m_loidx, _width, _m_readable, _m_writeable); + m_fields.push_back(new_field); +} + +// ------------------ ordt_drv_root methods ------------------ + +ordt_drv_root::ordt_drv_root() + : ordt_drv_regset("root") { + build(); +} + +void ordt_drv_root::build() { + std::shared_ptr r0_1 = std::make_shared("r0"); + r0_1->add_field("f0", 0, 8, true, true); + r0_1->add_field("f1", 8, 8, true, true); + r0_1->add_field("f2", 16, 16, true, true); + std::shared_ptr r1_2 = std::make_shared("r1"); + r1_2->add_field("f0", 0, 4, true, true); + r1_2->add_field("f1", 4, 4, true, true); + std::shared_ptr r2_3 = std::make_shared("r2"); + r2_3->add_field("f2", 0, 2, true, true); + r2_3->add_field("f0", 2, 2, true, true); + r2_3->add_field("f3", 4, 4, true, true); + std::shared_ptr example_addr_map_0 = std::make_shared("example_addr_map"); + example_addr_map_0->add_child(1, r0_1, 1, 0, 4); + example_addr_map_0->add_child(1, r1_2, 1, 4, 4); + example_addr_map_0->add_child(1, r2_3, 1, 8, 4); + add_child(1, example_addr_map_0, 1, 0, 0); +} + +int ordt_drv_root::get_address_using_version(const int version, const std::string pathstr, uint64_t &address, std::list &fields) { + address=0; + fields.clear(); + std::list path = get_path(pathstr); + if (path.size()>0) return get_address_using_list(version, path, true, address, fields); + #ifdef ORDT_PIO_DRV_VERBOSE + std::cout << "--> invalid path: " << pathstr << "\n"; + #endif + return 4; +} + diff --git a/test/basic_tests/rdl_c_header/golden/ordt_pio_drv.hpp b/test/basic_tests/rdl_c_header/golden/ordt_pio_drv.hpp new file mode 100644 index 0000000..07c9f56 --- /dev/null +++ b/test/basic_tests/rdl_c_header/golden/ordt_pio_drv.hpp @@ -0,0 +1,86 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:14 EDT 2023 +// + +#ifndef __ORDT_PIO_DRV_HPP_INCLUDED__ +#define __ORDT_PIO_DRV_HPP_INCLUDED__ + +#include +#include +#include +#include +#include +#include +#include +#define quote(x) #x + +class ordt_drv_path_element { + public: + std::string m_name; + int m_idx; + ordt_drv_path_element(std::string _m_name, int _m_idx); +}; + +class ordt_drv_field { + public: + std::string m_name; + int m_loidx; + int m_width; + bool m_readable; + bool m_writeable; + ordt_drv_field(std::string _m_name, int _m_loidx, int _m_width, bool _m_readable, bool _m_writeable); +}; + +class ordt_drv_element { + private: + std::list split(const std::string &text, char sep, bool trim_rb); + protected: + int get_version(const std::string tag); + std::list get_path(const std::string pathstr); + public: + std::string m_name; + ordt_drv_element(std::string _m_name); + virtual int get_address_using_list(const int version, std::list &path, const bool bypass_names, uint64_t &address, std::list &fields) = 0; + virtual int get_address_using_version(const int version, const std::string pathstr, uint64_t &address, std::list &fields); + std::vector get_tags(); + int get_address(const std::string tag, const std::string pathstr, uint64_t &address, std::list &fields); +}; + +class ordt_drv_regset_child { + public: + int m_map; + std::shared_ptr m_child; + int m_reps; + uint64_t m_offset; + uint64_t m_stride; + ordt_drv_regset_child(int _m_map, std::shared_ptr _m_child, int _m_reps, uint64_t _m_offset, uint64_t _m_stride); +}; + +class ordt_drv_regset : public ordt_drv_element { + protected: + std::list m_children; + public: + ordt_drv_regset(std::string _m_name); + virtual int get_address_using_list(const int version, std::list &path, const bool bypass_names, uint64_t &address, std::list &fields); + void add_child(int _m_map, std::shared_ptr _m_child, int _m_reps, uint64_t _m_offset, uint64_t _m_stride); +}; + +class ordt_drv_reg : public ordt_drv_element { + protected: + std::list m_fields; + public: + ordt_drv_reg(std::string _m_name); + virtual int get_address_using_list(const int version, std::list &path, const bool bypass_names, uint64_t &address, std::list &fields); + void add_field(std::string _m_name, int _m_loidx, int _width, bool _m_readable, bool _m_writeable); +}; + +class ordt_drv_root : public ordt_drv_regset { + public: + ordt_drv_root(); + void build(); + virtual int get_address_using_version(const int version, const std::string pathstr, uint64_t &address, std::list &fields); +}; + +#endif // __ORDT_PIO_DRV_HPP_INCLUDED__ diff --git a/test/basic_tests/rdl_c_header/golden/output.h b/test/basic_tests/rdl_c_header/golden/output.h index fa458c5..73bbc50 100644 --- a/test/basic_tests/rdl_c_header/golden/output.h +++ b/test/basic_tests/rdl_c_header/golden/output.h @@ -1,14 +1,8 @@ -/////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////// +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 13:46:41 EDT 2023 // -/* This is an automatically generated header file for example_addr_map address map */ -// -/* DO NOT MODIFY THIS FILE! USE 'openrdt' toolchain to modify register map! */ -// -/* Generated on: 2021-10-18 */ -// -/////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////// #ifndef __EXAMPLE_ADDR_MAP_REGISTER_MAP__ #define __EXAMPLE_ADDR_MAP_REGISTER_MAP__ @@ -49,25 +43,26 @@ (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) #endif /* _BITS_H */ + /* EXAMPLE_ADDR_MAP_REGISTERS memory map */ enum EXAMPLE_ADDR_MAP_REGS { - DEVICE_ID = 0x0, - SPI_CONFIG = 0x4, - SPI_STATUS = 0x8, + R0 = 0x0, + R1 = 0x4, + R2 = 0x8 }; -/* DEVICE_ID registers */ -#define FLD_A GENMASK(7, 0) -#define FLD_B GENMASK(15, 8) -#define FLD_C GENMASK(31, 16) +/* R0 (DEVICE_ID) register fields */ +#define R0_F0 GENMASK(7, 0) /* FLD_A */ +#define R0_F1 GENMASK(15, 8) /* FLD_B */ +#define R0_F2 GENMASK(31, 16) /* FLD_C */ -/* SPI_CONFIG registers */ -#define REV_MINOR GENMASK(3, 0) -#define REV_MAJOR GENMASK(7, 4) +/* R1 (SPI_CONFIG) register fields */ +#define R1_F0 GENMASK(3, 0) /* REV_MINOR */ +#define R1_F1 GENMASK(7, 4) /* REV_MAJOR */ -/* SPI_STATUS registers */ -#define MASTER GENMASK(3, 2) -#define MASTER1 GENMASK(1, 0) -#define TRANSFER GENMASK(7, 4) +/* R2 (SPI_STATUS) register fields */ +#define R2_F0 GENMASK(3, 2) /* MASTER */ +#define R2_F2 GENMASK(1, 0) /* MASTER1 */ +#define R2_F3 GENMASK(7, 4) /* TRANSFER */ #endif diff --git a/test/basic_tests/rdl_c_header/golden/output.js b/test/basic_tests/rdl_c_header/golden/output.js index 52a07ae..0ba9ffd 100644 --- a/test/basic_tests/rdl_c_header/golden/output.js +++ b/test/basic_tests/rdl_c_header/golden/output.js @@ -1,7 +1,7 @@ -/* Ordt 190715.01 autogenerated file - * Input: ./rdl_latex/test.rdl - * Parms: ./rdl_latex/test.parms - * Date: Wed Sep 15 10:17:15 EDT 2021 +/* Ordt 230719.01 autogenerated file + * Input: ./rdl_c_header/test.rdl + * Parms: ./rdl_c_header/test.parms + * Date: Thu Jul 20 12:53:13 EDT 2023 */ register_set example_addr_map "Registers for example_addr_map" { @@ -37,7 +37,7 @@ register_set example_addr_map "Registers for example_addr_map" { }; }; - register r1 "REVISION_ID" { + register r1 "SPI_CONFIG" { address = 0x4; category = { DYNAMIC_CONFIG }; description = "{ @@ -60,6 +60,36 @@ register_set example_addr_map "Registers for example_addr_map" { }; }; - register_set_size = 0x8; + register r2 "SPI_STATUS" { + address = 0x8; + category = { DYNAMIC_CONFIG }; + description = "{ + Register with revision number + }"; + nop[24]; + integer f3[4] "TRANSFER" param { + description = "{ + transferring + }"; + access_mode = READ_WRITE; + reset = 0x0; + }; + integer f0[2] "MASTER" param { + description = "{ + master enable + }"; + access_mode = READ_WRITE; + reset = 0x1; + }; + integer f2[2] "MASTER1" param { + description = "{ + master enable + }"; + access_mode = READ_WRITE; + reset = 0x1; + }; + }; + + register_set_size = 0xc; }; diff --git a/test/basic_tests/rdl_c_header/golden/output.py b/test/basic_tests/rdl_c_header/golden/output.py new file mode 100644 index 0000000..d53ad41 --- /dev/null +++ b/test/basic_tests/rdl_c_header/golden/output.py @@ -0,0 +1,294 @@ +# Ordt 230719.01 autogenerated file +# Input: ./rdl_c_header/test.rdl +# Parms: ./rdl_c_header/test.parms +# Date: Thu Jul 20 12:53:14 EDT 2023 +# + + +from enum import Enum, auto + +class ordt_drv_error(Enum): + BAD_TAG = auto() + BAD_PATH = auto() + BAD_ADDRESS = auto() + +class ordt_drv_return_type(Enum): + REG = auto() + REGSET = auto() + FIELD = auto() + +class ordt_drv_path_element: + + def __init__(self, name_str): + sub_lst = name_str.split('[') + if len(sub_lst)==2: + self.name = sub_lst[0] + self.idx = sub_lst[1].rstrip(']') + else: + self.name = name_str + self.idx = 1 + + +class ordt_drv_field: + + def __init__(self, name, loidx, width, readable, writeable, reset): + self.name = name + self.loidx = loidx + self.width = width + self.readable = readable + self.writeable = writeable + self.reset = reset + + +class ordt_drv_element: + ORDT_PIO_DRV_VERBOSE = True + + def __init__(self, name): + self.name = name + + def get_address_using_version(self, version, pathstr, address_in): + path = self.get_pathlist(pathstr) + if path: + return self.get_address_using_list(version, path, False, address_in) + if __class__.ORDT_PIO_DRV_VERBOSE: + print('--> invalid path: ' + pathstr) + return {'error':ordt_drv_error.BAD_PATH} + + def get_path_instance_list_using_version(self, version, pathstr, path_instance_list_in): + path = self.get_pathlist(pathstr) + if path: + return self.get_path_instance_list_using_list(version, path, False, path_instance_list_in) + if __class__.ORDT_PIO_DRV_VERBOSE: + print('--> invalid path: ' + pathstr) + return {'error':ordt_drv_error.BAD_PATH} + + def get_version(self, tag): + if tag == 'example_addr_map': + return 0 + else: + return -1 + + def get_tags(self): + tags = [] + tags.append('example_addr_map') + return tags + + def get_address_using_tag(self, tag, pathstr, address_in): + version = self.get_version(tag) + if version<0: + if __class__.ORDT_PIO_DRV_VERBOSE: + print('--> invalid tag: ' + tag) + return {'error':ordt_drv_error.BAD_TAG} + return self.get_address_using_version(version, pathstr, address_in) + + def get_path_instance_list_using_tag(self, tag, pathstr, path_instance_list_in): + version = self.get_version(tag) + if version<0: + if __class__.ORDT_PIO_DRV_VERBOSE: + print('--> invalid tag: ' + tag) + return {'error':ordt_drv_error.BAD_TAG} + return self.get_path_instance_list_using_version(version, pathstr, path_instance_list_in) + + def get_pathlist(self, pathstr): + pathlist = [] + lst = pathstr.split('.') + for str_elem in lst: + path_elem = ordt_drv_path_element(str_elem) + pathlist.append(path_elem) + return pathlist + + def get_path_using_tag(self, tag, address, path_in): + version = self.get_version(tag) + if version<0: + if __class__.ORDT_PIO_DRV_VERBOSE: + print('--> invalid tag: ' + tag) + return {'error':ordt_drv_error.BAD_TAG} + return self.get_path_using_version(version, address, path_in) + + +class ordt_drv_regset_child: + + def __init__(self, version_map, child, reps, offset, stride): + self.version_map = version_map + self.child = child + self.reps = reps + self.offset = offset + self.stride = stride + + def find_offset(self, address_in): + if not self.stride: + return (0, self.child.name) + if (address_in < self.offset) or (address_in >= self.offset + self.reps*self.stride): + return (0, None) + if self.reps < 2: + return (self.offset, '.' + self.child.name) + index = (address_in - self.offset) // self.stride + return (self.offset + index*self.stride, '.' + self.child.name + '[' + str(index) + ']') + + +class ordt_drv_regset(ordt_drv_element): + + def __init__(self, name): + super().__init__(name) + self.children = [] + + def get_address_using_list(self, version, path, bypass_names, address_in): + if not path: + return {'error':ordt_drv_error.BAD_PATH} + pelem = path[0] + if not bypass_names: + path.pop(0) + if not path: + return {'type':ordt_drv_return_type.REGSET, 'address':address_in, 'children':self.get_child_names(version)} + pelem = path[0] + for child in self.children: + if ((1< 1: + address += child.stride*int(pelem.idx) + return child.child.get_address_using_list(version, path, False, address) + if __class__.ORDT_PIO_DRV_VERBOSE: + print('--> unable to find child ' + pelem.name + ' in regset ' + self.name) + return {'error':ordt_drv_error.BAD_PATH} + + def get_path_instance_list_using_list(self, version, path, bypass_names, path_instance_list_in): + if not path: + return {'error':ordt_drv_error.BAD_PATH} + pelem = path[0] + if not bypass_names: + path.pop(0) + if not path: + return {'type':ordt_drv_return_type.REGSET, 'instances':path_instance_list_in} + pelem = path[0] + for child in self.children: + if ((1< unable to find child ' + pelem.name + ' in regset ' + self.name) + return {'error':ordt_drv_error.BAD_PATH} + + def add_child(self, version_map, child, reps, offset, stride): + new_child = ordt_drv_regset_child(version_map, child, reps, offset, stride) + self.children.append(new_child) + + def get_child_names(self, version): + childnames = [] + for child in self.children: + if (1< invalid child ' + pelem.name + ' specified in reg ' + self.name) + return {'error':ordt_drv_error.BAD_PATH} + + def get_path_instance_list_using_list(self, version, path, bypass_names, path_instance_list_in): + if not path: + return {'error':ordt_drv_error.BAD_PATH} + path.pop(0) + if not path: + return {'type':ordt_drv_return_type.REG, 'instances':path_instance_list_in} + if len(path) == 1: + fname = path[0].name + fld = self.get_field_by_name(fname) + if fld: + path_instance_list = path_instance_list_in.copy() + path_instance_list.append(fld) + return {'type':ordt_drv_return_type.FIELD, 'instances':path_instance_list} + if __class__.ORDT_PIO_DRV_VERBOSE: + pelem = path[0] + print('--> invalid child ' + pelem.name + ' specified in reg ' + self.name) + return {'error':ordt_drv_error.BAD_PATH} + + def get_field_by_name(self, name): + for fld in self.fields: + if fld.name == name: + return fld + + def add_field(self, name, loidx, width, readable, writeable, reset): + new_field = ordt_drv_field(name, loidx, width, readable, writeable, reset) + self.fields.append(new_field) + + def get_path_using_version(self, version, address_in, path_in): + return {'type':ordt_drv_return_type.REG, 'path':path_in} + + +class ordt_drv_root(ordt_drv_regset): + base_address = 0 + + def __init__(self): + super().__init__('root') + self.build() + + def build(self): + r0_5 = ordt_drv_reg('r0', 32) + r0_5.add_field('f0', 0, 8, True, True, 2) + r0_5.add_field('f1', 8, 8, True, True, 4) + r0_5.add_field('f2', 16, 16, True, True, 2571) + r1_6 = ordt_drv_reg('r1', 32) + r1_6.add_field('f0', 0, 4, True, True, 1) + r1_6.add_field('f1', 4, 4, True, True, 0) + r2_7 = ordt_drv_reg('r2', 32) + r2_7.add_field('f2', 0, 2, True, True, 1) + r2_7.add_field('f0', 2, 2, True, True, 1) + r2_7.add_field('f3', 4, 4, True, True, 0) + example_addr_map_4 = ordt_drv_regset('example_addr_map') + example_addr_map_4.add_child(1, r0_5, 1, 0, 4) + example_addr_map_4.add_child(1, r1_6, 1, 4, 4) + example_addr_map_4.add_child(1, r2_7, 1, 8, 4) + self.add_child(1, example_addr_map_4, 1, 0, 0) + + def get_address_using_version(self, version, pathstr, address_in): + path = self.get_pathlist(pathstr) + if path: + return self.get_address_using_list(version, path, True, address_in) + if __class__.ORDT_PIO_DRV_VERBOSE: + print('--> invalid path: ' + pathstr) + return {'error':ordt_drv_error.BAD_PATH} + + def get_path_instance_list_using_version(self, version, pathstr, path_instance_list_in): + path = self.get_pathlist(pathstr) + if path: + return self.get_path_instance_list_using_list(version, path, True, path_instance_list_in) + if __class__.ORDT_PIO_DRV_VERBOSE: + print('--> invalid path: ' + pathstr) + return {'error':ordt_drv_error.BAD_PATH} + + def get_address(self, tag, pathstr): + '''return address given a path string and tag''' + return self.get_address_using_tag(tag, pathstr, __class__.base_address) + + def get_path_instance_list(self, tag, pathstr): + '''return list of model elements given a path string and tag''' + return self.get_path_instance_list_using_tag(tag, pathstr, []) + + def get_path(self, tag, address): + '''return path string given an address and tag''' + return self.get_path_using_tag(tag, address, '') + + diff --git a/test/basic_tests/rdl_c_header/golden/output.reglist b/test/basic_tests/rdl_c_header/golden/output.reglist index 8ff9009..013ed5a 100644 --- a/test/basic_tests/rdl_c_header/golden/output.reglist +++ b/test/basic_tests/rdl_c_header/golden/output.reglist @@ -1,8 +1,9 @@ -// Ordt 190715.01 autogenerated file -// Input: ./rdl_latex/test.rdl -// Parms: ./rdl_latex/test.parms -// Date: Wed Sep 15 10:17:15 EDT 2021 +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:13 EDT 2023 // 0x0 size: 32 fields: 3 bits: 32 r0 0x4 size: 32 fields: 2 bits: 8 r1 +0x8 size: 32 fields: 3 bits: 8 r2 diff --git a/test/basic_tests/rdl_c_header/golden/output.sv b/test/basic_tests/rdl_c_header/golden/output.sv index 09d95c1..e820c0a 100644 --- a/test/basic_tests/rdl_c_header/golden/output.sv +++ b/test/basic_tests/rdl_c_header/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190715.01 autogenerated file -// Input: ./rdl_latex/test.rdl -// Parms: ./rdl_latex/test.parms -// Date: Wed Sep 15 10:17:15 EDT 2021 +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:13 EDT 2023 // // @@ -17,14 +17,21 @@ module example_addr_map_jrdl_logic d2l_r1_w, d2l_r1_we, d2l_r1_re, + d2l_r2_w, + d2l_r2_we, + d2l_r2_re, l2d_r0_r, l2d_r1_r, + l2d_r2_r, l2h_r0_f0_r, l2h_r0_f1_r, l2h_r0_f2_r, l2h_r1_f0_r, - l2h_r1_f1_r ); + l2h_r1_f1_r, + l2h_r2_f0_r, + l2h_r2_f2_r, + l2h_r2_f3_r ); //------- inputs input clk; @@ -35,15 +42,22 @@ module example_addr_map_jrdl_logic input [31:0] d2l_r1_w; input d2l_r1_we; input d2l_r1_re; + input [31:0] d2l_r2_w; + input d2l_r2_we; + input d2l_r2_re; //------- outputs output [31:0] l2d_r0_r; output [31:0] l2d_r1_r; + output [31:0] l2d_r2_r; output [7:0] l2h_r0_f0_r; output [7:0] l2h_r0_f1_r; output [15:0] l2h_r0_f2_r; output [3:0] l2h_r1_f0_r; output [3:0] l2h_r1_f1_r; + output [1:0] l2h_r2_f0_r; + output [1:0] l2h_r2_f2_r; + output [3:0] l2h_r2_f3_r; //------- reg defines @@ -64,7 +78,44 @@ module example_addr_map_jrdl_logic logic [3:0] reg_r1_f1_next; logic [3:0] l2h_r1_f1_r; logic [31:0] l2d_r1_r; + logic [1:0] rg_r2_f0; + logic [1:0] reg_r2_f0_next; + logic [1:0] l2h_r2_f0_r; + logic [1:0] rg_r2_f2; + logic [1:0] reg_r2_f2_next; + logic [1:0] l2h_r2_f2_r; + logic [3:0] rg_r2_f3; + logic [3:0] reg_r2_f3_next; + logic [3:0] l2h_r2_f3_r; + logic [31:0] l2d_r2_r; + + + //------- combinatorial assigns for r2 + always_comb begin + reg_r2_f0_next = rg_r2_f0; + l2h_r2_f0_r = rg_r2_f0; + reg_r2_f2_next = rg_r2_f2; + l2h_r2_f2_r = rg_r2_f2; + reg_r2_f3_next = rg_r2_f3; + l2h_r2_f3_r = rg_r2_f3; + if (d2l_r2_we) reg_r2_f0_next = d2l_r2_w [3:2] ; + if (d2l_r2_we) reg_r2_f2_next = d2l_r2_w [1:0] ; + if (d2l_r2_we) reg_r2_f3_next = d2l_r2_w [7:4] ; + end + //------- reg assigns for r2 + always_ff @ (posedge clk) begin + if (reset) begin + rg_r2_f0 <= #1 2'h1; + rg_r2_f2 <= #1 2'h1; + rg_r2_f3 <= #1 4'h0; + end + else begin + rg_r2_f0 <= #1 reg_r2_f0_next; + rg_r2_f2 <= #1 reg_r2_f2_next; + rg_r2_f3 <= #1 reg_r2_f3_next; + end + end //------- combinatorial assigns for r0 (pio read data) always_comb begin @@ -80,6 +131,14 @@ module example_addr_map_jrdl_logic l2d_r1_r [7:4] = rg_r1_f1; end + //------- combinatorial assigns for r2 (pio read data) + always_comb begin + l2d_r2_r = 32'b0; + l2d_r2_r [3:2] = rg_r2_f0; + l2d_r2_r [1:0] = rg_r2_f2; + l2d_r2_r [7:4] = rg_r2_f3; + end + //------- combinatorial assigns for r0 always_comb begin reg_r0_f0_next = rg_r0_f0; @@ -147,6 +206,7 @@ module example_addr_map_jrdl_decode leaf_dec_wr_width, l2d_r0_r, l2d_r1_r, + l2d_r2_r, dec_leaf_rd_data, dec_leaf_ack, @@ -160,7 +220,10 @@ module example_addr_map_jrdl_decode d2l_r0_re, d2l_r1_w, d2l_r1_we, - d2l_r1_re ); + d2l_r1_re, + d2l_r2_w, + d2l_r2_we, + d2l_r2_re ); //------- inputs input clk; @@ -174,6 +237,7 @@ module example_addr_map_jrdl_decode input [2:0] leaf_dec_wr_width; input [31:0] l2d_r0_r; input [31:0] l2d_r1_r; + input [31:0] l2d_r2_r; //------- outputs output [31:0] dec_leaf_rd_data; @@ -189,11 +253,14 @@ module example_addr_map_jrdl_decode output [31:0] d2l_r1_w; output d2l_r1_we; output d2l_r1_re; + output [31:0] d2l_r2_w; + output d2l_r2_we; + output d2l_r2_re; //------- wire defines logic [31:0] pio_dec_write_data; - logic pio_dec_address; + logic [3:2] pio_dec_address; logic pio_dec_read; logic pio_dec_write; logic [39:0] block_sel_addr; @@ -208,13 +275,16 @@ module example_addr_map_jrdl_decode logic [31:0] d2l_r1_w; logic d2l_r1_we; logic d2l_r1_re; + logic [31:0] d2l_r2_w; + logic d2l_r2_we; + logic d2l_r2_re; logic leaf_dec_valid_hld1; logic leaf_dec_valid_hld1_next; logic leaf_dec_wr_dvld_hld1; logic leaf_dec_wr_dvld_hld1_next; logic pio_write_active; logic pio_read_active; - logic pio_dec_address_d1; + logic [3:2] pio_dec_address_d1; logic [31:0] pio_dec_write_data_d1; logic [31:0] dec_pio_read_data; logic [31:0] dec_pio_read_data_d1; @@ -240,7 +310,7 @@ module example_addr_map_jrdl_decode assign dec_leaf_rd_data = dec_pio_read_data; assign dec_leaf_ack = dec_pio_ack; assign dec_leaf_nack = dec_pio_nack; - assign pio_dec_address = leaf_dec_addr [2] ; + assign pio_dec_address = leaf_dec_addr [3:2] ; assign block_sel_addr = 40'h0; assign block_sel = leaf_dec_block_sel; assign leaf_dec_wr_dvld_active = leaf_dec_wr_dvld | leaf_dec_wr_dvld_hld1; @@ -342,10 +412,13 @@ module example_addr_map_jrdl_decode d2l_r1_w = pio_dec_write_data_d1 [31:0] ; d2l_r1_we = 1'b0; d2l_r1_re = 1'b0; + d2l_r2_w = pio_dec_write_data_d1 [31:0] ; + d2l_r2_we = 1'b0; + d2l_r2_re = 1'b0; casez(pio_dec_address_d1) // Register: r0 Address: 0x0 External: false - 1'b0: + 2'b00: begin d2l_r0_we = pio_write_active & ~dec_pio_ack; d2l_r0_re = pio_read_active & ~dec_pio_ack; @@ -353,13 +426,21 @@ module example_addr_map_jrdl_decode dec_pio_read_data_next [31:0] = l2d_r0_r; end // Register: r1 Address: 0x4 External: false - 1'b1: + 2'b01: begin d2l_r1_we = pio_write_active & ~dec_pio_ack; d2l_r1_re = pio_read_active & ~dec_pio_ack; pio_internal_ack = pio_read_active | pio_write_active; dec_pio_read_data_next [31:0] = l2d_r1_r; end + // Register: r2 Address: 0x8 External: false + 2'b10: + begin + d2l_r2_we = pio_write_active & ~dec_pio_ack; + d2l_r2_re = pio_read_active & ~dec_pio_ack; + pio_internal_ack = pio_read_active | pio_write_active; + dec_pio_read_data_next [31:0] = l2d_r2_r; + end endcase end @@ -385,6 +466,9 @@ module example_addr_map_pio l2h_r0_f2_r, l2h_r1_f0_r, l2h_r1_f1_r, + l2h_r2_f0_r, + l2h_r2_f2_r, + l2h_r2_f3_r, dec_leaf_rd_data, dec_leaf_ack, dec_leaf_nack, @@ -410,6 +494,9 @@ module example_addr_map_pio output [15:0] l2h_r0_f2_r; output [3:0] l2h_r1_f0_r; output [3:0] l2h_r1_f1_r; + output [1:0] l2h_r2_f0_r; + output [1:0] l2h_r2_f2_r; + output [3:0] l2h_r2_f3_r; output [31:0] dec_leaf_rd_data; output dec_leaf_ack; output dec_leaf_nack; @@ -426,8 +513,12 @@ module example_addr_map_pio logic [31:0] d2l_r1_w; logic d2l_r1_we; logic d2l_r1_re; + logic [31:0] d2l_r2_w; + logic d2l_r2_we; + logic d2l_r2_re; logic [31:0] l2d_r0_r; logic [31:0] l2d_r1_r; + logic [31:0] l2d_r2_r; example_addr_map_jrdl_decode pio_decode ( .* ); diff --git a/test/basic_tests/rdl_c_header/golden/output.v b/test/basic_tests/rdl_c_header/golden/output.v index aaebd0a..5ef13bd 100644 --- a/test/basic_tests/rdl_c_header/golden/output.v +++ b/test/basic_tests/rdl_c_header/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190715.01 autogenerated file -// Input: ./rdl_latex/test.rdl -// Parms: ./rdl_latex/test.parms -// Date: Wed Sep 15 10:17:15 EDT 2021 +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:13 EDT 2023 // // @@ -17,14 +17,21 @@ module example_addr_map_jrdl_logic d2l_r1_w, d2l_r1_we, d2l_r1_re, + d2l_r2_w, + d2l_r2_we, + d2l_r2_re, l2d_r0_r, l2d_r1_r, + l2d_r2_r, l2h_r0_f0_r, l2h_r0_f1_r, l2h_r0_f2_r, l2h_r1_f0_r, - l2h_r1_f1_r ); + l2h_r1_f1_r, + l2h_r2_f0_r, + l2h_r2_f2_r, + l2h_r2_f3_r ); //------- inputs input clk; @@ -35,15 +42,22 @@ module example_addr_map_jrdl_logic input [31:0] d2l_r1_w; input d2l_r1_we; input d2l_r1_re; + input [31:0] d2l_r2_w; + input d2l_r2_we; + input d2l_r2_re; //------- outputs output [31:0] l2d_r0_r; output [31:0] l2d_r1_r; + output [31:0] l2d_r2_r; output [7:0] l2h_r0_f0_r; output [7:0] l2h_r0_f1_r; output [15:0] l2h_r0_f2_r; output [3:0] l2h_r1_f0_r; output [3:0] l2h_r1_f1_r; + output [1:0] l2h_r2_f0_r; + output [1:0] l2h_r2_f2_r; + output [3:0] l2h_r2_f3_r; //------- reg defines @@ -64,8 +78,45 @@ module example_addr_map_jrdl_logic reg [3:0] reg_r1_f1_next; reg [3:0] l2h_r1_f1_r; reg [31:0] l2d_r1_r; + reg [1:0] rg_r2_f0; + reg [1:0] reg_r2_f0_next; + reg [1:0] l2h_r2_f0_r; + reg [1:0] rg_r2_f2; + reg [1:0] reg_r2_f2_next; + reg [1:0] l2h_r2_f2_r; + reg [3:0] rg_r2_f3; + reg [3:0] reg_r2_f3_next; + reg [3:0] l2h_r2_f3_r; + reg [31:0] l2d_r2_r; + //------- combinatorial assigns for r2 + always @ (*) begin + reg_r2_f0_next = rg_r2_f0; + l2h_r2_f0_r = rg_r2_f0; + reg_r2_f2_next = rg_r2_f2; + l2h_r2_f2_r = rg_r2_f2; + reg_r2_f3_next = rg_r2_f3; + l2h_r2_f3_r = rg_r2_f3; + if (d2l_r2_we) reg_r2_f0_next = d2l_r2_w [3:2] ; + if (d2l_r2_we) reg_r2_f2_next = d2l_r2_w [1:0] ; + if (d2l_r2_we) reg_r2_f3_next = d2l_r2_w [7:4] ; + end + + //------- reg assigns for r2 + always @ (posedge clk) begin + if (reset) begin + rg_r2_f0 <= #1 2'h1; + rg_r2_f2 <= #1 2'h1; + rg_r2_f3 <= #1 4'h0; + end + else begin + rg_r2_f0 <= #1 reg_r2_f0_next; + rg_r2_f2 <= #1 reg_r2_f2_next; + rg_r2_f3 <= #1 reg_r2_f3_next; + end + end + //------- combinatorial assigns for r0 (pio read data) always @ (*) begin l2d_r0_r [7:0] = rg_r0_f0; @@ -80,6 +131,14 @@ module example_addr_map_jrdl_logic l2d_r1_r [7:4] = rg_r1_f1; end + //------- combinatorial assigns for r2 (pio read data) + always @ (*) begin + l2d_r2_r = 32'b0; + l2d_r2_r [3:2] = rg_r2_f0; + l2d_r2_r [1:0] = rg_r2_f2; + l2d_r2_r [7:4] = rg_r2_f3; + end + //------- combinatorial assigns for r0 always @ (*) begin reg_r0_f0_next = rg_r0_f0; @@ -147,6 +206,7 @@ module example_addr_map_jrdl_decode leaf_dec_wr_width, l2d_r0_r, l2d_r1_r, + l2d_r2_r, dec_leaf_rd_data, dec_leaf_ack, @@ -160,7 +220,10 @@ module example_addr_map_jrdl_decode d2l_r0_re, d2l_r1_w, d2l_r1_we, - d2l_r1_re ); + d2l_r1_re, + d2l_r2_w, + d2l_r2_we, + d2l_r2_re ); //------- inputs input clk; @@ -174,6 +237,7 @@ module example_addr_map_jrdl_decode input [2:0] leaf_dec_wr_width; input [31:0] l2d_r0_r; input [31:0] l2d_r1_r; + input [31:0] l2d_r2_r; //------- outputs output [31:0] dec_leaf_rd_data; @@ -189,11 +253,14 @@ module example_addr_map_jrdl_decode output [31:0] d2l_r1_w; output d2l_r1_we; output d2l_r1_re; + output [31:0] d2l_r2_w; + output d2l_r2_we; + output d2l_r2_re; //------- wire defines wire [31:0] pio_dec_write_data; - wire pio_dec_address; + wire [3:2] pio_dec_address; wire pio_dec_read; wire pio_dec_write; wire [39:0] block_sel_addr; @@ -208,13 +275,16 @@ module example_addr_map_jrdl_decode reg [31:0] d2l_r1_w; reg d2l_r1_we; reg d2l_r1_re; + reg [31:0] d2l_r2_w; + reg d2l_r2_we; + reg d2l_r2_re; reg leaf_dec_valid_hld1; reg leaf_dec_valid_hld1_next; reg leaf_dec_wr_dvld_hld1; reg leaf_dec_wr_dvld_hld1_next; reg pio_write_active; reg pio_read_active; - reg pio_dec_address_d1; + reg [3:2] pio_dec_address_d1; reg [31:0] pio_dec_write_data_d1; reg [31:0] dec_pio_read_data; reg [31:0] dec_pio_read_data_d1; @@ -240,7 +310,7 @@ module example_addr_map_jrdl_decode assign dec_leaf_rd_data = dec_pio_read_data; assign dec_leaf_ack = dec_pio_ack; assign dec_leaf_nack = dec_pio_nack; - assign pio_dec_address = leaf_dec_addr [2] ; + assign pio_dec_address = leaf_dec_addr [3:2] ; assign block_sel_addr = 40'h0; assign block_sel = leaf_dec_block_sel; assign leaf_dec_wr_dvld_active = leaf_dec_wr_dvld | leaf_dec_wr_dvld_hld1; @@ -342,10 +412,13 @@ module example_addr_map_jrdl_decode d2l_r1_w = pio_dec_write_data_d1 [31:0] ; d2l_r1_we = 1'b0; d2l_r1_re = 1'b0; + d2l_r2_w = pio_dec_write_data_d1 [31:0] ; + d2l_r2_we = 1'b0; + d2l_r2_re = 1'b0; casez(pio_dec_address_d1) // Register: r0 Address: 0x0 External: false - 1'b0: + 2'b00: begin d2l_r0_we = pio_write_active & ~dec_pio_ack; d2l_r0_re = pio_read_active & ~dec_pio_ack; @@ -353,13 +426,21 @@ module example_addr_map_jrdl_decode dec_pio_read_data_next [31:0] = l2d_r0_r; end // Register: r1 Address: 0x4 External: false - 1'b1: + 2'b01: begin d2l_r1_we = pio_write_active & ~dec_pio_ack; d2l_r1_re = pio_read_active & ~dec_pio_ack; pio_internal_ack = pio_read_active | pio_write_active; dec_pio_read_data_next [31:0] = l2d_r1_r; end + // Register: r2 Address: 0x8 External: false + 2'b10: + begin + d2l_r2_we = pio_write_active & ~dec_pio_ack; + d2l_r2_re = pio_read_active & ~dec_pio_ack; + pio_internal_ack = pio_read_active | pio_write_active; + dec_pio_read_data_next [31:0] = l2d_r2_r; + end endcase end @@ -385,6 +466,9 @@ module example_addr_map_pio l2h_r0_f2_r, l2h_r1_f0_r, l2h_r1_f1_r, + l2h_r2_f0_r, + l2h_r2_f2_r, + l2h_r2_f3_r, dec_leaf_rd_data, dec_leaf_ack, dec_leaf_nack, @@ -410,6 +494,9 @@ module example_addr_map_pio output [15:0] l2h_r0_f2_r; output [3:0] l2h_r1_f0_r; output [3:0] l2h_r1_f1_r; + output [1:0] l2h_r2_f0_r; + output [1:0] l2h_r2_f2_r; + output [3:0] l2h_r2_f3_r; output [31:0] dec_leaf_rd_data; output dec_leaf_ack; output dec_leaf_nack; @@ -426,8 +513,12 @@ module example_addr_map_pio wire [31:0] d2l_r1_w; wire d2l_r1_we; wire d2l_r1_re; + wire [31:0] d2l_r2_w; + wire d2l_r2_we; + wire d2l_r2_re; wire [31:0] l2d_r0_r; wire [31:0] l2d_r1_r; + wire [31:0] l2d_r2_r; example_addr_map_jrdl_decode pio_decode ( @@ -442,6 +533,7 @@ module example_addr_map_pio .leaf_dec_wr_width(leaf_dec_wr_width), .l2d_r0_r(l2d_r0_r), .l2d_r1_r(l2d_r1_r), + .l2d_r2_r(l2d_r2_r), .dec_leaf_rd_data(dec_leaf_rd_data), .dec_leaf_ack(dec_leaf_ack), .dec_leaf_nack(dec_leaf_nack), @@ -454,7 +546,10 @@ module example_addr_map_pio .d2l_r0_re(d2l_r0_re), .d2l_r1_w(d2l_r1_w), .d2l_r1_we(d2l_r1_we), - .d2l_r1_re(d2l_r1_re) ); + .d2l_r1_re(d2l_r1_re), + .d2l_r2_w(d2l_r2_w), + .d2l_r2_we(d2l_r2_we), + .d2l_r2_re(d2l_r2_re) ); example_addr_map_jrdl_logic pio_logic ( .clk(clk), @@ -465,13 +560,20 @@ module example_addr_map_pio .d2l_r1_w(d2l_r1_w), .d2l_r1_we(d2l_r1_we), .d2l_r1_re(d2l_r1_re), + .d2l_r2_w(d2l_r2_w), + .d2l_r2_we(d2l_r2_we), + .d2l_r2_re(d2l_r2_re), .l2d_r0_r(l2d_r0_r), .l2d_r1_r(l2d_r1_r), + .l2d_r2_r(l2d_r2_r), .l2h_r0_f0_r(l2h_r0_f0_r), .l2h_r0_f1_r(l2h_r0_f1_r), .l2h_r0_f2_r(l2h_r0_f2_r), .l2h_r1_f0_r(l2h_r1_f0_r), - .l2h_r1_f1_r(l2h_r1_f1_r) ); + .l2h_r1_f1_r(l2h_r1_f1_r), + .l2h_r2_f0_r(l2h_r2_f0_r), + .l2h_r2_f2_r(l2h_r2_f2_r), + .l2h_r2_f3_r(l2h_r2_f3_r) ); endmodule diff --git a/test/basic_tests/rdl_c_header/golden/output.xml b/test/basic_tests/rdl_c_header/golden/output.xml index 9c60574..c1cd7f4 100644 --- a/test/basic_tests/rdl_c_header/golden/output.xml +++ b/test/basic_tests/rdl_c_header/golden/output.xml @@ -1,11 +1,11 @@ - - + example_addr_map 0 example_addr_map registers @@ -22,7 +22,7 @@ r - 2 + 0x2 0 8 @@ -34,7 +34,7 @@ r - 4 + 0x4 8 8 @@ -46,7 +46,7 @@ r - a0b + 0xa0b 16 16 @@ -56,7 +56,7 @@ r1 - REVISION_ID + SPI_CONFIG 0x4 32 @@ -67,7 +67,7 @@ r - 1 + 0x1 0 4 @@ -79,7 +79,7 @@ r - 0 + 0x0 4 4 @@ -87,4 +87,49 @@ 2 RW + + r2 + SPI_STATUS + 0x8 + 32 + + + f0 + MASTER + RW + + r + + 0x1 + 2 + 2 + + + + f2 + MASTER1 + RW + + r + + 0x1 + 0 + 2 + + + + f3 + TRANSFER + RW + + r + + 0x0 + 4 + 4 + + + 2 + RW + diff --git a/test/basic_tests/rdl_c_header/golden/uvm_reg_jrdl_pkg.sv b/test/basic_tests/rdl_c_header/golden/uvm_reg_jrdl_pkg.sv index 13fcb7e..fbf3fbd 100644 --- a/test/basic_tests/rdl_c_header/golden/uvm_reg_jrdl_pkg.sv +++ b/test/basic_tests/rdl_c_header/golden/uvm_reg_jrdl_pkg.sv @@ -1,5 +1,5 @@ -// Ordt 190715.01 autogenerated file -// Date: Wed Sep 15 10:17:15 EDT 2021 +// Ordt 230719.01 autogenerated file +// Date: Thu Jul 20 12:53:13 EDT 2023 // diff --git a/test/basic_tests/rdl_c_header/golden/uvmregs.sv b/test/basic_tests/rdl_c_header/golden/uvmregs.sv index cbf95c1..8f91575 100644 --- a/test/basic_tests/rdl_c_header/golden/uvmregs.sv +++ b/test/basic_tests/rdl_c_header/golden/uvmregs.sv @@ -1,7 +1,7 @@ -// Ordt 190715.01 autogenerated file -// Input: ./rdl_latex/test.rdl -// Parms: ./rdl_latex/test.parms -// Date: Wed Sep 15 10:17:15 EDT 2021 +// Ordt 230719.01 autogenerated file +// Input: ./rdl_c_header/test.rdl +// Parms: ./rdl_c_header/test.parms +// Date: Thu Jul 20 12:53:13 EDT 2023 // import uvm_pkg::*; @@ -38,7 +38,7 @@ class reg_example_addr_map_r0 extends uvm_reg_rdl; endclass : reg_example_addr_map_r0 -// REVISION_ID +// SPI_CONFIG class reg_example_addr_map_r1 extends uvm_reg_rdl; string m_rdl_tag; rand uvm_reg_field_rdl f0; @@ -64,10 +64,42 @@ class reg_example_addr_map_r1 extends uvm_reg_rdl; endclass : reg_example_addr_map_r1 +// SPI_STATUS +class reg_example_addr_map_r2 extends uvm_reg_rdl; + string m_rdl_tag; + rand uvm_reg_field_rdl f2; + rand uvm_reg_field_rdl f0; + rand uvm_reg_field_rdl f3; + + function new(string name = "reg_example_addr_map_r2"); + super.new(name, 32, UVM_NO_COVERAGE); + endfunction: new + + virtual function void build(); + string rdl_reg_name; + this.f2 = new("f2"); + this.f2.set_rdl_access_info(1, 1, 1, 0, 0, 0); + this.f2.configure(this, 2, 0, "RW", 0, 2'h1, 1, 1, 0); + this.f0 = new("f0"); + this.f0.set_rdl_access_info(1, 1, 1, 0, 0, 0); + this.f0.configure(this, 2, 2, "RW", 0, 2'h1, 1, 1, 0); + this.f3 = new("f3"); + this.f3.set_rdl_access_info(1, 1, 1, 0, 0, 0); + this.f3.configure(this, 4, 4, "RW", 0, 4'h0, 1, 1, 0); + + rdl_reg_name = get_rdl_name("rg_"); + add_hdl_path_slice({rdl_reg_name, "f2"}, 0, 2); + add_hdl_path_slice({rdl_reg_name, "f0"}, 2, 2); + add_hdl_path_slice({rdl_reg_name, "f3"}, 4, 4); + endfunction: build + +endclass : reg_example_addr_map_r2 + // Base block class block_example_addr_map extends uvm_reg_block_rdl; rand reg_example_addr_map_r0 r0; rand reg_example_addr_map_r1 r1; + rand reg_example_addr_map_r2 r2; function new(string name = "block_example_addr_map"); super.new(name); @@ -89,6 +121,12 @@ class block_example_addr_map extends uvm_reg_block_rdl; this.r1.set_reg_test_info(0, 0, 2); this.r1.build(); this.default_map.add_reg(this.r1, `UVM_REG_ADDR_WIDTH'h4, "RW", 0); + this.r2 = new("r2"); + this.r2.configure(this, null, ""); + this.r2.set_rdl_tag("r2_"); + this.r2.set_reg_test_info(0, 0, 2); + this.r2.build(); + this.default_map.add_reg(this.r2, `UVM_REG_ADDR_WIDTH'h8, "RW", 0); this.add_callbacks(); endfunction: build diff --git a/test/basic_tests/rdl_c_header/golden/vbench.v b/test/basic_tests/rdl_c_header/golden/vbench.v deleted file mode 100644 index 7524a11..0000000 --- a/test/basic_tests/rdl_c_header/golden/vbench.v +++ /dev/null @@ -1,353 +0,0 @@ -// Ordt 190715.01 autogenerated file -// Input: ./rdl_latex/test.rdl -// Parms: ./rdl_latex/test.parms -// Date: Wed Sep 15 10:17:15 EDT 2021 -// - -`timescale 1 ns / 100 ps -// -//---------- module example_addr_map_test_leaf_bfm -// -module example_addr_map_test_leaf_bfm -( - address, - wr_data, - wr_enable, - rd_compare, - rd_data, - trans_type, - size, - leaf_go, - CLK, - dec_leaf_rd_data, - dec_leaf_ack, - dec_leaf_nack, - dec_leaf_accept, - dec_leaf_reject, - dec_leaf_retry_atomic, - dec_leaf_data_width, - - active, - done, - leaf_dec_addr, - leaf_dec_wr_data, - leaf_dec_valid, - leaf_dec_wr_dvld, - leaf_dec_cycle, - leaf_dec_wr_width ); - - //------- inputs - input [39:0] address; - input [31:0] wr_data; - input wr_enable; - input rd_compare; - input [31:0] rd_data; - input [1:0] trans_type; - input [3:0] size; - input leaf_go; - input CLK; - input [31:0] dec_leaf_rd_data; - input dec_leaf_ack; - input dec_leaf_nack; - input dec_leaf_accept; - input dec_leaf_reject; - input dec_leaf_retry_atomic; - input [2:0] dec_leaf_data_width; - - //------- outputs - output active; - output done; - output [39:0] leaf_dec_addr; - output [31:0] leaf_dec_wr_data; - output leaf_dec_valid; - output leaf_dec_wr_dvld; - output [1:0] leaf_dec_cycle; - output [2:0] leaf_dec_wr_width; - - - //------- reg defines - reg active; - reg done; - reg [39:0] leaf_dec_addr; - reg [31:0] leaf_dec_wr_data; - reg leaf_dec_valid; - reg leaf_dec_wr_dvld; - reg [1:0] leaf_dec_cycle; - reg [2:0] leaf_dec_wr_width; - reg [4:0] trans_size; - - initial begin - active = 0; - done = 0; - leaf_dec_addr = 0; - leaf_dec_wr_data = 0; - leaf_dec_valid = 0; - leaf_dec_wr_dvld = 0; - leaf_dec_cycle = 0; - leaf_dec_wr_width = 0; - end - - always @(posedge leaf_go) begin - @(posedge CLK); - #1 active = 1'b1; - leaf_dec_addr = address; - leaf_dec_wr_data = wr_data; - leaf_dec_valid = 1'b1; - leaf_dec_wr_dvld = 1'b0; - leaf_dec_cycle = trans_type; - trans_size = {1'b0, size} + 5'b1; - if (trans_type[1] == 1'b0) begin - leaf_dec_wr_width = size [2:0] ; - $display("%0d: initiating %d word write to address %x (data=%x)...", $time, trans_size, address, wr_data); - end - else begin - leaf_dec_wr_width = 0; - $display("%0d: initiating %d word read to address %x...", $time, trans_size, address); - end - - @(posedge CLK); - leaf_dec_valid = 1'b0; - leaf_dec_wr_dvld <= ~trans_type[1]; - while (~dec_leaf_reject & ~dec_leaf_ack & ~dec_leaf_nack) begin - @(posedge CLK); - leaf_dec_wr_dvld = 1'b0; - end - - leaf_dec_valid = 1'b0; - leaf_dec_wr_dvld = 1'b0; - done = 1'b1; - $display(" accept = %d", dec_leaf_accept); - $display(" reject = %d", dec_leaf_reject); - $display(" ack = %d", dec_leaf_ack); - $display(" nack = %d", dec_leaf_nack); - $display(" return size = %x", dec_leaf_data_width); - $display(" retry = %d", dec_leaf_retry_atomic); - if (trans_type[1] == 1'b1) begin - $display(" read data = %x", dec_leaf_rd_data); - if (rd_compare) begin - if (dec_leaf_rd_data !== rd_data) $display(" read compare FAILED - expected %x", rd_data); - else $display(" read compare OK - expected %x", rd_data); - end - end - #1 active = 1'b0; - #1 done = 1'b0; - end - -endmodule - -// -//---------- module example_addr_map_test -// -module example_addr_map_test ( ); - //------- wire defines - wire [31:0] leaf_dec_wr_data; - wire [39:0] leaf_dec_addr; - wire leaf_dec_block_sel; - wire leaf_dec_valid; - wire leaf_dec_wr_dvld; - wire [1:0] leaf_dec_cycle; - wire [2:0] leaf_dec_wr_width; - wire [31:0] dec_leaf_rd_data; - wire dec_leaf_ack; - wire dec_leaf_nack; - wire dec_leaf_accept; - wire dec_leaf_reject; - wire dec_leaf_retry_atomic; - wire [2:0] dec_leaf_data_width; - wire [7:0] l2h_r0_f0_r; - wire [7:0] l2h_r0_f1_r; - wire [15:0] l2h_r0_f2_r; - wire [3:0] l2h_r1_f0_r; - wire [3:0] l2h_r1_f1_r; - wire active; - wire done; - - //------- reg defines - reg CLK; - reg CLK_div2; - reg CLK_div4; - reg clk; - reg reset; - reg [39:0] address; - reg [31:0] wr_data; - reg wr_enable; - reg rd_compare; - reg [31:0] rd_data; - reg [1:0] trans_type; - reg [3:0] size; - reg leaf_go; - - always @(*) - clk = CLK; - - initial - begin - $display(" << Starting the Simulation >>"); - $dumpfile("test.vcd"); - $dumpvars(0,example_addr_map_test); - #5000 - $dumpoff; - $finish; - end - - initial - begin - CLK = 1'b0; // at time 0 - CLK_div2 = 1'b0; - CLK_div4 = 1'b0; - reset = 0; // toggle reset - #15 reset = 1'b1; - $display(" %0d: Applying reset...", $time); - #30 reset = 1'b0; - $display(" %0d: Releasing reset...", $time); - end - - always - #5 CLK = ~CLK; - - always @ (posedge CLK) - CLK_div2 = ~CLK_div2; - - always @ (posedge CLK_div2) - CLK_div4 = ~CLK_div4; - - // 32b write task - task write32; - input [39:0] in_address; - input [31:0] in_wr_data; - input in_wr_enable; - output [39:0] address; - output [31:0] wr_data; - output wr_enable; - output rd_compare; - output [31:0] rd_data; - output [1:0] trans_type; - output [3:0] size; - output leaf_go; - begin - address = #1 in_address; - wr_data = 0; - wr_data [31:0] = in_wr_data; - wr_enable = in_wr_enable; - rd_compare = 0; - rd_data = 0; - trans_type = 0; - size = 4'd0; - leaf_go = 1'b1; - end - endtask - - // 32b read task - task read32; - input [39:0] in_address; - input in_rd_compare; - input [31:0] in_rd_data; - output [39:0] address; - output [31:0] wr_data; - output wr_enable; - output rd_compare; - output [31:0] rd_data; - output [1:0] trans_type; - output [3:0] size; - output leaf_go; - begin - address = #1 in_address; - wr_data = 0; - wr_enable = 0; - rd_compare = in_rd_compare; - rd_data = 0; - rd_data [31:0] = in_rd_data; - trans_type = 2'b10; - size = 4'd0; - leaf_go = 1'b1; - end - endtask - - initial - begin - CLK = 0; - CLK_div2 = 0; - CLK_div4 = 0; - reset = 0; - address = 0; - wr_data = 0; - wr_enable = 0; - rd_compare = 0; - rd_data = 0; - trans_type = 0; - size = 0; - leaf_go = 0; - - address = 0; - wr_data = 0; - wr_enable = 0; - rd_compare = 0; - rd_data = 0; - trans_type = 0; - size = 0; - leaf_go = 0; - repeat(5) - @(posedge CLK); - - write32(40'h0, 32'ha5a5a5a5, 0, address, wr_data, wr_enable, rd_compare, rd_data, trans_type, size, leaf_go); - @ (posedge done) - leaf_go = #2 1'b0; - - read32(40'h0, 0, 0, address, wr_data, wr_enable, rd_compare, rd_data, trans_type, size, leaf_go); - @ (posedge done) - leaf_go = #2 1'b0; - - end - - - example_addr_map_pio pio_dut_0 ( - .clk(clk), - .reset(reset), - .leaf_dec_wr_data(leaf_dec_wr_data), - .leaf_dec_addr(leaf_dec_addr), - .leaf_dec_block_sel(leaf_dec_block_sel), - .leaf_dec_valid(leaf_dec_valid), - .leaf_dec_wr_dvld(leaf_dec_wr_dvld), - .leaf_dec_cycle(leaf_dec_cycle), - .leaf_dec_wr_width(leaf_dec_wr_width), - .l2h_r0_f0_r(l2h_r0_f0_r), - .l2h_r0_f1_r(l2h_r0_f1_r), - .l2h_r0_f2_r(l2h_r0_f2_r), - .l2h_r1_f0_r(l2h_r1_f0_r), - .l2h_r1_f1_r(l2h_r1_f1_r), - .dec_leaf_rd_data(dec_leaf_rd_data), - .dec_leaf_ack(dec_leaf_ack), - .dec_leaf_nack(dec_leaf_nack), - .dec_leaf_accept(dec_leaf_accept), - .dec_leaf_reject(dec_leaf_reject), - .dec_leaf_retry_atomic(dec_leaf_retry_atomic), - .dec_leaf_data_width(dec_leaf_data_width) ); - - example_addr_map_test_leaf_bfm leaf_bfm ( - .address(address), - .wr_data(wr_data), - .wr_enable(wr_enable), - .rd_compare(rd_compare), - .rd_data(rd_data), - .trans_type(trans_type), - .size(size), - .leaf_go(leaf_go), - .CLK(CLK), - .dec_leaf_rd_data(dec_leaf_rd_data), - .dec_leaf_ack(dec_leaf_ack), - .dec_leaf_nack(dec_leaf_nack), - .dec_leaf_accept(dec_leaf_accept), - .dec_leaf_reject(dec_leaf_reject), - .dec_leaf_retry_atomic(dec_leaf_retry_atomic), - .dec_leaf_data_width(dec_leaf_data_width), - .active(active), - .done(done), - .leaf_dec_addr(leaf_dec_addr), - .leaf_dec_wr_data(leaf_dec_wr_data), - .leaf_dec_valid(leaf_dec_valid), - .leaf_dec_wr_dvld(leaf_dec_wr_dvld), - .leaf_dec_cycle(leaf_dec_cycle), - .leaf_dec_wr_width(leaf_dec_wr_width) ); - -endmodule - diff --git a/test/basic_tests/rdl_c_header/output.h b/test/basic_tests/rdl_c_header/output.h deleted file mode 100644 index f65a302..0000000 --- a/test/basic_tests/rdl_c_header/output.h +++ /dev/null @@ -1,73 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////// -// -/* This is an automatically generated header file for example_addr_map address map */ -// -/* DO NOT MODIFY THIS FILE! USE 'openrdt' toolchain to modify register map! */ -// -/* Generated on: 2021-10-19 */ -// -/////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef __EXAMPLE_ADDR_MAP_REGISTER_MAP__ -#define __EXAMPLE_ADDR_MAP_REGISTER_MAP__ - -/* - * bits.h - * - * Struct and function declarations for dealing with bit assignment. - */ - -#ifndef _BITS_H -#define _BITS_H - -#define BITS_PER_LONG 32 - -// ## allows token concatenation -//X = 1 and Y = 10 would return 110 -#define __AC(X,Y) (X##Y) -#define _AC(X,Y) __AC(X,Y) - -#define _UL(x) (_AC(x, UL)) -#define UL(x) (_UL(x)) - -#define BIT(nr) (1UL << (nr)) -// BIT defines a bit mask for the specified bit number from 0 to whatever fits into an unsigned long -// so BIT(10) should evaluate to decimal 1024 (which is binary 1 left shifted by 10 bits) - -#define GENMASK_INPUT_CHECK(h, l) 0 - -// h is high index, l is low index in a bitfield -// __GENMASK returns 32 bit number with 1s in the h-to-l field -// if h = 4 and l = 1, __GENMASK would return 00000000000000000000000000011110 -#define __GENMASK(h, l) \ - (((~UL(0)) - (UL(1) << (l)) + 1) & \ - (~UL(0) >> (BITS_PER_LONG - 1 - (h)))) - -#define GENMASK(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) - -#endif /* _BITS_H */ -/* EXAMPLE_ADDR_MAP_REGISTERS memory map */ -enum EXAMPLE_ADDR_MAP_REGS { - DEVICE_ID = 0x0, - SPI_CONFIG = 0x4, - SPI_STATUS = 0x8, -}; - -/* DEVICE_ID registers */ -#define FLD_A GENMASK(7, 0) -#define FLD_B GENMASK(15, 8) -#define FLD_C GENMASK(31, 16) - -/* SPI_CONFIG registers */ -#define REV_MINOR GENMASK(3, 0) -#define REV_MAJOR GENMASK(7, 4) - -/* SPI_STATUS registers */ -#define MASTER GENMASK(3, 2) -#define MASTER1 GENMASK(1, 0) -#define TRANSFER GENMASK(7, 4) - -#endif diff --git a/test/basic_tests/rdl_fieldstruct/golden/output.h b/test/basic_tests/rdl_fieldstruct/golden/output.h new file mode 100644 index 0000000..a59a901 --- /dev/null +++ b/test/basic_tests/rdl_fieldstruct/golden/output.h @@ -0,0 +1,49 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_fieldstruct/test.rdl +// Parms: ./rdl_fieldstruct/test.parms +// Date: Thu Jul 20 13:46:42 EDT 2023 +// + +#ifndef __FOO_REGISTER_MAP__ +#define __FOO_REGISTER_MAP__ + +#include + +/* FOO_REGISTERS memory map */ +enum FOO_REGS { + AREG_0 = 0x0, + AREG_1 = 0x4, + BLABLA = 0x8 +}; + +/* AREG_0 register fields */ +#define AREG_0_HIER_FS_FS1_FLD1 GENMASK(3, 0) +#define AREG_0_HIER_FS_FS1_FLD2 BIT(4) +#define AREG_0_HIER_FS_FLD1 BIT(5) +#define AREG_0_HIER_FS_FS2_FLD1 GENMASK(9, 6) +#define AREG_0_HIER_FS_FS2_FLD2 BIT(14) +#define AREG_0_FS3_FLD1 GENMASK(27, 24) +#define AREG_0_FS3_FLD2 BIT(28) + +/* AREG_1 register fields */ +#define AREG_1_HIER_FS_FS1_FLD1 GENMASK(3, 0) +#define AREG_1_HIER_FS_FS1_FLD2 BIT(4) +#define AREG_1_HIER_FS_FLD1 BIT(5) +#define AREG_1_HIER_FS_FS2_FLD1 GENMASK(9, 6) +#define AREG_1_HIER_FS_FS2_FLD2 BIT(14) +#define AREG_1_FS3_FLD1 GENMASK(27, 24) +#define AREG_1_FS3_FLD2 BIT(28) + +/* BLABLA register fields */ +#define BLABLA_FS1_0_FLD1 GENMASK(3, 0) +#define BLABLA_FS1_0_FLD2 BIT(4) +#define BLABLA_FS1_1_FLD1 GENMASK(8, 5) +#define BLABLA_FS1_1_FLD2 BIT(9) +#define BLABLA_FS1_2_FLD1 GENMASK(13, 10) +#define BLABLA_FS1_2_FLD2 BIT(14) +#define BLABLA_FS3_0_FLD1 GENMASK(18, 15) +#define BLABLA_FS3_0_FLD2 BIT(19) +#define BLABLA_FS3_1_FLD1 GENMASK(26, 23) +#define BLABLA_FS3_1_FLD2 BIT(27) + +#endif diff --git a/test/basic_tests/rdl_hello/golden/output.h b/test/basic_tests/rdl_hello/golden/output.h new file mode 100644 index 0000000..f1de648 --- /dev/null +++ b/test/basic_tests/rdl_hello/golden/output.h @@ -0,0 +1,28 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_hello/test.rdl +// Parms: ./rdl_hello/test.parms +// Date: Thu Jul 20 13:46:43 EDT 2023 +// + +#ifndef __FOO_REGISTER_MAP__ +#define __FOO_REGISTER_MAP__ + +#include + +/* FOO_REGISTERS memory map */ +enum FOO_REGS { + BAR_A_REG_0 = 0x0, + BAR_A_REG_1 = 0x4 +}; + +/* BAR_A_REG_0 register fields */ +#define BAR_A_REG_0_FLD1 GENMASK(9, 0) /* field 1 */ +#define BAR_A_REG_0_FLD2 BIT(15) /* field 2 */ +#define BAR_A_REG_0_ERR25 BIT(25) + +/* BAR_A_REG_1 register fields */ +#define BAR_A_REG_1_FLD1 GENMASK(9, 0) /* field 1 */ +#define BAR_A_REG_1_FLD2 BIT(15) /* field 2 */ +#define BAR_A_REG_1_ERR25 BIT(25) + +#endif diff --git a/test/basic_tests/rdl_hier_01/golden/output.h b/test/basic_tests/rdl_hier_01/golden/output.h new file mode 100644 index 0000000..fc28708 --- /dev/null +++ b/test/basic_tests/rdl_hier_01/golden/output.h @@ -0,0 +1,744 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_hier_01/test.rdl +// Parms: ./rdl_hier_01/test.parms +// Date: Thu Jul 20 13:46:44 EDT 2023 +// + +#ifndef __BASE_MAP_REGISTER_MAP__ +#define __BASE_MAP_REGISTER_MAP__ + +#include + +/* BASE_MAP_REGISTERS memory map */ +enum BASE_MAP_REGS { + BASE_REGS_CONFIG_REGS_0 = 0x0, + BASE_REGS_CONFIG_REGS_1 = 0x4, + BASE_REGS_CONFIG_REGS_2 = 0x8, + BASE_REGS_CONFIG_REGS_3 = 0xc, + BASE_REGS_CONFIG_REGS_4 = 0x10, + BASE_REGS_CONFIG_REGS_5 = 0x14, + BASE_REGS_CONFIG_REGS_6 = 0x18, + BASE_REGS_CONFIG_REGS_7 = 0x1c, + BASE_REGS_STATE_REGS_0 = 0x100, + BASE_REGS_STATE_REGS_1 = 0x104, + BASE_REGS_STATE_REGS_2 = 0x108, + BASE_REGS_STATE_REGS_3 = 0x10c, + BASE_REGS_STATE_REGS_4 = 0x110, + BASE_REGS_STATE_REGS_5 = 0x114, + BASE_REGS_STATE_REGS_6 = 0x118, + BASE_REGS_STATE_REGS_7 = 0x11c, + EXT_BASE_REGS_CONFIG_REGS_0 = 0x10000, + EXT_BASE_REGS_CONFIG_REGS_1 = 0x10004, + EXT_BASE_REGS_CONFIG_REGS_2 = 0x10008, + EXT_BASE_REGS_CONFIG_REGS_3 = 0x1000c, + EXT_BASE_REGS_CONFIG_REGS_4 = 0x10010, + EXT_BASE_REGS_CONFIG_REGS_5 = 0x10014, + EXT_BASE_REGS_CONFIG_REGS_6 = 0x10018, + EXT_BASE_REGS_CONFIG_REGS_7 = 0x1001c, + EXT_BASE_REGS_STATE_REGS_0 = 0x10100, + EXT_BASE_REGS_STATE_REGS_1 = 0x10104, + EXT_BASE_REGS_STATE_REGS_2 = 0x10108, + EXT_BASE_REGS_STATE_REGS_3 = 0x1010c, + EXT_BASE_REGS_STATE_REGS_4 = 0x10110, + EXT_BASE_REGS_STATE_REGS_5 = 0x10114, + EXT_BASE_REGS_STATE_REGS_6 = 0x10118, + EXT_BASE_REGS_STATE_REGS_7 = 0x1011c, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x20000, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x20004, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x20008, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x2000c, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x20010, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x20014, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x20018, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x2001c, + L2_R16_CHILD_BASE_REGS_STATE_REGS_0 = 0x20100, + L2_R16_CHILD_BASE_REGS_STATE_REGS_1 = 0x20104, + L2_R16_CHILD_BASE_REGS_STATE_REGS_2 = 0x20108, + L2_R16_CHILD_BASE_REGS_STATE_REGS_3 = 0x2010c, + L2_R16_CHILD_BASE_REGS_STATE_REGS_4 = 0x20110, + L2_R16_CHILD_BASE_REGS_STATE_REGS_5 = 0x20114, + L2_R16_CHILD_BASE_REGS_STATE_REGS_6 = 0x20118, + L2_R16_CHILD_BASE_REGS_STATE_REGS_7 = 0x2011c, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x21000, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x21004, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x21008, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x2100c, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x21010, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x21014, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x21018, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x2101c, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x21100, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x21104, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x21108, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x2110c, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x21110, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x21114, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x21118, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x2111c, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x22000, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x22004, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x22008, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x2200c, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x22010, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x22014, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x22018, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x2201c, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 = 0x22100, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 = 0x22104, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 = 0x22108, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 = 0x2210c, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 = 0x22110, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 = 0x22114, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 = 0x22118, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 = 0x2211c, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x22800, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x22804, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x22808, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x2280c, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x22810, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x22814, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x22818, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x2281c, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x22900, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x22904, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x22908, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x2290c, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x22910, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x22914, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x22918, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x2291c, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x30000, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x30004, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x30008, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x3000c, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x30010, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x30014, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x30018, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x3001c, + L2_S8_CHILD_BASE_REGS_STATE_REGS_0 = 0x30100, + L2_S8_CHILD_BASE_REGS_STATE_REGS_1 = 0x30104, + L2_S8_CHILD_BASE_REGS_STATE_REGS_2 = 0x30108, + L2_S8_CHILD_BASE_REGS_STATE_REGS_3 = 0x3010c, + L2_S8_CHILD_BASE_REGS_STATE_REGS_4 = 0x30110, + L2_S8_CHILD_BASE_REGS_STATE_REGS_5 = 0x30114, + L2_S8_CHILD_BASE_REGS_STATE_REGS_6 = 0x30118, + L2_S8_CHILD_BASE_REGS_STATE_REGS_7 = 0x3011c, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x31000, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x31004, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x31008, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x3100c, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x31010, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x31014, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x31018, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x3101c, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x31100, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x31104, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x31108, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x3110c, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x31110, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x31114, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x31118, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x3111c, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x32000, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x32004, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x32008, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x3200c, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x32010, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x32014, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x32018, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x3201c, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 = 0x32100, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 = 0x32104, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 = 0x32108, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 = 0x3210c, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 = 0x32110, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 = 0x32114, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 = 0x32118, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 = 0x3211c, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x32800, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x32804, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x32808, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x3280c, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x32810, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x32814, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x32818, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x3281c, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x32900, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x32904, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x32908, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x3290c, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x32910, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x32914, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x32918, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x3291c, + NO_OPT_REG = 0x40000, + OPT_REG = 0x40010 +}; + +/* BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* NO_OPT_REG (State reg) register fields */ +#define NO_OPT_REG_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* OPT_REG (State reg) register fields */ +#define OPT_REG_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +#endif diff --git a/test/basic_tests/rdl_hier_02/golden/output.h b/test/basic_tests/rdl_hier_02/golden/output.h new file mode 100644 index 0000000..b93b64c --- /dev/null +++ b/test/basic_tests/rdl_hier_02/golden/output.h @@ -0,0 +1,1159 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_hier_02/test.rdl +// Parms: ./rdl_hier_02/test.parms +// Date: Thu Jul 20 13:46:46 EDT 2023 +// + +#ifndef __BASE_MAP_REGISTER_MAP__ +#define __BASE_MAP_REGISTER_MAP__ + +#include + +/* BASE_MAP_REGISTERS memory map */ +enum BASE_MAP_REGS { + BASE_REGS_CONFIG_REGS_0 = 0x0, + BASE_REGS_CONFIG_REGS_1 = 0x4, + BASE_REGS_CONFIG_REGS_2 = 0x8, + BASE_REGS_CONFIG_REGS_3 = 0xc, + BASE_REGS_CONFIG_REGS_4 = 0x10, + BASE_REGS_CONFIG_REGS_5 = 0x14, + BASE_REGS_CONFIG_REGS_6 = 0x18, + BASE_REGS_CONFIG_REGS_7 = 0x1c, + BASE_REGS_STATE_REGS_0 = 0x100, + BASE_REGS_STATE_REGS_1 = 0x104, + BASE_REGS_STATE_REGS_2 = 0x108, + BASE_REGS_STATE_REGS_3 = 0x10c, + BASE_REGS_STATE_REGS_4 = 0x110, + BASE_REGS_STATE_REGS_5 = 0x114, + BASE_REGS_STATE_REGS_6 = 0x118, + BASE_REGS_STATE_REGS_7 = 0x11c, + EXT_BASE_REGS_CONFIG_REGS_0 = 0x10000, + EXT_BASE_REGS_CONFIG_REGS_1 = 0x10004, + EXT_BASE_REGS_CONFIG_REGS_2 = 0x10008, + EXT_BASE_REGS_CONFIG_REGS_3 = 0x1000c, + EXT_BASE_REGS_CONFIG_REGS_4 = 0x10010, + EXT_BASE_REGS_CONFIG_REGS_5 = 0x10014, + EXT_BASE_REGS_CONFIG_REGS_6 = 0x10018, + EXT_BASE_REGS_CONFIG_REGS_7 = 0x1001c, + EXT_BASE_REGS_STATE_REGS_0 = 0x10100, + EXT_BASE_REGS_STATE_REGS_1 = 0x10104, + EXT_BASE_REGS_STATE_REGS_2 = 0x10108, + EXT_BASE_REGS_STATE_REGS_3 = 0x1010c, + EXT_BASE_REGS_STATE_REGS_4 = 0x10110, + EXT_BASE_REGS_STATE_REGS_5 = 0x10114, + EXT_BASE_REGS_STATE_REGS_6 = 0x10118, + EXT_BASE_REGS_STATE_REGS_7 = 0x1011c, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x20000, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x20004, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x20008, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x2000c, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x20010, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x20014, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x20018, + L2_R16_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x2001c, + L2_R16_CHILD_BASE_REGS_STATE_REGS_0 = 0x20100, + L2_R16_CHILD_BASE_REGS_STATE_REGS_1 = 0x20104, + L2_R16_CHILD_BASE_REGS_STATE_REGS_2 = 0x20108, + L2_R16_CHILD_BASE_REGS_STATE_REGS_3 = 0x2010c, + L2_R16_CHILD_BASE_REGS_STATE_REGS_4 = 0x20110, + L2_R16_CHILD_BASE_REGS_STATE_REGS_5 = 0x20114, + L2_R16_CHILD_BASE_REGS_STATE_REGS_6 = 0x20118, + L2_R16_CHILD_BASE_REGS_STATE_REGS_7 = 0x2011c, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x21000, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x21004, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x21008, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x2100c, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x21010, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x21014, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x21018, + L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x2101c, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x21100, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x21104, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x21108, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x2110c, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x21110, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x21114, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x21118, + L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x2111c, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x22000, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x22004, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x22008, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x2200c, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x22010, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x22014, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x22018, + L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x2201c, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 = 0x22100, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 = 0x22104, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 = 0x22108, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 = 0x2210c, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 = 0x22110, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 = 0x22114, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 = 0x22118, + L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 = 0x2211c, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x22800, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x22804, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x22808, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x2280c, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x22810, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x22814, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x22818, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x2281c, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x22900, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x22904, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x22908, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x2290c, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x22910, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x22914, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x22918, + L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x2291c, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x30000, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x30004, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x30008, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x3000c, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x30010, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x30014, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x30018, + L2_S8_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x3001c, + L2_S8_CHILD_BASE_REGS_STATE_REGS_0 = 0x30100, + L2_S8_CHILD_BASE_REGS_STATE_REGS_1 = 0x30104, + L2_S8_CHILD_BASE_REGS_STATE_REGS_2 = 0x30108, + L2_S8_CHILD_BASE_REGS_STATE_REGS_3 = 0x3010c, + L2_S8_CHILD_BASE_REGS_STATE_REGS_4 = 0x30110, + L2_S8_CHILD_BASE_REGS_STATE_REGS_5 = 0x30114, + L2_S8_CHILD_BASE_REGS_STATE_REGS_6 = 0x30118, + L2_S8_CHILD_BASE_REGS_STATE_REGS_7 = 0x3011c, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x31000, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x31004, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x31008, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x3100c, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x31010, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x31014, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x31018, + L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x3101c, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x31100, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x31104, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x31108, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x3110c, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x31110, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x31114, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x31118, + L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x3111c, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x32000, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x32004, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x32008, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x3200c, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x32010, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x32014, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x32018, + L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x3201c, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 = 0x32100, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 = 0x32104, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 = 0x32108, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 = 0x3210c, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 = 0x32110, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 = 0x32114, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 = 0x32118, + L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 = 0x3211c, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x32800, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x32804, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x32808, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x3280c, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x32810, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x32814, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x32818, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x3281c, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x32900, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x32904, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x32908, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x3290c, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x32910, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x32914, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x32918, + L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x3291c, + L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x40000, + L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x40004, + L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x40008, + L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x4000c, + L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x40010, + L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x40014, + L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x40018, + L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x4001c, + L2_DFLT_CHILD_BASE_REGS_STATE_REGS_0 = 0x40100, + L2_DFLT_CHILD_BASE_REGS_STATE_REGS_1 = 0x40104, + L2_DFLT_CHILD_BASE_REGS_STATE_REGS_2 = 0x40108, + L2_DFLT_CHILD_BASE_REGS_STATE_REGS_3 = 0x4010c, + L2_DFLT_CHILD_BASE_REGS_STATE_REGS_4 = 0x40110, + L2_DFLT_CHILD_BASE_REGS_STATE_REGS_5 = 0x40114, + L2_DFLT_CHILD_BASE_REGS_STATE_REGS_6 = 0x40118, + L2_DFLT_CHILD_BASE_REGS_STATE_REGS_7 = 0x4011c, + L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x41000, + L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x41004, + L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x41008, + L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x4100c, + L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x41010, + L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x41014, + L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x41018, + L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x4101c, + L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x41100, + L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x41104, + L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x41108, + L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x4110c, + L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x41110, + L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x41114, + L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x41118, + L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x4111c, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 = 0x42000, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 = 0x42004, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 = 0x42008, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 = 0x4200c, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 = 0x42010, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 = 0x42014, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 = 0x42018, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 = 0x4201c, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 = 0x42100, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 = 0x42104, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 = 0x42108, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 = 0x4210c, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 = 0x42110, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 = 0x42114, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 = 0x42118, + L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 = 0x4211c, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 = 0x42800, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 = 0x42804, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 = 0x42808, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 = 0x4280c, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 = 0x42810, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 = 0x42814, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 = 0x42818, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 = 0x4281c, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 = 0x42900, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 = 0x42904, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 = 0x42908, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 = 0x4290c, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 = 0x42910, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 = 0x42914, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 = 0x42918, + L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 = 0x4291c, + SINGLETON_RF_S8_SING_REG = 0x50000, + SINGLETON_RF_R16_SING_REG = 0x60000, + SINGLETON_RF_DFLT_SING_REG = 0x70000, + RF_LVL2_0_RF_LVL1_0_REG_DFLT = 0x80000, + RF_LVL2_0_RF_LVL1_0_REG_L1 = 0x80008, + RF_LVL2_0_RF_LVL1_0_REG_L2 = 0x80010, + RF_LVL2_0_RF_LVL1_1_REG_DFLT = 0x80080, + RF_LVL2_0_RF_LVL1_1_REG_L1 = 0x80088, + RF_LVL2_0_RF_LVL1_1_REG_L2 = 0x80090, + RF_LVL2_0_RF_LVL1_2_REG_DFLT = 0x80100, + RF_LVL2_0_RF_LVL1_2_REG_L1 = 0x80108, + RF_LVL2_0_RF_LVL1_2_REG_L2 = 0x80110, + RF_LVL2_0_RF_LVL1_3_REG_DFLT = 0x80180, + RF_LVL2_0_RF_LVL1_3_REG_L1 = 0x80188, + RF_LVL2_0_RF_LVL1_3_REG_L2 = 0x80190, + RF_LVL2_1_RF_LVL1_0_REG_DFLT = 0x81000, + RF_LVL2_1_RF_LVL1_0_REG_L1 = 0x81008, + RF_LVL2_1_RF_LVL1_0_REG_L2 = 0x81010, + RF_LVL2_1_RF_LVL1_1_REG_DFLT = 0x81080, + RF_LVL2_1_RF_LVL1_1_REG_L1 = 0x81088, + RF_LVL2_1_RF_LVL1_1_REG_L2 = 0x81090, + RF_LVL2_1_RF_LVL1_2_REG_DFLT = 0x81100, + RF_LVL2_1_RF_LVL1_2_REG_L1 = 0x81108, + RF_LVL2_1_RF_LVL1_2_REG_L2 = 0x81110, + RF_LVL2_1_RF_LVL1_3_REG_DFLT = 0x81180, + RF_LVL2_1_RF_LVL1_3_REG_L1 = 0x81188, + RF_LVL2_1_RF_LVL1_3_REG_L2 = 0x81190 +}; + +/* BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_R16_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_R16_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_R16_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_S8_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_S8_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_S8_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_DFLT_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_DFLT_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_0_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_1_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_2_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_3_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_4_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_5_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_6_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7 (State reg) register fields */ +#define L2_DFLT_CHILD_L3_CHILD_EXT_BASE_REGS_STATE_REGS_7_LSB_FIELD GENMASK(15, 0) /* Some state bits */ + +/* SINGLETON_RF_S8_SING_REG register fields */ +#define SINGLETON_RF_S8_SING_REG_LSB_FIELD GENMASK(15, 0) +#define SINGLETON_RF_S8_SING_REG_MSB_FIELD GENMASK(31, 16) + +/* SINGLETON_RF_R16_SING_REG register fields */ +#define SINGLETON_RF_R16_SING_REG_LSB_FIELD GENMASK(15, 0) +#define SINGLETON_RF_R16_SING_REG_MSB_FIELD GENMASK(31, 16) + +/* SINGLETON_RF_DFLT_SING_REG register fields */ +#define SINGLETON_RF_DFLT_SING_REG_LSB_FIELD GENMASK(15, 0) +#define SINGLETON_RF_DFLT_SING_REG_MSB_FIELD GENMASK(31, 16) + +/* RF_LVL2_0_RF_LVL1_0_REG_DFLT (Config reg set reg_dflt) register fields */ +#define RF_LVL2_0_RF_LVL1_0_REG_DFLT_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_0_REG_DFLT_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_0_REG_L1 (Config reg set reg_l1) register fields */ +#define RF_LVL2_0_RF_LVL1_0_REG_L1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_0_REG_L1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_0_REG_L2 (Config reg set reg_l2) register fields */ +#define RF_LVL2_0_RF_LVL1_0_REG_L2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_0_REG_L2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_1_REG_DFLT (Config reg set reg_dflt) register fields */ +#define RF_LVL2_0_RF_LVL1_1_REG_DFLT_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_1_REG_DFLT_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_1_REG_L1 (Config reg set reg_l1) register fields */ +#define RF_LVL2_0_RF_LVL1_1_REG_L1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_1_REG_L1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_1_REG_L2 (Config reg set reg_l2) register fields */ +#define RF_LVL2_0_RF_LVL1_1_REG_L2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_1_REG_L2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_2_REG_DFLT (Config reg set reg_dflt) register fields */ +#define RF_LVL2_0_RF_LVL1_2_REG_DFLT_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_2_REG_DFLT_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_2_REG_L1 (Config reg set reg_l1) register fields */ +#define RF_LVL2_0_RF_LVL1_2_REG_L1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_2_REG_L1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_2_REG_L2 (Config reg set reg_l2) register fields */ +#define RF_LVL2_0_RF_LVL1_2_REG_L2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_2_REG_L2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_3_REG_DFLT (Config reg set reg_dflt) register fields */ +#define RF_LVL2_0_RF_LVL1_3_REG_DFLT_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_3_REG_DFLT_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_3_REG_L1 (Config reg set reg_l1) register fields */ +#define RF_LVL2_0_RF_LVL1_3_REG_L1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_3_REG_L1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_0_RF_LVL1_3_REG_L2 (Config reg set reg_l2) register fields */ +#define RF_LVL2_0_RF_LVL1_3_REG_L2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_0_RF_LVL1_3_REG_L2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_0_REG_DFLT (Config reg set reg_dflt) register fields */ +#define RF_LVL2_1_RF_LVL1_0_REG_DFLT_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_0_REG_DFLT_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_0_REG_L1 (Config reg set reg_l1) register fields */ +#define RF_LVL2_1_RF_LVL1_0_REG_L1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_0_REG_L1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_0_REG_L2 (Config reg set reg_l2) register fields */ +#define RF_LVL2_1_RF_LVL1_0_REG_L2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_0_REG_L2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_1_REG_DFLT (Config reg set reg_dflt) register fields */ +#define RF_LVL2_1_RF_LVL1_1_REG_DFLT_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_1_REG_DFLT_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_1_REG_L1 (Config reg set reg_l1) register fields */ +#define RF_LVL2_1_RF_LVL1_1_REG_L1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_1_REG_L1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_1_REG_L2 (Config reg set reg_l2) register fields */ +#define RF_LVL2_1_RF_LVL1_1_REG_L2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_1_REG_L2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_2_REG_DFLT (Config reg set reg_dflt) register fields */ +#define RF_LVL2_1_RF_LVL1_2_REG_DFLT_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_2_REG_DFLT_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_2_REG_L1 (Config reg set reg_l1) register fields */ +#define RF_LVL2_1_RF_LVL1_2_REG_L1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_2_REG_L1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_2_REG_L2 (Config reg set reg_l2) register fields */ +#define RF_LVL2_1_RF_LVL1_2_REG_L2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_2_REG_L2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_3_REG_DFLT (Config reg set reg_dflt) register fields */ +#define RF_LVL2_1_RF_LVL1_3_REG_DFLT_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_3_REG_DFLT_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_3_REG_L1 (Config reg set reg_l1) register fields */ +#define RF_LVL2_1_RF_LVL1_3_REG_L1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_3_REG_L1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* RF_LVL2_1_RF_LVL1_3_REG_L2 (Config reg set reg_l2) register fields */ +#define RF_LVL2_1_RF_LVL1_3_REG_L2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define RF_LVL2_1_RF_LVL1_3_REG_L2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +#endif diff --git a/test/basic_tests/rdl_hwload/golden/output.h b/test/basic_tests/rdl_hwload/golden/output.h new file mode 100644 index 0000000..8baeca7 --- /dev/null +++ b/test/basic_tests/rdl_hwload/golden/output.h @@ -0,0 +1,58 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_hwload/test.rdl +// Parms: ./rdl_hwload/test.parms +// Date: Thu Jul 20 13:46:47 EDT 2023 +// + +#ifndef __BASEMAP_REGISTER_MAP__ +#define __BASEMAP_REGISTER_MAP__ + +#include + +/* BASEMAP_REGISTERS memory map */ +enum BASEMAP_REGS { + RF1_REG1 = 0x0, + RF1_REG2 = 0x10, + RF1_REG3 = 0x20, + RF2_REG1 = 0x100, + RF2_REG2 = 0x110, + RF2_REG3 = 0x120 +}; + +/* RF1_REG1 register fields */ +#define RF1_REG1_FLD1 GENMASK(7, 0) +#define RF1_REG1_FLD2 GENMASK(15, 8) +#define RF1_REG1_FLD3 GENMASK(23, 16) +#define RF1_REG1_FLD4 GENMASK(31, 24) + +/* RF1_REG2 register fields */ +#define RF1_REG2_FLD1 GENMASK(7, 0) +#define RF1_REG2_FLD2 GENMASK(15, 8) +#define RF1_REG2_FLD3 GENMASK(23, 16) +#define RF1_REG2_FLD4 GENMASK(31, 24) + +/* RF1_REG3 register fields */ +#define RF1_REG3_FLD1 GENMASK(7, 0) +#define RF1_REG3_FLD2 GENMASK(15, 8) +#define RF1_REG3_FLD3 GENMASK(23, 16) +#define RF1_REG3_FLD4 GENMASK(31, 24) + +/* RF2_REG1 register fields */ +#define RF2_REG1_FLD1 GENMASK(7, 0) +#define RF2_REG1_FLD2 GENMASK(15, 8) +#define RF2_REG1_FLD3 GENMASK(23, 16) +#define RF2_REG1_FLD4 GENMASK(31, 24) + +/* RF2_REG2 register fields */ +#define RF2_REG2_FLD1 GENMASK(7, 0) +#define RF2_REG2_FLD2 GENMASK(15, 8) +#define RF2_REG2_FLD3 GENMASK(23, 16) +#define RF2_REG2_FLD4 GENMASK(31, 24) + +/* RF2_REG3 register fields */ +#define RF2_REG3_FLD1 GENMASK(7, 0) +#define RF2_REG3_FLD2 GENMASK(15, 8) +#define RF2_REG3_FLD3 GENMASK(23, 16) +#define RF2_REG3_FLD4 GENMASK(31, 24) + +#endif diff --git a/test/basic_tests/rdl_intr_01/golden/output.h b/test/basic_tests/rdl_intr_01/golden/output.h new file mode 100644 index 0000000..854329c --- /dev/null +++ b/test/basic_tests/rdl_intr_01/golden/output.h @@ -0,0 +1,73 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_intr_01/test.rdl +// Parms: ./rdl_intr_01/test.parms +// Date: Thu Jul 20 13:46:48 EDT 2023 +// + +#ifndef __FOO_REGISTER_MAP__ +#define __FOO_REGISTER_MAP__ + +#include + +/* FOO_REGISTERS memory map */ +enum FOO_REGS { + BAR_A_REG_0 = 0x0, + BAR_A_REG_1 = 0x4, + BAR_INTR_REG1 = 0x100, + BAR_LOG_REG1 = 0x104, + BAR_LOG_REG2 = 0x108, + BAR_LOG_REG3 = 0x10c, + BAR_SUB_INTR_REG2 = 0x200, + BAR_SUB_INTR_REG3 = 0x300, + BAR_RST_REG = 0x304, + BAR_NEGINTR = 0x500, + BAR_BOTHINTR = 0x504, + INTR_CASCADE_MERGE = 0x1000 +}; + +/* BAR_A_REG_0 register fields */ +#define BAR_A_REG_0_FLD1 GENMASK(9, 0) +#define BAR_A_REG_0_FLD2 BIT(15) + +/* BAR_A_REG_1 register fields */ +#define BAR_A_REG_1_FLD1 GENMASK(9, 0) +#define BAR_A_REG_1_FLD2 BIT(15) + +/* BAR_INTR_REG1 register fields */ +#define BAR_INTR_REG1_INT1 BIT(0) /* interrupt 1 */ +#define BAR_INTR_REG1_INT2 BIT(1) /* interrupt 2 */ + +/* BAR_LOG_REG1 register fields */ +#define BAR_LOG_REG1_ERR_LOG GENMASK(9, 0) /* error log field */ + +/* BAR_LOG_REG2 register fields */ +#define BAR_LOG_REG2_ERR_LOG GENMASK(9, 0) /* error log field */ + +/* BAR_LOG_REG3 register fields */ +#define BAR_LOG_REG3_ERR_LOG GENMASK(9, 0) /* error log field */ + +/* BAR_SUB_INTR_REG2 register fields */ +#define BAR_SUB_INTR_REG2_INT1 BIT(0) /* interrupt 1 */ +#define BAR_SUB_INTR_REG2_INT2 BIT(1) /* interrupt 2 */ + +/* BAR_SUB_INTR_REG3 register fields */ +#define BAR_SUB_INTR_REG3_INT1 BIT(0) /* interrupt 1 */ +#define BAR_SUB_INTR_REG3_INT2 BIT(1) /* interrupt 2 */ + +/* BAR_RST_REG register fields */ +#define BAR_RST_REG_FLD1 GENMASK(7, 4) +#define BAR_RST_REG_FLD2 GENMASK(3, 0) +#define BAR_RST_REG_FLD3 GENMASK(10, 8) +#define BAR_RST_REG_FLD4 GENMASK(13, 11) + +/* BAR_NEGINTR (Reg negedge intr) register fields */ +#define BAR_NEGINTR_INTERRUPT BIT(0) /* negedge_intr check */ + +/* BAR_BOTHINTR (Reg bothedge intr) register fields */ +#define BAR_BOTHINTR_INTERRUPT BIT(0) /* bothedge_intr check */ + +/* INTR_CASCADE_MERGE register fields */ +#define INTR_CASCADE_MERGE_FLD1 BIT(0) +#define INTR_CASCADE_MERGE_FLD2 BIT(1) + +#endif diff --git a/test/basic_tests/rdl_iwrap/golden/output.h b/test/basic_tests/rdl_iwrap/golden/output.h new file mode 100644 index 0000000..de315db --- /dev/null +++ b/test/basic_tests/rdl_iwrap/golden/output.h @@ -0,0 +1,50 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_iwrap/test.rdl +// Parms: ./rdl_iwrap/test.parms +// Date: Thu Jul 20 13:46:49 EDT 2023 +// + +#ifndef __TOP_REGISTER_MAP__ +#define __TOP_REGISTER_MAP__ + +#include + +/* TOP_REGISTERS memory map */ +enum TOP_REGS { + REGS_NONE_REG_NONE = 0x0, + REGS_NONE_REG_INT = 0x4, + REGS_EXT_REG_NONE = 0x8, + REGS_EXT_REG_INT = 0xc, + WRAP_INFO_REG = 0x200 +}; + +/* REGS_NONE_REG_NONE register fields */ +#define REGS_NONE_REG_NONE_FLD_NONE BIT(0) +#define REGS_NONE_REG_NONE_FLD_GEN BIT(1) +#define REGS_NONE_REG_NONE_FLD_EXT BIT(2) +#define REGS_NONE_REG_NONE_FLD_INT BIT(3) + +/* REGS_NONE_REG_INT register fields */ +#define REGS_NONE_REG_INT_FLD_NONE BIT(0) +#define REGS_NONE_REG_INT_FLD_GEN BIT(1) +#define REGS_NONE_REG_INT_FLD_EXT BIT(2) +#define REGS_NONE_REG_INT_FLD_INT BIT(3) + +/* REGS_EXT_REG_NONE register fields */ +#define REGS_EXT_REG_NONE_FLD_NONE BIT(0) +#define REGS_EXT_REG_NONE_FLD_GEN BIT(1) +#define REGS_EXT_REG_NONE_FLD_EXT BIT(2) +#define REGS_EXT_REG_NONE_FLD_INT BIT(3) + +/* REGS_EXT_REG_INT register fields */ +#define REGS_EXT_REG_INT_FLD_NONE BIT(0) +#define REGS_EXT_REG_INT_FLD_GEN BIT(1) +#define REGS_EXT_REG_INT_FLD_EXT BIT(2) +#define REGS_EXT_REG_INT_FLD_INT BIT(3) + +/* WRAP_INFO_REG register fields */ +#define WRAP_INFO_REG_BAR1 BIT(0) +#define WRAP_INFO_REG_BAR2 BIT(1) +#define WRAP_INFO_REG_BAR3 BIT(2) + +#endif diff --git a/test/basic_tests/rdl_sec_if/golden/output.h b/test/basic_tests/rdl_sec_if/golden/output.h new file mode 100644 index 0000000..67e81ea --- /dev/null +++ b/test/basic_tests/rdl_sec_if/golden/output.h @@ -0,0 +1,96 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_sec_if/test.rdl +// Parms: ./rdl_sec_if/test.parms +// Date: Thu Jul 20 13:46:50 EDT 2023 +// + +#ifndef __BASE_MAP_REGISTER_MAP__ +#define __BASE_MAP_REGISTER_MAP__ + +#include + +/* BASE_MAP_REGISTERS memory map */ +enum BASE_MAP_REGS { + BASE_REGS_CONFIG_REGS_0 = 0x0, + BASE_REGS_CONFIG_REGS_1 = 0x4, + BASE_REGS_CONFIG_REGS_2 = 0x8, + BASE_REGS_CONFIG_REGS_3 = 0xc, + BASE_REGS_CONFIG_REGS_4 = 0x10, + BASE_REGS_CONFIG_REGS_5 = 0x14, + BASE_REGS_CONFIG_REGS_6 = 0x18, + BASE_REGS_CONFIG_REGS_7 = 0x1c, + PRIMARY_BASE_REGS_CONFIG_REGS_0 = 0x20, + PRIMARY_BASE_REGS_CONFIG_REGS_1 = 0x24, + PRIMARY_BASE_REGS_CONFIG_REGS_2 = 0x28, + PRIMARY_BASE_REGS_CONFIG_REGS_3 = 0x2c, + PRIMARY_BASE_REGS_CONFIG_REGS_4 = 0x30, + PRIMARY_BASE_REGS_CONFIG_REGS_5 = 0x34, + PRIMARY_BASE_REGS_CONFIG_REGS_6 = 0x38, + PRIMARY_BASE_REGS_CONFIG_REGS_7 = 0x3c +}; + +/* BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* PRIMARY_BASE_REGS_CONFIG_REGS_0 (Config reg set config_regs_0) register fields */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_0_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_0_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* PRIMARY_BASE_REGS_CONFIG_REGS_1 (Config reg set config_regs_1) register fields */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_1_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_1_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* PRIMARY_BASE_REGS_CONFIG_REGS_2 (Config reg set config_regs_2) register fields */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_2_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_2_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* PRIMARY_BASE_REGS_CONFIG_REGS_3 (Config reg set config_regs_3) register fields */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_3_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_3_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* PRIMARY_BASE_REGS_CONFIG_REGS_4 (Config reg set config_regs_4) register fields */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_4_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_4_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* PRIMARY_BASE_REGS_CONFIG_REGS_5 (Config reg set config_regs_5) register fields */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_5_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_5_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* PRIMARY_BASE_REGS_CONFIG_REGS_6 (Config reg set config_regs_6) register fields */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_6_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_6_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +/* PRIMARY_BASE_REGS_CONFIG_REGS_7 (Config reg set config_regs_7) register fields */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_7_LSB_FIELD GENMASK(15, 0) /* Bunch o lsb bits */ +#define PRIMARY_BASE_REGS_CONFIG_REGS_7_MSB_FIELD GENMASK(31, 16) /* Bunch o msb bits */ + +#endif diff --git a/test/basic_tests/rdl_uvmmem_default/golden/output.h b/test/basic_tests/rdl_uvmmem_default/golden/output.h new file mode 100644 index 0000000..2f591ba --- /dev/null +++ b/test/basic_tests/rdl_uvmmem_default/golden/output.h @@ -0,0 +1,3743 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_uvmmem_default/test.rdl +// Parms: ./rdl_uvmmem_default/test.parms +// Date: Thu Jul 20 13:46:52 EDT 2023 +// + +#ifndef __TOP_REGISTER_MAP__ +#define __TOP_REGISTER_MAP__ + +#include + +/* TOP_REGISTERS memory map */ +enum TOP_REGS { + SR1 = 0x0, + WR1 = 0x100, + SR_REPEAT1 = 0x200, + SR_REPEAT2 = 0x204, + SR_REPEAT3 = 0x208, + SRMEM1_0 = 0x2000, + SRMEM1_1 = 0x2004, + SRMEM1_2 = 0x2008, + SRMEM1_3 = 0x200c, + SRMEM1_4 = 0x2010, + SRMEM1_5 = 0x2014, + SRMEM1_6 = 0x2018, + SRMEM1_7 = 0x201c, + SRMEM1_8 = 0x2020, + SRMEM1_9 = 0x2024, + SRMEM1_10 = 0x2028, + SRMEM1_11 = 0x202c, + SRMEM1_12 = 0x2030, + SRMEM1_13 = 0x2034, + SRMEM1_14 = 0x2038, + SRMEM1_15 = 0x203c, + SRMEM1_16 = 0x2040, + SRMEM1_17 = 0x2044, + SRMEM1_18 = 0x2048, + SRMEM1_19 = 0x204c, + SRMEM1_20 = 0x2050, + SRMEM1_21 = 0x2054, + SRMEM1_22 = 0x2058, + SRMEM1_23 = 0x205c, + SRMEM1_24 = 0x2060, + SRMEM1_25 = 0x2064, + SRMEM1_26 = 0x2068, + SRMEM1_27 = 0x206c, + SRMEM1_28 = 0x2070, + SRMEM1_29 = 0x2074, + SRMEM1_30 = 0x2078, + SRMEM1_31 = 0x207c, + SRMEM1_32 = 0x2080, + SRMEM1_33 = 0x2084, + SRMEM1_34 = 0x2088, + SRMEM1_35 = 0x208c, + SRMEM1_36 = 0x2090, + SRMEM1_37 = 0x2094, + SRMEM1_38 = 0x2098, + SRMEM1_39 = 0x209c, + SRMEM1_40 = 0x20a0, + SRMEM1_41 = 0x20a4, + SRMEM1_42 = 0x20a8, + SRMEM1_43 = 0x20ac, + SRMEM1_44 = 0x20b0, + SRMEM1_45 = 0x20b4, + SRMEM1_46 = 0x20b8, + SRMEM1_47 = 0x20bc, + SRMEM1_48 = 0x20c0, + SRMEM1_49 = 0x20c4, + SRMEM1_50 = 0x20c8, + SRMEM1_51 = 0x20cc, + SRMEM1_52 = 0x20d0, + SRMEM1_53 = 0x20d4, + SRMEM1_54 = 0x20d8, + SRMEM1_55 = 0x20dc, + SRMEM1_56 = 0x20e0, + SRMEM1_57 = 0x20e4, + SRMEM1_58 = 0x20e8, + SRMEM1_59 = 0x20ec, + SRMEM1_60 = 0x20f0, + SRMEM1_61 = 0x20f4, + SRMEM1_62 = 0x20f8, + SRMEM1_63 = 0x20fc, + SRMEM1_64 = 0x2100, + SRMEM1_65 = 0x2104, + SRMEM1_66 = 0x2108, + SRMEM1_67 = 0x210c, + SRMEM1_68 = 0x2110, + SRMEM1_69 = 0x2114, + SRMEM1_70 = 0x2118, + SRMEM1_71 = 0x211c, + SRMEM1_72 = 0x2120, + SRMEM1_73 = 0x2124, + SRMEM1_74 = 0x2128, + SRMEM1_75 = 0x212c, + SRMEM1_76 = 0x2130, + SRMEM1_77 = 0x2134, + SRMEM1_78 = 0x2138, + SRMEM1_79 = 0x213c, + SRMEM1_80 = 0x2140, + SRMEM1_81 = 0x2144, + SRMEM1_82 = 0x2148, + SRMEM1_83 = 0x214c, + SRMEM1_84 = 0x2150, + SRMEM1_85 = 0x2154, + SRMEM1_86 = 0x2158, + SRMEM1_87 = 0x215c, + SRMEM1_88 = 0x2160, + SRMEM1_89 = 0x2164, + SRMEM1_90 = 0x2168, + SRMEM1_91 = 0x216c, + SRMEM1_92 = 0x2170, + SRMEM1_93 = 0x2174, + SRMEM1_94 = 0x2178, + SRMEM1_95 = 0x217c, + SRMEM1_96 = 0x2180, + SRMEM1_97 = 0x2184, + SRMEM1_98 = 0x2188, + SRMEM1_99 = 0x218c, + WRMEM1_0 = 0x20000, + WRMEM1_1 = 0x20010, + WRMEM1_2 = 0x20020, + WRMEM1_3 = 0x20030, + WRMEM1_4 = 0x20040, + WRMEM1_5 = 0x20050, + WRMEM1_6 = 0x20060, + WRMEM1_7 = 0x20070, + WRMEM1_8 = 0x20080, + WRMEM1_9 = 0x20090, + WRMEM1_10 = 0x200a0, + WRMEM1_11 = 0x200b0, + WRMEM1_12 = 0x200c0, + WRMEM1_13 = 0x200d0, + WRMEM1_14 = 0x200e0, + WRMEM1_15 = 0x200f0, + WRMEM1_16 = 0x20100, + WRMEM1_17 = 0x20110, + WRMEM1_18 = 0x20120, + WRMEM1_19 = 0x20130, + WRMEM1_20 = 0x20140, + WRMEM1_21 = 0x20150, + WRMEM1_22 = 0x20160, + WRMEM1_23 = 0x20170, + WRMEM1_24 = 0x20180, + WRMEM1_25 = 0x20190, + WRMEM1_26 = 0x201a0, + WRMEM1_27 = 0x201b0, + WRMEM1_28 = 0x201c0, + WRMEM1_29 = 0x201d0, + WRMEM1_30 = 0x201e0, + WRMEM1_31 = 0x201f0, + WRMEM1_32 = 0x20200, + WRMEM1_33 = 0x20210, + WRMEM1_34 = 0x20220, + WRMEM1_35 = 0x20230, + WRMEM1_36 = 0x20240, + WRMEM1_37 = 0x20250, + WRMEM1_38 = 0x20260, + WRMEM1_39 = 0x20270, + WRMEM1_40 = 0x20280, + WRMEM1_41 = 0x20290, + WRMEM1_42 = 0x202a0, + WRMEM1_43 = 0x202b0, + WRMEM1_44 = 0x202c0, + WRMEM1_45 = 0x202d0, + WRMEM1_46 = 0x202e0, + WRMEM1_47 = 0x202f0, + WRMEM1_48 = 0x20300, + WRMEM1_49 = 0x20310, + WRMEM1_50 = 0x20320, + WRMEM1_51 = 0x20330, + WRMEM1_52 = 0x20340, + WRMEM1_53 = 0x20350, + WRMEM1_54 = 0x20360, + WRMEM1_55 = 0x20370, + WRMEM1_56 = 0x20380, + WRMEM1_57 = 0x20390, + WRMEM1_58 = 0x203a0, + WRMEM1_59 = 0x203b0, + WRMEM1_60 = 0x203c0, + WRMEM1_61 = 0x203d0, + WRMEM1_62 = 0x203e0, + WRMEM1_63 = 0x203f0, + WRMEM1_64 = 0x20400, + WRMEM1_65 = 0x20410, + WRMEM1_66 = 0x20420, + WRMEM1_67 = 0x20430, + WRMEM1_68 = 0x20440, + WRMEM1_69 = 0x20450, + WRMEM1_70 = 0x20460, + WRMEM1_71 = 0x20470, + WRMEM1_72 = 0x20480, + WRMEM1_73 = 0x20490, + WRMEM1_74 = 0x204a0, + WRMEM1_75 = 0x204b0, + WRMEM1_76 = 0x204c0, + WRMEM1_77 = 0x204d0, + WRMEM1_78 = 0x204e0, + WRMEM1_79 = 0x204f0, + WRMEM1_80 = 0x20500, + WRMEM1_81 = 0x20510, + WRMEM1_82 = 0x20520, + WRMEM1_83 = 0x20530, + WRMEM1_84 = 0x20540, + WRMEM1_85 = 0x20550, + WRMEM1_86 = 0x20560, + WRMEM1_87 = 0x20570, + WRMEM1_88 = 0x20580, + WRMEM1_89 = 0x20590, + WRMEM1_90 = 0x205a0, + WRMEM1_91 = 0x205b0, + WRMEM1_92 = 0x205c0, + WRMEM1_93 = 0x205d0, + WRMEM1_94 = 0x205e0, + WRMEM1_95 = 0x205f0, + WRMEM1_96 = 0x20600, + WRMEM1_97 = 0x20610, + WRMEM1_98 = 0x20620, + WRMEM1_99 = 0x20630, + WRMEM1_100 = 0x20640, + WRMEM1_101 = 0x20650, + WRMEM1_102 = 0x20660, + WRMEM1_103 = 0x20670, + WRMEM1_104 = 0x20680, + WRMEM1_105 = 0x20690, + WRMEM1_106 = 0x206a0, + WRMEM1_107 = 0x206b0, + WRMEM1_108 = 0x206c0, + WRMEM1_109 = 0x206d0, + WRMEM1_110 = 0x206e0, + WRMEM1_111 = 0x206f0, + WRMEM1_112 = 0x20700, + WRMEM1_113 = 0x20710, + WRMEM1_114 = 0x20720, + WRMEM1_115 = 0x20730, + WRMEM1_116 = 0x20740, + WRMEM1_117 = 0x20750, + WRMEM1_118 = 0x20760, + WRMEM1_119 = 0x20770, + WRMEM1_120 = 0x20780, + WRMEM1_121 = 0x20790, + WRMEM1_122 = 0x207a0, + WRMEM1_123 = 0x207b0, + WRMEM1_124 = 0x207c0, + WRMEM1_125 = 0x207d0, + WRMEM1_126 = 0x207e0, + WRMEM1_127 = 0x207f0, + WRMEM1_128 = 0x20800, + WRMEM1_129 = 0x20810, + WRMEM1_130 = 0x20820, + WRMEM1_131 = 0x20830, + WRMEM1_132 = 0x20840, + WRMEM1_133 = 0x20850, + WRMEM1_134 = 0x20860, + WRMEM1_135 = 0x20870, + WRMEM1_136 = 0x20880, + WRMEM1_137 = 0x20890, + WRMEM1_138 = 0x208a0, + WRMEM1_139 = 0x208b0, + WRMEM1_140 = 0x208c0, + WRMEM1_141 = 0x208d0, + WRMEM1_142 = 0x208e0, + WRMEM1_143 = 0x208f0, + WRMEM1_144 = 0x20900, + WRMEM1_145 = 0x20910, + WRMEM1_146 = 0x20920, + WRMEM1_147 = 0x20930, + WRMEM1_148 = 0x20940, + WRMEM1_149 = 0x20950, + WRMEM1_150 = 0x20960, + WRMEM1_151 = 0x20970, + WRMEM1_152 = 0x20980, + WRMEM1_153 = 0x20990, + WRMEM1_154 = 0x209a0, + WRMEM1_155 = 0x209b0, + WRMEM1_156 = 0x209c0, + WRMEM1_157 = 0x209d0, + WRMEM1_158 = 0x209e0, + WRMEM1_159 = 0x209f0, + WRMEM1_160 = 0x20a00, + WRMEM1_161 = 0x20a10, + WRMEM1_162 = 0x20a20, + WRMEM1_163 = 0x20a30, + WRMEM1_164 = 0x20a40, + WRMEM1_165 = 0x20a50, + WRMEM1_166 = 0x20a60, + WRMEM1_167 = 0x20a70, + WRMEM1_168 = 0x20a80, + WRMEM1_169 = 0x20a90, + WRMEM1_170 = 0x20aa0, + WRMEM1_171 = 0x20ab0, + WRMEM1_172 = 0x20ac0, + WRMEM1_173 = 0x20ad0, + WRMEM1_174 = 0x20ae0, + WRMEM1_175 = 0x20af0, + WRMEM1_176 = 0x20b00, + WRMEM1_177 = 0x20b10, + WRMEM1_178 = 0x20b20, + WRMEM1_179 = 0x20b30, + WRMEM1_180 = 0x20b40, + WRMEM1_181 = 0x20b50, + WRMEM1_182 = 0x20b60, + WRMEM1_183 = 0x20b70, + WRMEM1_184 = 0x20b80, + WRMEM1_185 = 0x20b90, + WRMEM1_186 = 0x20ba0, + WRMEM1_187 = 0x20bb0, + WRMEM1_188 = 0x20bc0, + WRMEM1_189 = 0x20bd0, + WRMEM1_190 = 0x20be0, + WRMEM1_191 = 0x20bf0, + WRMEM1_192 = 0x20c00, + WRMEM1_193 = 0x20c10, + WRMEM1_194 = 0x20c20, + WRMEM1_195 = 0x20c30, + WRMEM1_196 = 0x20c40, + WRMEM1_197 = 0x20c50, + WRMEM1_198 = 0x20c60, + WRMEM1_199 = 0x20c70, + WRMEM1_200 = 0x20c80, + WRMEM1_201 = 0x20c90, + WRMEM1_202 = 0x20ca0, + WRMEM1_203 = 0x20cb0, + WRMEM1_204 = 0x20cc0, + WRMEM1_205 = 0x20cd0, + WRMEM1_206 = 0x20ce0, + WRMEM1_207 = 0x20cf0, + WRMEM1_208 = 0x20d00, + WRMEM1_209 = 0x20d10, + WRMEM1_210 = 0x20d20, + WRMEM1_211 = 0x20d30, + WRMEM1_212 = 0x20d40, + WRMEM1_213 = 0x20d50, + WRMEM1_214 = 0x20d60, + WRMEM1_215 = 0x20d70, + WRMEM1_216 = 0x20d80, + WRMEM1_217 = 0x20d90, + WRMEM1_218 = 0x20da0, + WRMEM1_219 = 0x20db0, + WRMEM1_220 = 0x20dc0, + WRMEM1_221 = 0x20dd0, + WRMEM1_222 = 0x20de0, + WRMEM1_223 = 0x20df0, + WRMEM1_224 = 0x20e00, + WRMEM1_225 = 0x20e10, + WRMEM1_226 = 0x20e20, + WRMEM1_227 = 0x20e30, + WRMEM1_228 = 0x20e40, + WRMEM1_229 = 0x20e50, + WRMEM1_230 = 0x20e60, + WRMEM1_231 = 0x20e70, + WRMEM1_232 = 0x20e80, + WRMEM1_233 = 0x20e90, + WRMEM1_234 = 0x20ea0, + WRMEM1_235 = 0x20eb0, + WRMEM1_236 = 0x20ec0, + WRMEM1_237 = 0x20ed0, + WRMEM1_238 = 0x20ee0, + WRMEM1_239 = 0x20ef0, + WRMEM1_240 = 0x20f00, + WRMEM1_241 = 0x20f10, + WRMEM1_242 = 0x20f20, + WRMEM1_243 = 0x20f30, + WRMEM1_244 = 0x20f40, + WRMEM1_245 = 0x20f50, + WRMEM1_246 = 0x20f60, + WRMEM1_247 = 0x20f70, + WRMEM1_248 = 0x20f80, + WRMEM1_249 = 0x20f90, + WRMEM1_250 = 0x20fa0, + WRMEM1_251 = 0x20fb0, + WRMEM1_252 = 0x20fc0, + WRMEM1_253 = 0x20fd0, + WRMEM1_254 = 0x20fe0, + WRMEM1_255 = 0x20ff0, + WRMEM1_256 = 0x21000, + WRMEM1_257 = 0x21010, + WRMEM1_258 = 0x21020, + WRMEM1_259 = 0x21030, + WRMEM1_260 = 0x21040, + WRMEM1_261 = 0x21050, + WRMEM1_262 = 0x21060, + WRMEM1_263 = 0x21070, + WRMEM1_264 = 0x21080, + WRMEM1_265 = 0x21090, + WRMEM1_266 = 0x210a0, + WRMEM1_267 = 0x210b0, + WRMEM1_268 = 0x210c0, + WRMEM1_269 = 0x210d0, + WRMEM1_270 = 0x210e0, + WRMEM1_271 = 0x210f0, + WRMEM1_272 = 0x21100, + WRMEM1_273 = 0x21110, + WRMEM1_274 = 0x21120, + WRMEM1_275 = 0x21130, + WRMEM1_276 = 0x21140, + WRMEM1_277 = 0x21150, + WRMEM1_278 = 0x21160, + WRMEM1_279 = 0x21170, + WRMEM1_280 = 0x21180, + WRMEM1_281 = 0x21190, + WRMEM1_282 = 0x211a0, + WRMEM1_283 = 0x211b0, + WRMEM1_284 = 0x211c0, + WRMEM1_285 = 0x211d0, + WRMEM1_286 = 0x211e0, + WRMEM1_287 = 0x211f0, + WRMEM1_288 = 0x21200, + WRMEM1_289 = 0x21210, + WRMEM1_290 = 0x21220, + WRMEM1_291 = 0x21230, + WRMEM1_292 = 0x21240, + WRMEM1_293 = 0x21250, + WRMEM1_294 = 0x21260, + WRMEM1_295 = 0x21270, + WRMEM1_296 = 0x21280, + WRMEM1_297 = 0x21290, + WRMEM1_298 = 0x212a0, + WRMEM1_299 = 0x212b0 +}; + +/* SR1 register fields */ +#define SR1_FLD1 GENMASK(31, 0) + +/* WR1 register fields */ +#define WR1_FLD1 GENMASK(15, 0) +#define WR1_FLD2 GENMASK(31, 16) +#define WR1_FLD3 GENMASK(47, 32) +#define WR1_FLD4 GENMASK(63, 48) +#define WR1_FLD5 GENMASK(79, 64) +#define WR1_FLD6 GENMASK(95, 80) +#define WR1_FLD7 GENMASK(111, 96) +#define WR1_FLD8 GENMASK(127, 112) + +/* SR_REPEAT1 register fields */ +#define SR_REPEAT1_FLD1 GENMASK(31, 0) + +/* SR_REPEAT2 register fields */ +#define SR_REPEAT2_FLD1 GENMASK(31, 0) + +/* SR_REPEAT3 register fields */ +#define SR_REPEAT3_FLD1 GENMASK(31, 0) + +/* SRMEM1_0 register fields */ +#define SRMEM1_0_FLD1 GENMASK(31, 0) + +/* SRMEM1_1 register fields */ +#define SRMEM1_1_FLD1 GENMASK(31, 0) + +/* SRMEM1_2 register fields */ +#define SRMEM1_2_FLD1 GENMASK(31, 0) + +/* SRMEM1_3 register fields */ +#define SRMEM1_3_FLD1 GENMASK(31, 0) + +/* SRMEM1_4 register fields */ +#define SRMEM1_4_FLD1 GENMASK(31, 0) + +/* SRMEM1_5 register fields */ +#define SRMEM1_5_FLD1 GENMASK(31, 0) + +/* SRMEM1_6 register fields */ +#define SRMEM1_6_FLD1 GENMASK(31, 0) + +/* SRMEM1_7 register fields */ +#define SRMEM1_7_FLD1 GENMASK(31, 0) + +/* SRMEM1_8 register fields */ +#define SRMEM1_8_FLD1 GENMASK(31, 0) + +/* SRMEM1_9 register fields */ +#define SRMEM1_9_FLD1 GENMASK(31, 0) + +/* SRMEM1_10 register fields */ +#define SRMEM1_10_FLD1 GENMASK(31, 0) + +/* SRMEM1_11 register fields */ +#define SRMEM1_11_FLD1 GENMASK(31, 0) + +/* SRMEM1_12 register fields */ +#define SRMEM1_12_FLD1 GENMASK(31, 0) + +/* SRMEM1_13 register fields */ +#define SRMEM1_13_FLD1 GENMASK(31, 0) + +/* SRMEM1_14 register fields */ +#define SRMEM1_14_FLD1 GENMASK(31, 0) + +/* SRMEM1_15 register fields */ +#define SRMEM1_15_FLD1 GENMASK(31, 0) + +/* SRMEM1_16 register fields */ +#define SRMEM1_16_FLD1 GENMASK(31, 0) + +/* SRMEM1_17 register fields */ +#define SRMEM1_17_FLD1 GENMASK(31, 0) + +/* SRMEM1_18 register fields */ +#define SRMEM1_18_FLD1 GENMASK(31, 0) + +/* SRMEM1_19 register fields */ +#define SRMEM1_19_FLD1 GENMASK(31, 0) + +/* SRMEM1_20 register fields */ +#define SRMEM1_20_FLD1 GENMASK(31, 0) + +/* SRMEM1_21 register fields */ +#define SRMEM1_21_FLD1 GENMASK(31, 0) + +/* SRMEM1_22 register fields */ +#define SRMEM1_22_FLD1 GENMASK(31, 0) + +/* SRMEM1_23 register fields */ +#define SRMEM1_23_FLD1 GENMASK(31, 0) + +/* SRMEM1_24 register fields */ +#define SRMEM1_24_FLD1 GENMASK(31, 0) + +/* SRMEM1_25 register fields */ +#define SRMEM1_25_FLD1 GENMASK(31, 0) + +/* SRMEM1_26 register fields */ +#define SRMEM1_26_FLD1 GENMASK(31, 0) + +/* SRMEM1_27 register fields */ +#define SRMEM1_27_FLD1 GENMASK(31, 0) + +/* SRMEM1_28 register fields */ +#define SRMEM1_28_FLD1 GENMASK(31, 0) + +/* SRMEM1_29 register fields */ +#define SRMEM1_29_FLD1 GENMASK(31, 0) + +/* SRMEM1_30 register fields */ +#define SRMEM1_30_FLD1 GENMASK(31, 0) + +/* SRMEM1_31 register fields */ +#define SRMEM1_31_FLD1 GENMASK(31, 0) + +/* SRMEM1_32 register fields */ +#define SRMEM1_32_FLD1 GENMASK(31, 0) + +/* SRMEM1_33 register fields */ +#define SRMEM1_33_FLD1 GENMASK(31, 0) + +/* SRMEM1_34 register fields */ +#define SRMEM1_34_FLD1 GENMASK(31, 0) + +/* SRMEM1_35 register fields */ +#define SRMEM1_35_FLD1 GENMASK(31, 0) + +/* SRMEM1_36 register fields */ +#define SRMEM1_36_FLD1 GENMASK(31, 0) + +/* SRMEM1_37 register fields */ +#define SRMEM1_37_FLD1 GENMASK(31, 0) + +/* SRMEM1_38 register fields */ +#define SRMEM1_38_FLD1 GENMASK(31, 0) + +/* SRMEM1_39 register fields */ +#define SRMEM1_39_FLD1 GENMASK(31, 0) + +/* SRMEM1_40 register fields */ +#define SRMEM1_40_FLD1 GENMASK(31, 0) + +/* SRMEM1_41 register fields */ +#define SRMEM1_41_FLD1 GENMASK(31, 0) + +/* SRMEM1_42 register fields */ +#define SRMEM1_42_FLD1 GENMASK(31, 0) + +/* SRMEM1_43 register fields */ +#define SRMEM1_43_FLD1 GENMASK(31, 0) + +/* SRMEM1_44 register fields */ +#define SRMEM1_44_FLD1 GENMASK(31, 0) + +/* SRMEM1_45 register fields */ +#define SRMEM1_45_FLD1 GENMASK(31, 0) + +/* SRMEM1_46 register fields */ +#define SRMEM1_46_FLD1 GENMASK(31, 0) + +/* SRMEM1_47 register fields */ +#define SRMEM1_47_FLD1 GENMASK(31, 0) + +/* SRMEM1_48 register fields */ +#define SRMEM1_48_FLD1 GENMASK(31, 0) + +/* SRMEM1_49 register fields */ +#define SRMEM1_49_FLD1 GENMASK(31, 0) + +/* SRMEM1_50 register fields */ +#define SRMEM1_50_FLD1 GENMASK(31, 0) + +/* SRMEM1_51 register fields */ +#define SRMEM1_51_FLD1 GENMASK(31, 0) + +/* SRMEM1_52 register fields */ +#define SRMEM1_52_FLD1 GENMASK(31, 0) + +/* SRMEM1_53 register fields */ +#define SRMEM1_53_FLD1 GENMASK(31, 0) + +/* SRMEM1_54 register fields */ +#define SRMEM1_54_FLD1 GENMASK(31, 0) + +/* SRMEM1_55 register fields */ +#define SRMEM1_55_FLD1 GENMASK(31, 0) + +/* SRMEM1_56 register fields */ +#define SRMEM1_56_FLD1 GENMASK(31, 0) + +/* SRMEM1_57 register fields */ +#define SRMEM1_57_FLD1 GENMASK(31, 0) + +/* SRMEM1_58 register fields */ +#define SRMEM1_58_FLD1 GENMASK(31, 0) + +/* SRMEM1_59 register fields */ +#define SRMEM1_59_FLD1 GENMASK(31, 0) + +/* SRMEM1_60 register fields */ +#define SRMEM1_60_FLD1 GENMASK(31, 0) + +/* SRMEM1_61 register fields */ +#define SRMEM1_61_FLD1 GENMASK(31, 0) + +/* SRMEM1_62 register fields */ +#define SRMEM1_62_FLD1 GENMASK(31, 0) + +/* SRMEM1_63 register fields */ +#define SRMEM1_63_FLD1 GENMASK(31, 0) + +/* SRMEM1_64 register fields */ +#define SRMEM1_64_FLD1 GENMASK(31, 0) + +/* SRMEM1_65 register fields */ +#define SRMEM1_65_FLD1 GENMASK(31, 0) + +/* SRMEM1_66 register fields */ +#define SRMEM1_66_FLD1 GENMASK(31, 0) + +/* SRMEM1_67 register fields */ +#define SRMEM1_67_FLD1 GENMASK(31, 0) + +/* SRMEM1_68 register fields */ +#define SRMEM1_68_FLD1 GENMASK(31, 0) + +/* SRMEM1_69 register fields */ +#define SRMEM1_69_FLD1 GENMASK(31, 0) + +/* SRMEM1_70 register fields */ +#define SRMEM1_70_FLD1 GENMASK(31, 0) + +/* SRMEM1_71 register fields */ +#define SRMEM1_71_FLD1 GENMASK(31, 0) + +/* SRMEM1_72 register fields */ +#define SRMEM1_72_FLD1 GENMASK(31, 0) + +/* SRMEM1_73 register fields */ +#define SRMEM1_73_FLD1 GENMASK(31, 0) + +/* SRMEM1_74 register fields */ +#define SRMEM1_74_FLD1 GENMASK(31, 0) + +/* SRMEM1_75 register fields */ +#define SRMEM1_75_FLD1 GENMASK(31, 0) + +/* SRMEM1_76 register fields */ +#define SRMEM1_76_FLD1 GENMASK(31, 0) + +/* SRMEM1_77 register fields */ +#define SRMEM1_77_FLD1 GENMASK(31, 0) + +/* SRMEM1_78 register fields */ +#define SRMEM1_78_FLD1 GENMASK(31, 0) + +/* SRMEM1_79 register fields */ +#define SRMEM1_79_FLD1 GENMASK(31, 0) + +/* SRMEM1_80 register fields */ +#define SRMEM1_80_FLD1 GENMASK(31, 0) + +/* SRMEM1_81 register fields */ +#define SRMEM1_81_FLD1 GENMASK(31, 0) + +/* SRMEM1_82 register fields */ +#define SRMEM1_82_FLD1 GENMASK(31, 0) + +/* SRMEM1_83 register fields */ +#define SRMEM1_83_FLD1 GENMASK(31, 0) + +/* SRMEM1_84 register fields */ +#define SRMEM1_84_FLD1 GENMASK(31, 0) + +/* SRMEM1_85 register fields */ +#define SRMEM1_85_FLD1 GENMASK(31, 0) + +/* SRMEM1_86 register fields */ +#define SRMEM1_86_FLD1 GENMASK(31, 0) + +/* SRMEM1_87 register fields */ +#define SRMEM1_87_FLD1 GENMASK(31, 0) + +/* SRMEM1_88 register fields */ +#define SRMEM1_88_FLD1 GENMASK(31, 0) + +/* SRMEM1_89 register fields */ +#define SRMEM1_89_FLD1 GENMASK(31, 0) + +/* SRMEM1_90 register fields */ +#define SRMEM1_90_FLD1 GENMASK(31, 0) + +/* SRMEM1_91 register fields */ +#define SRMEM1_91_FLD1 GENMASK(31, 0) + +/* SRMEM1_92 register fields */ +#define SRMEM1_92_FLD1 GENMASK(31, 0) + +/* SRMEM1_93 register fields */ +#define SRMEM1_93_FLD1 GENMASK(31, 0) + +/* SRMEM1_94 register fields */ +#define SRMEM1_94_FLD1 GENMASK(31, 0) + +/* SRMEM1_95 register fields */ +#define SRMEM1_95_FLD1 GENMASK(31, 0) + +/* SRMEM1_96 register fields */ +#define SRMEM1_96_FLD1 GENMASK(31, 0) + +/* SRMEM1_97 register fields */ +#define SRMEM1_97_FLD1 GENMASK(31, 0) + +/* SRMEM1_98 register fields */ +#define SRMEM1_98_FLD1 GENMASK(31, 0) + +/* SRMEM1_99 register fields */ +#define SRMEM1_99_FLD1 GENMASK(31, 0) + +/* WRMEM1_0 register fields */ +#define WRMEM1_0_FLD1 GENMASK(15, 0) +#define WRMEM1_0_FLD2 GENMASK(31, 16) +#define WRMEM1_0_FLD3 GENMASK(47, 32) +#define WRMEM1_0_FLD4 GENMASK(63, 48) +#define WRMEM1_0_FLD5 GENMASK(79, 64) +#define WRMEM1_0_FLD6 GENMASK(95, 80) +#define WRMEM1_0_FLD7 GENMASK(111, 96) +#define WRMEM1_0_FLD8 GENMASK(127, 112) + +/* WRMEM1_1 register fields */ +#define WRMEM1_1_FLD1 GENMASK(15, 0) +#define WRMEM1_1_FLD2 GENMASK(31, 16) +#define WRMEM1_1_FLD3 GENMASK(47, 32) +#define WRMEM1_1_FLD4 GENMASK(63, 48) +#define WRMEM1_1_FLD5 GENMASK(79, 64) +#define WRMEM1_1_FLD6 GENMASK(95, 80) +#define WRMEM1_1_FLD7 GENMASK(111, 96) +#define WRMEM1_1_FLD8 GENMASK(127, 112) + +/* WRMEM1_2 register fields */ +#define WRMEM1_2_FLD1 GENMASK(15, 0) +#define WRMEM1_2_FLD2 GENMASK(31, 16) +#define WRMEM1_2_FLD3 GENMASK(47, 32) +#define WRMEM1_2_FLD4 GENMASK(63, 48) +#define WRMEM1_2_FLD5 GENMASK(79, 64) +#define WRMEM1_2_FLD6 GENMASK(95, 80) +#define WRMEM1_2_FLD7 GENMASK(111, 96) +#define WRMEM1_2_FLD8 GENMASK(127, 112) + +/* WRMEM1_3 register fields */ +#define WRMEM1_3_FLD1 GENMASK(15, 0) +#define WRMEM1_3_FLD2 GENMASK(31, 16) +#define WRMEM1_3_FLD3 GENMASK(47, 32) +#define WRMEM1_3_FLD4 GENMASK(63, 48) +#define WRMEM1_3_FLD5 GENMASK(79, 64) +#define WRMEM1_3_FLD6 GENMASK(95, 80) +#define WRMEM1_3_FLD7 GENMASK(111, 96) +#define WRMEM1_3_FLD8 GENMASK(127, 112) + +/* WRMEM1_4 register fields */ +#define WRMEM1_4_FLD1 GENMASK(15, 0) +#define WRMEM1_4_FLD2 GENMASK(31, 16) +#define WRMEM1_4_FLD3 GENMASK(47, 32) +#define WRMEM1_4_FLD4 GENMASK(63, 48) +#define WRMEM1_4_FLD5 GENMASK(79, 64) +#define WRMEM1_4_FLD6 GENMASK(95, 80) +#define WRMEM1_4_FLD7 GENMASK(111, 96) +#define WRMEM1_4_FLD8 GENMASK(127, 112) + +/* WRMEM1_5 register fields */ +#define WRMEM1_5_FLD1 GENMASK(15, 0) +#define WRMEM1_5_FLD2 GENMASK(31, 16) +#define WRMEM1_5_FLD3 GENMASK(47, 32) +#define WRMEM1_5_FLD4 GENMASK(63, 48) +#define WRMEM1_5_FLD5 GENMASK(79, 64) +#define WRMEM1_5_FLD6 GENMASK(95, 80) +#define WRMEM1_5_FLD7 GENMASK(111, 96) +#define WRMEM1_5_FLD8 GENMASK(127, 112) + +/* WRMEM1_6 register fields */ +#define WRMEM1_6_FLD1 GENMASK(15, 0) +#define WRMEM1_6_FLD2 GENMASK(31, 16) +#define WRMEM1_6_FLD3 GENMASK(47, 32) +#define WRMEM1_6_FLD4 GENMASK(63, 48) +#define WRMEM1_6_FLD5 GENMASK(79, 64) +#define WRMEM1_6_FLD6 GENMASK(95, 80) +#define WRMEM1_6_FLD7 GENMASK(111, 96) +#define WRMEM1_6_FLD8 GENMASK(127, 112) + +/* WRMEM1_7 register fields */ +#define WRMEM1_7_FLD1 GENMASK(15, 0) +#define WRMEM1_7_FLD2 GENMASK(31, 16) +#define WRMEM1_7_FLD3 GENMASK(47, 32) +#define WRMEM1_7_FLD4 GENMASK(63, 48) +#define WRMEM1_7_FLD5 GENMASK(79, 64) +#define WRMEM1_7_FLD6 GENMASK(95, 80) +#define WRMEM1_7_FLD7 GENMASK(111, 96) +#define WRMEM1_7_FLD8 GENMASK(127, 112) + +/* WRMEM1_8 register fields */ +#define WRMEM1_8_FLD1 GENMASK(15, 0) +#define WRMEM1_8_FLD2 GENMASK(31, 16) +#define WRMEM1_8_FLD3 GENMASK(47, 32) +#define WRMEM1_8_FLD4 GENMASK(63, 48) +#define WRMEM1_8_FLD5 GENMASK(79, 64) +#define WRMEM1_8_FLD6 GENMASK(95, 80) +#define WRMEM1_8_FLD7 GENMASK(111, 96) +#define WRMEM1_8_FLD8 GENMASK(127, 112) + +/* WRMEM1_9 register fields */ +#define WRMEM1_9_FLD1 GENMASK(15, 0) +#define WRMEM1_9_FLD2 GENMASK(31, 16) +#define WRMEM1_9_FLD3 GENMASK(47, 32) +#define WRMEM1_9_FLD4 GENMASK(63, 48) +#define WRMEM1_9_FLD5 GENMASK(79, 64) +#define WRMEM1_9_FLD6 GENMASK(95, 80) +#define WRMEM1_9_FLD7 GENMASK(111, 96) +#define WRMEM1_9_FLD8 GENMASK(127, 112) + +/* WRMEM1_10 register fields */ +#define WRMEM1_10_FLD1 GENMASK(15, 0) +#define WRMEM1_10_FLD2 GENMASK(31, 16) +#define WRMEM1_10_FLD3 GENMASK(47, 32) +#define WRMEM1_10_FLD4 GENMASK(63, 48) +#define WRMEM1_10_FLD5 GENMASK(79, 64) +#define WRMEM1_10_FLD6 GENMASK(95, 80) +#define WRMEM1_10_FLD7 GENMASK(111, 96) +#define WRMEM1_10_FLD8 GENMASK(127, 112) + +/* WRMEM1_11 register fields */ +#define WRMEM1_11_FLD1 GENMASK(15, 0) +#define WRMEM1_11_FLD2 GENMASK(31, 16) +#define WRMEM1_11_FLD3 GENMASK(47, 32) +#define WRMEM1_11_FLD4 GENMASK(63, 48) +#define WRMEM1_11_FLD5 GENMASK(79, 64) +#define WRMEM1_11_FLD6 GENMASK(95, 80) +#define WRMEM1_11_FLD7 GENMASK(111, 96) +#define WRMEM1_11_FLD8 GENMASK(127, 112) + +/* WRMEM1_12 register fields */ +#define WRMEM1_12_FLD1 GENMASK(15, 0) +#define WRMEM1_12_FLD2 GENMASK(31, 16) +#define WRMEM1_12_FLD3 GENMASK(47, 32) +#define WRMEM1_12_FLD4 GENMASK(63, 48) +#define WRMEM1_12_FLD5 GENMASK(79, 64) +#define WRMEM1_12_FLD6 GENMASK(95, 80) +#define WRMEM1_12_FLD7 GENMASK(111, 96) +#define WRMEM1_12_FLD8 GENMASK(127, 112) + +/* WRMEM1_13 register fields */ +#define WRMEM1_13_FLD1 GENMASK(15, 0) +#define WRMEM1_13_FLD2 GENMASK(31, 16) +#define WRMEM1_13_FLD3 GENMASK(47, 32) +#define WRMEM1_13_FLD4 GENMASK(63, 48) +#define WRMEM1_13_FLD5 GENMASK(79, 64) +#define WRMEM1_13_FLD6 GENMASK(95, 80) +#define WRMEM1_13_FLD7 GENMASK(111, 96) +#define WRMEM1_13_FLD8 GENMASK(127, 112) + +/* WRMEM1_14 register fields */ +#define WRMEM1_14_FLD1 GENMASK(15, 0) +#define WRMEM1_14_FLD2 GENMASK(31, 16) +#define WRMEM1_14_FLD3 GENMASK(47, 32) +#define WRMEM1_14_FLD4 GENMASK(63, 48) +#define WRMEM1_14_FLD5 GENMASK(79, 64) +#define WRMEM1_14_FLD6 GENMASK(95, 80) +#define WRMEM1_14_FLD7 GENMASK(111, 96) +#define WRMEM1_14_FLD8 GENMASK(127, 112) + +/* WRMEM1_15 register fields */ +#define WRMEM1_15_FLD1 GENMASK(15, 0) +#define WRMEM1_15_FLD2 GENMASK(31, 16) +#define WRMEM1_15_FLD3 GENMASK(47, 32) +#define WRMEM1_15_FLD4 GENMASK(63, 48) +#define WRMEM1_15_FLD5 GENMASK(79, 64) +#define WRMEM1_15_FLD6 GENMASK(95, 80) +#define WRMEM1_15_FLD7 GENMASK(111, 96) +#define WRMEM1_15_FLD8 GENMASK(127, 112) + +/* WRMEM1_16 register fields */ +#define WRMEM1_16_FLD1 GENMASK(15, 0) +#define WRMEM1_16_FLD2 GENMASK(31, 16) +#define WRMEM1_16_FLD3 GENMASK(47, 32) +#define WRMEM1_16_FLD4 GENMASK(63, 48) +#define WRMEM1_16_FLD5 GENMASK(79, 64) +#define WRMEM1_16_FLD6 GENMASK(95, 80) +#define WRMEM1_16_FLD7 GENMASK(111, 96) +#define WRMEM1_16_FLD8 GENMASK(127, 112) + +/* WRMEM1_17 register fields */ +#define WRMEM1_17_FLD1 GENMASK(15, 0) +#define WRMEM1_17_FLD2 GENMASK(31, 16) +#define WRMEM1_17_FLD3 GENMASK(47, 32) +#define WRMEM1_17_FLD4 GENMASK(63, 48) +#define WRMEM1_17_FLD5 GENMASK(79, 64) +#define WRMEM1_17_FLD6 GENMASK(95, 80) +#define WRMEM1_17_FLD7 GENMASK(111, 96) +#define WRMEM1_17_FLD8 GENMASK(127, 112) + +/* WRMEM1_18 register fields */ +#define WRMEM1_18_FLD1 GENMASK(15, 0) +#define WRMEM1_18_FLD2 GENMASK(31, 16) +#define WRMEM1_18_FLD3 GENMASK(47, 32) +#define WRMEM1_18_FLD4 GENMASK(63, 48) +#define WRMEM1_18_FLD5 GENMASK(79, 64) +#define WRMEM1_18_FLD6 GENMASK(95, 80) +#define WRMEM1_18_FLD7 GENMASK(111, 96) +#define WRMEM1_18_FLD8 GENMASK(127, 112) + +/* WRMEM1_19 register fields */ +#define WRMEM1_19_FLD1 GENMASK(15, 0) +#define WRMEM1_19_FLD2 GENMASK(31, 16) +#define WRMEM1_19_FLD3 GENMASK(47, 32) +#define WRMEM1_19_FLD4 GENMASK(63, 48) +#define WRMEM1_19_FLD5 GENMASK(79, 64) +#define WRMEM1_19_FLD6 GENMASK(95, 80) +#define WRMEM1_19_FLD7 GENMASK(111, 96) +#define WRMEM1_19_FLD8 GENMASK(127, 112) + +/* WRMEM1_20 register fields */ +#define WRMEM1_20_FLD1 GENMASK(15, 0) +#define WRMEM1_20_FLD2 GENMASK(31, 16) +#define WRMEM1_20_FLD3 GENMASK(47, 32) +#define WRMEM1_20_FLD4 GENMASK(63, 48) +#define WRMEM1_20_FLD5 GENMASK(79, 64) +#define WRMEM1_20_FLD6 GENMASK(95, 80) +#define WRMEM1_20_FLD7 GENMASK(111, 96) +#define WRMEM1_20_FLD8 GENMASK(127, 112) + +/* WRMEM1_21 register fields */ +#define WRMEM1_21_FLD1 GENMASK(15, 0) +#define WRMEM1_21_FLD2 GENMASK(31, 16) +#define WRMEM1_21_FLD3 GENMASK(47, 32) +#define WRMEM1_21_FLD4 GENMASK(63, 48) +#define WRMEM1_21_FLD5 GENMASK(79, 64) +#define WRMEM1_21_FLD6 GENMASK(95, 80) +#define WRMEM1_21_FLD7 GENMASK(111, 96) +#define WRMEM1_21_FLD8 GENMASK(127, 112) + +/* WRMEM1_22 register fields */ +#define WRMEM1_22_FLD1 GENMASK(15, 0) +#define WRMEM1_22_FLD2 GENMASK(31, 16) +#define WRMEM1_22_FLD3 GENMASK(47, 32) +#define WRMEM1_22_FLD4 GENMASK(63, 48) +#define WRMEM1_22_FLD5 GENMASK(79, 64) +#define WRMEM1_22_FLD6 GENMASK(95, 80) +#define WRMEM1_22_FLD7 GENMASK(111, 96) +#define WRMEM1_22_FLD8 GENMASK(127, 112) + +/* WRMEM1_23 register fields */ +#define WRMEM1_23_FLD1 GENMASK(15, 0) +#define WRMEM1_23_FLD2 GENMASK(31, 16) +#define WRMEM1_23_FLD3 GENMASK(47, 32) +#define WRMEM1_23_FLD4 GENMASK(63, 48) +#define WRMEM1_23_FLD5 GENMASK(79, 64) +#define WRMEM1_23_FLD6 GENMASK(95, 80) +#define WRMEM1_23_FLD7 GENMASK(111, 96) +#define WRMEM1_23_FLD8 GENMASK(127, 112) + +/* WRMEM1_24 register fields */ +#define WRMEM1_24_FLD1 GENMASK(15, 0) +#define WRMEM1_24_FLD2 GENMASK(31, 16) +#define WRMEM1_24_FLD3 GENMASK(47, 32) +#define WRMEM1_24_FLD4 GENMASK(63, 48) +#define WRMEM1_24_FLD5 GENMASK(79, 64) +#define WRMEM1_24_FLD6 GENMASK(95, 80) +#define WRMEM1_24_FLD7 GENMASK(111, 96) +#define WRMEM1_24_FLD8 GENMASK(127, 112) + +/* WRMEM1_25 register fields */ +#define WRMEM1_25_FLD1 GENMASK(15, 0) +#define WRMEM1_25_FLD2 GENMASK(31, 16) +#define WRMEM1_25_FLD3 GENMASK(47, 32) +#define WRMEM1_25_FLD4 GENMASK(63, 48) +#define WRMEM1_25_FLD5 GENMASK(79, 64) +#define WRMEM1_25_FLD6 GENMASK(95, 80) +#define WRMEM1_25_FLD7 GENMASK(111, 96) +#define WRMEM1_25_FLD8 GENMASK(127, 112) + +/* WRMEM1_26 register fields */ +#define WRMEM1_26_FLD1 GENMASK(15, 0) +#define WRMEM1_26_FLD2 GENMASK(31, 16) +#define WRMEM1_26_FLD3 GENMASK(47, 32) +#define WRMEM1_26_FLD4 GENMASK(63, 48) +#define WRMEM1_26_FLD5 GENMASK(79, 64) +#define WRMEM1_26_FLD6 GENMASK(95, 80) +#define WRMEM1_26_FLD7 GENMASK(111, 96) +#define WRMEM1_26_FLD8 GENMASK(127, 112) + +/* WRMEM1_27 register fields */ +#define WRMEM1_27_FLD1 GENMASK(15, 0) +#define WRMEM1_27_FLD2 GENMASK(31, 16) +#define WRMEM1_27_FLD3 GENMASK(47, 32) +#define WRMEM1_27_FLD4 GENMASK(63, 48) +#define WRMEM1_27_FLD5 GENMASK(79, 64) +#define WRMEM1_27_FLD6 GENMASK(95, 80) +#define WRMEM1_27_FLD7 GENMASK(111, 96) +#define WRMEM1_27_FLD8 GENMASK(127, 112) + +/* WRMEM1_28 register fields */ +#define WRMEM1_28_FLD1 GENMASK(15, 0) +#define WRMEM1_28_FLD2 GENMASK(31, 16) +#define WRMEM1_28_FLD3 GENMASK(47, 32) +#define WRMEM1_28_FLD4 GENMASK(63, 48) +#define WRMEM1_28_FLD5 GENMASK(79, 64) +#define WRMEM1_28_FLD6 GENMASK(95, 80) +#define WRMEM1_28_FLD7 GENMASK(111, 96) +#define WRMEM1_28_FLD8 GENMASK(127, 112) + +/* WRMEM1_29 register fields */ +#define WRMEM1_29_FLD1 GENMASK(15, 0) +#define WRMEM1_29_FLD2 GENMASK(31, 16) +#define WRMEM1_29_FLD3 GENMASK(47, 32) +#define WRMEM1_29_FLD4 GENMASK(63, 48) +#define WRMEM1_29_FLD5 GENMASK(79, 64) +#define WRMEM1_29_FLD6 GENMASK(95, 80) +#define WRMEM1_29_FLD7 GENMASK(111, 96) +#define WRMEM1_29_FLD8 GENMASK(127, 112) + +/* WRMEM1_30 register fields */ +#define WRMEM1_30_FLD1 GENMASK(15, 0) +#define WRMEM1_30_FLD2 GENMASK(31, 16) +#define WRMEM1_30_FLD3 GENMASK(47, 32) +#define WRMEM1_30_FLD4 GENMASK(63, 48) +#define WRMEM1_30_FLD5 GENMASK(79, 64) +#define WRMEM1_30_FLD6 GENMASK(95, 80) +#define WRMEM1_30_FLD7 GENMASK(111, 96) +#define WRMEM1_30_FLD8 GENMASK(127, 112) + +/* WRMEM1_31 register fields */ +#define WRMEM1_31_FLD1 GENMASK(15, 0) +#define WRMEM1_31_FLD2 GENMASK(31, 16) +#define WRMEM1_31_FLD3 GENMASK(47, 32) +#define WRMEM1_31_FLD4 GENMASK(63, 48) +#define WRMEM1_31_FLD5 GENMASK(79, 64) +#define WRMEM1_31_FLD6 GENMASK(95, 80) +#define WRMEM1_31_FLD7 GENMASK(111, 96) +#define WRMEM1_31_FLD8 GENMASK(127, 112) + +/* WRMEM1_32 register fields */ +#define WRMEM1_32_FLD1 GENMASK(15, 0) +#define WRMEM1_32_FLD2 GENMASK(31, 16) +#define WRMEM1_32_FLD3 GENMASK(47, 32) +#define WRMEM1_32_FLD4 GENMASK(63, 48) +#define WRMEM1_32_FLD5 GENMASK(79, 64) +#define WRMEM1_32_FLD6 GENMASK(95, 80) +#define WRMEM1_32_FLD7 GENMASK(111, 96) +#define WRMEM1_32_FLD8 GENMASK(127, 112) + +/* WRMEM1_33 register fields */ +#define WRMEM1_33_FLD1 GENMASK(15, 0) +#define WRMEM1_33_FLD2 GENMASK(31, 16) +#define WRMEM1_33_FLD3 GENMASK(47, 32) +#define WRMEM1_33_FLD4 GENMASK(63, 48) +#define WRMEM1_33_FLD5 GENMASK(79, 64) +#define WRMEM1_33_FLD6 GENMASK(95, 80) +#define WRMEM1_33_FLD7 GENMASK(111, 96) +#define WRMEM1_33_FLD8 GENMASK(127, 112) + +/* WRMEM1_34 register fields */ +#define WRMEM1_34_FLD1 GENMASK(15, 0) +#define WRMEM1_34_FLD2 GENMASK(31, 16) +#define WRMEM1_34_FLD3 GENMASK(47, 32) +#define WRMEM1_34_FLD4 GENMASK(63, 48) +#define WRMEM1_34_FLD5 GENMASK(79, 64) +#define WRMEM1_34_FLD6 GENMASK(95, 80) +#define WRMEM1_34_FLD7 GENMASK(111, 96) +#define WRMEM1_34_FLD8 GENMASK(127, 112) + +/* WRMEM1_35 register fields */ +#define WRMEM1_35_FLD1 GENMASK(15, 0) +#define WRMEM1_35_FLD2 GENMASK(31, 16) +#define WRMEM1_35_FLD3 GENMASK(47, 32) +#define WRMEM1_35_FLD4 GENMASK(63, 48) +#define WRMEM1_35_FLD5 GENMASK(79, 64) +#define WRMEM1_35_FLD6 GENMASK(95, 80) +#define WRMEM1_35_FLD7 GENMASK(111, 96) +#define WRMEM1_35_FLD8 GENMASK(127, 112) + +/* WRMEM1_36 register fields */ +#define WRMEM1_36_FLD1 GENMASK(15, 0) +#define WRMEM1_36_FLD2 GENMASK(31, 16) +#define WRMEM1_36_FLD3 GENMASK(47, 32) +#define WRMEM1_36_FLD4 GENMASK(63, 48) +#define WRMEM1_36_FLD5 GENMASK(79, 64) +#define WRMEM1_36_FLD6 GENMASK(95, 80) +#define WRMEM1_36_FLD7 GENMASK(111, 96) +#define WRMEM1_36_FLD8 GENMASK(127, 112) + +/* WRMEM1_37 register fields */ +#define WRMEM1_37_FLD1 GENMASK(15, 0) +#define WRMEM1_37_FLD2 GENMASK(31, 16) +#define WRMEM1_37_FLD3 GENMASK(47, 32) +#define WRMEM1_37_FLD4 GENMASK(63, 48) +#define WRMEM1_37_FLD5 GENMASK(79, 64) +#define WRMEM1_37_FLD6 GENMASK(95, 80) +#define WRMEM1_37_FLD7 GENMASK(111, 96) +#define WRMEM1_37_FLD8 GENMASK(127, 112) + +/* WRMEM1_38 register fields */ +#define WRMEM1_38_FLD1 GENMASK(15, 0) +#define WRMEM1_38_FLD2 GENMASK(31, 16) +#define WRMEM1_38_FLD3 GENMASK(47, 32) +#define WRMEM1_38_FLD4 GENMASK(63, 48) +#define WRMEM1_38_FLD5 GENMASK(79, 64) +#define WRMEM1_38_FLD6 GENMASK(95, 80) +#define WRMEM1_38_FLD7 GENMASK(111, 96) +#define WRMEM1_38_FLD8 GENMASK(127, 112) + +/* WRMEM1_39 register fields */ +#define WRMEM1_39_FLD1 GENMASK(15, 0) +#define WRMEM1_39_FLD2 GENMASK(31, 16) +#define WRMEM1_39_FLD3 GENMASK(47, 32) +#define WRMEM1_39_FLD4 GENMASK(63, 48) +#define WRMEM1_39_FLD5 GENMASK(79, 64) +#define WRMEM1_39_FLD6 GENMASK(95, 80) +#define WRMEM1_39_FLD7 GENMASK(111, 96) +#define WRMEM1_39_FLD8 GENMASK(127, 112) + +/* WRMEM1_40 register fields */ +#define WRMEM1_40_FLD1 GENMASK(15, 0) +#define WRMEM1_40_FLD2 GENMASK(31, 16) +#define WRMEM1_40_FLD3 GENMASK(47, 32) +#define WRMEM1_40_FLD4 GENMASK(63, 48) +#define WRMEM1_40_FLD5 GENMASK(79, 64) +#define WRMEM1_40_FLD6 GENMASK(95, 80) +#define WRMEM1_40_FLD7 GENMASK(111, 96) +#define WRMEM1_40_FLD8 GENMASK(127, 112) + +/* WRMEM1_41 register fields */ +#define WRMEM1_41_FLD1 GENMASK(15, 0) +#define WRMEM1_41_FLD2 GENMASK(31, 16) +#define WRMEM1_41_FLD3 GENMASK(47, 32) +#define WRMEM1_41_FLD4 GENMASK(63, 48) +#define WRMEM1_41_FLD5 GENMASK(79, 64) +#define WRMEM1_41_FLD6 GENMASK(95, 80) +#define WRMEM1_41_FLD7 GENMASK(111, 96) +#define WRMEM1_41_FLD8 GENMASK(127, 112) + +/* WRMEM1_42 register fields */ +#define WRMEM1_42_FLD1 GENMASK(15, 0) +#define WRMEM1_42_FLD2 GENMASK(31, 16) +#define WRMEM1_42_FLD3 GENMASK(47, 32) +#define WRMEM1_42_FLD4 GENMASK(63, 48) +#define WRMEM1_42_FLD5 GENMASK(79, 64) +#define WRMEM1_42_FLD6 GENMASK(95, 80) +#define WRMEM1_42_FLD7 GENMASK(111, 96) +#define WRMEM1_42_FLD8 GENMASK(127, 112) + +/* WRMEM1_43 register fields */ +#define WRMEM1_43_FLD1 GENMASK(15, 0) +#define WRMEM1_43_FLD2 GENMASK(31, 16) +#define WRMEM1_43_FLD3 GENMASK(47, 32) +#define WRMEM1_43_FLD4 GENMASK(63, 48) +#define WRMEM1_43_FLD5 GENMASK(79, 64) +#define WRMEM1_43_FLD6 GENMASK(95, 80) +#define WRMEM1_43_FLD7 GENMASK(111, 96) +#define WRMEM1_43_FLD8 GENMASK(127, 112) + +/* WRMEM1_44 register fields */ +#define WRMEM1_44_FLD1 GENMASK(15, 0) +#define WRMEM1_44_FLD2 GENMASK(31, 16) +#define WRMEM1_44_FLD3 GENMASK(47, 32) +#define WRMEM1_44_FLD4 GENMASK(63, 48) +#define WRMEM1_44_FLD5 GENMASK(79, 64) +#define WRMEM1_44_FLD6 GENMASK(95, 80) +#define WRMEM1_44_FLD7 GENMASK(111, 96) +#define WRMEM1_44_FLD8 GENMASK(127, 112) + +/* WRMEM1_45 register fields */ +#define WRMEM1_45_FLD1 GENMASK(15, 0) +#define WRMEM1_45_FLD2 GENMASK(31, 16) +#define WRMEM1_45_FLD3 GENMASK(47, 32) +#define WRMEM1_45_FLD4 GENMASK(63, 48) +#define WRMEM1_45_FLD5 GENMASK(79, 64) +#define WRMEM1_45_FLD6 GENMASK(95, 80) +#define WRMEM1_45_FLD7 GENMASK(111, 96) +#define WRMEM1_45_FLD8 GENMASK(127, 112) + +/* WRMEM1_46 register fields */ +#define WRMEM1_46_FLD1 GENMASK(15, 0) +#define WRMEM1_46_FLD2 GENMASK(31, 16) +#define WRMEM1_46_FLD3 GENMASK(47, 32) +#define WRMEM1_46_FLD4 GENMASK(63, 48) +#define WRMEM1_46_FLD5 GENMASK(79, 64) +#define WRMEM1_46_FLD6 GENMASK(95, 80) +#define WRMEM1_46_FLD7 GENMASK(111, 96) +#define WRMEM1_46_FLD8 GENMASK(127, 112) + +/* WRMEM1_47 register fields */ +#define WRMEM1_47_FLD1 GENMASK(15, 0) +#define WRMEM1_47_FLD2 GENMASK(31, 16) +#define WRMEM1_47_FLD3 GENMASK(47, 32) +#define WRMEM1_47_FLD4 GENMASK(63, 48) +#define WRMEM1_47_FLD5 GENMASK(79, 64) +#define WRMEM1_47_FLD6 GENMASK(95, 80) +#define WRMEM1_47_FLD7 GENMASK(111, 96) +#define WRMEM1_47_FLD8 GENMASK(127, 112) + +/* WRMEM1_48 register fields */ +#define WRMEM1_48_FLD1 GENMASK(15, 0) +#define WRMEM1_48_FLD2 GENMASK(31, 16) +#define WRMEM1_48_FLD3 GENMASK(47, 32) +#define WRMEM1_48_FLD4 GENMASK(63, 48) +#define WRMEM1_48_FLD5 GENMASK(79, 64) +#define WRMEM1_48_FLD6 GENMASK(95, 80) +#define WRMEM1_48_FLD7 GENMASK(111, 96) +#define WRMEM1_48_FLD8 GENMASK(127, 112) + +/* WRMEM1_49 register fields */ +#define WRMEM1_49_FLD1 GENMASK(15, 0) +#define WRMEM1_49_FLD2 GENMASK(31, 16) +#define WRMEM1_49_FLD3 GENMASK(47, 32) +#define WRMEM1_49_FLD4 GENMASK(63, 48) +#define WRMEM1_49_FLD5 GENMASK(79, 64) +#define WRMEM1_49_FLD6 GENMASK(95, 80) +#define WRMEM1_49_FLD7 GENMASK(111, 96) +#define WRMEM1_49_FLD8 GENMASK(127, 112) + +/* WRMEM1_50 register fields */ +#define WRMEM1_50_FLD1 GENMASK(15, 0) +#define WRMEM1_50_FLD2 GENMASK(31, 16) +#define WRMEM1_50_FLD3 GENMASK(47, 32) +#define WRMEM1_50_FLD4 GENMASK(63, 48) +#define WRMEM1_50_FLD5 GENMASK(79, 64) +#define WRMEM1_50_FLD6 GENMASK(95, 80) +#define WRMEM1_50_FLD7 GENMASK(111, 96) +#define WRMEM1_50_FLD8 GENMASK(127, 112) + +/* WRMEM1_51 register fields */ +#define WRMEM1_51_FLD1 GENMASK(15, 0) +#define WRMEM1_51_FLD2 GENMASK(31, 16) +#define WRMEM1_51_FLD3 GENMASK(47, 32) +#define WRMEM1_51_FLD4 GENMASK(63, 48) +#define WRMEM1_51_FLD5 GENMASK(79, 64) +#define WRMEM1_51_FLD6 GENMASK(95, 80) +#define WRMEM1_51_FLD7 GENMASK(111, 96) +#define WRMEM1_51_FLD8 GENMASK(127, 112) + +/* WRMEM1_52 register fields */ +#define WRMEM1_52_FLD1 GENMASK(15, 0) +#define WRMEM1_52_FLD2 GENMASK(31, 16) +#define WRMEM1_52_FLD3 GENMASK(47, 32) +#define WRMEM1_52_FLD4 GENMASK(63, 48) +#define WRMEM1_52_FLD5 GENMASK(79, 64) +#define WRMEM1_52_FLD6 GENMASK(95, 80) +#define WRMEM1_52_FLD7 GENMASK(111, 96) +#define WRMEM1_52_FLD8 GENMASK(127, 112) + +/* WRMEM1_53 register fields */ +#define WRMEM1_53_FLD1 GENMASK(15, 0) +#define WRMEM1_53_FLD2 GENMASK(31, 16) +#define WRMEM1_53_FLD3 GENMASK(47, 32) +#define WRMEM1_53_FLD4 GENMASK(63, 48) +#define WRMEM1_53_FLD5 GENMASK(79, 64) +#define WRMEM1_53_FLD6 GENMASK(95, 80) +#define WRMEM1_53_FLD7 GENMASK(111, 96) +#define WRMEM1_53_FLD8 GENMASK(127, 112) + +/* WRMEM1_54 register fields */ +#define WRMEM1_54_FLD1 GENMASK(15, 0) +#define WRMEM1_54_FLD2 GENMASK(31, 16) +#define WRMEM1_54_FLD3 GENMASK(47, 32) +#define WRMEM1_54_FLD4 GENMASK(63, 48) +#define WRMEM1_54_FLD5 GENMASK(79, 64) +#define WRMEM1_54_FLD6 GENMASK(95, 80) +#define WRMEM1_54_FLD7 GENMASK(111, 96) +#define WRMEM1_54_FLD8 GENMASK(127, 112) + +/* WRMEM1_55 register fields */ +#define WRMEM1_55_FLD1 GENMASK(15, 0) +#define WRMEM1_55_FLD2 GENMASK(31, 16) +#define WRMEM1_55_FLD3 GENMASK(47, 32) +#define WRMEM1_55_FLD4 GENMASK(63, 48) +#define WRMEM1_55_FLD5 GENMASK(79, 64) +#define WRMEM1_55_FLD6 GENMASK(95, 80) +#define WRMEM1_55_FLD7 GENMASK(111, 96) +#define WRMEM1_55_FLD8 GENMASK(127, 112) + +/* WRMEM1_56 register fields */ +#define WRMEM1_56_FLD1 GENMASK(15, 0) +#define WRMEM1_56_FLD2 GENMASK(31, 16) +#define WRMEM1_56_FLD3 GENMASK(47, 32) +#define WRMEM1_56_FLD4 GENMASK(63, 48) +#define WRMEM1_56_FLD5 GENMASK(79, 64) +#define WRMEM1_56_FLD6 GENMASK(95, 80) +#define WRMEM1_56_FLD7 GENMASK(111, 96) +#define WRMEM1_56_FLD8 GENMASK(127, 112) + +/* WRMEM1_57 register fields */ +#define WRMEM1_57_FLD1 GENMASK(15, 0) +#define WRMEM1_57_FLD2 GENMASK(31, 16) +#define WRMEM1_57_FLD3 GENMASK(47, 32) +#define WRMEM1_57_FLD4 GENMASK(63, 48) +#define WRMEM1_57_FLD5 GENMASK(79, 64) +#define WRMEM1_57_FLD6 GENMASK(95, 80) +#define WRMEM1_57_FLD7 GENMASK(111, 96) +#define WRMEM1_57_FLD8 GENMASK(127, 112) + +/* WRMEM1_58 register fields */ +#define WRMEM1_58_FLD1 GENMASK(15, 0) +#define WRMEM1_58_FLD2 GENMASK(31, 16) +#define WRMEM1_58_FLD3 GENMASK(47, 32) +#define WRMEM1_58_FLD4 GENMASK(63, 48) +#define WRMEM1_58_FLD5 GENMASK(79, 64) +#define WRMEM1_58_FLD6 GENMASK(95, 80) +#define WRMEM1_58_FLD7 GENMASK(111, 96) +#define WRMEM1_58_FLD8 GENMASK(127, 112) + +/* WRMEM1_59 register fields */ +#define WRMEM1_59_FLD1 GENMASK(15, 0) +#define WRMEM1_59_FLD2 GENMASK(31, 16) +#define WRMEM1_59_FLD3 GENMASK(47, 32) +#define WRMEM1_59_FLD4 GENMASK(63, 48) +#define WRMEM1_59_FLD5 GENMASK(79, 64) +#define WRMEM1_59_FLD6 GENMASK(95, 80) +#define WRMEM1_59_FLD7 GENMASK(111, 96) +#define WRMEM1_59_FLD8 GENMASK(127, 112) + +/* WRMEM1_60 register fields */ +#define WRMEM1_60_FLD1 GENMASK(15, 0) +#define WRMEM1_60_FLD2 GENMASK(31, 16) +#define WRMEM1_60_FLD3 GENMASK(47, 32) +#define WRMEM1_60_FLD4 GENMASK(63, 48) +#define WRMEM1_60_FLD5 GENMASK(79, 64) +#define WRMEM1_60_FLD6 GENMASK(95, 80) +#define WRMEM1_60_FLD7 GENMASK(111, 96) +#define WRMEM1_60_FLD8 GENMASK(127, 112) + +/* WRMEM1_61 register fields */ +#define WRMEM1_61_FLD1 GENMASK(15, 0) +#define WRMEM1_61_FLD2 GENMASK(31, 16) +#define WRMEM1_61_FLD3 GENMASK(47, 32) +#define WRMEM1_61_FLD4 GENMASK(63, 48) +#define WRMEM1_61_FLD5 GENMASK(79, 64) +#define WRMEM1_61_FLD6 GENMASK(95, 80) +#define WRMEM1_61_FLD7 GENMASK(111, 96) +#define WRMEM1_61_FLD8 GENMASK(127, 112) + +/* WRMEM1_62 register fields */ +#define WRMEM1_62_FLD1 GENMASK(15, 0) +#define WRMEM1_62_FLD2 GENMASK(31, 16) +#define WRMEM1_62_FLD3 GENMASK(47, 32) +#define WRMEM1_62_FLD4 GENMASK(63, 48) +#define WRMEM1_62_FLD5 GENMASK(79, 64) +#define WRMEM1_62_FLD6 GENMASK(95, 80) +#define WRMEM1_62_FLD7 GENMASK(111, 96) +#define WRMEM1_62_FLD8 GENMASK(127, 112) + +/* WRMEM1_63 register fields */ +#define WRMEM1_63_FLD1 GENMASK(15, 0) +#define WRMEM1_63_FLD2 GENMASK(31, 16) +#define WRMEM1_63_FLD3 GENMASK(47, 32) +#define WRMEM1_63_FLD4 GENMASK(63, 48) +#define WRMEM1_63_FLD5 GENMASK(79, 64) +#define WRMEM1_63_FLD6 GENMASK(95, 80) +#define WRMEM1_63_FLD7 GENMASK(111, 96) +#define WRMEM1_63_FLD8 GENMASK(127, 112) + +/* WRMEM1_64 register fields */ +#define WRMEM1_64_FLD1 GENMASK(15, 0) +#define WRMEM1_64_FLD2 GENMASK(31, 16) +#define WRMEM1_64_FLD3 GENMASK(47, 32) +#define WRMEM1_64_FLD4 GENMASK(63, 48) +#define WRMEM1_64_FLD5 GENMASK(79, 64) +#define WRMEM1_64_FLD6 GENMASK(95, 80) +#define WRMEM1_64_FLD7 GENMASK(111, 96) +#define WRMEM1_64_FLD8 GENMASK(127, 112) + +/* WRMEM1_65 register fields */ +#define WRMEM1_65_FLD1 GENMASK(15, 0) +#define WRMEM1_65_FLD2 GENMASK(31, 16) +#define WRMEM1_65_FLD3 GENMASK(47, 32) +#define WRMEM1_65_FLD4 GENMASK(63, 48) +#define WRMEM1_65_FLD5 GENMASK(79, 64) +#define WRMEM1_65_FLD6 GENMASK(95, 80) +#define WRMEM1_65_FLD7 GENMASK(111, 96) +#define WRMEM1_65_FLD8 GENMASK(127, 112) + +/* WRMEM1_66 register fields */ +#define WRMEM1_66_FLD1 GENMASK(15, 0) +#define WRMEM1_66_FLD2 GENMASK(31, 16) +#define WRMEM1_66_FLD3 GENMASK(47, 32) +#define WRMEM1_66_FLD4 GENMASK(63, 48) +#define WRMEM1_66_FLD5 GENMASK(79, 64) +#define WRMEM1_66_FLD6 GENMASK(95, 80) +#define WRMEM1_66_FLD7 GENMASK(111, 96) +#define WRMEM1_66_FLD8 GENMASK(127, 112) + +/* WRMEM1_67 register fields */ +#define WRMEM1_67_FLD1 GENMASK(15, 0) +#define WRMEM1_67_FLD2 GENMASK(31, 16) +#define WRMEM1_67_FLD3 GENMASK(47, 32) +#define WRMEM1_67_FLD4 GENMASK(63, 48) +#define WRMEM1_67_FLD5 GENMASK(79, 64) +#define WRMEM1_67_FLD6 GENMASK(95, 80) +#define WRMEM1_67_FLD7 GENMASK(111, 96) +#define WRMEM1_67_FLD8 GENMASK(127, 112) + +/* WRMEM1_68 register fields */ +#define WRMEM1_68_FLD1 GENMASK(15, 0) +#define WRMEM1_68_FLD2 GENMASK(31, 16) +#define WRMEM1_68_FLD3 GENMASK(47, 32) +#define WRMEM1_68_FLD4 GENMASK(63, 48) +#define WRMEM1_68_FLD5 GENMASK(79, 64) +#define WRMEM1_68_FLD6 GENMASK(95, 80) +#define WRMEM1_68_FLD7 GENMASK(111, 96) +#define WRMEM1_68_FLD8 GENMASK(127, 112) + +/* WRMEM1_69 register fields */ +#define WRMEM1_69_FLD1 GENMASK(15, 0) +#define WRMEM1_69_FLD2 GENMASK(31, 16) +#define WRMEM1_69_FLD3 GENMASK(47, 32) +#define WRMEM1_69_FLD4 GENMASK(63, 48) +#define WRMEM1_69_FLD5 GENMASK(79, 64) +#define WRMEM1_69_FLD6 GENMASK(95, 80) +#define WRMEM1_69_FLD7 GENMASK(111, 96) +#define WRMEM1_69_FLD8 GENMASK(127, 112) + +/* WRMEM1_70 register fields */ +#define WRMEM1_70_FLD1 GENMASK(15, 0) +#define WRMEM1_70_FLD2 GENMASK(31, 16) +#define WRMEM1_70_FLD3 GENMASK(47, 32) +#define WRMEM1_70_FLD4 GENMASK(63, 48) +#define WRMEM1_70_FLD5 GENMASK(79, 64) +#define WRMEM1_70_FLD6 GENMASK(95, 80) +#define WRMEM1_70_FLD7 GENMASK(111, 96) +#define WRMEM1_70_FLD8 GENMASK(127, 112) + +/* WRMEM1_71 register fields */ +#define WRMEM1_71_FLD1 GENMASK(15, 0) +#define WRMEM1_71_FLD2 GENMASK(31, 16) +#define WRMEM1_71_FLD3 GENMASK(47, 32) +#define WRMEM1_71_FLD4 GENMASK(63, 48) +#define WRMEM1_71_FLD5 GENMASK(79, 64) +#define WRMEM1_71_FLD6 GENMASK(95, 80) +#define WRMEM1_71_FLD7 GENMASK(111, 96) +#define WRMEM1_71_FLD8 GENMASK(127, 112) + +/* WRMEM1_72 register fields */ +#define WRMEM1_72_FLD1 GENMASK(15, 0) +#define WRMEM1_72_FLD2 GENMASK(31, 16) +#define WRMEM1_72_FLD3 GENMASK(47, 32) +#define WRMEM1_72_FLD4 GENMASK(63, 48) +#define WRMEM1_72_FLD5 GENMASK(79, 64) +#define WRMEM1_72_FLD6 GENMASK(95, 80) +#define WRMEM1_72_FLD7 GENMASK(111, 96) +#define WRMEM1_72_FLD8 GENMASK(127, 112) + +/* WRMEM1_73 register fields */ +#define WRMEM1_73_FLD1 GENMASK(15, 0) +#define WRMEM1_73_FLD2 GENMASK(31, 16) +#define WRMEM1_73_FLD3 GENMASK(47, 32) +#define WRMEM1_73_FLD4 GENMASK(63, 48) +#define WRMEM1_73_FLD5 GENMASK(79, 64) +#define WRMEM1_73_FLD6 GENMASK(95, 80) +#define WRMEM1_73_FLD7 GENMASK(111, 96) +#define WRMEM1_73_FLD8 GENMASK(127, 112) + +/* WRMEM1_74 register fields */ +#define WRMEM1_74_FLD1 GENMASK(15, 0) +#define WRMEM1_74_FLD2 GENMASK(31, 16) +#define WRMEM1_74_FLD3 GENMASK(47, 32) +#define WRMEM1_74_FLD4 GENMASK(63, 48) +#define WRMEM1_74_FLD5 GENMASK(79, 64) +#define WRMEM1_74_FLD6 GENMASK(95, 80) +#define WRMEM1_74_FLD7 GENMASK(111, 96) +#define WRMEM1_74_FLD8 GENMASK(127, 112) + +/* WRMEM1_75 register fields */ +#define WRMEM1_75_FLD1 GENMASK(15, 0) +#define WRMEM1_75_FLD2 GENMASK(31, 16) +#define WRMEM1_75_FLD3 GENMASK(47, 32) +#define WRMEM1_75_FLD4 GENMASK(63, 48) +#define WRMEM1_75_FLD5 GENMASK(79, 64) +#define WRMEM1_75_FLD6 GENMASK(95, 80) +#define WRMEM1_75_FLD7 GENMASK(111, 96) +#define WRMEM1_75_FLD8 GENMASK(127, 112) + +/* WRMEM1_76 register fields */ +#define WRMEM1_76_FLD1 GENMASK(15, 0) +#define WRMEM1_76_FLD2 GENMASK(31, 16) +#define WRMEM1_76_FLD3 GENMASK(47, 32) +#define WRMEM1_76_FLD4 GENMASK(63, 48) +#define WRMEM1_76_FLD5 GENMASK(79, 64) +#define WRMEM1_76_FLD6 GENMASK(95, 80) +#define WRMEM1_76_FLD7 GENMASK(111, 96) +#define WRMEM1_76_FLD8 GENMASK(127, 112) + +/* WRMEM1_77 register fields */ +#define WRMEM1_77_FLD1 GENMASK(15, 0) +#define WRMEM1_77_FLD2 GENMASK(31, 16) +#define WRMEM1_77_FLD3 GENMASK(47, 32) +#define WRMEM1_77_FLD4 GENMASK(63, 48) +#define WRMEM1_77_FLD5 GENMASK(79, 64) +#define WRMEM1_77_FLD6 GENMASK(95, 80) +#define WRMEM1_77_FLD7 GENMASK(111, 96) +#define WRMEM1_77_FLD8 GENMASK(127, 112) + +/* WRMEM1_78 register fields */ +#define WRMEM1_78_FLD1 GENMASK(15, 0) +#define WRMEM1_78_FLD2 GENMASK(31, 16) +#define WRMEM1_78_FLD3 GENMASK(47, 32) +#define WRMEM1_78_FLD4 GENMASK(63, 48) +#define WRMEM1_78_FLD5 GENMASK(79, 64) +#define WRMEM1_78_FLD6 GENMASK(95, 80) +#define WRMEM1_78_FLD7 GENMASK(111, 96) +#define WRMEM1_78_FLD8 GENMASK(127, 112) + +/* WRMEM1_79 register fields */ +#define WRMEM1_79_FLD1 GENMASK(15, 0) +#define WRMEM1_79_FLD2 GENMASK(31, 16) +#define WRMEM1_79_FLD3 GENMASK(47, 32) +#define WRMEM1_79_FLD4 GENMASK(63, 48) +#define WRMEM1_79_FLD5 GENMASK(79, 64) +#define WRMEM1_79_FLD6 GENMASK(95, 80) +#define WRMEM1_79_FLD7 GENMASK(111, 96) +#define WRMEM1_79_FLD8 GENMASK(127, 112) + +/* WRMEM1_80 register fields */ +#define WRMEM1_80_FLD1 GENMASK(15, 0) +#define WRMEM1_80_FLD2 GENMASK(31, 16) +#define WRMEM1_80_FLD3 GENMASK(47, 32) +#define WRMEM1_80_FLD4 GENMASK(63, 48) +#define WRMEM1_80_FLD5 GENMASK(79, 64) +#define WRMEM1_80_FLD6 GENMASK(95, 80) +#define WRMEM1_80_FLD7 GENMASK(111, 96) +#define WRMEM1_80_FLD8 GENMASK(127, 112) + +/* WRMEM1_81 register fields */ +#define WRMEM1_81_FLD1 GENMASK(15, 0) +#define WRMEM1_81_FLD2 GENMASK(31, 16) +#define WRMEM1_81_FLD3 GENMASK(47, 32) +#define WRMEM1_81_FLD4 GENMASK(63, 48) +#define WRMEM1_81_FLD5 GENMASK(79, 64) +#define WRMEM1_81_FLD6 GENMASK(95, 80) +#define WRMEM1_81_FLD7 GENMASK(111, 96) +#define WRMEM1_81_FLD8 GENMASK(127, 112) + +/* WRMEM1_82 register fields */ +#define WRMEM1_82_FLD1 GENMASK(15, 0) +#define WRMEM1_82_FLD2 GENMASK(31, 16) +#define WRMEM1_82_FLD3 GENMASK(47, 32) +#define WRMEM1_82_FLD4 GENMASK(63, 48) +#define WRMEM1_82_FLD5 GENMASK(79, 64) +#define WRMEM1_82_FLD6 GENMASK(95, 80) +#define WRMEM1_82_FLD7 GENMASK(111, 96) +#define WRMEM1_82_FLD8 GENMASK(127, 112) + +/* WRMEM1_83 register fields */ +#define WRMEM1_83_FLD1 GENMASK(15, 0) +#define WRMEM1_83_FLD2 GENMASK(31, 16) +#define WRMEM1_83_FLD3 GENMASK(47, 32) +#define WRMEM1_83_FLD4 GENMASK(63, 48) +#define WRMEM1_83_FLD5 GENMASK(79, 64) +#define WRMEM1_83_FLD6 GENMASK(95, 80) +#define WRMEM1_83_FLD7 GENMASK(111, 96) +#define WRMEM1_83_FLD8 GENMASK(127, 112) + +/* WRMEM1_84 register fields */ +#define WRMEM1_84_FLD1 GENMASK(15, 0) +#define WRMEM1_84_FLD2 GENMASK(31, 16) +#define WRMEM1_84_FLD3 GENMASK(47, 32) +#define WRMEM1_84_FLD4 GENMASK(63, 48) +#define WRMEM1_84_FLD5 GENMASK(79, 64) +#define WRMEM1_84_FLD6 GENMASK(95, 80) +#define WRMEM1_84_FLD7 GENMASK(111, 96) +#define WRMEM1_84_FLD8 GENMASK(127, 112) + +/* WRMEM1_85 register fields */ +#define WRMEM1_85_FLD1 GENMASK(15, 0) +#define WRMEM1_85_FLD2 GENMASK(31, 16) +#define WRMEM1_85_FLD3 GENMASK(47, 32) +#define WRMEM1_85_FLD4 GENMASK(63, 48) +#define WRMEM1_85_FLD5 GENMASK(79, 64) +#define WRMEM1_85_FLD6 GENMASK(95, 80) +#define WRMEM1_85_FLD7 GENMASK(111, 96) +#define WRMEM1_85_FLD8 GENMASK(127, 112) + +/* WRMEM1_86 register fields */ +#define WRMEM1_86_FLD1 GENMASK(15, 0) +#define WRMEM1_86_FLD2 GENMASK(31, 16) +#define WRMEM1_86_FLD3 GENMASK(47, 32) +#define WRMEM1_86_FLD4 GENMASK(63, 48) +#define WRMEM1_86_FLD5 GENMASK(79, 64) +#define WRMEM1_86_FLD6 GENMASK(95, 80) +#define WRMEM1_86_FLD7 GENMASK(111, 96) +#define WRMEM1_86_FLD8 GENMASK(127, 112) + +/* WRMEM1_87 register fields */ +#define WRMEM1_87_FLD1 GENMASK(15, 0) +#define WRMEM1_87_FLD2 GENMASK(31, 16) +#define WRMEM1_87_FLD3 GENMASK(47, 32) +#define WRMEM1_87_FLD4 GENMASK(63, 48) +#define WRMEM1_87_FLD5 GENMASK(79, 64) +#define WRMEM1_87_FLD6 GENMASK(95, 80) +#define WRMEM1_87_FLD7 GENMASK(111, 96) +#define WRMEM1_87_FLD8 GENMASK(127, 112) + +/* WRMEM1_88 register fields */ +#define WRMEM1_88_FLD1 GENMASK(15, 0) +#define WRMEM1_88_FLD2 GENMASK(31, 16) +#define WRMEM1_88_FLD3 GENMASK(47, 32) +#define WRMEM1_88_FLD4 GENMASK(63, 48) +#define WRMEM1_88_FLD5 GENMASK(79, 64) +#define WRMEM1_88_FLD6 GENMASK(95, 80) +#define WRMEM1_88_FLD7 GENMASK(111, 96) +#define WRMEM1_88_FLD8 GENMASK(127, 112) + +/* WRMEM1_89 register fields */ +#define WRMEM1_89_FLD1 GENMASK(15, 0) +#define WRMEM1_89_FLD2 GENMASK(31, 16) +#define WRMEM1_89_FLD3 GENMASK(47, 32) +#define WRMEM1_89_FLD4 GENMASK(63, 48) +#define WRMEM1_89_FLD5 GENMASK(79, 64) +#define WRMEM1_89_FLD6 GENMASK(95, 80) +#define WRMEM1_89_FLD7 GENMASK(111, 96) +#define WRMEM1_89_FLD8 GENMASK(127, 112) + +/* WRMEM1_90 register fields */ +#define WRMEM1_90_FLD1 GENMASK(15, 0) +#define WRMEM1_90_FLD2 GENMASK(31, 16) +#define WRMEM1_90_FLD3 GENMASK(47, 32) +#define WRMEM1_90_FLD4 GENMASK(63, 48) +#define WRMEM1_90_FLD5 GENMASK(79, 64) +#define WRMEM1_90_FLD6 GENMASK(95, 80) +#define WRMEM1_90_FLD7 GENMASK(111, 96) +#define WRMEM1_90_FLD8 GENMASK(127, 112) + +/* WRMEM1_91 register fields */ +#define WRMEM1_91_FLD1 GENMASK(15, 0) +#define WRMEM1_91_FLD2 GENMASK(31, 16) +#define WRMEM1_91_FLD3 GENMASK(47, 32) +#define WRMEM1_91_FLD4 GENMASK(63, 48) +#define WRMEM1_91_FLD5 GENMASK(79, 64) +#define WRMEM1_91_FLD6 GENMASK(95, 80) +#define WRMEM1_91_FLD7 GENMASK(111, 96) +#define WRMEM1_91_FLD8 GENMASK(127, 112) + +/* WRMEM1_92 register fields */ +#define WRMEM1_92_FLD1 GENMASK(15, 0) +#define WRMEM1_92_FLD2 GENMASK(31, 16) +#define WRMEM1_92_FLD3 GENMASK(47, 32) +#define WRMEM1_92_FLD4 GENMASK(63, 48) +#define WRMEM1_92_FLD5 GENMASK(79, 64) +#define WRMEM1_92_FLD6 GENMASK(95, 80) +#define WRMEM1_92_FLD7 GENMASK(111, 96) +#define WRMEM1_92_FLD8 GENMASK(127, 112) + +/* WRMEM1_93 register fields */ +#define WRMEM1_93_FLD1 GENMASK(15, 0) +#define WRMEM1_93_FLD2 GENMASK(31, 16) +#define WRMEM1_93_FLD3 GENMASK(47, 32) +#define WRMEM1_93_FLD4 GENMASK(63, 48) +#define WRMEM1_93_FLD5 GENMASK(79, 64) +#define WRMEM1_93_FLD6 GENMASK(95, 80) +#define WRMEM1_93_FLD7 GENMASK(111, 96) +#define WRMEM1_93_FLD8 GENMASK(127, 112) + +/* WRMEM1_94 register fields */ +#define WRMEM1_94_FLD1 GENMASK(15, 0) +#define WRMEM1_94_FLD2 GENMASK(31, 16) +#define WRMEM1_94_FLD3 GENMASK(47, 32) +#define WRMEM1_94_FLD4 GENMASK(63, 48) +#define WRMEM1_94_FLD5 GENMASK(79, 64) +#define WRMEM1_94_FLD6 GENMASK(95, 80) +#define WRMEM1_94_FLD7 GENMASK(111, 96) +#define WRMEM1_94_FLD8 GENMASK(127, 112) + +/* WRMEM1_95 register fields */ +#define WRMEM1_95_FLD1 GENMASK(15, 0) +#define WRMEM1_95_FLD2 GENMASK(31, 16) +#define WRMEM1_95_FLD3 GENMASK(47, 32) +#define WRMEM1_95_FLD4 GENMASK(63, 48) +#define WRMEM1_95_FLD5 GENMASK(79, 64) +#define WRMEM1_95_FLD6 GENMASK(95, 80) +#define WRMEM1_95_FLD7 GENMASK(111, 96) +#define WRMEM1_95_FLD8 GENMASK(127, 112) + +/* WRMEM1_96 register fields */ +#define WRMEM1_96_FLD1 GENMASK(15, 0) +#define WRMEM1_96_FLD2 GENMASK(31, 16) +#define WRMEM1_96_FLD3 GENMASK(47, 32) +#define WRMEM1_96_FLD4 GENMASK(63, 48) +#define WRMEM1_96_FLD5 GENMASK(79, 64) +#define WRMEM1_96_FLD6 GENMASK(95, 80) +#define WRMEM1_96_FLD7 GENMASK(111, 96) +#define WRMEM1_96_FLD8 GENMASK(127, 112) + +/* WRMEM1_97 register fields */ +#define WRMEM1_97_FLD1 GENMASK(15, 0) +#define WRMEM1_97_FLD2 GENMASK(31, 16) +#define WRMEM1_97_FLD3 GENMASK(47, 32) +#define WRMEM1_97_FLD4 GENMASK(63, 48) +#define WRMEM1_97_FLD5 GENMASK(79, 64) +#define WRMEM1_97_FLD6 GENMASK(95, 80) +#define WRMEM1_97_FLD7 GENMASK(111, 96) +#define WRMEM1_97_FLD8 GENMASK(127, 112) + +/* WRMEM1_98 register fields */ +#define WRMEM1_98_FLD1 GENMASK(15, 0) +#define WRMEM1_98_FLD2 GENMASK(31, 16) +#define WRMEM1_98_FLD3 GENMASK(47, 32) +#define WRMEM1_98_FLD4 GENMASK(63, 48) +#define WRMEM1_98_FLD5 GENMASK(79, 64) +#define WRMEM1_98_FLD6 GENMASK(95, 80) +#define WRMEM1_98_FLD7 GENMASK(111, 96) +#define WRMEM1_98_FLD8 GENMASK(127, 112) + +/* WRMEM1_99 register fields */ +#define WRMEM1_99_FLD1 GENMASK(15, 0) +#define WRMEM1_99_FLD2 GENMASK(31, 16) +#define WRMEM1_99_FLD3 GENMASK(47, 32) +#define WRMEM1_99_FLD4 GENMASK(63, 48) +#define WRMEM1_99_FLD5 GENMASK(79, 64) +#define WRMEM1_99_FLD6 GENMASK(95, 80) +#define WRMEM1_99_FLD7 GENMASK(111, 96) +#define WRMEM1_99_FLD8 GENMASK(127, 112) + +/* WRMEM1_100 register fields */ +#define WRMEM1_100_FLD1 GENMASK(15, 0) +#define WRMEM1_100_FLD2 GENMASK(31, 16) +#define WRMEM1_100_FLD3 GENMASK(47, 32) +#define WRMEM1_100_FLD4 GENMASK(63, 48) +#define WRMEM1_100_FLD5 GENMASK(79, 64) +#define WRMEM1_100_FLD6 GENMASK(95, 80) +#define WRMEM1_100_FLD7 GENMASK(111, 96) +#define WRMEM1_100_FLD8 GENMASK(127, 112) + +/* WRMEM1_101 register fields */ +#define WRMEM1_101_FLD1 GENMASK(15, 0) +#define WRMEM1_101_FLD2 GENMASK(31, 16) +#define WRMEM1_101_FLD3 GENMASK(47, 32) +#define WRMEM1_101_FLD4 GENMASK(63, 48) +#define WRMEM1_101_FLD5 GENMASK(79, 64) +#define WRMEM1_101_FLD6 GENMASK(95, 80) +#define WRMEM1_101_FLD7 GENMASK(111, 96) +#define WRMEM1_101_FLD8 GENMASK(127, 112) + +/* WRMEM1_102 register fields */ +#define WRMEM1_102_FLD1 GENMASK(15, 0) +#define WRMEM1_102_FLD2 GENMASK(31, 16) +#define WRMEM1_102_FLD3 GENMASK(47, 32) +#define WRMEM1_102_FLD4 GENMASK(63, 48) +#define WRMEM1_102_FLD5 GENMASK(79, 64) +#define WRMEM1_102_FLD6 GENMASK(95, 80) +#define WRMEM1_102_FLD7 GENMASK(111, 96) +#define WRMEM1_102_FLD8 GENMASK(127, 112) + +/* WRMEM1_103 register fields */ +#define WRMEM1_103_FLD1 GENMASK(15, 0) +#define WRMEM1_103_FLD2 GENMASK(31, 16) +#define WRMEM1_103_FLD3 GENMASK(47, 32) +#define WRMEM1_103_FLD4 GENMASK(63, 48) +#define WRMEM1_103_FLD5 GENMASK(79, 64) +#define WRMEM1_103_FLD6 GENMASK(95, 80) +#define WRMEM1_103_FLD7 GENMASK(111, 96) +#define WRMEM1_103_FLD8 GENMASK(127, 112) + +/* WRMEM1_104 register fields */ +#define WRMEM1_104_FLD1 GENMASK(15, 0) +#define WRMEM1_104_FLD2 GENMASK(31, 16) +#define WRMEM1_104_FLD3 GENMASK(47, 32) +#define WRMEM1_104_FLD4 GENMASK(63, 48) +#define WRMEM1_104_FLD5 GENMASK(79, 64) +#define WRMEM1_104_FLD6 GENMASK(95, 80) +#define WRMEM1_104_FLD7 GENMASK(111, 96) +#define WRMEM1_104_FLD8 GENMASK(127, 112) + +/* WRMEM1_105 register fields */ +#define WRMEM1_105_FLD1 GENMASK(15, 0) +#define WRMEM1_105_FLD2 GENMASK(31, 16) +#define WRMEM1_105_FLD3 GENMASK(47, 32) +#define WRMEM1_105_FLD4 GENMASK(63, 48) +#define WRMEM1_105_FLD5 GENMASK(79, 64) +#define WRMEM1_105_FLD6 GENMASK(95, 80) +#define WRMEM1_105_FLD7 GENMASK(111, 96) +#define WRMEM1_105_FLD8 GENMASK(127, 112) + +/* WRMEM1_106 register fields */ +#define WRMEM1_106_FLD1 GENMASK(15, 0) +#define WRMEM1_106_FLD2 GENMASK(31, 16) +#define WRMEM1_106_FLD3 GENMASK(47, 32) +#define WRMEM1_106_FLD4 GENMASK(63, 48) +#define WRMEM1_106_FLD5 GENMASK(79, 64) +#define WRMEM1_106_FLD6 GENMASK(95, 80) +#define WRMEM1_106_FLD7 GENMASK(111, 96) +#define WRMEM1_106_FLD8 GENMASK(127, 112) + +/* WRMEM1_107 register fields */ +#define WRMEM1_107_FLD1 GENMASK(15, 0) +#define WRMEM1_107_FLD2 GENMASK(31, 16) +#define WRMEM1_107_FLD3 GENMASK(47, 32) +#define WRMEM1_107_FLD4 GENMASK(63, 48) +#define WRMEM1_107_FLD5 GENMASK(79, 64) +#define WRMEM1_107_FLD6 GENMASK(95, 80) +#define WRMEM1_107_FLD7 GENMASK(111, 96) +#define WRMEM1_107_FLD8 GENMASK(127, 112) + +/* WRMEM1_108 register fields */ +#define WRMEM1_108_FLD1 GENMASK(15, 0) +#define WRMEM1_108_FLD2 GENMASK(31, 16) +#define WRMEM1_108_FLD3 GENMASK(47, 32) +#define WRMEM1_108_FLD4 GENMASK(63, 48) +#define WRMEM1_108_FLD5 GENMASK(79, 64) +#define WRMEM1_108_FLD6 GENMASK(95, 80) +#define WRMEM1_108_FLD7 GENMASK(111, 96) +#define WRMEM1_108_FLD8 GENMASK(127, 112) + +/* WRMEM1_109 register fields */ +#define WRMEM1_109_FLD1 GENMASK(15, 0) +#define WRMEM1_109_FLD2 GENMASK(31, 16) +#define WRMEM1_109_FLD3 GENMASK(47, 32) +#define WRMEM1_109_FLD4 GENMASK(63, 48) +#define WRMEM1_109_FLD5 GENMASK(79, 64) +#define WRMEM1_109_FLD6 GENMASK(95, 80) +#define WRMEM1_109_FLD7 GENMASK(111, 96) +#define WRMEM1_109_FLD8 GENMASK(127, 112) + +/* WRMEM1_110 register fields */ +#define WRMEM1_110_FLD1 GENMASK(15, 0) +#define WRMEM1_110_FLD2 GENMASK(31, 16) +#define WRMEM1_110_FLD3 GENMASK(47, 32) +#define WRMEM1_110_FLD4 GENMASK(63, 48) +#define WRMEM1_110_FLD5 GENMASK(79, 64) +#define WRMEM1_110_FLD6 GENMASK(95, 80) +#define WRMEM1_110_FLD7 GENMASK(111, 96) +#define WRMEM1_110_FLD8 GENMASK(127, 112) + +/* WRMEM1_111 register fields */ +#define WRMEM1_111_FLD1 GENMASK(15, 0) +#define WRMEM1_111_FLD2 GENMASK(31, 16) +#define WRMEM1_111_FLD3 GENMASK(47, 32) +#define WRMEM1_111_FLD4 GENMASK(63, 48) +#define WRMEM1_111_FLD5 GENMASK(79, 64) +#define WRMEM1_111_FLD6 GENMASK(95, 80) +#define WRMEM1_111_FLD7 GENMASK(111, 96) +#define WRMEM1_111_FLD8 GENMASK(127, 112) + +/* WRMEM1_112 register fields */ +#define WRMEM1_112_FLD1 GENMASK(15, 0) +#define WRMEM1_112_FLD2 GENMASK(31, 16) +#define WRMEM1_112_FLD3 GENMASK(47, 32) +#define WRMEM1_112_FLD4 GENMASK(63, 48) +#define WRMEM1_112_FLD5 GENMASK(79, 64) +#define WRMEM1_112_FLD6 GENMASK(95, 80) +#define WRMEM1_112_FLD7 GENMASK(111, 96) +#define WRMEM1_112_FLD8 GENMASK(127, 112) + +/* WRMEM1_113 register fields */ +#define WRMEM1_113_FLD1 GENMASK(15, 0) +#define WRMEM1_113_FLD2 GENMASK(31, 16) +#define WRMEM1_113_FLD3 GENMASK(47, 32) +#define WRMEM1_113_FLD4 GENMASK(63, 48) +#define WRMEM1_113_FLD5 GENMASK(79, 64) +#define WRMEM1_113_FLD6 GENMASK(95, 80) +#define WRMEM1_113_FLD7 GENMASK(111, 96) +#define WRMEM1_113_FLD8 GENMASK(127, 112) + +/* WRMEM1_114 register fields */ +#define WRMEM1_114_FLD1 GENMASK(15, 0) +#define WRMEM1_114_FLD2 GENMASK(31, 16) +#define WRMEM1_114_FLD3 GENMASK(47, 32) +#define WRMEM1_114_FLD4 GENMASK(63, 48) +#define WRMEM1_114_FLD5 GENMASK(79, 64) +#define WRMEM1_114_FLD6 GENMASK(95, 80) +#define WRMEM1_114_FLD7 GENMASK(111, 96) +#define WRMEM1_114_FLD8 GENMASK(127, 112) + +/* WRMEM1_115 register fields */ +#define WRMEM1_115_FLD1 GENMASK(15, 0) +#define WRMEM1_115_FLD2 GENMASK(31, 16) +#define WRMEM1_115_FLD3 GENMASK(47, 32) +#define WRMEM1_115_FLD4 GENMASK(63, 48) +#define WRMEM1_115_FLD5 GENMASK(79, 64) +#define WRMEM1_115_FLD6 GENMASK(95, 80) +#define WRMEM1_115_FLD7 GENMASK(111, 96) +#define WRMEM1_115_FLD8 GENMASK(127, 112) + +/* WRMEM1_116 register fields */ +#define WRMEM1_116_FLD1 GENMASK(15, 0) +#define WRMEM1_116_FLD2 GENMASK(31, 16) +#define WRMEM1_116_FLD3 GENMASK(47, 32) +#define WRMEM1_116_FLD4 GENMASK(63, 48) +#define WRMEM1_116_FLD5 GENMASK(79, 64) +#define WRMEM1_116_FLD6 GENMASK(95, 80) +#define WRMEM1_116_FLD7 GENMASK(111, 96) +#define WRMEM1_116_FLD8 GENMASK(127, 112) + +/* WRMEM1_117 register fields */ +#define WRMEM1_117_FLD1 GENMASK(15, 0) +#define WRMEM1_117_FLD2 GENMASK(31, 16) +#define WRMEM1_117_FLD3 GENMASK(47, 32) +#define WRMEM1_117_FLD4 GENMASK(63, 48) +#define WRMEM1_117_FLD5 GENMASK(79, 64) +#define WRMEM1_117_FLD6 GENMASK(95, 80) +#define WRMEM1_117_FLD7 GENMASK(111, 96) +#define WRMEM1_117_FLD8 GENMASK(127, 112) + +/* WRMEM1_118 register fields */ +#define WRMEM1_118_FLD1 GENMASK(15, 0) +#define WRMEM1_118_FLD2 GENMASK(31, 16) +#define WRMEM1_118_FLD3 GENMASK(47, 32) +#define WRMEM1_118_FLD4 GENMASK(63, 48) +#define WRMEM1_118_FLD5 GENMASK(79, 64) +#define WRMEM1_118_FLD6 GENMASK(95, 80) +#define WRMEM1_118_FLD7 GENMASK(111, 96) +#define WRMEM1_118_FLD8 GENMASK(127, 112) + +/* WRMEM1_119 register fields */ +#define WRMEM1_119_FLD1 GENMASK(15, 0) +#define WRMEM1_119_FLD2 GENMASK(31, 16) +#define WRMEM1_119_FLD3 GENMASK(47, 32) +#define WRMEM1_119_FLD4 GENMASK(63, 48) +#define WRMEM1_119_FLD5 GENMASK(79, 64) +#define WRMEM1_119_FLD6 GENMASK(95, 80) +#define WRMEM1_119_FLD7 GENMASK(111, 96) +#define WRMEM1_119_FLD8 GENMASK(127, 112) + +/* WRMEM1_120 register fields */ +#define WRMEM1_120_FLD1 GENMASK(15, 0) +#define WRMEM1_120_FLD2 GENMASK(31, 16) +#define WRMEM1_120_FLD3 GENMASK(47, 32) +#define WRMEM1_120_FLD4 GENMASK(63, 48) +#define WRMEM1_120_FLD5 GENMASK(79, 64) +#define WRMEM1_120_FLD6 GENMASK(95, 80) +#define WRMEM1_120_FLD7 GENMASK(111, 96) +#define WRMEM1_120_FLD8 GENMASK(127, 112) + +/* WRMEM1_121 register fields */ +#define WRMEM1_121_FLD1 GENMASK(15, 0) +#define WRMEM1_121_FLD2 GENMASK(31, 16) +#define WRMEM1_121_FLD3 GENMASK(47, 32) +#define WRMEM1_121_FLD4 GENMASK(63, 48) +#define WRMEM1_121_FLD5 GENMASK(79, 64) +#define WRMEM1_121_FLD6 GENMASK(95, 80) +#define WRMEM1_121_FLD7 GENMASK(111, 96) +#define WRMEM1_121_FLD8 GENMASK(127, 112) + +/* WRMEM1_122 register fields */ +#define WRMEM1_122_FLD1 GENMASK(15, 0) +#define WRMEM1_122_FLD2 GENMASK(31, 16) +#define WRMEM1_122_FLD3 GENMASK(47, 32) +#define WRMEM1_122_FLD4 GENMASK(63, 48) +#define WRMEM1_122_FLD5 GENMASK(79, 64) +#define WRMEM1_122_FLD6 GENMASK(95, 80) +#define WRMEM1_122_FLD7 GENMASK(111, 96) +#define WRMEM1_122_FLD8 GENMASK(127, 112) + +/* WRMEM1_123 register fields */ +#define WRMEM1_123_FLD1 GENMASK(15, 0) +#define WRMEM1_123_FLD2 GENMASK(31, 16) +#define WRMEM1_123_FLD3 GENMASK(47, 32) +#define WRMEM1_123_FLD4 GENMASK(63, 48) +#define WRMEM1_123_FLD5 GENMASK(79, 64) +#define WRMEM1_123_FLD6 GENMASK(95, 80) +#define WRMEM1_123_FLD7 GENMASK(111, 96) +#define WRMEM1_123_FLD8 GENMASK(127, 112) + +/* WRMEM1_124 register fields */ +#define WRMEM1_124_FLD1 GENMASK(15, 0) +#define WRMEM1_124_FLD2 GENMASK(31, 16) +#define WRMEM1_124_FLD3 GENMASK(47, 32) +#define WRMEM1_124_FLD4 GENMASK(63, 48) +#define WRMEM1_124_FLD5 GENMASK(79, 64) +#define WRMEM1_124_FLD6 GENMASK(95, 80) +#define WRMEM1_124_FLD7 GENMASK(111, 96) +#define WRMEM1_124_FLD8 GENMASK(127, 112) + +/* WRMEM1_125 register fields */ +#define WRMEM1_125_FLD1 GENMASK(15, 0) +#define WRMEM1_125_FLD2 GENMASK(31, 16) +#define WRMEM1_125_FLD3 GENMASK(47, 32) +#define WRMEM1_125_FLD4 GENMASK(63, 48) +#define WRMEM1_125_FLD5 GENMASK(79, 64) +#define WRMEM1_125_FLD6 GENMASK(95, 80) +#define WRMEM1_125_FLD7 GENMASK(111, 96) +#define WRMEM1_125_FLD8 GENMASK(127, 112) + +/* WRMEM1_126 register fields */ +#define WRMEM1_126_FLD1 GENMASK(15, 0) +#define WRMEM1_126_FLD2 GENMASK(31, 16) +#define WRMEM1_126_FLD3 GENMASK(47, 32) +#define WRMEM1_126_FLD4 GENMASK(63, 48) +#define WRMEM1_126_FLD5 GENMASK(79, 64) +#define WRMEM1_126_FLD6 GENMASK(95, 80) +#define WRMEM1_126_FLD7 GENMASK(111, 96) +#define WRMEM1_126_FLD8 GENMASK(127, 112) + +/* WRMEM1_127 register fields */ +#define WRMEM1_127_FLD1 GENMASK(15, 0) +#define WRMEM1_127_FLD2 GENMASK(31, 16) +#define WRMEM1_127_FLD3 GENMASK(47, 32) +#define WRMEM1_127_FLD4 GENMASK(63, 48) +#define WRMEM1_127_FLD5 GENMASK(79, 64) +#define WRMEM1_127_FLD6 GENMASK(95, 80) +#define WRMEM1_127_FLD7 GENMASK(111, 96) +#define WRMEM1_127_FLD8 GENMASK(127, 112) + +/* WRMEM1_128 register fields */ +#define WRMEM1_128_FLD1 GENMASK(15, 0) +#define WRMEM1_128_FLD2 GENMASK(31, 16) +#define WRMEM1_128_FLD3 GENMASK(47, 32) +#define WRMEM1_128_FLD4 GENMASK(63, 48) +#define WRMEM1_128_FLD5 GENMASK(79, 64) +#define WRMEM1_128_FLD6 GENMASK(95, 80) +#define WRMEM1_128_FLD7 GENMASK(111, 96) +#define WRMEM1_128_FLD8 GENMASK(127, 112) + +/* WRMEM1_129 register fields */ +#define WRMEM1_129_FLD1 GENMASK(15, 0) +#define WRMEM1_129_FLD2 GENMASK(31, 16) +#define WRMEM1_129_FLD3 GENMASK(47, 32) +#define WRMEM1_129_FLD4 GENMASK(63, 48) +#define WRMEM1_129_FLD5 GENMASK(79, 64) +#define WRMEM1_129_FLD6 GENMASK(95, 80) +#define WRMEM1_129_FLD7 GENMASK(111, 96) +#define WRMEM1_129_FLD8 GENMASK(127, 112) + +/* WRMEM1_130 register fields */ +#define WRMEM1_130_FLD1 GENMASK(15, 0) +#define WRMEM1_130_FLD2 GENMASK(31, 16) +#define WRMEM1_130_FLD3 GENMASK(47, 32) +#define WRMEM1_130_FLD4 GENMASK(63, 48) +#define WRMEM1_130_FLD5 GENMASK(79, 64) +#define WRMEM1_130_FLD6 GENMASK(95, 80) +#define WRMEM1_130_FLD7 GENMASK(111, 96) +#define WRMEM1_130_FLD8 GENMASK(127, 112) + +/* WRMEM1_131 register fields */ +#define WRMEM1_131_FLD1 GENMASK(15, 0) +#define WRMEM1_131_FLD2 GENMASK(31, 16) +#define WRMEM1_131_FLD3 GENMASK(47, 32) +#define WRMEM1_131_FLD4 GENMASK(63, 48) +#define WRMEM1_131_FLD5 GENMASK(79, 64) +#define WRMEM1_131_FLD6 GENMASK(95, 80) +#define WRMEM1_131_FLD7 GENMASK(111, 96) +#define WRMEM1_131_FLD8 GENMASK(127, 112) + +/* WRMEM1_132 register fields */ +#define WRMEM1_132_FLD1 GENMASK(15, 0) +#define WRMEM1_132_FLD2 GENMASK(31, 16) +#define WRMEM1_132_FLD3 GENMASK(47, 32) +#define WRMEM1_132_FLD4 GENMASK(63, 48) +#define WRMEM1_132_FLD5 GENMASK(79, 64) +#define WRMEM1_132_FLD6 GENMASK(95, 80) +#define WRMEM1_132_FLD7 GENMASK(111, 96) +#define WRMEM1_132_FLD8 GENMASK(127, 112) + +/* WRMEM1_133 register fields */ +#define WRMEM1_133_FLD1 GENMASK(15, 0) +#define WRMEM1_133_FLD2 GENMASK(31, 16) +#define WRMEM1_133_FLD3 GENMASK(47, 32) +#define WRMEM1_133_FLD4 GENMASK(63, 48) +#define WRMEM1_133_FLD5 GENMASK(79, 64) +#define WRMEM1_133_FLD6 GENMASK(95, 80) +#define WRMEM1_133_FLD7 GENMASK(111, 96) +#define WRMEM1_133_FLD8 GENMASK(127, 112) + +/* WRMEM1_134 register fields */ +#define WRMEM1_134_FLD1 GENMASK(15, 0) +#define WRMEM1_134_FLD2 GENMASK(31, 16) +#define WRMEM1_134_FLD3 GENMASK(47, 32) +#define WRMEM1_134_FLD4 GENMASK(63, 48) +#define WRMEM1_134_FLD5 GENMASK(79, 64) +#define WRMEM1_134_FLD6 GENMASK(95, 80) +#define WRMEM1_134_FLD7 GENMASK(111, 96) +#define WRMEM1_134_FLD8 GENMASK(127, 112) + +/* WRMEM1_135 register fields */ +#define WRMEM1_135_FLD1 GENMASK(15, 0) +#define WRMEM1_135_FLD2 GENMASK(31, 16) +#define WRMEM1_135_FLD3 GENMASK(47, 32) +#define WRMEM1_135_FLD4 GENMASK(63, 48) +#define WRMEM1_135_FLD5 GENMASK(79, 64) +#define WRMEM1_135_FLD6 GENMASK(95, 80) +#define WRMEM1_135_FLD7 GENMASK(111, 96) +#define WRMEM1_135_FLD8 GENMASK(127, 112) + +/* WRMEM1_136 register fields */ +#define WRMEM1_136_FLD1 GENMASK(15, 0) +#define WRMEM1_136_FLD2 GENMASK(31, 16) +#define WRMEM1_136_FLD3 GENMASK(47, 32) +#define WRMEM1_136_FLD4 GENMASK(63, 48) +#define WRMEM1_136_FLD5 GENMASK(79, 64) +#define WRMEM1_136_FLD6 GENMASK(95, 80) +#define WRMEM1_136_FLD7 GENMASK(111, 96) +#define WRMEM1_136_FLD8 GENMASK(127, 112) + +/* WRMEM1_137 register fields */ +#define WRMEM1_137_FLD1 GENMASK(15, 0) +#define WRMEM1_137_FLD2 GENMASK(31, 16) +#define WRMEM1_137_FLD3 GENMASK(47, 32) +#define WRMEM1_137_FLD4 GENMASK(63, 48) +#define WRMEM1_137_FLD5 GENMASK(79, 64) +#define WRMEM1_137_FLD6 GENMASK(95, 80) +#define WRMEM1_137_FLD7 GENMASK(111, 96) +#define WRMEM1_137_FLD8 GENMASK(127, 112) + +/* WRMEM1_138 register fields */ +#define WRMEM1_138_FLD1 GENMASK(15, 0) +#define WRMEM1_138_FLD2 GENMASK(31, 16) +#define WRMEM1_138_FLD3 GENMASK(47, 32) +#define WRMEM1_138_FLD4 GENMASK(63, 48) +#define WRMEM1_138_FLD5 GENMASK(79, 64) +#define WRMEM1_138_FLD6 GENMASK(95, 80) +#define WRMEM1_138_FLD7 GENMASK(111, 96) +#define WRMEM1_138_FLD8 GENMASK(127, 112) + +/* WRMEM1_139 register fields */ +#define WRMEM1_139_FLD1 GENMASK(15, 0) +#define WRMEM1_139_FLD2 GENMASK(31, 16) +#define WRMEM1_139_FLD3 GENMASK(47, 32) +#define WRMEM1_139_FLD4 GENMASK(63, 48) +#define WRMEM1_139_FLD5 GENMASK(79, 64) +#define WRMEM1_139_FLD6 GENMASK(95, 80) +#define WRMEM1_139_FLD7 GENMASK(111, 96) +#define WRMEM1_139_FLD8 GENMASK(127, 112) + +/* WRMEM1_140 register fields */ +#define WRMEM1_140_FLD1 GENMASK(15, 0) +#define WRMEM1_140_FLD2 GENMASK(31, 16) +#define WRMEM1_140_FLD3 GENMASK(47, 32) +#define WRMEM1_140_FLD4 GENMASK(63, 48) +#define WRMEM1_140_FLD5 GENMASK(79, 64) +#define WRMEM1_140_FLD6 GENMASK(95, 80) +#define WRMEM1_140_FLD7 GENMASK(111, 96) +#define WRMEM1_140_FLD8 GENMASK(127, 112) + +/* WRMEM1_141 register fields */ +#define WRMEM1_141_FLD1 GENMASK(15, 0) +#define WRMEM1_141_FLD2 GENMASK(31, 16) +#define WRMEM1_141_FLD3 GENMASK(47, 32) +#define WRMEM1_141_FLD4 GENMASK(63, 48) +#define WRMEM1_141_FLD5 GENMASK(79, 64) +#define WRMEM1_141_FLD6 GENMASK(95, 80) +#define WRMEM1_141_FLD7 GENMASK(111, 96) +#define WRMEM1_141_FLD8 GENMASK(127, 112) + +/* WRMEM1_142 register fields */ +#define WRMEM1_142_FLD1 GENMASK(15, 0) +#define WRMEM1_142_FLD2 GENMASK(31, 16) +#define WRMEM1_142_FLD3 GENMASK(47, 32) +#define WRMEM1_142_FLD4 GENMASK(63, 48) +#define WRMEM1_142_FLD5 GENMASK(79, 64) +#define WRMEM1_142_FLD6 GENMASK(95, 80) +#define WRMEM1_142_FLD7 GENMASK(111, 96) +#define WRMEM1_142_FLD8 GENMASK(127, 112) + +/* WRMEM1_143 register fields */ +#define WRMEM1_143_FLD1 GENMASK(15, 0) +#define WRMEM1_143_FLD2 GENMASK(31, 16) +#define WRMEM1_143_FLD3 GENMASK(47, 32) +#define WRMEM1_143_FLD4 GENMASK(63, 48) +#define WRMEM1_143_FLD5 GENMASK(79, 64) +#define WRMEM1_143_FLD6 GENMASK(95, 80) +#define WRMEM1_143_FLD7 GENMASK(111, 96) +#define WRMEM1_143_FLD8 GENMASK(127, 112) + +/* WRMEM1_144 register fields */ +#define WRMEM1_144_FLD1 GENMASK(15, 0) +#define WRMEM1_144_FLD2 GENMASK(31, 16) +#define WRMEM1_144_FLD3 GENMASK(47, 32) +#define WRMEM1_144_FLD4 GENMASK(63, 48) +#define WRMEM1_144_FLD5 GENMASK(79, 64) +#define WRMEM1_144_FLD6 GENMASK(95, 80) +#define WRMEM1_144_FLD7 GENMASK(111, 96) +#define WRMEM1_144_FLD8 GENMASK(127, 112) + +/* WRMEM1_145 register fields */ +#define WRMEM1_145_FLD1 GENMASK(15, 0) +#define WRMEM1_145_FLD2 GENMASK(31, 16) +#define WRMEM1_145_FLD3 GENMASK(47, 32) +#define WRMEM1_145_FLD4 GENMASK(63, 48) +#define WRMEM1_145_FLD5 GENMASK(79, 64) +#define WRMEM1_145_FLD6 GENMASK(95, 80) +#define WRMEM1_145_FLD7 GENMASK(111, 96) +#define WRMEM1_145_FLD8 GENMASK(127, 112) + +/* WRMEM1_146 register fields */ +#define WRMEM1_146_FLD1 GENMASK(15, 0) +#define WRMEM1_146_FLD2 GENMASK(31, 16) +#define WRMEM1_146_FLD3 GENMASK(47, 32) +#define WRMEM1_146_FLD4 GENMASK(63, 48) +#define WRMEM1_146_FLD5 GENMASK(79, 64) +#define WRMEM1_146_FLD6 GENMASK(95, 80) +#define WRMEM1_146_FLD7 GENMASK(111, 96) +#define WRMEM1_146_FLD8 GENMASK(127, 112) + +/* WRMEM1_147 register fields */ +#define WRMEM1_147_FLD1 GENMASK(15, 0) +#define WRMEM1_147_FLD2 GENMASK(31, 16) +#define WRMEM1_147_FLD3 GENMASK(47, 32) +#define WRMEM1_147_FLD4 GENMASK(63, 48) +#define WRMEM1_147_FLD5 GENMASK(79, 64) +#define WRMEM1_147_FLD6 GENMASK(95, 80) +#define WRMEM1_147_FLD7 GENMASK(111, 96) +#define WRMEM1_147_FLD8 GENMASK(127, 112) + +/* WRMEM1_148 register fields */ +#define WRMEM1_148_FLD1 GENMASK(15, 0) +#define WRMEM1_148_FLD2 GENMASK(31, 16) +#define WRMEM1_148_FLD3 GENMASK(47, 32) +#define WRMEM1_148_FLD4 GENMASK(63, 48) +#define WRMEM1_148_FLD5 GENMASK(79, 64) +#define WRMEM1_148_FLD6 GENMASK(95, 80) +#define WRMEM1_148_FLD7 GENMASK(111, 96) +#define WRMEM1_148_FLD8 GENMASK(127, 112) + +/* WRMEM1_149 register fields */ +#define WRMEM1_149_FLD1 GENMASK(15, 0) +#define WRMEM1_149_FLD2 GENMASK(31, 16) +#define WRMEM1_149_FLD3 GENMASK(47, 32) +#define WRMEM1_149_FLD4 GENMASK(63, 48) +#define WRMEM1_149_FLD5 GENMASK(79, 64) +#define WRMEM1_149_FLD6 GENMASK(95, 80) +#define WRMEM1_149_FLD7 GENMASK(111, 96) +#define WRMEM1_149_FLD8 GENMASK(127, 112) + +/* WRMEM1_150 register fields */ +#define WRMEM1_150_FLD1 GENMASK(15, 0) +#define WRMEM1_150_FLD2 GENMASK(31, 16) +#define WRMEM1_150_FLD3 GENMASK(47, 32) +#define WRMEM1_150_FLD4 GENMASK(63, 48) +#define WRMEM1_150_FLD5 GENMASK(79, 64) +#define WRMEM1_150_FLD6 GENMASK(95, 80) +#define WRMEM1_150_FLD7 GENMASK(111, 96) +#define WRMEM1_150_FLD8 GENMASK(127, 112) + +/* WRMEM1_151 register fields */ +#define WRMEM1_151_FLD1 GENMASK(15, 0) +#define WRMEM1_151_FLD2 GENMASK(31, 16) +#define WRMEM1_151_FLD3 GENMASK(47, 32) +#define WRMEM1_151_FLD4 GENMASK(63, 48) +#define WRMEM1_151_FLD5 GENMASK(79, 64) +#define WRMEM1_151_FLD6 GENMASK(95, 80) +#define WRMEM1_151_FLD7 GENMASK(111, 96) +#define WRMEM1_151_FLD8 GENMASK(127, 112) + +/* WRMEM1_152 register fields */ +#define WRMEM1_152_FLD1 GENMASK(15, 0) +#define WRMEM1_152_FLD2 GENMASK(31, 16) +#define WRMEM1_152_FLD3 GENMASK(47, 32) +#define WRMEM1_152_FLD4 GENMASK(63, 48) +#define WRMEM1_152_FLD5 GENMASK(79, 64) +#define WRMEM1_152_FLD6 GENMASK(95, 80) +#define WRMEM1_152_FLD7 GENMASK(111, 96) +#define WRMEM1_152_FLD8 GENMASK(127, 112) + +/* WRMEM1_153 register fields */ +#define WRMEM1_153_FLD1 GENMASK(15, 0) +#define WRMEM1_153_FLD2 GENMASK(31, 16) +#define WRMEM1_153_FLD3 GENMASK(47, 32) +#define WRMEM1_153_FLD4 GENMASK(63, 48) +#define WRMEM1_153_FLD5 GENMASK(79, 64) +#define WRMEM1_153_FLD6 GENMASK(95, 80) +#define WRMEM1_153_FLD7 GENMASK(111, 96) +#define WRMEM1_153_FLD8 GENMASK(127, 112) + +/* WRMEM1_154 register fields */ +#define WRMEM1_154_FLD1 GENMASK(15, 0) +#define WRMEM1_154_FLD2 GENMASK(31, 16) +#define WRMEM1_154_FLD3 GENMASK(47, 32) +#define WRMEM1_154_FLD4 GENMASK(63, 48) +#define WRMEM1_154_FLD5 GENMASK(79, 64) +#define WRMEM1_154_FLD6 GENMASK(95, 80) +#define WRMEM1_154_FLD7 GENMASK(111, 96) +#define WRMEM1_154_FLD8 GENMASK(127, 112) + +/* WRMEM1_155 register fields */ +#define WRMEM1_155_FLD1 GENMASK(15, 0) +#define WRMEM1_155_FLD2 GENMASK(31, 16) +#define WRMEM1_155_FLD3 GENMASK(47, 32) +#define WRMEM1_155_FLD4 GENMASK(63, 48) +#define WRMEM1_155_FLD5 GENMASK(79, 64) +#define WRMEM1_155_FLD6 GENMASK(95, 80) +#define WRMEM1_155_FLD7 GENMASK(111, 96) +#define WRMEM1_155_FLD8 GENMASK(127, 112) + +/* WRMEM1_156 register fields */ +#define WRMEM1_156_FLD1 GENMASK(15, 0) +#define WRMEM1_156_FLD2 GENMASK(31, 16) +#define WRMEM1_156_FLD3 GENMASK(47, 32) +#define WRMEM1_156_FLD4 GENMASK(63, 48) +#define WRMEM1_156_FLD5 GENMASK(79, 64) +#define WRMEM1_156_FLD6 GENMASK(95, 80) +#define WRMEM1_156_FLD7 GENMASK(111, 96) +#define WRMEM1_156_FLD8 GENMASK(127, 112) + +/* WRMEM1_157 register fields */ +#define WRMEM1_157_FLD1 GENMASK(15, 0) +#define WRMEM1_157_FLD2 GENMASK(31, 16) +#define WRMEM1_157_FLD3 GENMASK(47, 32) +#define WRMEM1_157_FLD4 GENMASK(63, 48) +#define WRMEM1_157_FLD5 GENMASK(79, 64) +#define WRMEM1_157_FLD6 GENMASK(95, 80) +#define WRMEM1_157_FLD7 GENMASK(111, 96) +#define WRMEM1_157_FLD8 GENMASK(127, 112) + +/* WRMEM1_158 register fields */ +#define WRMEM1_158_FLD1 GENMASK(15, 0) +#define WRMEM1_158_FLD2 GENMASK(31, 16) +#define WRMEM1_158_FLD3 GENMASK(47, 32) +#define WRMEM1_158_FLD4 GENMASK(63, 48) +#define WRMEM1_158_FLD5 GENMASK(79, 64) +#define WRMEM1_158_FLD6 GENMASK(95, 80) +#define WRMEM1_158_FLD7 GENMASK(111, 96) +#define WRMEM1_158_FLD8 GENMASK(127, 112) + +/* WRMEM1_159 register fields */ +#define WRMEM1_159_FLD1 GENMASK(15, 0) +#define WRMEM1_159_FLD2 GENMASK(31, 16) +#define WRMEM1_159_FLD3 GENMASK(47, 32) +#define WRMEM1_159_FLD4 GENMASK(63, 48) +#define WRMEM1_159_FLD5 GENMASK(79, 64) +#define WRMEM1_159_FLD6 GENMASK(95, 80) +#define WRMEM1_159_FLD7 GENMASK(111, 96) +#define WRMEM1_159_FLD8 GENMASK(127, 112) + +/* WRMEM1_160 register fields */ +#define WRMEM1_160_FLD1 GENMASK(15, 0) +#define WRMEM1_160_FLD2 GENMASK(31, 16) +#define WRMEM1_160_FLD3 GENMASK(47, 32) +#define WRMEM1_160_FLD4 GENMASK(63, 48) +#define WRMEM1_160_FLD5 GENMASK(79, 64) +#define WRMEM1_160_FLD6 GENMASK(95, 80) +#define WRMEM1_160_FLD7 GENMASK(111, 96) +#define WRMEM1_160_FLD8 GENMASK(127, 112) + +/* WRMEM1_161 register fields */ +#define WRMEM1_161_FLD1 GENMASK(15, 0) +#define WRMEM1_161_FLD2 GENMASK(31, 16) +#define WRMEM1_161_FLD3 GENMASK(47, 32) +#define WRMEM1_161_FLD4 GENMASK(63, 48) +#define WRMEM1_161_FLD5 GENMASK(79, 64) +#define WRMEM1_161_FLD6 GENMASK(95, 80) +#define WRMEM1_161_FLD7 GENMASK(111, 96) +#define WRMEM1_161_FLD8 GENMASK(127, 112) + +/* WRMEM1_162 register fields */ +#define WRMEM1_162_FLD1 GENMASK(15, 0) +#define WRMEM1_162_FLD2 GENMASK(31, 16) +#define WRMEM1_162_FLD3 GENMASK(47, 32) +#define WRMEM1_162_FLD4 GENMASK(63, 48) +#define WRMEM1_162_FLD5 GENMASK(79, 64) +#define WRMEM1_162_FLD6 GENMASK(95, 80) +#define WRMEM1_162_FLD7 GENMASK(111, 96) +#define WRMEM1_162_FLD8 GENMASK(127, 112) + +/* WRMEM1_163 register fields */ +#define WRMEM1_163_FLD1 GENMASK(15, 0) +#define WRMEM1_163_FLD2 GENMASK(31, 16) +#define WRMEM1_163_FLD3 GENMASK(47, 32) +#define WRMEM1_163_FLD4 GENMASK(63, 48) +#define WRMEM1_163_FLD5 GENMASK(79, 64) +#define WRMEM1_163_FLD6 GENMASK(95, 80) +#define WRMEM1_163_FLD7 GENMASK(111, 96) +#define WRMEM1_163_FLD8 GENMASK(127, 112) + +/* WRMEM1_164 register fields */ +#define WRMEM1_164_FLD1 GENMASK(15, 0) +#define WRMEM1_164_FLD2 GENMASK(31, 16) +#define WRMEM1_164_FLD3 GENMASK(47, 32) +#define WRMEM1_164_FLD4 GENMASK(63, 48) +#define WRMEM1_164_FLD5 GENMASK(79, 64) +#define WRMEM1_164_FLD6 GENMASK(95, 80) +#define WRMEM1_164_FLD7 GENMASK(111, 96) +#define WRMEM1_164_FLD8 GENMASK(127, 112) + +/* WRMEM1_165 register fields */ +#define WRMEM1_165_FLD1 GENMASK(15, 0) +#define WRMEM1_165_FLD2 GENMASK(31, 16) +#define WRMEM1_165_FLD3 GENMASK(47, 32) +#define WRMEM1_165_FLD4 GENMASK(63, 48) +#define WRMEM1_165_FLD5 GENMASK(79, 64) +#define WRMEM1_165_FLD6 GENMASK(95, 80) +#define WRMEM1_165_FLD7 GENMASK(111, 96) +#define WRMEM1_165_FLD8 GENMASK(127, 112) + +/* WRMEM1_166 register fields */ +#define WRMEM1_166_FLD1 GENMASK(15, 0) +#define WRMEM1_166_FLD2 GENMASK(31, 16) +#define WRMEM1_166_FLD3 GENMASK(47, 32) +#define WRMEM1_166_FLD4 GENMASK(63, 48) +#define WRMEM1_166_FLD5 GENMASK(79, 64) +#define WRMEM1_166_FLD6 GENMASK(95, 80) +#define WRMEM1_166_FLD7 GENMASK(111, 96) +#define WRMEM1_166_FLD8 GENMASK(127, 112) + +/* WRMEM1_167 register fields */ +#define WRMEM1_167_FLD1 GENMASK(15, 0) +#define WRMEM1_167_FLD2 GENMASK(31, 16) +#define WRMEM1_167_FLD3 GENMASK(47, 32) +#define WRMEM1_167_FLD4 GENMASK(63, 48) +#define WRMEM1_167_FLD5 GENMASK(79, 64) +#define WRMEM1_167_FLD6 GENMASK(95, 80) +#define WRMEM1_167_FLD7 GENMASK(111, 96) +#define WRMEM1_167_FLD8 GENMASK(127, 112) + +/* WRMEM1_168 register fields */ +#define WRMEM1_168_FLD1 GENMASK(15, 0) +#define WRMEM1_168_FLD2 GENMASK(31, 16) +#define WRMEM1_168_FLD3 GENMASK(47, 32) +#define WRMEM1_168_FLD4 GENMASK(63, 48) +#define WRMEM1_168_FLD5 GENMASK(79, 64) +#define WRMEM1_168_FLD6 GENMASK(95, 80) +#define WRMEM1_168_FLD7 GENMASK(111, 96) +#define WRMEM1_168_FLD8 GENMASK(127, 112) + +/* WRMEM1_169 register fields */ +#define WRMEM1_169_FLD1 GENMASK(15, 0) +#define WRMEM1_169_FLD2 GENMASK(31, 16) +#define WRMEM1_169_FLD3 GENMASK(47, 32) +#define WRMEM1_169_FLD4 GENMASK(63, 48) +#define WRMEM1_169_FLD5 GENMASK(79, 64) +#define WRMEM1_169_FLD6 GENMASK(95, 80) +#define WRMEM1_169_FLD7 GENMASK(111, 96) +#define WRMEM1_169_FLD8 GENMASK(127, 112) + +/* WRMEM1_170 register fields */ +#define WRMEM1_170_FLD1 GENMASK(15, 0) +#define WRMEM1_170_FLD2 GENMASK(31, 16) +#define WRMEM1_170_FLD3 GENMASK(47, 32) +#define WRMEM1_170_FLD4 GENMASK(63, 48) +#define WRMEM1_170_FLD5 GENMASK(79, 64) +#define WRMEM1_170_FLD6 GENMASK(95, 80) +#define WRMEM1_170_FLD7 GENMASK(111, 96) +#define WRMEM1_170_FLD8 GENMASK(127, 112) + +/* WRMEM1_171 register fields */ +#define WRMEM1_171_FLD1 GENMASK(15, 0) +#define WRMEM1_171_FLD2 GENMASK(31, 16) +#define WRMEM1_171_FLD3 GENMASK(47, 32) +#define WRMEM1_171_FLD4 GENMASK(63, 48) +#define WRMEM1_171_FLD5 GENMASK(79, 64) +#define WRMEM1_171_FLD6 GENMASK(95, 80) +#define WRMEM1_171_FLD7 GENMASK(111, 96) +#define WRMEM1_171_FLD8 GENMASK(127, 112) + +/* WRMEM1_172 register fields */ +#define WRMEM1_172_FLD1 GENMASK(15, 0) +#define WRMEM1_172_FLD2 GENMASK(31, 16) +#define WRMEM1_172_FLD3 GENMASK(47, 32) +#define WRMEM1_172_FLD4 GENMASK(63, 48) +#define WRMEM1_172_FLD5 GENMASK(79, 64) +#define WRMEM1_172_FLD6 GENMASK(95, 80) +#define WRMEM1_172_FLD7 GENMASK(111, 96) +#define WRMEM1_172_FLD8 GENMASK(127, 112) + +/* WRMEM1_173 register fields */ +#define WRMEM1_173_FLD1 GENMASK(15, 0) +#define WRMEM1_173_FLD2 GENMASK(31, 16) +#define WRMEM1_173_FLD3 GENMASK(47, 32) +#define WRMEM1_173_FLD4 GENMASK(63, 48) +#define WRMEM1_173_FLD5 GENMASK(79, 64) +#define WRMEM1_173_FLD6 GENMASK(95, 80) +#define WRMEM1_173_FLD7 GENMASK(111, 96) +#define WRMEM1_173_FLD8 GENMASK(127, 112) + +/* WRMEM1_174 register fields */ +#define WRMEM1_174_FLD1 GENMASK(15, 0) +#define WRMEM1_174_FLD2 GENMASK(31, 16) +#define WRMEM1_174_FLD3 GENMASK(47, 32) +#define WRMEM1_174_FLD4 GENMASK(63, 48) +#define WRMEM1_174_FLD5 GENMASK(79, 64) +#define WRMEM1_174_FLD6 GENMASK(95, 80) +#define WRMEM1_174_FLD7 GENMASK(111, 96) +#define WRMEM1_174_FLD8 GENMASK(127, 112) + +/* WRMEM1_175 register fields */ +#define WRMEM1_175_FLD1 GENMASK(15, 0) +#define WRMEM1_175_FLD2 GENMASK(31, 16) +#define WRMEM1_175_FLD3 GENMASK(47, 32) +#define WRMEM1_175_FLD4 GENMASK(63, 48) +#define WRMEM1_175_FLD5 GENMASK(79, 64) +#define WRMEM1_175_FLD6 GENMASK(95, 80) +#define WRMEM1_175_FLD7 GENMASK(111, 96) +#define WRMEM1_175_FLD8 GENMASK(127, 112) + +/* WRMEM1_176 register fields */ +#define WRMEM1_176_FLD1 GENMASK(15, 0) +#define WRMEM1_176_FLD2 GENMASK(31, 16) +#define WRMEM1_176_FLD3 GENMASK(47, 32) +#define WRMEM1_176_FLD4 GENMASK(63, 48) +#define WRMEM1_176_FLD5 GENMASK(79, 64) +#define WRMEM1_176_FLD6 GENMASK(95, 80) +#define WRMEM1_176_FLD7 GENMASK(111, 96) +#define WRMEM1_176_FLD8 GENMASK(127, 112) + +/* WRMEM1_177 register fields */ +#define WRMEM1_177_FLD1 GENMASK(15, 0) +#define WRMEM1_177_FLD2 GENMASK(31, 16) +#define WRMEM1_177_FLD3 GENMASK(47, 32) +#define WRMEM1_177_FLD4 GENMASK(63, 48) +#define WRMEM1_177_FLD5 GENMASK(79, 64) +#define WRMEM1_177_FLD6 GENMASK(95, 80) +#define WRMEM1_177_FLD7 GENMASK(111, 96) +#define WRMEM1_177_FLD8 GENMASK(127, 112) + +/* WRMEM1_178 register fields */ +#define WRMEM1_178_FLD1 GENMASK(15, 0) +#define WRMEM1_178_FLD2 GENMASK(31, 16) +#define WRMEM1_178_FLD3 GENMASK(47, 32) +#define WRMEM1_178_FLD4 GENMASK(63, 48) +#define WRMEM1_178_FLD5 GENMASK(79, 64) +#define WRMEM1_178_FLD6 GENMASK(95, 80) +#define WRMEM1_178_FLD7 GENMASK(111, 96) +#define WRMEM1_178_FLD8 GENMASK(127, 112) + +/* WRMEM1_179 register fields */ +#define WRMEM1_179_FLD1 GENMASK(15, 0) +#define WRMEM1_179_FLD2 GENMASK(31, 16) +#define WRMEM1_179_FLD3 GENMASK(47, 32) +#define WRMEM1_179_FLD4 GENMASK(63, 48) +#define WRMEM1_179_FLD5 GENMASK(79, 64) +#define WRMEM1_179_FLD6 GENMASK(95, 80) +#define WRMEM1_179_FLD7 GENMASK(111, 96) +#define WRMEM1_179_FLD8 GENMASK(127, 112) + +/* WRMEM1_180 register fields */ +#define WRMEM1_180_FLD1 GENMASK(15, 0) +#define WRMEM1_180_FLD2 GENMASK(31, 16) +#define WRMEM1_180_FLD3 GENMASK(47, 32) +#define WRMEM1_180_FLD4 GENMASK(63, 48) +#define WRMEM1_180_FLD5 GENMASK(79, 64) +#define WRMEM1_180_FLD6 GENMASK(95, 80) +#define WRMEM1_180_FLD7 GENMASK(111, 96) +#define WRMEM1_180_FLD8 GENMASK(127, 112) + +/* WRMEM1_181 register fields */ +#define WRMEM1_181_FLD1 GENMASK(15, 0) +#define WRMEM1_181_FLD2 GENMASK(31, 16) +#define WRMEM1_181_FLD3 GENMASK(47, 32) +#define WRMEM1_181_FLD4 GENMASK(63, 48) +#define WRMEM1_181_FLD5 GENMASK(79, 64) +#define WRMEM1_181_FLD6 GENMASK(95, 80) +#define WRMEM1_181_FLD7 GENMASK(111, 96) +#define WRMEM1_181_FLD8 GENMASK(127, 112) + +/* WRMEM1_182 register fields */ +#define WRMEM1_182_FLD1 GENMASK(15, 0) +#define WRMEM1_182_FLD2 GENMASK(31, 16) +#define WRMEM1_182_FLD3 GENMASK(47, 32) +#define WRMEM1_182_FLD4 GENMASK(63, 48) +#define WRMEM1_182_FLD5 GENMASK(79, 64) +#define WRMEM1_182_FLD6 GENMASK(95, 80) +#define WRMEM1_182_FLD7 GENMASK(111, 96) +#define WRMEM1_182_FLD8 GENMASK(127, 112) + +/* WRMEM1_183 register fields */ +#define WRMEM1_183_FLD1 GENMASK(15, 0) +#define WRMEM1_183_FLD2 GENMASK(31, 16) +#define WRMEM1_183_FLD3 GENMASK(47, 32) +#define WRMEM1_183_FLD4 GENMASK(63, 48) +#define WRMEM1_183_FLD5 GENMASK(79, 64) +#define WRMEM1_183_FLD6 GENMASK(95, 80) +#define WRMEM1_183_FLD7 GENMASK(111, 96) +#define WRMEM1_183_FLD8 GENMASK(127, 112) + +/* WRMEM1_184 register fields */ +#define WRMEM1_184_FLD1 GENMASK(15, 0) +#define WRMEM1_184_FLD2 GENMASK(31, 16) +#define WRMEM1_184_FLD3 GENMASK(47, 32) +#define WRMEM1_184_FLD4 GENMASK(63, 48) +#define WRMEM1_184_FLD5 GENMASK(79, 64) +#define WRMEM1_184_FLD6 GENMASK(95, 80) +#define WRMEM1_184_FLD7 GENMASK(111, 96) +#define WRMEM1_184_FLD8 GENMASK(127, 112) + +/* WRMEM1_185 register fields */ +#define WRMEM1_185_FLD1 GENMASK(15, 0) +#define WRMEM1_185_FLD2 GENMASK(31, 16) +#define WRMEM1_185_FLD3 GENMASK(47, 32) +#define WRMEM1_185_FLD4 GENMASK(63, 48) +#define WRMEM1_185_FLD5 GENMASK(79, 64) +#define WRMEM1_185_FLD6 GENMASK(95, 80) +#define WRMEM1_185_FLD7 GENMASK(111, 96) +#define WRMEM1_185_FLD8 GENMASK(127, 112) + +/* WRMEM1_186 register fields */ +#define WRMEM1_186_FLD1 GENMASK(15, 0) +#define WRMEM1_186_FLD2 GENMASK(31, 16) +#define WRMEM1_186_FLD3 GENMASK(47, 32) +#define WRMEM1_186_FLD4 GENMASK(63, 48) +#define WRMEM1_186_FLD5 GENMASK(79, 64) +#define WRMEM1_186_FLD6 GENMASK(95, 80) +#define WRMEM1_186_FLD7 GENMASK(111, 96) +#define WRMEM1_186_FLD8 GENMASK(127, 112) + +/* WRMEM1_187 register fields */ +#define WRMEM1_187_FLD1 GENMASK(15, 0) +#define WRMEM1_187_FLD2 GENMASK(31, 16) +#define WRMEM1_187_FLD3 GENMASK(47, 32) +#define WRMEM1_187_FLD4 GENMASK(63, 48) +#define WRMEM1_187_FLD5 GENMASK(79, 64) +#define WRMEM1_187_FLD6 GENMASK(95, 80) +#define WRMEM1_187_FLD7 GENMASK(111, 96) +#define WRMEM1_187_FLD8 GENMASK(127, 112) + +/* WRMEM1_188 register fields */ +#define WRMEM1_188_FLD1 GENMASK(15, 0) +#define WRMEM1_188_FLD2 GENMASK(31, 16) +#define WRMEM1_188_FLD3 GENMASK(47, 32) +#define WRMEM1_188_FLD4 GENMASK(63, 48) +#define WRMEM1_188_FLD5 GENMASK(79, 64) +#define WRMEM1_188_FLD6 GENMASK(95, 80) +#define WRMEM1_188_FLD7 GENMASK(111, 96) +#define WRMEM1_188_FLD8 GENMASK(127, 112) + +/* WRMEM1_189 register fields */ +#define WRMEM1_189_FLD1 GENMASK(15, 0) +#define WRMEM1_189_FLD2 GENMASK(31, 16) +#define WRMEM1_189_FLD3 GENMASK(47, 32) +#define WRMEM1_189_FLD4 GENMASK(63, 48) +#define WRMEM1_189_FLD5 GENMASK(79, 64) +#define WRMEM1_189_FLD6 GENMASK(95, 80) +#define WRMEM1_189_FLD7 GENMASK(111, 96) +#define WRMEM1_189_FLD8 GENMASK(127, 112) + +/* WRMEM1_190 register fields */ +#define WRMEM1_190_FLD1 GENMASK(15, 0) +#define WRMEM1_190_FLD2 GENMASK(31, 16) +#define WRMEM1_190_FLD3 GENMASK(47, 32) +#define WRMEM1_190_FLD4 GENMASK(63, 48) +#define WRMEM1_190_FLD5 GENMASK(79, 64) +#define WRMEM1_190_FLD6 GENMASK(95, 80) +#define WRMEM1_190_FLD7 GENMASK(111, 96) +#define WRMEM1_190_FLD8 GENMASK(127, 112) + +/* WRMEM1_191 register fields */ +#define WRMEM1_191_FLD1 GENMASK(15, 0) +#define WRMEM1_191_FLD2 GENMASK(31, 16) +#define WRMEM1_191_FLD3 GENMASK(47, 32) +#define WRMEM1_191_FLD4 GENMASK(63, 48) +#define WRMEM1_191_FLD5 GENMASK(79, 64) +#define WRMEM1_191_FLD6 GENMASK(95, 80) +#define WRMEM1_191_FLD7 GENMASK(111, 96) +#define WRMEM1_191_FLD8 GENMASK(127, 112) + +/* WRMEM1_192 register fields */ +#define WRMEM1_192_FLD1 GENMASK(15, 0) +#define WRMEM1_192_FLD2 GENMASK(31, 16) +#define WRMEM1_192_FLD3 GENMASK(47, 32) +#define WRMEM1_192_FLD4 GENMASK(63, 48) +#define WRMEM1_192_FLD5 GENMASK(79, 64) +#define WRMEM1_192_FLD6 GENMASK(95, 80) +#define WRMEM1_192_FLD7 GENMASK(111, 96) +#define WRMEM1_192_FLD8 GENMASK(127, 112) + +/* WRMEM1_193 register fields */ +#define WRMEM1_193_FLD1 GENMASK(15, 0) +#define WRMEM1_193_FLD2 GENMASK(31, 16) +#define WRMEM1_193_FLD3 GENMASK(47, 32) +#define WRMEM1_193_FLD4 GENMASK(63, 48) +#define WRMEM1_193_FLD5 GENMASK(79, 64) +#define WRMEM1_193_FLD6 GENMASK(95, 80) +#define WRMEM1_193_FLD7 GENMASK(111, 96) +#define WRMEM1_193_FLD8 GENMASK(127, 112) + +/* WRMEM1_194 register fields */ +#define WRMEM1_194_FLD1 GENMASK(15, 0) +#define WRMEM1_194_FLD2 GENMASK(31, 16) +#define WRMEM1_194_FLD3 GENMASK(47, 32) +#define WRMEM1_194_FLD4 GENMASK(63, 48) +#define WRMEM1_194_FLD5 GENMASK(79, 64) +#define WRMEM1_194_FLD6 GENMASK(95, 80) +#define WRMEM1_194_FLD7 GENMASK(111, 96) +#define WRMEM1_194_FLD8 GENMASK(127, 112) + +/* WRMEM1_195 register fields */ +#define WRMEM1_195_FLD1 GENMASK(15, 0) +#define WRMEM1_195_FLD2 GENMASK(31, 16) +#define WRMEM1_195_FLD3 GENMASK(47, 32) +#define WRMEM1_195_FLD4 GENMASK(63, 48) +#define WRMEM1_195_FLD5 GENMASK(79, 64) +#define WRMEM1_195_FLD6 GENMASK(95, 80) +#define WRMEM1_195_FLD7 GENMASK(111, 96) +#define WRMEM1_195_FLD8 GENMASK(127, 112) + +/* WRMEM1_196 register fields */ +#define WRMEM1_196_FLD1 GENMASK(15, 0) +#define WRMEM1_196_FLD2 GENMASK(31, 16) +#define WRMEM1_196_FLD3 GENMASK(47, 32) +#define WRMEM1_196_FLD4 GENMASK(63, 48) +#define WRMEM1_196_FLD5 GENMASK(79, 64) +#define WRMEM1_196_FLD6 GENMASK(95, 80) +#define WRMEM1_196_FLD7 GENMASK(111, 96) +#define WRMEM1_196_FLD8 GENMASK(127, 112) + +/* WRMEM1_197 register fields */ +#define WRMEM1_197_FLD1 GENMASK(15, 0) +#define WRMEM1_197_FLD2 GENMASK(31, 16) +#define WRMEM1_197_FLD3 GENMASK(47, 32) +#define WRMEM1_197_FLD4 GENMASK(63, 48) +#define WRMEM1_197_FLD5 GENMASK(79, 64) +#define WRMEM1_197_FLD6 GENMASK(95, 80) +#define WRMEM1_197_FLD7 GENMASK(111, 96) +#define WRMEM1_197_FLD8 GENMASK(127, 112) + +/* WRMEM1_198 register fields */ +#define WRMEM1_198_FLD1 GENMASK(15, 0) +#define WRMEM1_198_FLD2 GENMASK(31, 16) +#define WRMEM1_198_FLD3 GENMASK(47, 32) +#define WRMEM1_198_FLD4 GENMASK(63, 48) +#define WRMEM1_198_FLD5 GENMASK(79, 64) +#define WRMEM1_198_FLD6 GENMASK(95, 80) +#define WRMEM1_198_FLD7 GENMASK(111, 96) +#define WRMEM1_198_FLD8 GENMASK(127, 112) + +/* WRMEM1_199 register fields */ +#define WRMEM1_199_FLD1 GENMASK(15, 0) +#define WRMEM1_199_FLD2 GENMASK(31, 16) +#define WRMEM1_199_FLD3 GENMASK(47, 32) +#define WRMEM1_199_FLD4 GENMASK(63, 48) +#define WRMEM1_199_FLD5 GENMASK(79, 64) +#define WRMEM1_199_FLD6 GENMASK(95, 80) +#define WRMEM1_199_FLD7 GENMASK(111, 96) +#define WRMEM1_199_FLD8 GENMASK(127, 112) + +/* WRMEM1_200 register fields */ +#define WRMEM1_200_FLD1 GENMASK(15, 0) +#define WRMEM1_200_FLD2 GENMASK(31, 16) +#define WRMEM1_200_FLD3 GENMASK(47, 32) +#define WRMEM1_200_FLD4 GENMASK(63, 48) +#define WRMEM1_200_FLD5 GENMASK(79, 64) +#define WRMEM1_200_FLD6 GENMASK(95, 80) +#define WRMEM1_200_FLD7 GENMASK(111, 96) +#define WRMEM1_200_FLD8 GENMASK(127, 112) + +/* WRMEM1_201 register fields */ +#define WRMEM1_201_FLD1 GENMASK(15, 0) +#define WRMEM1_201_FLD2 GENMASK(31, 16) +#define WRMEM1_201_FLD3 GENMASK(47, 32) +#define WRMEM1_201_FLD4 GENMASK(63, 48) +#define WRMEM1_201_FLD5 GENMASK(79, 64) +#define WRMEM1_201_FLD6 GENMASK(95, 80) +#define WRMEM1_201_FLD7 GENMASK(111, 96) +#define WRMEM1_201_FLD8 GENMASK(127, 112) + +/* WRMEM1_202 register fields */ +#define WRMEM1_202_FLD1 GENMASK(15, 0) +#define WRMEM1_202_FLD2 GENMASK(31, 16) +#define WRMEM1_202_FLD3 GENMASK(47, 32) +#define WRMEM1_202_FLD4 GENMASK(63, 48) +#define WRMEM1_202_FLD5 GENMASK(79, 64) +#define WRMEM1_202_FLD6 GENMASK(95, 80) +#define WRMEM1_202_FLD7 GENMASK(111, 96) +#define WRMEM1_202_FLD8 GENMASK(127, 112) + +/* WRMEM1_203 register fields */ +#define WRMEM1_203_FLD1 GENMASK(15, 0) +#define WRMEM1_203_FLD2 GENMASK(31, 16) +#define WRMEM1_203_FLD3 GENMASK(47, 32) +#define WRMEM1_203_FLD4 GENMASK(63, 48) +#define WRMEM1_203_FLD5 GENMASK(79, 64) +#define WRMEM1_203_FLD6 GENMASK(95, 80) +#define WRMEM1_203_FLD7 GENMASK(111, 96) +#define WRMEM1_203_FLD8 GENMASK(127, 112) + +/* WRMEM1_204 register fields */ +#define WRMEM1_204_FLD1 GENMASK(15, 0) +#define WRMEM1_204_FLD2 GENMASK(31, 16) +#define WRMEM1_204_FLD3 GENMASK(47, 32) +#define WRMEM1_204_FLD4 GENMASK(63, 48) +#define WRMEM1_204_FLD5 GENMASK(79, 64) +#define WRMEM1_204_FLD6 GENMASK(95, 80) +#define WRMEM1_204_FLD7 GENMASK(111, 96) +#define WRMEM1_204_FLD8 GENMASK(127, 112) + +/* WRMEM1_205 register fields */ +#define WRMEM1_205_FLD1 GENMASK(15, 0) +#define WRMEM1_205_FLD2 GENMASK(31, 16) +#define WRMEM1_205_FLD3 GENMASK(47, 32) +#define WRMEM1_205_FLD4 GENMASK(63, 48) +#define WRMEM1_205_FLD5 GENMASK(79, 64) +#define WRMEM1_205_FLD6 GENMASK(95, 80) +#define WRMEM1_205_FLD7 GENMASK(111, 96) +#define WRMEM1_205_FLD8 GENMASK(127, 112) + +/* WRMEM1_206 register fields */ +#define WRMEM1_206_FLD1 GENMASK(15, 0) +#define WRMEM1_206_FLD2 GENMASK(31, 16) +#define WRMEM1_206_FLD3 GENMASK(47, 32) +#define WRMEM1_206_FLD4 GENMASK(63, 48) +#define WRMEM1_206_FLD5 GENMASK(79, 64) +#define WRMEM1_206_FLD6 GENMASK(95, 80) +#define WRMEM1_206_FLD7 GENMASK(111, 96) +#define WRMEM1_206_FLD8 GENMASK(127, 112) + +/* WRMEM1_207 register fields */ +#define WRMEM1_207_FLD1 GENMASK(15, 0) +#define WRMEM1_207_FLD2 GENMASK(31, 16) +#define WRMEM1_207_FLD3 GENMASK(47, 32) +#define WRMEM1_207_FLD4 GENMASK(63, 48) +#define WRMEM1_207_FLD5 GENMASK(79, 64) +#define WRMEM1_207_FLD6 GENMASK(95, 80) +#define WRMEM1_207_FLD7 GENMASK(111, 96) +#define WRMEM1_207_FLD8 GENMASK(127, 112) + +/* WRMEM1_208 register fields */ +#define WRMEM1_208_FLD1 GENMASK(15, 0) +#define WRMEM1_208_FLD2 GENMASK(31, 16) +#define WRMEM1_208_FLD3 GENMASK(47, 32) +#define WRMEM1_208_FLD4 GENMASK(63, 48) +#define WRMEM1_208_FLD5 GENMASK(79, 64) +#define WRMEM1_208_FLD6 GENMASK(95, 80) +#define WRMEM1_208_FLD7 GENMASK(111, 96) +#define WRMEM1_208_FLD8 GENMASK(127, 112) + +/* WRMEM1_209 register fields */ +#define WRMEM1_209_FLD1 GENMASK(15, 0) +#define WRMEM1_209_FLD2 GENMASK(31, 16) +#define WRMEM1_209_FLD3 GENMASK(47, 32) +#define WRMEM1_209_FLD4 GENMASK(63, 48) +#define WRMEM1_209_FLD5 GENMASK(79, 64) +#define WRMEM1_209_FLD6 GENMASK(95, 80) +#define WRMEM1_209_FLD7 GENMASK(111, 96) +#define WRMEM1_209_FLD8 GENMASK(127, 112) + +/* WRMEM1_210 register fields */ +#define WRMEM1_210_FLD1 GENMASK(15, 0) +#define WRMEM1_210_FLD2 GENMASK(31, 16) +#define WRMEM1_210_FLD3 GENMASK(47, 32) +#define WRMEM1_210_FLD4 GENMASK(63, 48) +#define WRMEM1_210_FLD5 GENMASK(79, 64) +#define WRMEM1_210_FLD6 GENMASK(95, 80) +#define WRMEM1_210_FLD7 GENMASK(111, 96) +#define WRMEM1_210_FLD8 GENMASK(127, 112) + +/* WRMEM1_211 register fields */ +#define WRMEM1_211_FLD1 GENMASK(15, 0) +#define WRMEM1_211_FLD2 GENMASK(31, 16) +#define WRMEM1_211_FLD3 GENMASK(47, 32) +#define WRMEM1_211_FLD4 GENMASK(63, 48) +#define WRMEM1_211_FLD5 GENMASK(79, 64) +#define WRMEM1_211_FLD6 GENMASK(95, 80) +#define WRMEM1_211_FLD7 GENMASK(111, 96) +#define WRMEM1_211_FLD8 GENMASK(127, 112) + +/* WRMEM1_212 register fields */ +#define WRMEM1_212_FLD1 GENMASK(15, 0) +#define WRMEM1_212_FLD2 GENMASK(31, 16) +#define WRMEM1_212_FLD3 GENMASK(47, 32) +#define WRMEM1_212_FLD4 GENMASK(63, 48) +#define WRMEM1_212_FLD5 GENMASK(79, 64) +#define WRMEM1_212_FLD6 GENMASK(95, 80) +#define WRMEM1_212_FLD7 GENMASK(111, 96) +#define WRMEM1_212_FLD8 GENMASK(127, 112) + +/* WRMEM1_213 register fields */ +#define WRMEM1_213_FLD1 GENMASK(15, 0) +#define WRMEM1_213_FLD2 GENMASK(31, 16) +#define WRMEM1_213_FLD3 GENMASK(47, 32) +#define WRMEM1_213_FLD4 GENMASK(63, 48) +#define WRMEM1_213_FLD5 GENMASK(79, 64) +#define WRMEM1_213_FLD6 GENMASK(95, 80) +#define WRMEM1_213_FLD7 GENMASK(111, 96) +#define WRMEM1_213_FLD8 GENMASK(127, 112) + +/* WRMEM1_214 register fields */ +#define WRMEM1_214_FLD1 GENMASK(15, 0) +#define WRMEM1_214_FLD2 GENMASK(31, 16) +#define WRMEM1_214_FLD3 GENMASK(47, 32) +#define WRMEM1_214_FLD4 GENMASK(63, 48) +#define WRMEM1_214_FLD5 GENMASK(79, 64) +#define WRMEM1_214_FLD6 GENMASK(95, 80) +#define WRMEM1_214_FLD7 GENMASK(111, 96) +#define WRMEM1_214_FLD8 GENMASK(127, 112) + +/* WRMEM1_215 register fields */ +#define WRMEM1_215_FLD1 GENMASK(15, 0) +#define WRMEM1_215_FLD2 GENMASK(31, 16) +#define WRMEM1_215_FLD3 GENMASK(47, 32) +#define WRMEM1_215_FLD4 GENMASK(63, 48) +#define WRMEM1_215_FLD5 GENMASK(79, 64) +#define WRMEM1_215_FLD6 GENMASK(95, 80) +#define WRMEM1_215_FLD7 GENMASK(111, 96) +#define WRMEM1_215_FLD8 GENMASK(127, 112) + +/* WRMEM1_216 register fields */ +#define WRMEM1_216_FLD1 GENMASK(15, 0) +#define WRMEM1_216_FLD2 GENMASK(31, 16) +#define WRMEM1_216_FLD3 GENMASK(47, 32) +#define WRMEM1_216_FLD4 GENMASK(63, 48) +#define WRMEM1_216_FLD5 GENMASK(79, 64) +#define WRMEM1_216_FLD6 GENMASK(95, 80) +#define WRMEM1_216_FLD7 GENMASK(111, 96) +#define WRMEM1_216_FLD8 GENMASK(127, 112) + +/* WRMEM1_217 register fields */ +#define WRMEM1_217_FLD1 GENMASK(15, 0) +#define WRMEM1_217_FLD2 GENMASK(31, 16) +#define WRMEM1_217_FLD3 GENMASK(47, 32) +#define WRMEM1_217_FLD4 GENMASK(63, 48) +#define WRMEM1_217_FLD5 GENMASK(79, 64) +#define WRMEM1_217_FLD6 GENMASK(95, 80) +#define WRMEM1_217_FLD7 GENMASK(111, 96) +#define WRMEM1_217_FLD8 GENMASK(127, 112) + +/* WRMEM1_218 register fields */ +#define WRMEM1_218_FLD1 GENMASK(15, 0) +#define WRMEM1_218_FLD2 GENMASK(31, 16) +#define WRMEM1_218_FLD3 GENMASK(47, 32) +#define WRMEM1_218_FLD4 GENMASK(63, 48) +#define WRMEM1_218_FLD5 GENMASK(79, 64) +#define WRMEM1_218_FLD6 GENMASK(95, 80) +#define WRMEM1_218_FLD7 GENMASK(111, 96) +#define WRMEM1_218_FLD8 GENMASK(127, 112) + +/* WRMEM1_219 register fields */ +#define WRMEM1_219_FLD1 GENMASK(15, 0) +#define WRMEM1_219_FLD2 GENMASK(31, 16) +#define WRMEM1_219_FLD3 GENMASK(47, 32) +#define WRMEM1_219_FLD4 GENMASK(63, 48) +#define WRMEM1_219_FLD5 GENMASK(79, 64) +#define WRMEM1_219_FLD6 GENMASK(95, 80) +#define WRMEM1_219_FLD7 GENMASK(111, 96) +#define WRMEM1_219_FLD8 GENMASK(127, 112) + +/* WRMEM1_220 register fields */ +#define WRMEM1_220_FLD1 GENMASK(15, 0) +#define WRMEM1_220_FLD2 GENMASK(31, 16) +#define WRMEM1_220_FLD3 GENMASK(47, 32) +#define WRMEM1_220_FLD4 GENMASK(63, 48) +#define WRMEM1_220_FLD5 GENMASK(79, 64) +#define WRMEM1_220_FLD6 GENMASK(95, 80) +#define WRMEM1_220_FLD7 GENMASK(111, 96) +#define WRMEM1_220_FLD8 GENMASK(127, 112) + +/* WRMEM1_221 register fields */ +#define WRMEM1_221_FLD1 GENMASK(15, 0) +#define WRMEM1_221_FLD2 GENMASK(31, 16) +#define WRMEM1_221_FLD3 GENMASK(47, 32) +#define WRMEM1_221_FLD4 GENMASK(63, 48) +#define WRMEM1_221_FLD5 GENMASK(79, 64) +#define WRMEM1_221_FLD6 GENMASK(95, 80) +#define WRMEM1_221_FLD7 GENMASK(111, 96) +#define WRMEM1_221_FLD8 GENMASK(127, 112) + +/* WRMEM1_222 register fields */ +#define WRMEM1_222_FLD1 GENMASK(15, 0) +#define WRMEM1_222_FLD2 GENMASK(31, 16) +#define WRMEM1_222_FLD3 GENMASK(47, 32) +#define WRMEM1_222_FLD4 GENMASK(63, 48) +#define WRMEM1_222_FLD5 GENMASK(79, 64) +#define WRMEM1_222_FLD6 GENMASK(95, 80) +#define WRMEM1_222_FLD7 GENMASK(111, 96) +#define WRMEM1_222_FLD8 GENMASK(127, 112) + +/* WRMEM1_223 register fields */ +#define WRMEM1_223_FLD1 GENMASK(15, 0) +#define WRMEM1_223_FLD2 GENMASK(31, 16) +#define WRMEM1_223_FLD3 GENMASK(47, 32) +#define WRMEM1_223_FLD4 GENMASK(63, 48) +#define WRMEM1_223_FLD5 GENMASK(79, 64) +#define WRMEM1_223_FLD6 GENMASK(95, 80) +#define WRMEM1_223_FLD7 GENMASK(111, 96) +#define WRMEM1_223_FLD8 GENMASK(127, 112) + +/* WRMEM1_224 register fields */ +#define WRMEM1_224_FLD1 GENMASK(15, 0) +#define WRMEM1_224_FLD2 GENMASK(31, 16) +#define WRMEM1_224_FLD3 GENMASK(47, 32) +#define WRMEM1_224_FLD4 GENMASK(63, 48) +#define WRMEM1_224_FLD5 GENMASK(79, 64) +#define WRMEM1_224_FLD6 GENMASK(95, 80) +#define WRMEM1_224_FLD7 GENMASK(111, 96) +#define WRMEM1_224_FLD8 GENMASK(127, 112) + +/* WRMEM1_225 register fields */ +#define WRMEM1_225_FLD1 GENMASK(15, 0) +#define WRMEM1_225_FLD2 GENMASK(31, 16) +#define WRMEM1_225_FLD3 GENMASK(47, 32) +#define WRMEM1_225_FLD4 GENMASK(63, 48) +#define WRMEM1_225_FLD5 GENMASK(79, 64) +#define WRMEM1_225_FLD6 GENMASK(95, 80) +#define WRMEM1_225_FLD7 GENMASK(111, 96) +#define WRMEM1_225_FLD8 GENMASK(127, 112) + +/* WRMEM1_226 register fields */ +#define WRMEM1_226_FLD1 GENMASK(15, 0) +#define WRMEM1_226_FLD2 GENMASK(31, 16) +#define WRMEM1_226_FLD3 GENMASK(47, 32) +#define WRMEM1_226_FLD4 GENMASK(63, 48) +#define WRMEM1_226_FLD5 GENMASK(79, 64) +#define WRMEM1_226_FLD6 GENMASK(95, 80) +#define WRMEM1_226_FLD7 GENMASK(111, 96) +#define WRMEM1_226_FLD8 GENMASK(127, 112) + +/* WRMEM1_227 register fields */ +#define WRMEM1_227_FLD1 GENMASK(15, 0) +#define WRMEM1_227_FLD2 GENMASK(31, 16) +#define WRMEM1_227_FLD3 GENMASK(47, 32) +#define WRMEM1_227_FLD4 GENMASK(63, 48) +#define WRMEM1_227_FLD5 GENMASK(79, 64) +#define WRMEM1_227_FLD6 GENMASK(95, 80) +#define WRMEM1_227_FLD7 GENMASK(111, 96) +#define WRMEM1_227_FLD8 GENMASK(127, 112) + +/* WRMEM1_228 register fields */ +#define WRMEM1_228_FLD1 GENMASK(15, 0) +#define WRMEM1_228_FLD2 GENMASK(31, 16) +#define WRMEM1_228_FLD3 GENMASK(47, 32) +#define WRMEM1_228_FLD4 GENMASK(63, 48) +#define WRMEM1_228_FLD5 GENMASK(79, 64) +#define WRMEM1_228_FLD6 GENMASK(95, 80) +#define WRMEM1_228_FLD7 GENMASK(111, 96) +#define WRMEM1_228_FLD8 GENMASK(127, 112) + +/* WRMEM1_229 register fields */ +#define WRMEM1_229_FLD1 GENMASK(15, 0) +#define WRMEM1_229_FLD2 GENMASK(31, 16) +#define WRMEM1_229_FLD3 GENMASK(47, 32) +#define WRMEM1_229_FLD4 GENMASK(63, 48) +#define WRMEM1_229_FLD5 GENMASK(79, 64) +#define WRMEM1_229_FLD6 GENMASK(95, 80) +#define WRMEM1_229_FLD7 GENMASK(111, 96) +#define WRMEM1_229_FLD8 GENMASK(127, 112) + +/* WRMEM1_230 register fields */ +#define WRMEM1_230_FLD1 GENMASK(15, 0) +#define WRMEM1_230_FLD2 GENMASK(31, 16) +#define WRMEM1_230_FLD3 GENMASK(47, 32) +#define WRMEM1_230_FLD4 GENMASK(63, 48) +#define WRMEM1_230_FLD5 GENMASK(79, 64) +#define WRMEM1_230_FLD6 GENMASK(95, 80) +#define WRMEM1_230_FLD7 GENMASK(111, 96) +#define WRMEM1_230_FLD8 GENMASK(127, 112) + +/* WRMEM1_231 register fields */ +#define WRMEM1_231_FLD1 GENMASK(15, 0) +#define WRMEM1_231_FLD2 GENMASK(31, 16) +#define WRMEM1_231_FLD3 GENMASK(47, 32) +#define WRMEM1_231_FLD4 GENMASK(63, 48) +#define WRMEM1_231_FLD5 GENMASK(79, 64) +#define WRMEM1_231_FLD6 GENMASK(95, 80) +#define WRMEM1_231_FLD7 GENMASK(111, 96) +#define WRMEM1_231_FLD8 GENMASK(127, 112) + +/* WRMEM1_232 register fields */ +#define WRMEM1_232_FLD1 GENMASK(15, 0) +#define WRMEM1_232_FLD2 GENMASK(31, 16) +#define WRMEM1_232_FLD3 GENMASK(47, 32) +#define WRMEM1_232_FLD4 GENMASK(63, 48) +#define WRMEM1_232_FLD5 GENMASK(79, 64) +#define WRMEM1_232_FLD6 GENMASK(95, 80) +#define WRMEM1_232_FLD7 GENMASK(111, 96) +#define WRMEM1_232_FLD8 GENMASK(127, 112) + +/* WRMEM1_233 register fields */ +#define WRMEM1_233_FLD1 GENMASK(15, 0) +#define WRMEM1_233_FLD2 GENMASK(31, 16) +#define WRMEM1_233_FLD3 GENMASK(47, 32) +#define WRMEM1_233_FLD4 GENMASK(63, 48) +#define WRMEM1_233_FLD5 GENMASK(79, 64) +#define WRMEM1_233_FLD6 GENMASK(95, 80) +#define WRMEM1_233_FLD7 GENMASK(111, 96) +#define WRMEM1_233_FLD8 GENMASK(127, 112) + +/* WRMEM1_234 register fields */ +#define WRMEM1_234_FLD1 GENMASK(15, 0) +#define WRMEM1_234_FLD2 GENMASK(31, 16) +#define WRMEM1_234_FLD3 GENMASK(47, 32) +#define WRMEM1_234_FLD4 GENMASK(63, 48) +#define WRMEM1_234_FLD5 GENMASK(79, 64) +#define WRMEM1_234_FLD6 GENMASK(95, 80) +#define WRMEM1_234_FLD7 GENMASK(111, 96) +#define WRMEM1_234_FLD8 GENMASK(127, 112) + +/* WRMEM1_235 register fields */ +#define WRMEM1_235_FLD1 GENMASK(15, 0) +#define WRMEM1_235_FLD2 GENMASK(31, 16) +#define WRMEM1_235_FLD3 GENMASK(47, 32) +#define WRMEM1_235_FLD4 GENMASK(63, 48) +#define WRMEM1_235_FLD5 GENMASK(79, 64) +#define WRMEM1_235_FLD6 GENMASK(95, 80) +#define WRMEM1_235_FLD7 GENMASK(111, 96) +#define WRMEM1_235_FLD8 GENMASK(127, 112) + +/* WRMEM1_236 register fields */ +#define WRMEM1_236_FLD1 GENMASK(15, 0) +#define WRMEM1_236_FLD2 GENMASK(31, 16) +#define WRMEM1_236_FLD3 GENMASK(47, 32) +#define WRMEM1_236_FLD4 GENMASK(63, 48) +#define WRMEM1_236_FLD5 GENMASK(79, 64) +#define WRMEM1_236_FLD6 GENMASK(95, 80) +#define WRMEM1_236_FLD7 GENMASK(111, 96) +#define WRMEM1_236_FLD8 GENMASK(127, 112) + +/* WRMEM1_237 register fields */ +#define WRMEM1_237_FLD1 GENMASK(15, 0) +#define WRMEM1_237_FLD2 GENMASK(31, 16) +#define WRMEM1_237_FLD3 GENMASK(47, 32) +#define WRMEM1_237_FLD4 GENMASK(63, 48) +#define WRMEM1_237_FLD5 GENMASK(79, 64) +#define WRMEM1_237_FLD6 GENMASK(95, 80) +#define WRMEM1_237_FLD7 GENMASK(111, 96) +#define WRMEM1_237_FLD8 GENMASK(127, 112) + +/* WRMEM1_238 register fields */ +#define WRMEM1_238_FLD1 GENMASK(15, 0) +#define WRMEM1_238_FLD2 GENMASK(31, 16) +#define WRMEM1_238_FLD3 GENMASK(47, 32) +#define WRMEM1_238_FLD4 GENMASK(63, 48) +#define WRMEM1_238_FLD5 GENMASK(79, 64) +#define WRMEM1_238_FLD6 GENMASK(95, 80) +#define WRMEM1_238_FLD7 GENMASK(111, 96) +#define WRMEM1_238_FLD8 GENMASK(127, 112) + +/* WRMEM1_239 register fields */ +#define WRMEM1_239_FLD1 GENMASK(15, 0) +#define WRMEM1_239_FLD2 GENMASK(31, 16) +#define WRMEM1_239_FLD3 GENMASK(47, 32) +#define WRMEM1_239_FLD4 GENMASK(63, 48) +#define WRMEM1_239_FLD5 GENMASK(79, 64) +#define WRMEM1_239_FLD6 GENMASK(95, 80) +#define WRMEM1_239_FLD7 GENMASK(111, 96) +#define WRMEM1_239_FLD8 GENMASK(127, 112) + +/* WRMEM1_240 register fields */ +#define WRMEM1_240_FLD1 GENMASK(15, 0) +#define WRMEM1_240_FLD2 GENMASK(31, 16) +#define WRMEM1_240_FLD3 GENMASK(47, 32) +#define WRMEM1_240_FLD4 GENMASK(63, 48) +#define WRMEM1_240_FLD5 GENMASK(79, 64) +#define WRMEM1_240_FLD6 GENMASK(95, 80) +#define WRMEM1_240_FLD7 GENMASK(111, 96) +#define WRMEM1_240_FLD8 GENMASK(127, 112) + +/* WRMEM1_241 register fields */ +#define WRMEM1_241_FLD1 GENMASK(15, 0) +#define WRMEM1_241_FLD2 GENMASK(31, 16) +#define WRMEM1_241_FLD3 GENMASK(47, 32) +#define WRMEM1_241_FLD4 GENMASK(63, 48) +#define WRMEM1_241_FLD5 GENMASK(79, 64) +#define WRMEM1_241_FLD6 GENMASK(95, 80) +#define WRMEM1_241_FLD7 GENMASK(111, 96) +#define WRMEM1_241_FLD8 GENMASK(127, 112) + +/* WRMEM1_242 register fields */ +#define WRMEM1_242_FLD1 GENMASK(15, 0) +#define WRMEM1_242_FLD2 GENMASK(31, 16) +#define WRMEM1_242_FLD3 GENMASK(47, 32) +#define WRMEM1_242_FLD4 GENMASK(63, 48) +#define WRMEM1_242_FLD5 GENMASK(79, 64) +#define WRMEM1_242_FLD6 GENMASK(95, 80) +#define WRMEM1_242_FLD7 GENMASK(111, 96) +#define WRMEM1_242_FLD8 GENMASK(127, 112) + +/* WRMEM1_243 register fields */ +#define WRMEM1_243_FLD1 GENMASK(15, 0) +#define WRMEM1_243_FLD2 GENMASK(31, 16) +#define WRMEM1_243_FLD3 GENMASK(47, 32) +#define WRMEM1_243_FLD4 GENMASK(63, 48) +#define WRMEM1_243_FLD5 GENMASK(79, 64) +#define WRMEM1_243_FLD6 GENMASK(95, 80) +#define WRMEM1_243_FLD7 GENMASK(111, 96) +#define WRMEM1_243_FLD8 GENMASK(127, 112) + +/* WRMEM1_244 register fields */ +#define WRMEM1_244_FLD1 GENMASK(15, 0) +#define WRMEM1_244_FLD2 GENMASK(31, 16) +#define WRMEM1_244_FLD3 GENMASK(47, 32) +#define WRMEM1_244_FLD4 GENMASK(63, 48) +#define WRMEM1_244_FLD5 GENMASK(79, 64) +#define WRMEM1_244_FLD6 GENMASK(95, 80) +#define WRMEM1_244_FLD7 GENMASK(111, 96) +#define WRMEM1_244_FLD8 GENMASK(127, 112) + +/* WRMEM1_245 register fields */ +#define WRMEM1_245_FLD1 GENMASK(15, 0) +#define WRMEM1_245_FLD2 GENMASK(31, 16) +#define WRMEM1_245_FLD3 GENMASK(47, 32) +#define WRMEM1_245_FLD4 GENMASK(63, 48) +#define WRMEM1_245_FLD5 GENMASK(79, 64) +#define WRMEM1_245_FLD6 GENMASK(95, 80) +#define WRMEM1_245_FLD7 GENMASK(111, 96) +#define WRMEM1_245_FLD8 GENMASK(127, 112) + +/* WRMEM1_246 register fields */ +#define WRMEM1_246_FLD1 GENMASK(15, 0) +#define WRMEM1_246_FLD2 GENMASK(31, 16) +#define WRMEM1_246_FLD3 GENMASK(47, 32) +#define WRMEM1_246_FLD4 GENMASK(63, 48) +#define WRMEM1_246_FLD5 GENMASK(79, 64) +#define WRMEM1_246_FLD6 GENMASK(95, 80) +#define WRMEM1_246_FLD7 GENMASK(111, 96) +#define WRMEM1_246_FLD8 GENMASK(127, 112) + +/* WRMEM1_247 register fields */ +#define WRMEM1_247_FLD1 GENMASK(15, 0) +#define WRMEM1_247_FLD2 GENMASK(31, 16) +#define WRMEM1_247_FLD3 GENMASK(47, 32) +#define WRMEM1_247_FLD4 GENMASK(63, 48) +#define WRMEM1_247_FLD5 GENMASK(79, 64) +#define WRMEM1_247_FLD6 GENMASK(95, 80) +#define WRMEM1_247_FLD7 GENMASK(111, 96) +#define WRMEM1_247_FLD8 GENMASK(127, 112) + +/* WRMEM1_248 register fields */ +#define WRMEM1_248_FLD1 GENMASK(15, 0) +#define WRMEM1_248_FLD2 GENMASK(31, 16) +#define WRMEM1_248_FLD3 GENMASK(47, 32) +#define WRMEM1_248_FLD4 GENMASK(63, 48) +#define WRMEM1_248_FLD5 GENMASK(79, 64) +#define WRMEM1_248_FLD6 GENMASK(95, 80) +#define WRMEM1_248_FLD7 GENMASK(111, 96) +#define WRMEM1_248_FLD8 GENMASK(127, 112) + +/* WRMEM1_249 register fields */ +#define WRMEM1_249_FLD1 GENMASK(15, 0) +#define WRMEM1_249_FLD2 GENMASK(31, 16) +#define WRMEM1_249_FLD3 GENMASK(47, 32) +#define WRMEM1_249_FLD4 GENMASK(63, 48) +#define WRMEM1_249_FLD5 GENMASK(79, 64) +#define WRMEM1_249_FLD6 GENMASK(95, 80) +#define WRMEM1_249_FLD7 GENMASK(111, 96) +#define WRMEM1_249_FLD8 GENMASK(127, 112) + +/* WRMEM1_250 register fields */ +#define WRMEM1_250_FLD1 GENMASK(15, 0) +#define WRMEM1_250_FLD2 GENMASK(31, 16) +#define WRMEM1_250_FLD3 GENMASK(47, 32) +#define WRMEM1_250_FLD4 GENMASK(63, 48) +#define WRMEM1_250_FLD5 GENMASK(79, 64) +#define WRMEM1_250_FLD6 GENMASK(95, 80) +#define WRMEM1_250_FLD7 GENMASK(111, 96) +#define WRMEM1_250_FLD8 GENMASK(127, 112) + +/* WRMEM1_251 register fields */ +#define WRMEM1_251_FLD1 GENMASK(15, 0) +#define WRMEM1_251_FLD2 GENMASK(31, 16) +#define WRMEM1_251_FLD3 GENMASK(47, 32) +#define WRMEM1_251_FLD4 GENMASK(63, 48) +#define WRMEM1_251_FLD5 GENMASK(79, 64) +#define WRMEM1_251_FLD6 GENMASK(95, 80) +#define WRMEM1_251_FLD7 GENMASK(111, 96) +#define WRMEM1_251_FLD8 GENMASK(127, 112) + +/* WRMEM1_252 register fields */ +#define WRMEM1_252_FLD1 GENMASK(15, 0) +#define WRMEM1_252_FLD2 GENMASK(31, 16) +#define WRMEM1_252_FLD3 GENMASK(47, 32) +#define WRMEM1_252_FLD4 GENMASK(63, 48) +#define WRMEM1_252_FLD5 GENMASK(79, 64) +#define WRMEM1_252_FLD6 GENMASK(95, 80) +#define WRMEM1_252_FLD7 GENMASK(111, 96) +#define WRMEM1_252_FLD8 GENMASK(127, 112) + +/* WRMEM1_253 register fields */ +#define WRMEM1_253_FLD1 GENMASK(15, 0) +#define WRMEM1_253_FLD2 GENMASK(31, 16) +#define WRMEM1_253_FLD3 GENMASK(47, 32) +#define WRMEM1_253_FLD4 GENMASK(63, 48) +#define WRMEM1_253_FLD5 GENMASK(79, 64) +#define WRMEM1_253_FLD6 GENMASK(95, 80) +#define WRMEM1_253_FLD7 GENMASK(111, 96) +#define WRMEM1_253_FLD8 GENMASK(127, 112) + +/* WRMEM1_254 register fields */ +#define WRMEM1_254_FLD1 GENMASK(15, 0) +#define WRMEM1_254_FLD2 GENMASK(31, 16) +#define WRMEM1_254_FLD3 GENMASK(47, 32) +#define WRMEM1_254_FLD4 GENMASK(63, 48) +#define WRMEM1_254_FLD5 GENMASK(79, 64) +#define WRMEM1_254_FLD6 GENMASK(95, 80) +#define WRMEM1_254_FLD7 GENMASK(111, 96) +#define WRMEM1_254_FLD8 GENMASK(127, 112) + +/* WRMEM1_255 register fields */ +#define WRMEM1_255_FLD1 GENMASK(15, 0) +#define WRMEM1_255_FLD2 GENMASK(31, 16) +#define WRMEM1_255_FLD3 GENMASK(47, 32) +#define WRMEM1_255_FLD4 GENMASK(63, 48) +#define WRMEM1_255_FLD5 GENMASK(79, 64) +#define WRMEM1_255_FLD6 GENMASK(95, 80) +#define WRMEM1_255_FLD7 GENMASK(111, 96) +#define WRMEM1_255_FLD8 GENMASK(127, 112) + +/* WRMEM1_256 register fields */ +#define WRMEM1_256_FLD1 GENMASK(15, 0) +#define WRMEM1_256_FLD2 GENMASK(31, 16) +#define WRMEM1_256_FLD3 GENMASK(47, 32) +#define WRMEM1_256_FLD4 GENMASK(63, 48) +#define WRMEM1_256_FLD5 GENMASK(79, 64) +#define WRMEM1_256_FLD6 GENMASK(95, 80) +#define WRMEM1_256_FLD7 GENMASK(111, 96) +#define WRMEM1_256_FLD8 GENMASK(127, 112) + +/* WRMEM1_257 register fields */ +#define WRMEM1_257_FLD1 GENMASK(15, 0) +#define WRMEM1_257_FLD2 GENMASK(31, 16) +#define WRMEM1_257_FLD3 GENMASK(47, 32) +#define WRMEM1_257_FLD4 GENMASK(63, 48) +#define WRMEM1_257_FLD5 GENMASK(79, 64) +#define WRMEM1_257_FLD6 GENMASK(95, 80) +#define WRMEM1_257_FLD7 GENMASK(111, 96) +#define WRMEM1_257_FLD8 GENMASK(127, 112) + +/* WRMEM1_258 register fields */ +#define WRMEM1_258_FLD1 GENMASK(15, 0) +#define WRMEM1_258_FLD2 GENMASK(31, 16) +#define WRMEM1_258_FLD3 GENMASK(47, 32) +#define WRMEM1_258_FLD4 GENMASK(63, 48) +#define WRMEM1_258_FLD5 GENMASK(79, 64) +#define WRMEM1_258_FLD6 GENMASK(95, 80) +#define WRMEM1_258_FLD7 GENMASK(111, 96) +#define WRMEM1_258_FLD8 GENMASK(127, 112) + +/* WRMEM1_259 register fields */ +#define WRMEM1_259_FLD1 GENMASK(15, 0) +#define WRMEM1_259_FLD2 GENMASK(31, 16) +#define WRMEM1_259_FLD3 GENMASK(47, 32) +#define WRMEM1_259_FLD4 GENMASK(63, 48) +#define WRMEM1_259_FLD5 GENMASK(79, 64) +#define WRMEM1_259_FLD6 GENMASK(95, 80) +#define WRMEM1_259_FLD7 GENMASK(111, 96) +#define WRMEM1_259_FLD8 GENMASK(127, 112) + +/* WRMEM1_260 register fields */ +#define WRMEM1_260_FLD1 GENMASK(15, 0) +#define WRMEM1_260_FLD2 GENMASK(31, 16) +#define WRMEM1_260_FLD3 GENMASK(47, 32) +#define WRMEM1_260_FLD4 GENMASK(63, 48) +#define WRMEM1_260_FLD5 GENMASK(79, 64) +#define WRMEM1_260_FLD6 GENMASK(95, 80) +#define WRMEM1_260_FLD7 GENMASK(111, 96) +#define WRMEM1_260_FLD8 GENMASK(127, 112) + +/* WRMEM1_261 register fields */ +#define WRMEM1_261_FLD1 GENMASK(15, 0) +#define WRMEM1_261_FLD2 GENMASK(31, 16) +#define WRMEM1_261_FLD3 GENMASK(47, 32) +#define WRMEM1_261_FLD4 GENMASK(63, 48) +#define WRMEM1_261_FLD5 GENMASK(79, 64) +#define WRMEM1_261_FLD6 GENMASK(95, 80) +#define WRMEM1_261_FLD7 GENMASK(111, 96) +#define WRMEM1_261_FLD8 GENMASK(127, 112) + +/* WRMEM1_262 register fields */ +#define WRMEM1_262_FLD1 GENMASK(15, 0) +#define WRMEM1_262_FLD2 GENMASK(31, 16) +#define WRMEM1_262_FLD3 GENMASK(47, 32) +#define WRMEM1_262_FLD4 GENMASK(63, 48) +#define WRMEM1_262_FLD5 GENMASK(79, 64) +#define WRMEM1_262_FLD6 GENMASK(95, 80) +#define WRMEM1_262_FLD7 GENMASK(111, 96) +#define WRMEM1_262_FLD8 GENMASK(127, 112) + +/* WRMEM1_263 register fields */ +#define WRMEM1_263_FLD1 GENMASK(15, 0) +#define WRMEM1_263_FLD2 GENMASK(31, 16) +#define WRMEM1_263_FLD3 GENMASK(47, 32) +#define WRMEM1_263_FLD4 GENMASK(63, 48) +#define WRMEM1_263_FLD5 GENMASK(79, 64) +#define WRMEM1_263_FLD6 GENMASK(95, 80) +#define WRMEM1_263_FLD7 GENMASK(111, 96) +#define WRMEM1_263_FLD8 GENMASK(127, 112) + +/* WRMEM1_264 register fields */ +#define WRMEM1_264_FLD1 GENMASK(15, 0) +#define WRMEM1_264_FLD2 GENMASK(31, 16) +#define WRMEM1_264_FLD3 GENMASK(47, 32) +#define WRMEM1_264_FLD4 GENMASK(63, 48) +#define WRMEM1_264_FLD5 GENMASK(79, 64) +#define WRMEM1_264_FLD6 GENMASK(95, 80) +#define WRMEM1_264_FLD7 GENMASK(111, 96) +#define WRMEM1_264_FLD8 GENMASK(127, 112) + +/* WRMEM1_265 register fields */ +#define WRMEM1_265_FLD1 GENMASK(15, 0) +#define WRMEM1_265_FLD2 GENMASK(31, 16) +#define WRMEM1_265_FLD3 GENMASK(47, 32) +#define WRMEM1_265_FLD4 GENMASK(63, 48) +#define WRMEM1_265_FLD5 GENMASK(79, 64) +#define WRMEM1_265_FLD6 GENMASK(95, 80) +#define WRMEM1_265_FLD7 GENMASK(111, 96) +#define WRMEM1_265_FLD8 GENMASK(127, 112) + +/* WRMEM1_266 register fields */ +#define WRMEM1_266_FLD1 GENMASK(15, 0) +#define WRMEM1_266_FLD2 GENMASK(31, 16) +#define WRMEM1_266_FLD3 GENMASK(47, 32) +#define WRMEM1_266_FLD4 GENMASK(63, 48) +#define WRMEM1_266_FLD5 GENMASK(79, 64) +#define WRMEM1_266_FLD6 GENMASK(95, 80) +#define WRMEM1_266_FLD7 GENMASK(111, 96) +#define WRMEM1_266_FLD8 GENMASK(127, 112) + +/* WRMEM1_267 register fields */ +#define WRMEM1_267_FLD1 GENMASK(15, 0) +#define WRMEM1_267_FLD2 GENMASK(31, 16) +#define WRMEM1_267_FLD3 GENMASK(47, 32) +#define WRMEM1_267_FLD4 GENMASK(63, 48) +#define WRMEM1_267_FLD5 GENMASK(79, 64) +#define WRMEM1_267_FLD6 GENMASK(95, 80) +#define WRMEM1_267_FLD7 GENMASK(111, 96) +#define WRMEM1_267_FLD8 GENMASK(127, 112) + +/* WRMEM1_268 register fields */ +#define WRMEM1_268_FLD1 GENMASK(15, 0) +#define WRMEM1_268_FLD2 GENMASK(31, 16) +#define WRMEM1_268_FLD3 GENMASK(47, 32) +#define WRMEM1_268_FLD4 GENMASK(63, 48) +#define WRMEM1_268_FLD5 GENMASK(79, 64) +#define WRMEM1_268_FLD6 GENMASK(95, 80) +#define WRMEM1_268_FLD7 GENMASK(111, 96) +#define WRMEM1_268_FLD8 GENMASK(127, 112) + +/* WRMEM1_269 register fields */ +#define WRMEM1_269_FLD1 GENMASK(15, 0) +#define WRMEM1_269_FLD2 GENMASK(31, 16) +#define WRMEM1_269_FLD3 GENMASK(47, 32) +#define WRMEM1_269_FLD4 GENMASK(63, 48) +#define WRMEM1_269_FLD5 GENMASK(79, 64) +#define WRMEM1_269_FLD6 GENMASK(95, 80) +#define WRMEM1_269_FLD7 GENMASK(111, 96) +#define WRMEM1_269_FLD8 GENMASK(127, 112) + +/* WRMEM1_270 register fields */ +#define WRMEM1_270_FLD1 GENMASK(15, 0) +#define WRMEM1_270_FLD2 GENMASK(31, 16) +#define WRMEM1_270_FLD3 GENMASK(47, 32) +#define WRMEM1_270_FLD4 GENMASK(63, 48) +#define WRMEM1_270_FLD5 GENMASK(79, 64) +#define WRMEM1_270_FLD6 GENMASK(95, 80) +#define WRMEM1_270_FLD7 GENMASK(111, 96) +#define WRMEM1_270_FLD8 GENMASK(127, 112) + +/* WRMEM1_271 register fields */ +#define WRMEM1_271_FLD1 GENMASK(15, 0) +#define WRMEM1_271_FLD2 GENMASK(31, 16) +#define WRMEM1_271_FLD3 GENMASK(47, 32) +#define WRMEM1_271_FLD4 GENMASK(63, 48) +#define WRMEM1_271_FLD5 GENMASK(79, 64) +#define WRMEM1_271_FLD6 GENMASK(95, 80) +#define WRMEM1_271_FLD7 GENMASK(111, 96) +#define WRMEM1_271_FLD8 GENMASK(127, 112) + +/* WRMEM1_272 register fields */ +#define WRMEM1_272_FLD1 GENMASK(15, 0) +#define WRMEM1_272_FLD2 GENMASK(31, 16) +#define WRMEM1_272_FLD3 GENMASK(47, 32) +#define WRMEM1_272_FLD4 GENMASK(63, 48) +#define WRMEM1_272_FLD5 GENMASK(79, 64) +#define WRMEM1_272_FLD6 GENMASK(95, 80) +#define WRMEM1_272_FLD7 GENMASK(111, 96) +#define WRMEM1_272_FLD8 GENMASK(127, 112) + +/* WRMEM1_273 register fields */ +#define WRMEM1_273_FLD1 GENMASK(15, 0) +#define WRMEM1_273_FLD2 GENMASK(31, 16) +#define WRMEM1_273_FLD3 GENMASK(47, 32) +#define WRMEM1_273_FLD4 GENMASK(63, 48) +#define WRMEM1_273_FLD5 GENMASK(79, 64) +#define WRMEM1_273_FLD6 GENMASK(95, 80) +#define WRMEM1_273_FLD7 GENMASK(111, 96) +#define WRMEM1_273_FLD8 GENMASK(127, 112) + +/* WRMEM1_274 register fields */ +#define WRMEM1_274_FLD1 GENMASK(15, 0) +#define WRMEM1_274_FLD2 GENMASK(31, 16) +#define WRMEM1_274_FLD3 GENMASK(47, 32) +#define WRMEM1_274_FLD4 GENMASK(63, 48) +#define WRMEM1_274_FLD5 GENMASK(79, 64) +#define WRMEM1_274_FLD6 GENMASK(95, 80) +#define WRMEM1_274_FLD7 GENMASK(111, 96) +#define WRMEM1_274_FLD8 GENMASK(127, 112) + +/* WRMEM1_275 register fields */ +#define WRMEM1_275_FLD1 GENMASK(15, 0) +#define WRMEM1_275_FLD2 GENMASK(31, 16) +#define WRMEM1_275_FLD3 GENMASK(47, 32) +#define WRMEM1_275_FLD4 GENMASK(63, 48) +#define WRMEM1_275_FLD5 GENMASK(79, 64) +#define WRMEM1_275_FLD6 GENMASK(95, 80) +#define WRMEM1_275_FLD7 GENMASK(111, 96) +#define WRMEM1_275_FLD8 GENMASK(127, 112) + +/* WRMEM1_276 register fields */ +#define WRMEM1_276_FLD1 GENMASK(15, 0) +#define WRMEM1_276_FLD2 GENMASK(31, 16) +#define WRMEM1_276_FLD3 GENMASK(47, 32) +#define WRMEM1_276_FLD4 GENMASK(63, 48) +#define WRMEM1_276_FLD5 GENMASK(79, 64) +#define WRMEM1_276_FLD6 GENMASK(95, 80) +#define WRMEM1_276_FLD7 GENMASK(111, 96) +#define WRMEM1_276_FLD8 GENMASK(127, 112) + +/* WRMEM1_277 register fields */ +#define WRMEM1_277_FLD1 GENMASK(15, 0) +#define WRMEM1_277_FLD2 GENMASK(31, 16) +#define WRMEM1_277_FLD3 GENMASK(47, 32) +#define WRMEM1_277_FLD4 GENMASK(63, 48) +#define WRMEM1_277_FLD5 GENMASK(79, 64) +#define WRMEM1_277_FLD6 GENMASK(95, 80) +#define WRMEM1_277_FLD7 GENMASK(111, 96) +#define WRMEM1_277_FLD8 GENMASK(127, 112) + +/* WRMEM1_278 register fields */ +#define WRMEM1_278_FLD1 GENMASK(15, 0) +#define WRMEM1_278_FLD2 GENMASK(31, 16) +#define WRMEM1_278_FLD3 GENMASK(47, 32) +#define WRMEM1_278_FLD4 GENMASK(63, 48) +#define WRMEM1_278_FLD5 GENMASK(79, 64) +#define WRMEM1_278_FLD6 GENMASK(95, 80) +#define WRMEM1_278_FLD7 GENMASK(111, 96) +#define WRMEM1_278_FLD8 GENMASK(127, 112) + +/* WRMEM1_279 register fields */ +#define WRMEM1_279_FLD1 GENMASK(15, 0) +#define WRMEM1_279_FLD2 GENMASK(31, 16) +#define WRMEM1_279_FLD3 GENMASK(47, 32) +#define WRMEM1_279_FLD4 GENMASK(63, 48) +#define WRMEM1_279_FLD5 GENMASK(79, 64) +#define WRMEM1_279_FLD6 GENMASK(95, 80) +#define WRMEM1_279_FLD7 GENMASK(111, 96) +#define WRMEM1_279_FLD8 GENMASK(127, 112) + +/* WRMEM1_280 register fields */ +#define WRMEM1_280_FLD1 GENMASK(15, 0) +#define WRMEM1_280_FLD2 GENMASK(31, 16) +#define WRMEM1_280_FLD3 GENMASK(47, 32) +#define WRMEM1_280_FLD4 GENMASK(63, 48) +#define WRMEM1_280_FLD5 GENMASK(79, 64) +#define WRMEM1_280_FLD6 GENMASK(95, 80) +#define WRMEM1_280_FLD7 GENMASK(111, 96) +#define WRMEM1_280_FLD8 GENMASK(127, 112) + +/* WRMEM1_281 register fields */ +#define WRMEM1_281_FLD1 GENMASK(15, 0) +#define WRMEM1_281_FLD2 GENMASK(31, 16) +#define WRMEM1_281_FLD3 GENMASK(47, 32) +#define WRMEM1_281_FLD4 GENMASK(63, 48) +#define WRMEM1_281_FLD5 GENMASK(79, 64) +#define WRMEM1_281_FLD6 GENMASK(95, 80) +#define WRMEM1_281_FLD7 GENMASK(111, 96) +#define WRMEM1_281_FLD8 GENMASK(127, 112) + +/* WRMEM1_282 register fields */ +#define WRMEM1_282_FLD1 GENMASK(15, 0) +#define WRMEM1_282_FLD2 GENMASK(31, 16) +#define WRMEM1_282_FLD3 GENMASK(47, 32) +#define WRMEM1_282_FLD4 GENMASK(63, 48) +#define WRMEM1_282_FLD5 GENMASK(79, 64) +#define WRMEM1_282_FLD6 GENMASK(95, 80) +#define WRMEM1_282_FLD7 GENMASK(111, 96) +#define WRMEM1_282_FLD8 GENMASK(127, 112) + +/* WRMEM1_283 register fields */ +#define WRMEM1_283_FLD1 GENMASK(15, 0) +#define WRMEM1_283_FLD2 GENMASK(31, 16) +#define WRMEM1_283_FLD3 GENMASK(47, 32) +#define WRMEM1_283_FLD4 GENMASK(63, 48) +#define WRMEM1_283_FLD5 GENMASK(79, 64) +#define WRMEM1_283_FLD6 GENMASK(95, 80) +#define WRMEM1_283_FLD7 GENMASK(111, 96) +#define WRMEM1_283_FLD8 GENMASK(127, 112) + +/* WRMEM1_284 register fields */ +#define WRMEM1_284_FLD1 GENMASK(15, 0) +#define WRMEM1_284_FLD2 GENMASK(31, 16) +#define WRMEM1_284_FLD3 GENMASK(47, 32) +#define WRMEM1_284_FLD4 GENMASK(63, 48) +#define WRMEM1_284_FLD5 GENMASK(79, 64) +#define WRMEM1_284_FLD6 GENMASK(95, 80) +#define WRMEM1_284_FLD7 GENMASK(111, 96) +#define WRMEM1_284_FLD8 GENMASK(127, 112) + +/* WRMEM1_285 register fields */ +#define WRMEM1_285_FLD1 GENMASK(15, 0) +#define WRMEM1_285_FLD2 GENMASK(31, 16) +#define WRMEM1_285_FLD3 GENMASK(47, 32) +#define WRMEM1_285_FLD4 GENMASK(63, 48) +#define WRMEM1_285_FLD5 GENMASK(79, 64) +#define WRMEM1_285_FLD6 GENMASK(95, 80) +#define WRMEM1_285_FLD7 GENMASK(111, 96) +#define WRMEM1_285_FLD8 GENMASK(127, 112) + +/* WRMEM1_286 register fields */ +#define WRMEM1_286_FLD1 GENMASK(15, 0) +#define WRMEM1_286_FLD2 GENMASK(31, 16) +#define WRMEM1_286_FLD3 GENMASK(47, 32) +#define WRMEM1_286_FLD4 GENMASK(63, 48) +#define WRMEM1_286_FLD5 GENMASK(79, 64) +#define WRMEM1_286_FLD6 GENMASK(95, 80) +#define WRMEM1_286_FLD7 GENMASK(111, 96) +#define WRMEM1_286_FLD8 GENMASK(127, 112) + +/* WRMEM1_287 register fields */ +#define WRMEM1_287_FLD1 GENMASK(15, 0) +#define WRMEM1_287_FLD2 GENMASK(31, 16) +#define WRMEM1_287_FLD3 GENMASK(47, 32) +#define WRMEM1_287_FLD4 GENMASK(63, 48) +#define WRMEM1_287_FLD5 GENMASK(79, 64) +#define WRMEM1_287_FLD6 GENMASK(95, 80) +#define WRMEM1_287_FLD7 GENMASK(111, 96) +#define WRMEM1_287_FLD8 GENMASK(127, 112) + +/* WRMEM1_288 register fields */ +#define WRMEM1_288_FLD1 GENMASK(15, 0) +#define WRMEM1_288_FLD2 GENMASK(31, 16) +#define WRMEM1_288_FLD3 GENMASK(47, 32) +#define WRMEM1_288_FLD4 GENMASK(63, 48) +#define WRMEM1_288_FLD5 GENMASK(79, 64) +#define WRMEM1_288_FLD6 GENMASK(95, 80) +#define WRMEM1_288_FLD7 GENMASK(111, 96) +#define WRMEM1_288_FLD8 GENMASK(127, 112) + +/* WRMEM1_289 register fields */ +#define WRMEM1_289_FLD1 GENMASK(15, 0) +#define WRMEM1_289_FLD2 GENMASK(31, 16) +#define WRMEM1_289_FLD3 GENMASK(47, 32) +#define WRMEM1_289_FLD4 GENMASK(63, 48) +#define WRMEM1_289_FLD5 GENMASK(79, 64) +#define WRMEM1_289_FLD6 GENMASK(95, 80) +#define WRMEM1_289_FLD7 GENMASK(111, 96) +#define WRMEM1_289_FLD8 GENMASK(127, 112) + +/* WRMEM1_290 register fields */ +#define WRMEM1_290_FLD1 GENMASK(15, 0) +#define WRMEM1_290_FLD2 GENMASK(31, 16) +#define WRMEM1_290_FLD3 GENMASK(47, 32) +#define WRMEM1_290_FLD4 GENMASK(63, 48) +#define WRMEM1_290_FLD5 GENMASK(79, 64) +#define WRMEM1_290_FLD6 GENMASK(95, 80) +#define WRMEM1_290_FLD7 GENMASK(111, 96) +#define WRMEM1_290_FLD8 GENMASK(127, 112) + +/* WRMEM1_291 register fields */ +#define WRMEM1_291_FLD1 GENMASK(15, 0) +#define WRMEM1_291_FLD2 GENMASK(31, 16) +#define WRMEM1_291_FLD3 GENMASK(47, 32) +#define WRMEM1_291_FLD4 GENMASK(63, 48) +#define WRMEM1_291_FLD5 GENMASK(79, 64) +#define WRMEM1_291_FLD6 GENMASK(95, 80) +#define WRMEM1_291_FLD7 GENMASK(111, 96) +#define WRMEM1_291_FLD8 GENMASK(127, 112) + +/* WRMEM1_292 register fields */ +#define WRMEM1_292_FLD1 GENMASK(15, 0) +#define WRMEM1_292_FLD2 GENMASK(31, 16) +#define WRMEM1_292_FLD3 GENMASK(47, 32) +#define WRMEM1_292_FLD4 GENMASK(63, 48) +#define WRMEM1_292_FLD5 GENMASK(79, 64) +#define WRMEM1_292_FLD6 GENMASK(95, 80) +#define WRMEM1_292_FLD7 GENMASK(111, 96) +#define WRMEM1_292_FLD8 GENMASK(127, 112) + +/* WRMEM1_293 register fields */ +#define WRMEM1_293_FLD1 GENMASK(15, 0) +#define WRMEM1_293_FLD2 GENMASK(31, 16) +#define WRMEM1_293_FLD3 GENMASK(47, 32) +#define WRMEM1_293_FLD4 GENMASK(63, 48) +#define WRMEM1_293_FLD5 GENMASK(79, 64) +#define WRMEM1_293_FLD6 GENMASK(95, 80) +#define WRMEM1_293_FLD7 GENMASK(111, 96) +#define WRMEM1_293_FLD8 GENMASK(127, 112) + +/* WRMEM1_294 register fields */ +#define WRMEM1_294_FLD1 GENMASK(15, 0) +#define WRMEM1_294_FLD2 GENMASK(31, 16) +#define WRMEM1_294_FLD3 GENMASK(47, 32) +#define WRMEM1_294_FLD4 GENMASK(63, 48) +#define WRMEM1_294_FLD5 GENMASK(79, 64) +#define WRMEM1_294_FLD6 GENMASK(95, 80) +#define WRMEM1_294_FLD7 GENMASK(111, 96) +#define WRMEM1_294_FLD8 GENMASK(127, 112) + +/* WRMEM1_295 register fields */ +#define WRMEM1_295_FLD1 GENMASK(15, 0) +#define WRMEM1_295_FLD2 GENMASK(31, 16) +#define WRMEM1_295_FLD3 GENMASK(47, 32) +#define WRMEM1_295_FLD4 GENMASK(63, 48) +#define WRMEM1_295_FLD5 GENMASK(79, 64) +#define WRMEM1_295_FLD6 GENMASK(95, 80) +#define WRMEM1_295_FLD7 GENMASK(111, 96) +#define WRMEM1_295_FLD8 GENMASK(127, 112) + +/* WRMEM1_296 register fields */ +#define WRMEM1_296_FLD1 GENMASK(15, 0) +#define WRMEM1_296_FLD2 GENMASK(31, 16) +#define WRMEM1_296_FLD3 GENMASK(47, 32) +#define WRMEM1_296_FLD4 GENMASK(63, 48) +#define WRMEM1_296_FLD5 GENMASK(79, 64) +#define WRMEM1_296_FLD6 GENMASK(95, 80) +#define WRMEM1_296_FLD7 GENMASK(111, 96) +#define WRMEM1_296_FLD8 GENMASK(127, 112) + +/* WRMEM1_297 register fields */ +#define WRMEM1_297_FLD1 GENMASK(15, 0) +#define WRMEM1_297_FLD2 GENMASK(31, 16) +#define WRMEM1_297_FLD3 GENMASK(47, 32) +#define WRMEM1_297_FLD4 GENMASK(63, 48) +#define WRMEM1_297_FLD5 GENMASK(79, 64) +#define WRMEM1_297_FLD6 GENMASK(95, 80) +#define WRMEM1_297_FLD7 GENMASK(111, 96) +#define WRMEM1_297_FLD8 GENMASK(127, 112) + +/* WRMEM1_298 register fields */ +#define WRMEM1_298_FLD1 GENMASK(15, 0) +#define WRMEM1_298_FLD2 GENMASK(31, 16) +#define WRMEM1_298_FLD3 GENMASK(47, 32) +#define WRMEM1_298_FLD4 GENMASK(63, 48) +#define WRMEM1_298_FLD5 GENMASK(79, 64) +#define WRMEM1_298_FLD6 GENMASK(95, 80) +#define WRMEM1_298_FLD7 GENMASK(111, 96) +#define WRMEM1_298_FLD8 GENMASK(127, 112) + +/* WRMEM1_299 register fields */ +#define WRMEM1_299_FLD1 GENMASK(15, 0) +#define WRMEM1_299_FLD2 GENMASK(31, 16) +#define WRMEM1_299_FLD3 GENMASK(47, 32) +#define WRMEM1_299_FLD4 GENMASK(63, 48) +#define WRMEM1_299_FLD5 GENMASK(79, 64) +#define WRMEM1_299_FLD6 GENMASK(95, 80) +#define WRMEM1_299_FLD7 GENMASK(111, 96) +#define WRMEM1_299_FLD8 GENMASK(127, 112) + +#endif diff --git a/test/basic_tests/rdl_uvmmem_lite/golden/output.h b/test/basic_tests/rdl_uvmmem_lite/golden/output.h new file mode 100644 index 0000000..78a94e7 --- /dev/null +++ b/test/basic_tests/rdl_uvmmem_lite/golden/output.h @@ -0,0 +1,3743 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_uvmmem_lite/test.rdl +// Parms: ./rdl_uvmmem_lite/test.parms +// Date: Thu Jul 20 13:46:55 EDT 2023 +// + +#ifndef __TOP_REGISTER_MAP__ +#define __TOP_REGISTER_MAP__ + +#include + +/* TOP_REGISTERS memory map */ +enum TOP_REGS { + SR1 = 0x0, + WR1 = 0x100, + SR_REPEAT1 = 0x200, + SR_REPEAT2 = 0x204, + SR_REPEAT3 = 0x208, + SRMEM1_0 = 0x2000, + SRMEM1_1 = 0x2004, + SRMEM1_2 = 0x2008, + SRMEM1_3 = 0x200c, + SRMEM1_4 = 0x2010, + SRMEM1_5 = 0x2014, + SRMEM1_6 = 0x2018, + SRMEM1_7 = 0x201c, + SRMEM1_8 = 0x2020, + SRMEM1_9 = 0x2024, + SRMEM1_10 = 0x2028, + SRMEM1_11 = 0x202c, + SRMEM1_12 = 0x2030, + SRMEM1_13 = 0x2034, + SRMEM1_14 = 0x2038, + SRMEM1_15 = 0x203c, + SRMEM1_16 = 0x2040, + SRMEM1_17 = 0x2044, + SRMEM1_18 = 0x2048, + SRMEM1_19 = 0x204c, + SRMEM1_20 = 0x2050, + SRMEM1_21 = 0x2054, + SRMEM1_22 = 0x2058, + SRMEM1_23 = 0x205c, + SRMEM1_24 = 0x2060, + SRMEM1_25 = 0x2064, + SRMEM1_26 = 0x2068, + SRMEM1_27 = 0x206c, + SRMEM1_28 = 0x2070, + SRMEM1_29 = 0x2074, + SRMEM1_30 = 0x2078, + SRMEM1_31 = 0x207c, + SRMEM1_32 = 0x2080, + SRMEM1_33 = 0x2084, + SRMEM1_34 = 0x2088, + SRMEM1_35 = 0x208c, + SRMEM1_36 = 0x2090, + SRMEM1_37 = 0x2094, + SRMEM1_38 = 0x2098, + SRMEM1_39 = 0x209c, + SRMEM1_40 = 0x20a0, + SRMEM1_41 = 0x20a4, + SRMEM1_42 = 0x20a8, + SRMEM1_43 = 0x20ac, + SRMEM1_44 = 0x20b0, + SRMEM1_45 = 0x20b4, + SRMEM1_46 = 0x20b8, + SRMEM1_47 = 0x20bc, + SRMEM1_48 = 0x20c0, + SRMEM1_49 = 0x20c4, + SRMEM1_50 = 0x20c8, + SRMEM1_51 = 0x20cc, + SRMEM1_52 = 0x20d0, + SRMEM1_53 = 0x20d4, + SRMEM1_54 = 0x20d8, + SRMEM1_55 = 0x20dc, + SRMEM1_56 = 0x20e0, + SRMEM1_57 = 0x20e4, + SRMEM1_58 = 0x20e8, + SRMEM1_59 = 0x20ec, + SRMEM1_60 = 0x20f0, + SRMEM1_61 = 0x20f4, + SRMEM1_62 = 0x20f8, + SRMEM1_63 = 0x20fc, + SRMEM1_64 = 0x2100, + SRMEM1_65 = 0x2104, + SRMEM1_66 = 0x2108, + SRMEM1_67 = 0x210c, + SRMEM1_68 = 0x2110, + SRMEM1_69 = 0x2114, + SRMEM1_70 = 0x2118, + SRMEM1_71 = 0x211c, + SRMEM1_72 = 0x2120, + SRMEM1_73 = 0x2124, + SRMEM1_74 = 0x2128, + SRMEM1_75 = 0x212c, + SRMEM1_76 = 0x2130, + SRMEM1_77 = 0x2134, + SRMEM1_78 = 0x2138, + SRMEM1_79 = 0x213c, + SRMEM1_80 = 0x2140, + SRMEM1_81 = 0x2144, + SRMEM1_82 = 0x2148, + SRMEM1_83 = 0x214c, + SRMEM1_84 = 0x2150, + SRMEM1_85 = 0x2154, + SRMEM1_86 = 0x2158, + SRMEM1_87 = 0x215c, + SRMEM1_88 = 0x2160, + SRMEM1_89 = 0x2164, + SRMEM1_90 = 0x2168, + SRMEM1_91 = 0x216c, + SRMEM1_92 = 0x2170, + SRMEM1_93 = 0x2174, + SRMEM1_94 = 0x2178, + SRMEM1_95 = 0x217c, + SRMEM1_96 = 0x2180, + SRMEM1_97 = 0x2184, + SRMEM1_98 = 0x2188, + SRMEM1_99 = 0x218c, + WRMEM1_0 = 0x20000, + WRMEM1_1 = 0x20010, + WRMEM1_2 = 0x20020, + WRMEM1_3 = 0x20030, + WRMEM1_4 = 0x20040, + WRMEM1_5 = 0x20050, + WRMEM1_6 = 0x20060, + WRMEM1_7 = 0x20070, + WRMEM1_8 = 0x20080, + WRMEM1_9 = 0x20090, + WRMEM1_10 = 0x200a0, + WRMEM1_11 = 0x200b0, + WRMEM1_12 = 0x200c0, + WRMEM1_13 = 0x200d0, + WRMEM1_14 = 0x200e0, + WRMEM1_15 = 0x200f0, + WRMEM1_16 = 0x20100, + WRMEM1_17 = 0x20110, + WRMEM1_18 = 0x20120, + WRMEM1_19 = 0x20130, + WRMEM1_20 = 0x20140, + WRMEM1_21 = 0x20150, + WRMEM1_22 = 0x20160, + WRMEM1_23 = 0x20170, + WRMEM1_24 = 0x20180, + WRMEM1_25 = 0x20190, + WRMEM1_26 = 0x201a0, + WRMEM1_27 = 0x201b0, + WRMEM1_28 = 0x201c0, + WRMEM1_29 = 0x201d0, + WRMEM1_30 = 0x201e0, + WRMEM1_31 = 0x201f0, + WRMEM1_32 = 0x20200, + WRMEM1_33 = 0x20210, + WRMEM1_34 = 0x20220, + WRMEM1_35 = 0x20230, + WRMEM1_36 = 0x20240, + WRMEM1_37 = 0x20250, + WRMEM1_38 = 0x20260, + WRMEM1_39 = 0x20270, + WRMEM1_40 = 0x20280, + WRMEM1_41 = 0x20290, + WRMEM1_42 = 0x202a0, + WRMEM1_43 = 0x202b0, + WRMEM1_44 = 0x202c0, + WRMEM1_45 = 0x202d0, + WRMEM1_46 = 0x202e0, + WRMEM1_47 = 0x202f0, + WRMEM1_48 = 0x20300, + WRMEM1_49 = 0x20310, + WRMEM1_50 = 0x20320, + WRMEM1_51 = 0x20330, + WRMEM1_52 = 0x20340, + WRMEM1_53 = 0x20350, + WRMEM1_54 = 0x20360, + WRMEM1_55 = 0x20370, + WRMEM1_56 = 0x20380, + WRMEM1_57 = 0x20390, + WRMEM1_58 = 0x203a0, + WRMEM1_59 = 0x203b0, + WRMEM1_60 = 0x203c0, + WRMEM1_61 = 0x203d0, + WRMEM1_62 = 0x203e0, + WRMEM1_63 = 0x203f0, + WRMEM1_64 = 0x20400, + WRMEM1_65 = 0x20410, + WRMEM1_66 = 0x20420, + WRMEM1_67 = 0x20430, + WRMEM1_68 = 0x20440, + WRMEM1_69 = 0x20450, + WRMEM1_70 = 0x20460, + WRMEM1_71 = 0x20470, + WRMEM1_72 = 0x20480, + WRMEM1_73 = 0x20490, + WRMEM1_74 = 0x204a0, + WRMEM1_75 = 0x204b0, + WRMEM1_76 = 0x204c0, + WRMEM1_77 = 0x204d0, + WRMEM1_78 = 0x204e0, + WRMEM1_79 = 0x204f0, + WRMEM1_80 = 0x20500, + WRMEM1_81 = 0x20510, + WRMEM1_82 = 0x20520, + WRMEM1_83 = 0x20530, + WRMEM1_84 = 0x20540, + WRMEM1_85 = 0x20550, + WRMEM1_86 = 0x20560, + WRMEM1_87 = 0x20570, + WRMEM1_88 = 0x20580, + WRMEM1_89 = 0x20590, + WRMEM1_90 = 0x205a0, + WRMEM1_91 = 0x205b0, + WRMEM1_92 = 0x205c0, + WRMEM1_93 = 0x205d0, + WRMEM1_94 = 0x205e0, + WRMEM1_95 = 0x205f0, + WRMEM1_96 = 0x20600, + WRMEM1_97 = 0x20610, + WRMEM1_98 = 0x20620, + WRMEM1_99 = 0x20630, + WRMEM1_100 = 0x20640, + WRMEM1_101 = 0x20650, + WRMEM1_102 = 0x20660, + WRMEM1_103 = 0x20670, + WRMEM1_104 = 0x20680, + WRMEM1_105 = 0x20690, + WRMEM1_106 = 0x206a0, + WRMEM1_107 = 0x206b0, + WRMEM1_108 = 0x206c0, + WRMEM1_109 = 0x206d0, + WRMEM1_110 = 0x206e0, + WRMEM1_111 = 0x206f0, + WRMEM1_112 = 0x20700, + WRMEM1_113 = 0x20710, + WRMEM1_114 = 0x20720, + WRMEM1_115 = 0x20730, + WRMEM1_116 = 0x20740, + WRMEM1_117 = 0x20750, + WRMEM1_118 = 0x20760, + WRMEM1_119 = 0x20770, + WRMEM1_120 = 0x20780, + WRMEM1_121 = 0x20790, + WRMEM1_122 = 0x207a0, + WRMEM1_123 = 0x207b0, + WRMEM1_124 = 0x207c0, + WRMEM1_125 = 0x207d0, + WRMEM1_126 = 0x207e0, + WRMEM1_127 = 0x207f0, + WRMEM1_128 = 0x20800, + WRMEM1_129 = 0x20810, + WRMEM1_130 = 0x20820, + WRMEM1_131 = 0x20830, + WRMEM1_132 = 0x20840, + WRMEM1_133 = 0x20850, + WRMEM1_134 = 0x20860, + WRMEM1_135 = 0x20870, + WRMEM1_136 = 0x20880, + WRMEM1_137 = 0x20890, + WRMEM1_138 = 0x208a0, + WRMEM1_139 = 0x208b0, + WRMEM1_140 = 0x208c0, + WRMEM1_141 = 0x208d0, + WRMEM1_142 = 0x208e0, + WRMEM1_143 = 0x208f0, + WRMEM1_144 = 0x20900, + WRMEM1_145 = 0x20910, + WRMEM1_146 = 0x20920, + WRMEM1_147 = 0x20930, + WRMEM1_148 = 0x20940, + WRMEM1_149 = 0x20950, + WRMEM1_150 = 0x20960, + WRMEM1_151 = 0x20970, + WRMEM1_152 = 0x20980, + WRMEM1_153 = 0x20990, + WRMEM1_154 = 0x209a0, + WRMEM1_155 = 0x209b0, + WRMEM1_156 = 0x209c0, + WRMEM1_157 = 0x209d0, + WRMEM1_158 = 0x209e0, + WRMEM1_159 = 0x209f0, + WRMEM1_160 = 0x20a00, + WRMEM1_161 = 0x20a10, + WRMEM1_162 = 0x20a20, + WRMEM1_163 = 0x20a30, + WRMEM1_164 = 0x20a40, + WRMEM1_165 = 0x20a50, + WRMEM1_166 = 0x20a60, + WRMEM1_167 = 0x20a70, + WRMEM1_168 = 0x20a80, + WRMEM1_169 = 0x20a90, + WRMEM1_170 = 0x20aa0, + WRMEM1_171 = 0x20ab0, + WRMEM1_172 = 0x20ac0, + WRMEM1_173 = 0x20ad0, + WRMEM1_174 = 0x20ae0, + WRMEM1_175 = 0x20af0, + WRMEM1_176 = 0x20b00, + WRMEM1_177 = 0x20b10, + WRMEM1_178 = 0x20b20, + WRMEM1_179 = 0x20b30, + WRMEM1_180 = 0x20b40, + WRMEM1_181 = 0x20b50, + WRMEM1_182 = 0x20b60, + WRMEM1_183 = 0x20b70, + WRMEM1_184 = 0x20b80, + WRMEM1_185 = 0x20b90, + WRMEM1_186 = 0x20ba0, + WRMEM1_187 = 0x20bb0, + WRMEM1_188 = 0x20bc0, + WRMEM1_189 = 0x20bd0, + WRMEM1_190 = 0x20be0, + WRMEM1_191 = 0x20bf0, + WRMEM1_192 = 0x20c00, + WRMEM1_193 = 0x20c10, + WRMEM1_194 = 0x20c20, + WRMEM1_195 = 0x20c30, + WRMEM1_196 = 0x20c40, + WRMEM1_197 = 0x20c50, + WRMEM1_198 = 0x20c60, + WRMEM1_199 = 0x20c70, + WRMEM1_200 = 0x20c80, + WRMEM1_201 = 0x20c90, + WRMEM1_202 = 0x20ca0, + WRMEM1_203 = 0x20cb0, + WRMEM1_204 = 0x20cc0, + WRMEM1_205 = 0x20cd0, + WRMEM1_206 = 0x20ce0, + WRMEM1_207 = 0x20cf0, + WRMEM1_208 = 0x20d00, + WRMEM1_209 = 0x20d10, + WRMEM1_210 = 0x20d20, + WRMEM1_211 = 0x20d30, + WRMEM1_212 = 0x20d40, + WRMEM1_213 = 0x20d50, + WRMEM1_214 = 0x20d60, + WRMEM1_215 = 0x20d70, + WRMEM1_216 = 0x20d80, + WRMEM1_217 = 0x20d90, + WRMEM1_218 = 0x20da0, + WRMEM1_219 = 0x20db0, + WRMEM1_220 = 0x20dc0, + WRMEM1_221 = 0x20dd0, + WRMEM1_222 = 0x20de0, + WRMEM1_223 = 0x20df0, + WRMEM1_224 = 0x20e00, + WRMEM1_225 = 0x20e10, + WRMEM1_226 = 0x20e20, + WRMEM1_227 = 0x20e30, + WRMEM1_228 = 0x20e40, + WRMEM1_229 = 0x20e50, + WRMEM1_230 = 0x20e60, + WRMEM1_231 = 0x20e70, + WRMEM1_232 = 0x20e80, + WRMEM1_233 = 0x20e90, + WRMEM1_234 = 0x20ea0, + WRMEM1_235 = 0x20eb0, + WRMEM1_236 = 0x20ec0, + WRMEM1_237 = 0x20ed0, + WRMEM1_238 = 0x20ee0, + WRMEM1_239 = 0x20ef0, + WRMEM1_240 = 0x20f00, + WRMEM1_241 = 0x20f10, + WRMEM1_242 = 0x20f20, + WRMEM1_243 = 0x20f30, + WRMEM1_244 = 0x20f40, + WRMEM1_245 = 0x20f50, + WRMEM1_246 = 0x20f60, + WRMEM1_247 = 0x20f70, + WRMEM1_248 = 0x20f80, + WRMEM1_249 = 0x20f90, + WRMEM1_250 = 0x20fa0, + WRMEM1_251 = 0x20fb0, + WRMEM1_252 = 0x20fc0, + WRMEM1_253 = 0x20fd0, + WRMEM1_254 = 0x20fe0, + WRMEM1_255 = 0x20ff0, + WRMEM1_256 = 0x21000, + WRMEM1_257 = 0x21010, + WRMEM1_258 = 0x21020, + WRMEM1_259 = 0x21030, + WRMEM1_260 = 0x21040, + WRMEM1_261 = 0x21050, + WRMEM1_262 = 0x21060, + WRMEM1_263 = 0x21070, + WRMEM1_264 = 0x21080, + WRMEM1_265 = 0x21090, + WRMEM1_266 = 0x210a0, + WRMEM1_267 = 0x210b0, + WRMEM1_268 = 0x210c0, + WRMEM1_269 = 0x210d0, + WRMEM1_270 = 0x210e0, + WRMEM1_271 = 0x210f0, + WRMEM1_272 = 0x21100, + WRMEM1_273 = 0x21110, + WRMEM1_274 = 0x21120, + WRMEM1_275 = 0x21130, + WRMEM1_276 = 0x21140, + WRMEM1_277 = 0x21150, + WRMEM1_278 = 0x21160, + WRMEM1_279 = 0x21170, + WRMEM1_280 = 0x21180, + WRMEM1_281 = 0x21190, + WRMEM1_282 = 0x211a0, + WRMEM1_283 = 0x211b0, + WRMEM1_284 = 0x211c0, + WRMEM1_285 = 0x211d0, + WRMEM1_286 = 0x211e0, + WRMEM1_287 = 0x211f0, + WRMEM1_288 = 0x21200, + WRMEM1_289 = 0x21210, + WRMEM1_290 = 0x21220, + WRMEM1_291 = 0x21230, + WRMEM1_292 = 0x21240, + WRMEM1_293 = 0x21250, + WRMEM1_294 = 0x21260, + WRMEM1_295 = 0x21270, + WRMEM1_296 = 0x21280, + WRMEM1_297 = 0x21290, + WRMEM1_298 = 0x212a0, + WRMEM1_299 = 0x212b0 +}; + +/* SR1 register fields */ +#define SR1_FLD1 GENMASK(31, 0) + +/* WR1 register fields */ +#define WR1_FLD1 GENMASK(15, 0) +#define WR1_FLD2 GENMASK(31, 16) +#define WR1_FLD3 GENMASK(47, 32) +#define WR1_FLD4 GENMASK(63, 48) +#define WR1_FLD5 GENMASK(79, 64) +#define WR1_FLD6 GENMASK(95, 80) +#define WR1_FLD7 GENMASK(111, 96) +#define WR1_FLD8 GENMASK(127, 112) + +/* SR_REPEAT1 register fields */ +#define SR_REPEAT1_FLD1 GENMASK(31, 0) + +/* SR_REPEAT2 register fields */ +#define SR_REPEAT2_FLD1 GENMASK(31, 0) + +/* SR_REPEAT3 register fields */ +#define SR_REPEAT3_FLD1 GENMASK(31, 0) + +/* SRMEM1_0 register fields */ +#define SRMEM1_0_FLD1 GENMASK(31, 0) + +/* SRMEM1_1 register fields */ +#define SRMEM1_1_FLD1 GENMASK(31, 0) + +/* SRMEM1_2 register fields */ +#define SRMEM1_2_FLD1 GENMASK(31, 0) + +/* SRMEM1_3 register fields */ +#define SRMEM1_3_FLD1 GENMASK(31, 0) + +/* SRMEM1_4 register fields */ +#define SRMEM1_4_FLD1 GENMASK(31, 0) + +/* SRMEM1_5 register fields */ +#define SRMEM1_5_FLD1 GENMASK(31, 0) + +/* SRMEM1_6 register fields */ +#define SRMEM1_6_FLD1 GENMASK(31, 0) + +/* SRMEM1_7 register fields */ +#define SRMEM1_7_FLD1 GENMASK(31, 0) + +/* SRMEM1_8 register fields */ +#define SRMEM1_8_FLD1 GENMASK(31, 0) + +/* SRMEM1_9 register fields */ +#define SRMEM1_9_FLD1 GENMASK(31, 0) + +/* SRMEM1_10 register fields */ +#define SRMEM1_10_FLD1 GENMASK(31, 0) + +/* SRMEM1_11 register fields */ +#define SRMEM1_11_FLD1 GENMASK(31, 0) + +/* SRMEM1_12 register fields */ +#define SRMEM1_12_FLD1 GENMASK(31, 0) + +/* SRMEM1_13 register fields */ +#define SRMEM1_13_FLD1 GENMASK(31, 0) + +/* SRMEM1_14 register fields */ +#define SRMEM1_14_FLD1 GENMASK(31, 0) + +/* SRMEM1_15 register fields */ +#define SRMEM1_15_FLD1 GENMASK(31, 0) + +/* SRMEM1_16 register fields */ +#define SRMEM1_16_FLD1 GENMASK(31, 0) + +/* SRMEM1_17 register fields */ +#define SRMEM1_17_FLD1 GENMASK(31, 0) + +/* SRMEM1_18 register fields */ +#define SRMEM1_18_FLD1 GENMASK(31, 0) + +/* SRMEM1_19 register fields */ +#define SRMEM1_19_FLD1 GENMASK(31, 0) + +/* SRMEM1_20 register fields */ +#define SRMEM1_20_FLD1 GENMASK(31, 0) + +/* SRMEM1_21 register fields */ +#define SRMEM1_21_FLD1 GENMASK(31, 0) + +/* SRMEM1_22 register fields */ +#define SRMEM1_22_FLD1 GENMASK(31, 0) + +/* SRMEM1_23 register fields */ +#define SRMEM1_23_FLD1 GENMASK(31, 0) + +/* SRMEM1_24 register fields */ +#define SRMEM1_24_FLD1 GENMASK(31, 0) + +/* SRMEM1_25 register fields */ +#define SRMEM1_25_FLD1 GENMASK(31, 0) + +/* SRMEM1_26 register fields */ +#define SRMEM1_26_FLD1 GENMASK(31, 0) + +/* SRMEM1_27 register fields */ +#define SRMEM1_27_FLD1 GENMASK(31, 0) + +/* SRMEM1_28 register fields */ +#define SRMEM1_28_FLD1 GENMASK(31, 0) + +/* SRMEM1_29 register fields */ +#define SRMEM1_29_FLD1 GENMASK(31, 0) + +/* SRMEM1_30 register fields */ +#define SRMEM1_30_FLD1 GENMASK(31, 0) + +/* SRMEM1_31 register fields */ +#define SRMEM1_31_FLD1 GENMASK(31, 0) + +/* SRMEM1_32 register fields */ +#define SRMEM1_32_FLD1 GENMASK(31, 0) + +/* SRMEM1_33 register fields */ +#define SRMEM1_33_FLD1 GENMASK(31, 0) + +/* SRMEM1_34 register fields */ +#define SRMEM1_34_FLD1 GENMASK(31, 0) + +/* SRMEM1_35 register fields */ +#define SRMEM1_35_FLD1 GENMASK(31, 0) + +/* SRMEM1_36 register fields */ +#define SRMEM1_36_FLD1 GENMASK(31, 0) + +/* SRMEM1_37 register fields */ +#define SRMEM1_37_FLD1 GENMASK(31, 0) + +/* SRMEM1_38 register fields */ +#define SRMEM1_38_FLD1 GENMASK(31, 0) + +/* SRMEM1_39 register fields */ +#define SRMEM1_39_FLD1 GENMASK(31, 0) + +/* SRMEM1_40 register fields */ +#define SRMEM1_40_FLD1 GENMASK(31, 0) + +/* SRMEM1_41 register fields */ +#define SRMEM1_41_FLD1 GENMASK(31, 0) + +/* SRMEM1_42 register fields */ +#define SRMEM1_42_FLD1 GENMASK(31, 0) + +/* SRMEM1_43 register fields */ +#define SRMEM1_43_FLD1 GENMASK(31, 0) + +/* SRMEM1_44 register fields */ +#define SRMEM1_44_FLD1 GENMASK(31, 0) + +/* SRMEM1_45 register fields */ +#define SRMEM1_45_FLD1 GENMASK(31, 0) + +/* SRMEM1_46 register fields */ +#define SRMEM1_46_FLD1 GENMASK(31, 0) + +/* SRMEM1_47 register fields */ +#define SRMEM1_47_FLD1 GENMASK(31, 0) + +/* SRMEM1_48 register fields */ +#define SRMEM1_48_FLD1 GENMASK(31, 0) + +/* SRMEM1_49 register fields */ +#define SRMEM1_49_FLD1 GENMASK(31, 0) + +/* SRMEM1_50 register fields */ +#define SRMEM1_50_FLD1 GENMASK(31, 0) + +/* SRMEM1_51 register fields */ +#define SRMEM1_51_FLD1 GENMASK(31, 0) + +/* SRMEM1_52 register fields */ +#define SRMEM1_52_FLD1 GENMASK(31, 0) + +/* SRMEM1_53 register fields */ +#define SRMEM1_53_FLD1 GENMASK(31, 0) + +/* SRMEM1_54 register fields */ +#define SRMEM1_54_FLD1 GENMASK(31, 0) + +/* SRMEM1_55 register fields */ +#define SRMEM1_55_FLD1 GENMASK(31, 0) + +/* SRMEM1_56 register fields */ +#define SRMEM1_56_FLD1 GENMASK(31, 0) + +/* SRMEM1_57 register fields */ +#define SRMEM1_57_FLD1 GENMASK(31, 0) + +/* SRMEM1_58 register fields */ +#define SRMEM1_58_FLD1 GENMASK(31, 0) + +/* SRMEM1_59 register fields */ +#define SRMEM1_59_FLD1 GENMASK(31, 0) + +/* SRMEM1_60 register fields */ +#define SRMEM1_60_FLD1 GENMASK(31, 0) + +/* SRMEM1_61 register fields */ +#define SRMEM1_61_FLD1 GENMASK(31, 0) + +/* SRMEM1_62 register fields */ +#define SRMEM1_62_FLD1 GENMASK(31, 0) + +/* SRMEM1_63 register fields */ +#define SRMEM1_63_FLD1 GENMASK(31, 0) + +/* SRMEM1_64 register fields */ +#define SRMEM1_64_FLD1 GENMASK(31, 0) + +/* SRMEM1_65 register fields */ +#define SRMEM1_65_FLD1 GENMASK(31, 0) + +/* SRMEM1_66 register fields */ +#define SRMEM1_66_FLD1 GENMASK(31, 0) + +/* SRMEM1_67 register fields */ +#define SRMEM1_67_FLD1 GENMASK(31, 0) + +/* SRMEM1_68 register fields */ +#define SRMEM1_68_FLD1 GENMASK(31, 0) + +/* SRMEM1_69 register fields */ +#define SRMEM1_69_FLD1 GENMASK(31, 0) + +/* SRMEM1_70 register fields */ +#define SRMEM1_70_FLD1 GENMASK(31, 0) + +/* SRMEM1_71 register fields */ +#define SRMEM1_71_FLD1 GENMASK(31, 0) + +/* SRMEM1_72 register fields */ +#define SRMEM1_72_FLD1 GENMASK(31, 0) + +/* SRMEM1_73 register fields */ +#define SRMEM1_73_FLD1 GENMASK(31, 0) + +/* SRMEM1_74 register fields */ +#define SRMEM1_74_FLD1 GENMASK(31, 0) + +/* SRMEM1_75 register fields */ +#define SRMEM1_75_FLD1 GENMASK(31, 0) + +/* SRMEM1_76 register fields */ +#define SRMEM1_76_FLD1 GENMASK(31, 0) + +/* SRMEM1_77 register fields */ +#define SRMEM1_77_FLD1 GENMASK(31, 0) + +/* SRMEM1_78 register fields */ +#define SRMEM1_78_FLD1 GENMASK(31, 0) + +/* SRMEM1_79 register fields */ +#define SRMEM1_79_FLD1 GENMASK(31, 0) + +/* SRMEM1_80 register fields */ +#define SRMEM1_80_FLD1 GENMASK(31, 0) + +/* SRMEM1_81 register fields */ +#define SRMEM1_81_FLD1 GENMASK(31, 0) + +/* SRMEM1_82 register fields */ +#define SRMEM1_82_FLD1 GENMASK(31, 0) + +/* SRMEM1_83 register fields */ +#define SRMEM1_83_FLD1 GENMASK(31, 0) + +/* SRMEM1_84 register fields */ +#define SRMEM1_84_FLD1 GENMASK(31, 0) + +/* SRMEM1_85 register fields */ +#define SRMEM1_85_FLD1 GENMASK(31, 0) + +/* SRMEM1_86 register fields */ +#define SRMEM1_86_FLD1 GENMASK(31, 0) + +/* SRMEM1_87 register fields */ +#define SRMEM1_87_FLD1 GENMASK(31, 0) + +/* SRMEM1_88 register fields */ +#define SRMEM1_88_FLD1 GENMASK(31, 0) + +/* SRMEM1_89 register fields */ +#define SRMEM1_89_FLD1 GENMASK(31, 0) + +/* SRMEM1_90 register fields */ +#define SRMEM1_90_FLD1 GENMASK(31, 0) + +/* SRMEM1_91 register fields */ +#define SRMEM1_91_FLD1 GENMASK(31, 0) + +/* SRMEM1_92 register fields */ +#define SRMEM1_92_FLD1 GENMASK(31, 0) + +/* SRMEM1_93 register fields */ +#define SRMEM1_93_FLD1 GENMASK(31, 0) + +/* SRMEM1_94 register fields */ +#define SRMEM1_94_FLD1 GENMASK(31, 0) + +/* SRMEM1_95 register fields */ +#define SRMEM1_95_FLD1 GENMASK(31, 0) + +/* SRMEM1_96 register fields */ +#define SRMEM1_96_FLD1 GENMASK(31, 0) + +/* SRMEM1_97 register fields */ +#define SRMEM1_97_FLD1 GENMASK(31, 0) + +/* SRMEM1_98 register fields */ +#define SRMEM1_98_FLD1 GENMASK(31, 0) + +/* SRMEM1_99 register fields */ +#define SRMEM1_99_FLD1 GENMASK(31, 0) + +/* WRMEM1_0 register fields */ +#define WRMEM1_0_FLD1 GENMASK(15, 0) +#define WRMEM1_0_FLD2 GENMASK(31, 16) +#define WRMEM1_0_FLD3 GENMASK(47, 32) +#define WRMEM1_0_FLD4 GENMASK(63, 48) +#define WRMEM1_0_FLD5 GENMASK(79, 64) +#define WRMEM1_0_FLD6 GENMASK(95, 80) +#define WRMEM1_0_FLD7 GENMASK(111, 96) +#define WRMEM1_0_FLD8 GENMASK(127, 112) + +/* WRMEM1_1 register fields */ +#define WRMEM1_1_FLD1 GENMASK(15, 0) +#define WRMEM1_1_FLD2 GENMASK(31, 16) +#define WRMEM1_1_FLD3 GENMASK(47, 32) +#define WRMEM1_1_FLD4 GENMASK(63, 48) +#define WRMEM1_1_FLD5 GENMASK(79, 64) +#define WRMEM1_1_FLD6 GENMASK(95, 80) +#define WRMEM1_1_FLD7 GENMASK(111, 96) +#define WRMEM1_1_FLD8 GENMASK(127, 112) + +/* WRMEM1_2 register fields */ +#define WRMEM1_2_FLD1 GENMASK(15, 0) +#define WRMEM1_2_FLD2 GENMASK(31, 16) +#define WRMEM1_2_FLD3 GENMASK(47, 32) +#define WRMEM1_2_FLD4 GENMASK(63, 48) +#define WRMEM1_2_FLD5 GENMASK(79, 64) +#define WRMEM1_2_FLD6 GENMASK(95, 80) +#define WRMEM1_2_FLD7 GENMASK(111, 96) +#define WRMEM1_2_FLD8 GENMASK(127, 112) + +/* WRMEM1_3 register fields */ +#define WRMEM1_3_FLD1 GENMASK(15, 0) +#define WRMEM1_3_FLD2 GENMASK(31, 16) +#define WRMEM1_3_FLD3 GENMASK(47, 32) +#define WRMEM1_3_FLD4 GENMASK(63, 48) +#define WRMEM1_3_FLD5 GENMASK(79, 64) +#define WRMEM1_3_FLD6 GENMASK(95, 80) +#define WRMEM1_3_FLD7 GENMASK(111, 96) +#define WRMEM1_3_FLD8 GENMASK(127, 112) + +/* WRMEM1_4 register fields */ +#define WRMEM1_4_FLD1 GENMASK(15, 0) +#define WRMEM1_4_FLD2 GENMASK(31, 16) +#define WRMEM1_4_FLD3 GENMASK(47, 32) +#define WRMEM1_4_FLD4 GENMASK(63, 48) +#define WRMEM1_4_FLD5 GENMASK(79, 64) +#define WRMEM1_4_FLD6 GENMASK(95, 80) +#define WRMEM1_4_FLD7 GENMASK(111, 96) +#define WRMEM1_4_FLD8 GENMASK(127, 112) + +/* WRMEM1_5 register fields */ +#define WRMEM1_5_FLD1 GENMASK(15, 0) +#define WRMEM1_5_FLD2 GENMASK(31, 16) +#define WRMEM1_5_FLD3 GENMASK(47, 32) +#define WRMEM1_5_FLD4 GENMASK(63, 48) +#define WRMEM1_5_FLD5 GENMASK(79, 64) +#define WRMEM1_5_FLD6 GENMASK(95, 80) +#define WRMEM1_5_FLD7 GENMASK(111, 96) +#define WRMEM1_5_FLD8 GENMASK(127, 112) + +/* WRMEM1_6 register fields */ +#define WRMEM1_6_FLD1 GENMASK(15, 0) +#define WRMEM1_6_FLD2 GENMASK(31, 16) +#define WRMEM1_6_FLD3 GENMASK(47, 32) +#define WRMEM1_6_FLD4 GENMASK(63, 48) +#define WRMEM1_6_FLD5 GENMASK(79, 64) +#define WRMEM1_6_FLD6 GENMASK(95, 80) +#define WRMEM1_6_FLD7 GENMASK(111, 96) +#define WRMEM1_6_FLD8 GENMASK(127, 112) + +/* WRMEM1_7 register fields */ +#define WRMEM1_7_FLD1 GENMASK(15, 0) +#define WRMEM1_7_FLD2 GENMASK(31, 16) +#define WRMEM1_7_FLD3 GENMASK(47, 32) +#define WRMEM1_7_FLD4 GENMASK(63, 48) +#define WRMEM1_7_FLD5 GENMASK(79, 64) +#define WRMEM1_7_FLD6 GENMASK(95, 80) +#define WRMEM1_7_FLD7 GENMASK(111, 96) +#define WRMEM1_7_FLD8 GENMASK(127, 112) + +/* WRMEM1_8 register fields */ +#define WRMEM1_8_FLD1 GENMASK(15, 0) +#define WRMEM1_8_FLD2 GENMASK(31, 16) +#define WRMEM1_8_FLD3 GENMASK(47, 32) +#define WRMEM1_8_FLD4 GENMASK(63, 48) +#define WRMEM1_8_FLD5 GENMASK(79, 64) +#define WRMEM1_8_FLD6 GENMASK(95, 80) +#define WRMEM1_8_FLD7 GENMASK(111, 96) +#define WRMEM1_8_FLD8 GENMASK(127, 112) + +/* WRMEM1_9 register fields */ +#define WRMEM1_9_FLD1 GENMASK(15, 0) +#define WRMEM1_9_FLD2 GENMASK(31, 16) +#define WRMEM1_9_FLD3 GENMASK(47, 32) +#define WRMEM1_9_FLD4 GENMASK(63, 48) +#define WRMEM1_9_FLD5 GENMASK(79, 64) +#define WRMEM1_9_FLD6 GENMASK(95, 80) +#define WRMEM1_9_FLD7 GENMASK(111, 96) +#define WRMEM1_9_FLD8 GENMASK(127, 112) + +/* WRMEM1_10 register fields */ +#define WRMEM1_10_FLD1 GENMASK(15, 0) +#define WRMEM1_10_FLD2 GENMASK(31, 16) +#define WRMEM1_10_FLD3 GENMASK(47, 32) +#define WRMEM1_10_FLD4 GENMASK(63, 48) +#define WRMEM1_10_FLD5 GENMASK(79, 64) +#define WRMEM1_10_FLD6 GENMASK(95, 80) +#define WRMEM1_10_FLD7 GENMASK(111, 96) +#define WRMEM1_10_FLD8 GENMASK(127, 112) + +/* WRMEM1_11 register fields */ +#define WRMEM1_11_FLD1 GENMASK(15, 0) +#define WRMEM1_11_FLD2 GENMASK(31, 16) +#define WRMEM1_11_FLD3 GENMASK(47, 32) +#define WRMEM1_11_FLD4 GENMASK(63, 48) +#define WRMEM1_11_FLD5 GENMASK(79, 64) +#define WRMEM1_11_FLD6 GENMASK(95, 80) +#define WRMEM1_11_FLD7 GENMASK(111, 96) +#define WRMEM1_11_FLD8 GENMASK(127, 112) + +/* WRMEM1_12 register fields */ +#define WRMEM1_12_FLD1 GENMASK(15, 0) +#define WRMEM1_12_FLD2 GENMASK(31, 16) +#define WRMEM1_12_FLD3 GENMASK(47, 32) +#define WRMEM1_12_FLD4 GENMASK(63, 48) +#define WRMEM1_12_FLD5 GENMASK(79, 64) +#define WRMEM1_12_FLD6 GENMASK(95, 80) +#define WRMEM1_12_FLD7 GENMASK(111, 96) +#define WRMEM1_12_FLD8 GENMASK(127, 112) + +/* WRMEM1_13 register fields */ +#define WRMEM1_13_FLD1 GENMASK(15, 0) +#define WRMEM1_13_FLD2 GENMASK(31, 16) +#define WRMEM1_13_FLD3 GENMASK(47, 32) +#define WRMEM1_13_FLD4 GENMASK(63, 48) +#define WRMEM1_13_FLD5 GENMASK(79, 64) +#define WRMEM1_13_FLD6 GENMASK(95, 80) +#define WRMEM1_13_FLD7 GENMASK(111, 96) +#define WRMEM1_13_FLD8 GENMASK(127, 112) + +/* WRMEM1_14 register fields */ +#define WRMEM1_14_FLD1 GENMASK(15, 0) +#define WRMEM1_14_FLD2 GENMASK(31, 16) +#define WRMEM1_14_FLD3 GENMASK(47, 32) +#define WRMEM1_14_FLD4 GENMASK(63, 48) +#define WRMEM1_14_FLD5 GENMASK(79, 64) +#define WRMEM1_14_FLD6 GENMASK(95, 80) +#define WRMEM1_14_FLD7 GENMASK(111, 96) +#define WRMEM1_14_FLD8 GENMASK(127, 112) + +/* WRMEM1_15 register fields */ +#define WRMEM1_15_FLD1 GENMASK(15, 0) +#define WRMEM1_15_FLD2 GENMASK(31, 16) +#define WRMEM1_15_FLD3 GENMASK(47, 32) +#define WRMEM1_15_FLD4 GENMASK(63, 48) +#define WRMEM1_15_FLD5 GENMASK(79, 64) +#define WRMEM1_15_FLD6 GENMASK(95, 80) +#define WRMEM1_15_FLD7 GENMASK(111, 96) +#define WRMEM1_15_FLD8 GENMASK(127, 112) + +/* WRMEM1_16 register fields */ +#define WRMEM1_16_FLD1 GENMASK(15, 0) +#define WRMEM1_16_FLD2 GENMASK(31, 16) +#define WRMEM1_16_FLD3 GENMASK(47, 32) +#define WRMEM1_16_FLD4 GENMASK(63, 48) +#define WRMEM1_16_FLD5 GENMASK(79, 64) +#define WRMEM1_16_FLD6 GENMASK(95, 80) +#define WRMEM1_16_FLD7 GENMASK(111, 96) +#define WRMEM1_16_FLD8 GENMASK(127, 112) + +/* WRMEM1_17 register fields */ +#define WRMEM1_17_FLD1 GENMASK(15, 0) +#define WRMEM1_17_FLD2 GENMASK(31, 16) +#define WRMEM1_17_FLD3 GENMASK(47, 32) +#define WRMEM1_17_FLD4 GENMASK(63, 48) +#define WRMEM1_17_FLD5 GENMASK(79, 64) +#define WRMEM1_17_FLD6 GENMASK(95, 80) +#define WRMEM1_17_FLD7 GENMASK(111, 96) +#define WRMEM1_17_FLD8 GENMASK(127, 112) + +/* WRMEM1_18 register fields */ +#define WRMEM1_18_FLD1 GENMASK(15, 0) +#define WRMEM1_18_FLD2 GENMASK(31, 16) +#define WRMEM1_18_FLD3 GENMASK(47, 32) +#define WRMEM1_18_FLD4 GENMASK(63, 48) +#define WRMEM1_18_FLD5 GENMASK(79, 64) +#define WRMEM1_18_FLD6 GENMASK(95, 80) +#define WRMEM1_18_FLD7 GENMASK(111, 96) +#define WRMEM1_18_FLD8 GENMASK(127, 112) + +/* WRMEM1_19 register fields */ +#define WRMEM1_19_FLD1 GENMASK(15, 0) +#define WRMEM1_19_FLD2 GENMASK(31, 16) +#define WRMEM1_19_FLD3 GENMASK(47, 32) +#define WRMEM1_19_FLD4 GENMASK(63, 48) +#define WRMEM1_19_FLD5 GENMASK(79, 64) +#define WRMEM1_19_FLD6 GENMASK(95, 80) +#define WRMEM1_19_FLD7 GENMASK(111, 96) +#define WRMEM1_19_FLD8 GENMASK(127, 112) + +/* WRMEM1_20 register fields */ +#define WRMEM1_20_FLD1 GENMASK(15, 0) +#define WRMEM1_20_FLD2 GENMASK(31, 16) +#define WRMEM1_20_FLD3 GENMASK(47, 32) +#define WRMEM1_20_FLD4 GENMASK(63, 48) +#define WRMEM1_20_FLD5 GENMASK(79, 64) +#define WRMEM1_20_FLD6 GENMASK(95, 80) +#define WRMEM1_20_FLD7 GENMASK(111, 96) +#define WRMEM1_20_FLD8 GENMASK(127, 112) + +/* WRMEM1_21 register fields */ +#define WRMEM1_21_FLD1 GENMASK(15, 0) +#define WRMEM1_21_FLD2 GENMASK(31, 16) +#define WRMEM1_21_FLD3 GENMASK(47, 32) +#define WRMEM1_21_FLD4 GENMASK(63, 48) +#define WRMEM1_21_FLD5 GENMASK(79, 64) +#define WRMEM1_21_FLD6 GENMASK(95, 80) +#define WRMEM1_21_FLD7 GENMASK(111, 96) +#define WRMEM1_21_FLD8 GENMASK(127, 112) + +/* WRMEM1_22 register fields */ +#define WRMEM1_22_FLD1 GENMASK(15, 0) +#define WRMEM1_22_FLD2 GENMASK(31, 16) +#define WRMEM1_22_FLD3 GENMASK(47, 32) +#define WRMEM1_22_FLD4 GENMASK(63, 48) +#define WRMEM1_22_FLD5 GENMASK(79, 64) +#define WRMEM1_22_FLD6 GENMASK(95, 80) +#define WRMEM1_22_FLD7 GENMASK(111, 96) +#define WRMEM1_22_FLD8 GENMASK(127, 112) + +/* WRMEM1_23 register fields */ +#define WRMEM1_23_FLD1 GENMASK(15, 0) +#define WRMEM1_23_FLD2 GENMASK(31, 16) +#define WRMEM1_23_FLD3 GENMASK(47, 32) +#define WRMEM1_23_FLD4 GENMASK(63, 48) +#define WRMEM1_23_FLD5 GENMASK(79, 64) +#define WRMEM1_23_FLD6 GENMASK(95, 80) +#define WRMEM1_23_FLD7 GENMASK(111, 96) +#define WRMEM1_23_FLD8 GENMASK(127, 112) + +/* WRMEM1_24 register fields */ +#define WRMEM1_24_FLD1 GENMASK(15, 0) +#define WRMEM1_24_FLD2 GENMASK(31, 16) +#define WRMEM1_24_FLD3 GENMASK(47, 32) +#define WRMEM1_24_FLD4 GENMASK(63, 48) +#define WRMEM1_24_FLD5 GENMASK(79, 64) +#define WRMEM1_24_FLD6 GENMASK(95, 80) +#define WRMEM1_24_FLD7 GENMASK(111, 96) +#define WRMEM1_24_FLD8 GENMASK(127, 112) + +/* WRMEM1_25 register fields */ +#define WRMEM1_25_FLD1 GENMASK(15, 0) +#define WRMEM1_25_FLD2 GENMASK(31, 16) +#define WRMEM1_25_FLD3 GENMASK(47, 32) +#define WRMEM1_25_FLD4 GENMASK(63, 48) +#define WRMEM1_25_FLD5 GENMASK(79, 64) +#define WRMEM1_25_FLD6 GENMASK(95, 80) +#define WRMEM1_25_FLD7 GENMASK(111, 96) +#define WRMEM1_25_FLD8 GENMASK(127, 112) + +/* WRMEM1_26 register fields */ +#define WRMEM1_26_FLD1 GENMASK(15, 0) +#define WRMEM1_26_FLD2 GENMASK(31, 16) +#define WRMEM1_26_FLD3 GENMASK(47, 32) +#define WRMEM1_26_FLD4 GENMASK(63, 48) +#define WRMEM1_26_FLD5 GENMASK(79, 64) +#define WRMEM1_26_FLD6 GENMASK(95, 80) +#define WRMEM1_26_FLD7 GENMASK(111, 96) +#define WRMEM1_26_FLD8 GENMASK(127, 112) + +/* WRMEM1_27 register fields */ +#define WRMEM1_27_FLD1 GENMASK(15, 0) +#define WRMEM1_27_FLD2 GENMASK(31, 16) +#define WRMEM1_27_FLD3 GENMASK(47, 32) +#define WRMEM1_27_FLD4 GENMASK(63, 48) +#define WRMEM1_27_FLD5 GENMASK(79, 64) +#define WRMEM1_27_FLD6 GENMASK(95, 80) +#define WRMEM1_27_FLD7 GENMASK(111, 96) +#define WRMEM1_27_FLD8 GENMASK(127, 112) + +/* WRMEM1_28 register fields */ +#define WRMEM1_28_FLD1 GENMASK(15, 0) +#define WRMEM1_28_FLD2 GENMASK(31, 16) +#define WRMEM1_28_FLD3 GENMASK(47, 32) +#define WRMEM1_28_FLD4 GENMASK(63, 48) +#define WRMEM1_28_FLD5 GENMASK(79, 64) +#define WRMEM1_28_FLD6 GENMASK(95, 80) +#define WRMEM1_28_FLD7 GENMASK(111, 96) +#define WRMEM1_28_FLD8 GENMASK(127, 112) + +/* WRMEM1_29 register fields */ +#define WRMEM1_29_FLD1 GENMASK(15, 0) +#define WRMEM1_29_FLD2 GENMASK(31, 16) +#define WRMEM1_29_FLD3 GENMASK(47, 32) +#define WRMEM1_29_FLD4 GENMASK(63, 48) +#define WRMEM1_29_FLD5 GENMASK(79, 64) +#define WRMEM1_29_FLD6 GENMASK(95, 80) +#define WRMEM1_29_FLD7 GENMASK(111, 96) +#define WRMEM1_29_FLD8 GENMASK(127, 112) + +/* WRMEM1_30 register fields */ +#define WRMEM1_30_FLD1 GENMASK(15, 0) +#define WRMEM1_30_FLD2 GENMASK(31, 16) +#define WRMEM1_30_FLD3 GENMASK(47, 32) +#define WRMEM1_30_FLD4 GENMASK(63, 48) +#define WRMEM1_30_FLD5 GENMASK(79, 64) +#define WRMEM1_30_FLD6 GENMASK(95, 80) +#define WRMEM1_30_FLD7 GENMASK(111, 96) +#define WRMEM1_30_FLD8 GENMASK(127, 112) + +/* WRMEM1_31 register fields */ +#define WRMEM1_31_FLD1 GENMASK(15, 0) +#define WRMEM1_31_FLD2 GENMASK(31, 16) +#define WRMEM1_31_FLD3 GENMASK(47, 32) +#define WRMEM1_31_FLD4 GENMASK(63, 48) +#define WRMEM1_31_FLD5 GENMASK(79, 64) +#define WRMEM1_31_FLD6 GENMASK(95, 80) +#define WRMEM1_31_FLD7 GENMASK(111, 96) +#define WRMEM1_31_FLD8 GENMASK(127, 112) + +/* WRMEM1_32 register fields */ +#define WRMEM1_32_FLD1 GENMASK(15, 0) +#define WRMEM1_32_FLD2 GENMASK(31, 16) +#define WRMEM1_32_FLD3 GENMASK(47, 32) +#define WRMEM1_32_FLD4 GENMASK(63, 48) +#define WRMEM1_32_FLD5 GENMASK(79, 64) +#define WRMEM1_32_FLD6 GENMASK(95, 80) +#define WRMEM1_32_FLD7 GENMASK(111, 96) +#define WRMEM1_32_FLD8 GENMASK(127, 112) + +/* WRMEM1_33 register fields */ +#define WRMEM1_33_FLD1 GENMASK(15, 0) +#define WRMEM1_33_FLD2 GENMASK(31, 16) +#define WRMEM1_33_FLD3 GENMASK(47, 32) +#define WRMEM1_33_FLD4 GENMASK(63, 48) +#define WRMEM1_33_FLD5 GENMASK(79, 64) +#define WRMEM1_33_FLD6 GENMASK(95, 80) +#define WRMEM1_33_FLD7 GENMASK(111, 96) +#define WRMEM1_33_FLD8 GENMASK(127, 112) + +/* WRMEM1_34 register fields */ +#define WRMEM1_34_FLD1 GENMASK(15, 0) +#define WRMEM1_34_FLD2 GENMASK(31, 16) +#define WRMEM1_34_FLD3 GENMASK(47, 32) +#define WRMEM1_34_FLD4 GENMASK(63, 48) +#define WRMEM1_34_FLD5 GENMASK(79, 64) +#define WRMEM1_34_FLD6 GENMASK(95, 80) +#define WRMEM1_34_FLD7 GENMASK(111, 96) +#define WRMEM1_34_FLD8 GENMASK(127, 112) + +/* WRMEM1_35 register fields */ +#define WRMEM1_35_FLD1 GENMASK(15, 0) +#define WRMEM1_35_FLD2 GENMASK(31, 16) +#define WRMEM1_35_FLD3 GENMASK(47, 32) +#define WRMEM1_35_FLD4 GENMASK(63, 48) +#define WRMEM1_35_FLD5 GENMASK(79, 64) +#define WRMEM1_35_FLD6 GENMASK(95, 80) +#define WRMEM1_35_FLD7 GENMASK(111, 96) +#define WRMEM1_35_FLD8 GENMASK(127, 112) + +/* WRMEM1_36 register fields */ +#define WRMEM1_36_FLD1 GENMASK(15, 0) +#define WRMEM1_36_FLD2 GENMASK(31, 16) +#define WRMEM1_36_FLD3 GENMASK(47, 32) +#define WRMEM1_36_FLD4 GENMASK(63, 48) +#define WRMEM1_36_FLD5 GENMASK(79, 64) +#define WRMEM1_36_FLD6 GENMASK(95, 80) +#define WRMEM1_36_FLD7 GENMASK(111, 96) +#define WRMEM1_36_FLD8 GENMASK(127, 112) + +/* WRMEM1_37 register fields */ +#define WRMEM1_37_FLD1 GENMASK(15, 0) +#define WRMEM1_37_FLD2 GENMASK(31, 16) +#define WRMEM1_37_FLD3 GENMASK(47, 32) +#define WRMEM1_37_FLD4 GENMASK(63, 48) +#define WRMEM1_37_FLD5 GENMASK(79, 64) +#define WRMEM1_37_FLD6 GENMASK(95, 80) +#define WRMEM1_37_FLD7 GENMASK(111, 96) +#define WRMEM1_37_FLD8 GENMASK(127, 112) + +/* WRMEM1_38 register fields */ +#define WRMEM1_38_FLD1 GENMASK(15, 0) +#define WRMEM1_38_FLD2 GENMASK(31, 16) +#define WRMEM1_38_FLD3 GENMASK(47, 32) +#define WRMEM1_38_FLD4 GENMASK(63, 48) +#define WRMEM1_38_FLD5 GENMASK(79, 64) +#define WRMEM1_38_FLD6 GENMASK(95, 80) +#define WRMEM1_38_FLD7 GENMASK(111, 96) +#define WRMEM1_38_FLD8 GENMASK(127, 112) + +/* WRMEM1_39 register fields */ +#define WRMEM1_39_FLD1 GENMASK(15, 0) +#define WRMEM1_39_FLD2 GENMASK(31, 16) +#define WRMEM1_39_FLD3 GENMASK(47, 32) +#define WRMEM1_39_FLD4 GENMASK(63, 48) +#define WRMEM1_39_FLD5 GENMASK(79, 64) +#define WRMEM1_39_FLD6 GENMASK(95, 80) +#define WRMEM1_39_FLD7 GENMASK(111, 96) +#define WRMEM1_39_FLD8 GENMASK(127, 112) + +/* WRMEM1_40 register fields */ +#define WRMEM1_40_FLD1 GENMASK(15, 0) +#define WRMEM1_40_FLD2 GENMASK(31, 16) +#define WRMEM1_40_FLD3 GENMASK(47, 32) +#define WRMEM1_40_FLD4 GENMASK(63, 48) +#define WRMEM1_40_FLD5 GENMASK(79, 64) +#define WRMEM1_40_FLD6 GENMASK(95, 80) +#define WRMEM1_40_FLD7 GENMASK(111, 96) +#define WRMEM1_40_FLD8 GENMASK(127, 112) + +/* WRMEM1_41 register fields */ +#define WRMEM1_41_FLD1 GENMASK(15, 0) +#define WRMEM1_41_FLD2 GENMASK(31, 16) +#define WRMEM1_41_FLD3 GENMASK(47, 32) +#define WRMEM1_41_FLD4 GENMASK(63, 48) +#define WRMEM1_41_FLD5 GENMASK(79, 64) +#define WRMEM1_41_FLD6 GENMASK(95, 80) +#define WRMEM1_41_FLD7 GENMASK(111, 96) +#define WRMEM1_41_FLD8 GENMASK(127, 112) + +/* WRMEM1_42 register fields */ +#define WRMEM1_42_FLD1 GENMASK(15, 0) +#define WRMEM1_42_FLD2 GENMASK(31, 16) +#define WRMEM1_42_FLD3 GENMASK(47, 32) +#define WRMEM1_42_FLD4 GENMASK(63, 48) +#define WRMEM1_42_FLD5 GENMASK(79, 64) +#define WRMEM1_42_FLD6 GENMASK(95, 80) +#define WRMEM1_42_FLD7 GENMASK(111, 96) +#define WRMEM1_42_FLD8 GENMASK(127, 112) + +/* WRMEM1_43 register fields */ +#define WRMEM1_43_FLD1 GENMASK(15, 0) +#define WRMEM1_43_FLD2 GENMASK(31, 16) +#define WRMEM1_43_FLD3 GENMASK(47, 32) +#define WRMEM1_43_FLD4 GENMASK(63, 48) +#define WRMEM1_43_FLD5 GENMASK(79, 64) +#define WRMEM1_43_FLD6 GENMASK(95, 80) +#define WRMEM1_43_FLD7 GENMASK(111, 96) +#define WRMEM1_43_FLD8 GENMASK(127, 112) + +/* WRMEM1_44 register fields */ +#define WRMEM1_44_FLD1 GENMASK(15, 0) +#define WRMEM1_44_FLD2 GENMASK(31, 16) +#define WRMEM1_44_FLD3 GENMASK(47, 32) +#define WRMEM1_44_FLD4 GENMASK(63, 48) +#define WRMEM1_44_FLD5 GENMASK(79, 64) +#define WRMEM1_44_FLD6 GENMASK(95, 80) +#define WRMEM1_44_FLD7 GENMASK(111, 96) +#define WRMEM1_44_FLD8 GENMASK(127, 112) + +/* WRMEM1_45 register fields */ +#define WRMEM1_45_FLD1 GENMASK(15, 0) +#define WRMEM1_45_FLD2 GENMASK(31, 16) +#define WRMEM1_45_FLD3 GENMASK(47, 32) +#define WRMEM1_45_FLD4 GENMASK(63, 48) +#define WRMEM1_45_FLD5 GENMASK(79, 64) +#define WRMEM1_45_FLD6 GENMASK(95, 80) +#define WRMEM1_45_FLD7 GENMASK(111, 96) +#define WRMEM1_45_FLD8 GENMASK(127, 112) + +/* WRMEM1_46 register fields */ +#define WRMEM1_46_FLD1 GENMASK(15, 0) +#define WRMEM1_46_FLD2 GENMASK(31, 16) +#define WRMEM1_46_FLD3 GENMASK(47, 32) +#define WRMEM1_46_FLD4 GENMASK(63, 48) +#define WRMEM1_46_FLD5 GENMASK(79, 64) +#define WRMEM1_46_FLD6 GENMASK(95, 80) +#define WRMEM1_46_FLD7 GENMASK(111, 96) +#define WRMEM1_46_FLD8 GENMASK(127, 112) + +/* WRMEM1_47 register fields */ +#define WRMEM1_47_FLD1 GENMASK(15, 0) +#define WRMEM1_47_FLD2 GENMASK(31, 16) +#define WRMEM1_47_FLD3 GENMASK(47, 32) +#define WRMEM1_47_FLD4 GENMASK(63, 48) +#define WRMEM1_47_FLD5 GENMASK(79, 64) +#define WRMEM1_47_FLD6 GENMASK(95, 80) +#define WRMEM1_47_FLD7 GENMASK(111, 96) +#define WRMEM1_47_FLD8 GENMASK(127, 112) + +/* WRMEM1_48 register fields */ +#define WRMEM1_48_FLD1 GENMASK(15, 0) +#define WRMEM1_48_FLD2 GENMASK(31, 16) +#define WRMEM1_48_FLD3 GENMASK(47, 32) +#define WRMEM1_48_FLD4 GENMASK(63, 48) +#define WRMEM1_48_FLD5 GENMASK(79, 64) +#define WRMEM1_48_FLD6 GENMASK(95, 80) +#define WRMEM1_48_FLD7 GENMASK(111, 96) +#define WRMEM1_48_FLD8 GENMASK(127, 112) + +/* WRMEM1_49 register fields */ +#define WRMEM1_49_FLD1 GENMASK(15, 0) +#define WRMEM1_49_FLD2 GENMASK(31, 16) +#define WRMEM1_49_FLD3 GENMASK(47, 32) +#define WRMEM1_49_FLD4 GENMASK(63, 48) +#define WRMEM1_49_FLD5 GENMASK(79, 64) +#define WRMEM1_49_FLD6 GENMASK(95, 80) +#define WRMEM1_49_FLD7 GENMASK(111, 96) +#define WRMEM1_49_FLD8 GENMASK(127, 112) + +/* WRMEM1_50 register fields */ +#define WRMEM1_50_FLD1 GENMASK(15, 0) +#define WRMEM1_50_FLD2 GENMASK(31, 16) +#define WRMEM1_50_FLD3 GENMASK(47, 32) +#define WRMEM1_50_FLD4 GENMASK(63, 48) +#define WRMEM1_50_FLD5 GENMASK(79, 64) +#define WRMEM1_50_FLD6 GENMASK(95, 80) +#define WRMEM1_50_FLD7 GENMASK(111, 96) +#define WRMEM1_50_FLD8 GENMASK(127, 112) + +/* WRMEM1_51 register fields */ +#define WRMEM1_51_FLD1 GENMASK(15, 0) +#define WRMEM1_51_FLD2 GENMASK(31, 16) +#define WRMEM1_51_FLD3 GENMASK(47, 32) +#define WRMEM1_51_FLD4 GENMASK(63, 48) +#define WRMEM1_51_FLD5 GENMASK(79, 64) +#define WRMEM1_51_FLD6 GENMASK(95, 80) +#define WRMEM1_51_FLD7 GENMASK(111, 96) +#define WRMEM1_51_FLD8 GENMASK(127, 112) + +/* WRMEM1_52 register fields */ +#define WRMEM1_52_FLD1 GENMASK(15, 0) +#define WRMEM1_52_FLD2 GENMASK(31, 16) +#define WRMEM1_52_FLD3 GENMASK(47, 32) +#define WRMEM1_52_FLD4 GENMASK(63, 48) +#define WRMEM1_52_FLD5 GENMASK(79, 64) +#define WRMEM1_52_FLD6 GENMASK(95, 80) +#define WRMEM1_52_FLD7 GENMASK(111, 96) +#define WRMEM1_52_FLD8 GENMASK(127, 112) + +/* WRMEM1_53 register fields */ +#define WRMEM1_53_FLD1 GENMASK(15, 0) +#define WRMEM1_53_FLD2 GENMASK(31, 16) +#define WRMEM1_53_FLD3 GENMASK(47, 32) +#define WRMEM1_53_FLD4 GENMASK(63, 48) +#define WRMEM1_53_FLD5 GENMASK(79, 64) +#define WRMEM1_53_FLD6 GENMASK(95, 80) +#define WRMEM1_53_FLD7 GENMASK(111, 96) +#define WRMEM1_53_FLD8 GENMASK(127, 112) + +/* WRMEM1_54 register fields */ +#define WRMEM1_54_FLD1 GENMASK(15, 0) +#define WRMEM1_54_FLD2 GENMASK(31, 16) +#define WRMEM1_54_FLD3 GENMASK(47, 32) +#define WRMEM1_54_FLD4 GENMASK(63, 48) +#define WRMEM1_54_FLD5 GENMASK(79, 64) +#define WRMEM1_54_FLD6 GENMASK(95, 80) +#define WRMEM1_54_FLD7 GENMASK(111, 96) +#define WRMEM1_54_FLD8 GENMASK(127, 112) + +/* WRMEM1_55 register fields */ +#define WRMEM1_55_FLD1 GENMASK(15, 0) +#define WRMEM1_55_FLD2 GENMASK(31, 16) +#define WRMEM1_55_FLD3 GENMASK(47, 32) +#define WRMEM1_55_FLD4 GENMASK(63, 48) +#define WRMEM1_55_FLD5 GENMASK(79, 64) +#define WRMEM1_55_FLD6 GENMASK(95, 80) +#define WRMEM1_55_FLD7 GENMASK(111, 96) +#define WRMEM1_55_FLD8 GENMASK(127, 112) + +/* WRMEM1_56 register fields */ +#define WRMEM1_56_FLD1 GENMASK(15, 0) +#define WRMEM1_56_FLD2 GENMASK(31, 16) +#define WRMEM1_56_FLD3 GENMASK(47, 32) +#define WRMEM1_56_FLD4 GENMASK(63, 48) +#define WRMEM1_56_FLD5 GENMASK(79, 64) +#define WRMEM1_56_FLD6 GENMASK(95, 80) +#define WRMEM1_56_FLD7 GENMASK(111, 96) +#define WRMEM1_56_FLD8 GENMASK(127, 112) + +/* WRMEM1_57 register fields */ +#define WRMEM1_57_FLD1 GENMASK(15, 0) +#define WRMEM1_57_FLD2 GENMASK(31, 16) +#define WRMEM1_57_FLD3 GENMASK(47, 32) +#define WRMEM1_57_FLD4 GENMASK(63, 48) +#define WRMEM1_57_FLD5 GENMASK(79, 64) +#define WRMEM1_57_FLD6 GENMASK(95, 80) +#define WRMEM1_57_FLD7 GENMASK(111, 96) +#define WRMEM1_57_FLD8 GENMASK(127, 112) + +/* WRMEM1_58 register fields */ +#define WRMEM1_58_FLD1 GENMASK(15, 0) +#define WRMEM1_58_FLD2 GENMASK(31, 16) +#define WRMEM1_58_FLD3 GENMASK(47, 32) +#define WRMEM1_58_FLD4 GENMASK(63, 48) +#define WRMEM1_58_FLD5 GENMASK(79, 64) +#define WRMEM1_58_FLD6 GENMASK(95, 80) +#define WRMEM1_58_FLD7 GENMASK(111, 96) +#define WRMEM1_58_FLD8 GENMASK(127, 112) + +/* WRMEM1_59 register fields */ +#define WRMEM1_59_FLD1 GENMASK(15, 0) +#define WRMEM1_59_FLD2 GENMASK(31, 16) +#define WRMEM1_59_FLD3 GENMASK(47, 32) +#define WRMEM1_59_FLD4 GENMASK(63, 48) +#define WRMEM1_59_FLD5 GENMASK(79, 64) +#define WRMEM1_59_FLD6 GENMASK(95, 80) +#define WRMEM1_59_FLD7 GENMASK(111, 96) +#define WRMEM1_59_FLD8 GENMASK(127, 112) + +/* WRMEM1_60 register fields */ +#define WRMEM1_60_FLD1 GENMASK(15, 0) +#define WRMEM1_60_FLD2 GENMASK(31, 16) +#define WRMEM1_60_FLD3 GENMASK(47, 32) +#define WRMEM1_60_FLD4 GENMASK(63, 48) +#define WRMEM1_60_FLD5 GENMASK(79, 64) +#define WRMEM1_60_FLD6 GENMASK(95, 80) +#define WRMEM1_60_FLD7 GENMASK(111, 96) +#define WRMEM1_60_FLD8 GENMASK(127, 112) + +/* WRMEM1_61 register fields */ +#define WRMEM1_61_FLD1 GENMASK(15, 0) +#define WRMEM1_61_FLD2 GENMASK(31, 16) +#define WRMEM1_61_FLD3 GENMASK(47, 32) +#define WRMEM1_61_FLD4 GENMASK(63, 48) +#define WRMEM1_61_FLD5 GENMASK(79, 64) +#define WRMEM1_61_FLD6 GENMASK(95, 80) +#define WRMEM1_61_FLD7 GENMASK(111, 96) +#define WRMEM1_61_FLD8 GENMASK(127, 112) + +/* WRMEM1_62 register fields */ +#define WRMEM1_62_FLD1 GENMASK(15, 0) +#define WRMEM1_62_FLD2 GENMASK(31, 16) +#define WRMEM1_62_FLD3 GENMASK(47, 32) +#define WRMEM1_62_FLD4 GENMASK(63, 48) +#define WRMEM1_62_FLD5 GENMASK(79, 64) +#define WRMEM1_62_FLD6 GENMASK(95, 80) +#define WRMEM1_62_FLD7 GENMASK(111, 96) +#define WRMEM1_62_FLD8 GENMASK(127, 112) + +/* WRMEM1_63 register fields */ +#define WRMEM1_63_FLD1 GENMASK(15, 0) +#define WRMEM1_63_FLD2 GENMASK(31, 16) +#define WRMEM1_63_FLD3 GENMASK(47, 32) +#define WRMEM1_63_FLD4 GENMASK(63, 48) +#define WRMEM1_63_FLD5 GENMASK(79, 64) +#define WRMEM1_63_FLD6 GENMASK(95, 80) +#define WRMEM1_63_FLD7 GENMASK(111, 96) +#define WRMEM1_63_FLD8 GENMASK(127, 112) + +/* WRMEM1_64 register fields */ +#define WRMEM1_64_FLD1 GENMASK(15, 0) +#define WRMEM1_64_FLD2 GENMASK(31, 16) +#define WRMEM1_64_FLD3 GENMASK(47, 32) +#define WRMEM1_64_FLD4 GENMASK(63, 48) +#define WRMEM1_64_FLD5 GENMASK(79, 64) +#define WRMEM1_64_FLD6 GENMASK(95, 80) +#define WRMEM1_64_FLD7 GENMASK(111, 96) +#define WRMEM1_64_FLD8 GENMASK(127, 112) + +/* WRMEM1_65 register fields */ +#define WRMEM1_65_FLD1 GENMASK(15, 0) +#define WRMEM1_65_FLD2 GENMASK(31, 16) +#define WRMEM1_65_FLD3 GENMASK(47, 32) +#define WRMEM1_65_FLD4 GENMASK(63, 48) +#define WRMEM1_65_FLD5 GENMASK(79, 64) +#define WRMEM1_65_FLD6 GENMASK(95, 80) +#define WRMEM1_65_FLD7 GENMASK(111, 96) +#define WRMEM1_65_FLD8 GENMASK(127, 112) + +/* WRMEM1_66 register fields */ +#define WRMEM1_66_FLD1 GENMASK(15, 0) +#define WRMEM1_66_FLD2 GENMASK(31, 16) +#define WRMEM1_66_FLD3 GENMASK(47, 32) +#define WRMEM1_66_FLD4 GENMASK(63, 48) +#define WRMEM1_66_FLD5 GENMASK(79, 64) +#define WRMEM1_66_FLD6 GENMASK(95, 80) +#define WRMEM1_66_FLD7 GENMASK(111, 96) +#define WRMEM1_66_FLD8 GENMASK(127, 112) + +/* WRMEM1_67 register fields */ +#define WRMEM1_67_FLD1 GENMASK(15, 0) +#define WRMEM1_67_FLD2 GENMASK(31, 16) +#define WRMEM1_67_FLD3 GENMASK(47, 32) +#define WRMEM1_67_FLD4 GENMASK(63, 48) +#define WRMEM1_67_FLD5 GENMASK(79, 64) +#define WRMEM1_67_FLD6 GENMASK(95, 80) +#define WRMEM1_67_FLD7 GENMASK(111, 96) +#define WRMEM1_67_FLD8 GENMASK(127, 112) + +/* WRMEM1_68 register fields */ +#define WRMEM1_68_FLD1 GENMASK(15, 0) +#define WRMEM1_68_FLD2 GENMASK(31, 16) +#define WRMEM1_68_FLD3 GENMASK(47, 32) +#define WRMEM1_68_FLD4 GENMASK(63, 48) +#define WRMEM1_68_FLD5 GENMASK(79, 64) +#define WRMEM1_68_FLD6 GENMASK(95, 80) +#define WRMEM1_68_FLD7 GENMASK(111, 96) +#define WRMEM1_68_FLD8 GENMASK(127, 112) + +/* WRMEM1_69 register fields */ +#define WRMEM1_69_FLD1 GENMASK(15, 0) +#define WRMEM1_69_FLD2 GENMASK(31, 16) +#define WRMEM1_69_FLD3 GENMASK(47, 32) +#define WRMEM1_69_FLD4 GENMASK(63, 48) +#define WRMEM1_69_FLD5 GENMASK(79, 64) +#define WRMEM1_69_FLD6 GENMASK(95, 80) +#define WRMEM1_69_FLD7 GENMASK(111, 96) +#define WRMEM1_69_FLD8 GENMASK(127, 112) + +/* WRMEM1_70 register fields */ +#define WRMEM1_70_FLD1 GENMASK(15, 0) +#define WRMEM1_70_FLD2 GENMASK(31, 16) +#define WRMEM1_70_FLD3 GENMASK(47, 32) +#define WRMEM1_70_FLD4 GENMASK(63, 48) +#define WRMEM1_70_FLD5 GENMASK(79, 64) +#define WRMEM1_70_FLD6 GENMASK(95, 80) +#define WRMEM1_70_FLD7 GENMASK(111, 96) +#define WRMEM1_70_FLD8 GENMASK(127, 112) + +/* WRMEM1_71 register fields */ +#define WRMEM1_71_FLD1 GENMASK(15, 0) +#define WRMEM1_71_FLD2 GENMASK(31, 16) +#define WRMEM1_71_FLD3 GENMASK(47, 32) +#define WRMEM1_71_FLD4 GENMASK(63, 48) +#define WRMEM1_71_FLD5 GENMASK(79, 64) +#define WRMEM1_71_FLD6 GENMASK(95, 80) +#define WRMEM1_71_FLD7 GENMASK(111, 96) +#define WRMEM1_71_FLD8 GENMASK(127, 112) + +/* WRMEM1_72 register fields */ +#define WRMEM1_72_FLD1 GENMASK(15, 0) +#define WRMEM1_72_FLD2 GENMASK(31, 16) +#define WRMEM1_72_FLD3 GENMASK(47, 32) +#define WRMEM1_72_FLD4 GENMASK(63, 48) +#define WRMEM1_72_FLD5 GENMASK(79, 64) +#define WRMEM1_72_FLD6 GENMASK(95, 80) +#define WRMEM1_72_FLD7 GENMASK(111, 96) +#define WRMEM1_72_FLD8 GENMASK(127, 112) + +/* WRMEM1_73 register fields */ +#define WRMEM1_73_FLD1 GENMASK(15, 0) +#define WRMEM1_73_FLD2 GENMASK(31, 16) +#define WRMEM1_73_FLD3 GENMASK(47, 32) +#define WRMEM1_73_FLD4 GENMASK(63, 48) +#define WRMEM1_73_FLD5 GENMASK(79, 64) +#define WRMEM1_73_FLD6 GENMASK(95, 80) +#define WRMEM1_73_FLD7 GENMASK(111, 96) +#define WRMEM1_73_FLD8 GENMASK(127, 112) + +/* WRMEM1_74 register fields */ +#define WRMEM1_74_FLD1 GENMASK(15, 0) +#define WRMEM1_74_FLD2 GENMASK(31, 16) +#define WRMEM1_74_FLD3 GENMASK(47, 32) +#define WRMEM1_74_FLD4 GENMASK(63, 48) +#define WRMEM1_74_FLD5 GENMASK(79, 64) +#define WRMEM1_74_FLD6 GENMASK(95, 80) +#define WRMEM1_74_FLD7 GENMASK(111, 96) +#define WRMEM1_74_FLD8 GENMASK(127, 112) + +/* WRMEM1_75 register fields */ +#define WRMEM1_75_FLD1 GENMASK(15, 0) +#define WRMEM1_75_FLD2 GENMASK(31, 16) +#define WRMEM1_75_FLD3 GENMASK(47, 32) +#define WRMEM1_75_FLD4 GENMASK(63, 48) +#define WRMEM1_75_FLD5 GENMASK(79, 64) +#define WRMEM1_75_FLD6 GENMASK(95, 80) +#define WRMEM1_75_FLD7 GENMASK(111, 96) +#define WRMEM1_75_FLD8 GENMASK(127, 112) + +/* WRMEM1_76 register fields */ +#define WRMEM1_76_FLD1 GENMASK(15, 0) +#define WRMEM1_76_FLD2 GENMASK(31, 16) +#define WRMEM1_76_FLD3 GENMASK(47, 32) +#define WRMEM1_76_FLD4 GENMASK(63, 48) +#define WRMEM1_76_FLD5 GENMASK(79, 64) +#define WRMEM1_76_FLD6 GENMASK(95, 80) +#define WRMEM1_76_FLD7 GENMASK(111, 96) +#define WRMEM1_76_FLD8 GENMASK(127, 112) + +/* WRMEM1_77 register fields */ +#define WRMEM1_77_FLD1 GENMASK(15, 0) +#define WRMEM1_77_FLD2 GENMASK(31, 16) +#define WRMEM1_77_FLD3 GENMASK(47, 32) +#define WRMEM1_77_FLD4 GENMASK(63, 48) +#define WRMEM1_77_FLD5 GENMASK(79, 64) +#define WRMEM1_77_FLD6 GENMASK(95, 80) +#define WRMEM1_77_FLD7 GENMASK(111, 96) +#define WRMEM1_77_FLD8 GENMASK(127, 112) + +/* WRMEM1_78 register fields */ +#define WRMEM1_78_FLD1 GENMASK(15, 0) +#define WRMEM1_78_FLD2 GENMASK(31, 16) +#define WRMEM1_78_FLD3 GENMASK(47, 32) +#define WRMEM1_78_FLD4 GENMASK(63, 48) +#define WRMEM1_78_FLD5 GENMASK(79, 64) +#define WRMEM1_78_FLD6 GENMASK(95, 80) +#define WRMEM1_78_FLD7 GENMASK(111, 96) +#define WRMEM1_78_FLD8 GENMASK(127, 112) + +/* WRMEM1_79 register fields */ +#define WRMEM1_79_FLD1 GENMASK(15, 0) +#define WRMEM1_79_FLD2 GENMASK(31, 16) +#define WRMEM1_79_FLD3 GENMASK(47, 32) +#define WRMEM1_79_FLD4 GENMASK(63, 48) +#define WRMEM1_79_FLD5 GENMASK(79, 64) +#define WRMEM1_79_FLD6 GENMASK(95, 80) +#define WRMEM1_79_FLD7 GENMASK(111, 96) +#define WRMEM1_79_FLD8 GENMASK(127, 112) + +/* WRMEM1_80 register fields */ +#define WRMEM1_80_FLD1 GENMASK(15, 0) +#define WRMEM1_80_FLD2 GENMASK(31, 16) +#define WRMEM1_80_FLD3 GENMASK(47, 32) +#define WRMEM1_80_FLD4 GENMASK(63, 48) +#define WRMEM1_80_FLD5 GENMASK(79, 64) +#define WRMEM1_80_FLD6 GENMASK(95, 80) +#define WRMEM1_80_FLD7 GENMASK(111, 96) +#define WRMEM1_80_FLD8 GENMASK(127, 112) + +/* WRMEM1_81 register fields */ +#define WRMEM1_81_FLD1 GENMASK(15, 0) +#define WRMEM1_81_FLD2 GENMASK(31, 16) +#define WRMEM1_81_FLD3 GENMASK(47, 32) +#define WRMEM1_81_FLD4 GENMASK(63, 48) +#define WRMEM1_81_FLD5 GENMASK(79, 64) +#define WRMEM1_81_FLD6 GENMASK(95, 80) +#define WRMEM1_81_FLD7 GENMASK(111, 96) +#define WRMEM1_81_FLD8 GENMASK(127, 112) + +/* WRMEM1_82 register fields */ +#define WRMEM1_82_FLD1 GENMASK(15, 0) +#define WRMEM1_82_FLD2 GENMASK(31, 16) +#define WRMEM1_82_FLD3 GENMASK(47, 32) +#define WRMEM1_82_FLD4 GENMASK(63, 48) +#define WRMEM1_82_FLD5 GENMASK(79, 64) +#define WRMEM1_82_FLD6 GENMASK(95, 80) +#define WRMEM1_82_FLD7 GENMASK(111, 96) +#define WRMEM1_82_FLD8 GENMASK(127, 112) + +/* WRMEM1_83 register fields */ +#define WRMEM1_83_FLD1 GENMASK(15, 0) +#define WRMEM1_83_FLD2 GENMASK(31, 16) +#define WRMEM1_83_FLD3 GENMASK(47, 32) +#define WRMEM1_83_FLD4 GENMASK(63, 48) +#define WRMEM1_83_FLD5 GENMASK(79, 64) +#define WRMEM1_83_FLD6 GENMASK(95, 80) +#define WRMEM1_83_FLD7 GENMASK(111, 96) +#define WRMEM1_83_FLD8 GENMASK(127, 112) + +/* WRMEM1_84 register fields */ +#define WRMEM1_84_FLD1 GENMASK(15, 0) +#define WRMEM1_84_FLD2 GENMASK(31, 16) +#define WRMEM1_84_FLD3 GENMASK(47, 32) +#define WRMEM1_84_FLD4 GENMASK(63, 48) +#define WRMEM1_84_FLD5 GENMASK(79, 64) +#define WRMEM1_84_FLD6 GENMASK(95, 80) +#define WRMEM1_84_FLD7 GENMASK(111, 96) +#define WRMEM1_84_FLD8 GENMASK(127, 112) + +/* WRMEM1_85 register fields */ +#define WRMEM1_85_FLD1 GENMASK(15, 0) +#define WRMEM1_85_FLD2 GENMASK(31, 16) +#define WRMEM1_85_FLD3 GENMASK(47, 32) +#define WRMEM1_85_FLD4 GENMASK(63, 48) +#define WRMEM1_85_FLD5 GENMASK(79, 64) +#define WRMEM1_85_FLD6 GENMASK(95, 80) +#define WRMEM1_85_FLD7 GENMASK(111, 96) +#define WRMEM1_85_FLD8 GENMASK(127, 112) + +/* WRMEM1_86 register fields */ +#define WRMEM1_86_FLD1 GENMASK(15, 0) +#define WRMEM1_86_FLD2 GENMASK(31, 16) +#define WRMEM1_86_FLD3 GENMASK(47, 32) +#define WRMEM1_86_FLD4 GENMASK(63, 48) +#define WRMEM1_86_FLD5 GENMASK(79, 64) +#define WRMEM1_86_FLD6 GENMASK(95, 80) +#define WRMEM1_86_FLD7 GENMASK(111, 96) +#define WRMEM1_86_FLD8 GENMASK(127, 112) + +/* WRMEM1_87 register fields */ +#define WRMEM1_87_FLD1 GENMASK(15, 0) +#define WRMEM1_87_FLD2 GENMASK(31, 16) +#define WRMEM1_87_FLD3 GENMASK(47, 32) +#define WRMEM1_87_FLD4 GENMASK(63, 48) +#define WRMEM1_87_FLD5 GENMASK(79, 64) +#define WRMEM1_87_FLD6 GENMASK(95, 80) +#define WRMEM1_87_FLD7 GENMASK(111, 96) +#define WRMEM1_87_FLD8 GENMASK(127, 112) + +/* WRMEM1_88 register fields */ +#define WRMEM1_88_FLD1 GENMASK(15, 0) +#define WRMEM1_88_FLD2 GENMASK(31, 16) +#define WRMEM1_88_FLD3 GENMASK(47, 32) +#define WRMEM1_88_FLD4 GENMASK(63, 48) +#define WRMEM1_88_FLD5 GENMASK(79, 64) +#define WRMEM1_88_FLD6 GENMASK(95, 80) +#define WRMEM1_88_FLD7 GENMASK(111, 96) +#define WRMEM1_88_FLD8 GENMASK(127, 112) + +/* WRMEM1_89 register fields */ +#define WRMEM1_89_FLD1 GENMASK(15, 0) +#define WRMEM1_89_FLD2 GENMASK(31, 16) +#define WRMEM1_89_FLD3 GENMASK(47, 32) +#define WRMEM1_89_FLD4 GENMASK(63, 48) +#define WRMEM1_89_FLD5 GENMASK(79, 64) +#define WRMEM1_89_FLD6 GENMASK(95, 80) +#define WRMEM1_89_FLD7 GENMASK(111, 96) +#define WRMEM1_89_FLD8 GENMASK(127, 112) + +/* WRMEM1_90 register fields */ +#define WRMEM1_90_FLD1 GENMASK(15, 0) +#define WRMEM1_90_FLD2 GENMASK(31, 16) +#define WRMEM1_90_FLD3 GENMASK(47, 32) +#define WRMEM1_90_FLD4 GENMASK(63, 48) +#define WRMEM1_90_FLD5 GENMASK(79, 64) +#define WRMEM1_90_FLD6 GENMASK(95, 80) +#define WRMEM1_90_FLD7 GENMASK(111, 96) +#define WRMEM1_90_FLD8 GENMASK(127, 112) + +/* WRMEM1_91 register fields */ +#define WRMEM1_91_FLD1 GENMASK(15, 0) +#define WRMEM1_91_FLD2 GENMASK(31, 16) +#define WRMEM1_91_FLD3 GENMASK(47, 32) +#define WRMEM1_91_FLD4 GENMASK(63, 48) +#define WRMEM1_91_FLD5 GENMASK(79, 64) +#define WRMEM1_91_FLD6 GENMASK(95, 80) +#define WRMEM1_91_FLD7 GENMASK(111, 96) +#define WRMEM1_91_FLD8 GENMASK(127, 112) + +/* WRMEM1_92 register fields */ +#define WRMEM1_92_FLD1 GENMASK(15, 0) +#define WRMEM1_92_FLD2 GENMASK(31, 16) +#define WRMEM1_92_FLD3 GENMASK(47, 32) +#define WRMEM1_92_FLD4 GENMASK(63, 48) +#define WRMEM1_92_FLD5 GENMASK(79, 64) +#define WRMEM1_92_FLD6 GENMASK(95, 80) +#define WRMEM1_92_FLD7 GENMASK(111, 96) +#define WRMEM1_92_FLD8 GENMASK(127, 112) + +/* WRMEM1_93 register fields */ +#define WRMEM1_93_FLD1 GENMASK(15, 0) +#define WRMEM1_93_FLD2 GENMASK(31, 16) +#define WRMEM1_93_FLD3 GENMASK(47, 32) +#define WRMEM1_93_FLD4 GENMASK(63, 48) +#define WRMEM1_93_FLD5 GENMASK(79, 64) +#define WRMEM1_93_FLD6 GENMASK(95, 80) +#define WRMEM1_93_FLD7 GENMASK(111, 96) +#define WRMEM1_93_FLD8 GENMASK(127, 112) + +/* WRMEM1_94 register fields */ +#define WRMEM1_94_FLD1 GENMASK(15, 0) +#define WRMEM1_94_FLD2 GENMASK(31, 16) +#define WRMEM1_94_FLD3 GENMASK(47, 32) +#define WRMEM1_94_FLD4 GENMASK(63, 48) +#define WRMEM1_94_FLD5 GENMASK(79, 64) +#define WRMEM1_94_FLD6 GENMASK(95, 80) +#define WRMEM1_94_FLD7 GENMASK(111, 96) +#define WRMEM1_94_FLD8 GENMASK(127, 112) + +/* WRMEM1_95 register fields */ +#define WRMEM1_95_FLD1 GENMASK(15, 0) +#define WRMEM1_95_FLD2 GENMASK(31, 16) +#define WRMEM1_95_FLD3 GENMASK(47, 32) +#define WRMEM1_95_FLD4 GENMASK(63, 48) +#define WRMEM1_95_FLD5 GENMASK(79, 64) +#define WRMEM1_95_FLD6 GENMASK(95, 80) +#define WRMEM1_95_FLD7 GENMASK(111, 96) +#define WRMEM1_95_FLD8 GENMASK(127, 112) + +/* WRMEM1_96 register fields */ +#define WRMEM1_96_FLD1 GENMASK(15, 0) +#define WRMEM1_96_FLD2 GENMASK(31, 16) +#define WRMEM1_96_FLD3 GENMASK(47, 32) +#define WRMEM1_96_FLD4 GENMASK(63, 48) +#define WRMEM1_96_FLD5 GENMASK(79, 64) +#define WRMEM1_96_FLD6 GENMASK(95, 80) +#define WRMEM1_96_FLD7 GENMASK(111, 96) +#define WRMEM1_96_FLD8 GENMASK(127, 112) + +/* WRMEM1_97 register fields */ +#define WRMEM1_97_FLD1 GENMASK(15, 0) +#define WRMEM1_97_FLD2 GENMASK(31, 16) +#define WRMEM1_97_FLD3 GENMASK(47, 32) +#define WRMEM1_97_FLD4 GENMASK(63, 48) +#define WRMEM1_97_FLD5 GENMASK(79, 64) +#define WRMEM1_97_FLD6 GENMASK(95, 80) +#define WRMEM1_97_FLD7 GENMASK(111, 96) +#define WRMEM1_97_FLD8 GENMASK(127, 112) + +/* WRMEM1_98 register fields */ +#define WRMEM1_98_FLD1 GENMASK(15, 0) +#define WRMEM1_98_FLD2 GENMASK(31, 16) +#define WRMEM1_98_FLD3 GENMASK(47, 32) +#define WRMEM1_98_FLD4 GENMASK(63, 48) +#define WRMEM1_98_FLD5 GENMASK(79, 64) +#define WRMEM1_98_FLD6 GENMASK(95, 80) +#define WRMEM1_98_FLD7 GENMASK(111, 96) +#define WRMEM1_98_FLD8 GENMASK(127, 112) + +/* WRMEM1_99 register fields */ +#define WRMEM1_99_FLD1 GENMASK(15, 0) +#define WRMEM1_99_FLD2 GENMASK(31, 16) +#define WRMEM1_99_FLD3 GENMASK(47, 32) +#define WRMEM1_99_FLD4 GENMASK(63, 48) +#define WRMEM1_99_FLD5 GENMASK(79, 64) +#define WRMEM1_99_FLD6 GENMASK(95, 80) +#define WRMEM1_99_FLD7 GENMASK(111, 96) +#define WRMEM1_99_FLD8 GENMASK(127, 112) + +/* WRMEM1_100 register fields */ +#define WRMEM1_100_FLD1 GENMASK(15, 0) +#define WRMEM1_100_FLD2 GENMASK(31, 16) +#define WRMEM1_100_FLD3 GENMASK(47, 32) +#define WRMEM1_100_FLD4 GENMASK(63, 48) +#define WRMEM1_100_FLD5 GENMASK(79, 64) +#define WRMEM1_100_FLD6 GENMASK(95, 80) +#define WRMEM1_100_FLD7 GENMASK(111, 96) +#define WRMEM1_100_FLD8 GENMASK(127, 112) + +/* WRMEM1_101 register fields */ +#define WRMEM1_101_FLD1 GENMASK(15, 0) +#define WRMEM1_101_FLD2 GENMASK(31, 16) +#define WRMEM1_101_FLD3 GENMASK(47, 32) +#define WRMEM1_101_FLD4 GENMASK(63, 48) +#define WRMEM1_101_FLD5 GENMASK(79, 64) +#define WRMEM1_101_FLD6 GENMASK(95, 80) +#define WRMEM1_101_FLD7 GENMASK(111, 96) +#define WRMEM1_101_FLD8 GENMASK(127, 112) + +/* WRMEM1_102 register fields */ +#define WRMEM1_102_FLD1 GENMASK(15, 0) +#define WRMEM1_102_FLD2 GENMASK(31, 16) +#define WRMEM1_102_FLD3 GENMASK(47, 32) +#define WRMEM1_102_FLD4 GENMASK(63, 48) +#define WRMEM1_102_FLD5 GENMASK(79, 64) +#define WRMEM1_102_FLD6 GENMASK(95, 80) +#define WRMEM1_102_FLD7 GENMASK(111, 96) +#define WRMEM1_102_FLD8 GENMASK(127, 112) + +/* WRMEM1_103 register fields */ +#define WRMEM1_103_FLD1 GENMASK(15, 0) +#define WRMEM1_103_FLD2 GENMASK(31, 16) +#define WRMEM1_103_FLD3 GENMASK(47, 32) +#define WRMEM1_103_FLD4 GENMASK(63, 48) +#define WRMEM1_103_FLD5 GENMASK(79, 64) +#define WRMEM1_103_FLD6 GENMASK(95, 80) +#define WRMEM1_103_FLD7 GENMASK(111, 96) +#define WRMEM1_103_FLD8 GENMASK(127, 112) + +/* WRMEM1_104 register fields */ +#define WRMEM1_104_FLD1 GENMASK(15, 0) +#define WRMEM1_104_FLD2 GENMASK(31, 16) +#define WRMEM1_104_FLD3 GENMASK(47, 32) +#define WRMEM1_104_FLD4 GENMASK(63, 48) +#define WRMEM1_104_FLD5 GENMASK(79, 64) +#define WRMEM1_104_FLD6 GENMASK(95, 80) +#define WRMEM1_104_FLD7 GENMASK(111, 96) +#define WRMEM1_104_FLD8 GENMASK(127, 112) + +/* WRMEM1_105 register fields */ +#define WRMEM1_105_FLD1 GENMASK(15, 0) +#define WRMEM1_105_FLD2 GENMASK(31, 16) +#define WRMEM1_105_FLD3 GENMASK(47, 32) +#define WRMEM1_105_FLD4 GENMASK(63, 48) +#define WRMEM1_105_FLD5 GENMASK(79, 64) +#define WRMEM1_105_FLD6 GENMASK(95, 80) +#define WRMEM1_105_FLD7 GENMASK(111, 96) +#define WRMEM1_105_FLD8 GENMASK(127, 112) + +/* WRMEM1_106 register fields */ +#define WRMEM1_106_FLD1 GENMASK(15, 0) +#define WRMEM1_106_FLD2 GENMASK(31, 16) +#define WRMEM1_106_FLD3 GENMASK(47, 32) +#define WRMEM1_106_FLD4 GENMASK(63, 48) +#define WRMEM1_106_FLD5 GENMASK(79, 64) +#define WRMEM1_106_FLD6 GENMASK(95, 80) +#define WRMEM1_106_FLD7 GENMASK(111, 96) +#define WRMEM1_106_FLD8 GENMASK(127, 112) + +/* WRMEM1_107 register fields */ +#define WRMEM1_107_FLD1 GENMASK(15, 0) +#define WRMEM1_107_FLD2 GENMASK(31, 16) +#define WRMEM1_107_FLD3 GENMASK(47, 32) +#define WRMEM1_107_FLD4 GENMASK(63, 48) +#define WRMEM1_107_FLD5 GENMASK(79, 64) +#define WRMEM1_107_FLD6 GENMASK(95, 80) +#define WRMEM1_107_FLD7 GENMASK(111, 96) +#define WRMEM1_107_FLD8 GENMASK(127, 112) + +/* WRMEM1_108 register fields */ +#define WRMEM1_108_FLD1 GENMASK(15, 0) +#define WRMEM1_108_FLD2 GENMASK(31, 16) +#define WRMEM1_108_FLD3 GENMASK(47, 32) +#define WRMEM1_108_FLD4 GENMASK(63, 48) +#define WRMEM1_108_FLD5 GENMASK(79, 64) +#define WRMEM1_108_FLD6 GENMASK(95, 80) +#define WRMEM1_108_FLD7 GENMASK(111, 96) +#define WRMEM1_108_FLD8 GENMASK(127, 112) + +/* WRMEM1_109 register fields */ +#define WRMEM1_109_FLD1 GENMASK(15, 0) +#define WRMEM1_109_FLD2 GENMASK(31, 16) +#define WRMEM1_109_FLD3 GENMASK(47, 32) +#define WRMEM1_109_FLD4 GENMASK(63, 48) +#define WRMEM1_109_FLD5 GENMASK(79, 64) +#define WRMEM1_109_FLD6 GENMASK(95, 80) +#define WRMEM1_109_FLD7 GENMASK(111, 96) +#define WRMEM1_109_FLD8 GENMASK(127, 112) + +/* WRMEM1_110 register fields */ +#define WRMEM1_110_FLD1 GENMASK(15, 0) +#define WRMEM1_110_FLD2 GENMASK(31, 16) +#define WRMEM1_110_FLD3 GENMASK(47, 32) +#define WRMEM1_110_FLD4 GENMASK(63, 48) +#define WRMEM1_110_FLD5 GENMASK(79, 64) +#define WRMEM1_110_FLD6 GENMASK(95, 80) +#define WRMEM1_110_FLD7 GENMASK(111, 96) +#define WRMEM1_110_FLD8 GENMASK(127, 112) + +/* WRMEM1_111 register fields */ +#define WRMEM1_111_FLD1 GENMASK(15, 0) +#define WRMEM1_111_FLD2 GENMASK(31, 16) +#define WRMEM1_111_FLD3 GENMASK(47, 32) +#define WRMEM1_111_FLD4 GENMASK(63, 48) +#define WRMEM1_111_FLD5 GENMASK(79, 64) +#define WRMEM1_111_FLD6 GENMASK(95, 80) +#define WRMEM1_111_FLD7 GENMASK(111, 96) +#define WRMEM1_111_FLD8 GENMASK(127, 112) + +/* WRMEM1_112 register fields */ +#define WRMEM1_112_FLD1 GENMASK(15, 0) +#define WRMEM1_112_FLD2 GENMASK(31, 16) +#define WRMEM1_112_FLD3 GENMASK(47, 32) +#define WRMEM1_112_FLD4 GENMASK(63, 48) +#define WRMEM1_112_FLD5 GENMASK(79, 64) +#define WRMEM1_112_FLD6 GENMASK(95, 80) +#define WRMEM1_112_FLD7 GENMASK(111, 96) +#define WRMEM1_112_FLD8 GENMASK(127, 112) + +/* WRMEM1_113 register fields */ +#define WRMEM1_113_FLD1 GENMASK(15, 0) +#define WRMEM1_113_FLD2 GENMASK(31, 16) +#define WRMEM1_113_FLD3 GENMASK(47, 32) +#define WRMEM1_113_FLD4 GENMASK(63, 48) +#define WRMEM1_113_FLD5 GENMASK(79, 64) +#define WRMEM1_113_FLD6 GENMASK(95, 80) +#define WRMEM1_113_FLD7 GENMASK(111, 96) +#define WRMEM1_113_FLD8 GENMASK(127, 112) + +/* WRMEM1_114 register fields */ +#define WRMEM1_114_FLD1 GENMASK(15, 0) +#define WRMEM1_114_FLD2 GENMASK(31, 16) +#define WRMEM1_114_FLD3 GENMASK(47, 32) +#define WRMEM1_114_FLD4 GENMASK(63, 48) +#define WRMEM1_114_FLD5 GENMASK(79, 64) +#define WRMEM1_114_FLD6 GENMASK(95, 80) +#define WRMEM1_114_FLD7 GENMASK(111, 96) +#define WRMEM1_114_FLD8 GENMASK(127, 112) + +/* WRMEM1_115 register fields */ +#define WRMEM1_115_FLD1 GENMASK(15, 0) +#define WRMEM1_115_FLD2 GENMASK(31, 16) +#define WRMEM1_115_FLD3 GENMASK(47, 32) +#define WRMEM1_115_FLD4 GENMASK(63, 48) +#define WRMEM1_115_FLD5 GENMASK(79, 64) +#define WRMEM1_115_FLD6 GENMASK(95, 80) +#define WRMEM1_115_FLD7 GENMASK(111, 96) +#define WRMEM1_115_FLD8 GENMASK(127, 112) + +/* WRMEM1_116 register fields */ +#define WRMEM1_116_FLD1 GENMASK(15, 0) +#define WRMEM1_116_FLD2 GENMASK(31, 16) +#define WRMEM1_116_FLD3 GENMASK(47, 32) +#define WRMEM1_116_FLD4 GENMASK(63, 48) +#define WRMEM1_116_FLD5 GENMASK(79, 64) +#define WRMEM1_116_FLD6 GENMASK(95, 80) +#define WRMEM1_116_FLD7 GENMASK(111, 96) +#define WRMEM1_116_FLD8 GENMASK(127, 112) + +/* WRMEM1_117 register fields */ +#define WRMEM1_117_FLD1 GENMASK(15, 0) +#define WRMEM1_117_FLD2 GENMASK(31, 16) +#define WRMEM1_117_FLD3 GENMASK(47, 32) +#define WRMEM1_117_FLD4 GENMASK(63, 48) +#define WRMEM1_117_FLD5 GENMASK(79, 64) +#define WRMEM1_117_FLD6 GENMASK(95, 80) +#define WRMEM1_117_FLD7 GENMASK(111, 96) +#define WRMEM1_117_FLD8 GENMASK(127, 112) + +/* WRMEM1_118 register fields */ +#define WRMEM1_118_FLD1 GENMASK(15, 0) +#define WRMEM1_118_FLD2 GENMASK(31, 16) +#define WRMEM1_118_FLD3 GENMASK(47, 32) +#define WRMEM1_118_FLD4 GENMASK(63, 48) +#define WRMEM1_118_FLD5 GENMASK(79, 64) +#define WRMEM1_118_FLD6 GENMASK(95, 80) +#define WRMEM1_118_FLD7 GENMASK(111, 96) +#define WRMEM1_118_FLD8 GENMASK(127, 112) + +/* WRMEM1_119 register fields */ +#define WRMEM1_119_FLD1 GENMASK(15, 0) +#define WRMEM1_119_FLD2 GENMASK(31, 16) +#define WRMEM1_119_FLD3 GENMASK(47, 32) +#define WRMEM1_119_FLD4 GENMASK(63, 48) +#define WRMEM1_119_FLD5 GENMASK(79, 64) +#define WRMEM1_119_FLD6 GENMASK(95, 80) +#define WRMEM1_119_FLD7 GENMASK(111, 96) +#define WRMEM1_119_FLD8 GENMASK(127, 112) + +/* WRMEM1_120 register fields */ +#define WRMEM1_120_FLD1 GENMASK(15, 0) +#define WRMEM1_120_FLD2 GENMASK(31, 16) +#define WRMEM1_120_FLD3 GENMASK(47, 32) +#define WRMEM1_120_FLD4 GENMASK(63, 48) +#define WRMEM1_120_FLD5 GENMASK(79, 64) +#define WRMEM1_120_FLD6 GENMASK(95, 80) +#define WRMEM1_120_FLD7 GENMASK(111, 96) +#define WRMEM1_120_FLD8 GENMASK(127, 112) + +/* WRMEM1_121 register fields */ +#define WRMEM1_121_FLD1 GENMASK(15, 0) +#define WRMEM1_121_FLD2 GENMASK(31, 16) +#define WRMEM1_121_FLD3 GENMASK(47, 32) +#define WRMEM1_121_FLD4 GENMASK(63, 48) +#define WRMEM1_121_FLD5 GENMASK(79, 64) +#define WRMEM1_121_FLD6 GENMASK(95, 80) +#define WRMEM1_121_FLD7 GENMASK(111, 96) +#define WRMEM1_121_FLD8 GENMASK(127, 112) + +/* WRMEM1_122 register fields */ +#define WRMEM1_122_FLD1 GENMASK(15, 0) +#define WRMEM1_122_FLD2 GENMASK(31, 16) +#define WRMEM1_122_FLD3 GENMASK(47, 32) +#define WRMEM1_122_FLD4 GENMASK(63, 48) +#define WRMEM1_122_FLD5 GENMASK(79, 64) +#define WRMEM1_122_FLD6 GENMASK(95, 80) +#define WRMEM1_122_FLD7 GENMASK(111, 96) +#define WRMEM1_122_FLD8 GENMASK(127, 112) + +/* WRMEM1_123 register fields */ +#define WRMEM1_123_FLD1 GENMASK(15, 0) +#define WRMEM1_123_FLD2 GENMASK(31, 16) +#define WRMEM1_123_FLD3 GENMASK(47, 32) +#define WRMEM1_123_FLD4 GENMASK(63, 48) +#define WRMEM1_123_FLD5 GENMASK(79, 64) +#define WRMEM1_123_FLD6 GENMASK(95, 80) +#define WRMEM1_123_FLD7 GENMASK(111, 96) +#define WRMEM1_123_FLD8 GENMASK(127, 112) + +/* WRMEM1_124 register fields */ +#define WRMEM1_124_FLD1 GENMASK(15, 0) +#define WRMEM1_124_FLD2 GENMASK(31, 16) +#define WRMEM1_124_FLD3 GENMASK(47, 32) +#define WRMEM1_124_FLD4 GENMASK(63, 48) +#define WRMEM1_124_FLD5 GENMASK(79, 64) +#define WRMEM1_124_FLD6 GENMASK(95, 80) +#define WRMEM1_124_FLD7 GENMASK(111, 96) +#define WRMEM1_124_FLD8 GENMASK(127, 112) + +/* WRMEM1_125 register fields */ +#define WRMEM1_125_FLD1 GENMASK(15, 0) +#define WRMEM1_125_FLD2 GENMASK(31, 16) +#define WRMEM1_125_FLD3 GENMASK(47, 32) +#define WRMEM1_125_FLD4 GENMASK(63, 48) +#define WRMEM1_125_FLD5 GENMASK(79, 64) +#define WRMEM1_125_FLD6 GENMASK(95, 80) +#define WRMEM1_125_FLD7 GENMASK(111, 96) +#define WRMEM1_125_FLD8 GENMASK(127, 112) + +/* WRMEM1_126 register fields */ +#define WRMEM1_126_FLD1 GENMASK(15, 0) +#define WRMEM1_126_FLD2 GENMASK(31, 16) +#define WRMEM1_126_FLD3 GENMASK(47, 32) +#define WRMEM1_126_FLD4 GENMASK(63, 48) +#define WRMEM1_126_FLD5 GENMASK(79, 64) +#define WRMEM1_126_FLD6 GENMASK(95, 80) +#define WRMEM1_126_FLD7 GENMASK(111, 96) +#define WRMEM1_126_FLD8 GENMASK(127, 112) + +/* WRMEM1_127 register fields */ +#define WRMEM1_127_FLD1 GENMASK(15, 0) +#define WRMEM1_127_FLD2 GENMASK(31, 16) +#define WRMEM1_127_FLD3 GENMASK(47, 32) +#define WRMEM1_127_FLD4 GENMASK(63, 48) +#define WRMEM1_127_FLD5 GENMASK(79, 64) +#define WRMEM1_127_FLD6 GENMASK(95, 80) +#define WRMEM1_127_FLD7 GENMASK(111, 96) +#define WRMEM1_127_FLD8 GENMASK(127, 112) + +/* WRMEM1_128 register fields */ +#define WRMEM1_128_FLD1 GENMASK(15, 0) +#define WRMEM1_128_FLD2 GENMASK(31, 16) +#define WRMEM1_128_FLD3 GENMASK(47, 32) +#define WRMEM1_128_FLD4 GENMASK(63, 48) +#define WRMEM1_128_FLD5 GENMASK(79, 64) +#define WRMEM1_128_FLD6 GENMASK(95, 80) +#define WRMEM1_128_FLD7 GENMASK(111, 96) +#define WRMEM1_128_FLD8 GENMASK(127, 112) + +/* WRMEM1_129 register fields */ +#define WRMEM1_129_FLD1 GENMASK(15, 0) +#define WRMEM1_129_FLD2 GENMASK(31, 16) +#define WRMEM1_129_FLD3 GENMASK(47, 32) +#define WRMEM1_129_FLD4 GENMASK(63, 48) +#define WRMEM1_129_FLD5 GENMASK(79, 64) +#define WRMEM1_129_FLD6 GENMASK(95, 80) +#define WRMEM1_129_FLD7 GENMASK(111, 96) +#define WRMEM1_129_FLD8 GENMASK(127, 112) + +/* WRMEM1_130 register fields */ +#define WRMEM1_130_FLD1 GENMASK(15, 0) +#define WRMEM1_130_FLD2 GENMASK(31, 16) +#define WRMEM1_130_FLD3 GENMASK(47, 32) +#define WRMEM1_130_FLD4 GENMASK(63, 48) +#define WRMEM1_130_FLD5 GENMASK(79, 64) +#define WRMEM1_130_FLD6 GENMASK(95, 80) +#define WRMEM1_130_FLD7 GENMASK(111, 96) +#define WRMEM1_130_FLD8 GENMASK(127, 112) + +/* WRMEM1_131 register fields */ +#define WRMEM1_131_FLD1 GENMASK(15, 0) +#define WRMEM1_131_FLD2 GENMASK(31, 16) +#define WRMEM1_131_FLD3 GENMASK(47, 32) +#define WRMEM1_131_FLD4 GENMASK(63, 48) +#define WRMEM1_131_FLD5 GENMASK(79, 64) +#define WRMEM1_131_FLD6 GENMASK(95, 80) +#define WRMEM1_131_FLD7 GENMASK(111, 96) +#define WRMEM1_131_FLD8 GENMASK(127, 112) + +/* WRMEM1_132 register fields */ +#define WRMEM1_132_FLD1 GENMASK(15, 0) +#define WRMEM1_132_FLD2 GENMASK(31, 16) +#define WRMEM1_132_FLD3 GENMASK(47, 32) +#define WRMEM1_132_FLD4 GENMASK(63, 48) +#define WRMEM1_132_FLD5 GENMASK(79, 64) +#define WRMEM1_132_FLD6 GENMASK(95, 80) +#define WRMEM1_132_FLD7 GENMASK(111, 96) +#define WRMEM1_132_FLD8 GENMASK(127, 112) + +/* WRMEM1_133 register fields */ +#define WRMEM1_133_FLD1 GENMASK(15, 0) +#define WRMEM1_133_FLD2 GENMASK(31, 16) +#define WRMEM1_133_FLD3 GENMASK(47, 32) +#define WRMEM1_133_FLD4 GENMASK(63, 48) +#define WRMEM1_133_FLD5 GENMASK(79, 64) +#define WRMEM1_133_FLD6 GENMASK(95, 80) +#define WRMEM1_133_FLD7 GENMASK(111, 96) +#define WRMEM1_133_FLD8 GENMASK(127, 112) + +/* WRMEM1_134 register fields */ +#define WRMEM1_134_FLD1 GENMASK(15, 0) +#define WRMEM1_134_FLD2 GENMASK(31, 16) +#define WRMEM1_134_FLD3 GENMASK(47, 32) +#define WRMEM1_134_FLD4 GENMASK(63, 48) +#define WRMEM1_134_FLD5 GENMASK(79, 64) +#define WRMEM1_134_FLD6 GENMASK(95, 80) +#define WRMEM1_134_FLD7 GENMASK(111, 96) +#define WRMEM1_134_FLD8 GENMASK(127, 112) + +/* WRMEM1_135 register fields */ +#define WRMEM1_135_FLD1 GENMASK(15, 0) +#define WRMEM1_135_FLD2 GENMASK(31, 16) +#define WRMEM1_135_FLD3 GENMASK(47, 32) +#define WRMEM1_135_FLD4 GENMASK(63, 48) +#define WRMEM1_135_FLD5 GENMASK(79, 64) +#define WRMEM1_135_FLD6 GENMASK(95, 80) +#define WRMEM1_135_FLD7 GENMASK(111, 96) +#define WRMEM1_135_FLD8 GENMASK(127, 112) + +/* WRMEM1_136 register fields */ +#define WRMEM1_136_FLD1 GENMASK(15, 0) +#define WRMEM1_136_FLD2 GENMASK(31, 16) +#define WRMEM1_136_FLD3 GENMASK(47, 32) +#define WRMEM1_136_FLD4 GENMASK(63, 48) +#define WRMEM1_136_FLD5 GENMASK(79, 64) +#define WRMEM1_136_FLD6 GENMASK(95, 80) +#define WRMEM1_136_FLD7 GENMASK(111, 96) +#define WRMEM1_136_FLD8 GENMASK(127, 112) + +/* WRMEM1_137 register fields */ +#define WRMEM1_137_FLD1 GENMASK(15, 0) +#define WRMEM1_137_FLD2 GENMASK(31, 16) +#define WRMEM1_137_FLD3 GENMASK(47, 32) +#define WRMEM1_137_FLD4 GENMASK(63, 48) +#define WRMEM1_137_FLD5 GENMASK(79, 64) +#define WRMEM1_137_FLD6 GENMASK(95, 80) +#define WRMEM1_137_FLD7 GENMASK(111, 96) +#define WRMEM1_137_FLD8 GENMASK(127, 112) + +/* WRMEM1_138 register fields */ +#define WRMEM1_138_FLD1 GENMASK(15, 0) +#define WRMEM1_138_FLD2 GENMASK(31, 16) +#define WRMEM1_138_FLD3 GENMASK(47, 32) +#define WRMEM1_138_FLD4 GENMASK(63, 48) +#define WRMEM1_138_FLD5 GENMASK(79, 64) +#define WRMEM1_138_FLD6 GENMASK(95, 80) +#define WRMEM1_138_FLD7 GENMASK(111, 96) +#define WRMEM1_138_FLD8 GENMASK(127, 112) + +/* WRMEM1_139 register fields */ +#define WRMEM1_139_FLD1 GENMASK(15, 0) +#define WRMEM1_139_FLD2 GENMASK(31, 16) +#define WRMEM1_139_FLD3 GENMASK(47, 32) +#define WRMEM1_139_FLD4 GENMASK(63, 48) +#define WRMEM1_139_FLD5 GENMASK(79, 64) +#define WRMEM1_139_FLD6 GENMASK(95, 80) +#define WRMEM1_139_FLD7 GENMASK(111, 96) +#define WRMEM1_139_FLD8 GENMASK(127, 112) + +/* WRMEM1_140 register fields */ +#define WRMEM1_140_FLD1 GENMASK(15, 0) +#define WRMEM1_140_FLD2 GENMASK(31, 16) +#define WRMEM1_140_FLD3 GENMASK(47, 32) +#define WRMEM1_140_FLD4 GENMASK(63, 48) +#define WRMEM1_140_FLD5 GENMASK(79, 64) +#define WRMEM1_140_FLD6 GENMASK(95, 80) +#define WRMEM1_140_FLD7 GENMASK(111, 96) +#define WRMEM1_140_FLD8 GENMASK(127, 112) + +/* WRMEM1_141 register fields */ +#define WRMEM1_141_FLD1 GENMASK(15, 0) +#define WRMEM1_141_FLD2 GENMASK(31, 16) +#define WRMEM1_141_FLD3 GENMASK(47, 32) +#define WRMEM1_141_FLD4 GENMASK(63, 48) +#define WRMEM1_141_FLD5 GENMASK(79, 64) +#define WRMEM1_141_FLD6 GENMASK(95, 80) +#define WRMEM1_141_FLD7 GENMASK(111, 96) +#define WRMEM1_141_FLD8 GENMASK(127, 112) + +/* WRMEM1_142 register fields */ +#define WRMEM1_142_FLD1 GENMASK(15, 0) +#define WRMEM1_142_FLD2 GENMASK(31, 16) +#define WRMEM1_142_FLD3 GENMASK(47, 32) +#define WRMEM1_142_FLD4 GENMASK(63, 48) +#define WRMEM1_142_FLD5 GENMASK(79, 64) +#define WRMEM1_142_FLD6 GENMASK(95, 80) +#define WRMEM1_142_FLD7 GENMASK(111, 96) +#define WRMEM1_142_FLD8 GENMASK(127, 112) + +/* WRMEM1_143 register fields */ +#define WRMEM1_143_FLD1 GENMASK(15, 0) +#define WRMEM1_143_FLD2 GENMASK(31, 16) +#define WRMEM1_143_FLD3 GENMASK(47, 32) +#define WRMEM1_143_FLD4 GENMASK(63, 48) +#define WRMEM1_143_FLD5 GENMASK(79, 64) +#define WRMEM1_143_FLD6 GENMASK(95, 80) +#define WRMEM1_143_FLD7 GENMASK(111, 96) +#define WRMEM1_143_FLD8 GENMASK(127, 112) + +/* WRMEM1_144 register fields */ +#define WRMEM1_144_FLD1 GENMASK(15, 0) +#define WRMEM1_144_FLD2 GENMASK(31, 16) +#define WRMEM1_144_FLD3 GENMASK(47, 32) +#define WRMEM1_144_FLD4 GENMASK(63, 48) +#define WRMEM1_144_FLD5 GENMASK(79, 64) +#define WRMEM1_144_FLD6 GENMASK(95, 80) +#define WRMEM1_144_FLD7 GENMASK(111, 96) +#define WRMEM1_144_FLD8 GENMASK(127, 112) + +/* WRMEM1_145 register fields */ +#define WRMEM1_145_FLD1 GENMASK(15, 0) +#define WRMEM1_145_FLD2 GENMASK(31, 16) +#define WRMEM1_145_FLD3 GENMASK(47, 32) +#define WRMEM1_145_FLD4 GENMASK(63, 48) +#define WRMEM1_145_FLD5 GENMASK(79, 64) +#define WRMEM1_145_FLD6 GENMASK(95, 80) +#define WRMEM1_145_FLD7 GENMASK(111, 96) +#define WRMEM1_145_FLD8 GENMASK(127, 112) + +/* WRMEM1_146 register fields */ +#define WRMEM1_146_FLD1 GENMASK(15, 0) +#define WRMEM1_146_FLD2 GENMASK(31, 16) +#define WRMEM1_146_FLD3 GENMASK(47, 32) +#define WRMEM1_146_FLD4 GENMASK(63, 48) +#define WRMEM1_146_FLD5 GENMASK(79, 64) +#define WRMEM1_146_FLD6 GENMASK(95, 80) +#define WRMEM1_146_FLD7 GENMASK(111, 96) +#define WRMEM1_146_FLD8 GENMASK(127, 112) + +/* WRMEM1_147 register fields */ +#define WRMEM1_147_FLD1 GENMASK(15, 0) +#define WRMEM1_147_FLD2 GENMASK(31, 16) +#define WRMEM1_147_FLD3 GENMASK(47, 32) +#define WRMEM1_147_FLD4 GENMASK(63, 48) +#define WRMEM1_147_FLD5 GENMASK(79, 64) +#define WRMEM1_147_FLD6 GENMASK(95, 80) +#define WRMEM1_147_FLD7 GENMASK(111, 96) +#define WRMEM1_147_FLD8 GENMASK(127, 112) + +/* WRMEM1_148 register fields */ +#define WRMEM1_148_FLD1 GENMASK(15, 0) +#define WRMEM1_148_FLD2 GENMASK(31, 16) +#define WRMEM1_148_FLD3 GENMASK(47, 32) +#define WRMEM1_148_FLD4 GENMASK(63, 48) +#define WRMEM1_148_FLD5 GENMASK(79, 64) +#define WRMEM1_148_FLD6 GENMASK(95, 80) +#define WRMEM1_148_FLD7 GENMASK(111, 96) +#define WRMEM1_148_FLD8 GENMASK(127, 112) + +/* WRMEM1_149 register fields */ +#define WRMEM1_149_FLD1 GENMASK(15, 0) +#define WRMEM1_149_FLD2 GENMASK(31, 16) +#define WRMEM1_149_FLD3 GENMASK(47, 32) +#define WRMEM1_149_FLD4 GENMASK(63, 48) +#define WRMEM1_149_FLD5 GENMASK(79, 64) +#define WRMEM1_149_FLD6 GENMASK(95, 80) +#define WRMEM1_149_FLD7 GENMASK(111, 96) +#define WRMEM1_149_FLD8 GENMASK(127, 112) + +/* WRMEM1_150 register fields */ +#define WRMEM1_150_FLD1 GENMASK(15, 0) +#define WRMEM1_150_FLD2 GENMASK(31, 16) +#define WRMEM1_150_FLD3 GENMASK(47, 32) +#define WRMEM1_150_FLD4 GENMASK(63, 48) +#define WRMEM1_150_FLD5 GENMASK(79, 64) +#define WRMEM1_150_FLD6 GENMASK(95, 80) +#define WRMEM1_150_FLD7 GENMASK(111, 96) +#define WRMEM1_150_FLD8 GENMASK(127, 112) + +/* WRMEM1_151 register fields */ +#define WRMEM1_151_FLD1 GENMASK(15, 0) +#define WRMEM1_151_FLD2 GENMASK(31, 16) +#define WRMEM1_151_FLD3 GENMASK(47, 32) +#define WRMEM1_151_FLD4 GENMASK(63, 48) +#define WRMEM1_151_FLD5 GENMASK(79, 64) +#define WRMEM1_151_FLD6 GENMASK(95, 80) +#define WRMEM1_151_FLD7 GENMASK(111, 96) +#define WRMEM1_151_FLD8 GENMASK(127, 112) + +/* WRMEM1_152 register fields */ +#define WRMEM1_152_FLD1 GENMASK(15, 0) +#define WRMEM1_152_FLD2 GENMASK(31, 16) +#define WRMEM1_152_FLD3 GENMASK(47, 32) +#define WRMEM1_152_FLD4 GENMASK(63, 48) +#define WRMEM1_152_FLD5 GENMASK(79, 64) +#define WRMEM1_152_FLD6 GENMASK(95, 80) +#define WRMEM1_152_FLD7 GENMASK(111, 96) +#define WRMEM1_152_FLD8 GENMASK(127, 112) + +/* WRMEM1_153 register fields */ +#define WRMEM1_153_FLD1 GENMASK(15, 0) +#define WRMEM1_153_FLD2 GENMASK(31, 16) +#define WRMEM1_153_FLD3 GENMASK(47, 32) +#define WRMEM1_153_FLD4 GENMASK(63, 48) +#define WRMEM1_153_FLD5 GENMASK(79, 64) +#define WRMEM1_153_FLD6 GENMASK(95, 80) +#define WRMEM1_153_FLD7 GENMASK(111, 96) +#define WRMEM1_153_FLD8 GENMASK(127, 112) + +/* WRMEM1_154 register fields */ +#define WRMEM1_154_FLD1 GENMASK(15, 0) +#define WRMEM1_154_FLD2 GENMASK(31, 16) +#define WRMEM1_154_FLD3 GENMASK(47, 32) +#define WRMEM1_154_FLD4 GENMASK(63, 48) +#define WRMEM1_154_FLD5 GENMASK(79, 64) +#define WRMEM1_154_FLD6 GENMASK(95, 80) +#define WRMEM1_154_FLD7 GENMASK(111, 96) +#define WRMEM1_154_FLD8 GENMASK(127, 112) + +/* WRMEM1_155 register fields */ +#define WRMEM1_155_FLD1 GENMASK(15, 0) +#define WRMEM1_155_FLD2 GENMASK(31, 16) +#define WRMEM1_155_FLD3 GENMASK(47, 32) +#define WRMEM1_155_FLD4 GENMASK(63, 48) +#define WRMEM1_155_FLD5 GENMASK(79, 64) +#define WRMEM1_155_FLD6 GENMASK(95, 80) +#define WRMEM1_155_FLD7 GENMASK(111, 96) +#define WRMEM1_155_FLD8 GENMASK(127, 112) + +/* WRMEM1_156 register fields */ +#define WRMEM1_156_FLD1 GENMASK(15, 0) +#define WRMEM1_156_FLD2 GENMASK(31, 16) +#define WRMEM1_156_FLD3 GENMASK(47, 32) +#define WRMEM1_156_FLD4 GENMASK(63, 48) +#define WRMEM1_156_FLD5 GENMASK(79, 64) +#define WRMEM1_156_FLD6 GENMASK(95, 80) +#define WRMEM1_156_FLD7 GENMASK(111, 96) +#define WRMEM1_156_FLD8 GENMASK(127, 112) + +/* WRMEM1_157 register fields */ +#define WRMEM1_157_FLD1 GENMASK(15, 0) +#define WRMEM1_157_FLD2 GENMASK(31, 16) +#define WRMEM1_157_FLD3 GENMASK(47, 32) +#define WRMEM1_157_FLD4 GENMASK(63, 48) +#define WRMEM1_157_FLD5 GENMASK(79, 64) +#define WRMEM1_157_FLD6 GENMASK(95, 80) +#define WRMEM1_157_FLD7 GENMASK(111, 96) +#define WRMEM1_157_FLD8 GENMASK(127, 112) + +/* WRMEM1_158 register fields */ +#define WRMEM1_158_FLD1 GENMASK(15, 0) +#define WRMEM1_158_FLD2 GENMASK(31, 16) +#define WRMEM1_158_FLD3 GENMASK(47, 32) +#define WRMEM1_158_FLD4 GENMASK(63, 48) +#define WRMEM1_158_FLD5 GENMASK(79, 64) +#define WRMEM1_158_FLD6 GENMASK(95, 80) +#define WRMEM1_158_FLD7 GENMASK(111, 96) +#define WRMEM1_158_FLD8 GENMASK(127, 112) + +/* WRMEM1_159 register fields */ +#define WRMEM1_159_FLD1 GENMASK(15, 0) +#define WRMEM1_159_FLD2 GENMASK(31, 16) +#define WRMEM1_159_FLD3 GENMASK(47, 32) +#define WRMEM1_159_FLD4 GENMASK(63, 48) +#define WRMEM1_159_FLD5 GENMASK(79, 64) +#define WRMEM1_159_FLD6 GENMASK(95, 80) +#define WRMEM1_159_FLD7 GENMASK(111, 96) +#define WRMEM1_159_FLD8 GENMASK(127, 112) + +/* WRMEM1_160 register fields */ +#define WRMEM1_160_FLD1 GENMASK(15, 0) +#define WRMEM1_160_FLD2 GENMASK(31, 16) +#define WRMEM1_160_FLD3 GENMASK(47, 32) +#define WRMEM1_160_FLD4 GENMASK(63, 48) +#define WRMEM1_160_FLD5 GENMASK(79, 64) +#define WRMEM1_160_FLD6 GENMASK(95, 80) +#define WRMEM1_160_FLD7 GENMASK(111, 96) +#define WRMEM1_160_FLD8 GENMASK(127, 112) + +/* WRMEM1_161 register fields */ +#define WRMEM1_161_FLD1 GENMASK(15, 0) +#define WRMEM1_161_FLD2 GENMASK(31, 16) +#define WRMEM1_161_FLD3 GENMASK(47, 32) +#define WRMEM1_161_FLD4 GENMASK(63, 48) +#define WRMEM1_161_FLD5 GENMASK(79, 64) +#define WRMEM1_161_FLD6 GENMASK(95, 80) +#define WRMEM1_161_FLD7 GENMASK(111, 96) +#define WRMEM1_161_FLD8 GENMASK(127, 112) + +/* WRMEM1_162 register fields */ +#define WRMEM1_162_FLD1 GENMASK(15, 0) +#define WRMEM1_162_FLD2 GENMASK(31, 16) +#define WRMEM1_162_FLD3 GENMASK(47, 32) +#define WRMEM1_162_FLD4 GENMASK(63, 48) +#define WRMEM1_162_FLD5 GENMASK(79, 64) +#define WRMEM1_162_FLD6 GENMASK(95, 80) +#define WRMEM1_162_FLD7 GENMASK(111, 96) +#define WRMEM1_162_FLD8 GENMASK(127, 112) + +/* WRMEM1_163 register fields */ +#define WRMEM1_163_FLD1 GENMASK(15, 0) +#define WRMEM1_163_FLD2 GENMASK(31, 16) +#define WRMEM1_163_FLD3 GENMASK(47, 32) +#define WRMEM1_163_FLD4 GENMASK(63, 48) +#define WRMEM1_163_FLD5 GENMASK(79, 64) +#define WRMEM1_163_FLD6 GENMASK(95, 80) +#define WRMEM1_163_FLD7 GENMASK(111, 96) +#define WRMEM1_163_FLD8 GENMASK(127, 112) + +/* WRMEM1_164 register fields */ +#define WRMEM1_164_FLD1 GENMASK(15, 0) +#define WRMEM1_164_FLD2 GENMASK(31, 16) +#define WRMEM1_164_FLD3 GENMASK(47, 32) +#define WRMEM1_164_FLD4 GENMASK(63, 48) +#define WRMEM1_164_FLD5 GENMASK(79, 64) +#define WRMEM1_164_FLD6 GENMASK(95, 80) +#define WRMEM1_164_FLD7 GENMASK(111, 96) +#define WRMEM1_164_FLD8 GENMASK(127, 112) + +/* WRMEM1_165 register fields */ +#define WRMEM1_165_FLD1 GENMASK(15, 0) +#define WRMEM1_165_FLD2 GENMASK(31, 16) +#define WRMEM1_165_FLD3 GENMASK(47, 32) +#define WRMEM1_165_FLD4 GENMASK(63, 48) +#define WRMEM1_165_FLD5 GENMASK(79, 64) +#define WRMEM1_165_FLD6 GENMASK(95, 80) +#define WRMEM1_165_FLD7 GENMASK(111, 96) +#define WRMEM1_165_FLD8 GENMASK(127, 112) + +/* WRMEM1_166 register fields */ +#define WRMEM1_166_FLD1 GENMASK(15, 0) +#define WRMEM1_166_FLD2 GENMASK(31, 16) +#define WRMEM1_166_FLD3 GENMASK(47, 32) +#define WRMEM1_166_FLD4 GENMASK(63, 48) +#define WRMEM1_166_FLD5 GENMASK(79, 64) +#define WRMEM1_166_FLD6 GENMASK(95, 80) +#define WRMEM1_166_FLD7 GENMASK(111, 96) +#define WRMEM1_166_FLD8 GENMASK(127, 112) + +/* WRMEM1_167 register fields */ +#define WRMEM1_167_FLD1 GENMASK(15, 0) +#define WRMEM1_167_FLD2 GENMASK(31, 16) +#define WRMEM1_167_FLD3 GENMASK(47, 32) +#define WRMEM1_167_FLD4 GENMASK(63, 48) +#define WRMEM1_167_FLD5 GENMASK(79, 64) +#define WRMEM1_167_FLD6 GENMASK(95, 80) +#define WRMEM1_167_FLD7 GENMASK(111, 96) +#define WRMEM1_167_FLD8 GENMASK(127, 112) + +/* WRMEM1_168 register fields */ +#define WRMEM1_168_FLD1 GENMASK(15, 0) +#define WRMEM1_168_FLD2 GENMASK(31, 16) +#define WRMEM1_168_FLD3 GENMASK(47, 32) +#define WRMEM1_168_FLD4 GENMASK(63, 48) +#define WRMEM1_168_FLD5 GENMASK(79, 64) +#define WRMEM1_168_FLD6 GENMASK(95, 80) +#define WRMEM1_168_FLD7 GENMASK(111, 96) +#define WRMEM1_168_FLD8 GENMASK(127, 112) + +/* WRMEM1_169 register fields */ +#define WRMEM1_169_FLD1 GENMASK(15, 0) +#define WRMEM1_169_FLD2 GENMASK(31, 16) +#define WRMEM1_169_FLD3 GENMASK(47, 32) +#define WRMEM1_169_FLD4 GENMASK(63, 48) +#define WRMEM1_169_FLD5 GENMASK(79, 64) +#define WRMEM1_169_FLD6 GENMASK(95, 80) +#define WRMEM1_169_FLD7 GENMASK(111, 96) +#define WRMEM1_169_FLD8 GENMASK(127, 112) + +/* WRMEM1_170 register fields */ +#define WRMEM1_170_FLD1 GENMASK(15, 0) +#define WRMEM1_170_FLD2 GENMASK(31, 16) +#define WRMEM1_170_FLD3 GENMASK(47, 32) +#define WRMEM1_170_FLD4 GENMASK(63, 48) +#define WRMEM1_170_FLD5 GENMASK(79, 64) +#define WRMEM1_170_FLD6 GENMASK(95, 80) +#define WRMEM1_170_FLD7 GENMASK(111, 96) +#define WRMEM1_170_FLD8 GENMASK(127, 112) + +/* WRMEM1_171 register fields */ +#define WRMEM1_171_FLD1 GENMASK(15, 0) +#define WRMEM1_171_FLD2 GENMASK(31, 16) +#define WRMEM1_171_FLD3 GENMASK(47, 32) +#define WRMEM1_171_FLD4 GENMASK(63, 48) +#define WRMEM1_171_FLD5 GENMASK(79, 64) +#define WRMEM1_171_FLD6 GENMASK(95, 80) +#define WRMEM1_171_FLD7 GENMASK(111, 96) +#define WRMEM1_171_FLD8 GENMASK(127, 112) + +/* WRMEM1_172 register fields */ +#define WRMEM1_172_FLD1 GENMASK(15, 0) +#define WRMEM1_172_FLD2 GENMASK(31, 16) +#define WRMEM1_172_FLD3 GENMASK(47, 32) +#define WRMEM1_172_FLD4 GENMASK(63, 48) +#define WRMEM1_172_FLD5 GENMASK(79, 64) +#define WRMEM1_172_FLD6 GENMASK(95, 80) +#define WRMEM1_172_FLD7 GENMASK(111, 96) +#define WRMEM1_172_FLD8 GENMASK(127, 112) + +/* WRMEM1_173 register fields */ +#define WRMEM1_173_FLD1 GENMASK(15, 0) +#define WRMEM1_173_FLD2 GENMASK(31, 16) +#define WRMEM1_173_FLD3 GENMASK(47, 32) +#define WRMEM1_173_FLD4 GENMASK(63, 48) +#define WRMEM1_173_FLD5 GENMASK(79, 64) +#define WRMEM1_173_FLD6 GENMASK(95, 80) +#define WRMEM1_173_FLD7 GENMASK(111, 96) +#define WRMEM1_173_FLD8 GENMASK(127, 112) + +/* WRMEM1_174 register fields */ +#define WRMEM1_174_FLD1 GENMASK(15, 0) +#define WRMEM1_174_FLD2 GENMASK(31, 16) +#define WRMEM1_174_FLD3 GENMASK(47, 32) +#define WRMEM1_174_FLD4 GENMASK(63, 48) +#define WRMEM1_174_FLD5 GENMASK(79, 64) +#define WRMEM1_174_FLD6 GENMASK(95, 80) +#define WRMEM1_174_FLD7 GENMASK(111, 96) +#define WRMEM1_174_FLD8 GENMASK(127, 112) + +/* WRMEM1_175 register fields */ +#define WRMEM1_175_FLD1 GENMASK(15, 0) +#define WRMEM1_175_FLD2 GENMASK(31, 16) +#define WRMEM1_175_FLD3 GENMASK(47, 32) +#define WRMEM1_175_FLD4 GENMASK(63, 48) +#define WRMEM1_175_FLD5 GENMASK(79, 64) +#define WRMEM1_175_FLD6 GENMASK(95, 80) +#define WRMEM1_175_FLD7 GENMASK(111, 96) +#define WRMEM1_175_FLD8 GENMASK(127, 112) + +/* WRMEM1_176 register fields */ +#define WRMEM1_176_FLD1 GENMASK(15, 0) +#define WRMEM1_176_FLD2 GENMASK(31, 16) +#define WRMEM1_176_FLD3 GENMASK(47, 32) +#define WRMEM1_176_FLD4 GENMASK(63, 48) +#define WRMEM1_176_FLD5 GENMASK(79, 64) +#define WRMEM1_176_FLD6 GENMASK(95, 80) +#define WRMEM1_176_FLD7 GENMASK(111, 96) +#define WRMEM1_176_FLD8 GENMASK(127, 112) + +/* WRMEM1_177 register fields */ +#define WRMEM1_177_FLD1 GENMASK(15, 0) +#define WRMEM1_177_FLD2 GENMASK(31, 16) +#define WRMEM1_177_FLD3 GENMASK(47, 32) +#define WRMEM1_177_FLD4 GENMASK(63, 48) +#define WRMEM1_177_FLD5 GENMASK(79, 64) +#define WRMEM1_177_FLD6 GENMASK(95, 80) +#define WRMEM1_177_FLD7 GENMASK(111, 96) +#define WRMEM1_177_FLD8 GENMASK(127, 112) + +/* WRMEM1_178 register fields */ +#define WRMEM1_178_FLD1 GENMASK(15, 0) +#define WRMEM1_178_FLD2 GENMASK(31, 16) +#define WRMEM1_178_FLD3 GENMASK(47, 32) +#define WRMEM1_178_FLD4 GENMASK(63, 48) +#define WRMEM1_178_FLD5 GENMASK(79, 64) +#define WRMEM1_178_FLD6 GENMASK(95, 80) +#define WRMEM1_178_FLD7 GENMASK(111, 96) +#define WRMEM1_178_FLD8 GENMASK(127, 112) + +/* WRMEM1_179 register fields */ +#define WRMEM1_179_FLD1 GENMASK(15, 0) +#define WRMEM1_179_FLD2 GENMASK(31, 16) +#define WRMEM1_179_FLD3 GENMASK(47, 32) +#define WRMEM1_179_FLD4 GENMASK(63, 48) +#define WRMEM1_179_FLD5 GENMASK(79, 64) +#define WRMEM1_179_FLD6 GENMASK(95, 80) +#define WRMEM1_179_FLD7 GENMASK(111, 96) +#define WRMEM1_179_FLD8 GENMASK(127, 112) + +/* WRMEM1_180 register fields */ +#define WRMEM1_180_FLD1 GENMASK(15, 0) +#define WRMEM1_180_FLD2 GENMASK(31, 16) +#define WRMEM1_180_FLD3 GENMASK(47, 32) +#define WRMEM1_180_FLD4 GENMASK(63, 48) +#define WRMEM1_180_FLD5 GENMASK(79, 64) +#define WRMEM1_180_FLD6 GENMASK(95, 80) +#define WRMEM1_180_FLD7 GENMASK(111, 96) +#define WRMEM1_180_FLD8 GENMASK(127, 112) + +/* WRMEM1_181 register fields */ +#define WRMEM1_181_FLD1 GENMASK(15, 0) +#define WRMEM1_181_FLD2 GENMASK(31, 16) +#define WRMEM1_181_FLD3 GENMASK(47, 32) +#define WRMEM1_181_FLD4 GENMASK(63, 48) +#define WRMEM1_181_FLD5 GENMASK(79, 64) +#define WRMEM1_181_FLD6 GENMASK(95, 80) +#define WRMEM1_181_FLD7 GENMASK(111, 96) +#define WRMEM1_181_FLD8 GENMASK(127, 112) + +/* WRMEM1_182 register fields */ +#define WRMEM1_182_FLD1 GENMASK(15, 0) +#define WRMEM1_182_FLD2 GENMASK(31, 16) +#define WRMEM1_182_FLD3 GENMASK(47, 32) +#define WRMEM1_182_FLD4 GENMASK(63, 48) +#define WRMEM1_182_FLD5 GENMASK(79, 64) +#define WRMEM1_182_FLD6 GENMASK(95, 80) +#define WRMEM1_182_FLD7 GENMASK(111, 96) +#define WRMEM1_182_FLD8 GENMASK(127, 112) + +/* WRMEM1_183 register fields */ +#define WRMEM1_183_FLD1 GENMASK(15, 0) +#define WRMEM1_183_FLD2 GENMASK(31, 16) +#define WRMEM1_183_FLD3 GENMASK(47, 32) +#define WRMEM1_183_FLD4 GENMASK(63, 48) +#define WRMEM1_183_FLD5 GENMASK(79, 64) +#define WRMEM1_183_FLD6 GENMASK(95, 80) +#define WRMEM1_183_FLD7 GENMASK(111, 96) +#define WRMEM1_183_FLD8 GENMASK(127, 112) + +/* WRMEM1_184 register fields */ +#define WRMEM1_184_FLD1 GENMASK(15, 0) +#define WRMEM1_184_FLD2 GENMASK(31, 16) +#define WRMEM1_184_FLD3 GENMASK(47, 32) +#define WRMEM1_184_FLD4 GENMASK(63, 48) +#define WRMEM1_184_FLD5 GENMASK(79, 64) +#define WRMEM1_184_FLD6 GENMASK(95, 80) +#define WRMEM1_184_FLD7 GENMASK(111, 96) +#define WRMEM1_184_FLD8 GENMASK(127, 112) + +/* WRMEM1_185 register fields */ +#define WRMEM1_185_FLD1 GENMASK(15, 0) +#define WRMEM1_185_FLD2 GENMASK(31, 16) +#define WRMEM1_185_FLD3 GENMASK(47, 32) +#define WRMEM1_185_FLD4 GENMASK(63, 48) +#define WRMEM1_185_FLD5 GENMASK(79, 64) +#define WRMEM1_185_FLD6 GENMASK(95, 80) +#define WRMEM1_185_FLD7 GENMASK(111, 96) +#define WRMEM1_185_FLD8 GENMASK(127, 112) + +/* WRMEM1_186 register fields */ +#define WRMEM1_186_FLD1 GENMASK(15, 0) +#define WRMEM1_186_FLD2 GENMASK(31, 16) +#define WRMEM1_186_FLD3 GENMASK(47, 32) +#define WRMEM1_186_FLD4 GENMASK(63, 48) +#define WRMEM1_186_FLD5 GENMASK(79, 64) +#define WRMEM1_186_FLD6 GENMASK(95, 80) +#define WRMEM1_186_FLD7 GENMASK(111, 96) +#define WRMEM1_186_FLD8 GENMASK(127, 112) + +/* WRMEM1_187 register fields */ +#define WRMEM1_187_FLD1 GENMASK(15, 0) +#define WRMEM1_187_FLD2 GENMASK(31, 16) +#define WRMEM1_187_FLD3 GENMASK(47, 32) +#define WRMEM1_187_FLD4 GENMASK(63, 48) +#define WRMEM1_187_FLD5 GENMASK(79, 64) +#define WRMEM1_187_FLD6 GENMASK(95, 80) +#define WRMEM1_187_FLD7 GENMASK(111, 96) +#define WRMEM1_187_FLD8 GENMASK(127, 112) + +/* WRMEM1_188 register fields */ +#define WRMEM1_188_FLD1 GENMASK(15, 0) +#define WRMEM1_188_FLD2 GENMASK(31, 16) +#define WRMEM1_188_FLD3 GENMASK(47, 32) +#define WRMEM1_188_FLD4 GENMASK(63, 48) +#define WRMEM1_188_FLD5 GENMASK(79, 64) +#define WRMEM1_188_FLD6 GENMASK(95, 80) +#define WRMEM1_188_FLD7 GENMASK(111, 96) +#define WRMEM1_188_FLD8 GENMASK(127, 112) + +/* WRMEM1_189 register fields */ +#define WRMEM1_189_FLD1 GENMASK(15, 0) +#define WRMEM1_189_FLD2 GENMASK(31, 16) +#define WRMEM1_189_FLD3 GENMASK(47, 32) +#define WRMEM1_189_FLD4 GENMASK(63, 48) +#define WRMEM1_189_FLD5 GENMASK(79, 64) +#define WRMEM1_189_FLD6 GENMASK(95, 80) +#define WRMEM1_189_FLD7 GENMASK(111, 96) +#define WRMEM1_189_FLD8 GENMASK(127, 112) + +/* WRMEM1_190 register fields */ +#define WRMEM1_190_FLD1 GENMASK(15, 0) +#define WRMEM1_190_FLD2 GENMASK(31, 16) +#define WRMEM1_190_FLD3 GENMASK(47, 32) +#define WRMEM1_190_FLD4 GENMASK(63, 48) +#define WRMEM1_190_FLD5 GENMASK(79, 64) +#define WRMEM1_190_FLD6 GENMASK(95, 80) +#define WRMEM1_190_FLD7 GENMASK(111, 96) +#define WRMEM1_190_FLD8 GENMASK(127, 112) + +/* WRMEM1_191 register fields */ +#define WRMEM1_191_FLD1 GENMASK(15, 0) +#define WRMEM1_191_FLD2 GENMASK(31, 16) +#define WRMEM1_191_FLD3 GENMASK(47, 32) +#define WRMEM1_191_FLD4 GENMASK(63, 48) +#define WRMEM1_191_FLD5 GENMASK(79, 64) +#define WRMEM1_191_FLD6 GENMASK(95, 80) +#define WRMEM1_191_FLD7 GENMASK(111, 96) +#define WRMEM1_191_FLD8 GENMASK(127, 112) + +/* WRMEM1_192 register fields */ +#define WRMEM1_192_FLD1 GENMASK(15, 0) +#define WRMEM1_192_FLD2 GENMASK(31, 16) +#define WRMEM1_192_FLD3 GENMASK(47, 32) +#define WRMEM1_192_FLD4 GENMASK(63, 48) +#define WRMEM1_192_FLD5 GENMASK(79, 64) +#define WRMEM1_192_FLD6 GENMASK(95, 80) +#define WRMEM1_192_FLD7 GENMASK(111, 96) +#define WRMEM1_192_FLD8 GENMASK(127, 112) + +/* WRMEM1_193 register fields */ +#define WRMEM1_193_FLD1 GENMASK(15, 0) +#define WRMEM1_193_FLD2 GENMASK(31, 16) +#define WRMEM1_193_FLD3 GENMASK(47, 32) +#define WRMEM1_193_FLD4 GENMASK(63, 48) +#define WRMEM1_193_FLD5 GENMASK(79, 64) +#define WRMEM1_193_FLD6 GENMASK(95, 80) +#define WRMEM1_193_FLD7 GENMASK(111, 96) +#define WRMEM1_193_FLD8 GENMASK(127, 112) + +/* WRMEM1_194 register fields */ +#define WRMEM1_194_FLD1 GENMASK(15, 0) +#define WRMEM1_194_FLD2 GENMASK(31, 16) +#define WRMEM1_194_FLD3 GENMASK(47, 32) +#define WRMEM1_194_FLD4 GENMASK(63, 48) +#define WRMEM1_194_FLD5 GENMASK(79, 64) +#define WRMEM1_194_FLD6 GENMASK(95, 80) +#define WRMEM1_194_FLD7 GENMASK(111, 96) +#define WRMEM1_194_FLD8 GENMASK(127, 112) + +/* WRMEM1_195 register fields */ +#define WRMEM1_195_FLD1 GENMASK(15, 0) +#define WRMEM1_195_FLD2 GENMASK(31, 16) +#define WRMEM1_195_FLD3 GENMASK(47, 32) +#define WRMEM1_195_FLD4 GENMASK(63, 48) +#define WRMEM1_195_FLD5 GENMASK(79, 64) +#define WRMEM1_195_FLD6 GENMASK(95, 80) +#define WRMEM1_195_FLD7 GENMASK(111, 96) +#define WRMEM1_195_FLD8 GENMASK(127, 112) + +/* WRMEM1_196 register fields */ +#define WRMEM1_196_FLD1 GENMASK(15, 0) +#define WRMEM1_196_FLD2 GENMASK(31, 16) +#define WRMEM1_196_FLD3 GENMASK(47, 32) +#define WRMEM1_196_FLD4 GENMASK(63, 48) +#define WRMEM1_196_FLD5 GENMASK(79, 64) +#define WRMEM1_196_FLD6 GENMASK(95, 80) +#define WRMEM1_196_FLD7 GENMASK(111, 96) +#define WRMEM1_196_FLD8 GENMASK(127, 112) + +/* WRMEM1_197 register fields */ +#define WRMEM1_197_FLD1 GENMASK(15, 0) +#define WRMEM1_197_FLD2 GENMASK(31, 16) +#define WRMEM1_197_FLD3 GENMASK(47, 32) +#define WRMEM1_197_FLD4 GENMASK(63, 48) +#define WRMEM1_197_FLD5 GENMASK(79, 64) +#define WRMEM1_197_FLD6 GENMASK(95, 80) +#define WRMEM1_197_FLD7 GENMASK(111, 96) +#define WRMEM1_197_FLD8 GENMASK(127, 112) + +/* WRMEM1_198 register fields */ +#define WRMEM1_198_FLD1 GENMASK(15, 0) +#define WRMEM1_198_FLD2 GENMASK(31, 16) +#define WRMEM1_198_FLD3 GENMASK(47, 32) +#define WRMEM1_198_FLD4 GENMASK(63, 48) +#define WRMEM1_198_FLD5 GENMASK(79, 64) +#define WRMEM1_198_FLD6 GENMASK(95, 80) +#define WRMEM1_198_FLD7 GENMASK(111, 96) +#define WRMEM1_198_FLD8 GENMASK(127, 112) + +/* WRMEM1_199 register fields */ +#define WRMEM1_199_FLD1 GENMASK(15, 0) +#define WRMEM1_199_FLD2 GENMASK(31, 16) +#define WRMEM1_199_FLD3 GENMASK(47, 32) +#define WRMEM1_199_FLD4 GENMASK(63, 48) +#define WRMEM1_199_FLD5 GENMASK(79, 64) +#define WRMEM1_199_FLD6 GENMASK(95, 80) +#define WRMEM1_199_FLD7 GENMASK(111, 96) +#define WRMEM1_199_FLD8 GENMASK(127, 112) + +/* WRMEM1_200 register fields */ +#define WRMEM1_200_FLD1 GENMASK(15, 0) +#define WRMEM1_200_FLD2 GENMASK(31, 16) +#define WRMEM1_200_FLD3 GENMASK(47, 32) +#define WRMEM1_200_FLD4 GENMASK(63, 48) +#define WRMEM1_200_FLD5 GENMASK(79, 64) +#define WRMEM1_200_FLD6 GENMASK(95, 80) +#define WRMEM1_200_FLD7 GENMASK(111, 96) +#define WRMEM1_200_FLD8 GENMASK(127, 112) + +/* WRMEM1_201 register fields */ +#define WRMEM1_201_FLD1 GENMASK(15, 0) +#define WRMEM1_201_FLD2 GENMASK(31, 16) +#define WRMEM1_201_FLD3 GENMASK(47, 32) +#define WRMEM1_201_FLD4 GENMASK(63, 48) +#define WRMEM1_201_FLD5 GENMASK(79, 64) +#define WRMEM1_201_FLD6 GENMASK(95, 80) +#define WRMEM1_201_FLD7 GENMASK(111, 96) +#define WRMEM1_201_FLD8 GENMASK(127, 112) + +/* WRMEM1_202 register fields */ +#define WRMEM1_202_FLD1 GENMASK(15, 0) +#define WRMEM1_202_FLD2 GENMASK(31, 16) +#define WRMEM1_202_FLD3 GENMASK(47, 32) +#define WRMEM1_202_FLD4 GENMASK(63, 48) +#define WRMEM1_202_FLD5 GENMASK(79, 64) +#define WRMEM1_202_FLD6 GENMASK(95, 80) +#define WRMEM1_202_FLD7 GENMASK(111, 96) +#define WRMEM1_202_FLD8 GENMASK(127, 112) + +/* WRMEM1_203 register fields */ +#define WRMEM1_203_FLD1 GENMASK(15, 0) +#define WRMEM1_203_FLD2 GENMASK(31, 16) +#define WRMEM1_203_FLD3 GENMASK(47, 32) +#define WRMEM1_203_FLD4 GENMASK(63, 48) +#define WRMEM1_203_FLD5 GENMASK(79, 64) +#define WRMEM1_203_FLD6 GENMASK(95, 80) +#define WRMEM1_203_FLD7 GENMASK(111, 96) +#define WRMEM1_203_FLD8 GENMASK(127, 112) + +/* WRMEM1_204 register fields */ +#define WRMEM1_204_FLD1 GENMASK(15, 0) +#define WRMEM1_204_FLD2 GENMASK(31, 16) +#define WRMEM1_204_FLD3 GENMASK(47, 32) +#define WRMEM1_204_FLD4 GENMASK(63, 48) +#define WRMEM1_204_FLD5 GENMASK(79, 64) +#define WRMEM1_204_FLD6 GENMASK(95, 80) +#define WRMEM1_204_FLD7 GENMASK(111, 96) +#define WRMEM1_204_FLD8 GENMASK(127, 112) + +/* WRMEM1_205 register fields */ +#define WRMEM1_205_FLD1 GENMASK(15, 0) +#define WRMEM1_205_FLD2 GENMASK(31, 16) +#define WRMEM1_205_FLD3 GENMASK(47, 32) +#define WRMEM1_205_FLD4 GENMASK(63, 48) +#define WRMEM1_205_FLD5 GENMASK(79, 64) +#define WRMEM1_205_FLD6 GENMASK(95, 80) +#define WRMEM1_205_FLD7 GENMASK(111, 96) +#define WRMEM1_205_FLD8 GENMASK(127, 112) + +/* WRMEM1_206 register fields */ +#define WRMEM1_206_FLD1 GENMASK(15, 0) +#define WRMEM1_206_FLD2 GENMASK(31, 16) +#define WRMEM1_206_FLD3 GENMASK(47, 32) +#define WRMEM1_206_FLD4 GENMASK(63, 48) +#define WRMEM1_206_FLD5 GENMASK(79, 64) +#define WRMEM1_206_FLD6 GENMASK(95, 80) +#define WRMEM1_206_FLD7 GENMASK(111, 96) +#define WRMEM1_206_FLD8 GENMASK(127, 112) + +/* WRMEM1_207 register fields */ +#define WRMEM1_207_FLD1 GENMASK(15, 0) +#define WRMEM1_207_FLD2 GENMASK(31, 16) +#define WRMEM1_207_FLD3 GENMASK(47, 32) +#define WRMEM1_207_FLD4 GENMASK(63, 48) +#define WRMEM1_207_FLD5 GENMASK(79, 64) +#define WRMEM1_207_FLD6 GENMASK(95, 80) +#define WRMEM1_207_FLD7 GENMASK(111, 96) +#define WRMEM1_207_FLD8 GENMASK(127, 112) + +/* WRMEM1_208 register fields */ +#define WRMEM1_208_FLD1 GENMASK(15, 0) +#define WRMEM1_208_FLD2 GENMASK(31, 16) +#define WRMEM1_208_FLD3 GENMASK(47, 32) +#define WRMEM1_208_FLD4 GENMASK(63, 48) +#define WRMEM1_208_FLD5 GENMASK(79, 64) +#define WRMEM1_208_FLD6 GENMASK(95, 80) +#define WRMEM1_208_FLD7 GENMASK(111, 96) +#define WRMEM1_208_FLD8 GENMASK(127, 112) + +/* WRMEM1_209 register fields */ +#define WRMEM1_209_FLD1 GENMASK(15, 0) +#define WRMEM1_209_FLD2 GENMASK(31, 16) +#define WRMEM1_209_FLD3 GENMASK(47, 32) +#define WRMEM1_209_FLD4 GENMASK(63, 48) +#define WRMEM1_209_FLD5 GENMASK(79, 64) +#define WRMEM1_209_FLD6 GENMASK(95, 80) +#define WRMEM1_209_FLD7 GENMASK(111, 96) +#define WRMEM1_209_FLD8 GENMASK(127, 112) + +/* WRMEM1_210 register fields */ +#define WRMEM1_210_FLD1 GENMASK(15, 0) +#define WRMEM1_210_FLD2 GENMASK(31, 16) +#define WRMEM1_210_FLD3 GENMASK(47, 32) +#define WRMEM1_210_FLD4 GENMASK(63, 48) +#define WRMEM1_210_FLD5 GENMASK(79, 64) +#define WRMEM1_210_FLD6 GENMASK(95, 80) +#define WRMEM1_210_FLD7 GENMASK(111, 96) +#define WRMEM1_210_FLD8 GENMASK(127, 112) + +/* WRMEM1_211 register fields */ +#define WRMEM1_211_FLD1 GENMASK(15, 0) +#define WRMEM1_211_FLD2 GENMASK(31, 16) +#define WRMEM1_211_FLD3 GENMASK(47, 32) +#define WRMEM1_211_FLD4 GENMASK(63, 48) +#define WRMEM1_211_FLD5 GENMASK(79, 64) +#define WRMEM1_211_FLD6 GENMASK(95, 80) +#define WRMEM1_211_FLD7 GENMASK(111, 96) +#define WRMEM1_211_FLD8 GENMASK(127, 112) + +/* WRMEM1_212 register fields */ +#define WRMEM1_212_FLD1 GENMASK(15, 0) +#define WRMEM1_212_FLD2 GENMASK(31, 16) +#define WRMEM1_212_FLD3 GENMASK(47, 32) +#define WRMEM1_212_FLD4 GENMASK(63, 48) +#define WRMEM1_212_FLD5 GENMASK(79, 64) +#define WRMEM1_212_FLD6 GENMASK(95, 80) +#define WRMEM1_212_FLD7 GENMASK(111, 96) +#define WRMEM1_212_FLD8 GENMASK(127, 112) + +/* WRMEM1_213 register fields */ +#define WRMEM1_213_FLD1 GENMASK(15, 0) +#define WRMEM1_213_FLD2 GENMASK(31, 16) +#define WRMEM1_213_FLD3 GENMASK(47, 32) +#define WRMEM1_213_FLD4 GENMASK(63, 48) +#define WRMEM1_213_FLD5 GENMASK(79, 64) +#define WRMEM1_213_FLD6 GENMASK(95, 80) +#define WRMEM1_213_FLD7 GENMASK(111, 96) +#define WRMEM1_213_FLD8 GENMASK(127, 112) + +/* WRMEM1_214 register fields */ +#define WRMEM1_214_FLD1 GENMASK(15, 0) +#define WRMEM1_214_FLD2 GENMASK(31, 16) +#define WRMEM1_214_FLD3 GENMASK(47, 32) +#define WRMEM1_214_FLD4 GENMASK(63, 48) +#define WRMEM1_214_FLD5 GENMASK(79, 64) +#define WRMEM1_214_FLD6 GENMASK(95, 80) +#define WRMEM1_214_FLD7 GENMASK(111, 96) +#define WRMEM1_214_FLD8 GENMASK(127, 112) + +/* WRMEM1_215 register fields */ +#define WRMEM1_215_FLD1 GENMASK(15, 0) +#define WRMEM1_215_FLD2 GENMASK(31, 16) +#define WRMEM1_215_FLD3 GENMASK(47, 32) +#define WRMEM1_215_FLD4 GENMASK(63, 48) +#define WRMEM1_215_FLD5 GENMASK(79, 64) +#define WRMEM1_215_FLD6 GENMASK(95, 80) +#define WRMEM1_215_FLD7 GENMASK(111, 96) +#define WRMEM1_215_FLD8 GENMASK(127, 112) + +/* WRMEM1_216 register fields */ +#define WRMEM1_216_FLD1 GENMASK(15, 0) +#define WRMEM1_216_FLD2 GENMASK(31, 16) +#define WRMEM1_216_FLD3 GENMASK(47, 32) +#define WRMEM1_216_FLD4 GENMASK(63, 48) +#define WRMEM1_216_FLD5 GENMASK(79, 64) +#define WRMEM1_216_FLD6 GENMASK(95, 80) +#define WRMEM1_216_FLD7 GENMASK(111, 96) +#define WRMEM1_216_FLD8 GENMASK(127, 112) + +/* WRMEM1_217 register fields */ +#define WRMEM1_217_FLD1 GENMASK(15, 0) +#define WRMEM1_217_FLD2 GENMASK(31, 16) +#define WRMEM1_217_FLD3 GENMASK(47, 32) +#define WRMEM1_217_FLD4 GENMASK(63, 48) +#define WRMEM1_217_FLD5 GENMASK(79, 64) +#define WRMEM1_217_FLD6 GENMASK(95, 80) +#define WRMEM1_217_FLD7 GENMASK(111, 96) +#define WRMEM1_217_FLD8 GENMASK(127, 112) + +/* WRMEM1_218 register fields */ +#define WRMEM1_218_FLD1 GENMASK(15, 0) +#define WRMEM1_218_FLD2 GENMASK(31, 16) +#define WRMEM1_218_FLD3 GENMASK(47, 32) +#define WRMEM1_218_FLD4 GENMASK(63, 48) +#define WRMEM1_218_FLD5 GENMASK(79, 64) +#define WRMEM1_218_FLD6 GENMASK(95, 80) +#define WRMEM1_218_FLD7 GENMASK(111, 96) +#define WRMEM1_218_FLD8 GENMASK(127, 112) + +/* WRMEM1_219 register fields */ +#define WRMEM1_219_FLD1 GENMASK(15, 0) +#define WRMEM1_219_FLD2 GENMASK(31, 16) +#define WRMEM1_219_FLD3 GENMASK(47, 32) +#define WRMEM1_219_FLD4 GENMASK(63, 48) +#define WRMEM1_219_FLD5 GENMASK(79, 64) +#define WRMEM1_219_FLD6 GENMASK(95, 80) +#define WRMEM1_219_FLD7 GENMASK(111, 96) +#define WRMEM1_219_FLD8 GENMASK(127, 112) + +/* WRMEM1_220 register fields */ +#define WRMEM1_220_FLD1 GENMASK(15, 0) +#define WRMEM1_220_FLD2 GENMASK(31, 16) +#define WRMEM1_220_FLD3 GENMASK(47, 32) +#define WRMEM1_220_FLD4 GENMASK(63, 48) +#define WRMEM1_220_FLD5 GENMASK(79, 64) +#define WRMEM1_220_FLD6 GENMASK(95, 80) +#define WRMEM1_220_FLD7 GENMASK(111, 96) +#define WRMEM1_220_FLD8 GENMASK(127, 112) + +/* WRMEM1_221 register fields */ +#define WRMEM1_221_FLD1 GENMASK(15, 0) +#define WRMEM1_221_FLD2 GENMASK(31, 16) +#define WRMEM1_221_FLD3 GENMASK(47, 32) +#define WRMEM1_221_FLD4 GENMASK(63, 48) +#define WRMEM1_221_FLD5 GENMASK(79, 64) +#define WRMEM1_221_FLD6 GENMASK(95, 80) +#define WRMEM1_221_FLD7 GENMASK(111, 96) +#define WRMEM1_221_FLD8 GENMASK(127, 112) + +/* WRMEM1_222 register fields */ +#define WRMEM1_222_FLD1 GENMASK(15, 0) +#define WRMEM1_222_FLD2 GENMASK(31, 16) +#define WRMEM1_222_FLD3 GENMASK(47, 32) +#define WRMEM1_222_FLD4 GENMASK(63, 48) +#define WRMEM1_222_FLD5 GENMASK(79, 64) +#define WRMEM1_222_FLD6 GENMASK(95, 80) +#define WRMEM1_222_FLD7 GENMASK(111, 96) +#define WRMEM1_222_FLD8 GENMASK(127, 112) + +/* WRMEM1_223 register fields */ +#define WRMEM1_223_FLD1 GENMASK(15, 0) +#define WRMEM1_223_FLD2 GENMASK(31, 16) +#define WRMEM1_223_FLD3 GENMASK(47, 32) +#define WRMEM1_223_FLD4 GENMASK(63, 48) +#define WRMEM1_223_FLD5 GENMASK(79, 64) +#define WRMEM1_223_FLD6 GENMASK(95, 80) +#define WRMEM1_223_FLD7 GENMASK(111, 96) +#define WRMEM1_223_FLD8 GENMASK(127, 112) + +/* WRMEM1_224 register fields */ +#define WRMEM1_224_FLD1 GENMASK(15, 0) +#define WRMEM1_224_FLD2 GENMASK(31, 16) +#define WRMEM1_224_FLD3 GENMASK(47, 32) +#define WRMEM1_224_FLD4 GENMASK(63, 48) +#define WRMEM1_224_FLD5 GENMASK(79, 64) +#define WRMEM1_224_FLD6 GENMASK(95, 80) +#define WRMEM1_224_FLD7 GENMASK(111, 96) +#define WRMEM1_224_FLD8 GENMASK(127, 112) + +/* WRMEM1_225 register fields */ +#define WRMEM1_225_FLD1 GENMASK(15, 0) +#define WRMEM1_225_FLD2 GENMASK(31, 16) +#define WRMEM1_225_FLD3 GENMASK(47, 32) +#define WRMEM1_225_FLD4 GENMASK(63, 48) +#define WRMEM1_225_FLD5 GENMASK(79, 64) +#define WRMEM1_225_FLD6 GENMASK(95, 80) +#define WRMEM1_225_FLD7 GENMASK(111, 96) +#define WRMEM1_225_FLD8 GENMASK(127, 112) + +/* WRMEM1_226 register fields */ +#define WRMEM1_226_FLD1 GENMASK(15, 0) +#define WRMEM1_226_FLD2 GENMASK(31, 16) +#define WRMEM1_226_FLD3 GENMASK(47, 32) +#define WRMEM1_226_FLD4 GENMASK(63, 48) +#define WRMEM1_226_FLD5 GENMASK(79, 64) +#define WRMEM1_226_FLD6 GENMASK(95, 80) +#define WRMEM1_226_FLD7 GENMASK(111, 96) +#define WRMEM1_226_FLD8 GENMASK(127, 112) + +/* WRMEM1_227 register fields */ +#define WRMEM1_227_FLD1 GENMASK(15, 0) +#define WRMEM1_227_FLD2 GENMASK(31, 16) +#define WRMEM1_227_FLD3 GENMASK(47, 32) +#define WRMEM1_227_FLD4 GENMASK(63, 48) +#define WRMEM1_227_FLD5 GENMASK(79, 64) +#define WRMEM1_227_FLD6 GENMASK(95, 80) +#define WRMEM1_227_FLD7 GENMASK(111, 96) +#define WRMEM1_227_FLD8 GENMASK(127, 112) + +/* WRMEM1_228 register fields */ +#define WRMEM1_228_FLD1 GENMASK(15, 0) +#define WRMEM1_228_FLD2 GENMASK(31, 16) +#define WRMEM1_228_FLD3 GENMASK(47, 32) +#define WRMEM1_228_FLD4 GENMASK(63, 48) +#define WRMEM1_228_FLD5 GENMASK(79, 64) +#define WRMEM1_228_FLD6 GENMASK(95, 80) +#define WRMEM1_228_FLD7 GENMASK(111, 96) +#define WRMEM1_228_FLD8 GENMASK(127, 112) + +/* WRMEM1_229 register fields */ +#define WRMEM1_229_FLD1 GENMASK(15, 0) +#define WRMEM1_229_FLD2 GENMASK(31, 16) +#define WRMEM1_229_FLD3 GENMASK(47, 32) +#define WRMEM1_229_FLD4 GENMASK(63, 48) +#define WRMEM1_229_FLD5 GENMASK(79, 64) +#define WRMEM1_229_FLD6 GENMASK(95, 80) +#define WRMEM1_229_FLD7 GENMASK(111, 96) +#define WRMEM1_229_FLD8 GENMASK(127, 112) + +/* WRMEM1_230 register fields */ +#define WRMEM1_230_FLD1 GENMASK(15, 0) +#define WRMEM1_230_FLD2 GENMASK(31, 16) +#define WRMEM1_230_FLD3 GENMASK(47, 32) +#define WRMEM1_230_FLD4 GENMASK(63, 48) +#define WRMEM1_230_FLD5 GENMASK(79, 64) +#define WRMEM1_230_FLD6 GENMASK(95, 80) +#define WRMEM1_230_FLD7 GENMASK(111, 96) +#define WRMEM1_230_FLD8 GENMASK(127, 112) + +/* WRMEM1_231 register fields */ +#define WRMEM1_231_FLD1 GENMASK(15, 0) +#define WRMEM1_231_FLD2 GENMASK(31, 16) +#define WRMEM1_231_FLD3 GENMASK(47, 32) +#define WRMEM1_231_FLD4 GENMASK(63, 48) +#define WRMEM1_231_FLD5 GENMASK(79, 64) +#define WRMEM1_231_FLD6 GENMASK(95, 80) +#define WRMEM1_231_FLD7 GENMASK(111, 96) +#define WRMEM1_231_FLD8 GENMASK(127, 112) + +/* WRMEM1_232 register fields */ +#define WRMEM1_232_FLD1 GENMASK(15, 0) +#define WRMEM1_232_FLD2 GENMASK(31, 16) +#define WRMEM1_232_FLD3 GENMASK(47, 32) +#define WRMEM1_232_FLD4 GENMASK(63, 48) +#define WRMEM1_232_FLD5 GENMASK(79, 64) +#define WRMEM1_232_FLD6 GENMASK(95, 80) +#define WRMEM1_232_FLD7 GENMASK(111, 96) +#define WRMEM1_232_FLD8 GENMASK(127, 112) + +/* WRMEM1_233 register fields */ +#define WRMEM1_233_FLD1 GENMASK(15, 0) +#define WRMEM1_233_FLD2 GENMASK(31, 16) +#define WRMEM1_233_FLD3 GENMASK(47, 32) +#define WRMEM1_233_FLD4 GENMASK(63, 48) +#define WRMEM1_233_FLD5 GENMASK(79, 64) +#define WRMEM1_233_FLD6 GENMASK(95, 80) +#define WRMEM1_233_FLD7 GENMASK(111, 96) +#define WRMEM1_233_FLD8 GENMASK(127, 112) + +/* WRMEM1_234 register fields */ +#define WRMEM1_234_FLD1 GENMASK(15, 0) +#define WRMEM1_234_FLD2 GENMASK(31, 16) +#define WRMEM1_234_FLD3 GENMASK(47, 32) +#define WRMEM1_234_FLD4 GENMASK(63, 48) +#define WRMEM1_234_FLD5 GENMASK(79, 64) +#define WRMEM1_234_FLD6 GENMASK(95, 80) +#define WRMEM1_234_FLD7 GENMASK(111, 96) +#define WRMEM1_234_FLD8 GENMASK(127, 112) + +/* WRMEM1_235 register fields */ +#define WRMEM1_235_FLD1 GENMASK(15, 0) +#define WRMEM1_235_FLD2 GENMASK(31, 16) +#define WRMEM1_235_FLD3 GENMASK(47, 32) +#define WRMEM1_235_FLD4 GENMASK(63, 48) +#define WRMEM1_235_FLD5 GENMASK(79, 64) +#define WRMEM1_235_FLD6 GENMASK(95, 80) +#define WRMEM1_235_FLD7 GENMASK(111, 96) +#define WRMEM1_235_FLD8 GENMASK(127, 112) + +/* WRMEM1_236 register fields */ +#define WRMEM1_236_FLD1 GENMASK(15, 0) +#define WRMEM1_236_FLD2 GENMASK(31, 16) +#define WRMEM1_236_FLD3 GENMASK(47, 32) +#define WRMEM1_236_FLD4 GENMASK(63, 48) +#define WRMEM1_236_FLD5 GENMASK(79, 64) +#define WRMEM1_236_FLD6 GENMASK(95, 80) +#define WRMEM1_236_FLD7 GENMASK(111, 96) +#define WRMEM1_236_FLD8 GENMASK(127, 112) + +/* WRMEM1_237 register fields */ +#define WRMEM1_237_FLD1 GENMASK(15, 0) +#define WRMEM1_237_FLD2 GENMASK(31, 16) +#define WRMEM1_237_FLD3 GENMASK(47, 32) +#define WRMEM1_237_FLD4 GENMASK(63, 48) +#define WRMEM1_237_FLD5 GENMASK(79, 64) +#define WRMEM1_237_FLD6 GENMASK(95, 80) +#define WRMEM1_237_FLD7 GENMASK(111, 96) +#define WRMEM1_237_FLD8 GENMASK(127, 112) + +/* WRMEM1_238 register fields */ +#define WRMEM1_238_FLD1 GENMASK(15, 0) +#define WRMEM1_238_FLD2 GENMASK(31, 16) +#define WRMEM1_238_FLD3 GENMASK(47, 32) +#define WRMEM1_238_FLD4 GENMASK(63, 48) +#define WRMEM1_238_FLD5 GENMASK(79, 64) +#define WRMEM1_238_FLD6 GENMASK(95, 80) +#define WRMEM1_238_FLD7 GENMASK(111, 96) +#define WRMEM1_238_FLD8 GENMASK(127, 112) + +/* WRMEM1_239 register fields */ +#define WRMEM1_239_FLD1 GENMASK(15, 0) +#define WRMEM1_239_FLD2 GENMASK(31, 16) +#define WRMEM1_239_FLD3 GENMASK(47, 32) +#define WRMEM1_239_FLD4 GENMASK(63, 48) +#define WRMEM1_239_FLD5 GENMASK(79, 64) +#define WRMEM1_239_FLD6 GENMASK(95, 80) +#define WRMEM1_239_FLD7 GENMASK(111, 96) +#define WRMEM1_239_FLD8 GENMASK(127, 112) + +/* WRMEM1_240 register fields */ +#define WRMEM1_240_FLD1 GENMASK(15, 0) +#define WRMEM1_240_FLD2 GENMASK(31, 16) +#define WRMEM1_240_FLD3 GENMASK(47, 32) +#define WRMEM1_240_FLD4 GENMASK(63, 48) +#define WRMEM1_240_FLD5 GENMASK(79, 64) +#define WRMEM1_240_FLD6 GENMASK(95, 80) +#define WRMEM1_240_FLD7 GENMASK(111, 96) +#define WRMEM1_240_FLD8 GENMASK(127, 112) + +/* WRMEM1_241 register fields */ +#define WRMEM1_241_FLD1 GENMASK(15, 0) +#define WRMEM1_241_FLD2 GENMASK(31, 16) +#define WRMEM1_241_FLD3 GENMASK(47, 32) +#define WRMEM1_241_FLD4 GENMASK(63, 48) +#define WRMEM1_241_FLD5 GENMASK(79, 64) +#define WRMEM1_241_FLD6 GENMASK(95, 80) +#define WRMEM1_241_FLD7 GENMASK(111, 96) +#define WRMEM1_241_FLD8 GENMASK(127, 112) + +/* WRMEM1_242 register fields */ +#define WRMEM1_242_FLD1 GENMASK(15, 0) +#define WRMEM1_242_FLD2 GENMASK(31, 16) +#define WRMEM1_242_FLD3 GENMASK(47, 32) +#define WRMEM1_242_FLD4 GENMASK(63, 48) +#define WRMEM1_242_FLD5 GENMASK(79, 64) +#define WRMEM1_242_FLD6 GENMASK(95, 80) +#define WRMEM1_242_FLD7 GENMASK(111, 96) +#define WRMEM1_242_FLD8 GENMASK(127, 112) + +/* WRMEM1_243 register fields */ +#define WRMEM1_243_FLD1 GENMASK(15, 0) +#define WRMEM1_243_FLD2 GENMASK(31, 16) +#define WRMEM1_243_FLD3 GENMASK(47, 32) +#define WRMEM1_243_FLD4 GENMASK(63, 48) +#define WRMEM1_243_FLD5 GENMASK(79, 64) +#define WRMEM1_243_FLD6 GENMASK(95, 80) +#define WRMEM1_243_FLD7 GENMASK(111, 96) +#define WRMEM1_243_FLD8 GENMASK(127, 112) + +/* WRMEM1_244 register fields */ +#define WRMEM1_244_FLD1 GENMASK(15, 0) +#define WRMEM1_244_FLD2 GENMASK(31, 16) +#define WRMEM1_244_FLD3 GENMASK(47, 32) +#define WRMEM1_244_FLD4 GENMASK(63, 48) +#define WRMEM1_244_FLD5 GENMASK(79, 64) +#define WRMEM1_244_FLD6 GENMASK(95, 80) +#define WRMEM1_244_FLD7 GENMASK(111, 96) +#define WRMEM1_244_FLD8 GENMASK(127, 112) + +/* WRMEM1_245 register fields */ +#define WRMEM1_245_FLD1 GENMASK(15, 0) +#define WRMEM1_245_FLD2 GENMASK(31, 16) +#define WRMEM1_245_FLD3 GENMASK(47, 32) +#define WRMEM1_245_FLD4 GENMASK(63, 48) +#define WRMEM1_245_FLD5 GENMASK(79, 64) +#define WRMEM1_245_FLD6 GENMASK(95, 80) +#define WRMEM1_245_FLD7 GENMASK(111, 96) +#define WRMEM1_245_FLD8 GENMASK(127, 112) + +/* WRMEM1_246 register fields */ +#define WRMEM1_246_FLD1 GENMASK(15, 0) +#define WRMEM1_246_FLD2 GENMASK(31, 16) +#define WRMEM1_246_FLD3 GENMASK(47, 32) +#define WRMEM1_246_FLD4 GENMASK(63, 48) +#define WRMEM1_246_FLD5 GENMASK(79, 64) +#define WRMEM1_246_FLD6 GENMASK(95, 80) +#define WRMEM1_246_FLD7 GENMASK(111, 96) +#define WRMEM1_246_FLD8 GENMASK(127, 112) + +/* WRMEM1_247 register fields */ +#define WRMEM1_247_FLD1 GENMASK(15, 0) +#define WRMEM1_247_FLD2 GENMASK(31, 16) +#define WRMEM1_247_FLD3 GENMASK(47, 32) +#define WRMEM1_247_FLD4 GENMASK(63, 48) +#define WRMEM1_247_FLD5 GENMASK(79, 64) +#define WRMEM1_247_FLD6 GENMASK(95, 80) +#define WRMEM1_247_FLD7 GENMASK(111, 96) +#define WRMEM1_247_FLD8 GENMASK(127, 112) + +/* WRMEM1_248 register fields */ +#define WRMEM1_248_FLD1 GENMASK(15, 0) +#define WRMEM1_248_FLD2 GENMASK(31, 16) +#define WRMEM1_248_FLD3 GENMASK(47, 32) +#define WRMEM1_248_FLD4 GENMASK(63, 48) +#define WRMEM1_248_FLD5 GENMASK(79, 64) +#define WRMEM1_248_FLD6 GENMASK(95, 80) +#define WRMEM1_248_FLD7 GENMASK(111, 96) +#define WRMEM1_248_FLD8 GENMASK(127, 112) + +/* WRMEM1_249 register fields */ +#define WRMEM1_249_FLD1 GENMASK(15, 0) +#define WRMEM1_249_FLD2 GENMASK(31, 16) +#define WRMEM1_249_FLD3 GENMASK(47, 32) +#define WRMEM1_249_FLD4 GENMASK(63, 48) +#define WRMEM1_249_FLD5 GENMASK(79, 64) +#define WRMEM1_249_FLD6 GENMASK(95, 80) +#define WRMEM1_249_FLD7 GENMASK(111, 96) +#define WRMEM1_249_FLD8 GENMASK(127, 112) + +/* WRMEM1_250 register fields */ +#define WRMEM1_250_FLD1 GENMASK(15, 0) +#define WRMEM1_250_FLD2 GENMASK(31, 16) +#define WRMEM1_250_FLD3 GENMASK(47, 32) +#define WRMEM1_250_FLD4 GENMASK(63, 48) +#define WRMEM1_250_FLD5 GENMASK(79, 64) +#define WRMEM1_250_FLD6 GENMASK(95, 80) +#define WRMEM1_250_FLD7 GENMASK(111, 96) +#define WRMEM1_250_FLD8 GENMASK(127, 112) + +/* WRMEM1_251 register fields */ +#define WRMEM1_251_FLD1 GENMASK(15, 0) +#define WRMEM1_251_FLD2 GENMASK(31, 16) +#define WRMEM1_251_FLD3 GENMASK(47, 32) +#define WRMEM1_251_FLD4 GENMASK(63, 48) +#define WRMEM1_251_FLD5 GENMASK(79, 64) +#define WRMEM1_251_FLD6 GENMASK(95, 80) +#define WRMEM1_251_FLD7 GENMASK(111, 96) +#define WRMEM1_251_FLD8 GENMASK(127, 112) + +/* WRMEM1_252 register fields */ +#define WRMEM1_252_FLD1 GENMASK(15, 0) +#define WRMEM1_252_FLD2 GENMASK(31, 16) +#define WRMEM1_252_FLD3 GENMASK(47, 32) +#define WRMEM1_252_FLD4 GENMASK(63, 48) +#define WRMEM1_252_FLD5 GENMASK(79, 64) +#define WRMEM1_252_FLD6 GENMASK(95, 80) +#define WRMEM1_252_FLD7 GENMASK(111, 96) +#define WRMEM1_252_FLD8 GENMASK(127, 112) + +/* WRMEM1_253 register fields */ +#define WRMEM1_253_FLD1 GENMASK(15, 0) +#define WRMEM1_253_FLD2 GENMASK(31, 16) +#define WRMEM1_253_FLD3 GENMASK(47, 32) +#define WRMEM1_253_FLD4 GENMASK(63, 48) +#define WRMEM1_253_FLD5 GENMASK(79, 64) +#define WRMEM1_253_FLD6 GENMASK(95, 80) +#define WRMEM1_253_FLD7 GENMASK(111, 96) +#define WRMEM1_253_FLD8 GENMASK(127, 112) + +/* WRMEM1_254 register fields */ +#define WRMEM1_254_FLD1 GENMASK(15, 0) +#define WRMEM1_254_FLD2 GENMASK(31, 16) +#define WRMEM1_254_FLD3 GENMASK(47, 32) +#define WRMEM1_254_FLD4 GENMASK(63, 48) +#define WRMEM1_254_FLD5 GENMASK(79, 64) +#define WRMEM1_254_FLD6 GENMASK(95, 80) +#define WRMEM1_254_FLD7 GENMASK(111, 96) +#define WRMEM1_254_FLD8 GENMASK(127, 112) + +/* WRMEM1_255 register fields */ +#define WRMEM1_255_FLD1 GENMASK(15, 0) +#define WRMEM1_255_FLD2 GENMASK(31, 16) +#define WRMEM1_255_FLD3 GENMASK(47, 32) +#define WRMEM1_255_FLD4 GENMASK(63, 48) +#define WRMEM1_255_FLD5 GENMASK(79, 64) +#define WRMEM1_255_FLD6 GENMASK(95, 80) +#define WRMEM1_255_FLD7 GENMASK(111, 96) +#define WRMEM1_255_FLD8 GENMASK(127, 112) + +/* WRMEM1_256 register fields */ +#define WRMEM1_256_FLD1 GENMASK(15, 0) +#define WRMEM1_256_FLD2 GENMASK(31, 16) +#define WRMEM1_256_FLD3 GENMASK(47, 32) +#define WRMEM1_256_FLD4 GENMASK(63, 48) +#define WRMEM1_256_FLD5 GENMASK(79, 64) +#define WRMEM1_256_FLD6 GENMASK(95, 80) +#define WRMEM1_256_FLD7 GENMASK(111, 96) +#define WRMEM1_256_FLD8 GENMASK(127, 112) + +/* WRMEM1_257 register fields */ +#define WRMEM1_257_FLD1 GENMASK(15, 0) +#define WRMEM1_257_FLD2 GENMASK(31, 16) +#define WRMEM1_257_FLD3 GENMASK(47, 32) +#define WRMEM1_257_FLD4 GENMASK(63, 48) +#define WRMEM1_257_FLD5 GENMASK(79, 64) +#define WRMEM1_257_FLD6 GENMASK(95, 80) +#define WRMEM1_257_FLD7 GENMASK(111, 96) +#define WRMEM1_257_FLD8 GENMASK(127, 112) + +/* WRMEM1_258 register fields */ +#define WRMEM1_258_FLD1 GENMASK(15, 0) +#define WRMEM1_258_FLD2 GENMASK(31, 16) +#define WRMEM1_258_FLD3 GENMASK(47, 32) +#define WRMEM1_258_FLD4 GENMASK(63, 48) +#define WRMEM1_258_FLD5 GENMASK(79, 64) +#define WRMEM1_258_FLD6 GENMASK(95, 80) +#define WRMEM1_258_FLD7 GENMASK(111, 96) +#define WRMEM1_258_FLD8 GENMASK(127, 112) + +/* WRMEM1_259 register fields */ +#define WRMEM1_259_FLD1 GENMASK(15, 0) +#define WRMEM1_259_FLD2 GENMASK(31, 16) +#define WRMEM1_259_FLD3 GENMASK(47, 32) +#define WRMEM1_259_FLD4 GENMASK(63, 48) +#define WRMEM1_259_FLD5 GENMASK(79, 64) +#define WRMEM1_259_FLD6 GENMASK(95, 80) +#define WRMEM1_259_FLD7 GENMASK(111, 96) +#define WRMEM1_259_FLD8 GENMASK(127, 112) + +/* WRMEM1_260 register fields */ +#define WRMEM1_260_FLD1 GENMASK(15, 0) +#define WRMEM1_260_FLD2 GENMASK(31, 16) +#define WRMEM1_260_FLD3 GENMASK(47, 32) +#define WRMEM1_260_FLD4 GENMASK(63, 48) +#define WRMEM1_260_FLD5 GENMASK(79, 64) +#define WRMEM1_260_FLD6 GENMASK(95, 80) +#define WRMEM1_260_FLD7 GENMASK(111, 96) +#define WRMEM1_260_FLD8 GENMASK(127, 112) + +/* WRMEM1_261 register fields */ +#define WRMEM1_261_FLD1 GENMASK(15, 0) +#define WRMEM1_261_FLD2 GENMASK(31, 16) +#define WRMEM1_261_FLD3 GENMASK(47, 32) +#define WRMEM1_261_FLD4 GENMASK(63, 48) +#define WRMEM1_261_FLD5 GENMASK(79, 64) +#define WRMEM1_261_FLD6 GENMASK(95, 80) +#define WRMEM1_261_FLD7 GENMASK(111, 96) +#define WRMEM1_261_FLD8 GENMASK(127, 112) + +/* WRMEM1_262 register fields */ +#define WRMEM1_262_FLD1 GENMASK(15, 0) +#define WRMEM1_262_FLD2 GENMASK(31, 16) +#define WRMEM1_262_FLD3 GENMASK(47, 32) +#define WRMEM1_262_FLD4 GENMASK(63, 48) +#define WRMEM1_262_FLD5 GENMASK(79, 64) +#define WRMEM1_262_FLD6 GENMASK(95, 80) +#define WRMEM1_262_FLD7 GENMASK(111, 96) +#define WRMEM1_262_FLD8 GENMASK(127, 112) + +/* WRMEM1_263 register fields */ +#define WRMEM1_263_FLD1 GENMASK(15, 0) +#define WRMEM1_263_FLD2 GENMASK(31, 16) +#define WRMEM1_263_FLD3 GENMASK(47, 32) +#define WRMEM1_263_FLD4 GENMASK(63, 48) +#define WRMEM1_263_FLD5 GENMASK(79, 64) +#define WRMEM1_263_FLD6 GENMASK(95, 80) +#define WRMEM1_263_FLD7 GENMASK(111, 96) +#define WRMEM1_263_FLD8 GENMASK(127, 112) + +/* WRMEM1_264 register fields */ +#define WRMEM1_264_FLD1 GENMASK(15, 0) +#define WRMEM1_264_FLD2 GENMASK(31, 16) +#define WRMEM1_264_FLD3 GENMASK(47, 32) +#define WRMEM1_264_FLD4 GENMASK(63, 48) +#define WRMEM1_264_FLD5 GENMASK(79, 64) +#define WRMEM1_264_FLD6 GENMASK(95, 80) +#define WRMEM1_264_FLD7 GENMASK(111, 96) +#define WRMEM1_264_FLD8 GENMASK(127, 112) + +/* WRMEM1_265 register fields */ +#define WRMEM1_265_FLD1 GENMASK(15, 0) +#define WRMEM1_265_FLD2 GENMASK(31, 16) +#define WRMEM1_265_FLD3 GENMASK(47, 32) +#define WRMEM1_265_FLD4 GENMASK(63, 48) +#define WRMEM1_265_FLD5 GENMASK(79, 64) +#define WRMEM1_265_FLD6 GENMASK(95, 80) +#define WRMEM1_265_FLD7 GENMASK(111, 96) +#define WRMEM1_265_FLD8 GENMASK(127, 112) + +/* WRMEM1_266 register fields */ +#define WRMEM1_266_FLD1 GENMASK(15, 0) +#define WRMEM1_266_FLD2 GENMASK(31, 16) +#define WRMEM1_266_FLD3 GENMASK(47, 32) +#define WRMEM1_266_FLD4 GENMASK(63, 48) +#define WRMEM1_266_FLD5 GENMASK(79, 64) +#define WRMEM1_266_FLD6 GENMASK(95, 80) +#define WRMEM1_266_FLD7 GENMASK(111, 96) +#define WRMEM1_266_FLD8 GENMASK(127, 112) + +/* WRMEM1_267 register fields */ +#define WRMEM1_267_FLD1 GENMASK(15, 0) +#define WRMEM1_267_FLD2 GENMASK(31, 16) +#define WRMEM1_267_FLD3 GENMASK(47, 32) +#define WRMEM1_267_FLD4 GENMASK(63, 48) +#define WRMEM1_267_FLD5 GENMASK(79, 64) +#define WRMEM1_267_FLD6 GENMASK(95, 80) +#define WRMEM1_267_FLD7 GENMASK(111, 96) +#define WRMEM1_267_FLD8 GENMASK(127, 112) + +/* WRMEM1_268 register fields */ +#define WRMEM1_268_FLD1 GENMASK(15, 0) +#define WRMEM1_268_FLD2 GENMASK(31, 16) +#define WRMEM1_268_FLD3 GENMASK(47, 32) +#define WRMEM1_268_FLD4 GENMASK(63, 48) +#define WRMEM1_268_FLD5 GENMASK(79, 64) +#define WRMEM1_268_FLD6 GENMASK(95, 80) +#define WRMEM1_268_FLD7 GENMASK(111, 96) +#define WRMEM1_268_FLD8 GENMASK(127, 112) + +/* WRMEM1_269 register fields */ +#define WRMEM1_269_FLD1 GENMASK(15, 0) +#define WRMEM1_269_FLD2 GENMASK(31, 16) +#define WRMEM1_269_FLD3 GENMASK(47, 32) +#define WRMEM1_269_FLD4 GENMASK(63, 48) +#define WRMEM1_269_FLD5 GENMASK(79, 64) +#define WRMEM1_269_FLD6 GENMASK(95, 80) +#define WRMEM1_269_FLD7 GENMASK(111, 96) +#define WRMEM1_269_FLD8 GENMASK(127, 112) + +/* WRMEM1_270 register fields */ +#define WRMEM1_270_FLD1 GENMASK(15, 0) +#define WRMEM1_270_FLD2 GENMASK(31, 16) +#define WRMEM1_270_FLD3 GENMASK(47, 32) +#define WRMEM1_270_FLD4 GENMASK(63, 48) +#define WRMEM1_270_FLD5 GENMASK(79, 64) +#define WRMEM1_270_FLD6 GENMASK(95, 80) +#define WRMEM1_270_FLD7 GENMASK(111, 96) +#define WRMEM1_270_FLD8 GENMASK(127, 112) + +/* WRMEM1_271 register fields */ +#define WRMEM1_271_FLD1 GENMASK(15, 0) +#define WRMEM1_271_FLD2 GENMASK(31, 16) +#define WRMEM1_271_FLD3 GENMASK(47, 32) +#define WRMEM1_271_FLD4 GENMASK(63, 48) +#define WRMEM1_271_FLD5 GENMASK(79, 64) +#define WRMEM1_271_FLD6 GENMASK(95, 80) +#define WRMEM1_271_FLD7 GENMASK(111, 96) +#define WRMEM1_271_FLD8 GENMASK(127, 112) + +/* WRMEM1_272 register fields */ +#define WRMEM1_272_FLD1 GENMASK(15, 0) +#define WRMEM1_272_FLD2 GENMASK(31, 16) +#define WRMEM1_272_FLD3 GENMASK(47, 32) +#define WRMEM1_272_FLD4 GENMASK(63, 48) +#define WRMEM1_272_FLD5 GENMASK(79, 64) +#define WRMEM1_272_FLD6 GENMASK(95, 80) +#define WRMEM1_272_FLD7 GENMASK(111, 96) +#define WRMEM1_272_FLD8 GENMASK(127, 112) + +/* WRMEM1_273 register fields */ +#define WRMEM1_273_FLD1 GENMASK(15, 0) +#define WRMEM1_273_FLD2 GENMASK(31, 16) +#define WRMEM1_273_FLD3 GENMASK(47, 32) +#define WRMEM1_273_FLD4 GENMASK(63, 48) +#define WRMEM1_273_FLD5 GENMASK(79, 64) +#define WRMEM1_273_FLD6 GENMASK(95, 80) +#define WRMEM1_273_FLD7 GENMASK(111, 96) +#define WRMEM1_273_FLD8 GENMASK(127, 112) + +/* WRMEM1_274 register fields */ +#define WRMEM1_274_FLD1 GENMASK(15, 0) +#define WRMEM1_274_FLD2 GENMASK(31, 16) +#define WRMEM1_274_FLD3 GENMASK(47, 32) +#define WRMEM1_274_FLD4 GENMASK(63, 48) +#define WRMEM1_274_FLD5 GENMASK(79, 64) +#define WRMEM1_274_FLD6 GENMASK(95, 80) +#define WRMEM1_274_FLD7 GENMASK(111, 96) +#define WRMEM1_274_FLD8 GENMASK(127, 112) + +/* WRMEM1_275 register fields */ +#define WRMEM1_275_FLD1 GENMASK(15, 0) +#define WRMEM1_275_FLD2 GENMASK(31, 16) +#define WRMEM1_275_FLD3 GENMASK(47, 32) +#define WRMEM1_275_FLD4 GENMASK(63, 48) +#define WRMEM1_275_FLD5 GENMASK(79, 64) +#define WRMEM1_275_FLD6 GENMASK(95, 80) +#define WRMEM1_275_FLD7 GENMASK(111, 96) +#define WRMEM1_275_FLD8 GENMASK(127, 112) + +/* WRMEM1_276 register fields */ +#define WRMEM1_276_FLD1 GENMASK(15, 0) +#define WRMEM1_276_FLD2 GENMASK(31, 16) +#define WRMEM1_276_FLD3 GENMASK(47, 32) +#define WRMEM1_276_FLD4 GENMASK(63, 48) +#define WRMEM1_276_FLD5 GENMASK(79, 64) +#define WRMEM1_276_FLD6 GENMASK(95, 80) +#define WRMEM1_276_FLD7 GENMASK(111, 96) +#define WRMEM1_276_FLD8 GENMASK(127, 112) + +/* WRMEM1_277 register fields */ +#define WRMEM1_277_FLD1 GENMASK(15, 0) +#define WRMEM1_277_FLD2 GENMASK(31, 16) +#define WRMEM1_277_FLD3 GENMASK(47, 32) +#define WRMEM1_277_FLD4 GENMASK(63, 48) +#define WRMEM1_277_FLD5 GENMASK(79, 64) +#define WRMEM1_277_FLD6 GENMASK(95, 80) +#define WRMEM1_277_FLD7 GENMASK(111, 96) +#define WRMEM1_277_FLD8 GENMASK(127, 112) + +/* WRMEM1_278 register fields */ +#define WRMEM1_278_FLD1 GENMASK(15, 0) +#define WRMEM1_278_FLD2 GENMASK(31, 16) +#define WRMEM1_278_FLD3 GENMASK(47, 32) +#define WRMEM1_278_FLD4 GENMASK(63, 48) +#define WRMEM1_278_FLD5 GENMASK(79, 64) +#define WRMEM1_278_FLD6 GENMASK(95, 80) +#define WRMEM1_278_FLD7 GENMASK(111, 96) +#define WRMEM1_278_FLD8 GENMASK(127, 112) + +/* WRMEM1_279 register fields */ +#define WRMEM1_279_FLD1 GENMASK(15, 0) +#define WRMEM1_279_FLD2 GENMASK(31, 16) +#define WRMEM1_279_FLD3 GENMASK(47, 32) +#define WRMEM1_279_FLD4 GENMASK(63, 48) +#define WRMEM1_279_FLD5 GENMASK(79, 64) +#define WRMEM1_279_FLD6 GENMASK(95, 80) +#define WRMEM1_279_FLD7 GENMASK(111, 96) +#define WRMEM1_279_FLD8 GENMASK(127, 112) + +/* WRMEM1_280 register fields */ +#define WRMEM1_280_FLD1 GENMASK(15, 0) +#define WRMEM1_280_FLD2 GENMASK(31, 16) +#define WRMEM1_280_FLD3 GENMASK(47, 32) +#define WRMEM1_280_FLD4 GENMASK(63, 48) +#define WRMEM1_280_FLD5 GENMASK(79, 64) +#define WRMEM1_280_FLD6 GENMASK(95, 80) +#define WRMEM1_280_FLD7 GENMASK(111, 96) +#define WRMEM1_280_FLD8 GENMASK(127, 112) + +/* WRMEM1_281 register fields */ +#define WRMEM1_281_FLD1 GENMASK(15, 0) +#define WRMEM1_281_FLD2 GENMASK(31, 16) +#define WRMEM1_281_FLD3 GENMASK(47, 32) +#define WRMEM1_281_FLD4 GENMASK(63, 48) +#define WRMEM1_281_FLD5 GENMASK(79, 64) +#define WRMEM1_281_FLD6 GENMASK(95, 80) +#define WRMEM1_281_FLD7 GENMASK(111, 96) +#define WRMEM1_281_FLD8 GENMASK(127, 112) + +/* WRMEM1_282 register fields */ +#define WRMEM1_282_FLD1 GENMASK(15, 0) +#define WRMEM1_282_FLD2 GENMASK(31, 16) +#define WRMEM1_282_FLD3 GENMASK(47, 32) +#define WRMEM1_282_FLD4 GENMASK(63, 48) +#define WRMEM1_282_FLD5 GENMASK(79, 64) +#define WRMEM1_282_FLD6 GENMASK(95, 80) +#define WRMEM1_282_FLD7 GENMASK(111, 96) +#define WRMEM1_282_FLD8 GENMASK(127, 112) + +/* WRMEM1_283 register fields */ +#define WRMEM1_283_FLD1 GENMASK(15, 0) +#define WRMEM1_283_FLD2 GENMASK(31, 16) +#define WRMEM1_283_FLD3 GENMASK(47, 32) +#define WRMEM1_283_FLD4 GENMASK(63, 48) +#define WRMEM1_283_FLD5 GENMASK(79, 64) +#define WRMEM1_283_FLD6 GENMASK(95, 80) +#define WRMEM1_283_FLD7 GENMASK(111, 96) +#define WRMEM1_283_FLD8 GENMASK(127, 112) + +/* WRMEM1_284 register fields */ +#define WRMEM1_284_FLD1 GENMASK(15, 0) +#define WRMEM1_284_FLD2 GENMASK(31, 16) +#define WRMEM1_284_FLD3 GENMASK(47, 32) +#define WRMEM1_284_FLD4 GENMASK(63, 48) +#define WRMEM1_284_FLD5 GENMASK(79, 64) +#define WRMEM1_284_FLD6 GENMASK(95, 80) +#define WRMEM1_284_FLD7 GENMASK(111, 96) +#define WRMEM1_284_FLD8 GENMASK(127, 112) + +/* WRMEM1_285 register fields */ +#define WRMEM1_285_FLD1 GENMASK(15, 0) +#define WRMEM1_285_FLD2 GENMASK(31, 16) +#define WRMEM1_285_FLD3 GENMASK(47, 32) +#define WRMEM1_285_FLD4 GENMASK(63, 48) +#define WRMEM1_285_FLD5 GENMASK(79, 64) +#define WRMEM1_285_FLD6 GENMASK(95, 80) +#define WRMEM1_285_FLD7 GENMASK(111, 96) +#define WRMEM1_285_FLD8 GENMASK(127, 112) + +/* WRMEM1_286 register fields */ +#define WRMEM1_286_FLD1 GENMASK(15, 0) +#define WRMEM1_286_FLD2 GENMASK(31, 16) +#define WRMEM1_286_FLD3 GENMASK(47, 32) +#define WRMEM1_286_FLD4 GENMASK(63, 48) +#define WRMEM1_286_FLD5 GENMASK(79, 64) +#define WRMEM1_286_FLD6 GENMASK(95, 80) +#define WRMEM1_286_FLD7 GENMASK(111, 96) +#define WRMEM1_286_FLD8 GENMASK(127, 112) + +/* WRMEM1_287 register fields */ +#define WRMEM1_287_FLD1 GENMASK(15, 0) +#define WRMEM1_287_FLD2 GENMASK(31, 16) +#define WRMEM1_287_FLD3 GENMASK(47, 32) +#define WRMEM1_287_FLD4 GENMASK(63, 48) +#define WRMEM1_287_FLD5 GENMASK(79, 64) +#define WRMEM1_287_FLD6 GENMASK(95, 80) +#define WRMEM1_287_FLD7 GENMASK(111, 96) +#define WRMEM1_287_FLD8 GENMASK(127, 112) + +/* WRMEM1_288 register fields */ +#define WRMEM1_288_FLD1 GENMASK(15, 0) +#define WRMEM1_288_FLD2 GENMASK(31, 16) +#define WRMEM1_288_FLD3 GENMASK(47, 32) +#define WRMEM1_288_FLD4 GENMASK(63, 48) +#define WRMEM1_288_FLD5 GENMASK(79, 64) +#define WRMEM1_288_FLD6 GENMASK(95, 80) +#define WRMEM1_288_FLD7 GENMASK(111, 96) +#define WRMEM1_288_FLD8 GENMASK(127, 112) + +/* WRMEM1_289 register fields */ +#define WRMEM1_289_FLD1 GENMASK(15, 0) +#define WRMEM1_289_FLD2 GENMASK(31, 16) +#define WRMEM1_289_FLD3 GENMASK(47, 32) +#define WRMEM1_289_FLD4 GENMASK(63, 48) +#define WRMEM1_289_FLD5 GENMASK(79, 64) +#define WRMEM1_289_FLD6 GENMASK(95, 80) +#define WRMEM1_289_FLD7 GENMASK(111, 96) +#define WRMEM1_289_FLD8 GENMASK(127, 112) + +/* WRMEM1_290 register fields */ +#define WRMEM1_290_FLD1 GENMASK(15, 0) +#define WRMEM1_290_FLD2 GENMASK(31, 16) +#define WRMEM1_290_FLD3 GENMASK(47, 32) +#define WRMEM1_290_FLD4 GENMASK(63, 48) +#define WRMEM1_290_FLD5 GENMASK(79, 64) +#define WRMEM1_290_FLD6 GENMASK(95, 80) +#define WRMEM1_290_FLD7 GENMASK(111, 96) +#define WRMEM1_290_FLD8 GENMASK(127, 112) + +/* WRMEM1_291 register fields */ +#define WRMEM1_291_FLD1 GENMASK(15, 0) +#define WRMEM1_291_FLD2 GENMASK(31, 16) +#define WRMEM1_291_FLD3 GENMASK(47, 32) +#define WRMEM1_291_FLD4 GENMASK(63, 48) +#define WRMEM1_291_FLD5 GENMASK(79, 64) +#define WRMEM1_291_FLD6 GENMASK(95, 80) +#define WRMEM1_291_FLD7 GENMASK(111, 96) +#define WRMEM1_291_FLD8 GENMASK(127, 112) + +/* WRMEM1_292 register fields */ +#define WRMEM1_292_FLD1 GENMASK(15, 0) +#define WRMEM1_292_FLD2 GENMASK(31, 16) +#define WRMEM1_292_FLD3 GENMASK(47, 32) +#define WRMEM1_292_FLD4 GENMASK(63, 48) +#define WRMEM1_292_FLD5 GENMASK(79, 64) +#define WRMEM1_292_FLD6 GENMASK(95, 80) +#define WRMEM1_292_FLD7 GENMASK(111, 96) +#define WRMEM1_292_FLD8 GENMASK(127, 112) + +/* WRMEM1_293 register fields */ +#define WRMEM1_293_FLD1 GENMASK(15, 0) +#define WRMEM1_293_FLD2 GENMASK(31, 16) +#define WRMEM1_293_FLD3 GENMASK(47, 32) +#define WRMEM1_293_FLD4 GENMASK(63, 48) +#define WRMEM1_293_FLD5 GENMASK(79, 64) +#define WRMEM1_293_FLD6 GENMASK(95, 80) +#define WRMEM1_293_FLD7 GENMASK(111, 96) +#define WRMEM1_293_FLD8 GENMASK(127, 112) + +/* WRMEM1_294 register fields */ +#define WRMEM1_294_FLD1 GENMASK(15, 0) +#define WRMEM1_294_FLD2 GENMASK(31, 16) +#define WRMEM1_294_FLD3 GENMASK(47, 32) +#define WRMEM1_294_FLD4 GENMASK(63, 48) +#define WRMEM1_294_FLD5 GENMASK(79, 64) +#define WRMEM1_294_FLD6 GENMASK(95, 80) +#define WRMEM1_294_FLD7 GENMASK(111, 96) +#define WRMEM1_294_FLD8 GENMASK(127, 112) + +/* WRMEM1_295 register fields */ +#define WRMEM1_295_FLD1 GENMASK(15, 0) +#define WRMEM1_295_FLD2 GENMASK(31, 16) +#define WRMEM1_295_FLD3 GENMASK(47, 32) +#define WRMEM1_295_FLD4 GENMASK(63, 48) +#define WRMEM1_295_FLD5 GENMASK(79, 64) +#define WRMEM1_295_FLD6 GENMASK(95, 80) +#define WRMEM1_295_FLD7 GENMASK(111, 96) +#define WRMEM1_295_FLD8 GENMASK(127, 112) + +/* WRMEM1_296 register fields */ +#define WRMEM1_296_FLD1 GENMASK(15, 0) +#define WRMEM1_296_FLD2 GENMASK(31, 16) +#define WRMEM1_296_FLD3 GENMASK(47, 32) +#define WRMEM1_296_FLD4 GENMASK(63, 48) +#define WRMEM1_296_FLD5 GENMASK(79, 64) +#define WRMEM1_296_FLD6 GENMASK(95, 80) +#define WRMEM1_296_FLD7 GENMASK(111, 96) +#define WRMEM1_296_FLD8 GENMASK(127, 112) + +/* WRMEM1_297 register fields */ +#define WRMEM1_297_FLD1 GENMASK(15, 0) +#define WRMEM1_297_FLD2 GENMASK(31, 16) +#define WRMEM1_297_FLD3 GENMASK(47, 32) +#define WRMEM1_297_FLD4 GENMASK(63, 48) +#define WRMEM1_297_FLD5 GENMASK(79, 64) +#define WRMEM1_297_FLD6 GENMASK(95, 80) +#define WRMEM1_297_FLD7 GENMASK(111, 96) +#define WRMEM1_297_FLD8 GENMASK(127, 112) + +/* WRMEM1_298 register fields */ +#define WRMEM1_298_FLD1 GENMASK(15, 0) +#define WRMEM1_298_FLD2 GENMASK(31, 16) +#define WRMEM1_298_FLD3 GENMASK(47, 32) +#define WRMEM1_298_FLD4 GENMASK(63, 48) +#define WRMEM1_298_FLD5 GENMASK(79, 64) +#define WRMEM1_298_FLD6 GENMASK(95, 80) +#define WRMEM1_298_FLD7 GENMASK(111, 96) +#define WRMEM1_298_FLD8 GENMASK(127, 112) + +/* WRMEM1_299 register fields */ +#define WRMEM1_299_FLD1 GENMASK(15, 0) +#define WRMEM1_299_FLD2 GENMASK(31, 16) +#define WRMEM1_299_FLD3 GENMASK(47, 32) +#define WRMEM1_299_FLD4 GENMASK(63, 48) +#define WRMEM1_299_FLD5 GENMASK(79, 64) +#define WRMEM1_299_FLD6 GENMASK(95, 80) +#define WRMEM1_299_FLD7 GENMASK(111, 96) +#define WRMEM1_299_FLD8 GENMASK(127, 112) + +#endif diff --git a/test/basic_tests/rdl_uvmmem_mimic/golden/output.h b/test/basic_tests/rdl_uvmmem_mimic/golden/output.h new file mode 100644 index 0000000..29de439 --- /dev/null +++ b/test/basic_tests/rdl_uvmmem_mimic/golden/output.h @@ -0,0 +1,3743 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_uvmmem_mimic/test.rdl +// Parms: ./rdl_uvmmem_mimic/test.parms +// Date: Thu Jul 20 13:46:57 EDT 2023 +// + +#ifndef __TOP_REGISTER_MAP__ +#define __TOP_REGISTER_MAP__ + +#include + +/* TOP_REGISTERS memory map */ +enum TOP_REGS { + SR1 = 0x0, + WR1 = 0x100, + SR_REPEAT1 = 0x200, + SR_REPEAT2 = 0x204, + SR_REPEAT3 = 0x208, + SRMEM1_0 = 0x2000, + SRMEM1_1 = 0x2004, + SRMEM1_2 = 0x2008, + SRMEM1_3 = 0x200c, + SRMEM1_4 = 0x2010, + SRMEM1_5 = 0x2014, + SRMEM1_6 = 0x2018, + SRMEM1_7 = 0x201c, + SRMEM1_8 = 0x2020, + SRMEM1_9 = 0x2024, + SRMEM1_10 = 0x2028, + SRMEM1_11 = 0x202c, + SRMEM1_12 = 0x2030, + SRMEM1_13 = 0x2034, + SRMEM1_14 = 0x2038, + SRMEM1_15 = 0x203c, + SRMEM1_16 = 0x2040, + SRMEM1_17 = 0x2044, + SRMEM1_18 = 0x2048, + SRMEM1_19 = 0x204c, + SRMEM1_20 = 0x2050, + SRMEM1_21 = 0x2054, + SRMEM1_22 = 0x2058, + SRMEM1_23 = 0x205c, + SRMEM1_24 = 0x2060, + SRMEM1_25 = 0x2064, + SRMEM1_26 = 0x2068, + SRMEM1_27 = 0x206c, + SRMEM1_28 = 0x2070, + SRMEM1_29 = 0x2074, + SRMEM1_30 = 0x2078, + SRMEM1_31 = 0x207c, + SRMEM1_32 = 0x2080, + SRMEM1_33 = 0x2084, + SRMEM1_34 = 0x2088, + SRMEM1_35 = 0x208c, + SRMEM1_36 = 0x2090, + SRMEM1_37 = 0x2094, + SRMEM1_38 = 0x2098, + SRMEM1_39 = 0x209c, + SRMEM1_40 = 0x20a0, + SRMEM1_41 = 0x20a4, + SRMEM1_42 = 0x20a8, + SRMEM1_43 = 0x20ac, + SRMEM1_44 = 0x20b0, + SRMEM1_45 = 0x20b4, + SRMEM1_46 = 0x20b8, + SRMEM1_47 = 0x20bc, + SRMEM1_48 = 0x20c0, + SRMEM1_49 = 0x20c4, + SRMEM1_50 = 0x20c8, + SRMEM1_51 = 0x20cc, + SRMEM1_52 = 0x20d0, + SRMEM1_53 = 0x20d4, + SRMEM1_54 = 0x20d8, + SRMEM1_55 = 0x20dc, + SRMEM1_56 = 0x20e0, + SRMEM1_57 = 0x20e4, + SRMEM1_58 = 0x20e8, + SRMEM1_59 = 0x20ec, + SRMEM1_60 = 0x20f0, + SRMEM1_61 = 0x20f4, + SRMEM1_62 = 0x20f8, + SRMEM1_63 = 0x20fc, + SRMEM1_64 = 0x2100, + SRMEM1_65 = 0x2104, + SRMEM1_66 = 0x2108, + SRMEM1_67 = 0x210c, + SRMEM1_68 = 0x2110, + SRMEM1_69 = 0x2114, + SRMEM1_70 = 0x2118, + SRMEM1_71 = 0x211c, + SRMEM1_72 = 0x2120, + SRMEM1_73 = 0x2124, + SRMEM1_74 = 0x2128, + SRMEM1_75 = 0x212c, + SRMEM1_76 = 0x2130, + SRMEM1_77 = 0x2134, + SRMEM1_78 = 0x2138, + SRMEM1_79 = 0x213c, + SRMEM1_80 = 0x2140, + SRMEM1_81 = 0x2144, + SRMEM1_82 = 0x2148, + SRMEM1_83 = 0x214c, + SRMEM1_84 = 0x2150, + SRMEM1_85 = 0x2154, + SRMEM1_86 = 0x2158, + SRMEM1_87 = 0x215c, + SRMEM1_88 = 0x2160, + SRMEM1_89 = 0x2164, + SRMEM1_90 = 0x2168, + SRMEM1_91 = 0x216c, + SRMEM1_92 = 0x2170, + SRMEM1_93 = 0x2174, + SRMEM1_94 = 0x2178, + SRMEM1_95 = 0x217c, + SRMEM1_96 = 0x2180, + SRMEM1_97 = 0x2184, + SRMEM1_98 = 0x2188, + SRMEM1_99 = 0x218c, + WRMEM1_0 = 0x20000, + WRMEM1_1 = 0x20010, + WRMEM1_2 = 0x20020, + WRMEM1_3 = 0x20030, + WRMEM1_4 = 0x20040, + WRMEM1_5 = 0x20050, + WRMEM1_6 = 0x20060, + WRMEM1_7 = 0x20070, + WRMEM1_8 = 0x20080, + WRMEM1_9 = 0x20090, + WRMEM1_10 = 0x200a0, + WRMEM1_11 = 0x200b0, + WRMEM1_12 = 0x200c0, + WRMEM1_13 = 0x200d0, + WRMEM1_14 = 0x200e0, + WRMEM1_15 = 0x200f0, + WRMEM1_16 = 0x20100, + WRMEM1_17 = 0x20110, + WRMEM1_18 = 0x20120, + WRMEM1_19 = 0x20130, + WRMEM1_20 = 0x20140, + WRMEM1_21 = 0x20150, + WRMEM1_22 = 0x20160, + WRMEM1_23 = 0x20170, + WRMEM1_24 = 0x20180, + WRMEM1_25 = 0x20190, + WRMEM1_26 = 0x201a0, + WRMEM1_27 = 0x201b0, + WRMEM1_28 = 0x201c0, + WRMEM1_29 = 0x201d0, + WRMEM1_30 = 0x201e0, + WRMEM1_31 = 0x201f0, + WRMEM1_32 = 0x20200, + WRMEM1_33 = 0x20210, + WRMEM1_34 = 0x20220, + WRMEM1_35 = 0x20230, + WRMEM1_36 = 0x20240, + WRMEM1_37 = 0x20250, + WRMEM1_38 = 0x20260, + WRMEM1_39 = 0x20270, + WRMEM1_40 = 0x20280, + WRMEM1_41 = 0x20290, + WRMEM1_42 = 0x202a0, + WRMEM1_43 = 0x202b0, + WRMEM1_44 = 0x202c0, + WRMEM1_45 = 0x202d0, + WRMEM1_46 = 0x202e0, + WRMEM1_47 = 0x202f0, + WRMEM1_48 = 0x20300, + WRMEM1_49 = 0x20310, + WRMEM1_50 = 0x20320, + WRMEM1_51 = 0x20330, + WRMEM1_52 = 0x20340, + WRMEM1_53 = 0x20350, + WRMEM1_54 = 0x20360, + WRMEM1_55 = 0x20370, + WRMEM1_56 = 0x20380, + WRMEM1_57 = 0x20390, + WRMEM1_58 = 0x203a0, + WRMEM1_59 = 0x203b0, + WRMEM1_60 = 0x203c0, + WRMEM1_61 = 0x203d0, + WRMEM1_62 = 0x203e0, + WRMEM1_63 = 0x203f0, + WRMEM1_64 = 0x20400, + WRMEM1_65 = 0x20410, + WRMEM1_66 = 0x20420, + WRMEM1_67 = 0x20430, + WRMEM1_68 = 0x20440, + WRMEM1_69 = 0x20450, + WRMEM1_70 = 0x20460, + WRMEM1_71 = 0x20470, + WRMEM1_72 = 0x20480, + WRMEM1_73 = 0x20490, + WRMEM1_74 = 0x204a0, + WRMEM1_75 = 0x204b0, + WRMEM1_76 = 0x204c0, + WRMEM1_77 = 0x204d0, + WRMEM1_78 = 0x204e0, + WRMEM1_79 = 0x204f0, + WRMEM1_80 = 0x20500, + WRMEM1_81 = 0x20510, + WRMEM1_82 = 0x20520, + WRMEM1_83 = 0x20530, + WRMEM1_84 = 0x20540, + WRMEM1_85 = 0x20550, + WRMEM1_86 = 0x20560, + WRMEM1_87 = 0x20570, + WRMEM1_88 = 0x20580, + WRMEM1_89 = 0x20590, + WRMEM1_90 = 0x205a0, + WRMEM1_91 = 0x205b0, + WRMEM1_92 = 0x205c0, + WRMEM1_93 = 0x205d0, + WRMEM1_94 = 0x205e0, + WRMEM1_95 = 0x205f0, + WRMEM1_96 = 0x20600, + WRMEM1_97 = 0x20610, + WRMEM1_98 = 0x20620, + WRMEM1_99 = 0x20630, + WRMEM1_100 = 0x20640, + WRMEM1_101 = 0x20650, + WRMEM1_102 = 0x20660, + WRMEM1_103 = 0x20670, + WRMEM1_104 = 0x20680, + WRMEM1_105 = 0x20690, + WRMEM1_106 = 0x206a0, + WRMEM1_107 = 0x206b0, + WRMEM1_108 = 0x206c0, + WRMEM1_109 = 0x206d0, + WRMEM1_110 = 0x206e0, + WRMEM1_111 = 0x206f0, + WRMEM1_112 = 0x20700, + WRMEM1_113 = 0x20710, + WRMEM1_114 = 0x20720, + WRMEM1_115 = 0x20730, + WRMEM1_116 = 0x20740, + WRMEM1_117 = 0x20750, + WRMEM1_118 = 0x20760, + WRMEM1_119 = 0x20770, + WRMEM1_120 = 0x20780, + WRMEM1_121 = 0x20790, + WRMEM1_122 = 0x207a0, + WRMEM1_123 = 0x207b0, + WRMEM1_124 = 0x207c0, + WRMEM1_125 = 0x207d0, + WRMEM1_126 = 0x207e0, + WRMEM1_127 = 0x207f0, + WRMEM1_128 = 0x20800, + WRMEM1_129 = 0x20810, + WRMEM1_130 = 0x20820, + WRMEM1_131 = 0x20830, + WRMEM1_132 = 0x20840, + WRMEM1_133 = 0x20850, + WRMEM1_134 = 0x20860, + WRMEM1_135 = 0x20870, + WRMEM1_136 = 0x20880, + WRMEM1_137 = 0x20890, + WRMEM1_138 = 0x208a0, + WRMEM1_139 = 0x208b0, + WRMEM1_140 = 0x208c0, + WRMEM1_141 = 0x208d0, + WRMEM1_142 = 0x208e0, + WRMEM1_143 = 0x208f0, + WRMEM1_144 = 0x20900, + WRMEM1_145 = 0x20910, + WRMEM1_146 = 0x20920, + WRMEM1_147 = 0x20930, + WRMEM1_148 = 0x20940, + WRMEM1_149 = 0x20950, + WRMEM1_150 = 0x20960, + WRMEM1_151 = 0x20970, + WRMEM1_152 = 0x20980, + WRMEM1_153 = 0x20990, + WRMEM1_154 = 0x209a0, + WRMEM1_155 = 0x209b0, + WRMEM1_156 = 0x209c0, + WRMEM1_157 = 0x209d0, + WRMEM1_158 = 0x209e0, + WRMEM1_159 = 0x209f0, + WRMEM1_160 = 0x20a00, + WRMEM1_161 = 0x20a10, + WRMEM1_162 = 0x20a20, + WRMEM1_163 = 0x20a30, + WRMEM1_164 = 0x20a40, + WRMEM1_165 = 0x20a50, + WRMEM1_166 = 0x20a60, + WRMEM1_167 = 0x20a70, + WRMEM1_168 = 0x20a80, + WRMEM1_169 = 0x20a90, + WRMEM1_170 = 0x20aa0, + WRMEM1_171 = 0x20ab0, + WRMEM1_172 = 0x20ac0, + WRMEM1_173 = 0x20ad0, + WRMEM1_174 = 0x20ae0, + WRMEM1_175 = 0x20af0, + WRMEM1_176 = 0x20b00, + WRMEM1_177 = 0x20b10, + WRMEM1_178 = 0x20b20, + WRMEM1_179 = 0x20b30, + WRMEM1_180 = 0x20b40, + WRMEM1_181 = 0x20b50, + WRMEM1_182 = 0x20b60, + WRMEM1_183 = 0x20b70, + WRMEM1_184 = 0x20b80, + WRMEM1_185 = 0x20b90, + WRMEM1_186 = 0x20ba0, + WRMEM1_187 = 0x20bb0, + WRMEM1_188 = 0x20bc0, + WRMEM1_189 = 0x20bd0, + WRMEM1_190 = 0x20be0, + WRMEM1_191 = 0x20bf0, + WRMEM1_192 = 0x20c00, + WRMEM1_193 = 0x20c10, + WRMEM1_194 = 0x20c20, + WRMEM1_195 = 0x20c30, + WRMEM1_196 = 0x20c40, + WRMEM1_197 = 0x20c50, + WRMEM1_198 = 0x20c60, + WRMEM1_199 = 0x20c70, + WRMEM1_200 = 0x20c80, + WRMEM1_201 = 0x20c90, + WRMEM1_202 = 0x20ca0, + WRMEM1_203 = 0x20cb0, + WRMEM1_204 = 0x20cc0, + WRMEM1_205 = 0x20cd0, + WRMEM1_206 = 0x20ce0, + WRMEM1_207 = 0x20cf0, + WRMEM1_208 = 0x20d00, + WRMEM1_209 = 0x20d10, + WRMEM1_210 = 0x20d20, + WRMEM1_211 = 0x20d30, + WRMEM1_212 = 0x20d40, + WRMEM1_213 = 0x20d50, + WRMEM1_214 = 0x20d60, + WRMEM1_215 = 0x20d70, + WRMEM1_216 = 0x20d80, + WRMEM1_217 = 0x20d90, + WRMEM1_218 = 0x20da0, + WRMEM1_219 = 0x20db0, + WRMEM1_220 = 0x20dc0, + WRMEM1_221 = 0x20dd0, + WRMEM1_222 = 0x20de0, + WRMEM1_223 = 0x20df0, + WRMEM1_224 = 0x20e00, + WRMEM1_225 = 0x20e10, + WRMEM1_226 = 0x20e20, + WRMEM1_227 = 0x20e30, + WRMEM1_228 = 0x20e40, + WRMEM1_229 = 0x20e50, + WRMEM1_230 = 0x20e60, + WRMEM1_231 = 0x20e70, + WRMEM1_232 = 0x20e80, + WRMEM1_233 = 0x20e90, + WRMEM1_234 = 0x20ea0, + WRMEM1_235 = 0x20eb0, + WRMEM1_236 = 0x20ec0, + WRMEM1_237 = 0x20ed0, + WRMEM1_238 = 0x20ee0, + WRMEM1_239 = 0x20ef0, + WRMEM1_240 = 0x20f00, + WRMEM1_241 = 0x20f10, + WRMEM1_242 = 0x20f20, + WRMEM1_243 = 0x20f30, + WRMEM1_244 = 0x20f40, + WRMEM1_245 = 0x20f50, + WRMEM1_246 = 0x20f60, + WRMEM1_247 = 0x20f70, + WRMEM1_248 = 0x20f80, + WRMEM1_249 = 0x20f90, + WRMEM1_250 = 0x20fa0, + WRMEM1_251 = 0x20fb0, + WRMEM1_252 = 0x20fc0, + WRMEM1_253 = 0x20fd0, + WRMEM1_254 = 0x20fe0, + WRMEM1_255 = 0x20ff0, + WRMEM1_256 = 0x21000, + WRMEM1_257 = 0x21010, + WRMEM1_258 = 0x21020, + WRMEM1_259 = 0x21030, + WRMEM1_260 = 0x21040, + WRMEM1_261 = 0x21050, + WRMEM1_262 = 0x21060, + WRMEM1_263 = 0x21070, + WRMEM1_264 = 0x21080, + WRMEM1_265 = 0x21090, + WRMEM1_266 = 0x210a0, + WRMEM1_267 = 0x210b0, + WRMEM1_268 = 0x210c0, + WRMEM1_269 = 0x210d0, + WRMEM1_270 = 0x210e0, + WRMEM1_271 = 0x210f0, + WRMEM1_272 = 0x21100, + WRMEM1_273 = 0x21110, + WRMEM1_274 = 0x21120, + WRMEM1_275 = 0x21130, + WRMEM1_276 = 0x21140, + WRMEM1_277 = 0x21150, + WRMEM1_278 = 0x21160, + WRMEM1_279 = 0x21170, + WRMEM1_280 = 0x21180, + WRMEM1_281 = 0x21190, + WRMEM1_282 = 0x211a0, + WRMEM1_283 = 0x211b0, + WRMEM1_284 = 0x211c0, + WRMEM1_285 = 0x211d0, + WRMEM1_286 = 0x211e0, + WRMEM1_287 = 0x211f0, + WRMEM1_288 = 0x21200, + WRMEM1_289 = 0x21210, + WRMEM1_290 = 0x21220, + WRMEM1_291 = 0x21230, + WRMEM1_292 = 0x21240, + WRMEM1_293 = 0x21250, + WRMEM1_294 = 0x21260, + WRMEM1_295 = 0x21270, + WRMEM1_296 = 0x21280, + WRMEM1_297 = 0x21290, + WRMEM1_298 = 0x212a0, + WRMEM1_299 = 0x212b0 +}; + +/* SR1 register fields */ +#define SR1_FLD1 GENMASK(31, 0) + +/* WR1 register fields */ +#define WR1_FLD1 GENMASK(15, 0) +#define WR1_FLD2 GENMASK(31, 16) +#define WR1_FLD3 GENMASK(47, 32) +#define WR1_FLD4 GENMASK(63, 48) +#define WR1_FLD5 GENMASK(79, 64) +#define WR1_FLD6 GENMASK(95, 80) +#define WR1_FLD7 GENMASK(111, 96) +#define WR1_FLD8 GENMASK(127, 112) + +/* SR_REPEAT1 register fields */ +#define SR_REPEAT1_FLD1 GENMASK(31, 0) + +/* SR_REPEAT2 register fields */ +#define SR_REPEAT2_FLD1 GENMASK(31, 0) + +/* SR_REPEAT3 register fields */ +#define SR_REPEAT3_FLD1 GENMASK(31, 0) + +/* SRMEM1_0 register fields */ +#define SRMEM1_0_FLD1 GENMASK(31, 0) + +/* SRMEM1_1 register fields */ +#define SRMEM1_1_FLD1 GENMASK(31, 0) + +/* SRMEM1_2 register fields */ +#define SRMEM1_2_FLD1 GENMASK(31, 0) + +/* SRMEM1_3 register fields */ +#define SRMEM1_3_FLD1 GENMASK(31, 0) + +/* SRMEM1_4 register fields */ +#define SRMEM1_4_FLD1 GENMASK(31, 0) + +/* SRMEM1_5 register fields */ +#define SRMEM1_5_FLD1 GENMASK(31, 0) + +/* SRMEM1_6 register fields */ +#define SRMEM1_6_FLD1 GENMASK(31, 0) + +/* SRMEM1_7 register fields */ +#define SRMEM1_7_FLD1 GENMASK(31, 0) + +/* SRMEM1_8 register fields */ +#define SRMEM1_8_FLD1 GENMASK(31, 0) + +/* SRMEM1_9 register fields */ +#define SRMEM1_9_FLD1 GENMASK(31, 0) + +/* SRMEM1_10 register fields */ +#define SRMEM1_10_FLD1 GENMASK(31, 0) + +/* SRMEM1_11 register fields */ +#define SRMEM1_11_FLD1 GENMASK(31, 0) + +/* SRMEM1_12 register fields */ +#define SRMEM1_12_FLD1 GENMASK(31, 0) + +/* SRMEM1_13 register fields */ +#define SRMEM1_13_FLD1 GENMASK(31, 0) + +/* SRMEM1_14 register fields */ +#define SRMEM1_14_FLD1 GENMASK(31, 0) + +/* SRMEM1_15 register fields */ +#define SRMEM1_15_FLD1 GENMASK(31, 0) + +/* SRMEM1_16 register fields */ +#define SRMEM1_16_FLD1 GENMASK(31, 0) + +/* SRMEM1_17 register fields */ +#define SRMEM1_17_FLD1 GENMASK(31, 0) + +/* SRMEM1_18 register fields */ +#define SRMEM1_18_FLD1 GENMASK(31, 0) + +/* SRMEM1_19 register fields */ +#define SRMEM1_19_FLD1 GENMASK(31, 0) + +/* SRMEM1_20 register fields */ +#define SRMEM1_20_FLD1 GENMASK(31, 0) + +/* SRMEM1_21 register fields */ +#define SRMEM1_21_FLD1 GENMASK(31, 0) + +/* SRMEM1_22 register fields */ +#define SRMEM1_22_FLD1 GENMASK(31, 0) + +/* SRMEM1_23 register fields */ +#define SRMEM1_23_FLD1 GENMASK(31, 0) + +/* SRMEM1_24 register fields */ +#define SRMEM1_24_FLD1 GENMASK(31, 0) + +/* SRMEM1_25 register fields */ +#define SRMEM1_25_FLD1 GENMASK(31, 0) + +/* SRMEM1_26 register fields */ +#define SRMEM1_26_FLD1 GENMASK(31, 0) + +/* SRMEM1_27 register fields */ +#define SRMEM1_27_FLD1 GENMASK(31, 0) + +/* SRMEM1_28 register fields */ +#define SRMEM1_28_FLD1 GENMASK(31, 0) + +/* SRMEM1_29 register fields */ +#define SRMEM1_29_FLD1 GENMASK(31, 0) + +/* SRMEM1_30 register fields */ +#define SRMEM1_30_FLD1 GENMASK(31, 0) + +/* SRMEM1_31 register fields */ +#define SRMEM1_31_FLD1 GENMASK(31, 0) + +/* SRMEM1_32 register fields */ +#define SRMEM1_32_FLD1 GENMASK(31, 0) + +/* SRMEM1_33 register fields */ +#define SRMEM1_33_FLD1 GENMASK(31, 0) + +/* SRMEM1_34 register fields */ +#define SRMEM1_34_FLD1 GENMASK(31, 0) + +/* SRMEM1_35 register fields */ +#define SRMEM1_35_FLD1 GENMASK(31, 0) + +/* SRMEM1_36 register fields */ +#define SRMEM1_36_FLD1 GENMASK(31, 0) + +/* SRMEM1_37 register fields */ +#define SRMEM1_37_FLD1 GENMASK(31, 0) + +/* SRMEM1_38 register fields */ +#define SRMEM1_38_FLD1 GENMASK(31, 0) + +/* SRMEM1_39 register fields */ +#define SRMEM1_39_FLD1 GENMASK(31, 0) + +/* SRMEM1_40 register fields */ +#define SRMEM1_40_FLD1 GENMASK(31, 0) + +/* SRMEM1_41 register fields */ +#define SRMEM1_41_FLD1 GENMASK(31, 0) + +/* SRMEM1_42 register fields */ +#define SRMEM1_42_FLD1 GENMASK(31, 0) + +/* SRMEM1_43 register fields */ +#define SRMEM1_43_FLD1 GENMASK(31, 0) + +/* SRMEM1_44 register fields */ +#define SRMEM1_44_FLD1 GENMASK(31, 0) + +/* SRMEM1_45 register fields */ +#define SRMEM1_45_FLD1 GENMASK(31, 0) + +/* SRMEM1_46 register fields */ +#define SRMEM1_46_FLD1 GENMASK(31, 0) + +/* SRMEM1_47 register fields */ +#define SRMEM1_47_FLD1 GENMASK(31, 0) + +/* SRMEM1_48 register fields */ +#define SRMEM1_48_FLD1 GENMASK(31, 0) + +/* SRMEM1_49 register fields */ +#define SRMEM1_49_FLD1 GENMASK(31, 0) + +/* SRMEM1_50 register fields */ +#define SRMEM1_50_FLD1 GENMASK(31, 0) + +/* SRMEM1_51 register fields */ +#define SRMEM1_51_FLD1 GENMASK(31, 0) + +/* SRMEM1_52 register fields */ +#define SRMEM1_52_FLD1 GENMASK(31, 0) + +/* SRMEM1_53 register fields */ +#define SRMEM1_53_FLD1 GENMASK(31, 0) + +/* SRMEM1_54 register fields */ +#define SRMEM1_54_FLD1 GENMASK(31, 0) + +/* SRMEM1_55 register fields */ +#define SRMEM1_55_FLD1 GENMASK(31, 0) + +/* SRMEM1_56 register fields */ +#define SRMEM1_56_FLD1 GENMASK(31, 0) + +/* SRMEM1_57 register fields */ +#define SRMEM1_57_FLD1 GENMASK(31, 0) + +/* SRMEM1_58 register fields */ +#define SRMEM1_58_FLD1 GENMASK(31, 0) + +/* SRMEM1_59 register fields */ +#define SRMEM1_59_FLD1 GENMASK(31, 0) + +/* SRMEM1_60 register fields */ +#define SRMEM1_60_FLD1 GENMASK(31, 0) + +/* SRMEM1_61 register fields */ +#define SRMEM1_61_FLD1 GENMASK(31, 0) + +/* SRMEM1_62 register fields */ +#define SRMEM1_62_FLD1 GENMASK(31, 0) + +/* SRMEM1_63 register fields */ +#define SRMEM1_63_FLD1 GENMASK(31, 0) + +/* SRMEM1_64 register fields */ +#define SRMEM1_64_FLD1 GENMASK(31, 0) + +/* SRMEM1_65 register fields */ +#define SRMEM1_65_FLD1 GENMASK(31, 0) + +/* SRMEM1_66 register fields */ +#define SRMEM1_66_FLD1 GENMASK(31, 0) + +/* SRMEM1_67 register fields */ +#define SRMEM1_67_FLD1 GENMASK(31, 0) + +/* SRMEM1_68 register fields */ +#define SRMEM1_68_FLD1 GENMASK(31, 0) + +/* SRMEM1_69 register fields */ +#define SRMEM1_69_FLD1 GENMASK(31, 0) + +/* SRMEM1_70 register fields */ +#define SRMEM1_70_FLD1 GENMASK(31, 0) + +/* SRMEM1_71 register fields */ +#define SRMEM1_71_FLD1 GENMASK(31, 0) + +/* SRMEM1_72 register fields */ +#define SRMEM1_72_FLD1 GENMASK(31, 0) + +/* SRMEM1_73 register fields */ +#define SRMEM1_73_FLD1 GENMASK(31, 0) + +/* SRMEM1_74 register fields */ +#define SRMEM1_74_FLD1 GENMASK(31, 0) + +/* SRMEM1_75 register fields */ +#define SRMEM1_75_FLD1 GENMASK(31, 0) + +/* SRMEM1_76 register fields */ +#define SRMEM1_76_FLD1 GENMASK(31, 0) + +/* SRMEM1_77 register fields */ +#define SRMEM1_77_FLD1 GENMASK(31, 0) + +/* SRMEM1_78 register fields */ +#define SRMEM1_78_FLD1 GENMASK(31, 0) + +/* SRMEM1_79 register fields */ +#define SRMEM1_79_FLD1 GENMASK(31, 0) + +/* SRMEM1_80 register fields */ +#define SRMEM1_80_FLD1 GENMASK(31, 0) + +/* SRMEM1_81 register fields */ +#define SRMEM1_81_FLD1 GENMASK(31, 0) + +/* SRMEM1_82 register fields */ +#define SRMEM1_82_FLD1 GENMASK(31, 0) + +/* SRMEM1_83 register fields */ +#define SRMEM1_83_FLD1 GENMASK(31, 0) + +/* SRMEM1_84 register fields */ +#define SRMEM1_84_FLD1 GENMASK(31, 0) + +/* SRMEM1_85 register fields */ +#define SRMEM1_85_FLD1 GENMASK(31, 0) + +/* SRMEM1_86 register fields */ +#define SRMEM1_86_FLD1 GENMASK(31, 0) + +/* SRMEM1_87 register fields */ +#define SRMEM1_87_FLD1 GENMASK(31, 0) + +/* SRMEM1_88 register fields */ +#define SRMEM1_88_FLD1 GENMASK(31, 0) + +/* SRMEM1_89 register fields */ +#define SRMEM1_89_FLD1 GENMASK(31, 0) + +/* SRMEM1_90 register fields */ +#define SRMEM1_90_FLD1 GENMASK(31, 0) + +/* SRMEM1_91 register fields */ +#define SRMEM1_91_FLD1 GENMASK(31, 0) + +/* SRMEM1_92 register fields */ +#define SRMEM1_92_FLD1 GENMASK(31, 0) + +/* SRMEM1_93 register fields */ +#define SRMEM1_93_FLD1 GENMASK(31, 0) + +/* SRMEM1_94 register fields */ +#define SRMEM1_94_FLD1 GENMASK(31, 0) + +/* SRMEM1_95 register fields */ +#define SRMEM1_95_FLD1 GENMASK(31, 0) + +/* SRMEM1_96 register fields */ +#define SRMEM1_96_FLD1 GENMASK(31, 0) + +/* SRMEM1_97 register fields */ +#define SRMEM1_97_FLD1 GENMASK(31, 0) + +/* SRMEM1_98 register fields */ +#define SRMEM1_98_FLD1 GENMASK(31, 0) + +/* SRMEM1_99 register fields */ +#define SRMEM1_99_FLD1 GENMASK(31, 0) + +/* WRMEM1_0 register fields */ +#define WRMEM1_0_FLD1 GENMASK(15, 0) +#define WRMEM1_0_FLD2 GENMASK(31, 16) +#define WRMEM1_0_FLD3 GENMASK(47, 32) +#define WRMEM1_0_FLD4 GENMASK(63, 48) +#define WRMEM1_0_FLD5 GENMASK(79, 64) +#define WRMEM1_0_FLD6 GENMASK(95, 80) +#define WRMEM1_0_FLD7 GENMASK(111, 96) +#define WRMEM1_0_FLD8 GENMASK(127, 112) + +/* WRMEM1_1 register fields */ +#define WRMEM1_1_FLD1 GENMASK(15, 0) +#define WRMEM1_1_FLD2 GENMASK(31, 16) +#define WRMEM1_1_FLD3 GENMASK(47, 32) +#define WRMEM1_1_FLD4 GENMASK(63, 48) +#define WRMEM1_1_FLD5 GENMASK(79, 64) +#define WRMEM1_1_FLD6 GENMASK(95, 80) +#define WRMEM1_1_FLD7 GENMASK(111, 96) +#define WRMEM1_1_FLD8 GENMASK(127, 112) + +/* WRMEM1_2 register fields */ +#define WRMEM1_2_FLD1 GENMASK(15, 0) +#define WRMEM1_2_FLD2 GENMASK(31, 16) +#define WRMEM1_2_FLD3 GENMASK(47, 32) +#define WRMEM1_2_FLD4 GENMASK(63, 48) +#define WRMEM1_2_FLD5 GENMASK(79, 64) +#define WRMEM1_2_FLD6 GENMASK(95, 80) +#define WRMEM1_2_FLD7 GENMASK(111, 96) +#define WRMEM1_2_FLD8 GENMASK(127, 112) + +/* WRMEM1_3 register fields */ +#define WRMEM1_3_FLD1 GENMASK(15, 0) +#define WRMEM1_3_FLD2 GENMASK(31, 16) +#define WRMEM1_3_FLD3 GENMASK(47, 32) +#define WRMEM1_3_FLD4 GENMASK(63, 48) +#define WRMEM1_3_FLD5 GENMASK(79, 64) +#define WRMEM1_3_FLD6 GENMASK(95, 80) +#define WRMEM1_3_FLD7 GENMASK(111, 96) +#define WRMEM1_3_FLD8 GENMASK(127, 112) + +/* WRMEM1_4 register fields */ +#define WRMEM1_4_FLD1 GENMASK(15, 0) +#define WRMEM1_4_FLD2 GENMASK(31, 16) +#define WRMEM1_4_FLD3 GENMASK(47, 32) +#define WRMEM1_4_FLD4 GENMASK(63, 48) +#define WRMEM1_4_FLD5 GENMASK(79, 64) +#define WRMEM1_4_FLD6 GENMASK(95, 80) +#define WRMEM1_4_FLD7 GENMASK(111, 96) +#define WRMEM1_4_FLD8 GENMASK(127, 112) + +/* WRMEM1_5 register fields */ +#define WRMEM1_5_FLD1 GENMASK(15, 0) +#define WRMEM1_5_FLD2 GENMASK(31, 16) +#define WRMEM1_5_FLD3 GENMASK(47, 32) +#define WRMEM1_5_FLD4 GENMASK(63, 48) +#define WRMEM1_5_FLD5 GENMASK(79, 64) +#define WRMEM1_5_FLD6 GENMASK(95, 80) +#define WRMEM1_5_FLD7 GENMASK(111, 96) +#define WRMEM1_5_FLD8 GENMASK(127, 112) + +/* WRMEM1_6 register fields */ +#define WRMEM1_6_FLD1 GENMASK(15, 0) +#define WRMEM1_6_FLD2 GENMASK(31, 16) +#define WRMEM1_6_FLD3 GENMASK(47, 32) +#define WRMEM1_6_FLD4 GENMASK(63, 48) +#define WRMEM1_6_FLD5 GENMASK(79, 64) +#define WRMEM1_6_FLD6 GENMASK(95, 80) +#define WRMEM1_6_FLD7 GENMASK(111, 96) +#define WRMEM1_6_FLD8 GENMASK(127, 112) + +/* WRMEM1_7 register fields */ +#define WRMEM1_7_FLD1 GENMASK(15, 0) +#define WRMEM1_7_FLD2 GENMASK(31, 16) +#define WRMEM1_7_FLD3 GENMASK(47, 32) +#define WRMEM1_7_FLD4 GENMASK(63, 48) +#define WRMEM1_7_FLD5 GENMASK(79, 64) +#define WRMEM1_7_FLD6 GENMASK(95, 80) +#define WRMEM1_7_FLD7 GENMASK(111, 96) +#define WRMEM1_7_FLD8 GENMASK(127, 112) + +/* WRMEM1_8 register fields */ +#define WRMEM1_8_FLD1 GENMASK(15, 0) +#define WRMEM1_8_FLD2 GENMASK(31, 16) +#define WRMEM1_8_FLD3 GENMASK(47, 32) +#define WRMEM1_8_FLD4 GENMASK(63, 48) +#define WRMEM1_8_FLD5 GENMASK(79, 64) +#define WRMEM1_8_FLD6 GENMASK(95, 80) +#define WRMEM1_8_FLD7 GENMASK(111, 96) +#define WRMEM1_8_FLD8 GENMASK(127, 112) + +/* WRMEM1_9 register fields */ +#define WRMEM1_9_FLD1 GENMASK(15, 0) +#define WRMEM1_9_FLD2 GENMASK(31, 16) +#define WRMEM1_9_FLD3 GENMASK(47, 32) +#define WRMEM1_9_FLD4 GENMASK(63, 48) +#define WRMEM1_9_FLD5 GENMASK(79, 64) +#define WRMEM1_9_FLD6 GENMASK(95, 80) +#define WRMEM1_9_FLD7 GENMASK(111, 96) +#define WRMEM1_9_FLD8 GENMASK(127, 112) + +/* WRMEM1_10 register fields */ +#define WRMEM1_10_FLD1 GENMASK(15, 0) +#define WRMEM1_10_FLD2 GENMASK(31, 16) +#define WRMEM1_10_FLD3 GENMASK(47, 32) +#define WRMEM1_10_FLD4 GENMASK(63, 48) +#define WRMEM1_10_FLD5 GENMASK(79, 64) +#define WRMEM1_10_FLD6 GENMASK(95, 80) +#define WRMEM1_10_FLD7 GENMASK(111, 96) +#define WRMEM1_10_FLD8 GENMASK(127, 112) + +/* WRMEM1_11 register fields */ +#define WRMEM1_11_FLD1 GENMASK(15, 0) +#define WRMEM1_11_FLD2 GENMASK(31, 16) +#define WRMEM1_11_FLD3 GENMASK(47, 32) +#define WRMEM1_11_FLD4 GENMASK(63, 48) +#define WRMEM1_11_FLD5 GENMASK(79, 64) +#define WRMEM1_11_FLD6 GENMASK(95, 80) +#define WRMEM1_11_FLD7 GENMASK(111, 96) +#define WRMEM1_11_FLD8 GENMASK(127, 112) + +/* WRMEM1_12 register fields */ +#define WRMEM1_12_FLD1 GENMASK(15, 0) +#define WRMEM1_12_FLD2 GENMASK(31, 16) +#define WRMEM1_12_FLD3 GENMASK(47, 32) +#define WRMEM1_12_FLD4 GENMASK(63, 48) +#define WRMEM1_12_FLD5 GENMASK(79, 64) +#define WRMEM1_12_FLD6 GENMASK(95, 80) +#define WRMEM1_12_FLD7 GENMASK(111, 96) +#define WRMEM1_12_FLD8 GENMASK(127, 112) + +/* WRMEM1_13 register fields */ +#define WRMEM1_13_FLD1 GENMASK(15, 0) +#define WRMEM1_13_FLD2 GENMASK(31, 16) +#define WRMEM1_13_FLD3 GENMASK(47, 32) +#define WRMEM1_13_FLD4 GENMASK(63, 48) +#define WRMEM1_13_FLD5 GENMASK(79, 64) +#define WRMEM1_13_FLD6 GENMASK(95, 80) +#define WRMEM1_13_FLD7 GENMASK(111, 96) +#define WRMEM1_13_FLD8 GENMASK(127, 112) + +/* WRMEM1_14 register fields */ +#define WRMEM1_14_FLD1 GENMASK(15, 0) +#define WRMEM1_14_FLD2 GENMASK(31, 16) +#define WRMEM1_14_FLD3 GENMASK(47, 32) +#define WRMEM1_14_FLD4 GENMASK(63, 48) +#define WRMEM1_14_FLD5 GENMASK(79, 64) +#define WRMEM1_14_FLD6 GENMASK(95, 80) +#define WRMEM1_14_FLD7 GENMASK(111, 96) +#define WRMEM1_14_FLD8 GENMASK(127, 112) + +/* WRMEM1_15 register fields */ +#define WRMEM1_15_FLD1 GENMASK(15, 0) +#define WRMEM1_15_FLD2 GENMASK(31, 16) +#define WRMEM1_15_FLD3 GENMASK(47, 32) +#define WRMEM1_15_FLD4 GENMASK(63, 48) +#define WRMEM1_15_FLD5 GENMASK(79, 64) +#define WRMEM1_15_FLD6 GENMASK(95, 80) +#define WRMEM1_15_FLD7 GENMASK(111, 96) +#define WRMEM1_15_FLD8 GENMASK(127, 112) + +/* WRMEM1_16 register fields */ +#define WRMEM1_16_FLD1 GENMASK(15, 0) +#define WRMEM1_16_FLD2 GENMASK(31, 16) +#define WRMEM1_16_FLD3 GENMASK(47, 32) +#define WRMEM1_16_FLD4 GENMASK(63, 48) +#define WRMEM1_16_FLD5 GENMASK(79, 64) +#define WRMEM1_16_FLD6 GENMASK(95, 80) +#define WRMEM1_16_FLD7 GENMASK(111, 96) +#define WRMEM1_16_FLD8 GENMASK(127, 112) + +/* WRMEM1_17 register fields */ +#define WRMEM1_17_FLD1 GENMASK(15, 0) +#define WRMEM1_17_FLD2 GENMASK(31, 16) +#define WRMEM1_17_FLD3 GENMASK(47, 32) +#define WRMEM1_17_FLD4 GENMASK(63, 48) +#define WRMEM1_17_FLD5 GENMASK(79, 64) +#define WRMEM1_17_FLD6 GENMASK(95, 80) +#define WRMEM1_17_FLD7 GENMASK(111, 96) +#define WRMEM1_17_FLD8 GENMASK(127, 112) + +/* WRMEM1_18 register fields */ +#define WRMEM1_18_FLD1 GENMASK(15, 0) +#define WRMEM1_18_FLD2 GENMASK(31, 16) +#define WRMEM1_18_FLD3 GENMASK(47, 32) +#define WRMEM1_18_FLD4 GENMASK(63, 48) +#define WRMEM1_18_FLD5 GENMASK(79, 64) +#define WRMEM1_18_FLD6 GENMASK(95, 80) +#define WRMEM1_18_FLD7 GENMASK(111, 96) +#define WRMEM1_18_FLD8 GENMASK(127, 112) + +/* WRMEM1_19 register fields */ +#define WRMEM1_19_FLD1 GENMASK(15, 0) +#define WRMEM1_19_FLD2 GENMASK(31, 16) +#define WRMEM1_19_FLD3 GENMASK(47, 32) +#define WRMEM1_19_FLD4 GENMASK(63, 48) +#define WRMEM1_19_FLD5 GENMASK(79, 64) +#define WRMEM1_19_FLD6 GENMASK(95, 80) +#define WRMEM1_19_FLD7 GENMASK(111, 96) +#define WRMEM1_19_FLD8 GENMASK(127, 112) + +/* WRMEM1_20 register fields */ +#define WRMEM1_20_FLD1 GENMASK(15, 0) +#define WRMEM1_20_FLD2 GENMASK(31, 16) +#define WRMEM1_20_FLD3 GENMASK(47, 32) +#define WRMEM1_20_FLD4 GENMASK(63, 48) +#define WRMEM1_20_FLD5 GENMASK(79, 64) +#define WRMEM1_20_FLD6 GENMASK(95, 80) +#define WRMEM1_20_FLD7 GENMASK(111, 96) +#define WRMEM1_20_FLD8 GENMASK(127, 112) + +/* WRMEM1_21 register fields */ +#define WRMEM1_21_FLD1 GENMASK(15, 0) +#define WRMEM1_21_FLD2 GENMASK(31, 16) +#define WRMEM1_21_FLD3 GENMASK(47, 32) +#define WRMEM1_21_FLD4 GENMASK(63, 48) +#define WRMEM1_21_FLD5 GENMASK(79, 64) +#define WRMEM1_21_FLD6 GENMASK(95, 80) +#define WRMEM1_21_FLD7 GENMASK(111, 96) +#define WRMEM1_21_FLD8 GENMASK(127, 112) + +/* WRMEM1_22 register fields */ +#define WRMEM1_22_FLD1 GENMASK(15, 0) +#define WRMEM1_22_FLD2 GENMASK(31, 16) +#define WRMEM1_22_FLD3 GENMASK(47, 32) +#define WRMEM1_22_FLD4 GENMASK(63, 48) +#define WRMEM1_22_FLD5 GENMASK(79, 64) +#define WRMEM1_22_FLD6 GENMASK(95, 80) +#define WRMEM1_22_FLD7 GENMASK(111, 96) +#define WRMEM1_22_FLD8 GENMASK(127, 112) + +/* WRMEM1_23 register fields */ +#define WRMEM1_23_FLD1 GENMASK(15, 0) +#define WRMEM1_23_FLD2 GENMASK(31, 16) +#define WRMEM1_23_FLD3 GENMASK(47, 32) +#define WRMEM1_23_FLD4 GENMASK(63, 48) +#define WRMEM1_23_FLD5 GENMASK(79, 64) +#define WRMEM1_23_FLD6 GENMASK(95, 80) +#define WRMEM1_23_FLD7 GENMASK(111, 96) +#define WRMEM1_23_FLD8 GENMASK(127, 112) + +/* WRMEM1_24 register fields */ +#define WRMEM1_24_FLD1 GENMASK(15, 0) +#define WRMEM1_24_FLD2 GENMASK(31, 16) +#define WRMEM1_24_FLD3 GENMASK(47, 32) +#define WRMEM1_24_FLD4 GENMASK(63, 48) +#define WRMEM1_24_FLD5 GENMASK(79, 64) +#define WRMEM1_24_FLD6 GENMASK(95, 80) +#define WRMEM1_24_FLD7 GENMASK(111, 96) +#define WRMEM1_24_FLD8 GENMASK(127, 112) + +/* WRMEM1_25 register fields */ +#define WRMEM1_25_FLD1 GENMASK(15, 0) +#define WRMEM1_25_FLD2 GENMASK(31, 16) +#define WRMEM1_25_FLD3 GENMASK(47, 32) +#define WRMEM1_25_FLD4 GENMASK(63, 48) +#define WRMEM1_25_FLD5 GENMASK(79, 64) +#define WRMEM1_25_FLD6 GENMASK(95, 80) +#define WRMEM1_25_FLD7 GENMASK(111, 96) +#define WRMEM1_25_FLD8 GENMASK(127, 112) + +/* WRMEM1_26 register fields */ +#define WRMEM1_26_FLD1 GENMASK(15, 0) +#define WRMEM1_26_FLD2 GENMASK(31, 16) +#define WRMEM1_26_FLD3 GENMASK(47, 32) +#define WRMEM1_26_FLD4 GENMASK(63, 48) +#define WRMEM1_26_FLD5 GENMASK(79, 64) +#define WRMEM1_26_FLD6 GENMASK(95, 80) +#define WRMEM1_26_FLD7 GENMASK(111, 96) +#define WRMEM1_26_FLD8 GENMASK(127, 112) + +/* WRMEM1_27 register fields */ +#define WRMEM1_27_FLD1 GENMASK(15, 0) +#define WRMEM1_27_FLD2 GENMASK(31, 16) +#define WRMEM1_27_FLD3 GENMASK(47, 32) +#define WRMEM1_27_FLD4 GENMASK(63, 48) +#define WRMEM1_27_FLD5 GENMASK(79, 64) +#define WRMEM1_27_FLD6 GENMASK(95, 80) +#define WRMEM1_27_FLD7 GENMASK(111, 96) +#define WRMEM1_27_FLD8 GENMASK(127, 112) + +/* WRMEM1_28 register fields */ +#define WRMEM1_28_FLD1 GENMASK(15, 0) +#define WRMEM1_28_FLD2 GENMASK(31, 16) +#define WRMEM1_28_FLD3 GENMASK(47, 32) +#define WRMEM1_28_FLD4 GENMASK(63, 48) +#define WRMEM1_28_FLD5 GENMASK(79, 64) +#define WRMEM1_28_FLD6 GENMASK(95, 80) +#define WRMEM1_28_FLD7 GENMASK(111, 96) +#define WRMEM1_28_FLD8 GENMASK(127, 112) + +/* WRMEM1_29 register fields */ +#define WRMEM1_29_FLD1 GENMASK(15, 0) +#define WRMEM1_29_FLD2 GENMASK(31, 16) +#define WRMEM1_29_FLD3 GENMASK(47, 32) +#define WRMEM1_29_FLD4 GENMASK(63, 48) +#define WRMEM1_29_FLD5 GENMASK(79, 64) +#define WRMEM1_29_FLD6 GENMASK(95, 80) +#define WRMEM1_29_FLD7 GENMASK(111, 96) +#define WRMEM1_29_FLD8 GENMASK(127, 112) + +/* WRMEM1_30 register fields */ +#define WRMEM1_30_FLD1 GENMASK(15, 0) +#define WRMEM1_30_FLD2 GENMASK(31, 16) +#define WRMEM1_30_FLD3 GENMASK(47, 32) +#define WRMEM1_30_FLD4 GENMASK(63, 48) +#define WRMEM1_30_FLD5 GENMASK(79, 64) +#define WRMEM1_30_FLD6 GENMASK(95, 80) +#define WRMEM1_30_FLD7 GENMASK(111, 96) +#define WRMEM1_30_FLD8 GENMASK(127, 112) + +/* WRMEM1_31 register fields */ +#define WRMEM1_31_FLD1 GENMASK(15, 0) +#define WRMEM1_31_FLD2 GENMASK(31, 16) +#define WRMEM1_31_FLD3 GENMASK(47, 32) +#define WRMEM1_31_FLD4 GENMASK(63, 48) +#define WRMEM1_31_FLD5 GENMASK(79, 64) +#define WRMEM1_31_FLD6 GENMASK(95, 80) +#define WRMEM1_31_FLD7 GENMASK(111, 96) +#define WRMEM1_31_FLD8 GENMASK(127, 112) + +/* WRMEM1_32 register fields */ +#define WRMEM1_32_FLD1 GENMASK(15, 0) +#define WRMEM1_32_FLD2 GENMASK(31, 16) +#define WRMEM1_32_FLD3 GENMASK(47, 32) +#define WRMEM1_32_FLD4 GENMASK(63, 48) +#define WRMEM1_32_FLD5 GENMASK(79, 64) +#define WRMEM1_32_FLD6 GENMASK(95, 80) +#define WRMEM1_32_FLD7 GENMASK(111, 96) +#define WRMEM1_32_FLD8 GENMASK(127, 112) + +/* WRMEM1_33 register fields */ +#define WRMEM1_33_FLD1 GENMASK(15, 0) +#define WRMEM1_33_FLD2 GENMASK(31, 16) +#define WRMEM1_33_FLD3 GENMASK(47, 32) +#define WRMEM1_33_FLD4 GENMASK(63, 48) +#define WRMEM1_33_FLD5 GENMASK(79, 64) +#define WRMEM1_33_FLD6 GENMASK(95, 80) +#define WRMEM1_33_FLD7 GENMASK(111, 96) +#define WRMEM1_33_FLD8 GENMASK(127, 112) + +/* WRMEM1_34 register fields */ +#define WRMEM1_34_FLD1 GENMASK(15, 0) +#define WRMEM1_34_FLD2 GENMASK(31, 16) +#define WRMEM1_34_FLD3 GENMASK(47, 32) +#define WRMEM1_34_FLD4 GENMASK(63, 48) +#define WRMEM1_34_FLD5 GENMASK(79, 64) +#define WRMEM1_34_FLD6 GENMASK(95, 80) +#define WRMEM1_34_FLD7 GENMASK(111, 96) +#define WRMEM1_34_FLD8 GENMASK(127, 112) + +/* WRMEM1_35 register fields */ +#define WRMEM1_35_FLD1 GENMASK(15, 0) +#define WRMEM1_35_FLD2 GENMASK(31, 16) +#define WRMEM1_35_FLD3 GENMASK(47, 32) +#define WRMEM1_35_FLD4 GENMASK(63, 48) +#define WRMEM1_35_FLD5 GENMASK(79, 64) +#define WRMEM1_35_FLD6 GENMASK(95, 80) +#define WRMEM1_35_FLD7 GENMASK(111, 96) +#define WRMEM1_35_FLD8 GENMASK(127, 112) + +/* WRMEM1_36 register fields */ +#define WRMEM1_36_FLD1 GENMASK(15, 0) +#define WRMEM1_36_FLD2 GENMASK(31, 16) +#define WRMEM1_36_FLD3 GENMASK(47, 32) +#define WRMEM1_36_FLD4 GENMASK(63, 48) +#define WRMEM1_36_FLD5 GENMASK(79, 64) +#define WRMEM1_36_FLD6 GENMASK(95, 80) +#define WRMEM1_36_FLD7 GENMASK(111, 96) +#define WRMEM1_36_FLD8 GENMASK(127, 112) + +/* WRMEM1_37 register fields */ +#define WRMEM1_37_FLD1 GENMASK(15, 0) +#define WRMEM1_37_FLD2 GENMASK(31, 16) +#define WRMEM1_37_FLD3 GENMASK(47, 32) +#define WRMEM1_37_FLD4 GENMASK(63, 48) +#define WRMEM1_37_FLD5 GENMASK(79, 64) +#define WRMEM1_37_FLD6 GENMASK(95, 80) +#define WRMEM1_37_FLD7 GENMASK(111, 96) +#define WRMEM1_37_FLD8 GENMASK(127, 112) + +/* WRMEM1_38 register fields */ +#define WRMEM1_38_FLD1 GENMASK(15, 0) +#define WRMEM1_38_FLD2 GENMASK(31, 16) +#define WRMEM1_38_FLD3 GENMASK(47, 32) +#define WRMEM1_38_FLD4 GENMASK(63, 48) +#define WRMEM1_38_FLD5 GENMASK(79, 64) +#define WRMEM1_38_FLD6 GENMASK(95, 80) +#define WRMEM1_38_FLD7 GENMASK(111, 96) +#define WRMEM1_38_FLD8 GENMASK(127, 112) + +/* WRMEM1_39 register fields */ +#define WRMEM1_39_FLD1 GENMASK(15, 0) +#define WRMEM1_39_FLD2 GENMASK(31, 16) +#define WRMEM1_39_FLD3 GENMASK(47, 32) +#define WRMEM1_39_FLD4 GENMASK(63, 48) +#define WRMEM1_39_FLD5 GENMASK(79, 64) +#define WRMEM1_39_FLD6 GENMASK(95, 80) +#define WRMEM1_39_FLD7 GENMASK(111, 96) +#define WRMEM1_39_FLD8 GENMASK(127, 112) + +/* WRMEM1_40 register fields */ +#define WRMEM1_40_FLD1 GENMASK(15, 0) +#define WRMEM1_40_FLD2 GENMASK(31, 16) +#define WRMEM1_40_FLD3 GENMASK(47, 32) +#define WRMEM1_40_FLD4 GENMASK(63, 48) +#define WRMEM1_40_FLD5 GENMASK(79, 64) +#define WRMEM1_40_FLD6 GENMASK(95, 80) +#define WRMEM1_40_FLD7 GENMASK(111, 96) +#define WRMEM1_40_FLD8 GENMASK(127, 112) + +/* WRMEM1_41 register fields */ +#define WRMEM1_41_FLD1 GENMASK(15, 0) +#define WRMEM1_41_FLD2 GENMASK(31, 16) +#define WRMEM1_41_FLD3 GENMASK(47, 32) +#define WRMEM1_41_FLD4 GENMASK(63, 48) +#define WRMEM1_41_FLD5 GENMASK(79, 64) +#define WRMEM1_41_FLD6 GENMASK(95, 80) +#define WRMEM1_41_FLD7 GENMASK(111, 96) +#define WRMEM1_41_FLD8 GENMASK(127, 112) + +/* WRMEM1_42 register fields */ +#define WRMEM1_42_FLD1 GENMASK(15, 0) +#define WRMEM1_42_FLD2 GENMASK(31, 16) +#define WRMEM1_42_FLD3 GENMASK(47, 32) +#define WRMEM1_42_FLD4 GENMASK(63, 48) +#define WRMEM1_42_FLD5 GENMASK(79, 64) +#define WRMEM1_42_FLD6 GENMASK(95, 80) +#define WRMEM1_42_FLD7 GENMASK(111, 96) +#define WRMEM1_42_FLD8 GENMASK(127, 112) + +/* WRMEM1_43 register fields */ +#define WRMEM1_43_FLD1 GENMASK(15, 0) +#define WRMEM1_43_FLD2 GENMASK(31, 16) +#define WRMEM1_43_FLD3 GENMASK(47, 32) +#define WRMEM1_43_FLD4 GENMASK(63, 48) +#define WRMEM1_43_FLD5 GENMASK(79, 64) +#define WRMEM1_43_FLD6 GENMASK(95, 80) +#define WRMEM1_43_FLD7 GENMASK(111, 96) +#define WRMEM1_43_FLD8 GENMASK(127, 112) + +/* WRMEM1_44 register fields */ +#define WRMEM1_44_FLD1 GENMASK(15, 0) +#define WRMEM1_44_FLD2 GENMASK(31, 16) +#define WRMEM1_44_FLD3 GENMASK(47, 32) +#define WRMEM1_44_FLD4 GENMASK(63, 48) +#define WRMEM1_44_FLD5 GENMASK(79, 64) +#define WRMEM1_44_FLD6 GENMASK(95, 80) +#define WRMEM1_44_FLD7 GENMASK(111, 96) +#define WRMEM1_44_FLD8 GENMASK(127, 112) + +/* WRMEM1_45 register fields */ +#define WRMEM1_45_FLD1 GENMASK(15, 0) +#define WRMEM1_45_FLD2 GENMASK(31, 16) +#define WRMEM1_45_FLD3 GENMASK(47, 32) +#define WRMEM1_45_FLD4 GENMASK(63, 48) +#define WRMEM1_45_FLD5 GENMASK(79, 64) +#define WRMEM1_45_FLD6 GENMASK(95, 80) +#define WRMEM1_45_FLD7 GENMASK(111, 96) +#define WRMEM1_45_FLD8 GENMASK(127, 112) + +/* WRMEM1_46 register fields */ +#define WRMEM1_46_FLD1 GENMASK(15, 0) +#define WRMEM1_46_FLD2 GENMASK(31, 16) +#define WRMEM1_46_FLD3 GENMASK(47, 32) +#define WRMEM1_46_FLD4 GENMASK(63, 48) +#define WRMEM1_46_FLD5 GENMASK(79, 64) +#define WRMEM1_46_FLD6 GENMASK(95, 80) +#define WRMEM1_46_FLD7 GENMASK(111, 96) +#define WRMEM1_46_FLD8 GENMASK(127, 112) + +/* WRMEM1_47 register fields */ +#define WRMEM1_47_FLD1 GENMASK(15, 0) +#define WRMEM1_47_FLD2 GENMASK(31, 16) +#define WRMEM1_47_FLD3 GENMASK(47, 32) +#define WRMEM1_47_FLD4 GENMASK(63, 48) +#define WRMEM1_47_FLD5 GENMASK(79, 64) +#define WRMEM1_47_FLD6 GENMASK(95, 80) +#define WRMEM1_47_FLD7 GENMASK(111, 96) +#define WRMEM1_47_FLD8 GENMASK(127, 112) + +/* WRMEM1_48 register fields */ +#define WRMEM1_48_FLD1 GENMASK(15, 0) +#define WRMEM1_48_FLD2 GENMASK(31, 16) +#define WRMEM1_48_FLD3 GENMASK(47, 32) +#define WRMEM1_48_FLD4 GENMASK(63, 48) +#define WRMEM1_48_FLD5 GENMASK(79, 64) +#define WRMEM1_48_FLD6 GENMASK(95, 80) +#define WRMEM1_48_FLD7 GENMASK(111, 96) +#define WRMEM1_48_FLD8 GENMASK(127, 112) + +/* WRMEM1_49 register fields */ +#define WRMEM1_49_FLD1 GENMASK(15, 0) +#define WRMEM1_49_FLD2 GENMASK(31, 16) +#define WRMEM1_49_FLD3 GENMASK(47, 32) +#define WRMEM1_49_FLD4 GENMASK(63, 48) +#define WRMEM1_49_FLD5 GENMASK(79, 64) +#define WRMEM1_49_FLD6 GENMASK(95, 80) +#define WRMEM1_49_FLD7 GENMASK(111, 96) +#define WRMEM1_49_FLD8 GENMASK(127, 112) + +/* WRMEM1_50 register fields */ +#define WRMEM1_50_FLD1 GENMASK(15, 0) +#define WRMEM1_50_FLD2 GENMASK(31, 16) +#define WRMEM1_50_FLD3 GENMASK(47, 32) +#define WRMEM1_50_FLD4 GENMASK(63, 48) +#define WRMEM1_50_FLD5 GENMASK(79, 64) +#define WRMEM1_50_FLD6 GENMASK(95, 80) +#define WRMEM1_50_FLD7 GENMASK(111, 96) +#define WRMEM1_50_FLD8 GENMASK(127, 112) + +/* WRMEM1_51 register fields */ +#define WRMEM1_51_FLD1 GENMASK(15, 0) +#define WRMEM1_51_FLD2 GENMASK(31, 16) +#define WRMEM1_51_FLD3 GENMASK(47, 32) +#define WRMEM1_51_FLD4 GENMASK(63, 48) +#define WRMEM1_51_FLD5 GENMASK(79, 64) +#define WRMEM1_51_FLD6 GENMASK(95, 80) +#define WRMEM1_51_FLD7 GENMASK(111, 96) +#define WRMEM1_51_FLD8 GENMASK(127, 112) + +/* WRMEM1_52 register fields */ +#define WRMEM1_52_FLD1 GENMASK(15, 0) +#define WRMEM1_52_FLD2 GENMASK(31, 16) +#define WRMEM1_52_FLD3 GENMASK(47, 32) +#define WRMEM1_52_FLD4 GENMASK(63, 48) +#define WRMEM1_52_FLD5 GENMASK(79, 64) +#define WRMEM1_52_FLD6 GENMASK(95, 80) +#define WRMEM1_52_FLD7 GENMASK(111, 96) +#define WRMEM1_52_FLD8 GENMASK(127, 112) + +/* WRMEM1_53 register fields */ +#define WRMEM1_53_FLD1 GENMASK(15, 0) +#define WRMEM1_53_FLD2 GENMASK(31, 16) +#define WRMEM1_53_FLD3 GENMASK(47, 32) +#define WRMEM1_53_FLD4 GENMASK(63, 48) +#define WRMEM1_53_FLD5 GENMASK(79, 64) +#define WRMEM1_53_FLD6 GENMASK(95, 80) +#define WRMEM1_53_FLD7 GENMASK(111, 96) +#define WRMEM1_53_FLD8 GENMASK(127, 112) + +/* WRMEM1_54 register fields */ +#define WRMEM1_54_FLD1 GENMASK(15, 0) +#define WRMEM1_54_FLD2 GENMASK(31, 16) +#define WRMEM1_54_FLD3 GENMASK(47, 32) +#define WRMEM1_54_FLD4 GENMASK(63, 48) +#define WRMEM1_54_FLD5 GENMASK(79, 64) +#define WRMEM1_54_FLD6 GENMASK(95, 80) +#define WRMEM1_54_FLD7 GENMASK(111, 96) +#define WRMEM1_54_FLD8 GENMASK(127, 112) + +/* WRMEM1_55 register fields */ +#define WRMEM1_55_FLD1 GENMASK(15, 0) +#define WRMEM1_55_FLD2 GENMASK(31, 16) +#define WRMEM1_55_FLD3 GENMASK(47, 32) +#define WRMEM1_55_FLD4 GENMASK(63, 48) +#define WRMEM1_55_FLD5 GENMASK(79, 64) +#define WRMEM1_55_FLD6 GENMASK(95, 80) +#define WRMEM1_55_FLD7 GENMASK(111, 96) +#define WRMEM1_55_FLD8 GENMASK(127, 112) + +/* WRMEM1_56 register fields */ +#define WRMEM1_56_FLD1 GENMASK(15, 0) +#define WRMEM1_56_FLD2 GENMASK(31, 16) +#define WRMEM1_56_FLD3 GENMASK(47, 32) +#define WRMEM1_56_FLD4 GENMASK(63, 48) +#define WRMEM1_56_FLD5 GENMASK(79, 64) +#define WRMEM1_56_FLD6 GENMASK(95, 80) +#define WRMEM1_56_FLD7 GENMASK(111, 96) +#define WRMEM1_56_FLD8 GENMASK(127, 112) + +/* WRMEM1_57 register fields */ +#define WRMEM1_57_FLD1 GENMASK(15, 0) +#define WRMEM1_57_FLD2 GENMASK(31, 16) +#define WRMEM1_57_FLD3 GENMASK(47, 32) +#define WRMEM1_57_FLD4 GENMASK(63, 48) +#define WRMEM1_57_FLD5 GENMASK(79, 64) +#define WRMEM1_57_FLD6 GENMASK(95, 80) +#define WRMEM1_57_FLD7 GENMASK(111, 96) +#define WRMEM1_57_FLD8 GENMASK(127, 112) + +/* WRMEM1_58 register fields */ +#define WRMEM1_58_FLD1 GENMASK(15, 0) +#define WRMEM1_58_FLD2 GENMASK(31, 16) +#define WRMEM1_58_FLD3 GENMASK(47, 32) +#define WRMEM1_58_FLD4 GENMASK(63, 48) +#define WRMEM1_58_FLD5 GENMASK(79, 64) +#define WRMEM1_58_FLD6 GENMASK(95, 80) +#define WRMEM1_58_FLD7 GENMASK(111, 96) +#define WRMEM1_58_FLD8 GENMASK(127, 112) + +/* WRMEM1_59 register fields */ +#define WRMEM1_59_FLD1 GENMASK(15, 0) +#define WRMEM1_59_FLD2 GENMASK(31, 16) +#define WRMEM1_59_FLD3 GENMASK(47, 32) +#define WRMEM1_59_FLD4 GENMASK(63, 48) +#define WRMEM1_59_FLD5 GENMASK(79, 64) +#define WRMEM1_59_FLD6 GENMASK(95, 80) +#define WRMEM1_59_FLD7 GENMASK(111, 96) +#define WRMEM1_59_FLD8 GENMASK(127, 112) + +/* WRMEM1_60 register fields */ +#define WRMEM1_60_FLD1 GENMASK(15, 0) +#define WRMEM1_60_FLD2 GENMASK(31, 16) +#define WRMEM1_60_FLD3 GENMASK(47, 32) +#define WRMEM1_60_FLD4 GENMASK(63, 48) +#define WRMEM1_60_FLD5 GENMASK(79, 64) +#define WRMEM1_60_FLD6 GENMASK(95, 80) +#define WRMEM1_60_FLD7 GENMASK(111, 96) +#define WRMEM1_60_FLD8 GENMASK(127, 112) + +/* WRMEM1_61 register fields */ +#define WRMEM1_61_FLD1 GENMASK(15, 0) +#define WRMEM1_61_FLD2 GENMASK(31, 16) +#define WRMEM1_61_FLD3 GENMASK(47, 32) +#define WRMEM1_61_FLD4 GENMASK(63, 48) +#define WRMEM1_61_FLD5 GENMASK(79, 64) +#define WRMEM1_61_FLD6 GENMASK(95, 80) +#define WRMEM1_61_FLD7 GENMASK(111, 96) +#define WRMEM1_61_FLD8 GENMASK(127, 112) + +/* WRMEM1_62 register fields */ +#define WRMEM1_62_FLD1 GENMASK(15, 0) +#define WRMEM1_62_FLD2 GENMASK(31, 16) +#define WRMEM1_62_FLD3 GENMASK(47, 32) +#define WRMEM1_62_FLD4 GENMASK(63, 48) +#define WRMEM1_62_FLD5 GENMASK(79, 64) +#define WRMEM1_62_FLD6 GENMASK(95, 80) +#define WRMEM1_62_FLD7 GENMASK(111, 96) +#define WRMEM1_62_FLD8 GENMASK(127, 112) + +/* WRMEM1_63 register fields */ +#define WRMEM1_63_FLD1 GENMASK(15, 0) +#define WRMEM1_63_FLD2 GENMASK(31, 16) +#define WRMEM1_63_FLD3 GENMASK(47, 32) +#define WRMEM1_63_FLD4 GENMASK(63, 48) +#define WRMEM1_63_FLD5 GENMASK(79, 64) +#define WRMEM1_63_FLD6 GENMASK(95, 80) +#define WRMEM1_63_FLD7 GENMASK(111, 96) +#define WRMEM1_63_FLD8 GENMASK(127, 112) + +/* WRMEM1_64 register fields */ +#define WRMEM1_64_FLD1 GENMASK(15, 0) +#define WRMEM1_64_FLD2 GENMASK(31, 16) +#define WRMEM1_64_FLD3 GENMASK(47, 32) +#define WRMEM1_64_FLD4 GENMASK(63, 48) +#define WRMEM1_64_FLD5 GENMASK(79, 64) +#define WRMEM1_64_FLD6 GENMASK(95, 80) +#define WRMEM1_64_FLD7 GENMASK(111, 96) +#define WRMEM1_64_FLD8 GENMASK(127, 112) + +/* WRMEM1_65 register fields */ +#define WRMEM1_65_FLD1 GENMASK(15, 0) +#define WRMEM1_65_FLD2 GENMASK(31, 16) +#define WRMEM1_65_FLD3 GENMASK(47, 32) +#define WRMEM1_65_FLD4 GENMASK(63, 48) +#define WRMEM1_65_FLD5 GENMASK(79, 64) +#define WRMEM1_65_FLD6 GENMASK(95, 80) +#define WRMEM1_65_FLD7 GENMASK(111, 96) +#define WRMEM1_65_FLD8 GENMASK(127, 112) + +/* WRMEM1_66 register fields */ +#define WRMEM1_66_FLD1 GENMASK(15, 0) +#define WRMEM1_66_FLD2 GENMASK(31, 16) +#define WRMEM1_66_FLD3 GENMASK(47, 32) +#define WRMEM1_66_FLD4 GENMASK(63, 48) +#define WRMEM1_66_FLD5 GENMASK(79, 64) +#define WRMEM1_66_FLD6 GENMASK(95, 80) +#define WRMEM1_66_FLD7 GENMASK(111, 96) +#define WRMEM1_66_FLD8 GENMASK(127, 112) + +/* WRMEM1_67 register fields */ +#define WRMEM1_67_FLD1 GENMASK(15, 0) +#define WRMEM1_67_FLD2 GENMASK(31, 16) +#define WRMEM1_67_FLD3 GENMASK(47, 32) +#define WRMEM1_67_FLD4 GENMASK(63, 48) +#define WRMEM1_67_FLD5 GENMASK(79, 64) +#define WRMEM1_67_FLD6 GENMASK(95, 80) +#define WRMEM1_67_FLD7 GENMASK(111, 96) +#define WRMEM1_67_FLD8 GENMASK(127, 112) + +/* WRMEM1_68 register fields */ +#define WRMEM1_68_FLD1 GENMASK(15, 0) +#define WRMEM1_68_FLD2 GENMASK(31, 16) +#define WRMEM1_68_FLD3 GENMASK(47, 32) +#define WRMEM1_68_FLD4 GENMASK(63, 48) +#define WRMEM1_68_FLD5 GENMASK(79, 64) +#define WRMEM1_68_FLD6 GENMASK(95, 80) +#define WRMEM1_68_FLD7 GENMASK(111, 96) +#define WRMEM1_68_FLD8 GENMASK(127, 112) + +/* WRMEM1_69 register fields */ +#define WRMEM1_69_FLD1 GENMASK(15, 0) +#define WRMEM1_69_FLD2 GENMASK(31, 16) +#define WRMEM1_69_FLD3 GENMASK(47, 32) +#define WRMEM1_69_FLD4 GENMASK(63, 48) +#define WRMEM1_69_FLD5 GENMASK(79, 64) +#define WRMEM1_69_FLD6 GENMASK(95, 80) +#define WRMEM1_69_FLD7 GENMASK(111, 96) +#define WRMEM1_69_FLD8 GENMASK(127, 112) + +/* WRMEM1_70 register fields */ +#define WRMEM1_70_FLD1 GENMASK(15, 0) +#define WRMEM1_70_FLD2 GENMASK(31, 16) +#define WRMEM1_70_FLD3 GENMASK(47, 32) +#define WRMEM1_70_FLD4 GENMASK(63, 48) +#define WRMEM1_70_FLD5 GENMASK(79, 64) +#define WRMEM1_70_FLD6 GENMASK(95, 80) +#define WRMEM1_70_FLD7 GENMASK(111, 96) +#define WRMEM1_70_FLD8 GENMASK(127, 112) + +/* WRMEM1_71 register fields */ +#define WRMEM1_71_FLD1 GENMASK(15, 0) +#define WRMEM1_71_FLD2 GENMASK(31, 16) +#define WRMEM1_71_FLD3 GENMASK(47, 32) +#define WRMEM1_71_FLD4 GENMASK(63, 48) +#define WRMEM1_71_FLD5 GENMASK(79, 64) +#define WRMEM1_71_FLD6 GENMASK(95, 80) +#define WRMEM1_71_FLD7 GENMASK(111, 96) +#define WRMEM1_71_FLD8 GENMASK(127, 112) + +/* WRMEM1_72 register fields */ +#define WRMEM1_72_FLD1 GENMASK(15, 0) +#define WRMEM1_72_FLD2 GENMASK(31, 16) +#define WRMEM1_72_FLD3 GENMASK(47, 32) +#define WRMEM1_72_FLD4 GENMASK(63, 48) +#define WRMEM1_72_FLD5 GENMASK(79, 64) +#define WRMEM1_72_FLD6 GENMASK(95, 80) +#define WRMEM1_72_FLD7 GENMASK(111, 96) +#define WRMEM1_72_FLD8 GENMASK(127, 112) + +/* WRMEM1_73 register fields */ +#define WRMEM1_73_FLD1 GENMASK(15, 0) +#define WRMEM1_73_FLD2 GENMASK(31, 16) +#define WRMEM1_73_FLD3 GENMASK(47, 32) +#define WRMEM1_73_FLD4 GENMASK(63, 48) +#define WRMEM1_73_FLD5 GENMASK(79, 64) +#define WRMEM1_73_FLD6 GENMASK(95, 80) +#define WRMEM1_73_FLD7 GENMASK(111, 96) +#define WRMEM1_73_FLD8 GENMASK(127, 112) + +/* WRMEM1_74 register fields */ +#define WRMEM1_74_FLD1 GENMASK(15, 0) +#define WRMEM1_74_FLD2 GENMASK(31, 16) +#define WRMEM1_74_FLD3 GENMASK(47, 32) +#define WRMEM1_74_FLD4 GENMASK(63, 48) +#define WRMEM1_74_FLD5 GENMASK(79, 64) +#define WRMEM1_74_FLD6 GENMASK(95, 80) +#define WRMEM1_74_FLD7 GENMASK(111, 96) +#define WRMEM1_74_FLD8 GENMASK(127, 112) + +/* WRMEM1_75 register fields */ +#define WRMEM1_75_FLD1 GENMASK(15, 0) +#define WRMEM1_75_FLD2 GENMASK(31, 16) +#define WRMEM1_75_FLD3 GENMASK(47, 32) +#define WRMEM1_75_FLD4 GENMASK(63, 48) +#define WRMEM1_75_FLD5 GENMASK(79, 64) +#define WRMEM1_75_FLD6 GENMASK(95, 80) +#define WRMEM1_75_FLD7 GENMASK(111, 96) +#define WRMEM1_75_FLD8 GENMASK(127, 112) + +/* WRMEM1_76 register fields */ +#define WRMEM1_76_FLD1 GENMASK(15, 0) +#define WRMEM1_76_FLD2 GENMASK(31, 16) +#define WRMEM1_76_FLD3 GENMASK(47, 32) +#define WRMEM1_76_FLD4 GENMASK(63, 48) +#define WRMEM1_76_FLD5 GENMASK(79, 64) +#define WRMEM1_76_FLD6 GENMASK(95, 80) +#define WRMEM1_76_FLD7 GENMASK(111, 96) +#define WRMEM1_76_FLD8 GENMASK(127, 112) + +/* WRMEM1_77 register fields */ +#define WRMEM1_77_FLD1 GENMASK(15, 0) +#define WRMEM1_77_FLD2 GENMASK(31, 16) +#define WRMEM1_77_FLD3 GENMASK(47, 32) +#define WRMEM1_77_FLD4 GENMASK(63, 48) +#define WRMEM1_77_FLD5 GENMASK(79, 64) +#define WRMEM1_77_FLD6 GENMASK(95, 80) +#define WRMEM1_77_FLD7 GENMASK(111, 96) +#define WRMEM1_77_FLD8 GENMASK(127, 112) + +/* WRMEM1_78 register fields */ +#define WRMEM1_78_FLD1 GENMASK(15, 0) +#define WRMEM1_78_FLD2 GENMASK(31, 16) +#define WRMEM1_78_FLD3 GENMASK(47, 32) +#define WRMEM1_78_FLD4 GENMASK(63, 48) +#define WRMEM1_78_FLD5 GENMASK(79, 64) +#define WRMEM1_78_FLD6 GENMASK(95, 80) +#define WRMEM1_78_FLD7 GENMASK(111, 96) +#define WRMEM1_78_FLD8 GENMASK(127, 112) + +/* WRMEM1_79 register fields */ +#define WRMEM1_79_FLD1 GENMASK(15, 0) +#define WRMEM1_79_FLD2 GENMASK(31, 16) +#define WRMEM1_79_FLD3 GENMASK(47, 32) +#define WRMEM1_79_FLD4 GENMASK(63, 48) +#define WRMEM1_79_FLD5 GENMASK(79, 64) +#define WRMEM1_79_FLD6 GENMASK(95, 80) +#define WRMEM1_79_FLD7 GENMASK(111, 96) +#define WRMEM1_79_FLD8 GENMASK(127, 112) + +/* WRMEM1_80 register fields */ +#define WRMEM1_80_FLD1 GENMASK(15, 0) +#define WRMEM1_80_FLD2 GENMASK(31, 16) +#define WRMEM1_80_FLD3 GENMASK(47, 32) +#define WRMEM1_80_FLD4 GENMASK(63, 48) +#define WRMEM1_80_FLD5 GENMASK(79, 64) +#define WRMEM1_80_FLD6 GENMASK(95, 80) +#define WRMEM1_80_FLD7 GENMASK(111, 96) +#define WRMEM1_80_FLD8 GENMASK(127, 112) + +/* WRMEM1_81 register fields */ +#define WRMEM1_81_FLD1 GENMASK(15, 0) +#define WRMEM1_81_FLD2 GENMASK(31, 16) +#define WRMEM1_81_FLD3 GENMASK(47, 32) +#define WRMEM1_81_FLD4 GENMASK(63, 48) +#define WRMEM1_81_FLD5 GENMASK(79, 64) +#define WRMEM1_81_FLD6 GENMASK(95, 80) +#define WRMEM1_81_FLD7 GENMASK(111, 96) +#define WRMEM1_81_FLD8 GENMASK(127, 112) + +/* WRMEM1_82 register fields */ +#define WRMEM1_82_FLD1 GENMASK(15, 0) +#define WRMEM1_82_FLD2 GENMASK(31, 16) +#define WRMEM1_82_FLD3 GENMASK(47, 32) +#define WRMEM1_82_FLD4 GENMASK(63, 48) +#define WRMEM1_82_FLD5 GENMASK(79, 64) +#define WRMEM1_82_FLD6 GENMASK(95, 80) +#define WRMEM1_82_FLD7 GENMASK(111, 96) +#define WRMEM1_82_FLD8 GENMASK(127, 112) + +/* WRMEM1_83 register fields */ +#define WRMEM1_83_FLD1 GENMASK(15, 0) +#define WRMEM1_83_FLD2 GENMASK(31, 16) +#define WRMEM1_83_FLD3 GENMASK(47, 32) +#define WRMEM1_83_FLD4 GENMASK(63, 48) +#define WRMEM1_83_FLD5 GENMASK(79, 64) +#define WRMEM1_83_FLD6 GENMASK(95, 80) +#define WRMEM1_83_FLD7 GENMASK(111, 96) +#define WRMEM1_83_FLD8 GENMASK(127, 112) + +/* WRMEM1_84 register fields */ +#define WRMEM1_84_FLD1 GENMASK(15, 0) +#define WRMEM1_84_FLD2 GENMASK(31, 16) +#define WRMEM1_84_FLD3 GENMASK(47, 32) +#define WRMEM1_84_FLD4 GENMASK(63, 48) +#define WRMEM1_84_FLD5 GENMASK(79, 64) +#define WRMEM1_84_FLD6 GENMASK(95, 80) +#define WRMEM1_84_FLD7 GENMASK(111, 96) +#define WRMEM1_84_FLD8 GENMASK(127, 112) + +/* WRMEM1_85 register fields */ +#define WRMEM1_85_FLD1 GENMASK(15, 0) +#define WRMEM1_85_FLD2 GENMASK(31, 16) +#define WRMEM1_85_FLD3 GENMASK(47, 32) +#define WRMEM1_85_FLD4 GENMASK(63, 48) +#define WRMEM1_85_FLD5 GENMASK(79, 64) +#define WRMEM1_85_FLD6 GENMASK(95, 80) +#define WRMEM1_85_FLD7 GENMASK(111, 96) +#define WRMEM1_85_FLD8 GENMASK(127, 112) + +/* WRMEM1_86 register fields */ +#define WRMEM1_86_FLD1 GENMASK(15, 0) +#define WRMEM1_86_FLD2 GENMASK(31, 16) +#define WRMEM1_86_FLD3 GENMASK(47, 32) +#define WRMEM1_86_FLD4 GENMASK(63, 48) +#define WRMEM1_86_FLD5 GENMASK(79, 64) +#define WRMEM1_86_FLD6 GENMASK(95, 80) +#define WRMEM1_86_FLD7 GENMASK(111, 96) +#define WRMEM1_86_FLD8 GENMASK(127, 112) + +/* WRMEM1_87 register fields */ +#define WRMEM1_87_FLD1 GENMASK(15, 0) +#define WRMEM1_87_FLD2 GENMASK(31, 16) +#define WRMEM1_87_FLD3 GENMASK(47, 32) +#define WRMEM1_87_FLD4 GENMASK(63, 48) +#define WRMEM1_87_FLD5 GENMASK(79, 64) +#define WRMEM1_87_FLD6 GENMASK(95, 80) +#define WRMEM1_87_FLD7 GENMASK(111, 96) +#define WRMEM1_87_FLD8 GENMASK(127, 112) + +/* WRMEM1_88 register fields */ +#define WRMEM1_88_FLD1 GENMASK(15, 0) +#define WRMEM1_88_FLD2 GENMASK(31, 16) +#define WRMEM1_88_FLD3 GENMASK(47, 32) +#define WRMEM1_88_FLD4 GENMASK(63, 48) +#define WRMEM1_88_FLD5 GENMASK(79, 64) +#define WRMEM1_88_FLD6 GENMASK(95, 80) +#define WRMEM1_88_FLD7 GENMASK(111, 96) +#define WRMEM1_88_FLD8 GENMASK(127, 112) + +/* WRMEM1_89 register fields */ +#define WRMEM1_89_FLD1 GENMASK(15, 0) +#define WRMEM1_89_FLD2 GENMASK(31, 16) +#define WRMEM1_89_FLD3 GENMASK(47, 32) +#define WRMEM1_89_FLD4 GENMASK(63, 48) +#define WRMEM1_89_FLD5 GENMASK(79, 64) +#define WRMEM1_89_FLD6 GENMASK(95, 80) +#define WRMEM1_89_FLD7 GENMASK(111, 96) +#define WRMEM1_89_FLD8 GENMASK(127, 112) + +/* WRMEM1_90 register fields */ +#define WRMEM1_90_FLD1 GENMASK(15, 0) +#define WRMEM1_90_FLD2 GENMASK(31, 16) +#define WRMEM1_90_FLD3 GENMASK(47, 32) +#define WRMEM1_90_FLD4 GENMASK(63, 48) +#define WRMEM1_90_FLD5 GENMASK(79, 64) +#define WRMEM1_90_FLD6 GENMASK(95, 80) +#define WRMEM1_90_FLD7 GENMASK(111, 96) +#define WRMEM1_90_FLD8 GENMASK(127, 112) + +/* WRMEM1_91 register fields */ +#define WRMEM1_91_FLD1 GENMASK(15, 0) +#define WRMEM1_91_FLD2 GENMASK(31, 16) +#define WRMEM1_91_FLD3 GENMASK(47, 32) +#define WRMEM1_91_FLD4 GENMASK(63, 48) +#define WRMEM1_91_FLD5 GENMASK(79, 64) +#define WRMEM1_91_FLD6 GENMASK(95, 80) +#define WRMEM1_91_FLD7 GENMASK(111, 96) +#define WRMEM1_91_FLD8 GENMASK(127, 112) + +/* WRMEM1_92 register fields */ +#define WRMEM1_92_FLD1 GENMASK(15, 0) +#define WRMEM1_92_FLD2 GENMASK(31, 16) +#define WRMEM1_92_FLD3 GENMASK(47, 32) +#define WRMEM1_92_FLD4 GENMASK(63, 48) +#define WRMEM1_92_FLD5 GENMASK(79, 64) +#define WRMEM1_92_FLD6 GENMASK(95, 80) +#define WRMEM1_92_FLD7 GENMASK(111, 96) +#define WRMEM1_92_FLD8 GENMASK(127, 112) + +/* WRMEM1_93 register fields */ +#define WRMEM1_93_FLD1 GENMASK(15, 0) +#define WRMEM1_93_FLD2 GENMASK(31, 16) +#define WRMEM1_93_FLD3 GENMASK(47, 32) +#define WRMEM1_93_FLD4 GENMASK(63, 48) +#define WRMEM1_93_FLD5 GENMASK(79, 64) +#define WRMEM1_93_FLD6 GENMASK(95, 80) +#define WRMEM1_93_FLD7 GENMASK(111, 96) +#define WRMEM1_93_FLD8 GENMASK(127, 112) + +/* WRMEM1_94 register fields */ +#define WRMEM1_94_FLD1 GENMASK(15, 0) +#define WRMEM1_94_FLD2 GENMASK(31, 16) +#define WRMEM1_94_FLD3 GENMASK(47, 32) +#define WRMEM1_94_FLD4 GENMASK(63, 48) +#define WRMEM1_94_FLD5 GENMASK(79, 64) +#define WRMEM1_94_FLD6 GENMASK(95, 80) +#define WRMEM1_94_FLD7 GENMASK(111, 96) +#define WRMEM1_94_FLD8 GENMASK(127, 112) + +/* WRMEM1_95 register fields */ +#define WRMEM1_95_FLD1 GENMASK(15, 0) +#define WRMEM1_95_FLD2 GENMASK(31, 16) +#define WRMEM1_95_FLD3 GENMASK(47, 32) +#define WRMEM1_95_FLD4 GENMASK(63, 48) +#define WRMEM1_95_FLD5 GENMASK(79, 64) +#define WRMEM1_95_FLD6 GENMASK(95, 80) +#define WRMEM1_95_FLD7 GENMASK(111, 96) +#define WRMEM1_95_FLD8 GENMASK(127, 112) + +/* WRMEM1_96 register fields */ +#define WRMEM1_96_FLD1 GENMASK(15, 0) +#define WRMEM1_96_FLD2 GENMASK(31, 16) +#define WRMEM1_96_FLD3 GENMASK(47, 32) +#define WRMEM1_96_FLD4 GENMASK(63, 48) +#define WRMEM1_96_FLD5 GENMASK(79, 64) +#define WRMEM1_96_FLD6 GENMASK(95, 80) +#define WRMEM1_96_FLD7 GENMASK(111, 96) +#define WRMEM1_96_FLD8 GENMASK(127, 112) + +/* WRMEM1_97 register fields */ +#define WRMEM1_97_FLD1 GENMASK(15, 0) +#define WRMEM1_97_FLD2 GENMASK(31, 16) +#define WRMEM1_97_FLD3 GENMASK(47, 32) +#define WRMEM1_97_FLD4 GENMASK(63, 48) +#define WRMEM1_97_FLD5 GENMASK(79, 64) +#define WRMEM1_97_FLD6 GENMASK(95, 80) +#define WRMEM1_97_FLD7 GENMASK(111, 96) +#define WRMEM1_97_FLD8 GENMASK(127, 112) + +/* WRMEM1_98 register fields */ +#define WRMEM1_98_FLD1 GENMASK(15, 0) +#define WRMEM1_98_FLD2 GENMASK(31, 16) +#define WRMEM1_98_FLD3 GENMASK(47, 32) +#define WRMEM1_98_FLD4 GENMASK(63, 48) +#define WRMEM1_98_FLD5 GENMASK(79, 64) +#define WRMEM1_98_FLD6 GENMASK(95, 80) +#define WRMEM1_98_FLD7 GENMASK(111, 96) +#define WRMEM1_98_FLD8 GENMASK(127, 112) + +/* WRMEM1_99 register fields */ +#define WRMEM1_99_FLD1 GENMASK(15, 0) +#define WRMEM1_99_FLD2 GENMASK(31, 16) +#define WRMEM1_99_FLD3 GENMASK(47, 32) +#define WRMEM1_99_FLD4 GENMASK(63, 48) +#define WRMEM1_99_FLD5 GENMASK(79, 64) +#define WRMEM1_99_FLD6 GENMASK(95, 80) +#define WRMEM1_99_FLD7 GENMASK(111, 96) +#define WRMEM1_99_FLD8 GENMASK(127, 112) + +/* WRMEM1_100 register fields */ +#define WRMEM1_100_FLD1 GENMASK(15, 0) +#define WRMEM1_100_FLD2 GENMASK(31, 16) +#define WRMEM1_100_FLD3 GENMASK(47, 32) +#define WRMEM1_100_FLD4 GENMASK(63, 48) +#define WRMEM1_100_FLD5 GENMASK(79, 64) +#define WRMEM1_100_FLD6 GENMASK(95, 80) +#define WRMEM1_100_FLD7 GENMASK(111, 96) +#define WRMEM1_100_FLD8 GENMASK(127, 112) + +/* WRMEM1_101 register fields */ +#define WRMEM1_101_FLD1 GENMASK(15, 0) +#define WRMEM1_101_FLD2 GENMASK(31, 16) +#define WRMEM1_101_FLD3 GENMASK(47, 32) +#define WRMEM1_101_FLD4 GENMASK(63, 48) +#define WRMEM1_101_FLD5 GENMASK(79, 64) +#define WRMEM1_101_FLD6 GENMASK(95, 80) +#define WRMEM1_101_FLD7 GENMASK(111, 96) +#define WRMEM1_101_FLD8 GENMASK(127, 112) + +/* WRMEM1_102 register fields */ +#define WRMEM1_102_FLD1 GENMASK(15, 0) +#define WRMEM1_102_FLD2 GENMASK(31, 16) +#define WRMEM1_102_FLD3 GENMASK(47, 32) +#define WRMEM1_102_FLD4 GENMASK(63, 48) +#define WRMEM1_102_FLD5 GENMASK(79, 64) +#define WRMEM1_102_FLD6 GENMASK(95, 80) +#define WRMEM1_102_FLD7 GENMASK(111, 96) +#define WRMEM1_102_FLD8 GENMASK(127, 112) + +/* WRMEM1_103 register fields */ +#define WRMEM1_103_FLD1 GENMASK(15, 0) +#define WRMEM1_103_FLD2 GENMASK(31, 16) +#define WRMEM1_103_FLD3 GENMASK(47, 32) +#define WRMEM1_103_FLD4 GENMASK(63, 48) +#define WRMEM1_103_FLD5 GENMASK(79, 64) +#define WRMEM1_103_FLD6 GENMASK(95, 80) +#define WRMEM1_103_FLD7 GENMASK(111, 96) +#define WRMEM1_103_FLD8 GENMASK(127, 112) + +/* WRMEM1_104 register fields */ +#define WRMEM1_104_FLD1 GENMASK(15, 0) +#define WRMEM1_104_FLD2 GENMASK(31, 16) +#define WRMEM1_104_FLD3 GENMASK(47, 32) +#define WRMEM1_104_FLD4 GENMASK(63, 48) +#define WRMEM1_104_FLD5 GENMASK(79, 64) +#define WRMEM1_104_FLD6 GENMASK(95, 80) +#define WRMEM1_104_FLD7 GENMASK(111, 96) +#define WRMEM1_104_FLD8 GENMASK(127, 112) + +/* WRMEM1_105 register fields */ +#define WRMEM1_105_FLD1 GENMASK(15, 0) +#define WRMEM1_105_FLD2 GENMASK(31, 16) +#define WRMEM1_105_FLD3 GENMASK(47, 32) +#define WRMEM1_105_FLD4 GENMASK(63, 48) +#define WRMEM1_105_FLD5 GENMASK(79, 64) +#define WRMEM1_105_FLD6 GENMASK(95, 80) +#define WRMEM1_105_FLD7 GENMASK(111, 96) +#define WRMEM1_105_FLD8 GENMASK(127, 112) + +/* WRMEM1_106 register fields */ +#define WRMEM1_106_FLD1 GENMASK(15, 0) +#define WRMEM1_106_FLD2 GENMASK(31, 16) +#define WRMEM1_106_FLD3 GENMASK(47, 32) +#define WRMEM1_106_FLD4 GENMASK(63, 48) +#define WRMEM1_106_FLD5 GENMASK(79, 64) +#define WRMEM1_106_FLD6 GENMASK(95, 80) +#define WRMEM1_106_FLD7 GENMASK(111, 96) +#define WRMEM1_106_FLD8 GENMASK(127, 112) + +/* WRMEM1_107 register fields */ +#define WRMEM1_107_FLD1 GENMASK(15, 0) +#define WRMEM1_107_FLD2 GENMASK(31, 16) +#define WRMEM1_107_FLD3 GENMASK(47, 32) +#define WRMEM1_107_FLD4 GENMASK(63, 48) +#define WRMEM1_107_FLD5 GENMASK(79, 64) +#define WRMEM1_107_FLD6 GENMASK(95, 80) +#define WRMEM1_107_FLD7 GENMASK(111, 96) +#define WRMEM1_107_FLD8 GENMASK(127, 112) + +/* WRMEM1_108 register fields */ +#define WRMEM1_108_FLD1 GENMASK(15, 0) +#define WRMEM1_108_FLD2 GENMASK(31, 16) +#define WRMEM1_108_FLD3 GENMASK(47, 32) +#define WRMEM1_108_FLD4 GENMASK(63, 48) +#define WRMEM1_108_FLD5 GENMASK(79, 64) +#define WRMEM1_108_FLD6 GENMASK(95, 80) +#define WRMEM1_108_FLD7 GENMASK(111, 96) +#define WRMEM1_108_FLD8 GENMASK(127, 112) + +/* WRMEM1_109 register fields */ +#define WRMEM1_109_FLD1 GENMASK(15, 0) +#define WRMEM1_109_FLD2 GENMASK(31, 16) +#define WRMEM1_109_FLD3 GENMASK(47, 32) +#define WRMEM1_109_FLD4 GENMASK(63, 48) +#define WRMEM1_109_FLD5 GENMASK(79, 64) +#define WRMEM1_109_FLD6 GENMASK(95, 80) +#define WRMEM1_109_FLD7 GENMASK(111, 96) +#define WRMEM1_109_FLD8 GENMASK(127, 112) + +/* WRMEM1_110 register fields */ +#define WRMEM1_110_FLD1 GENMASK(15, 0) +#define WRMEM1_110_FLD2 GENMASK(31, 16) +#define WRMEM1_110_FLD3 GENMASK(47, 32) +#define WRMEM1_110_FLD4 GENMASK(63, 48) +#define WRMEM1_110_FLD5 GENMASK(79, 64) +#define WRMEM1_110_FLD6 GENMASK(95, 80) +#define WRMEM1_110_FLD7 GENMASK(111, 96) +#define WRMEM1_110_FLD8 GENMASK(127, 112) + +/* WRMEM1_111 register fields */ +#define WRMEM1_111_FLD1 GENMASK(15, 0) +#define WRMEM1_111_FLD2 GENMASK(31, 16) +#define WRMEM1_111_FLD3 GENMASK(47, 32) +#define WRMEM1_111_FLD4 GENMASK(63, 48) +#define WRMEM1_111_FLD5 GENMASK(79, 64) +#define WRMEM1_111_FLD6 GENMASK(95, 80) +#define WRMEM1_111_FLD7 GENMASK(111, 96) +#define WRMEM1_111_FLD8 GENMASK(127, 112) + +/* WRMEM1_112 register fields */ +#define WRMEM1_112_FLD1 GENMASK(15, 0) +#define WRMEM1_112_FLD2 GENMASK(31, 16) +#define WRMEM1_112_FLD3 GENMASK(47, 32) +#define WRMEM1_112_FLD4 GENMASK(63, 48) +#define WRMEM1_112_FLD5 GENMASK(79, 64) +#define WRMEM1_112_FLD6 GENMASK(95, 80) +#define WRMEM1_112_FLD7 GENMASK(111, 96) +#define WRMEM1_112_FLD8 GENMASK(127, 112) + +/* WRMEM1_113 register fields */ +#define WRMEM1_113_FLD1 GENMASK(15, 0) +#define WRMEM1_113_FLD2 GENMASK(31, 16) +#define WRMEM1_113_FLD3 GENMASK(47, 32) +#define WRMEM1_113_FLD4 GENMASK(63, 48) +#define WRMEM1_113_FLD5 GENMASK(79, 64) +#define WRMEM1_113_FLD6 GENMASK(95, 80) +#define WRMEM1_113_FLD7 GENMASK(111, 96) +#define WRMEM1_113_FLD8 GENMASK(127, 112) + +/* WRMEM1_114 register fields */ +#define WRMEM1_114_FLD1 GENMASK(15, 0) +#define WRMEM1_114_FLD2 GENMASK(31, 16) +#define WRMEM1_114_FLD3 GENMASK(47, 32) +#define WRMEM1_114_FLD4 GENMASK(63, 48) +#define WRMEM1_114_FLD5 GENMASK(79, 64) +#define WRMEM1_114_FLD6 GENMASK(95, 80) +#define WRMEM1_114_FLD7 GENMASK(111, 96) +#define WRMEM1_114_FLD8 GENMASK(127, 112) + +/* WRMEM1_115 register fields */ +#define WRMEM1_115_FLD1 GENMASK(15, 0) +#define WRMEM1_115_FLD2 GENMASK(31, 16) +#define WRMEM1_115_FLD3 GENMASK(47, 32) +#define WRMEM1_115_FLD4 GENMASK(63, 48) +#define WRMEM1_115_FLD5 GENMASK(79, 64) +#define WRMEM1_115_FLD6 GENMASK(95, 80) +#define WRMEM1_115_FLD7 GENMASK(111, 96) +#define WRMEM1_115_FLD8 GENMASK(127, 112) + +/* WRMEM1_116 register fields */ +#define WRMEM1_116_FLD1 GENMASK(15, 0) +#define WRMEM1_116_FLD2 GENMASK(31, 16) +#define WRMEM1_116_FLD3 GENMASK(47, 32) +#define WRMEM1_116_FLD4 GENMASK(63, 48) +#define WRMEM1_116_FLD5 GENMASK(79, 64) +#define WRMEM1_116_FLD6 GENMASK(95, 80) +#define WRMEM1_116_FLD7 GENMASK(111, 96) +#define WRMEM1_116_FLD8 GENMASK(127, 112) + +/* WRMEM1_117 register fields */ +#define WRMEM1_117_FLD1 GENMASK(15, 0) +#define WRMEM1_117_FLD2 GENMASK(31, 16) +#define WRMEM1_117_FLD3 GENMASK(47, 32) +#define WRMEM1_117_FLD4 GENMASK(63, 48) +#define WRMEM1_117_FLD5 GENMASK(79, 64) +#define WRMEM1_117_FLD6 GENMASK(95, 80) +#define WRMEM1_117_FLD7 GENMASK(111, 96) +#define WRMEM1_117_FLD8 GENMASK(127, 112) + +/* WRMEM1_118 register fields */ +#define WRMEM1_118_FLD1 GENMASK(15, 0) +#define WRMEM1_118_FLD2 GENMASK(31, 16) +#define WRMEM1_118_FLD3 GENMASK(47, 32) +#define WRMEM1_118_FLD4 GENMASK(63, 48) +#define WRMEM1_118_FLD5 GENMASK(79, 64) +#define WRMEM1_118_FLD6 GENMASK(95, 80) +#define WRMEM1_118_FLD7 GENMASK(111, 96) +#define WRMEM1_118_FLD8 GENMASK(127, 112) + +/* WRMEM1_119 register fields */ +#define WRMEM1_119_FLD1 GENMASK(15, 0) +#define WRMEM1_119_FLD2 GENMASK(31, 16) +#define WRMEM1_119_FLD3 GENMASK(47, 32) +#define WRMEM1_119_FLD4 GENMASK(63, 48) +#define WRMEM1_119_FLD5 GENMASK(79, 64) +#define WRMEM1_119_FLD6 GENMASK(95, 80) +#define WRMEM1_119_FLD7 GENMASK(111, 96) +#define WRMEM1_119_FLD8 GENMASK(127, 112) + +/* WRMEM1_120 register fields */ +#define WRMEM1_120_FLD1 GENMASK(15, 0) +#define WRMEM1_120_FLD2 GENMASK(31, 16) +#define WRMEM1_120_FLD3 GENMASK(47, 32) +#define WRMEM1_120_FLD4 GENMASK(63, 48) +#define WRMEM1_120_FLD5 GENMASK(79, 64) +#define WRMEM1_120_FLD6 GENMASK(95, 80) +#define WRMEM1_120_FLD7 GENMASK(111, 96) +#define WRMEM1_120_FLD8 GENMASK(127, 112) + +/* WRMEM1_121 register fields */ +#define WRMEM1_121_FLD1 GENMASK(15, 0) +#define WRMEM1_121_FLD2 GENMASK(31, 16) +#define WRMEM1_121_FLD3 GENMASK(47, 32) +#define WRMEM1_121_FLD4 GENMASK(63, 48) +#define WRMEM1_121_FLD5 GENMASK(79, 64) +#define WRMEM1_121_FLD6 GENMASK(95, 80) +#define WRMEM1_121_FLD7 GENMASK(111, 96) +#define WRMEM1_121_FLD8 GENMASK(127, 112) + +/* WRMEM1_122 register fields */ +#define WRMEM1_122_FLD1 GENMASK(15, 0) +#define WRMEM1_122_FLD2 GENMASK(31, 16) +#define WRMEM1_122_FLD3 GENMASK(47, 32) +#define WRMEM1_122_FLD4 GENMASK(63, 48) +#define WRMEM1_122_FLD5 GENMASK(79, 64) +#define WRMEM1_122_FLD6 GENMASK(95, 80) +#define WRMEM1_122_FLD7 GENMASK(111, 96) +#define WRMEM1_122_FLD8 GENMASK(127, 112) + +/* WRMEM1_123 register fields */ +#define WRMEM1_123_FLD1 GENMASK(15, 0) +#define WRMEM1_123_FLD2 GENMASK(31, 16) +#define WRMEM1_123_FLD3 GENMASK(47, 32) +#define WRMEM1_123_FLD4 GENMASK(63, 48) +#define WRMEM1_123_FLD5 GENMASK(79, 64) +#define WRMEM1_123_FLD6 GENMASK(95, 80) +#define WRMEM1_123_FLD7 GENMASK(111, 96) +#define WRMEM1_123_FLD8 GENMASK(127, 112) + +/* WRMEM1_124 register fields */ +#define WRMEM1_124_FLD1 GENMASK(15, 0) +#define WRMEM1_124_FLD2 GENMASK(31, 16) +#define WRMEM1_124_FLD3 GENMASK(47, 32) +#define WRMEM1_124_FLD4 GENMASK(63, 48) +#define WRMEM1_124_FLD5 GENMASK(79, 64) +#define WRMEM1_124_FLD6 GENMASK(95, 80) +#define WRMEM1_124_FLD7 GENMASK(111, 96) +#define WRMEM1_124_FLD8 GENMASK(127, 112) + +/* WRMEM1_125 register fields */ +#define WRMEM1_125_FLD1 GENMASK(15, 0) +#define WRMEM1_125_FLD2 GENMASK(31, 16) +#define WRMEM1_125_FLD3 GENMASK(47, 32) +#define WRMEM1_125_FLD4 GENMASK(63, 48) +#define WRMEM1_125_FLD5 GENMASK(79, 64) +#define WRMEM1_125_FLD6 GENMASK(95, 80) +#define WRMEM1_125_FLD7 GENMASK(111, 96) +#define WRMEM1_125_FLD8 GENMASK(127, 112) + +/* WRMEM1_126 register fields */ +#define WRMEM1_126_FLD1 GENMASK(15, 0) +#define WRMEM1_126_FLD2 GENMASK(31, 16) +#define WRMEM1_126_FLD3 GENMASK(47, 32) +#define WRMEM1_126_FLD4 GENMASK(63, 48) +#define WRMEM1_126_FLD5 GENMASK(79, 64) +#define WRMEM1_126_FLD6 GENMASK(95, 80) +#define WRMEM1_126_FLD7 GENMASK(111, 96) +#define WRMEM1_126_FLD8 GENMASK(127, 112) + +/* WRMEM1_127 register fields */ +#define WRMEM1_127_FLD1 GENMASK(15, 0) +#define WRMEM1_127_FLD2 GENMASK(31, 16) +#define WRMEM1_127_FLD3 GENMASK(47, 32) +#define WRMEM1_127_FLD4 GENMASK(63, 48) +#define WRMEM1_127_FLD5 GENMASK(79, 64) +#define WRMEM1_127_FLD6 GENMASK(95, 80) +#define WRMEM1_127_FLD7 GENMASK(111, 96) +#define WRMEM1_127_FLD8 GENMASK(127, 112) + +/* WRMEM1_128 register fields */ +#define WRMEM1_128_FLD1 GENMASK(15, 0) +#define WRMEM1_128_FLD2 GENMASK(31, 16) +#define WRMEM1_128_FLD3 GENMASK(47, 32) +#define WRMEM1_128_FLD4 GENMASK(63, 48) +#define WRMEM1_128_FLD5 GENMASK(79, 64) +#define WRMEM1_128_FLD6 GENMASK(95, 80) +#define WRMEM1_128_FLD7 GENMASK(111, 96) +#define WRMEM1_128_FLD8 GENMASK(127, 112) + +/* WRMEM1_129 register fields */ +#define WRMEM1_129_FLD1 GENMASK(15, 0) +#define WRMEM1_129_FLD2 GENMASK(31, 16) +#define WRMEM1_129_FLD3 GENMASK(47, 32) +#define WRMEM1_129_FLD4 GENMASK(63, 48) +#define WRMEM1_129_FLD5 GENMASK(79, 64) +#define WRMEM1_129_FLD6 GENMASK(95, 80) +#define WRMEM1_129_FLD7 GENMASK(111, 96) +#define WRMEM1_129_FLD8 GENMASK(127, 112) + +/* WRMEM1_130 register fields */ +#define WRMEM1_130_FLD1 GENMASK(15, 0) +#define WRMEM1_130_FLD2 GENMASK(31, 16) +#define WRMEM1_130_FLD3 GENMASK(47, 32) +#define WRMEM1_130_FLD4 GENMASK(63, 48) +#define WRMEM1_130_FLD5 GENMASK(79, 64) +#define WRMEM1_130_FLD6 GENMASK(95, 80) +#define WRMEM1_130_FLD7 GENMASK(111, 96) +#define WRMEM1_130_FLD8 GENMASK(127, 112) + +/* WRMEM1_131 register fields */ +#define WRMEM1_131_FLD1 GENMASK(15, 0) +#define WRMEM1_131_FLD2 GENMASK(31, 16) +#define WRMEM1_131_FLD3 GENMASK(47, 32) +#define WRMEM1_131_FLD4 GENMASK(63, 48) +#define WRMEM1_131_FLD5 GENMASK(79, 64) +#define WRMEM1_131_FLD6 GENMASK(95, 80) +#define WRMEM1_131_FLD7 GENMASK(111, 96) +#define WRMEM1_131_FLD8 GENMASK(127, 112) + +/* WRMEM1_132 register fields */ +#define WRMEM1_132_FLD1 GENMASK(15, 0) +#define WRMEM1_132_FLD2 GENMASK(31, 16) +#define WRMEM1_132_FLD3 GENMASK(47, 32) +#define WRMEM1_132_FLD4 GENMASK(63, 48) +#define WRMEM1_132_FLD5 GENMASK(79, 64) +#define WRMEM1_132_FLD6 GENMASK(95, 80) +#define WRMEM1_132_FLD7 GENMASK(111, 96) +#define WRMEM1_132_FLD8 GENMASK(127, 112) + +/* WRMEM1_133 register fields */ +#define WRMEM1_133_FLD1 GENMASK(15, 0) +#define WRMEM1_133_FLD2 GENMASK(31, 16) +#define WRMEM1_133_FLD3 GENMASK(47, 32) +#define WRMEM1_133_FLD4 GENMASK(63, 48) +#define WRMEM1_133_FLD5 GENMASK(79, 64) +#define WRMEM1_133_FLD6 GENMASK(95, 80) +#define WRMEM1_133_FLD7 GENMASK(111, 96) +#define WRMEM1_133_FLD8 GENMASK(127, 112) + +/* WRMEM1_134 register fields */ +#define WRMEM1_134_FLD1 GENMASK(15, 0) +#define WRMEM1_134_FLD2 GENMASK(31, 16) +#define WRMEM1_134_FLD3 GENMASK(47, 32) +#define WRMEM1_134_FLD4 GENMASK(63, 48) +#define WRMEM1_134_FLD5 GENMASK(79, 64) +#define WRMEM1_134_FLD6 GENMASK(95, 80) +#define WRMEM1_134_FLD7 GENMASK(111, 96) +#define WRMEM1_134_FLD8 GENMASK(127, 112) + +/* WRMEM1_135 register fields */ +#define WRMEM1_135_FLD1 GENMASK(15, 0) +#define WRMEM1_135_FLD2 GENMASK(31, 16) +#define WRMEM1_135_FLD3 GENMASK(47, 32) +#define WRMEM1_135_FLD4 GENMASK(63, 48) +#define WRMEM1_135_FLD5 GENMASK(79, 64) +#define WRMEM1_135_FLD6 GENMASK(95, 80) +#define WRMEM1_135_FLD7 GENMASK(111, 96) +#define WRMEM1_135_FLD8 GENMASK(127, 112) + +/* WRMEM1_136 register fields */ +#define WRMEM1_136_FLD1 GENMASK(15, 0) +#define WRMEM1_136_FLD2 GENMASK(31, 16) +#define WRMEM1_136_FLD3 GENMASK(47, 32) +#define WRMEM1_136_FLD4 GENMASK(63, 48) +#define WRMEM1_136_FLD5 GENMASK(79, 64) +#define WRMEM1_136_FLD6 GENMASK(95, 80) +#define WRMEM1_136_FLD7 GENMASK(111, 96) +#define WRMEM1_136_FLD8 GENMASK(127, 112) + +/* WRMEM1_137 register fields */ +#define WRMEM1_137_FLD1 GENMASK(15, 0) +#define WRMEM1_137_FLD2 GENMASK(31, 16) +#define WRMEM1_137_FLD3 GENMASK(47, 32) +#define WRMEM1_137_FLD4 GENMASK(63, 48) +#define WRMEM1_137_FLD5 GENMASK(79, 64) +#define WRMEM1_137_FLD6 GENMASK(95, 80) +#define WRMEM1_137_FLD7 GENMASK(111, 96) +#define WRMEM1_137_FLD8 GENMASK(127, 112) + +/* WRMEM1_138 register fields */ +#define WRMEM1_138_FLD1 GENMASK(15, 0) +#define WRMEM1_138_FLD2 GENMASK(31, 16) +#define WRMEM1_138_FLD3 GENMASK(47, 32) +#define WRMEM1_138_FLD4 GENMASK(63, 48) +#define WRMEM1_138_FLD5 GENMASK(79, 64) +#define WRMEM1_138_FLD6 GENMASK(95, 80) +#define WRMEM1_138_FLD7 GENMASK(111, 96) +#define WRMEM1_138_FLD8 GENMASK(127, 112) + +/* WRMEM1_139 register fields */ +#define WRMEM1_139_FLD1 GENMASK(15, 0) +#define WRMEM1_139_FLD2 GENMASK(31, 16) +#define WRMEM1_139_FLD3 GENMASK(47, 32) +#define WRMEM1_139_FLD4 GENMASK(63, 48) +#define WRMEM1_139_FLD5 GENMASK(79, 64) +#define WRMEM1_139_FLD6 GENMASK(95, 80) +#define WRMEM1_139_FLD7 GENMASK(111, 96) +#define WRMEM1_139_FLD8 GENMASK(127, 112) + +/* WRMEM1_140 register fields */ +#define WRMEM1_140_FLD1 GENMASK(15, 0) +#define WRMEM1_140_FLD2 GENMASK(31, 16) +#define WRMEM1_140_FLD3 GENMASK(47, 32) +#define WRMEM1_140_FLD4 GENMASK(63, 48) +#define WRMEM1_140_FLD5 GENMASK(79, 64) +#define WRMEM1_140_FLD6 GENMASK(95, 80) +#define WRMEM1_140_FLD7 GENMASK(111, 96) +#define WRMEM1_140_FLD8 GENMASK(127, 112) + +/* WRMEM1_141 register fields */ +#define WRMEM1_141_FLD1 GENMASK(15, 0) +#define WRMEM1_141_FLD2 GENMASK(31, 16) +#define WRMEM1_141_FLD3 GENMASK(47, 32) +#define WRMEM1_141_FLD4 GENMASK(63, 48) +#define WRMEM1_141_FLD5 GENMASK(79, 64) +#define WRMEM1_141_FLD6 GENMASK(95, 80) +#define WRMEM1_141_FLD7 GENMASK(111, 96) +#define WRMEM1_141_FLD8 GENMASK(127, 112) + +/* WRMEM1_142 register fields */ +#define WRMEM1_142_FLD1 GENMASK(15, 0) +#define WRMEM1_142_FLD2 GENMASK(31, 16) +#define WRMEM1_142_FLD3 GENMASK(47, 32) +#define WRMEM1_142_FLD4 GENMASK(63, 48) +#define WRMEM1_142_FLD5 GENMASK(79, 64) +#define WRMEM1_142_FLD6 GENMASK(95, 80) +#define WRMEM1_142_FLD7 GENMASK(111, 96) +#define WRMEM1_142_FLD8 GENMASK(127, 112) + +/* WRMEM1_143 register fields */ +#define WRMEM1_143_FLD1 GENMASK(15, 0) +#define WRMEM1_143_FLD2 GENMASK(31, 16) +#define WRMEM1_143_FLD3 GENMASK(47, 32) +#define WRMEM1_143_FLD4 GENMASK(63, 48) +#define WRMEM1_143_FLD5 GENMASK(79, 64) +#define WRMEM1_143_FLD6 GENMASK(95, 80) +#define WRMEM1_143_FLD7 GENMASK(111, 96) +#define WRMEM1_143_FLD8 GENMASK(127, 112) + +/* WRMEM1_144 register fields */ +#define WRMEM1_144_FLD1 GENMASK(15, 0) +#define WRMEM1_144_FLD2 GENMASK(31, 16) +#define WRMEM1_144_FLD3 GENMASK(47, 32) +#define WRMEM1_144_FLD4 GENMASK(63, 48) +#define WRMEM1_144_FLD5 GENMASK(79, 64) +#define WRMEM1_144_FLD6 GENMASK(95, 80) +#define WRMEM1_144_FLD7 GENMASK(111, 96) +#define WRMEM1_144_FLD8 GENMASK(127, 112) + +/* WRMEM1_145 register fields */ +#define WRMEM1_145_FLD1 GENMASK(15, 0) +#define WRMEM1_145_FLD2 GENMASK(31, 16) +#define WRMEM1_145_FLD3 GENMASK(47, 32) +#define WRMEM1_145_FLD4 GENMASK(63, 48) +#define WRMEM1_145_FLD5 GENMASK(79, 64) +#define WRMEM1_145_FLD6 GENMASK(95, 80) +#define WRMEM1_145_FLD7 GENMASK(111, 96) +#define WRMEM1_145_FLD8 GENMASK(127, 112) + +/* WRMEM1_146 register fields */ +#define WRMEM1_146_FLD1 GENMASK(15, 0) +#define WRMEM1_146_FLD2 GENMASK(31, 16) +#define WRMEM1_146_FLD3 GENMASK(47, 32) +#define WRMEM1_146_FLD4 GENMASK(63, 48) +#define WRMEM1_146_FLD5 GENMASK(79, 64) +#define WRMEM1_146_FLD6 GENMASK(95, 80) +#define WRMEM1_146_FLD7 GENMASK(111, 96) +#define WRMEM1_146_FLD8 GENMASK(127, 112) + +/* WRMEM1_147 register fields */ +#define WRMEM1_147_FLD1 GENMASK(15, 0) +#define WRMEM1_147_FLD2 GENMASK(31, 16) +#define WRMEM1_147_FLD3 GENMASK(47, 32) +#define WRMEM1_147_FLD4 GENMASK(63, 48) +#define WRMEM1_147_FLD5 GENMASK(79, 64) +#define WRMEM1_147_FLD6 GENMASK(95, 80) +#define WRMEM1_147_FLD7 GENMASK(111, 96) +#define WRMEM1_147_FLD8 GENMASK(127, 112) + +/* WRMEM1_148 register fields */ +#define WRMEM1_148_FLD1 GENMASK(15, 0) +#define WRMEM1_148_FLD2 GENMASK(31, 16) +#define WRMEM1_148_FLD3 GENMASK(47, 32) +#define WRMEM1_148_FLD4 GENMASK(63, 48) +#define WRMEM1_148_FLD5 GENMASK(79, 64) +#define WRMEM1_148_FLD6 GENMASK(95, 80) +#define WRMEM1_148_FLD7 GENMASK(111, 96) +#define WRMEM1_148_FLD8 GENMASK(127, 112) + +/* WRMEM1_149 register fields */ +#define WRMEM1_149_FLD1 GENMASK(15, 0) +#define WRMEM1_149_FLD2 GENMASK(31, 16) +#define WRMEM1_149_FLD3 GENMASK(47, 32) +#define WRMEM1_149_FLD4 GENMASK(63, 48) +#define WRMEM1_149_FLD5 GENMASK(79, 64) +#define WRMEM1_149_FLD6 GENMASK(95, 80) +#define WRMEM1_149_FLD7 GENMASK(111, 96) +#define WRMEM1_149_FLD8 GENMASK(127, 112) + +/* WRMEM1_150 register fields */ +#define WRMEM1_150_FLD1 GENMASK(15, 0) +#define WRMEM1_150_FLD2 GENMASK(31, 16) +#define WRMEM1_150_FLD3 GENMASK(47, 32) +#define WRMEM1_150_FLD4 GENMASK(63, 48) +#define WRMEM1_150_FLD5 GENMASK(79, 64) +#define WRMEM1_150_FLD6 GENMASK(95, 80) +#define WRMEM1_150_FLD7 GENMASK(111, 96) +#define WRMEM1_150_FLD8 GENMASK(127, 112) + +/* WRMEM1_151 register fields */ +#define WRMEM1_151_FLD1 GENMASK(15, 0) +#define WRMEM1_151_FLD2 GENMASK(31, 16) +#define WRMEM1_151_FLD3 GENMASK(47, 32) +#define WRMEM1_151_FLD4 GENMASK(63, 48) +#define WRMEM1_151_FLD5 GENMASK(79, 64) +#define WRMEM1_151_FLD6 GENMASK(95, 80) +#define WRMEM1_151_FLD7 GENMASK(111, 96) +#define WRMEM1_151_FLD8 GENMASK(127, 112) + +/* WRMEM1_152 register fields */ +#define WRMEM1_152_FLD1 GENMASK(15, 0) +#define WRMEM1_152_FLD2 GENMASK(31, 16) +#define WRMEM1_152_FLD3 GENMASK(47, 32) +#define WRMEM1_152_FLD4 GENMASK(63, 48) +#define WRMEM1_152_FLD5 GENMASK(79, 64) +#define WRMEM1_152_FLD6 GENMASK(95, 80) +#define WRMEM1_152_FLD7 GENMASK(111, 96) +#define WRMEM1_152_FLD8 GENMASK(127, 112) + +/* WRMEM1_153 register fields */ +#define WRMEM1_153_FLD1 GENMASK(15, 0) +#define WRMEM1_153_FLD2 GENMASK(31, 16) +#define WRMEM1_153_FLD3 GENMASK(47, 32) +#define WRMEM1_153_FLD4 GENMASK(63, 48) +#define WRMEM1_153_FLD5 GENMASK(79, 64) +#define WRMEM1_153_FLD6 GENMASK(95, 80) +#define WRMEM1_153_FLD7 GENMASK(111, 96) +#define WRMEM1_153_FLD8 GENMASK(127, 112) + +/* WRMEM1_154 register fields */ +#define WRMEM1_154_FLD1 GENMASK(15, 0) +#define WRMEM1_154_FLD2 GENMASK(31, 16) +#define WRMEM1_154_FLD3 GENMASK(47, 32) +#define WRMEM1_154_FLD4 GENMASK(63, 48) +#define WRMEM1_154_FLD5 GENMASK(79, 64) +#define WRMEM1_154_FLD6 GENMASK(95, 80) +#define WRMEM1_154_FLD7 GENMASK(111, 96) +#define WRMEM1_154_FLD8 GENMASK(127, 112) + +/* WRMEM1_155 register fields */ +#define WRMEM1_155_FLD1 GENMASK(15, 0) +#define WRMEM1_155_FLD2 GENMASK(31, 16) +#define WRMEM1_155_FLD3 GENMASK(47, 32) +#define WRMEM1_155_FLD4 GENMASK(63, 48) +#define WRMEM1_155_FLD5 GENMASK(79, 64) +#define WRMEM1_155_FLD6 GENMASK(95, 80) +#define WRMEM1_155_FLD7 GENMASK(111, 96) +#define WRMEM1_155_FLD8 GENMASK(127, 112) + +/* WRMEM1_156 register fields */ +#define WRMEM1_156_FLD1 GENMASK(15, 0) +#define WRMEM1_156_FLD2 GENMASK(31, 16) +#define WRMEM1_156_FLD3 GENMASK(47, 32) +#define WRMEM1_156_FLD4 GENMASK(63, 48) +#define WRMEM1_156_FLD5 GENMASK(79, 64) +#define WRMEM1_156_FLD6 GENMASK(95, 80) +#define WRMEM1_156_FLD7 GENMASK(111, 96) +#define WRMEM1_156_FLD8 GENMASK(127, 112) + +/* WRMEM1_157 register fields */ +#define WRMEM1_157_FLD1 GENMASK(15, 0) +#define WRMEM1_157_FLD2 GENMASK(31, 16) +#define WRMEM1_157_FLD3 GENMASK(47, 32) +#define WRMEM1_157_FLD4 GENMASK(63, 48) +#define WRMEM1_157_FLD5 GENMASK(79, 64) +#define WRMEM1_157_FLD6 GENMASK(95, 80) +#define WRMEM1_157_FLD7 GENMASK(111, 96) +#define WRMEM1_157_FLD8 GENMASK(127, 112) + +/* WRMEM1_158 register fields */ +#define WRMEM1_158_FLD1 GENMASK(15, 0) +#define WRMEM1_158_FLD2 GENMASK(31, 16) +#define WRMEM1_158_FLD3 GENMASK(47, 32) +#define WRMEM1_158_FLD4 GENMASK(63, 48) +#define WRMEM1_158_FLD5 GENMASK(79, 64) +#define WRMEM1_158_FLD6 GENMASK(95, 80) +#define WRMEM1_158_FLD7 GENMASK(111, 96) +#define WRMEM1_158_FLD8 GENMASK(127, 112) + +/* WRMEM1_159 register fields */ +#define WRMEM1_159_FLD1 GENMASK(15, 0) +#define WRMEM1_159_FLD2 GENMASK(31, 16) +#define WRMEM1_159_FLD3 GENMASK(47, 32) +#define WRMEM1_159_FLD4 GENMASK(63, 48) +#define WRMEM1_159_FLD5 GENMASK(79, 64) +#define WRMEM1_159_FLD6 GENMASK(95, 80) +#define WRMEM1_159_FLD7 GENMASK(111, 96) +#define WRMEM1_159_FLD8 GENMASK(127, 112) + +/* WRMEM1_160 register fields */ +#define WRMEM1_160_FLD1 GENMASK(15, 0) +#define WRMEM1_160_FLD2 GENMASK(31, 16) +#define WRMEM1_160_FLD3 GENMASK(47, 32) +#define WRMEM1_160_FLD4 GENMASK(63, 48) +#define WRMEM1_160_FLD5 GENMASK(79, 64) +#define WRMEM1_160_FLD6 GENMASK(95, 80) +#define WRMEM1_160_FLD7 GENMASK(111, 96) +#define WRMEM1_160_FLD8 GENMASK(127, 112) + +/* WRMEM1_161 register fields */ +#define WRMEM1_161_FLD1 GENMASK(15, 0) +#define WRMEM1_161_FLD2 GENMASK(31, 16) +#define WRMEM1_161_FLD3 GENMASK(47, 32) +#define WRMEM1_161_FLD4 GENMASK(63, 48) +#define WRMEM1_161_FLD5 GENMASK(79, 64) +#define WRMEM1_161_FLD6 GENMASK(95, 80) +#define WRMEM1_161_FLD7 GENMASK(111, 96) +#define WRMEM1_161_FLD8 GENMASK(127, 112) + +/* WRMEM1_162 register fields */ +#define WRMEM1_162_FLD1 GENMASK(15, 0) +#define WRMEM1_162_FLD2 GENMASK(31, 16) +#define WRMEM1_162_FLD3 GENMASK(47, 32) +#define WRMEM1_162_FLD4 GENMASK(63, 48) +#define WRMEM1_162_FLD5 GENMASK(79, 64) +#define WRMEM1_162_FLD6 GENMASK(95, 80) +#define WRMEM1_162_FLD7 GENMASK(111, 96) +#define WRMEM1_162_FLD8 GENMASK(127, 112) + +/* WRMEM1_163 register fields */ +#define WRMEM1_163_FLD1 GENMASK(15, 0) +#define WRMEM1_163_FLD2 GENMASK(31, 16) +#define WRMEM1_163_FLD3 GENMASK(47, 32) +#define WRMEM1_163_FLD4 GENMASK(63, 48) +#define WRMEM1_163_FLD5 GENMASK(79, 64) +#define WRMEM1_163_FLD6 GENMASK(95, 80) +#define WRMEM1_163_FLD7 GENMASK(111, 96) +#define WRMEM1_163_FLD8 GENMASK(127, 112) + +/* WRMEM1_164 register fields */ +#define WRMEM1_164_FLD1 GENMASK(15, 0) +#define WRMEM1_164_FLD2 GENMASK(31, 16) +#define WRMEM1_164_FLD3 GENMASK(47, 32) +#define WRMEM1_164_FLD4 GENMASK(63, 48) +#define WRMEM1_164_FLD5 GENMASK(79, 64) +#define WRMEM1_164_FLD6 GENMASK(95, 80) +#define WRMEM1_164_FLD7 GENMASK(111, 96) +#define WRMEM1_164_FLD8 GENMASK(127, 112) + +/* WRMEM1_165 register fields */ +#define WRMEM1_165_FLD1 GENMASK(15, 0) +#define WRMEM1_165_FLD2 GENMASK(31, 16) +#define WRMEM1_165_FLD3 GENMASK(47, 32) +#define WRMEM1_165_FLD4 GENMASK(63, 48) +#define WRMEM1_165_FLD5 GENMASK(79, 64) +#define WRMEM1_165_FLD6 GENMASK(95, 80) +#define WRMEM1_165_FLD7 GENMASK(111, 96) +#define WRMEM1_165_FLD8 GENMASK(127, 112) + +/* WRMEM1_166 register fields */ +#define WRMEM1_166_FLD1 GENMASK(15, 0) +#define WRMEM1_166_FLD2 GENMASK(31, 16) +#define WRMEM1_166_FLD3 GENMASK(47, 32) +#define WRMEM1_166_FLD4 GENMASK(63, 48) +#define WRMEM1_166_FLD5 GENMASK(79, 64) +#define WRMEM1_166_FLD6 GENMASK(95, 80) +#define WRMEM1_166_FLD7 GENMASK(111, 96) +#define WRMEM1_166_FLD8 GENMASK(127, 112) + +/* WRMEM1_167 register fields */ +#define WRMEM1_167_FLD1 GENMASK(15, 0) +#define WRMEM1_167_FLD2 GENMASK(31, 16) +#define WRMEM1_167_FLD3 GENMASK(47, 32) +#define WRMEM1_167_FLD4 GENMASK(63, 48) +#define WRMEM1_167_FLD5 GENMASK(79, 64) +#define WRMEM1_167_FLD6 GENMASK(95, 80) +#define WRMEM1_167_FLD7 GENMASK(111, 96) +#define WRMEM1_167_FLD8 GENMASK(127, 112) + +/* WRMEM1_168 register fields */ +#define WRMEM1_168_FLD1 GENMASK(15, 0) +#define WRMEM1_168_FLD2 GENMASK(31, 16) +#define WRMEM1_168_FLD3 GENMASK(47, 32) +#define WRMEM1_168_FLD4 GENMASK(63, 48) +#define WRMEM1_168_FLD5 GENMASK(79, 64) +#define WRMEM1_168_FLD6 GENMASK(95, 80) +#define WRMEM1_168_FLD7 GENMASK(111, 96) +#define WRMEM1_168_FLD8 GENMASK(127, 112) + +/* WRMEM1_169 register fields */ +#define WRMEM1_169_FLD1 GENMASK(15, 0) +#define WRMEM1_169_FLD2 GENMASK(31, 16) +#define WRMEM1_169_FLD3 GENMASK(47, 32) +#define WRMEM1_169_FLD4 GENMASK(63, 48) +#define WRMEM1_169_FLD5 GENMASK(79, 64) +#define WRMEM1_169_FLD6 GENMASK(95, 80) +#define WRMEM1_169_FLD7 GENMASK(111, 96) +#define WRMEM1_169_FLD8 GENMASK(127, 112) + +/* WRMEM1_170 register fields */ +#define WRMEM1_170_FLD1 GENMASK(15, 0) +#define WRMEM1_170_FLD2 GENMASK(31, 16) +#define WRMEM1_170_FLD3 GENMASK(47, 32) +#define WRMEM1_170_FLD4 GENMASK(63, 48) +#define WRMEM1_170_FLD5 GENMASK(79, 64) +#define WRMEM1_170_FLD6 GENMASK(95, 80) +#define WRMEM1_170_FLD7 GENMASK(111, 96) +#define WRMEM1_170_FLD8 GENMASK(127, 112) + +/* WRMEM1_171 register fields */ +#define WRMEM1_171_FLD1 GENMASK(15, 0) +#define WRMEM1_171_FLD2 GENMASK(31, 16) +#define WRMEM1_171_FLD3 GENMASK(47, 32) +#define WRMEM1_171_FLD4 GENMASK(63, 48) +#define WRMEM1_171_FLD5 GENMASK(79, 64) +#define WRMEM1_171_FLD6 GENMASK(95, 80) +#define WRMEM1_171_FLD7 GENMASK(111, 96) +#define WRMEM1_171_FLD8 GENMASK(127, 112) + +/* WRMEM1_172 register fields */ +#define WRMEM1_172_FLD1 GENMASK(15, 0) +#define WRMEM1_172_FLD2 GENMASK(31, 16) +#define WRMEM1_172_FLD3 GENMASK(47, 32) +#define WRMEM1_172_FLD4 GENMASK(63, 48) +#define WRMEM1_172_FLD5 GENMASK(79, 64) +#define WRMEM1_172_FLD6 GENMASK(95, 80) +#define WRMEM1_172_FLD7 GENMASK(111, 96) +#define WRMEM1_172_FLD8 GENMASK(127, 112) + +/* WRMEM1_173 register fields */ +#define WRMEM1_173_FLD1 GENMASK(15, 0) +#define WRMEM1_173_FLD2 GENMASK(31, 16) +#define WRMEM1_173_FLD3 GENMASK(47, 32) +#define WRMEM1_173_FLD4 GENMASK(63, 48) +#define WRMEM1_173_FLD5 GENMASK(79, 64) +#define WRMEM1_173_FLD6 GENMASK(95, 80) +#define WRMEM1_173_FLD7 GENMASK(111, 96) +#define WRMEM1_173_FLD8 GENMASK(127, 112) + +/* WRMEM1_174 register fields */ +#define WRMEM1_174_FLD1 GENMASK(15, 0) +#define WRMEM1_174_FLD2 GENMASK(31, 16) +#define WRMEM1_174_FLD3 GENMASK(47, 32) +#define WRMEM1_174_FLD4 GENMASK(63, 48) +#define WRMEM1_174_FLD5 GENMASK(79, 64) +#define WRMEM1_174_FLD6 GENMASK(95, 80) +#define WRMEM1_174_FLD7 GENMASK(111, 96) +#define WRMEM1_174_FLD8 GENMASK(127, 112) + +/* WRMEM1_175 register fields */ +#define WRMEM1_175_FLD1 GENMASK(15, 0) +#define WRMEM1_175_FLD2 GENMASK(31, 16) +#define WRMEM1_175_FLD3 GENMASK(47, 32) +#define WRMEM1_175_FLD4 GENMASK(63, 48) +#define WRMEM1_175_FLD5 GENMASK(79, 64) +#define WRMEM1_175_FLD6 GENMASK(95, 80) +#define WRMEM1_175_FLD7 GENMASK(111, 96) +#define WRMEM1_175_FLD8 GENMASK(127, 112) + +/* WRMEM1_176 register fields */ +#define WRMEM1_176_FLD1 GENMASK(15, 0) +#define WRMEM1_176_FLD2 GENMASK(31, 16) +#define WRMEM1_176_FLD3 GENMASK(47, 32) +#define WRMEM1_176_FLD4 GENMASK(63, 48) +#define WRMEM1_176_FLD5 GENMASK(79, 64) +#define WRMEM1_176_FLD6 GENMASK(95, 80) +#define WRMEM1_176_FLD7 GENMASK(111, 96) +#define WRMEM1_176_FLD8 GENMASK(127, 112) + +/* WRMEM1_177 register fields */ +#define WRMEM1_177_FLD1 GENMASK(15, 0) +#define WRMEM1_177_FLD2 GENMASK(31, 16) +#define WRMEM1_177_FLD3 GENMASK(47, 32) +#define WRMEM1_177_FLD4 GENMASK(63, 48) +#define WRMEM1_177_FLD5 GENMASK(79, 64) +#define WRMEM1_177_FLD6 GENMASK(95, 80) +#define WRMEM1_177_FLD7 GENMASK(111, 96) +#define WRMEM1_177_FLD8 GENMASK(127, 112) + +/* WRMEM1_178 register fields */ +#define WRMEM1_178_FLD1 GENMASK(15, 0) +#define WRMEM1_178_FLD2 GENMASK(31, 16) +#define WRMEM1_178_FLD3 GENMASK(47, 32) +#define WRMEM1_178_FLD4 GENMASK(63, 48) +#define WRMEM1_178_FLD5 GENMASK(79, 64) +#define WRMEM1_178_FLD6 GENMASK(95, 80) +#define WRMEM1_178_FLD7 GENMASK(111, 96) +#define WRMEM1_178_FLD8 GENMASK(127, 112) + +/* WRMEM1_179 register fields */ +#define WRMEM1_179_FLD1 GENMASK(15, 0) +#define WRMEM1_179_FLD2 GENMASK(31, 16) +#define WRMEM1_179_FLD3 GENMASK(47, 32) +#define WRMEM1_179_FLD4 GENMASK(63, 48) +#define WRMEM1_179_FLD5 GENMASK(79, 64) +#define WRMEM1_179_FLD6 GENMASK(95, 80) +#define WRMEM1_179_FLD7 GENMASK(111, 96) +#define WRMEM1_179_FLD8 GENMASK(127, 112) + +/* WRMEM1_180 register fields */ +#define WRMEM1_180_FLD1 GENMASK(15, 0) +#define WRMEM1_180_FLD2 GENMASK(31, 16) +#define WRMEM1_180_FLD3 GENMASK(47, 32) +#define WRMEM1_180_FLD4 GENMASK(63, 48) +#define WRMEM1_180_FLD5 GENMASK(79, 64) +#define WRMEM1_180_FLD6 GENMASK(95, 80) +#define WRMEM1_180_FLD7 GENMASK(111, 96) +#define WRMEM1_180_FLD8 GENMASK(127, 112) + +/* WRMEM1_181 register fields */ +#define WRMEM1_181_FLD1 GENMASK(15, 0) +#define WRMEM1_181_FLD2 GENMASK(31, 16) +#define WRMEM1_181_FLD3 GENMASK(47, 32) +#define WRMEM1_181_FLD4 GENMASK(63, 48) +#define WRMEM1_181_FLD5 GENMASK(79, 64) +#define WRMEM1_181_FLD6 GENMASK(95, 80) +#define WRMEM1_181_FLD7 GENMASK(111, 96) +#define WRMEM1_181_FLD8 GENMASK(127, 112) + +/* WRMEM1_182 register fields */ +#define WRMEM1_182_FLD1 GENMASK(15, 0) +#define WRMEM1_182_FLD2 GENMASK(31, 16) +#define WRMEM1_182_FLD3 GENMASK(47, 32) +#define WRMEM1_182_FLD4 GENMASK(63, 48) +#define WRMEM1_182_FLD5 GENMASK(79, 64) +#define WRMEM1_182_FLD6 GENMASK(95, 80) +#define WRMEM1_182_FLD7 GENMASK(111, 96) +#define WRMEM1_182_FLD8 GENMASK(127, 112) + +/* WRMEM1_183 register fields */ +#define WRMEM1_183_FLD1 GENMASK(15, 0) +#define WRMEM1_183_FLD2 GENMASK(31, 16) +#define WRMEM1_183_FLD3 GENMASK(47, 32) +#define WRMEM1_183_FLD4 GENMASK(63, 48) +#define WRMEM1_183_FLD5 GENMASK(79, 64) +#define WRMEM1_183_FLD6 GENMASK(95, 80) +#define WRMEM1_183_FLD7 GENMASK(111, 96) +#define WRMEM1_183_FLD8 GENMASK(127, 112) + +/* WRMEM1_184 register fields */ +#define WRMEM1_184_FLD1 GENMASK(15, 0) +#define WRMEM1_184_FLD2 GENMASK(31, 16) +#define WRMEM1_184_FLD3 GENMASK(47, 32) +#define WRMEM1_184_FLD4 GENMASK(63, 48) +#define WRMEM1_184_FLD5 GENMASK(79, 64) +#define WRMEM1_184_FLD6 GENMASK(95, 80) +#define WRMEM1_184_FLD7 GENMASK(111, 96) +#define WRMEM1_184_FLD8 GENMASK(127, 112) + +/* WRMEM1_185 register fields */ +#define WRMEM1_185_FLD1 GENMASK(15, 0) +#define WRMEM1_185_FLD2 GENMASK(31, 16) +#define WRMEM1_185_FLD3 GENMASK(47, 32) +#define WRMEM1_185_FLD4 GENMASK(63, 48) +#define WRMEM1_185_FLD5 GENMASK(79, 64) +#define WRMEM1_185_FLD6 GENMASK(95, 80) +#define WRMEM1_185_FLD7 GENMASK(111, 96) +#define WRMEM1_185_FLD8 GENMASK(127, 112) + +/* WRMEM1_186 register fields */ +#define WRMEM1_186_FLD1 GENMASK(15, 0) +#define WRMEM1_186_FLD2 GENMASK(31, 16) +#define WRMEM1_186_FLD3 GENMASK(47, 32) +#define WRMEM1_186_FLD4 GENMASK(63, 48) +#define WRMEM1_186_FLD5 GENMASK(79, 64) +#define WRMEM1_186_FLD6 GENMASK(95, 80) +#define WRMEM1_186_FLD7 GENMASK(111, 96) +#define WRMEM1_186_FLD8 GENMASK(127, 112) + +/* WRMEM1_187 register fields */ +#define WRMEM1_187_FLD1 GENMASK(15, 0) +#define WRMEM1_187_FLD2 GENMASK(31, 16) +#define WRMEM1_187_FLD3 GENMASK(47, 32) +#define WRMEM1_187_FLD4 GENMASK(63, 48) +#define WRMEM1_187_FLD5 GENMASK(79, 64) +#define WRMEM1_187_FLD6 GENMASK(95, 80) +#define WRMEM1_187_FLD7 GENMASK(111, 96) +#define WRMEM1_187_FLD8 GENMASK(127, 112) + +/* WRMEM1_188 register fields */ +#define WRMEM1_188_FLD1 GENMASK(15, 0) +#define WRMEM1_188_FLD2 GENMASK(31, 16) +#define WRMEM1_188_FLD3 GENMASK(47, 32) +#define WRMEM1_188_FLD4 GENMASK(63, 48) +#define WRMEM1_188_FLD5 GENMASK(79, 64) +#define WRMEM1_188_FLD6 GENMASK(95, 80) +#define WRMEM1_188_FLD7 GENMASK(111, 96) +#define WRMEM1_188_FLD8 GENMASK(127, 112) + +/* WRMEM1_189 register fields */ +#define WRMEM1_189_FLD1 GENMASK(15, 0) +#define WRMEM1_189_FLD2 GENMASK(31, 16) +#define WRMEM1_189_FLD3 GENMASK(47, 32) +#define WRMEM1_189_FLD4 GENMASK(63, 48) +#define WRMEM1_189_FLD5 GENMASK(79, 64) +#define WRMEM1_189_FLD6 GENMASK(95, 80) +#define WRMEM1_189_FLD7 GENMASK(111, 96) +#define WRMEM1_189_FLD8 GENMASK(127, 112) + +/* WRMEM1_190 register fields */ +#define WRMEM1_190_FLD1 GENMASK(15, 0) +#define WRMEM1_190_FLD2 GENMASK(31, 16) +#define WRMEM1_190_FLD3 GENMASK(47, 32) +#define WRMEM1_190_FLD4 GENMASK(63, 48) +#define WRMEM1_190_FLD5 GENMASK(79, 64) +#define WRMEM1_190_FLD6 GENMASK(95, 80) +#define WRMEM1_190_FLD7 GENMASK(111, 96) +#define WRMEM1_190_FLD8 GENMASK(127, 112) + +/* WRMEM1_191 register fields */ +#define WRMEM1_191_FLD1 GENMASK(15, 0) +#define WRMEM1_191_FLD2 GENMASK(31, 16) +#define WRMEM1_191_FLD3 GENMASK(47, 32) +#define WRMEM1_191_FLD4 GENMASK(63, 48) +#define WRMEM1_191_FLD5 GENMASK(79, 64) +#define WRMEM1_191_FLD6 GENMASK(95, 80) +#define WRMEM1_191_FLD7 GENMASK(111, 96) +#define WRMEM1_191_FLD8 GENMASK(127, 112) + +/* WRMEM1_192 register fields */ +#define WRMEM1_192_FLD1 GENMASK(15, 0) +#define WRMEM1_192_FLD2 GENMASK(31, 16) +#define WRMEM1_192_FLD3 GENMASK(47, 32) +#define WRMEM1_192_FLD4 GENMASK(63, 48) +#define WRMEM1_192_FLD5 GENMASK(79, 64) +#define WRMEM1_192_FLD6 GENMASK(95, 80) +#define WRMEM1_192_FLD7 GENMASK(111, 96) +#define WRMEM1_192_FLD8 GENMASK(127, 112) + +/* WRMEM1_193 register fields */ +#define WRMEM1_193_FLD1 GENMASK(15, 0) +#define WRMEM1_193_FLD2 GENMASK(31, 16) +#define WRMEM1_193_FLD3 GENMASK(47, 32) +#define WRMEM1_193_FLD4 GENMASK(63, 48) +#define WRMEM1_193_FLD5 GENMASK(79, 64) +#define WRMEM1_193_FLD6 GENMASK(95, 80) +#define WRMEM1_193_FLD7 GENMASK(111, 96) +#define WRMEM1_193_FLD8 GENMASK(127, 112) + +/* WRMEM1_194 register fields */ +#define WRMEM1_194_FLD1 GENMASK(15, 0) +#define WRMEM1_194_FLD2 GENMASK(31, 16) +#define WRMEM1_194_FLD3 GENMASK(47, 32) +#define WRMEM1_194_FLD4 GENMASK(63, 48) +#define WRMEM1_194_FLD5 GENMASK(79, 64) +#define WRMEM1_194_FLD6 GENMASK(95, 80) +#define WRMEM1_194_FLD7 GENMASK(111, 96) +#define WRMEM1_194_FLD8 GENMASK(127, 112) + +/* WRMEM1_195 register fields */ +#define WRMEM1_195_FLD1 GENMASK(15, 0) +#define WRMEM1_195_FLD2 GENMASK(31, 16) +#define WRMEM1_195_FLD3 GENMASK(47, 32) +#define WRMEM1_195_FLD4 GENMASK(63, 48) +#define WRMEM1_195_FLD5 GENMASK(79, 64) +#define WRMEM1_195_FLD6 GENMASK(95, 80) +#define WRMEM1_195_FLD7 GENMASK(111, 96) +#define WRMEM1_195_FLD8 GENMASK(127, 112) + +/* WRMEM1_196 register fields */ +#define WRMEM1_196_FLD1 GENMASK(15, 0) +#define WRMEM1_196_FLD2 GENMASK(31, 16) +#define WRMEM1_196_FLD3 GENMASK(47, 32) +#define WRMEM1_196_FLD4 GENMASK(63, 48) +#define WRMEM1_196_FLD5 GENMASK(79, 64) +#define WRMEM1_196_FLD6 GENMASK(95, 80) +#define WRMEM1_196_FLD7 GENMASK(111, 96) +#define WRMEM1_196_FLD8 GENMASK(127, 112) + +/* WRMEM1_197 register fields */ +#define WRMEM1_197_FLD1 GENMASK(15, 0) +#define WRMEM1_197_FLD2 GENMASK(31, 16) +#define WRMEM1_197_FLD3 GENMASK(47, 32) +#define WRMEM1_197_FLD4 GENMASK(63, 48) +#define WRMEM1_197_FLD5 GENMASK(79, 64) +#define WRMEM1_197_FLD6 GENMASK(95, 80) +#define WRMEM1_197_FLD7 GENMASK(111, 96) +#define WRMEM1_197_FLD8 GENMASK(127, 112) + +/* WRMEM1_198 register fields */ +#define WRMEM1_198_FLD1 GENMASK(15, 0) +#define WRMEM1_198_FLD2 GENMASK(31, 16) +#define WRMEM1_198_FLD3 GENMASK(47, 32) +#define WRMEM1_198_FLD4 GENMASK(63, 48) +#define WRMEM1_198_FLD5 GENMASK(79, 64) +#define WRMEM1_198_FLD6 GENMASK(95, 80) +#define WRMEM1_198_FLD7 GENMASK(111, 96) +#define WRMEM1_198_FLD8 GENMASK(127, 112) + +/* WRMEM1_199 register fields */ +#define WRMEM1_199_FLD1 GENMASK(15, 0) +#define WRMEM1_199_FLD2 GENMASK(31, 16) +#define WRMEM1_199_FLD3 GENMASK(47, 32) +#define WRMEM1_199_FLD4 GENMASK(63, 48) +#define WRMEM1_199_FLD5 GENMASK(79, 64) +#define WRMEM1_199_FLD6 GENMASK(95, 80) +#define WRMEM1_199_FLD7 GENMASK(111, 96) +#define WRMEM1_199_FLD8 GENMASK(127, 112) + +/* WRMEM1_200 register fields */ +#define WRMEM1_200_FLD1 GENMASK(15, 0) +#define WRMEM1_200_FLD2 GENMASK(31, 16) +#define WRMEM1_200_FLD3 GENMASK(47, 32) +#define WRMEM1_200_FLD4 GENMASK(63, 48) +#define WRMEM1_200_FLD5 GENMASK(79, 64) +#define WRMEM1_200_FLD6 GENMASK(95, 80) +#define WRMEM1_200_FLD7 GENMASK(111, 96) +#define WRMEM1_200_FLD8 GENMASK(127, 112) + +/* WRMEM1_201 register fields */ +#define WRMEM1_201_FLD1 GENMASK(15, 0) +#define WRMEM1_201_FLD2 GENMASK(31, 16) +#define WRMEM1_201_FLD3 GENMASK(47, 32) +#define WRMEM1_201_FLD4 GENMASK(63, 48) +#define WRMEM1_201_FLD5 GENMASK(79, 64) +#define WRMEM1_201_FLD6 GENMASK(95, 80) +#define WRMEM1_201_FLD7 GENMASK(111, 96) +#define WRMEM1_201_FLD8 GENMASK(127, 112) + +/* WRMEM1_202 register fields */ +#define WRMEM1_202_FLD1 GENMASK(15, 0) +#define WRMEM1_202_FLD2 GENMASK(31, 16) +#define WRMEM1_202_FLD3 GENMASK(47, 32) +#define WRMEM1_202_FLD4 GENMASK(63, 48) +#define WRMEM1_202_FLD5 GENMASK(79, 64) +#define WRMEM1_202_FLD6 GENMASK(95, 80) +#define WRMEM1_202_FLD7 GENMASK(111, 96) +#define WRMEM1_202_FLD8 GENMASK(127, 112) + +/* WRMEM1_203 register fields */ +#define WRMEM1_203_FLD1 GENMASK(15, 0) +#define WRMEM1_203_FLD2 GENMASK(31, 16) +#define WRMEM1_203_FLD3 GENMASK(47, 32) +#define WRMEM1_203_FLD4 GENMASK(63, 48) +#define WRMEM1_203_FLD5 GENMASK(79, 64) +#define WRMEM1_203_FLD6 GENMASK(95, 80) +#define WRMEM1_203_FLD7 GENMASK(111, 96) +#define WRMEM1_203_FLD8 GENMASK(127, 112) + +/* WRMEM1_204 register fields */ +#define WRMEM1_204_FLD1 GENMASK(15, 0) +#define WRMEM1_204_FLD2 GENMASK(31, 16) +#define WRMEM1_204_FLD3 GENMASK(47, 32) +#define WRMEM1_204_FLD4 GENMASK(63, 48) +#define WRMEM1_204_FLD5 GENMASK(79, 64) +#define WRMEM1_204_FLD6 GENMASK(95, 80) +#define WRMEM1_204_FLD7 GENMASK(111, 96) +#define WRMEM1_204_FLD8 GENMASK(127, 112) + +/* WRMEM1_205 register fields */ +#define WRMEM1_205_FLD1 GENMASK(15, 0) +#define WRMEM1_205_FLD2 GENMASK(31, 16) +#define WRMEM1_205_FLD3 GENMASK(47, 32) +#define WRMEM1_205_FLD4 GENMASK(63, 48) +#define WRMEM1_205_FLD5 GENMASK(79, 64) +#define WRMEM1_205_FLD6 GENMASK(95, 80) +#define WRMEM1_205_FLD7 GENMASK(111, 96) +#define WRMEM1_205_FLD8 GENMASK(127, 112) + +/* WRMEM1_206 register fields */ +#define WRMEM1_206_FLD1 GENMASK(15, 0) +#define WRMEM1_206_FLD2 GENMASK(31, 16) +#define WRMEM1_206_FLD3 GENMASK(47, 32) +#define WRMEM1_206_FLD4 GENMASK(63, 48) +#define WRMEM1_206_FLD5 GENMASK(79, 64) +#define WRMEM1_206_FLD6 GENMASK(95, 80) +#define WRMEM1_206_FLD7 GENMASK(111, 96) +#define WRMEM1_206_FLD8 GENMASK(127, 112) + +/* WRMEM1_207 register fields */ +#define WRMEM1_207_FLD1 GENMASK(15, 0) +#define WRMEM1_207_FLD2 GENMASK(31, 16) +#define WRMEM1_207_FLD3 GENMASK(47, 32) +#define WRMEM1_207_FLD4 GENMASK(63, 48) +#define WRMEM1_207_FLD5 GENMASK(79, 64) +#define WRMEM1_207_FLD6 GENMASK(95, 80) +#define WRMEM1_207_FLD7 GENMASK(111, 96) +#define WRMEM1_207_FLD8 GENMASK(127, 112) + +/* WRMEM1_208 register fields */ +#define WRMEM1_208_FLD1 GENMASK(15, 0) +#define WRMEM1_208_FLD2 GENMASK(31, 16) +#define WRMEM1_208_FLD3 GENMASK(47, 32) +#define WRMEM1_208_FLD4 GENMASK(63, 48) +#define WRMEM1_208_FLD5 GENMASK(79, 64) +#define WRMEM1_208_FLD6 GENMASK(95, 80) +#define WRMEM1_208_FLD7 GENMASK(111, 96) +#define WRMEM1_208_FLD8 GENMASK(127, 112) + +/* WRMEM1_209 register fields */ +#define WRMEM1_209_FLD1 GENMASK(15, 0) +#define WRMEM1_209_FLD2 GENMASK(31, 16) +#define WRMEM1_209_FLD3 GENMASK(47, 32) +#define WRMEM1_209_FLD4 GENMASK(63, 48) +#define WRMEM1_209_FLD5 GENMASK(79, 64) +#define WRMEM1_209_FLD6 GENMASK(95, 80) +#define WRMEM1_209_FLD7 GENMASK(111, 96) +#define WRMEM1_209_FLD8 GENMASK(127, 112) + +/* WRMEM1_210 register fields */ +#define WRMEM1_210_FLD1 GENMASK(15, 0) +#define WRMEM1_210_FLD2 GENMASK(31, 16) +#define WRMEM1_210_FLD3 GENMASK(47, 32) +#define WRMEM1_210_FLD4 GENMASK(63, 48) +#define WRMEM1_210_FLD5 GENMASK(79, 64) +#define WRMEM1_210_FLD6 GENMASK(95, 80) +#define WRMEM1_210_FLD7 GENMASK(111, 96) +#define WRMEM1_210_FLD8 GENMASK(127, 112) + +/* WRMEM1_211 register fields */ +#define WRMEM1_211_FLD1 GENMASK(15, 0) +#define WRMEM1_211_FLD2 GENMASK(31, 16) +#define WRMEM1_211_FLD3 GENMASK(47, 32) +#define WRMEM1_211_FLD4 GENMASK(63, 48) +#define WRMEM1_211_FLD5 GENMASK(79, 64) +#define WRMEM1_211_FLD6 GENMASK(95, 80) +#define WRMEM1_211_FLD7 GENMASK(111, 96) +#define WRMEM1_211_FLD8 GENMASK(127, 112) + +/* WRMEM1_212 register fields */ +#define WRMEM1_212_FLD1 GENMASK(15, 0) +#define WRMEM1_212_FLD2 GENMASK(31, 16) +#define WRMEM1_212_FLD3 GENMASK(47, 32) +#define WRMEM1_212_FLD4 GENMASK(63, 48) +#define WRMEM1_212_FLD5 GENMASK(79, 64) +#define WRMEM1_212_FLD6 GENMASK(95, 80) +#define WRMEM1_212_FLD7 GENMASK(111, 96) +#define WRMEM1_212_FLD8 GENMASK(127, 112) + +/* WRMEM1_213 register fields */ +#define WRMEM1_213_FLD1 GENMASK(15, 0) +#define WRMEM1_213_FLD2 GENMASK(31, 16) +#define WRMEM1_213_FLD3 GENMASK(47, 32) +#define WRMEM1_213_FLD4 GENMASK(63, 48) +#define WRMEM1_213_FLD5 GENMASK(79, 64) +#define WRMEM1_213_FLD6 GENMASK(95, 80) +#define WRMEM1_213_FLD7 GENMASK(111, 96) +#define WRMEM1_213_FLD8 GENMASK(127, 112) + +/* WRMEM1_214 register fields */ +#define WRMEM1_214_FLD1 GENMASK(15, 0) +#define WRMEM1_214_FLD2 GENMASK(31, 16) +#define WRMEM1_214_FLD3 GENMASK(47, 32) +#define WRMEM1_214_FLD4 GENMASK(63, 48) +#define WRMEM1_214_FLD5 GENMASK(79, 64) +#define WRMEM1_214_FLD6 GENMASK(95, 80) +#define WRMEM1_214_FLD7 GENMASK(111, 96) +#define WRMEM1_214_FLD8 GENMASK(127, 112) + +/* WRMEM1_215 register fields */ +#define WRMEM1_215_FLD1 GENMASK(15, 0) +#define WRMEM1_215_FLD2 GENMASK(31, 16) +#define WRMEM1_215_FLD3 GENMASK(47, 32) +#define WRMEM1_215_FLD4 GENMASK(63, 48) +#define WRMEM1_215_FLD5 GENMASK(79, 64) +#define WRMEM1_215_FLD6 GENMASK(95, 80) +#define WRMEM1_215_FLD7 GENMASK(111, 96) +#define WRMEM1_215_FLD8 GENMASK(127, 112) + +/* WRMEM1_216 register fields */ +#define WRMEM1_216_FLD1 GENMASK(15, 0) +#define WRMEM1_216_FLD2 GENMASK(31, 16) +#define WRMEM1_216_FLD3 GENMASK(47, 32) +#define WRMEM1_216_FLD4 GENMASK(63, 48) +#define WRMEM1_216_FLD5 GENMASK(79, 64) +#define WRMEM1_216_FLD6 GENMASK(95, 80) +#define WRMEM1_216_FLD7 GENMASK(111, 96) +#define WRMEM1_216_FLD8 GENMASK(127, 112) + +/* WRMEM1_217 register fields */ +#define WRMEM1_217_FLD1 GENMASK(15, 0) +#define WRMEM1_217_FLD2 GENMASK(31, 16) +#define WRMEM1_217_FLD3 GENMASK(47, 32) +#define WRMEM1_217_FLD4 GENMASK(63, 48) +#define WRMEM1_217_FLD5 GENMASK(79, 64) +#define WRMEM1_217_FLD6 GENMASK(95, 80) +#define WRMEM1_217_FLD7 GENMASK(111, 96) +#define WRMEM1_217_FLD8 GENMASK(127, 112) + +/* WRMEM1_218 register fields */ +#define WRMEM1_218_FLD1 GENMASK(15, 0) +#define WRMEM1_218_FLD2 GENMASK(31, 16) +#define WRMEM1_218_FLD3 GENMASK(47, 32) +#define WRMEM1_218_FLD4 GENMASK(63, 48) +#define WRMEM1_218_FLD5 GENMASK(79, 64) +#define WRMEM1_218_FLD6 GENMASK(95, 80) +#define WRMEM1_218_FLD7 GENMASK(111, 96) +#define WRMEM1_218_FLD8 GENMASK(127, 112) + +/* WRMEM1_219 register fields */ +#define WRMEM1_219_FLD1 GENMASK(15, 0) +#define WRMEM1_219_FLD2 GENMASK(31, 16) +#define WRMEM1_219_FLD3 GENMASK(47, 32) +#define WRMEM1_219_FLD4 GENMASK(63, 48) +#define WRMEM1_219_FLD5 GENMASK(79, 64) +#define WRMEM1_219_FLD6 GENMASK(95, 80) +#define WRMEM1_219_FLD7 GENMASK(111, 96) +#define WRMEM1_219_FLD8 GENMASK(127, 112) + +/* WRMEM1_220 register fields */ +#define WRMEM1_220_FLD1 GENMASK(15, 0) +#define WRMEM1_220_FLD2 GENMASK(31, 16) +#define WRMEM1_220_FLD3 GENMASK(47, 32) +#define WRMEM1_220_FLD4 GENMASK(63, 48) +#define WRMEM1_220_FLD5 GENMASK(79, 64) +#define WRMEM1_220_FLD6 GENMASK(95, 80) +#define WRMEM1_220_FLD7 GENMASK(111, 96) +#define WRMEM1_220_FLD8 GENMASK(127, 112) + +/* WRMEM1_221 register fields */ +#define WRMEM1_221_FLD1 GENMASK(15, 0) +#define WRMEM1_221_FLD2 GENMASK(31, 16) +#define WRMEM1_221_FLD3 GENMASK(47, 32) +#define WRMEM1_221_FLD4 GENMASK(63, 48) +#define WRMEM1_221_FLD5 GENMASK(79, 64) +#define WRMEM1_221_FLD6 GENMASK(95, 80) +#define WRMEM1_221_FLD7 GENMASK(111, 96) +#define WRMEM1_221_FLD8 GENMASK(127, 112) + +/* WRMEM1_222 register fields */ +#define WRMEM1_222_FLD1 GENMASK(15, 0) +#define WRMEM1_222_FLD2 GENMASK(31, 16) +#define WRMEM1_222_FLD3 GENMASK(47, 32) +#define WRMEM1_222_FLD4 GENMASK(63, 48) +#define WRMEM1_222_FLD5 GENMASK(79, 64) +#define WRMEM1_222_FLD6 GENMASK(95, 80) +#define WRMEM1_222_FLD7 GENMASK(111, 96) +#define WRMEM1_222_FLD8 GENMASK(127, 112) + +/* WRMEM1_223 register fields */ +#define WRMEM1_223_FLD1 GENMASK(15, 0) +#define WRMEM1_223_FLD2 GENMASK(31, 16) +#define WRMEM1_223_FLD3 GENMASK(47, 32) +#define WRMEM1_223_FLD4 GENMASK(63, 48) +#define WRMEM1_223_FLD5 GENMASK(79, 64) +#define WRMEM1_223_FLD6 GENMASK(95, 80) +#define WRMEM1_223_FLD7 GENMASK(111, 96) +#define WRMEM1_223_FLD8 GENMASK(127, 112) + +/* WRMEM1_224 register fields */ +#define WRMEM1_224_FLD1 GENMASK(15, 0) +#define WRMEM1_224_FLD2 GENMASK(31, 16) +#define WRMEM1_224_FLD3 GENMASK(47, 32) +#define WRMEM1_224_FLD4 GENMASK(63, 48) +#define WRMEM1_224_FLD5 GENMASK(79, 64) +#define WRMEM1_224_FLD6 GENMASK(95, 80) +#define WRMEM1_224_FLD7 GENMASK(111, 96) +#define WRMEM1_224_FLD8 GENMASK(127, 112) + +/* WRMEM1_225 register fields */ +#define WRMEM1_225_FLD1 GENMASK(15, 0) +#define WRMEM1_225_FLD2 GENMASK(31, 16) +#define WRMEM1_225_FLD3 GENMASK(47, 32) +#define WRMEM1_225_FLD4 GENMASK(63, 48) +#define WRMEM1_225_FLD5 GENMASK(79, 64) +#define WRMEM1_225_FLD6 GENMASK(95, 80) +#define WRMEM1_225_FLD7 GENMASK(111, 96) +#define WRMEM1_225_FLD8 GENMASK(127, 112) + +/* WRMEM1_226 register fields */ +#define WRMEM1_226_FLD1 GENMASK(15, 0) +#define WRMEM1_226_FLD2 GENMASK(31, 16) +#define WRMEM1_226_FLD3 GENMASK(47, 32) +#define WRMEM1_226_FLD4 GENMASK(63, 48) +#define WRMEM1_226_FLD5 GENMASK(79, 64) +#define WRMEM1_226_FLD6 GENMASK(95, 80) +#define WRMEM1_226_FLD7 GENMASK(111, 96) +#define WRMEM1_226_FLD8 GENMASK(127, 112) + +/* WRMEM1_227 register fields */ +#define WRMEM1_227_FLD1 GENMASK(15, 0) +#define WRMEM1_227_FLD2 GENMASK(31, 16) +#define WRMEM1_227_FLD3 GENMASK(47, 32) +#define WRMEM1_227_FLD4 GENMASK(63, 48) +#define WRMEM1_227_FLD5 GENMASK(79, 64) +#define WRMEM1_227_FLD6 GENMASK(95, 80) +#define WRMEM1_227_FLD7 GENMASK(111, 96) +#define WRMEM1_227_FLD8 GENMASK(127, 112) + +/* WRMEM1_228 register fields */ +#define WRMEM1_228_FLD1 GENMASK(15, 0) +#define WRMEM1_228_FLD2 GENMASK(31, 16) +#define WRMEM1_228_FLD3 GENMASK(47, 32) +#define WRMEM1_228_FLD4 GENMASK(63, 48) +#define WRMEM1_228_FLD5 GENMASK(79, 64) +#define WRMEM1_228_FLD6 GENMASK(95, 80) +#define WRMEM1_228_FLD7 GENMASK(111, 96) +#define WRMEM1_228_FLD8 GENMASK(127, 112) + +/* WRMEM1_229 register fields */ +#define WRMEM1_229_FLD1 GENMASK(15, 0) +#define WRMEM1_229_FLD2 GENMASK(31, 16) +#define WRMEM1_229_FLD3 GENMASK(47, 32) +#define WRMEM1_229_FLD4 GENMASK(63, 48) +#define WRMEM1_229_FLD5 GENMASK(79, 64) +#define WRMEM1_229_FLD6 GENMASK(95, 80) +#define WRMEM1_229_FLD7 GENMASK(111, 96) +#define WRMEM1_229_FLD8 GENMASK(127, 112) + +/* WRMEM1_230 register fields */ +#define WRMEM1_230_FLD1 GENMASK(15, 0) +#define WRMEM1_230_FLD2 GENMASK(31, 16) +#define WRMEM1_230_FLD3 GENMASK(47, 32) +#define WRMEM1_230_FLD4 GENMASK(63, 48) +#define WRMEM1_230_FLD5 GENMASK(79, 64) +#define WRMEM1_230_FLD6 GENMASK(95, 80) +#define WRMEM1_230_FLD7 GENMASK(111, 96) +#define WRMEM1_230_FLD8 GENMASK(127, 112) + +/* WRMEM1_231 register fields */ +#define WRMEM1_231_FLD1 GENMASK(15, 0) +#define WRMEM1_231_FLD2 GENMASK(31, 16) +#define WRMEM1_231_FLD3 GENMASK(47, 32) +#define WRMEM1_231_FLD4 GENMASK(63, 48) +#define WRMEM1_231_FLD5 GENMASK(79, 64) +#define WRMEM1_231_FLD6 GENMASK(95, 80) +#define WRMEM1_231_FLD7 GENMASK(111, 96) +#define WRMEM1_231_FLD8 GENMASK(127, 112) + +/* WRMEM1_232 register fields */ +#define WRMEM1_232_FLD1 GENMASK(15, 0) +#define WRMEM1_232_FLD2 GENMASK(31, 16) +#define WRMEM1_232_FLD3 GENMASK(47, 32) +#define WRMEM1_232_FLD4 GENMASK(63, 48) +#define WRMEM1_232_FLD5 GENMASK(79, 64) +#define WRMEM1_232_FLD6 GENMASK(95, 80) +#define WRMEM1_232_FLD7 GENMASK(111, 96) +#define WRMEM1_232_FLD8 GENMASK(127, 112) + +/* WRMEM1_233 register fields */ +#define WRMEM1_233_FLD1 GENMASK(15, 0) +#define WRMEM1_233_FLD2 GENMASK(31, 16) +#define WRMEM1_233_FLD3 GENMASK(47, 32) +#define WRMEM1_233_FLD4 GENMASK(63, 48) +#define WRMEM1_233_FLD5 GENMASK(79, 64) +#define WRMEM1_233_FLD6 GENMASK(95, 80) +#define WRMEM1_233_FLD7 GENMASK(111, 96) +#define WRMEM1_233_FLD8 GENMASK(127, 112) + +/* WRMEM1_234 register fields */ +#define WRMEM1_234_FLD1 GENMASK(15, 0) +#define WRMEM1_234_FLD2 GENMASK(31, 16) +#define WRMEM1_234_FLD3 GENMASK(47, 32) +#define WRMEM1_234_FLD4 GENMASK(63, 48) +#define WRMEM1_234_FLD5 GENMASK(79, 64) +#define WRMEM1_234_FLD6 GENMASK(95, 80) +#define WRMEM1_234_FLD7 GENMASK(111, 96) +#define WRMEM1_234_FLD8 GENMASK(127, 112) + +/* WRMEM1_235 register fields */ +#define WRMEM1_235_FLD1 GENMASK(15, 0) +#define WRMEM1_235_FLD2 GENMASK(31, 16) +#define WRMEM1_235_FLD3 GENMASK(47, 32) +#define WRMEM1_235_FLD4 GENMASK(63, 48) +#define WRMEM1_235_FLD5 GENMASK(79, 64) +#define WRMEM1_235_FLD6 GENMASK(95, 80) +#define WRMEM1_235_FLD7 GENMASK(111, 96) +#define WRMEM1_235_FLD8 GENMASK(127, 112) + +/* WRMEM1_236 register fields */ +#define WRMEM1_236_FLD1 GENMASK(15, 0) +#define WRMEM1_236_FLD2 GENMASK(31, 16) +#define WRMEM1_236_FLD3 GENMASK(47, 32) +#define WRMEM1_236_FLD4 GENMASK(63, 48) +#define WRMEM1_236_FLD5 GENMASK(79, 64) +#define WRMEM1_236_FLD6 GENMASK(95, 80) +#define WRMEM1_236_FLD7 GENMASK(111, 96) +#define WRMEM1_236_FLD8 GENMASK(127, 112) + +/* WRMEM1_237 register fields */ +#define WRMEM1_237_FLD1 GENMASK(15, 0) +#define WRMEM1_237_FLD2 GENMASK(31, 16) +#define WRMEM1_237_FLD3 GENMASK(47, 32) +#define WRMEM1_237_FLD4 GENMASK(63, 48) +#define WRMEM1_237_FLD5 GENMASK(79, 64) +#define WRMEM1_237_FLD6 GENMASK(95, 80) +#define WRMEM1_237_FLD7 GENMASK(111, 96) +#define WRMEM1_237_FLD8 GENMASK(127, 112) + +/* WRMEM1_238 register fields */ +#define WRMEM1_238_FLD1 GENMASK(15, 0) +#define WRMEM1_238_FLD2 GENMASK(31, 16) +#define WRMEM1_238_FLD3 GENMASK(47, 32) +#define WRMEM1_238_FLD4 GENMASK(63, 48) +#define WRMEM1_238_FLD5 GENMASK(79, 64) +#define WRMEM1_238_FLD6 GENMASK(95, 80) +#define WRMEM1_238_FLD7 GENMASK(111, 96) +#define WRMEM1_238_FLD8 GENMASK(127, 112) + +/* WRMEM1_239 register fields */ +#define WRMEM1_239_FLD1 GENMASK(15, 0) +#define WRMEM1_239_FLD2 GENMASK(31, 16) +#define WRMEM1_239_FLD3 GENMASK(47, 32) +#define WRMEM1_239_FLD4 GENMASK(63, 48) +#define WRMEM1_239_FLD5 GENMASK(79, 64) +#define WRMEM1_239_FLD6 GENMASK(95, 80) +#define WRMEM1_239_FLD7 GENMASK(111, 96) +#define WRMEM1_239_FLD8 GENMASK(127, 112) + +/* WRMEM1_240 register fields */ +#define WRMEM1_240_FLD1 GENMASK(15, 0) +#define WRMEM1_240_FLD2 GENMASK(31, 16) +#define WRMEM1_240_FLD3 GENMASK(47, 32) +#define WRMEM1_240_FLD4 GENMASK(63, 48) +#define WRMEM1_240_FLD5 GENMASK(79, 64) +#define WRMEM1_240_FLD6 GENMASK(95, 80) +#define WRMEM1_240_FLD7 GENMASK(111, 96) +#define WRMEM1_240_FLD8 GENMASK(127, 112) + +/* WRMEM1_241 register fields */ +#define WRMEM1_241_FLD1 GENMASK(15, 0) +#define WRMEM1_241_FLD2 GENMASK(31, 16) +#define WRMEM1_241_FLD3 GENMASK(47, 32) +#define WRMEM1_241_FLD4 GENMASK(63, 48) +#define WRMEM1_241_FLD5 GENMASK(79, 64) +#define WRMEM1_241_FLD6 GENMASK(95, 80) +#define WRMEM1_241_FLD7 GENMASK(111, 96) +#define WRMEM1_241_FLD8 GENMASK(127, 112) + +/* WRMEM1_242 register fields */ +#define WRMEM1_242_FLD1 GENMASK(15, 0) +#define WRMEM1_242_FLD2 GENMASK(31, 16) +#define WRMEM1_242_FLD3 GENMASK(47, 32) +#define WRMEM1_242_FLD4 GENMASK(63, 48) +#define WRMEM1_242_FLD5 GENMASK(79, 64) +#define WRMEM1_242_FLD6 GENMASK(95, 80) +#define WRMEM1_242_FLD7 GENMASK(111, 96) +#define WRMEM1_242_FLD8 GENMASK(127, 112) + +/* WRMEM1_243 register fields */ +#define WRMEM1_243_FLD1 GENMASK(15, 0) +#define WRMEM1_243_FLD2 GENMASK(31, 16) +#define WRMEM1_243_FLD3 GENMASK(47, 32) +#define WRMEM1_243_FLD4 GENMASK(63, 48) +#define WRMEM1_243_FLD5 GENMASK(79, 64) +#define WRMEM1_243_FLD6 GENMASK(95, 80) +#define WRMEM1_243_FLD7 GENMASK(111, 96) +#define WRMEM1_243_FLD8 GENMASK(127, 112) + +/* WRMEM1_244 register fields */ +#define WRMEM1_244_FLD1 GENMASK(15, 0) +#define WRMEM1_244_FLD2 GENMASK(31, 16) +#define WRMEM1_244_FLD3 GENMASK(47, 32) +#define WRMEM1_244_FLD4 GENMASK(63, 48) +#define WRMEM1_244_FLD5 GENMASK(79, 64) +#define WRMEM1_244_FLD6 GENMASK(95, 80) +#define WRMEM1_244_FLD7 GENMASK(111, 96) +#define WRMEM1_244_FLD8 GENMASK(127, 112) + +/* WRMEM1_245 register fields */ +#define WRMEM1_245_FLD1 GENMASK(15, 0) +#define WRMEM1_245_FLD2 GENMASK(31, 16) +#define WRMEM1_245_FLD3 GENMASK(47, 32) +#define WRMEM1_245_FLD4 GENMASK(63, 48) +#define WRMEM1_245_FLD5 GENMASK(79, 64) +#define WRMEM1_245_FLD6 GENMASK(95, 80) +#define WRMEM1_245_FLD7 GENMASK(111, 96) +#define WRMEM1_245_FLD8 GENMASK(127, 112) + +/* WRMEM1_246 register fields */ +#define WRMEM1_246_FLD1 GENMASK(15, 0) +#define WRMEM1_246_FLD2 GENMASK(31, 16) +#define WRMEM1_246_FLD3 GENMASK(47, 32) +#define WRMEM1_246_FLD4 GENMASK(63, 48) +#define WRMEM1_246_FLD5 GENMASK(79, 64) +#define WRMEM1_246_FLD6 GENMASK(95, 80) +#define WRMEM1_246_FLD7 GENMASK(111, 96) +#define WRMEM1_246_FLD8 GENMASK(127, 112) + +/* WRMEM1_247 register fields */ +#define WRMEM1_247_FLD1 GENMASK(15, 0) +#define WRMEM1_247_FLD2 GENMASK(31, 16) +#define WRMEM1_247_FLD3 GENMASK(47, 32) +#define WRMEM1_247_FLD4 GENMASK(63, 48) +#define WRMEM1_247_FLD5 GENMASK(79, 64) +#define WRMEM1_247_FLD6 GENMASK(95, 80) +#define WRMEM1_247_FLD7 GENMASK(111, 96) +#define WRMEM1_247_FLD8 GENMASK(127, 112) + +/* WRMEM1_248 register fields */ +#define WRMEM1_248_FLD1 GENMASK(15, 0) +#define WRMEM1_248_FLD2 GENMASK(31, 16) +#define WRMEM1_248_FLD3 GENMASK(47, 32) +#define WRMEM1_248_FLD4 GENMASK(63, 48) +#define WRMEM1_248_FLD5 GENMASK(79, 64) +#define WRMEM1_248_FLD6 GENMASK(95, 80) +#define WRMEM1_248_FLD7 GENMASK(111, 96) +#define WRMEM1_248_FLD8 GENMASK(127, 112) + +/* WRMEM1_249 register fields */ +#define WRMEM1_249_FLD1 GENMASK(15, 0) +#define WRMEM1_249_FLD2 GENMASK(31, 16) +#define WRMEM1_249_FLD3 GENMASK(47, 32) +#define WRMEM1_249_FLD4 GENMASK(63, 48) +#define WRMEM1_249_FLD5 GENMASK(79, 64) +#define WRMEM1_249_FLD6 GENMASK(95, 80) +#define WRMEM1_249_FLD7 GENMASK(111, 96) +#define WRMEM1_249_FLD8 GENMASK(127, 112) + +/* WRMEM1_250 register fields */ +#define WRMEM1_250_FLD1 GENMASK(15, 0) +#define WRMEM1_250_FLD2 GENMASK(31, 16) +#define WRMEM1_250_FLD3 GENMASK(47, 32) +#define WRMEM1_250_FLD4 GENMASK(63, 48) +#define WRMEM1_250_FLD5 GENMASK(79, 64) +#define WRMEM1_250_FLD6 GENMASK(95, 80) +#define WRMEM1_250_FLD7 GENMASK(111, 96) +#define WRMEM1_250_FLD8 GENMASK(127, 112) + +/* WRMEM1_251 register fields */ +#define WRMEM1_251_FLD1 GENMASK(15, 0) +#define WRMEM1_251_FLD2 GENMASK(31, 16) +#define WRMEM1_251_FLD3 GENMASK(47, 32) +#define WRMEM1_251_FLD4 GENMASK(63, 48) +#define WRMEM1_251_FLD5 GENMASK(79, 64) +#define WRMEM1_251_FLD6 GENMASK(95, 80) +#define WRMEM1_251_FLD7 GENMASK(111, 96) +#define WRMEM1_251_FLD8 GENMASK(127, 112) + +/* WRMEM1_252 register fields */ +#define WRMEM1_252_FLD1 GENMASK(15, 0) +#define WRMEM1_252_FLD2 GENMASK(31, 16) +#define WRMEM1_252_FLD3 GENMASK(47, 32) +#define WRMEM1_252_FLD4 GENMASK(63, 48) +#define WRMEM1_252_FLD5 GENMASK(79, 64) +#define WRMEM1_252_FLD6 GENMASK(95, 80) +#define WRMEM1_252_FLD7 GENMASK(111, 96) +#define WRMEM1_252_FLD8 GENMASK(127, 112) + +/* WRMEM1_253 register fields */ +#define WRMEM1_253_FLD1 GENMASK(15, 0) +#define WRMEM1_253_FLD2 GENMASK(31, 16) +#define WRMEM1_253_FLD3 GENMASK(47, 32) +#define WRMEM1_253_FLD4 GENMASK(63, 48) +#define WRMEM1_253_FLD5 GENMASK(79, 64) +#define WRMEM1_253_FLD6 GENMASK(95, 80) +#define WRMEM1_253_FLD7 GENMASK(111, 96) +#define WRMEM1_253_FLD8 GENMASK(127, 112) + +/* WRMEM1_254 register fields */ +#define WRMEM1_254_FLD1 GENMASK(15, 0) +#define WRMEM1_254_FLD2 GENMASK(31, 16) +#define WRMEM1_254_FLD3 GENMASK(47, 32) +#define WRMEM1_254_FLD4 GENMASK(63, 48) +#define WRMEM1_254_FLD5 GENMASK(79, 64) +#define WRMEM1_254_FLD6 GENMASK(95, 80) +#define WRMEM1_254_FLD7 GENMASK(111, 96) +#define WRMEM1_254_FLD8 GENMASK(127, 112) + +/* WRMEM1_255 register fields */ +#define WRMEM1_255_FLD1 GENMASK(15, 0) +#define WRMEM1_255_FLD2 GENMASK(31, 16) +#define WRMEM1_255_FLD3 GENMASK(47, 32) +#define WRMEM1_255_FLD4 GENMASK(63, 48) +#define WRMEM1_255_FLD5 GENMASK(79, 64) +#define WRMEM1_255_FLD6 GENMASK(95, 80) +#define WRMEM1_255_FLD7 GENMASK(111, 96) +#define WRMEM1_255_FLD8 GENMASK(127, 112) + +/* WRMEM1_256 register fields */ +#define WRMEM1_256_FLD1 GENMASK(15, 0) +#define WRMEM1_256_FLD2 GENMASK(31, 16) +#define WRMEM1_256_FLD3 GENMASK(47, 32) +#define WRMEM1_256_FLD4 GENMASK(63, 48) +#define WRMEM1_256_FLD5 GENMASK(79, 64) +#define WRMEM1_256_FLD6 GENMASK(95, 80) +#define WRMEM1_256_FLD7 GENMASK(111, 96) +#define WRMEM1_256_FLD8 GENMASK(127, 112) + +/* WRMEM1_257 register fields */ +#define WRMEM1_257_FLD1 GENMASK(15, 0) +#define WRMEM1_257_FLD2 GENMASK(31, 16) +#define WRMEM1_257_FLD3 GENMASK(47, 32) +#define WRMEM1_257_FLD4 GENMASK(63, 48) +#define WRMEM1_257_FLD5 GENMASK(79, 64) +#define WRMEM1_257_FLD6 GENMASK(95, 80) +#define WRMEM1_257_FLD7 GENMASK(111, 96) +#define WRMEM1_257_FLD8 GENMASK(127, 112) + +/* WRMEM1_258 register fields */ +#define WRMEM1_258_FLD1 GENMASK(15, 0) +#define WRMEM1_258_FLD2 GENMASK(31, 16) +#define WRMEM1_258_FLD3 GENMASK(47, 32) +#define WRMEM1_258_FLD4 GENMASK(63, 48) +#define WRMEM1_258_FLD5 GENMASK(79, 64) +#define WRMEM1_258_FLD6 GENMASK(95, 80) +#define WRMEM1_258_FLD7 GENMASK(111, 96) +#define WRMEM1_258_FLD8 GENMASK(127, 112) + +/* WRMEM1_259 register fields */ +#define WRMEM1_259_FLD1 GENMASK(15, 0) +#define WRMEM1_259_FLD2 GENMASK(31, 16) +#define WRMEM1_259_FLD3 GENMASK(47, 32) +#define WRMEM1_259_FLD4 GENMASK(63, 48) +#define WRMEM1_259_FLD5 GENMASK(79, 64) +#define WRMEM1_259_FLD6 GENMASK(95, 80) +#define WRMEM1_259_FLD7 GENMASK(111, 96) +#define WRMEM1_259_FLD8 GENMASK(127, 112) + +/* WRMEM1_260 register fields */ +#define WRMEM1_260_FLD1 GENMASK(15, 0) +#define WRMEM1_260_FLD2 GENMASK(31, 16) +#define WRMEM1_260_FLD3 GENMASK(47, 32) +#define WRMEM1_260_FLD4 GENMASK(63, 48) +#define WRMEM1_260_FLD5 GENMASK(79, 64) +#define WRMEM1_260_FLD6 GENMASK(95, 80) +#define WRMEM1_260_FLD7 GENMASK(111, 96) +#define WRMEM1_260_FLD8 GENMASK(127, 112) + +/* WRMEM1_261 register fields */ +#define WRMEM1_261_FLD1 GENMASK(15, 0) +#define WRMEM1_261_FLD2 GENMASK(31, 16) +#define WRMEM1_261_FLD3 GENMASK(47, 32) +#define WRMEM1_261_FLD4 GENMASK(63, 48) +#define WRMEM1_261_FLD5 GENMASK(79, 64) +#define WRMEM1_261_FLD6 GENMASK(95, 80) +#define WRMEM1_261_FLD7 GENMASK(111, 96) +#define WRMEM1_261_FLD8 GENMASK(127, 112) + +/* WRMEM1_262 register fields */ +#define WRMEM1_262_FLD1 GENMASK(15, 0) +#define WRMEM1_262_FLD2 GENMASK(31, 16) +#define WRMEM1_262_FLD3 GENMASK(47, 32) +#define WRMEM1_262_FLD4 GENMASK(63, 48) +#define WRMEM1_262_FLD5 GENMASK(79, 64) +#define WRMEM1_262_FLD6 GENMASK(95, 80) +#define WRMEM1_262_FLD7 GENMASK(111, 96) +#define WRMEM1_262_FLD8 GENMASK(127, 112) + +/* WRMEM1_263 register fields */ +#define WRMEM1_263_FLD1 GENMASK(15, 0) +#define WRMEM1_263_FLD2 GENMASK(31, 16) +#define WRMEM1_263_FLD3 GENMASK(47, 32) +#define WRMEM1_263_FLD4 GENMASK(63, 48) +#define WRMEM1_263_FLD5 GENMASK(79, 64) +#define WRMEM1_263_FLD6 GENMASK(95, 80) +#define WRMEM1_263_FLD7 GENMASK(111, 96) +#define WRMEM1_263_FLD8 GENMASK(127, 112) + +/* WRMEM1_264 register fields */ +#define WRMEM1_264_FLD1 GENMASK(15, 0) +#define WRMEM1_264_FLD2 GENMASK(31, 16) +#define WRMEM1_264_FLD3 GENMASK(47, 32) +#define WRMEM1_264_FLD4 GENMASK(63, 48) +#define WRMEM1_264_FLD5 GENMASK(79, 64) +#define WRMEM1_264_FLD6 GENMASK(95, 80) +#define WRMEM1_264_FLD7 GENMASK(111, 96) +#define WRMEM1_264_FLD8 GENMASK(127, 112) + +/* WRMEM1_265 register fields */ +#define WRMEM1_265_FLD1 GENMASK(15, 0) +#define WRMEM1_265_FLD2 GENMASK(31, 16) +#define WRMEM1_265_FLD3 GENMASK(47, 32) +#define WRMEM1_265_FLD4 GENMASK(63, 48) +#define WRMEM1_265_FLD5 GENMASK(79, 64) +#define WRMEM1_265_FLD6 GENMASK(95, 80) +#define WRMEM1_265_FLD7 GENMASK(111, 96) +#define WRMEM1_265_FLD8 GENMASK(127, 112) + +/* WRMEM1_266 register fields */ +#define WRMEM1_266_FLD1 GENMASK(15, 0) +#define WRMEM1_266_FLD2 GENMASK(31, 16) +#define WRMEM1_266_FLD3 GENMASK(47, 32) +#define WRMEM1_266_FLD4 GENMASK(63, 48) +#define WRMEM1_266_FLD5 GENMASK(79, 64) +#define WRMEM1_266_FLD6 GENMASK(95, 80) +#define WRMEM1_266_FLD7 GENMASK(111, 96) +#define WRMEM1_266_FLD8 GENMASK(127, 112) + +/* WRMEM1_267 register fields */ +#define WRMEM1_267_FLD1 GENMASK(15, 0) +#define WRMEM1_267_FLD2 GENMASK(31, 16) +#define WRMEM1_267_FLD3 GENMASK(47, 32) +#define WRMEM1_267_FLD4 GENMASK(63, 48) +#define WRMEM1_267_FLD5 GENMASK(79, 64) +#define WRMEM1_267_FLD6 GENMASK(95, 80) +#define WRMEM1_267_FLD7 GENMASK(111, 96) +#define WRMEM1_267_FLD8 GENMASK(127, 112) + +/* WRMEM1_268 register fields */ +#define WRMEM1_268_FLD1 GENMASK(15, 0) +#define WRMEM1_268_FLD2 GENMASK(31, 16) +#define WRMEM1_268_FLD3 GENMASK(47, 32) +#define WRMEM1_268_FLD4 GENMASK(63, 48) +#define WRMEM1_268_FLD5 GENMASK(79, 64) +#define WRMEM1_268_FLD6 GENMASK(95, 80) +#define WRMEM1_268_FLD7 GENMASK(111, 96) +#define WRMEM1_268_FLD8 GENMASK(127, 112) + +/* WRMEM1_269 register fields */ +#define WRMEM1_269_FLD1 GENMASK(15, 0) +#define WRMEM1_269_FLD2 GENMASK(31, 16) +#define WRMEM1_269_FLD3 GENMASK(47, 32) +#define WRMEM1_269_FLD4 GENMASK(63, 48) +#define WRMEM1_269_FLD5 GENMASK(79, 64) +#define WRMEM1_269_FLD6 GENMASK(95, 80) +#define WRMEM1_269_FLD7 GENMASK(111, 96) +#define WRMEM1_269_FLD8 GENMASK(127, 112) + +/* WRMEM1_270 register fields */ +#define WRMEM1_270_FLD1 GENMASK(15, 0) +#define WRMEM1_270_FLD2 GENMASK(31, 16) +#define WRMEM1_270_FLD3 GENMASK(47, 32) +#define WRMEM1_270_FLD4 GENMASK(63, 48) +#define WRMEM1_270_FLD5 GENMASK(79, 64) +#define WRMEM1_270_FLD6 GENMASK(95, 80) +#define WRMEM1_270_FLD7 GENMASK(111, 96) +#define WRMEM1_270_FLD8 GENMASK(127, 112) + +/* WRMEM1_271 register fields */ +#define WRMEM1_271_FLD1 GENMASK(15, 0) +#define WRMEM1_271_FLD2 GENMASK(31, 16) +#define WRMEM1_271_FLD3 GENMASK(47, 32) +#define WRMEM1_271_FLD4 GENMASK(63, 48) +#define WRMEM1_271_FLD5 GENMASK(79, 64) +#define WRMEM1_271_FLD6 GENMASK(95, 80) +#define WRMEM1_271_FLD7 GENMASK(111, 96) +#define WRMEM1_271_FLD8 GENMASK(127, 112) + +/* WRMEM1_272 register fields */ +#define WRMEM1_272_FLD1 GENMASK(15, 0) +#define WRMEM1_272_FLD2 GENMASK(31, 16) +#define WRMEM1_272_FLD3 GENMASK(47, 32) +#define WRMEM1_272_FLD4 GENMASK(63, 48) +#define WRMEM1_272_FLD5 GENMASK(79, 64) +#define WRMEM1_272_FLD6 GENMASK(95, 80) +#define WRMEM1_272_FLD7 GENMASK(111, 96) +#define WRMEM1_272_FLD8 GENMASK(127, 112) + +/* WRMEM1_273 register fields */ +#define WRMEM1_273_FLD1 GENMASK(15, 0) +#define WRMEM1_273_FLD2 GENMASK(31, 16) +#define WRMEM1_273_FLD3 GENMASK(47, 32) +#define WRMEM1_273_FLD4 GENMASK(63, 48) +#define WRMEM1_273_FLD5 GENMASK(79, 64) +#define WRMEM1_273_FLD6 GENMASK(95, 80) +#define WRMEM1_273_FLD7 GENMASK(111, 96) +#define WRMEM1_273_FLD8 GENMASK(127, 112) + +/* WRMEM1_274 register fields */ +#define WRMEM1_274_FLD1 GENMASK(15, 0) +#define WRMEM1_274_FLD2 GENMASK(31, 16) +#define WRMEM1_274_FLD3 GENMASK(47, 32) +#define WRMEM1_274_FLD4 GENMASK(63, 48) +#define WRMEM1_274_FLD5 GENMASK(79, 64) +#define WRMEM1_274_FLD6 GENMASK(95, 80) +#define WRMEM1_274_FLD7 GENMASK(111, 96) +#define WRMEM1_274_FLD8 GENMASK(127, 112) + +/* WRMEM1_275 register fields */ +#define WRMEM1_275_FLD1 GENMASK(15, 0) +#define WRMEM1_275_FLD2 GENMASK(31, 16) +#define WRMEM1_275_FLD3 GENMASK(47, 32) +#define WRMEM1_275_FLD4 GENMASK(63, 48) +#define WRMEM1_275_FLD5 GENMASK(79, 64) +#define WRMEM1_275_FLD6 GENMASK(95, 80) +#define WRMEM1_275_FLD7 GENMASK(111, 96) +#define WRMEM1_275_FLD8 GENMASK(127, 112) + +/* WRMEM1_276 register fields */ +#define WRMEM1_276_FLD1 GENMASK(15, 0) +#define WRMEM1_276_FLD2 GENMASK(31, 16) +#define WRMEM1_276_FLD3 GENMASK(47, 32) +#define WRMEM1_276_FLD4 GENMASK(63, 48) +#define WRMEM1_276_FLD5 GENMASK(79, 64) +#define WRMEM1_276_FLD6 GENMASK(95, 80) +#define WRMEM1_276_FLD7 GENMASK(111, 96) +#define WRMEM1_276_FLD8 GENMASK(127, 112) + +/* WRMEM1_277 register fields */ +#define WRMEM1_277_FLD1 GENMASK(15, 0) +#define WRMEM1_277_FLD2 GENMASK(31, 16) +#define WRMEM1_277_FLD3 GENMASK(47, 32) +#define WRMEM1_277_FLD4 GENMASK(63, 48) +#define WRMEM1_277_FLD5 GENMASK(79, 64) +#define WRMEM1_277_FLD6 GENMASK(95, 80) +#define WRMEM1_277_FLD7 GENMASK(111, 96) +#define WRMEM1_277_FLD8 GENMASK(127, 112) + +/* WRMEM1_278 register fields */ +#define WRMEM1_278_FLD1 GENMASK(15, 0) +#define WRMEM1_278_FLD2 GENMASK(31, 16) +#define WRMEM1_278_FLD3 GENMASK(47, 32) +#define WRMEM1_278_FLD4 GENMASK(63, 48) +#define WRMEM1_278_FLD5 GENMASK(79, 64) +#define WRMEM1_278_FLD6 GENMASK(95, 80) +#define WRMEM1_278_FLD7 GENMASK(111, 96) +#define WRMEM1_278_FLD8 GENMASK(127, 112) + +/* WRMEM1_279 register fields */ +#define WRMEM1_279_FLD1 GENMASK(15, 0) +#define WRMEM1_279_FLD2 GENMASK(31, 16) +#define WRMEM1_279_FLD3 GENMASK(47, 32) +#define WRMEM1_279_FLD4 GENMASK(63, 48) +#define WRMEM1_279_FLD5 GENMASK(79, 64) +#define WRMEM1_279_FLD6 GENMASK(95, 80) +#define WRMEM1_279_FLD7 GENMASK(111, 96) +#define WRMEM1_279_FLD8 GENMASK(127, 112) + +/* WRMEM1_280 register fields */ +#define WRMEM1_280_FLD1 GENMASK(15, 0) +#define WRMEM1_280_FLD2 GENMASK(31, 16) +#define WRMEM1_280_FLD3 GENMASK(47, 32) +#define WRMEM1_280_FLD4 GENMASK(63, 48) +#define WRMEM1_280_FLD5 GENMASK(79, 64) +#define WRMEM1_280_FLD6 GENMASK(95, 80) +#define WRMEM1_280_FLD7 GENMASK(111, 96) +#define WRMEM1_280_FLD8 GENMASK(127, 112) + +/* WRMEM1_281 register fields */ +#define WRMEM1_281_FLD1 GENMASK(15, 0) +#define WRMEM1_281_FLD2 GENMASK(31, 16) +#define WRMEM1_281_FLD3 GENMASK(47, 32) +#define WRMEM1_281_FLD4 GENMASK(63, 48) +#define WRMEM1_281_FLD5 GENMASK(79, 64) +#define WRMEM1_281_FLD6 GENMASK(95, 80) +#define WRMEM1_281_FLD7 GENMASK(111, 96) +#define WRMEM1_281_FLD8 GENMASK(127, 112) + +/* WRMEM1_282 register fields */ +#define WRMEM1_282_FLD1 GENMASK(15, 0) +#define WRMEM1_282_FLD2 GENMASK(31, 16) +#define WRMEM1_282_FLD3 GENMASK(47, 32) +#define WRMEM1_282_FLD4 GENMASK(63, 48) +#define WRMEM1_282_FLD5 GENMASK(79, 64) +#define WRMEM1_282_FLD6 GENMASK(95, 80) +#define WRMEM1_282_FLD7 GENMASK(111, 96) +#define WRMEM1_282_FLD8 GENMASK(127, 112) + +/* WRMEM1_283 register fields */ +#define WRMEM1_283_FLD1 GENMASK(15, 0) +#define WRMEM1_283_FLD2 GENMASK(31, 16) +#define WRMEM1_283_FLD3 GENMASK(47, 32) +#define WRMEM1_283_FLD4 GENMASK(63, 48) +#define WRMEM1_283_FLD5 GENMASK(79, 64) +#define WRMEM1_283_FLD6 GENMASK(95, 80) +#define WRMEM1_283_FLD7 GENMASK(111, 96) +#define WRMEM1_283_FLD8 GENMASK(127, 112) + +/* WRMEM1_284 register fields */ +#define WRMEM1_284_FLD1 GENMASK(15, 0) +#define WRMEM1_284_FLD2 GENMASK(31, 16) +#define WRMEM1_284_FLD3 GENMASK(47, 32) +#define WRMEM1_284_FLD4 GENMASK(63, 48) +#define WRMEM1_284_FLD5 GENMASK(79, 64) +#define WRMEM1_284_FLD6 GENMASK(95, 80) +#define WRMEM1_284_FLD7 GENMASK(111, 96) +#define WRMEM1_284_FLD8 GENMASK(127, 112) + +/* WRMEM1_285 register fields */ +#define WRMEM1_285_FLD1 GENMASK(15, 0) +#define WRMEM1_285_FLD2 GENMASK(31, 16) +#define WRMEM1_285_FLD3 GENMASK(47, 32) +#define WRMEM1_285_FLD4 GENMASK(63, 48) +#define WRMEM1_285_FLD5 GENMASK(79, 64) +#define WRMEM1_285_FLD6 GENMASK(95, 80) +#define WRMEM1_285_FLD7 GENMASK(111, 96) +#define WRMEM1_285_FLD8 GENMASK(127, 112) + +/* WRMEM1_286 register fields */ +#define WRMEM1_286_FLD1 GENMASK(15, 0) +#define WRMEM1_286_FLD2 GENMASK(31, 16) +#define WRMEM1_286_FLD3 GENMASK(47, 32) +#define WRMEM1_286_FLD4 GENMASK(63, 48) +#define WRMEM1_286_FLD5 GENMASK(79, 64) +#define WRMEM1_286_FLD6 GENMASK(95, 80) +#define WRMEM1_286_FLD7 GENMASK(111, 96) +#define WRMEM1_286_FLD8 GENMASK(127, 112) + +/* WRMEM1_287 register fields */ +#define WRMEM1_287_FLD1 GENMASK(15, 0) +#define WRMEM1_287_FLD2 GENMASK(31, 16) +#define WRMEM1_287_FLD3 GENMASK(47, 32) +#define WRMEM1_287_FLD4 GENMASK(63, 48) +#define WRMEM1_287_FLD5 GENMASK(79, 64) +#define WRMEM1_287_FLD6 GENMASK(95, 80) +#define WRMEM1_287_FLD7 GENMASK(111, 96) +#define WRMEM1_287_FLD8 GENMASK(127, 112) + +/* WRMEM1_288 register fields */ +#define WRMEM1_288_FLD1 GENMASK(15, 0) +#define WRMEM1_288_FLD2 GENMASK(31, 16) +#define WRMEM1_288_FLD3 GENMASK(47, 32) +#define WRMEM1_288_FLD4 GENMASK(63, 48) +#define WRMEM1_288_FLD5 GENMASK(79, 64) +#define WRMEM1_288_FLD6 GENMASK(95, 80) +#define WRMEM1_288_FLD7 GENMASK(111, 96) +#define WRMEM1_288_FLD8 GENMASK(127, 112) + +/* WRMEM1_289 register fields */ +#define WRMEM1_289_FLD1 GENMASK(15, 0) +#define WRMEM1_289_FLD2 GENMASK(31, 16) +#define WRMEM1_289_FLD3 GENMASK(47, 32) +#define WRMEM1_289_FLD4 GENMASK(63, 48) +#define WRMEM1_289_FLD5 GENMASK(79, 64) +#define WRMEM1_289_FLD6 GENMASK(95, 80) +#define WRMEM1_289_FLD7 GENMASK(111, 96) +#define WRMEM1_289_FLD8 GENMASK(127, 112) + +/* WRMEM1_290 register fields */ +#define WRMEM1_290_FLD1 GENMASK(15, 0) +#define WRMEM1_290_FLD2 GENMASK(31, 16) +#define WRMEM1_290_FLD3 GENMASK(47, 32) +#define WRMEM1_290_FLD4 GENMASK(63, 48) +#define WRMEM1_290_FLD5 GENMASK(79, 64) +#define WRMEM1_290_FLD6 GENMASK(95, 80) +#define WRMEM1_290_FLD7 GENMASK(111, 96) +#define WRMEM1_290_FLD8 GENMASK(127, 112) + +/* WRMEM1_291 register fields */ +#define WRMEM1_291_FLD1 GENMASK(15, 0) +#define WRMEM1_291_FLD2 GENMASK(31, 16) +#define WRMEM1_291_FLD3 GENMASK(47, 32) +#define WRMEM1_291_FLD4 GENMASK(63, 48) +#define WRMEM1_291_FLD5 GENMASK(79, 64) +#define WRMEM1_291_FLD6 GENMASK(95, 80) +#define WRMEM1_291_FLD7 GENMASK(111, 96) +#define WRMEM1_291_FLD8 GENMASK(127, 112) + +/* WRMEM1_292 register fields */ +#define WRMEM1_292_FLD1 GENMASK(15, 0) +#define WRMEM1_292_FLD2 GENMASK(31, 16) +#define WRMEM1_292_FLD3 GENMASK(47, 32) +#define WRMEM1_292_FLD4 GENMASK(63, 48) +#define WRMEM1_292_FLD5 GENMASK(79, 64) +#define WRMEM1_292_FLD6 GENMASK(95, 80) +#define WRMEM1_292_FLD7 GENMASK(111, 96) +#define WRMEM1_292_FLD8 GENMASK(127, 112) + +/* WRMEM1_293 register fields */ +#define WRMEM1_293_FLD1 GENMASK(15, 0) +#define WRMEM1_293_FLD2 GENMASK(31, 16) +#define WRMEM1_293_FLD3 GENMASK(47, 32) +#define WRMEM1_293_FLD4 GENMASK(63, 48) +#define WRMEM1_293_FLD5 GENMASK(79, 64) +#define WRMEM1_293_FLD6 GENMASK(95, 80) +#define WRMEM1_293_FLD7 GENMASK(111, 96) +#define WRMEM1_293_FLD8 GENMASK(127, 112) + +/* WRMEM1_294 register fields */ +#define WRMEM1_294_FLD1 GENMASK(15, 0) +#define WRMEM1_294_FLD2 GENMASK(31, 16) +#define WRMEM1_294_FLD3 GENMASK(47, 32) +#define WRMEM1_294_FLD4 GENMASK(63, 48) +#define WRMEM1_294_FLD5 GENMASK(79, 64) +#define WRMEM1_294_FLD6 GENMASK(95, 80) +#define WRMEM1_294_FLD7 GENMASK(111, 96) +#define WRMEM1_294_FLD8 GENMASK(127, 112) + +/* WRMEM1_295 register fields */ +#define WRMEM1_295_FLD1 GENMASK(15, 0) +#define WRMEM1_295_FLD2 GENMASK(31, 16) +#define WRMEM1_295_FLD3 GENMASK(47, 32) +#define WRMEM1_295_FLD4 GENMASK(63, 48) +#define WRMEM1_295_FLD5 GENMASK(79, 64) +#define WRMEM1_295_FLD6 GENMASK(95, 80) +#define WRMEM1_295_FLD7 GENMASK(111, 96) +#define WRMEM1_295_FLD8 GENMASK(127, 112) + +/* WRMEM1_296 register fields */ +#define WRMEM1_296_FLD1 GENMASK(15, 0) +#define WRMEM1_296_FLD2 GENMASK(31, 16) +#define WRMEM1_296_FLD3 GENMASK(47, 32) +#define WRMEM1_296_FLD4 GENMASK(63, 48) +#define WRMEM1_296_FLD5 GENMASK(79, 64) +#define WRMEM1_296_FLD6 GENMASK(95, 80) +#define WRMEM1_296_FLD7 GENMASK(111, 96) +#define WRMEM1_296_FLD8 GENMASK(127, 112) + +/* WRMEM1_297 register fields */ +#define WRMEM1_297_FLD1 GENMASK(15, 0) +#define WRMEM1_297_FLD2 GENMASK(31, 16) +#define WRMEM1_297_FLD3 GENMASK(47, 32) +#define WRMEM1_297_FLD4 GENMASK(63, 48) +#define WRMEM1_297_FLD5 GENMASK(79, 64) +#define WRMEM1_297_FLD6 GENMASK(95, 80) +#define WRMEM1_297_FLD7 GENMASK(111, 96) +#define WRMEM1_297_FLD8 GENMASK(127, 112) + +/* WRMEM1_298 register fields */ +#define WRMEM1_298_FLD1 GENMASK(15, 0) +#define WRMEM1_298_FLD2 GENMASK(31, 16) +#define WRMEM1_298_FLD3 GENMASK(47, 32) +#define WRMEM1_298_FLD4 GENMASK(63, 48) +#define WRMEM1_298_FLD5 GENMASK(79, 64) +#define WRMEM1_298_FLD6 GENMASK(95, 80) +#define WRMEM1_298_FLD7 GENMASK(111, 96) +#define WRMEM1_298_FLD8 GENMASK(127, 112) + +/* WRMEM1_299 register fields */ +#define WRMEM1_299_FLD1 GENMASK(15, 0) +#define WRMEM1_299_FLD2 GENMASK(31, 16) +#define WRMEM1_299_FLD3 GENMASK(47, 32) +#define WRMEM1_299_FLD4 GENMASK(63, 48) +#define WRMEM1_299_FLD5 GENMASK(79, 64) +#define WRMEM1_299_FLD6 GENMASK(95, 80) +#define WRMEM1_299_FLD7 GENMASK(111, 96) +#define WRMEM1_299_FLD8 GENMASK(127, 112) + +#endif diff --git a/test/basic_tests/rdl_uvmmem_nums/golden/output.h b/test/basic_tests/rdl_uvmmem_nums/golden/output.h new file mode 100644 index 0000000..5f4581d --- /dev/null +++ b/test/basic_tests/rdl_uvmmem_nums/golden/output.h @@ -0,0 +1,3743 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_uvmmem_nums/test.rdl +// Parms: ./rdl_uvmmem_nums/test.parms +// Date: Thu Jul 20 13:47:00 EDT 2023 +// + +#ifndef __TOP_REGISTER_MAP__ +#define __TOP_REGISTER_MAP__ + +#include + +/* TOP_REGISTERS memory map */ +enum TOP_REGS { + SR1 = 0x0, + WR1 = 0x100, + SR_REPEAT1 = 0x200, + SR_REPEAT2 = 0x204, + SR_REPEAT3 = 0x208, + SRMEM1_0 = 0x2000, + SRMEM1_1 = 0x2004, + SRMEM1_2 = 0x2008, + SRMEM1_3 = 0x200c, + SRMEM1_4 = 0x2010, + SRMEM1_5 = 0x2014, + SRMEM1_6 = 0x2018, + SRMEM1_7 = 0x201c, + SRMEM1_8 = 0x2020, + SRMEM1_9 = 0x2024, + SRMEM1_10 = 0x2028, + SRMEM1_11 = 0x202c, + SRMEM1_12 = 0x2030, + SRMEM1_13 = 0x2034, + SRMEM1_14 = 0x2038, + SRMEM1_15 = 0x203c, + SRMEM1_16 = 0x2040, + SRMEM1_17 = 0x2044, + SRMEM1_18 = 0x2048, + SRMEM1_19 = 0x204c, + SRMEM1_20 = 0x2050, + SRMEM1_21 = 0x2054, + SRMEM1_22 = 0x2058, + SRMEM1_23 = 0x205c, + SRMEM1_24 = 0x2060, + SRMEM1_25 = 0x2064, + SRMEM1_26 = 0x2068, + SRMEM1_27 = 0x206c, + SRMEM1_28 = 0x2070, + SRMEM1_29 = 0x2074, + SRMEM1_30 = 0x2078, + SRMEM1_31 = 0x207c, + SRMEM1_32 = 0x2080, + SRMEM1_33 = 0x2084, + SRMEM1_34 = 0x2088, + SRMEM1_35 = 0x208c, + SRMEM1_36 = 0x2090, + SRMEM1_37 = 0x2094, + SRMEM1_38 = 0x2098, + SRMEM1_39 = 0x209c, + SRMEM1_40 = 0x20a0, + SRMEM1_41 = 0x20a4, + SRMEM1_42 = 0x20a8, + SRMEM1_43 = 0x20ac, + SRMEM1_44 = 0x20b0, + SRMEM1_45 = 0x20b4, + SRMEM1_46 = 0x20b8, + SRMEM1_47 = 0x20bc, + SRMEM1_48 = 0x20c0, + SRMEM1_49 = 0x20c4, + SRMEM1_50 = 0x20c8, + SRMEM1_51 = 0x20cc, + SRMEM1_52 = 0x20d0, + SRMEM1_53 = 0x20d4, + SRMEM1_54 = 0x20d8, + SRMEM1_55 = 0x20dc, + SRMEM1_56 = 0x20e0, + SRMEM1_57 = 0x20e4, + SRMEM1_58 = 0x20e8, + SRMEM1_59 = 0x20ec, + SRMEM1_60 = 0x20f0, + SRMEM1_61 = 0x20f4, + SRMEM1_62 = 0x20f8, + SRMEM1_63 = 0x20fc, + SRMEM1_64 = 0x2100, + SRMEM1_65 = 0x2104, + SRMEM1_66 = 0x2108, + SRMEM1_67 = 0x210c, + SRMEM1_68 = 0x2110, + SRMEM1_69 = 0x2114, + SRMEM1_70 = 0x2118, + SRMEM1_71 = 0x211c, + SRMEM1_72 = 0x2120, + SRMEM1_73 = 0x2124, + SRMEM1_74 = 0x2128, + SRMEM1_75 = 0x212c, + SRMEM1_76 = 0x2130, + SRMEM1_77 = 0x2134, + SRMEM1_78 = 0x2138, + SRMEM1_79 = 0x213c, + SRMEM1_80 = 0x2140, + SRMEM1_81 = 0x2144, + SRMEM1_82 = 0x2148, + SRMEM1_83 = 0x214c, + SRMEM1_84 = 0x2150, + SRMEM1_85 = 0x2154, + SRMEM1_86 = 0x2158, + SRMEM1_87 = 0x215c, + SRMEM1_88 = 0x2160, + SRMEM1_89 = 0x2164, + SRMEM1_90 = 0x2168, + SRMEM1_91 = 0x216c, + SRMEM1_92 = 0x2170, + SRMEM1_93 = 0x2174, + SRMEM1_94 = 0x2178, + SRMEM1_95 = 0x217c, + SRMEM1_96 = 0x2180, + SRMEM1_97 = 0x2184, + SRMEM1_98 = 0x2188, + SRMEM1_99 = 0x218c, + WRMEM1_0 = 0x20000, + WRMEM1_1 = 0x20010, + WRMEM1_2 = 0x20020, + WRMEM1_3 = 0x20030, + WRMEM1_4 = 0x20040, + WRMEM1_5 = 0x20050, + WRMEM1_6 = 0x20060, + WRMEM1_7 = 0x20070, + WRMEM1_8 = 0x20080, + WRMEM1_9 = 0x20090, + WRMEM1_10 = 0x200a0, + WRMEM1_11 = 0x200b0, + WRMEM1_12 = 0x200c0, + WRMEM1_13 = 0x200d0, + WRMEM1_14 = 0x200e0, + WRMEM1_15 = 0x200f0, + WRMEM1_16 = 0x20100, + WRMEM1_17 = 0x20110, + WRMEM1_18 = 0x20120, + WRMEM1_19 = 0x20130, + WRMEM1_20 = 0x20140, + WRMEM1_21 = 0x20150, + WRMEM1_22 = 0x20160, + WRMEM1_23 = 0x20170, + WRMEM1_24 = 0x20180, + WRMEM1_25 = 0x20190, + WRMEM1_26 = 0x201a0, + WRMEM1_27 = 0x201b0, + WRMEM1_28 = 0x201c0, + WRMEM1_29 = 0x201d0, + WRMEM1_30 = 0x201e0, + WRMEM1_31 = 0x201f0, + WRMEM1_32 = 0x20200, + WRMEM1_33 = 0x20210, + WRMEM1_34 = 0x20220, + WRMEM1_35 = 0x20230, + WRMEM1_36 = 0x20240, + WRMEM1_37 = 0x20250, + WRMEM1_38 = 0x20260, + WRMEM1_39 = 0x20270, + WRMEM1_40 = 0x20280, + WRMEM1_41 = 0x20290, + WRMEM1_42 = 0x202a0, + WRMEM1_43 = 0x202b0, + WRMEM1_44 = 0x202c0, + WRMEM1_45 = 0x202d0, + WRMEM1_46 = 0x202e0, + WRMEM1_47 = 0x202f0, + WRMEM1_48 = 0x20300, + WRMEM1_49 = 0x20310, + WRMEM1_50 = 0x20320, + WRMEM1_51 = 0x20330, + WRMEM1_52 = 0x20340, + WRMEM1_53 = 0x20350, + WRMEM1_54 = 0x20360, + WRMEM1_55 = 0x20370, + WRMEM1_56 = 0x20380, + WRMEM1_57 = 0x20390, + WRMEM1_58 = 0x203a0, + WRMEM1_59 = 0x203b0, + WRMEM1_60 = 0x203c0, + WRMEM1_61 = 0x203d0, + WRMEM1_62 = 0x203e0, + WRMEM1_63 = 0x203f0, + WRMEM1_64 = 0x20400, + WRMEM1_65 = 0x20410, + WRMEM1_66 = 0x20420, + WRMEM1_67 = 0x20430, + WRMEM1_68 = 0x20440, + WRMEM1_69 = 0x20450, + WRMEM1_70 = 0x20460, + WRMEM1_71 = 0x20470, + WRMEM1_72 = 0x20480, + WRMEM1_73 = 0x20490, + WRMEM1_74 = 0x204a0, + WRMEM1_75 = 0x204b0, + WRMEM1_76 = 0x204c0, + WRMEM1_77 = 0x204d0, + WRMEM1_78 = 0x204e0, + WRMEM1_79 = 0x204f0, + WRMEM1_80 = 0x20500, + WRMEM1_81 = 0x20510, + WRMEM1_82 = 0x20520, + WRMEM1_83 = 0x20530, + WRMEM1_84 = 0x20540, + WRMEM1_85 = 0x20550, + WRMEM1_86 = 0x20560, + WRMEM1_87 = 0x20570, + WRMEM1_88 = 0x20580, + WRMEM1_89 = 0x20590, + WRMEM1_90 = 0x205a0, + WRMEM1_91 = 0x205b0, + WRMEM1_92 = 0x205c0, + WRMEM1_93 = 0x205d0, + WRMEM1_94 = 0x205e0, + WRMEM1_95 = 0x205f0, + WRMEM1_96 = 0x20600, + WRMEM1_97 = 0x20610, + WRMEM1_98 = 0x20620, + WRMEM1_99 = 0x20630, + WRMEM1_100 = 0x20640, + WRMEM1_101 = 0x20650, + WRMEM1_102 = 0x20660, + WRMEM1_103 = 0x20670, + WRMEM1_104 = 0x20680, + WRMEM1_105 = 0x20690, + WRMEM1_106 = 0x206a0, + WRMEM1_107 = 0x206b0, + WRMEM1_108 = 0x206c0, + WRMEM1_109 = 0x206d0, + WRMEM1_110 = 0x206e0, + WRMEM1_111 = 0x206f0, + WRMEM1_112 = 0x20700, + WRMEM1_113 = 0x20710, + WRMEM1_114 = 0x20720, + WRMEM1_115 = 0x20730, + WRMEM1_116 = 0x20740, + WRMEM1_117 = 0x20750, + WRMEM1_118 = 0x20760, + WRMEM1_119 = 0x20770, + WRMEM1_120 = 0x20780, + WRMEM1_121 = 0x20790, + WRMEM1_122 = 0x207a0, + WRMEM1_123 = 0x207b0, + WRMEM1_124 = 0x207c0, + WRMEM1_125 = 0x207d0, + WRMEM1_126 = 0x207e0, + WRMEM1_127 = 0x207f0, + WRMEM1_128 = 0x20800, + WRMEM1_129 = 0x20810, + WRMEM1_130 = 0x20820, + WRMEM1_131 = 0x20830, + WRMEM1_132 = 0x20840, + WRMEM1_133 = 0x20850, + WRMEM1_134 = 0x20860, + WRMEM1_135 = 0x20870, + WRMEM1_136 = 0x20880, + WRMEM1_137 = 0x20890, + WRMEM1_138 = 0x208a0, + WRMEM1_139 = 0x208b0, + WRMEM1_140 = 0x208c0, + WRMEM1_141 = 0x208d0, + WRMEM1_142 = 0x208e0, + WRMEM1_143 = 0x208f0, + WRMEM1_144 = 0x20900, + WRMEM1_145 = 0x20910, + WRMEM1_146 = 0x20920, + WRMEM1_147 = 0x20930, + WRMEM1_148 = 0x20940, + WRMEM1_149 = 0x20950, + WRMEM1_150 = 0x20960, + WRMEM1_151 = 0x20970, + WRMEM1_152 = 0x20980, + WRMEM1_153 = 0x20990, + WRMEM1_154 = 0x209a0, + WRMEM1_155 = 0x209b0, + WRMEM1_156 = 0x209c0, + WRMEM1_157 = 0x209d0, + WRMEM1_158 = 0x209e0, + WRMEM1_159 = 0x209f0, + WRMEM1_160 = 0x20a00, + WRMEM1_161 = 0x20a10, + WRMEM1_162 = 0x20a20, + WRMEM1_163 = 0x20a30, + WRMEM1_164 = 0x20a40, + WRMEM1_165 = 0x20a50, + WRMEM1_166 = 0x20a60, + WRMEM1_167 = 0x20a70, + WRMEM1_168 = 0x20a80, + WRMEM1_169 = 0x20a90, + WRMEM1_170 = 0x20aa0, + WRMEM1_171 = 0x20ab0, + WRMEM1_172 = 0x20ac0, + WRMEM1_173 = 0x20ad0, + WRMEM1_174 = 0x20ae0, + WRMEM1_175 = 0x20af0, + WRMEM1_176 = 0x20b00, + WRMEM1_177 = 0x20b10, + WRMEM1_178 = 0x20b20, + WRMEM1_179 = 0x20b30, + WRMEM1_180 = 0x20b40, + WRMEM1_181 = 0x20b50, + WRMEM1_182 = 0x20b60, + WRMEM1_183 = 0x20b70, + WRMEM1_184 = 0x20b80, + WRMEM1_185 = 0x20b90, + WRMEM1_186 = 0x20ba0, + WRMEM1_187 = 0x20bb0, + WRMEM1_188 = 0x20bc0, + WRMEM1_189 = 0x20bd0, + WRMEM1_190 = 0x20be0, + WRMEM1_191 = 0x20bf0, + WRMEM1_192 = 0x20c00, + WRMEM1_193 = 0x20c10, + WRMEM1_194 = 0x20c20, + WRMEM1_195 = 0x20c30, + WRMEM1_196 = 0x20c40, + WRMEM1_197 = 0x20c50, + WRMEM1_198 = 0x20c60, + WRMEM1_199 = 0x20c70, + WRMEM1_200 = 0x20c80, + WRMEM1_201 = 0x20c90, + WRMEM1_202 = 0x20ca0, + WRMEM1_203 = 0x20cb0, + WRMEM1_204 = 0x20cc0, + WRMEM1_205 = 0x20cd0, + WRMEM1_206 = 0x20ce0, + WRMEM1_207 = 0x20cf0, + WRMEM1_208 = 0x20d00, + WRMEM1_209 = 0x20d10, + WRMEM1_210 = 0x20d20, + WRMEM1_211 = 0x20d30, + WRMEM1_212 = 0x20d40, + WRMEM1_213 = 0x20d50, + WRMEM1_214 = 0x20d60, + WRMEM1_215 = 0x20d70, + WRMEM1_216 = 0x20d80, + WRMEM1_217 = 0x20d90, + WRMEM1_218 = 0x20da0, + WRMEM1_219 = 0x20db0, + WRMEM1_220 = 0x20dc0, + WRMEM1_221 = 0x20dd0, + WRMEM1_222 = 0x20de0, + WRMEM1_223 = 0x20df0, + WRMEM1_224 = 0x20e00, + WRMEM1_225 = 0x20e10, + WRMEM1_226 = 0x20e20, + WRMEM1_227 = 0x20e30, + WRMEM1_228 = 0x20e40, + WRMEM1_229 = 0x20e50, + WRMEM1_230 = 0x20e60, + WRMEM1_231 = 0x20e70, + WRMEM1_232 = 0x20e80, + WRMEM1_233 = 0x20e90, + WRMEM1_234 = 0x20ea0, + WRMEM1_235 = 0x20eb0, + WRMEM1_236 = 0x20ec0, + WRMEM1_237 = 0x20ed0, + WRMEM1_238 = 0x20ee0, + WRMEM1_239 = 0x20ef0, + WRMEM1_240 = 0x20f00, + WRMEM1_241 = 0x20f10, + WRMEM1_242 = 0x20f20, + WRMEM1_243 = 0x20f30, + WRMEM1_244 = 0x20f40, + WRMEM1_245 = 0x20f50, + WRMEM1_246 = 0x20f60, + WRMEM1_247 = 0x20f70, + WRMEM1_248 = 0x20f80, + WRMEM1_249 = 0x20f90, + WRMEM1_250 = 0x20fa0, + WRMEM1_251 = 0x20fb0, + WRMEM1_252 = 0x20fc0, + WRMEM1_253 = 0x20fd0, + WRMEM1_254 = 0x20fe0, + WRMEM1_255 = 0x20ff0, + WRMEM1_256 = 0x21000, + WRMEM1_257 = 0x21010, + WRMEM1_258 = 0x21020, + WRMEM1_259 = 0x21030, + WRMEM1_260 = 0x21040, + WRMEM1_261 = 0x21050, + WRMEM1_262 = 0x21060, + WRMEM1_263 = 0x21070, + WRMEM1_264 = 0x21080, + WRMEM1_265 = 0x21090, + WRMEM1_266 = 0x210a0, + WRMEM1_267 = 0x210b0, + WRMEM1_268 = 0x210c0, + WRMEM1_269 = 0x210d0, + WRMEM1_270 = 0x210e0, + WRMEM1_271 = 0x210f0, + WRMEM1_272 = 0x21100, + WRMEM1_273 = 0x21110, + WRMEM1_274 = 0x21120, + WRMEM1_275 = 0x21130, + WRMEM1_276 = 0x21140, + WRMEM1_277 = 0x21150, + WRMEM1_278 = 0x21160, + WRMEM1_279 = 0x21170, + WRMEM1_280 = 0x21180, + WRMEM1_281 = 0x21190, + WRMEM1_282 = 0x211a0, + WRMEM1_283 = 0x211b0, + WRMEM1_284 = 0x211c0, + WRMEM1_285 = 0x211d0, + WRMEM1_286 = 0x211e0, + WRMEM1_287 = 0x211f0, + WRMEM1_288 = 0x21200, + WRMEM1_289 = 0x21210, + WRMEM1_290 = 0x21220, + WRMEM1_291 = 0x21230, + WRMEM1_292 = 0x21240, + WRMEM1_293 = 0x21250, + WRMEM1_294 = 0x21260, + WRMEM1_295 = 0x21270, + WRMEM1_296 = 0x21280, + WRMEM1_297 = 0x21290, + WRMEM1_298 = 0x212a0, + WRMEM1_299 = 0x212b0 +}; + +/* SR1 register fields */ +#define SR1_FLD1 GENMASK(31, 0) + +/* WR1 register fields */ +#define WR1_FLD1 GENMASK(15, 0) +#define WR1_FLD2 GENMASK(31, 16) +#define WR1_FLD3 GENMASK(47, 32) +#define WR1_FLD4 GENMASK(63, 48) +#define WR1_FLD5 GENMASK(79, 64) +#define WR1_FLD6 GENMASK(95, 80) +#define WR1_FLD7 GENMASK(111, 96) +#define WR1_FLD8 GENMASK(127, 112) + +/* SR_REPEAT1 register fields */ +#define SR_REPEAT1_FLD1 GENMASK(31, 0) + +/* SR_REPEAT2 register fields */ +#define SR_REPEAT2_FLD1 GENMASK(31, 0) + +/* SR_REPEAT3 register fields */ +#define SR_REPEAT3_FLD1 GENMASK(31, 0) + +/* SRMEM1_0 register fields */ +#define SRMEM1_0_FLD1 GENMASK(31, 0) + +/* SRMEM1_1 register fields */ +#define SRMEM1_1_FLD1 GENMASK(31, 0) + +/* SRMEM1_2 register fields */ +#define SRMEM1_2_FLD1 GENMASK(31, 0) + +/* SRMEM1_3 register fields */ +#define SRMEM1_3_FLD1 GENMASK(31, 0) + +/* SRMEM1_4 register fields */ +#define SRMEM1_4_FLD1 GENMASK(31, 0) + +/* SRMEM1_5 register fields */ +#define SRMEM1_5_FLD1 GENMASK(31, 0) + +/* SRMEM1_6 register fields */ +#define SRMEM1_6_FLD1 GENMASK(31, 0) + +/* SRMEM1_7 register fields */ +#define SRMEM1_7_FLD1 GENMASK(31, 0) + +/* SRMEM1_8 register fields */ +#define SRMEM1_8_FLD1 GENMASK(31, 0) + +/* SRMEM1_9 register fields */ +#define SRMEM1_9_FLD1 GENMASK(31, 0) + +/* SRMEM1_10 register fields */ +#define SRMEM1_10_FLD1 GENMASK(31, 0) + +/* SRMEM1_11 register fields */ +#define SRMEM1_11_FLD1 GENMASK(31, 0) + +/* SRMEM1_12 register fields */ +#define SRMEM1_12_FLD1 GENMASK(31, 0) + +/* SRMEM1_13 register fields */ +#define SRMEM1_13_FLD1 GENMASK(31, 0) + +/* SRMEM1_14 register fields */ +#define SRMEM1_14_FLD1 GENMASK(31, 0) + +/* SRMEM1_15 register fields */ +#define SRMEM1_15_FLD1 GENMASK(31, 0) + +/* SRMEM1_16 register fields */ +#define SRMEM1_16_FLD1 GENMASK(31, 0) + +/* SRMEM1_17 register fields */ +#define SRMEM1_17_FLD1 GENMASK(31, 0) + +/* SRMEM1_18 register fields */ +#define SRMEM1_18_FLD1 GENMASK(31, 0) + +/* SRMEM1_19 register fields */ +#define SRMEM1_19_FLD1 GENMASK(31, 0) + +/* SRMEM1_20 register fields */ +#define SRMEM1_20_FLD1 GENMASK(31, 0) + +/* SRMEM1_21 register fields */ +#define SRMEM1_21_FLD1 GENMASK(31, 0) + +/* SRMEM1_22 register fields */ +#define SRMEM1_22_FLD1 GENMASK(31, 0) + +/* SRMEM1_23 register fields */ +#define SRMEM1_23_FLD1 GENMASK(31, 0) + +/* SRMEM1_24 register fields */ +#define SRMEM1_24_FLD1 GENMASK(31, 0) + +/* SRMEM1_25 register fields */ +#define SRMEM1_25_FLD1 GENMASK(31, 0) + +/* SRMEM1_26 register fields */ +#define SRMEM1_26_FLD1 GENMASK(31, 0) + +/* SRMEM1_27 register fields */ +#define SRMEM1_27_FLD1 GENMASK(31, 0) + +/* SRMEM1_28 register fields */ +#define SRMEM1_28_FLD1 GENMASK(31, 0) + +/* SRMEM1_29 register fields */ +#define SRMEM1_29_FLD1 GENMASK(31, 0) + +/* SRMEM1_30 register fields */ +#define SRMEM1_30_FLD1 GENMASK(31, 0) + +/* SRMEM1_31 register fields */ +#define SRMEM1_31_FLD1 GENMASK(31, 0) + +/* SRMEM1_32 register fields */ +#define SRMEM1_32_FLD1 GENMASK(31, 0) + +/* SRMEM1_33 register fields */ +#define SRMEM1_33_FLD1 GENMASK(31, 0) + +/* SRMEM1_34 register fields */ +#define SRMEM1_34_FLD1 GENMASK(31, 0) + +/* SRMEM1_35 register fields */ +#define SRMEM1_35_FLD1 GENMASK(31, 0) + +/* SRMEM1_36 register fields */ +#define SRMEM1_36_FLD1 GENMASK(31, 0) + +/* SRMEM1_37 register fields */ +#define SRMEM1_37_FLD1 GENMASK(31, 0) + +/* SRMEM1_38 register fields */ +#define SRMEM1_38_FLD1 GENMASK(31, 0) + +/* SRMEM1_39 register fields */ +#define SRMEM1_39_FLD1 GENMASK(31, 0) + +/* SRMEM1_40 register fields */ +#define SRMEM1_40_FLD1 GENMASK(31, 0) + +/* SRMEM1_41 register fields */ +#define SRMEM1_41_FLD1 GENMASK(31, 0) + +/* SRMEM1_42 register fields */ +#define SRMEM1_42_FLD1 GENMASK(31, 0) + +/* SRMEM1_43 register fields */ +#define SRMEM1_43_FLD1 GENMASK(31, 0) + +/* SRMEM1_44 register fields */ +#define SRMEM1_44_FLD1 GENMASK(31, 0) + +/* SRMEM1_45 register fields */ +#define SRMEM1_45_FLD1 GENMASK(31, 0) + +/* SRMEM1_46 register fields */ +#define SRMEM1_46_FLD1 GENMASK(31, 0) + +/* SRMEM1_47 register fields */ +#define SRMEM1_47_FLD1 GENMASK(31, 0) + +/* SRMEM1_48 register fields */ +#define SRMEM1_48_FLD1 GENMASK(31, 0) + +/* SRMEM1_49 register fields */ +#define SRMEM1_49_FLD1 GENMASK(31, 0) + +/* SRMEM1_50 register fields */ +#define SRMEM1_50_FLD1 GENMASK(31, 0) + +/* SRMEM1_51 register fields */ +#define SRMEM1_51_FLD1 GENMASK(31, 0) + +/* SRMEM1_52 register fields */ +#define SRMEM1_52_FLD1 GENMASK(31, 0) + +/* SRMEM1_53 register fields */ +#define SRMEM1_53_FLD1 GENMASK(31, 0) + +/* SRMEM1_54 register fields */ +#define SRMEM1_54_FLD1 GENMASK(31, 0) + +/* SRMEM1_55 register fields */ +#define SRMEM1_55_FLD1 GENMASK(31, 0) + +/* SRMEM1_56 register fields */ +#define SRMEM1_56_FLD1 GENMASK(31, 0) + +/* SRMEM1_57 register fields */ +#define SRMEM1_57_FLD1 GENMASK(31, 0) + +/* SRMEM1_58 register fields */ +#define SRMEM1_58_FLD1 GENMASK(31, 0) + +/* SRMEM1_59 register fields */ +#define SRMEM1_59_FLD1 GENMASK(31, 0) + +/* SRMEM1_60 register fields */ +#define SRMEM1_60_FLD1 GENMASK(31, 0) + +/* SRMEM1_61 register fields */ +#define SRMEM1_61_FLD1 GENMASK(31, 0) + +/* SRMEM1_62 register fields */ +#define SRMEM1_62_FLD1 GENMASK(31, 0) + +/* SRMEM1_63 register fields */ +#define SRMEM1_63_FLD1 GENMASK(31, 0) + +/* SRMEM1_64 register fields */ +#define SRMEM1_64_FLD1 GENMASK(31, 0) + +/* SRMEM1_65 register fields */ +#define SRMEM1_65_FLD1 GENMASK(31, 0) + +/* SRMEM1_66 register fields */ +#define SRMEM1_66_FLD1 GENMASK(31, 0) + +/* SRMEM1_67 register fields */ +#define SRMEM1_67_FLD1 GENMASK(31, 0) + +/* SRMEM1_68 register fields */ +#define SRMEM1_68_FLD1 GENMASK(31, 0) + +/* SRMEM1_69 register fields */ +#define SRMEM1_69_FLD1 GENMASK(31, 0) + +/* SRMEM1_70 register fields */ +#define SRMEM1_70_FLD1 GENMASK(31, 0) + +/* SRMEM1_71 register fields */ +#define SRMEM1_71_FLD1 GENMASK(31, 0) + +/* SRMEM1_72 register fields */ +#define SRMEM1_72_FLD1 GENMASK(31, 0) + +/* SRMEM1_73 register fields */ +#define SRMEM1_73_FLD1 GENMASK(31, 0) + +/* SRMEM1_74 register fields */ +#define SRMEM1_74_FLD1 GENMASK(31, 0) + +/* SRMEM1_75 register fields */ +#define SRMEM1_75_FLD1 GENMASK(31, 0) + +/* SRMEM1_76 register fields */ +#define SRMEM1_76_FLD1 GENMASK(31, 0) + +/* SRMEM1_77 register fields */ +#define SRMEM1_77_FLD1 GENMASK(31, 0) + +/* SRMEM1_78 register fields */ +#define SRMEM1_78_FLD1 GENMASK(31, 0) + +/* SRMEM1_79 register fields */ +#define SRMEM1_79_FLD1 GENMASK(31, 0) + +/* SRMEM1_80 register fields */ +#define SRMEM1_80_FLD1 GENMASK(31, 0) + +/* SRMEM1_81 register fields */ +#define SRMEM1_81_FLD1 GENMASK(31, 0) + +/* SRMEM1_82 register fields */ +#define SRMEM1_82_FLD1 GENMASK(31, 0) + +/* SRMEM1_83 register fields */ +#define SRMEM1_83_FLD1 GENMASK(31, 0) + +/* SRMEM1_84 register fields */ +#define SRMEM1_84_FLD1 GENMASK(31, 0) + +/* SRMEM1_85 register fields */ +#define SRMEM1_85_FLD1 GENMASK(31, 0) + +/* SRMEM1_86 register fields */ +#define SRMEM1_86_FLD1 GENMASK(31, 0) + +/* SRMEM1_87 register fields */ +#define SRMEM1_87_FLD1 GENMASK(31, 0) + +/* SRMEM1_88 register fields */ +#define SRMEM1_88_FLD1 GENMASK(31, 0) + +/* SRMEM1_89 register fields */ +#define SRMEM1_89_FLD1 GENMASK(31, 0) + +/* SRMEM1_90 register fields */ +#define SRMEM1_90_FLD1 GENMASK(31, 0) + +/* SRMEM1_91 register fields */ +#define SRMEM1_91_FLD1 GENMASK(31, 0) + +/* SRMEM1_92 register fields */ +#define SRMEM1_92_FLD1 GENMASK(31, 0) + +/* SRMEM1_93 register fields */ +#define SRMEM1_93_FLD1 GENMASK(31, 0) + +/* SRMEM1_94 register fields */ +#define SRMEM1_94_FLD1 GENMASK(31, 0) + +/* SRMEM1_95 register fields */ +#define SRMEM1_95_FLD1 GENMASK(31, 0) + +/* SRMEM1_96 register fields */ +#define SRMEM1_96_FLD1 GENMASK(31, 0) + +/* SRMEM1_97 register fields */ +#define SRMEM1_97_FLD1 GENMASK(31, 0) + +/* SRMEM1_98 register fields */ +#define SRMEM1_98_FLD1 GENMASK(31, 0) + +/* SRMEM1_99 register fields */ +#define SRMEM1_99_FLD1 GENMASK(31, 0) + +/* WRMEM1_0 register fields */ +#define WRMEM1_0_FLD1 GENMASK(15, 0) +#define WRMEM1_0_FLD2 GENMASK(31, 16) +#define WRMEM1_0_FLD3 GENMASK(47, 32) +#define WRMEM1_0_FLD4 GENMASK(63, 48) +#define WRMEM1_0_FLD5 GENMASK(79, 64) +#define WRMEM1_0_FLD6 GENMASK(95, 80) +#define WRMEM1_0_FLD7 GENMASK(111, 96) +#define WRMEM1_0_FLD8 GENMASK(127, 112) + +/* WRMEM1_1 register fields */ +#define WRMEM1_1_FLD1 GENMASK(15, 0) +#define WRMEM1_1_FLD2 GENMASK(31, 16) +#define WRMEM1_1_FLD3 GENMASK(47, 32) +#define WRMEM1_1_FLD4 GENMASK(63, 48) +#define WRMEM1_1_FLD5 GENMASK(79, 64) +#define WRMEM1_1_FLD6 GENMASK(95, 80) +#define WRMEM1_1_FLD7 GENMASK(111, 96) +#define WRMEM1_1_FLD8 GENMASK(127, 112) + +/* WRMEM1_2 register fields */ +#define WRMEM1_2_FLD1 GENMASK(15, 0) +#define WRMEM1_2_FLD2 GENMASK(31, 16) +#define WRMEM1_2_FLD3 GENMASK(47, 32) +#define WRMEM1_2_FLD4 GENMASK(63, 48) +#define WRMEM1_2_FLD5 GENMASK(79, 64) +#define WRMEM1_2_FLD6 GENMASK(95, 80) +#define WRMEM1_2_FLD7 GENMASK(111, 96) +#define WRMEM1_2_FLD8 GENMASK(127, 112) + +/* WRMEM1_3 register fields */ +#define WRMEM1_3_FLD1 GENMASK(15, 0) +#define WRMEM1_3_FLD2 GENMASK(31, 16) +#define WRMEM1_3_FLD3 GENMASK(47, 32) +#define WRMEM1_3_FLD4 GENMASK(63, 48) +#define WRMEM1_3_FLD5 GENMASK(79, 64) +#define WRMEM1_3_FLD6 GENMASK(95, 80) +#define WRMEM1_3_FLD7 GENMASK(111, 96) +#define WRMEM1_3_FLD8 GENMASK(127, 112) + +/* WRMEM1_4 register fields */ +#define WRMEM1_4_FLD1 GENMASK(15, 0) +#define WRMEM1_4_FLD2 GENMASK(31, 16) +#define WRMEM1_4_FLD3 GENMASK(47, 32) +#define WRMEM1_4_FLD4 GENMASK(63, 48) +#define WRMEM1_4_FLD5 GENMASK(79, 64) +#define WRMEM1_4_FLD6 GENMASK(95, 80) +#define WRMEM1_4_FLD7 GENMASK(111, 96) +#define WRMEM1_4_FLD8 GENMASK(127, 112) + +/* WRMEM1_5 register fields */ +#define WRMEM1_5_FLD1 GENMASK(15, 0) +#define WRMEM1_5_FLD2 GENMASK(31, 16) +#define WRMEM1_5_FLD3 GENMASK(47, 32) +#define WRMEM1_5_FLD4 GENMASK(63, 48) +#define WRMEM1_5_FLD5 GENMASK(79, 64) +#define WRMEM1_5_FLD6 GENMASK(95, 80) +#define WRMEM1_5_FLD7 GENMASK(111, 96) +#define WRMEM1_5_FLD8 GENMASK(127, 112) + +/* WRMEM1_6 register fields */ +#define WRMEM1_6_FLD1 GENMASK(15, 0) +#define WRMEM1_6_FLD2 GENMASK(31, 16) +#define WRMEM1_6_FLD3 GENMASK(47, 32) +#define WRMEM1_6_FLD4 GENMASK(63, 48) +#define WRMEM1_6_FLD5 GENMASK(79, 64) +#define WRMEM1_6_FLD6 GENMASK(95, 80) +#define WRMEM1_6_FLD7 GENMASK(111, 96) +#define WRMEM1_6_FLD8 GENMASK(127, 112) + +/* WRMEM1_7 register fields */ +#define WRMEM1_7_FLD1 GENMASK(15, 0) +#define WRMEM1_7_FLD2 GENMASK(31, 16) +#define WRMEM1_7_FLD3 GENMASK(47, 32) +#define WRMEM1_7_FLD4 GENMASK(63, 48) +#define WRMEM1_7_FLD5 GENMASK(79, 64) +#define WRMEM1_7_FLD6 GENMASK(95, 80) +#define WRMEM1_7_FLD7 GENMASK(111, 96) +#define WRMEM1_7_FLD8 GENMASK(127, 112) + +/* WRMEM1_8 register fields */ +#define WRMEM1_8_FLD1 GENMASK(15, 0) +#define WRMEM1_8_FLD2 GENMASK(31, 16) +#define WRMEM1_8_FLD3 GENMASK(47, 32) +#define WRMEM1_8_FLD4 GENMASK(63, 48) +#define WRMEM1_8_FLD5 GENMASK(79, 64) +#define WRMEM1_8_FLD6 GENMASK(95, 80) +#define WRMEM1_8_FLD7 GENMASK(111, 96) +#define WRMEM1_8_FLD8 GENMASK(127, 112) + +/* WRMEM1_9 register fields */ +#define WRMEM1_9_FLD1 GENMASK(15, 0) +#define WRMEM1_9_FLD2 GENMASK(31, 16) +#define WRMEM1_9_FLD3 GENMASK(47, 32) +#define WRMEM1_9_FLD4 GENMASK(63, 48) +#define WRMEM1_9_FLD5 GENMASK(79, 64) +#define WRMEM1_9_FLD6 GENMASK(95, 80) +#define WRMEM1_9_FLD7 GENMASK(111, 96) +#define WRMEM1_9_FLD8 GENMASK(127, 112) + +/* WRMEM1_10 register fields */ +#define WRMEM1_10_FLD1 GENMASK(15, 0) +#define WRMEM1_10_FLD2 GENMASK(31, 16) +#define WRMEM1_10_FLD3 GENMASK(47, 32) +#define WRMEM1_10_FLD4 GENMASK(63, 48) +#define WRMEM1_10_FLD5 GENMASK(79, 64) +#define WRMEM1_10_FLD6 GENMASK(95, 80) +#define WRMEM1_10_FLD7 GENMASK(111, 96) +#define WRMEM1_10_FLD8 GENMASK(127, 112) + +/* WRMEM1_11 register fields */ +#define WRMEM1_11_FLD1 GENMASK(15, 0) +#define WRMEM1_11_FLD2 GENMASK(31, 16) +#define WRMEM1_11_FLD3 GENMASK(47, 32) +#define WRMEM1_11_FLD4 GENMASK(63, 48) +#define WRMEM1_11_FLD5 GENMASK(79, 64) +#define WRMEM1_11_FLD6 GENMASK(95, 80) +#define WRMEM1_11_FLD7 GENMASK(111, 96) +#define WRMEM1_11_FLD8 GENMASK(127, 112) + +/* WRMEM1_12 register fields */ +#define WRMEM1_12_FLD1 GENMASK(15, 0) +#define WRMEM1_12_FLD2 GENMASK(31, 16) +#define WRMEM1_12_FLD3 GENMASK(47, 32) +#define WRMEM1_12_FLD4 GENMASK(63, 48) +#define WRMEM1_12_FLD5 GENMASK(79, 64) +#define WRMEM1_12_FLD6 GENMASK(95, 80) +#define WRMEM1_12_FLD7 GENMASK(111, 96) +#define WRMEM1_12_FLD8 GENMASK(127, 112) + +/* WRMEM1_13 register fields */ +#define WRMEM1_13_FLD1 GENMASK(15, 0) +#define WRMEM1_13_FLD2 GENMASK(31, 16) +#define WRMEM1_13_FLD3 GENMASK(47, 32) +#define WRMEM1_13_FLD4 GENMASK(63, 48) +#define WRMEM1_13_FLD5 GENMASK(79, 64) +#define WRMEM1_13_FLD6 GENMASK(95, 80) +#define WRMEM1_13_FLD7 GENMASK(111, 96) +#define WRMEM1_13_FLD8 GENMASK(127, 112) + +/* WRMEM1_14 register fields */ +#define WRMEM1_14_FLD1 GENMASK(15, 0) +#define WRMEM1_14_FLD2 GENMASK(31, 16) +#define WRMEM1_14_FLD3 GENMASK(47, 32) +#define WRMEM1_14_FLD4 GENMASK(63, 48) +#define WRMEM1_14_FLD5 GENMASK(79, 64) +#define WRMEM1_14_FLD6 GENMASK(95, 80) +#define WRMEM1_14_FLD7 GENMASK(111, 96) +#define WRMEM1_14_FLD8 GENMASK(127, 112) + +/* WRMEM1_15 register fields */ +#define WRMEM1_15_FLD1 GENMASK(15, 0) +#define WRMEM1_15_FLD2 GENMASK(31, 16) +#define WRMEM1_15_FLD3 GENMASK(47, 32) +#define WRMEM1_15_FLD4 GENMASK(63, 48) +#define WRMEM1_15_FLD5 GENMASK(79, 64) +#define WRMEM1_15_FLD6 GENMASK(95, 80) +#define WRMEM1_15_FLD7 GENMASK(111, 96) +#define WRMEM1_15_FLD8 GENMASK(127, 112) + +/* WRMEM1_16 register fields */ +#define WRMEM1_16_FLD1 GENMASK(15, 0) +#define WRMEM1_16_FLD2 GENMASK(31, 16) +#define WRMEM1_16_FLD3 GENMASK(47, 32) +#define WRMEM1_16_FLD4 GENMASK(63, 48) +#define WRMEM1_16_FLD5 GENMASK(79, 64) +#define WRMEM1_16_FLD6 GENMASK(95, 80) +#define WRMEM1_16_FLD7 GENMASK(111, 96) +#define WRMEM1_16_FLD8 GENMASK(127, 112) + +/* WRMEM1_17 register fields */ +#define WRMEM1_17_FLD1 GENMASK(15, 0) +#define WRMEM1_17_FLD2 GENMASK(31, 16) +#define WRMEM1_17_FLD3 GENMASK(47, 32) +#define WRMEM1_17_FLD4 GENMASK(63, 48) +#define WRMEM1_17_FLD5 GENMASK(79, 64) +#define WRMEM1_17_FLD6 GENMASK(95, 80) +#define WRMEM1_17_FLD7 GENMASK(111, 96) +#define WRMEM1_17_FLD8 GENMASK(127, 112) + +/* WRMEM1_18 register fields */ +#define WRMEM1_18_FLD1 GENMASK(15, 0) +#define WRMEM1_18_FLD2 GENMASK(31, 16) +#define WRMEM1_18_FLD3 GENMASK(47, 32) +#define WRMEM1_18_FLD4 GENMASK(63, 48) +#define WRMEM1_18_FLD5 GENMASK(79, 64) +#define WRMEM1_18_FLD6 GENMASK(95, 80) +#define WRMEM1_18_FLD7 GENMASK(111, 96) +#define WRMEM1_18_FLD8 GENMASK(127, 112) + +/* WRMEM1_19 register fields */ +#define WRMEM1_19_FLD1 GENMASK(15, 0) +#define WRMEM1_19_FLD2 GENMASK(31, 16) +#define WRMEM1_19_FLD3 GENMASK(47, 32) +#define WRMEM1_19_FLD4 GENMASK(63, 48) +#define WRMEM1_19_FLD5 GENMASK(79, 64) +#define WRMEM1_19_FLD6 GENMASK(95, 80) +#define WRMEM1_19_FLD7 GENMASK(111, 96) +#define WRMEM1_19_FLD8 GENMASK(127, 112) + +/* WRMEM1_20 register fields */ +#define WRMEM1_20_FLD1 GENMASK(15, 0) +#define WRMEM1_20_FLD2 GENMASK(31, 16) +#define WRMEM1_20_FLD3 GENMASK(47, 32) +#define WRMEM1_20_FLD4 GENMASK(63, 48) +#define WRMEM1_20_FLD5 GENMASK(79, 64) +#define WRMEM1_20_FLD6 GENMASK(95, 80) +#define WRMEM1_20_FLD7 GENMASK(111, 96) +#define WRMEM1_20_FLD8 GENMASK(127, 112) + +/* WRMEM1_21 register fields */ +#define WRMEM1_21_FLD1 GENMASK(15, 0) +#define WRMEM1_21_FLD2 GENMASK(31, 16) +#define WRMEM1_21_FLD3 GENMASK(47, 32) +#define WRMEM1_21_FLD4 GENMASK(63, 48) +#define WRMEM1_21_FLD5 GENMASK(79, 64) +#define WRMEM1_21_FLD6 GENMASK(95, 80) +#define WRMEM1_21_FLD7 GENMASK(111, 96) +#define WRMEM1_21_FLD8 GENMASK(127, 112) + +/* WRMEM1_22 register fields */ +#define WRMEM1_22_FLD1 GENMASK(15, 0) +#define WRMEM1_22_FLD2 GENMASK(31, 16) +#define WRMEM1_22_FLD3 GENMASK(47, 32) +#define WRMEM1_22_FLD4 GENMASK(63, 48) +#define WRMEM1_22_FLD5 GENMASK(79, 64) +#define WRMEM1_22_FLD6 GENMASK(95, 80) +#define WRMEM1_22_FLD7 GENMASK(111, 96) +#define WRMEM1_22_FLD8 GENMASK(127, 112) + +/* WRMEM1_23 register fields */ +#define WRMEM1_23_FLD1 GENMASK(15, 0) +#define WRMEM1_23_FLD2 GENMASK(31, 16) +#define WRMEM1_23_FLD3 GENMASK(47, 32) +#define WRMEM1_23_FLD4 GENMASK(63, 48) +#define WRMEM1_23_FLD5 GENMASK(79, 64) +#define WRMEM1_23_FLD6 GENMASK(95, 80) +#define WRMEM1_23_FLD7 GENMASK(111, 96) +#define WRMEM1_23_FLD8 GENMASK(127, 112) + +/* WRMEM1_24 register fields */ +#define WRMEM1_24_FLD1 GENMASK(15, 0) +#define WRMEM1_24_FLD2 GENMASK(31, 16) +#define WRMEM1_24_FLD3 GENMASK(47, 32) +#define WRMEM1_24_FLD4 GENMASK(63, 48) +#define WRMEM1_24_FLD5 GENMASK(79, 64) +#define WRMEM1_24_FLD6 GENMASK(95, 80) +#define WRMEM1_24_FLD7 GENMASK(111, 96) +#define WRMEM1_24_FLD8 GENMASK(127, 112) + +/* WRMEM1_25 register fields */ +#define WRMEM1_25_FLD1 GENMASK(15, 0) +#define WRMEM1_25_FLD2 GENMASK(31, 16) +#define WRMEM1_25_FLD3 GENMASK(47, 32) +#define WRMEM1_25_FLD4 GENMASK(63, 48) +#define WRMEM1_25_FLD5 GENMASK(79, 64) +#define WRMEM1_25_FLD6 GENMASK(95, 80) +#define WRMEM1_25_FLD7 GENMASK(111, 96) +#define WRMEM1_25_FLD8 GENMASK(127, 112) + +/* WRMEM1_26 register fields */ +#define WRMEM1_26_FLD1 GENMASK(15, 0) +#define WRMEM1_26_FLD2 GENMASK(31, 16) +#define WRMEM1_26_FLD3 GENMASK(47, 32) +#define WRMEM1_26_FLD4 GENMASK(63, 48) +#define WRMEM1_26_FLD5 GENMASK(79, 64) +#define WRMEM1_26_FLD6 GENMASK(95, 80) +#define WRMEM1_26_FLD7 GENMASK(111, 96) +#define WRMEM1_26_FLD8 GENMASK(127, 112) + +/* WRMEM1_27 register fields */ +#define WRMEM1_27_FLD1 GENMASK(15, 0) +#define WRMEM1_27_FLD2 GENMASK(31, 16) +#define WRMEM1_27_FLD3 GENMASK(47, 32) +#define WRMEM1_27_FLD4 GENMASK(63, 48) +#define WRMEM1_27_FLD5 GENMASK(79, 64) +#define WRMEM1_27_FLD6 GENMASK(95, 80) +#define WRMEM1_27_FLD7 GENMASK(111, 96) +#define WRMEM1_27_FLD8 GENMASK(127, 112) + +/* WRMEM1_28 register fields */ +#define WRMEM1_28_FLD1 GENMASK(15, 0) +#define WRMEM1_28_FLD2 GENMASK(31, 16) +#define WRMEM1_28_FLD3 GENMASK(47, 32) +#define WRMEM1_28_FLD4 GENMASK(63, 48) +#define WRMEM1_28_FLD5 GENMASK(79, 64) +#define WRMEM1_28_FLD6 GENMASK(95, 80) +#define WRMEM1_28_FLD7 GENMASK(111, 96) +#define WRMEM1_28_FLD8 GENMASK(127, 112) + +/* WRMEM1_29 register fields */ +#define WRMEM1_29_FLD1 GENMASK(15, 0) +#define WRMEM1_29_FLD2 GENMASK(31, 16) +#define WRMEM1_29_FLD3 GENMASK(47, 32) +#define WRMEM1_29_FLD4 GENMASK(63, 48) +#define WRMEM1_29_FLD5 GENMASK(79, 64) +#define WRMEM1_29_FLD6 GENMASK(95, 80) +#define WRMEM1_29_FLD7 GENMASK(111, 96) +#define WRMEM1_29_FLD8 GENMASK(127, 112) + +/* WRMEM1_30 register fields */ +#define WRMEM1_30_FLD1 GENMASK(15, 0) +#define WRMEM1_30_FLD2 GENMASK(31, 16) +#define WRMEM1_30_FLD3 GENMASK(47, 32) +#define WRMEM1_30_FLD4 GENMASK(63, 48) +#define WRMEM1_30_FLD5 GENMASK(79, 64) +#define WRMEM1_30_FLD6 GENMASK(95, 80) +#define WRMEM1_30_FLD7 GENMASK(111, 96) +#define WRMEM1_30_FLD8 GENMASK(127, 112) + +/* WRMEM1_31 register fields */ +#define WRMEM1_31_FLD1 GENMASK(15, 0) +#define WRMEM1_31_FLD2 GENMASK(31, 16) +#define WRMEM1_31_FLD3 GENMASK(47, 32) +#define WRMEM1_31_FLD4 GENMASK(63, 48) +#define WRMEM1_31_FLD5 GENMASK(79, 64) +#define WRMEM1_31_FLD6 GENMASK(95, 80) +#define WRMEM1_31_FLD7 GENMASK(111, 96) +#define WRMEM1_31_FLD8 GENMASK(127, 112) + +/* WRMEM1_32 register fields */ +#define WRMEM1_32_FLD1 GENMASK(15, 0) +#define WRMEM1_32_FLD2 GENMASK(31, 16) +#define WRMEM1_32_FLD3 GENMASK(47, 32) +#define WRMEM1_32_FLD4 GENMASK(63, 48) +#define WRMEM1_32_FLD5 GENMASK(79, 64) +#define WRMEM1_32_FLD6 GENMASK(95, 80) +#define WRMEM1_32_FLD7 GENMASK(111, 96) +#define WRMEM1_32_FLD8 GENMASK(127, 112) + +/* WRMEM1_33 register fields */ +#define WRMEM1_33_FLD1 GENMASK(15, 0) +#define WRMEM1_33_FLD2 GENMASK(31, 16) +#define WRMEM1_33_FLD3 GENMASK(47, 32) +#define WRMEM1_33_FLD4 GENMASK(63, 48) +#define WRMEM1_33_FLD5 GENMASK(79, 64) +#define WRMEM1_33_FLD6 GENMASK(95, 80) +#define WRMEM1_33_FLD7 GENMASK(111, 96) +#define WRMEM1_33_FLD8 GENMASK(127, 112) + +/* WRMEM1_34 register fields */ +#define WRMEM1_34_FLD1 GENMASK(15, 0) +#define WRMEM1_34_FLD2 GENMASK(31, 16) +#define WRMEM1_34_FLD3 GENMASK(47, 32) +#define WRMEM1_34_FLD4 GENMASK(63, 48) +#define WRMEM1_34_FLD5 GENMASK(79, 64) +#define WRMEM1_34_FLD6 GENMASK(95, 80) +#define WRMEM1_34_FLD7 GENMASK(111, 96) +#define WRMEM1_34_FLD8 GENMASK(127, 112) + +/* WRMEM1_35 register fields */ +#define WRMEM1_35_FLD1 GENMASK(15, 0) +#define WRMEM1_35_FLD2 GENMASK(31, 16) +#define WRMEM1_35_FLD3 GENMASK(47, 32) +#define WRMEM1_35_FLD4 GENMASK(63, 48) +#define WRMEM1_35_FLD5 GENMASK(79, 64) +#define WRMEM1_35_FLD6 GENMASK(95, 80) +#define WRMEM1_35_FLD7 GENMASK(111, 96) +#define WRMEM1_35_FLD8 GENMASK(127, 112) + +/* WRMEM1_36 register fields */ +#define WRMEM1_36_FLD1 GENMASK(15, 0) +#define WRMEM1_36_FLD2 GENMASK(31, 16) +#define WRMEM1_36_FLD3 GENMASK(47, 32) +#define WRMEM1_36_FLD4 GENMASK(63, 48) +#define WRMEM1_36_FLD5 GENMASK(79, 64) +#define WRMEM1_36_FLD6 GENMASK(95, 80) +#define WRMEM1_36_FLD7 GENMASK(111, 96) +#define WRMEM1_36_FLD8 GENMASK(127, 112) + +/* WRMEM1_37 register fields */ +#define WRMEM1_37_FLD1 GENMASK(15, 0) +#define WRMEM1_37_FLD2 GENMASK(31, 16) +#define WRMEM1_37_FLD3 GENMASK(47, 32) +#define WRMEM1_37_FLD4 GENMASK(63, 48) +#define WRMEM1_37_FLD5 GENMASK(79, 64) +#define WRMEM1_37_FLD6 GENMASK(95, 80) +#define WRMEM1_37_FLD7 GENMASK(111, 96) +#define WRMEM1_37_FLD8 GENMASK(127, 112) + +/* WRMEM1_38 register fields */ +#define WRMEM1_38_FLD1 GENMASK(15, 0) +#define WRMEM1_38_FLD2 GENMASK(31, 16) +#define WRMEM1_38_FLD3 GENMASK(47, 32) +#define WRMEM1_38_FLD4 GENMASK(63, 48) +#define WRMEM1_38_FLD5 GENMASK(79, 64) +#define WRMEM1_38_FLD6 GENMASK(95, 80) +#define WRMEM1_38_FLD7 GENMASK(111, 96) +#define WRMEM1_38_FLD8 GENMASK(127, 112) + +/* WRMEM1_39 register fields */ +#define WRMEM1_39_FLD1 GENMASK(15, 0) +#define WRMEM1_39_FLD2 GENMASK(31, 16) +#define WRMEM1_39_FLD3 GENMASK(47, 32) +#define WRMEM1_39_FLD4 GENMASK(63, 48) +#define WRMEM1_39_FLD5 GENMASK(79, 64) +#define WRMEM1_39_FLD6 GENMASK(95, 80) +#define WRMEM1_39_FLD7 GENMASK(111, 96) +#define WRMEM1_39_FLD8 GENMASK(127, 112) + +/* WRMEM1_40 register fields */ +#define WRMEM1_40_FLD1 GENMASK(15, 0) +#define WRMEM1_40_FLD2 GENMASK(31, 16) +#define WRMEM1_40_FLD3 GENMASK(47, 32) +#define WRMEM1_40_FLD4 GENMASK(63, 48) +#define WRMEM1_40_FLD5 GENMASK(79, 64) +#define WRMEM1_40_FLD6 GENMASK(95, 80) +#define WRMEM1_40_FLD7 GENMASK(111, 96) +#define WRMEM1_40_FLD8 GENMASK(127, 112) + +/* WRMEM1_41 register fields */ +#define WRMEM1_41_FLD1 GENMASK(15, 0) +#define WRMEM1_41_FLD2 GENMASK(31, 16) +#define WRMEM1_41_FLD3 GENMASK(47, 32) +#define WRMEM1_41_FLD4 GENMASK(63, 48) +#define WRMEM1_41_FLD5 GENMASK(79, 64) +#define WRMEM1_41_FLD6 GENMASK(95, 80) +#define WRMEM1_41_FLD7 GENMASK(111, 96) +#define WRMEM1_41_FLD8 GENMASK(127, 112) + +/* WRMEM1_42 register fields */ +#define WRMEM1_42_FLD1 GENMASK(15, 0) +#define WRMEM1_42_FLD2 GENMASK(31, 16) +#define WRMEM1_42_FLD3 GENMASK(47, 32) +#define WRMEM1_42_FLD4 GENMASK(63, 48) +#define WRMEM1_42_FLD5 GENMASK(79, 64) +#define WRMEM1_42_FLD6 GENMASK(95, 80) +#define WRMEM1_42_FLD7 GENMASK(111, 96) +#define WRMEM1_42_FLD8 GENMASK(127, 112) + +/* WRMEM1_43 register fields */ +#define WRMEM1_43_FLD1 GENMASK(15, 0) +#define WRMEM1_43_FLD2 GENMASK(31, 16) +#define WRMEM1_43_FLD3 GENMASK(47, 32) +#define WRMEM1_43_FLD4 GENMASK(63, 48) +#define WRMEM1_43_FLD5 GENMASK(79, 64) +#define WRMEM1_43_FLD6 GENMASK(95, 80) +#define WRMEM1_43_FLD7 GENMASK(111, 96) +#define WRMEM1_43_FLD8 GENMASK(127, 112) + +/* WRMEM1_44 register fields */ +#define WRMEM1_44_FLD1 GENMASK(15, 0) +#define WRMEM1_44_FLD2 GENMASK(31, 16) +#define WRMEM1_44_FLD3 GENMASK(47, 32) +#define WRMEM1_44_FLD4 GENMASK(63, 48) +#define WRMEM1_44_FLD5 GENMASK(79, 64) +#define WRMEM1_44_FLD6 GENMASK(95, 80) +#define WRMEM1_44_FLD7 GENMASK(111, 96) +#define WRMEM1_44_FLD8 GENMASK(127, 112) + +/* WRMEM1_45 register fields */ +#define WRMEM1_45_FLD1 GENMASK(15, 0) +#define WRMEM1_45_FLD2 GENMASK(31, 16) +#define WRMEM1_45_FLD3 GENMASK(47, 32) +#define WRMEM1_45_FLD4 GENMASK(63, 48) +#define WRMEM1_45_FLD5 GENMASK(79, 64) +#define WRMEM1_45_FLD6 GENMASK(95, 80) +#define WRMEM1_45_FLD7 GENMASK(111, 96) +#define WRMEM1_45_FLD8 GENMASK(127, 112) + +/* WRMEM1_46 register fields */ +#define WRMEM1_46_FLD1 GENMASK(15, 0) +#define WRMEM1_46_FLD2 GENMASK(31, 16) +#define WRMEM1_46_FLD3 GENMASK(47, 32) +#define WRMEM1_46_FLD4 GENMASK(63, 48) +#define WRMEM1_46_FLD5 GENMASK(79, 64) +#define WRMEM1_46_FLD6 GENMASK(95, 80) +#define WRMEM1_46_FLD7 GENMASK(111, 96) +#define WRMEM1_46_FLD8 GENMASK(127, 112) + +/* WRMEM1_47 register fields */ +#define WRMEM1_47_FLD1 GENMASK(15, 0) +#define WRMEM1_47_FLD2 GENMASK(31, 16) +#define WRMEM1_47_FLD3 GENMASK(47, 32) +#define WRMEM1_47_FLD4 GENMASK(63, 48) +#define WRMEM1_47_FLD5 GENMASK(79, 64) +#define WRMEM1_47_FLD6 GENMASK(95, 80) +#define WRMEM1_47_FLD7 GENMASK(111, 96) +#define WRMEM1_47_FLD8 GENMASK(127, 112) + +/* WRMEM1_48 register fields */ +#define WRMEM1_48_FLD1 GENMASK(15, 0) +#define WRMEM1_48_FLD2 GENMASK(31, 16) +#define WRMEM1_48_FLD3 GENMASK(47, 32) +#define WRMEM1_48_FLD4 GENMASK(63, 48) +#define WRMEM1_48_FLD5 GENMASK(79, 64) +#define WRMEM1_48_FLD6 GENMASK(95, 80) +#define WRMEM1_48_FLD7 GENMASK(111, 96) +#define WRMEM1_48_FLD8 GENMASK(127, 112) + +/* WRMEM1_49 register fields */ +#define WRMEM1_49_FLD1 GENMASK(15, 0) +#define WRMEM1_49_FLD2 GENMASK(31, 16) +#define WRMEM1_49_FLD3 GENMASK(47, 32) +#define WRMEM1_49_FLD4 GENMASK(63, 48) +#define WRMEM1_49_FLD5 GENMASK(79, 64) +#define WRMEM1_49_FLD6 GENMASK(95, 80) +#define WRMEM1_49_FLD7 GENMASK(111, 96) +#define WRMEM1_49_FLD8 GENMASK(127, 112) + +/* WRMEM1_50 register fields */ +#define WRMEM1_50_FLD1 GENMASK(15, 0) +#define WRMEM1_50_FLD2 GENMASK(31, 16) +#define WRMEM1_50_FLD3 GENMASK(47, 32) +#define WRMEM1_50_FLD4 GENMASK(63, 48) +#define WRMEM1_50_FLD5 GENMASK(79, 64) +#define WRMEM1_50_FLD6 GENMASK(95, 80) +#define WRMEM1_50_FLD7 GENMASK(111, 96) +#define WRMEM1_50_FLD8 GENMASK(127, 112) + +/* WRMEM1_51 register fields */ +#define WRMEM1_51_FLD1 GENMASK(15, 0) +#define WRMEM1_51_FLD2 GENMASK(31, 16) +#define WRMEM1_51_FLD3 GENMASK(47, 32) +#define WRMEM1_51_FLD4 GENMASK(63, 48) +#define WRMEM1_51_FLD5 GENMASK(79, 64) +#define WRMEM1_51_FLD6 GENMASK(95, 80) +#define WRMEM1_51_FLD7 GENMASK(111, 96) +#define WRMEM1_51_FLD8 GENMASK(127, 112) + +/* WRMEM1_52 register fields */ +#define WRMEM1_52_FLD1 GENMASK(15, 0) +#define WRMEM1_52_FLD2 GENMASK(31, 16) +#define WRMEM1_52_FLD3 GENMASK(47, 32) +#define WRMEM1_52_FLD4 GENMASK(63, 48) +#define WRMEM1_52_FLD5 GENMASK(79, 64) +#define WRMEM1_52_FLD6 GENMASK(95, 80) +#define WRMEM1_52_FLD7 GENMASK(111, 96) +#define WRMEM1_52_FLD8 GENMASK(127, 112) + +/* WRMEM1_53 register fields */ +#define WRMEM1_53_FLD1 GENMASK(15, 0) +#define WRMEM1_53_FLD2 GENMASK(31, 16) +#define WRMEM1_53_FLD3 GENMASK(47, 32) +#define WRMEM1_53_FLD4 GENMASK(63, 48) +#define WRMEM1_53_FLD5 GENMASK(79, 64) +#define WRMEM1_53_FLD6 GENMASK(95, 80) +#define WRMEM1_53_FLD7 GENMASK(111, 96) +#define WRMEM1_53_FLD8 GENMASK(127, 112) + +/* WRMEM1_54 register fields */ +#define WRMEM1_54_FLD1 GENMASK(15, 0) +#define WRMEM1_54_FLD2 GENMASK(31, 16) +#define WRMEM1_54_FLD3 GENMASK(47, 32) +#define WRMEM1_54_FLD4 GENMASK(63, 48) +#define WRMEM1_54_FLD5 GENMASK(79, 64) +#define WRMEM1_54_FLD6 GENMASK(95, 80) +#define WRMEM1_54_FLD7 GENMASK(111, 96) +#define WRMEM1_54_FLD8 GENMASK(127, 112) + +/* WRMEM1_55 register fields */ +#define WRMEM1_55_FLD1 GENMASK(15, 0) +#define WRMEM1_55_FLD2 GENMASK(31, 16) +#define WRMEM1_55_FLD3 GENMASK(47, 32) +#define WRMEM1_55_FLD4 GENMASK(63, 48) +#define WRMEM1_55_FLD5 GENMASK(79, 64) +#define WRMEM1_55_FLD6 GENMASK(95, 80) +#define WRMEM1_55_FLD7 GENMASK(111, 96) +#define WRMEM1_55_FLD8 GENMASK(127, 112) + +/* WRMEM1_56 register fields */ +#define WRMEM1_56_FLD1 GENMASK(15, 0) +#define WRMEM1_56_FLD2 GENMASK(31, 16) +#define WRMEM1_56_FLD3 GENMASK(47, 32) +#define WRMEM1_56_FLD4 GENMASK(63, 48) +#define WRMEM1_56_FLD5 GENMASK(79, 64) +#define WRMEM1_56_FLD6 GENMASK(95, 80) +#define WRMEM1_56_FLD7 GENMASK(111, 96) +#define WRMEM1_56_FLD8 GENMASK(127, 112) + +/* WRMEM1_57 register fields */ +#define WRMEM1_57_FLD1 GENMASK(15, 0) +#define WRMEM1_57_FLD2 GENMASK(31, 16) +#define WRMEM1_57_FLD3 GENMASK(47, 32) +#define WRMEM1_57_FLD4 GENMASK(63, 48) +#define WRMEM1_57_FLD5 GENMASK(79, 64) +#define WRMEM1_57_FLD6 GENMASK(95, 80) +#define WRMEM1_57_FLD7 GENMASK(111, 96) +#define WRMEM1_57_FLD8 GENMASK(127, 112) + +/* WRMEM1_58 register fields */ +#define WRMEM1_58_FLD1 GENMASK(15, 0) +#define WRMEM1_58_FLD2 GENMASK(31, 16) +#define WRMEM1_58_FLD3 GENMASK(47, 32) +#define WRMEM1_58_FLD4 GENMASK(63, 48) +#define WRMEM1_58_FLD5 GENMASK(79, 64) +#define WRMEM1_58_FLD6 GENMASK(95, 80) +#define WRMEM1_58_FLD7 GENMASK(111, 96) +#define WRMEM1_58_FLD8 GENMASK(127, 112) + +/* WRMEM1_59 register fields */ +#define WRMEM1_59_FLD1 GENMASK(15, 0) +#define WRMEM1_59_FLD2 GENMASK(31, 16) +#define WRMEM1_59_FLD3 GENMASK(47, 32) +#define WRMEM1_59_FLD4 GENMASK(63, 48) +#define WRMEM1_59_FLD5 GENMASK(79, 64) +#define WRMEM1_59_FLD6 GENMASK(95, 80) +#define WRMEM1_59_FLD7 GENMASK(111, 96) +#define WRMEM1_59_FLD8 GENMASK(127, 112) + +/* WRMEM1_60 register fields */ +#define WRMEM1_60_FLD1 GENMASK(15, 0) +#define WRMEM1_60_FLD2 GENMASK(31, 16) +#define WRMEM1_60_FLD3 GENMASK(47, 32) +#define WRMEM1_60_FLD4 GENMASK(63, 48) +#define WRMEM1_60_FLD5 GENMASK(79, 64) +#define WRMEM1_60_FLD6 GENMASK(95, 80) +#define WRMEM1_60_FLD7 GENMASK(111, 96) +#define WRMEM1_60_FLD8 GENMASK(127, 112) + +/* WRMEM1_61 register fields */ +#define WRMEM1_61_FLD1 GENMASK(15, 0) +#define WRMEM1_61_FLD2 GENMASK(31, 16) +#define WRMEM1_61_FLD3 GENMASK(47, 32) +#define WRMEM1_61_FLD4 GENMASK(63, 48) +#define WRMEM1_61_FLD5 GENMASK(79, 64) +#define WRMEM1_61_FLD6 GENMASK(95, 80) +#define WRMEM1_61_FLD7 GENMASK(111, 96) +#define WRMEM1_61_FLD8 GENMASK(127, 112) + +/* WRMEM1_62 register fields */ +#define WRMEM1_62_FLD1 GENMASK(15, 0) +#define WRMEM1_62_FLD2 GENMASK(31, 16) +#define WRMEM1_62_FLD3 GENMASK(47, 32) +#define WRMEM1_62_FLD4 GENMASK(63, 48) +#define WRMEM1_62_FLD5 GENMASK(79, 64) +#define WRMEM1_62_FLD6 GENMASK(95, 80) +#define WRMEM1_62_FLD7 GENMASK(111, 96) +#define WRMEM1_62_FLD8 GENMASK(127, 112) + +/* WRMEM1_63 register fields */ +#define WRMEM1_63_FLD1 GENMASK(15, 0) +#define WRMEM1_63_FLD2 GENMASK(31, 16) +#define WRMEM1_63_FLD3 GENMASK(47, 32) +#define WRMEM1_63_FLD4 GENMASK(63, 48) +#define WRMEM1_63_FLD5 GENMASK(79, 64) +#define WRMEM1_63_FLD6 GENMASK(95, 80) +#define WRMEM1_63_FLD7 GENMASK(111, 96) +#define WRMEM1_63_FLD8 GENMASK(127, 112) + +/* WRMEM1_64 register fields */ +#define WRMEM1_64_FLD1 GENMASK(15, 0) +#define WRMEM1_64_FLD2 GENMASK(31, 16) +#define WRMEM1_64_FLD3 GENMASK(47, 32) +#define WRMEM1_64_FLD4 GENMASK(63, 48) +#define WRMEM1_64_FLD5 GENMASK(79, 64) +#define WRMEM1_64_FLD6 GENMASK(95, 80) +#define WRMEM1_64_FLD7 GENMASK(111, 96) +#define WRMEM1_64_FLD8 GENMASK(127, 112) + +/* WRMEM1_65 register fields */ +#define WRMEM1_65_FLD1 GENMASK(15, 0) +#define WRMEM1_65_FLD2 GENMASK(31, 16) +#define WRMEM1_65_FLD3 GENMASK(47, 32) +#define WRMEM1_65_FLD4 GENMASK(63, 48) +#define WRMEM1_65_FLD5 GENMASK(79, 64) +#define WRMEM1_65_FLD6 GENMASK(95, 80) +#define WRMEM1_65_FLD7 GENMASK(111, 96) +#define WRMEM1_65_FLD8 GENMASK(127, 112) + +/* WRMEM1_66 register fields */ +#define WRMEM1_66_FLD1 GENMASK(15, 0) +#define WRMEM1_66_FLD2 GENMASK(31, 16) +#define WRMEM1_66_FLD3 GENMASK(47, 32) +#define WRMEM1_66_FLD4 GENMASK(63, 48) +#define WRMEM1_66_FLD5 GENMASK(79, 64) +#define WRMEM1_66_FLD6 GENMASK(95, 80) +#define WRMEM1_66_FLD7 GENMASK(111, 96) +#define WRMEM1_66_FLD8 GENMASK(127, 112) + +/* WRMEM1_67 register fields */ +#define WRMEM1_67_FLD1 GENMASK(15, 0) +#define WRMEM1_67_FLD2 GENMASK(31, 16) +#define WRMEM1_67_FLD3 GENMASK(47, 32) +#define WRMEM1_67_FLD4 GENMASK(63, 48) +#define WRMEM1_67_FLD5 GENMASK(79, 64) +#define WRMEM1_67_FLD6 GENMASK(95, 80) +#define WRMEM1_67_FLD7 GENMASK(111, 96) +#define WRMEM1_67_FLD8 GENMASK(127, 112) + +/* WRMEM1_68 register fields */ +#define WRMEM1_68_FLD1 GENMASK(15, 0) +#define WRMEM1_68_FLD2 GENMASK(31, 16) +#define WRMEM1_68_FLD3 GENMASK(47, 32) +#define WRMEM1_68_FLD4 GENMASK(63, 48) +#define WRMEM1_68_FLD5 GENMASK(79, 64) +#define WRMEM1_68_FLD6 GENMASK(95, 80) +#define WRMEM1_68_FLD7 GENMASK(111, 96) +#define WRMEM1_68_FLD8 GENMASK(127, 112) + +/* WRMEM1_69 register fields */ +#define WRMEM1_69_FLD1 GENMASK(15, 0) +#define WRMEM1_69_FLD2 GENMASK(31, 16) +#define WRMEM1_69_FLD3 GENMASK(47, 32) +#define WRMEM1_69_FLD4 GENMASK(63, 48) +#define WRMEM1_69_FLD5 GENMASK(79, 64) +#define WRMEM1_69_FLD6 GENMASK(95, 80) +#define WRMEM1_69_FLD7 GENMASK(111, 96) +#define WRMEM1_69_FLD8 GENMASK(127, 112) + +/* WRMEM1_70 register fields */ +#define WRMEM1_70_FLD1 GENMASK(15, 0) +#define WRMEM1_70_FLD2 GENMASK(31, 16) +#define WRMEM1_70_FLD3 GENMASK(47, 32) +#define WRMEM1_70_FLD4 GENMASK(63, 48) +#define WRMEM1_70_FLD5 GENMASK(79, 64) +#define WRMEM1_70_FLD6 GENMASK(95, 80) +#define WRMEM1_70_FLD7 GENMASK(111, 96) +#define WRMEM1_70_FLD8 GENMASK(127, 112) + +/* WRMEM1_71 register fields */ +#define WRMEM1_71_FLD1 GENMASK(15, 0) +#define WRMEM1_71_FLD2 GENMASK(31, 16) +#define WRMEM1_71_FLD3 GENMASK(47, 32) +#define WRMEM1_71_FLD4 GENMASK(63, 48) +#define WRMEM1_71_FLD5 GENMASK(79, 64) +#define WRMEM1_71_FLD6 GENMASK(95, 80) +#define WRMEM1_71_FLD7 GENMASK(111, 96) +#define WRMEM1_71_FLD8 GENMASK(127, 112) + +/* WRMEM1_72 register fields */ +#define WRMEM1_72_FLD1 GENMASK(15, 0) +#define WRMEM1_72_FLD2 GENMASK(31, 16) +#define WRMEM1_72_FLD3 GENMASK(47, 32) +#define WRMEM1_72_FLD4 GENMASK(63, 48) +#define WRMEM1_72_FLD5 GENMASK(79, 64) +#define WRMEM1_72_FLD6 GENMASK(95, 80) +#define WRMEM1_72_FLD7 GENMASK(111, 96) +#define WRMEM1_72_FLD8 GENMASK(127, 112) + +/* WRMEM1_73 register fields */ +#define WRMEM1_73_FLD1 GENMASK(15, 0) +#define WRMEM1_73_FLD2 GENMASK(31, 16) +#define WRMEM1_73_FLD3 GENMASK(47, 32) +#define WRMEM1_73_FLD4 GENMASK(63, 48) +#define WRMEM1_73_FLD5 GENMASK(79, 64) +#define WRMEM1_73_FLD6 GENMASK(95, 80) +#define WRMEM1_73_FLD7 GENMASK(111, 96) +#define WRMEM1_73_FLD8 GENMASK(127, 112) + +/* WRMEM1_74 register fields */ +#define WRMEM1_74_FLD1 GENMASK(15, 0) +#define WRMEM1_74_FLD2 GENMASK(31, 16) +#define WRMEM1_74_FLD3 GENMASK(47, 32) +#define WRMEM1_74_FLD4 GENMASK(63, 48) +#define WRMEM1_74_FLD5 GENMASK(79, 64) +#define WRMEM1_74_FLD6 GENMASK(95, 80) +#define WRMEM1_74_FLD7 GENMASK(111, 96) +#define WRMEM1_74_FLD8 GENMASK(127, 112) + +/* WRMEM1_75 register fields */ +#define WRMEM1_75_FLD1 GENMASK(15, 0) +#define WRMEM1_75_FLD2 GENMASK(31, 16) +#define WRMEM1_75_FLD3 GENMASK(47, 32) +#define WRMEM1_75_FLD4 GENMASK(63, 48) +#define WRMEM1_75_FLD5 GENMASK(79, 64) +#define WRMEM1_75_FLD6 GENMASK(95, 80) +#define WRMEM1_75_FLD7 GENMASK(111, 96) +#define WRMEM1_75_FLD8 GENMASK(127, 112) + +/* WRMEM1_76 register fields */ +#define WRMEM1_76_FLD1 GENMASK(15, 0) +#define WRMEM1_76_FLD2 GENMASK(31, 16) +#define WRMEM1_76_FLD3 GENMASK(47, 32) +#define WRMEM1_76_FLD4 GENMASK(63, 48) +#define WRMEM1_76_FLD5 GENMASK(79, 64) +#define WRMEM1_76_FLD6 GENMASK(95, 80) +#define WRMEM1_76_FLD7 GENMASK(111, 96) +#define WRMEM1_76_FLD8 GENMASK(127, 112) + +/* WRMEM1_77 register fields */ +#define WRMEM1_77_FLD1 GENMASK(15, 0) +#define WRMEM1_77_FLD2 GENMASK(31, 16) +#define WRMEM1_77_FLD3 GENMASK(47, 32) +#define WRMEM1_77_FLD4 GENMASK(63, 48) +#define WRMEM1_77_FLD5 GENMASK(79, 64) +#define WRMEM1_77_FLD6 GENMASK(95, 80) +#define WRMEM1_77_FLD7 GENMASK(111, 96) +#define WRMEM1_77_FLD8 GENMASK(127, 112) + +/* WRMEM1_78 register fields */ +#define WRMEM1_78_FLD1 GENMASK(15, 0) +#define WRMEM1_78_FLD2 GENMASK(31, 16) +#define WRMEM1_78_FLD3 GENMASK(47, 32) +#define WRMEM1_78_FLD4 GENMASK(63, 48) +#define WRMEM1_78_FLD5 GENMASK(79, 64) +#define WRMEM1_78_FLD6 GENMASK(95, 80) +#define WRMEM1_78_FLD7 GENMASK(111, 96) +#define WRMEM1_78_FLD8 GENMASK(127, 112) + +/* WRMEM1_79 register fields */ +#define WRMEM1_79_FLD1 GENMASK(15, 0) +#define WRMEM1_79_FLD2 GENMASK(31, 16) +#define WRMEM1_79_FLD3 GENMASK(47, 32) +#define WRMEM1_79_FLD4 GENMASK(63, 48) +#define WRMEM1_79_FLD5 GENMASK(79, 64) +#define WRMEM1_79_FLD6 GENMASK(95, 80) +#define WRMEM1_79_FLD7 GENMASK(111, 96) +#define WRMEM1_79_FLD8 GENMASK(127, 112) + +/* WRMEM1_80 register fields */ +#define WRMEM1_80_FLD1 GENMASK(15, 0) +#define WRMEM1_80_FLD2 GENMASK(31, 16) +#define WRMEM1_80_FLD3 GENMASK(47, 32) +#define WRMEM1_80_FLD4 GENMASK(63, 48) +#define WRMEM1_80_FLD5 GENMASK(79, 64) +#define WRMEM1_80_FLD6 GENMASK(95, 80) +#define WRMEM1_80_FLD7 GENMASK(111, 96) +#define WRMEM1_80_FLD8 GENMASK(127, 112) + +/* WRMEM1_81 register fields */ +#define WRMEM1_81_FLD1 GENMASK(15, 0) +#define WRMEM1_81_FLD2 GENMASK(31, 16) +#define WRMEM1_81_FLD3 GENMASK(47, 32) +#define WRMEM1_81_FLD4 GENMASK(63, 48) +#define WRMEM1_81_FLD5 GENMASK(79, 64) +#define WRMEM1_81_FLD6 GENMASK(95, 80) +#define WRMEM1_81_FLD7 GENMASK(111, 96) +#define WRMEM1_81_FLD8 GENMASK(127, 112) + +/* WRMEM1_82 register fields */ +#define WRMEM1_82_FLD1 GENMASK(15, 0) +#define WRMEM1_82_FLD2 GENMASK(31, 16) +#define WRMEM1_82_FLD3 GENMASK(47, 32) +#define WRMEM1_82_FLD4 GENMASK(63, 48) +#define WRMEM1_82_FLD5 GENMASK(79, 64) +#define WRMEM1_82_FLD6 GENMASK(95, 80) +#define WRMEM1_82_FLD7 GENMASK(111, 96) +#define WRMEM1_82_FLD8 GENMASK(127, 112) + +/* WRMEM1_83 register fields */ +#define WRMEM1_83_FLD1 GENMASK(15, 0) +#define WRMEM1_83_FLD2 GENMASK(31, 16) +#define WRMEM1_83_FLD3 GENMASK(47, 32) +#define WRMEM1_83_FLD4 GENMASK(63, 48) +#define WRMEM1_83_FLD5 GENMASK(79, 64) +#define WRMEM1_83_FLD6 GENMASK(95, 80) +#define WRMEM1_83_FLD7 GENMASK(111, 96) +#define WRMEM1_83_FLD8 GENMASK(127, 112) + +/* WRMEM1_84 register fields */ +#define WRMEM1_84_FLD1 GENMASK(15, 0) +#define WRMEM1_84_FLD2 GENMASK(31, 16) +#define WRMEM1_84_FLD3 GENMASK(47, 32) +#define WRMEM1_84_FLD4 GENMASK(63, 48) +#define WRMEM1_84_FLD5 GENMASK(79, 64) +#define WRMEM1_84_FLD6 GENMASK(95, 80) +#define WRMEM1_84_FLD7 GENMASK(111, 96) +#define WRMEM1_84_FLD8 GENMASK(127, 112) + +/* WRMEM1_85 register fields */ +#define WRMEM1_85_FLD1 GENMASK(15, 0) +#define WRMEM1_85_FLD2 GENMASK(31, 16) +#define WRMEM1_85_FLD3 GENMASK(47, 32) +#define WRMEM1_85_FLD4 GENMASK(63, 48) +#define WRMEM1_85_FLD5 GENMASK(79, 64) +#define WRMEM1_85_FLD6 GENMASK(95, 80) +#define WRMEM1_85_FLD7 GENMASK(111, 96) +#define WRMEM1_85_FLD8 GENMASK(127, 112) + +/* WRMEM1_86 register fields */ +#define WRMEM1_86_FLD1 GENMASK(15, 0) +#define WRMEM1_86_FLD2 GENMASK(31, 16) +#define WRMEM1_86_FLD3 GENMASK(47, 32) +#define WRMEM1_86_FLD4 GENMASK(63, 48) +#define WRMEM1_86_FLD5 GENMASK(79, 64) +#define WRMEM1_86_FLD6 GENMASK(95, 80) +#define WRMEM1_86_FLD7 GENMASK(111, 96) +#define WRMEM1_86_FLD8 GENMASK(127, 112) + +/* WRMEM1_87 register fields */ +#define WRMEM1_87_FLD1 GENMASK(15, 0) +#define WRMEM1_87_FLD2 GENMASK(31, 16) +#define WRMEM1_87_FLD3 GENMASK(47, 32) +#define WRMEM1_87_FLD4 GENMASK(63, 48) +#define WRMEM1_87_FLD5 GENMASK(79, 64) +#define WRMEM1_87_FLD6 GENMASK(95, 80) +#define WRMEM1_87_FLD7 GENMASK(111, 96) +#define WRMEM1_87_FLD8 GENMASK(127, 112) + +/* WRMEM1_88 register fields */ +#define WRMEM1_88_FLD1 GENMASK(15, 0) +#define WRMEM1_88_FLD2 GENMASK(31, 16) +#define WRMEM1_88_FLD3 GENMASK(47, 32) +#define WRMEM1_88_FLD4 GENMASK(63, 48) +#define WRMEM1_88_FLD5 GENMASK(79, 64) +#define WRMEM1_88_FLD6 GENMASK(95, 80) +#define WRMEM1_88_FLD7 GENMASK(111, 96) +#define WRMEM1_88_FLD8 GENMASK(127, 112) + +/* WRMEM1_89 register fields */ +#define WRMEM1_89_FLD1 GENMASK(15, 0) +#define WRMEM1_89_FLD2 GENMASK(31, 16) +#define WRMEM1_89_FLD3 GENMASK(47, 32) +#define WRMEM1_89_FLD4 GENMASK(63, 48) +#define WRMEM1_89_FLD5 GENMASK(79, 64) +#define WRMEM1_89_FLD6 GENMASK(95, 80) +#define WRMEM1_89_FLD7 GENMASK(111, 96) +#define WRMEM1_89_FLD8 GENMASK(127, 112) + +/* WRMEM1_90 register fields */ +#define WRMEM1_90_FLD1 GENMASK(15, 0) +#define WRMEM1_90_FLD2 GENMASK(31, 16) +#define WRMEM1_90_FLD3 GENMASK(47, 32) +#define WRMEM1_90_FLD4 GENMASK(63, 48) +#define WRMEM1_90_FLD5 GENMASK(79, 64) +#define WRMEM1_90_FLD6 GENMASK(95, 80) +#define WRMEM1_90_FLD7 GENMASK(111, 96) +#define WRMEM1_90_FLD8 GENMASK(127, 112) + +/* WRMEM1_91 register fields */ +#define WRMEM1_91_FLD1 GENMASK(15, 0) +#define WRMEM1_91_FLD2 GENMASK(31, 16) +#define WRMEM1_91_FLD3 GENMASK(47, 32) +#define WRMEM1_91_FLD4 GENMASK(63, 48) +#define WRMEM1_91_FLD5 GENMASK(79, 64) +#define WRMEM1_91_FLD6 GENMASK(95, 80) +#define WRMEM1_91_FLD7 GENMASK(111, 96) +#define WRMEM1_91_FLD8 GENMASK(127, 112) + +/* WRMEM1_92 register fields */ +#define WRMEM1_92_FLD1 GENMASK(15, 0) +#define WRMEM1_92_FLD2 GENMASK(31, 16) +#define WRMEM1_92_FLD3 GENMASK(47, 32) +#define WRMEM1_92_FLD4 GENMASK(63, 48) +#define WRMEM1_92_FLD5 GENMASK(79, 64) +#define WRMEM1_92_FLD6 GENMASK(95, 80) +#define WRMEM1_92_FLD7 GENMASK(111, 96) +#define WRMEM1_92_FLD8 GENMASK(127, 112) + +/* WRMEM1_93 register fields */ +#define WRMEM1_93_FLD1 GENMASK(15, 0) +#define WRMEM1_93_FLD2 GENMASK(31, 16) +#define WRMEM1_93_FLD3 GENMASK(47, 32) +#define WRMEM1_93_FLD4 GENMASK(63, 48) +#define WRMEM1_93_FLD5 GENMASK(79, 64) +#define WRMEM1_93_FLD6 GENMASK(95, 80) +#define WRMEM1_93_FLD7 GENMASK(111, 96) +#define WRMEM1_93_FLD8 GENMASK(127, 112) + +/* WRMEM1_94 register fields */ +#define WRMEM1_94_FLD1 GENMASK(15, 0) +#define WRMEM1_94_FLD2 GENMASK(31, 16) +#define WRMEM1_94_FLD3 GENMASK(47, 32) +#define WRMEM1_94_FLD4 GENMASK(63, 48) +#define WRMEM1_94_FLD5 GENMASK(79, 64) +#define WRMEM1_94_FLD6 GENMASK(95, 80) +#define WRMEM1_94_FLD7 GENMASK(111, 96) +#define WRMEM1_94_FLD8 GENMASK(127, 112) + +/* WRMEM1_95 register fields */ +#define WRMEM1_95_FLD1 GENMASK(15, 0) +#define WRMEM1_95_FLD2 GENMASK(31, 16) +#define WRMEM1_95_FLD3 GENMASK(47, 32) +#define WRMEM1_95_FLD4 GENMASK(63, 48) +#define WRMEM1_95_FLD5 GENMASK(79, 64) +#define WRMEM1_95_FLD6 GENMASK(95, 80) +#define WRMEM1_95_FLD7 GENMASK(111, 96) +#define WRMEM1_95_FLD8 GENMASK(127, 112) + +/* WRMEM1_96 register fields */ +#define WRMEM1_96_FLD1 GENMASK(15, 0) +#define WRMEM1_96_FLD2 GENMASK(31, 16) +#define WRMEM1_96_FLD3 GENMASK(47, 32) +#define WRMEM1_96_FLD4 GENMASK(63, 48) +#define WRMEM1_96_FLD5 GENMASK(79, 64) +#define WRMEM1_96_FLD6 GENMASK(95, 80) +#define WRMEM1_96_FLD7 GENMASK(111, 96) +#define WRMEM1_96_FLD8 GENMASK(127, 112) + +/* WRMEM1_97 register fields */ +#define WRMEM1_97_FLD1 GENMASK(15, 0) +#define WRMEM1_97_FLD2 GENMASK(31, 16) +#define WRMEM1_97_FLD3 GENMASK(47, 32) +#define WRMEM1_97_FLD4 GENMASK(63, 48) +#define WRMEM1_97_FLD5 GENMASK(79, 64) +#define WRMEM1_97_FLD6 GENMASK(95, 80) +#define WRMEM1_97_FLD7 GENMASK(111, 96) +#define WRMEM1_97_FLD8 GENMASK(127, 112) + +/* WRMEM1_98 register fields */ +#define WRMEM1_98_FLD1 GENMASK(15, 0) +#define WRMEM1_98_FLD2 GENMASK(31, 16) +#define WRMEM1_98_FLD3 GENMASK(47, 32) +#define WRMEM1_98_FLD4 GENMASK(63, 48) +#define WRMEM1_98_FLD5 GENMASK(79, 64) +#define WRMEM1_98_FLD6 GENMASK(95, 80) +#define WRMEM1_98_FLD7 GENMASK(111, 96) +#define WRMEM1_98_FLD8 GENMASK(127, 112) + +/* WRMEM1_99 register fields */ +#define WRMEM1_99_FLD1 GENMASK(15, 0) +#define WRMEM1_99_FLD2 GENMASK(31, 16) +#define WRMEM1_99_FLD3 GENMASK(47, 32) +#define WRMEM1_99_FLD4 GENMASK(63, 48) +#define WRMEM1_99_FLD5 GENMASK(79, 64) +#define WRMEM1_99_FLD6 GENMASK(95, 80) +#define WRMEM1_99_FLD7 GENMASK(111, 96) +#define WRMEM1_99_FLD8 GENMASK(127, 112) + +/* WRMEM1_100 register fields */ +#define WRMEM1_100_FLD1 GENMASK(15, 0) +#define WRMEM1_100_FLD2 GENMASK(31, 16) +#define WRMEM1_100_FLD3 GENMASK(47, 32) +#define WRMEM1_100_FLD4 GENMASK(63, 48) +#define WRMEM1_100_FLD5 GENMASK(79, 64) +#define WRMEM1_100_FLD6 GENMASK(95, 80) +#define WRMEM1_100_FLD7 GENMASK(111, 96) +#define WRMEM1_100_FLD8 GENMASK(127, 112) + +/* WRMEM1_101 register fields */ +#define WRMEM1_101_FLD1 GENMASK(15, 0) +#define WRMEM1_101_FLD2 GENMASK(31, 16) +#define WRMEM1_101_FLD3 GENMASK(47, 32) +#define WRMEM1_101_FLD4 GENMASK(63, 48) +#define WRMEM1_101_FLD5 GENMASK(79, 64) +#define WRMEM1_101_FLD6 GENMASK(95, 80) +#define WRMEM1_101_FLD7 GENMASK(111, 96) +#define WRMEM1_101_FLD8 GENMASK(127, 112) + +/* WRMEM1_102 register fields */ +#define WRMEM1_102_FLD1 GENMASK(15, 0) +#define WRMEM1_102_FLD2 GENMASK(31, 16) +#define WRMEM1_102_FLD3 GENMASK(47, 32) +#define WRMEM1_102_FLD4 GENMASK(63, 48) +#define WRMEM1_102_FLD5 GENMASK(79, 64) +#define WRMEM1_102_FLD6 GENMASK(95, 80) +#define WRMEM1_102_FLD7 GENMASK(111, 96) +#define WRMEM1_102_FLD8 GENMASK(127, 112) + +/* WRMEM1_103 register fields */ +#define WRMEM1_103_FLD1 GENMASK(15, 0) +#define WRMEM1_103_FLD2 GENMASK(31, 16) +#define WRMEM1_103_FLD3 GENMASK(47, 32) +#define WRMEM1_103_FLD4 GENMASK(63, 48) +#define WRMEM1_103_FLD5 GENMASK(79, 64) +#define WRMEM1_103_FLD6 GENMASK(95, 80) +#define WRMEM1_103_FLD7 GENMASK(111, 96) +#define WRMEM1_103_FLD8 GENMASK(127, 112) + +/* WRMEM1_104 register fields */ +#define WRMEM1_104_FLD1 GENMASK(15, 0) +#define WRMEM1_104_FLD2 GENMASK(31, 16) +#define WRMEM1_104_FLD3 GENMASK(47, 32) +#define WRMEM1_104_FLD4 GENMASK(63, 48) +#define WRMEM1_104_FLD5 GENMASK(79, 64) +#define WRMEM1_104_FLD6 GENMASK(95, 80) +#define WRMEM1_104_FLD7 GENMASK(111, 96) +#define WRMEM1_104_FLD8 GENMASK(127, 112) + +/* WRMEM1_105 register fields */ +#define WRMEM1_105_FLD1 GENMASK(15, 0) +#define WRMEM1_105_FLD2 GENMASK(31, 16) +#define WRMEM1_105_FLD3 GENMASK(47, 32) +#define WRMEM1_105_FLD4 GENMASK(63, 48) +#define WRMEM1_105_FLD5 GENMASK(79, 64) +#define WRMEM1_105_FLD6 GENMASK(95, 80) +#define WRMEM1_105_FLD7 GENMASK(111, 96) +#define WRMEM1_105_FLD8 GENMASK(127, 112) + +/* WRMEM1_106 register fields */ +#define WRMEM1_106_FLD1 GENMASK(15, 0) +#define WRMEM1_106_FLD2 GENMASK(31, 16) +#define WRMEM1_106_FLD3 GENMASK(47, 32) +#define WRMEM1_106_FLD4 GENMASK(63, 48) +#define WRMEM1_106_FLD5 GENMASK(79, 64) +#define WRMEM1_106_FLD6 GENMASK(95, 80) +#define WRMEM1_106_FLD7 GENMASK(111, 96) +#define WRMEM1_106_FLD8 GENMASK(127, 112) + +/* WRMEM1_107 register fields */ +#define WRMEM1_107_FLD1 GENMASK(15, 0) +#define WRMEM1_107_FLD2 GENMASK(31, 16) +#define WRMEM1_107_FLD3 GENMASK(47, 32) +#define WRMEM1_107_FLD4 GENMASK(63, 48) +#define WRMEM1_107_FLD5 GENMASK(79, 64) +#define WRMEM1_107_FLD6 GENMASK(95, 80) +#define WRMEM1_107_FLD7 GENMASK(111, 96) +#define WRMEM1_107_FLD8 GENMASK(127, 112) + +/* WRMEM1_108 register fields */ +#define WRMEM1_108_FLD1 GENMASK(15, 0) +#define WRMEM1_108_FLD2 GENMASK(31, 16) +#define WRMEM1_108_FLD3 GENMASK(47, 32) +#define WRMEM1_108_FLD4 GENMASK(63, 48) +#define WRMEM1_108_FLD5 GENMASK(79, 64) +#define WRMEM1_108_FLD6 GENMASK(95, 80) +#define WRMEM1_108_FLD7 GENMASK(111, 96) +#define WRMEM1_108_FLD8 GENMASK(127, 112) + +/* WRMEM1_109 register fields */ +#define WRMEM1_109_FLD1 GENMASK(15, 0) +#define WRMEM1_109_FLD2 GENMASK(31, 16) +#define WRMEM1_109_FLD3 GENMASK(47, 32) +#define WRMEM1_109_FLD4 GENMASK(63, 48) +#define WRMEM1_109_FLD5 GENMASK(79, 64) +#define WRMEM1_109_FLD6 GENMASK(95, 80) +#define WRMEM1_109_FLD7 GENMASK(111, 96) +#define WRMEM1_109_FLD8 GENMASK(127, 112) + +/* WRMEM1_110 register fields */ +#define WRMEM1_110_FLD1 GENMASK(15, 0) +#define WRMEM1_110_FLD2 GENMASK(31, 16) +#define WRMEM1_110_FLD3 GENMASK(47, 32) +#define WRMEM1_110_FLD4 GENMASK(63, 48) +#define WRMEM1_110_FLD5 GENMASK(79, 64) +#define WRMEM1_110_FLD6 GENMASK(95, 80) +#define WRMEM1_110_FLD7 GENMASK(111, 96) +#define WRMEM1_110_FLD8 GENMASK(127, 112) + +/* WRMEM1_111 register fields */ +#define WRMEM1_111_FLD1 GENMASK(15, 0) +#define WRMEM1_111_FLD2 GENMASK(31, 16) +#define WRMEM1_111_FLD3 GENMASK(47, 32) +#define WRMEM1_111_FLD4 GENMASK(63, 48) +#define WRMEM1_111_FLD5 GENMASK(79, 64) +#define WRMEM1_111_FLD6 GENMASK(95, 80) +#define WRMEM1_111_FLD7 GENMASK(111, 96) +#define WRMEM1_111_FLD8 GENMASK(127, 112) + +/* WRMEM1_112 register fields */ +#define WRMEM1_112_FLD1 GENMASK(15, 0) +#define WRMEM1_112_FLD2 GENMASK(31, 16) +#define WRMEM1_112_FLD3 GENMASK(47, 32) +#define WRMEM1_112_FLD4 GENMASK(63, 48) +#define WRMEM1_112_FLD5 GENMASK(79, 64) +#define WRMEM1_112_FLD6 GENMASK(95, 80) +#define WRMEM1_112_FLD7 GENMASK(111, 96) +#define WRMEM1_112_FLD8 GENMASK(127, 112) + +/* WRMEM1_113 register fields */ +#define WRMEM1_113_FLD1 GENMASK(15, 0) +#define WRMEM1_113_FLD2 GENMASK(31, 16) +#define WRMEM1_113_FLD3 GENMASK(47, 32) +#define WRMEM1_113_FLD4 GENMASK(63, 48) +#define WRMEM1_113_FLD5 GENMASK(79, 64) +#define WRMEM1_113_FLD6 GENMASK(95, 80) +#define WRMEM1_113_FLD7 GENMASK(111, 96) +#define WRMEM1_113_FLD8 GENMASK(127, 112) + +/* WRMEM1_114 register fields */ +#define WRMEM1_114_FLD1 GENMASK(15, 0) +#define WRMEM1_114_FLD2 GENMASK(31, 16) +#define WRMEM1_114_FLD3 GENMASK(47, 32) +#define WRMEM1_114_FLD4 GENMASK(63, 48) +#define WRMEM1_114_FLD5 GENMASK(79, 64) +#define WRMEM1_114_FLD6 GENMASK(95, 80) +#define WRMEM1_114_FLD7 GENMASK(111, 96) +#define WRMEM1_114_FLD8 GENMASK(127, 112) + +/* WRMEM1_115 register fields */ +#define WRMEM1_115_FLD1 GENMASK(15, 0) +#define WRMEM1_115_FLD2 GENMASK(31, 16) +#define WRMEM1_115_FLD3 GENMASK(47, 32) +#define WRMEM1_115_FLD4 GENMASK(63, 48) +#define WRMEM1_115_FLD5 GENMASK(79, 64) +#define WRMEM1_115_FLD6 GENMASK(95, 80) +#define WRMEM1_115_FLD7 GENMASK(111, 96) +#define WRMEM1_115_FLD8 GENMASK(127, 112) + +/* WRMEM1_116 register fields */ +#define WRMEM1_116_FLD1 GENMASK(15, 0) +#define WRMEM1_116_FLD2 GENMASK(31, 16) +#define WRMEM1_116_FLD3 GENMASK(47, 32) +#define WRMEM1_116_FLD4 GENMASK(63, 48) +#define WRMEM1_116_FLD5 GENMASK(79, 64) +#define WRMEM1_116_FLD6 GENMASK(95, 80) +#define WRMEM1_116_FLD7 GENMASK(111, 96) +#define WRMEM1_116_FLD8 GENMASK(127, 112) + +/* WRMEM1_117 register fields */ +#define WRMEM1_117_FLD1 GENMASK(15, 0) +#define WRMEM1_117_FLD2 GENMASK(31, 16) +#define WRMEM1_117_FLD3 GENMASK(47, 32) +#define WRMEM1_117_FLD4 GENMASK(63, 48) +#define WRMEM1_117_FLD5 GENMASK(79, 64) +#define WRMEM1_117_FLD6 GENMASK(95, 80) +#define WRMEM1_117_FLD7 GENMASK(111, 96) +#define WRMEM1_117_FLD8 GENMASK(127, 112) + +/* WRMEM1_118 register fields */ +#define WRMEM1_118_FLD1 GENMASK(15, 0) +#define WRMEM1_118_FLD2 GENMASK(31, 16) +#define WRMEM1_118_FLD3 GENMASK(47, 32) +#define WRMEM1_118_FLD4 GENMASK(63, 48) +#define WRMEM1_118_FLD5 GENMASK(79, 64) +#define WRMEM1_118_FLD6 GENMASK(95, 80) +#define WRMEM1_118_FLD7 GENMASK(111, 96) +#define WRMEM1_118_FLD8 GENMASK(127, 112) + +/* WRMEM1_119 register fields */ +#define WRMEM1_119_FLD1 GENMASK(15, 0) +#define WRMEM1_119_FLD2 GENMASK(31, 16) +#define WRMEM1_119_FLD3 GENMASK(47, 32) +#define WRMEM1_119_FLD4 GENMASK(63, 48) +#define WRMEM1_119_FLD5 GENMASK(79, 64) +#define WRMEM1_119_FLD6 GENMASK(95, 80) +#define WRMEM1_119_FLD7 GENMASK(111, 96) +#define WRMEM1_119_FLD8 GENMASK(127, 112) + +/* WRMEM1_120 register fields */ +#define WRMEM1_120_FLD1 GENMASK(15, 0) +#define WRMEM1_120_FLD2 GENMASK(31, 16) +#define WRMEM1_120_FLD3 GENMASK(47, 32) +#define WRMEM1_120_FLD4 GENMASK(63, 48) +#define WRMEM1_120_FLD5 GENMASK(79, 64) +#define WRMEM1_120_FLD6 GENMASK(95, 80) +#define WRMEM1_120_FLD7 GENMASK(111, 96) +#define WRMEM1_120_FLD8 GENMASK(127, 112) + +/* WRMEM1_121 register fields */ +#define WRMEM1_121_FLD1 GENMASK(15, 0) +#define WRMEM1_121_FLD2 GENMASK(31, 16) +#define WRMEM1_121_FLD3 GENMASK(47, 32) +#define WRMEM1_121_FLD4 GENMASK(63, 48) +#define WRMEM1_121_FLD5 GENMASK(79, 64) +#define WRMEM1_121_FLD6 GENMASK(95, 80) +#define WRMEM1_121_FLD7 GENMASK(111, 96) +#define WRMEM1_121_FLD8 GENMASK(127, 112) + +/* WRMEM1_122 register fields */ +#define WRMEM1_122_FLD1 GENMASK(15, 0) +#define WRMEM1_122_FLD2 GENMASK(31, 16) +#define WRMEM1_122_FLD3 GENMASK(47, 32) +#define WRMEM1_122_FLD4 GENMASK(63, 48) +#define WRMEM1_122_FLD5 GENMASK(79, 64) +#define WRMEM1_122_FLD6 GENMASK(95, 80) +#define WRMEM1_122_FLD7 GENMASK(111, 96) +#define WRMEM1_122_FLD8 GENMASK(127, 112) + +/* WRMEM1_123 register fields */ +#define WRMEM1_123_FLD1 GENMASK(15, 0) +#define WRMEM1_123_FLD2 GENMASK(31, 16) +#define WRMEM1_123_FLD3 GENMASK(47, 32) +#define WRMEM1_123_FLD4 GENMASK(63, 48) +#define WRMEM1_123_FLD5 GENMASK(79, 64) +#define WRMEM1_123_FLD6 GENMASK(95, 80) +#define WRMEM1_123_FLD7 GENMASK(111, 96) +#define WRMEM1_123_FLD8 GENMASK(127, 112) + +/* WRMEM1_124 register fields */ +#define WRMEM1_124_FLD1 GENMASK(15, 0) +#define WRMEM1_124_FLD2 GENMASK(31, 16) +#define WRMEM1_124_FLD3 GENMASK(47, 32) +#define WRMEM1_124_FLD4 GENMASK(63, 48) +#define WRMEM1_124_FLD5 GENMASK(79, 64) +#define WRMEM1_124_FLD6 GENMASK(95, 80) +#define WRMEM1_124_FLD7 GENMASK(111, 96) +#define WRMEM1_124_FLD8 GENMASK(127, 112) + +/* WRMEM1_125 register fields */ +#define WRMEM1_125_FLD1 GENMASK(15, 0) +#define WRMEM1_125_FLD2 GENMASK(31, 16) +#define WRMEM1_125_FLD3 GENMASK(47, 32) +#define WRMEM1_125_FLD4 GENMASK(63, 48) +#define WRMEM1_125_FLD5 GENMASK(79, 64) +#define WRMEM1_125_FLD6 GENMASK(95, 80) +#define WRMEM1_125_FLD7 GENMASK(111, 96) +#define WRMEM1_125_FLD8 GENMASK(127, 112) + +/* WRMEM1_126 register fields */ +#define WRMEM1_126_FLD1 GENMASK(15, 0) +#define WRMEM1_126_FLD2 GENMASK(31, 16) +#define WRMEM1_126_FLD3 GENMASK(47, 32) +#define WRMEM1_126_FLD4 GENMASK(63, 48) +#define WRMEM1_126_FLD5 GENMASK(79, 64) +#define WRMEM1_126_FLD6 GENMASK(95, 80) +#define WRMEM1_126_FLD7 GENMASK(111, 96) +#define WRMEM1_126_FLD8 GENMASK(127, 112) + +/* WRMEM1_127 register fields */ +#define WRMEM1_127_FLD1 GENMASK(15, 0) +#define WRMEM1_127_FLD2 GENMASK(31, 16) +#define WRMEM1_127_FLD3 GENMASK(47, 32) +#define WRMEM1_127_FLD4 GENMASK(63, 48) +#define WRMEM1_127_FLD5 GENMASK(79, 64) +#define WRMEM1_127_FLD6 GENMASK(95, 80) +#define WRMEM1_127_FLD7 GENMASK(111, 96) +#define WRMEM1_127_FLD8 GENMASK(127, 112) + +/* WRMEM1_128 register fields */ +#define WRMEM1_128_FLD1 GENMASK(15, 0) +#define WRMEM1_128_FLD2 GENMASK(31, 16) +#define WRMEM1_128_FLD3 GENMASK(47, 32) +#define WRMEM1_128_FLD4 GENMASK(63, 48) +#define WRMEM1_128_FLD5 GENMASK(79, 64) +#define WRMEM1_128_FLD6 GENMASK(95, 80) +#define WRMEM1_128_FLD7 GENMASK(111, 96) +#define WRMEM1_128_FLD8 GENMASK(127, 112) + +/* WRMEM1_129 register fields */ +#define WRMEM1_129_FLD1 GENMASK(15, 0) +#define WRMEM1_129_FLD2 GENMASK(31, 16) +#define WRMEM1_129_FLD3 GENMASK(47, 32) +#define WRMEM1_129_FLD4 GENMASK(63, 48) +#define WRMEM1_129_FLD5 GENMASK(79, 64) +#define WRMEM1_129_FLD6 GENMASK(95, 80) +#define WRMEM1_129_FLD7 GENMASK(111, 96) +#define WRMEM1_129_FLD8 GENMASK(127, 112) + +/* WRMEM1_130 register fields */ +#define WRMEM1_130_FLD1 GENMASK(15, 0) +#define WRMEM1_130_FLD2 GENMASK(31, 16) +#define WRMEM1_130_FLD3 GENMASK(47, 32) +#define WRMEM1_130_FLD4 GENMASK(63, 48) +#define WRMEM1_130_FLD5 GENMASK(79, 64) +#define WRMEM1_130_FLD6 GENMASK(95, 80) +#define WRMEM1_130_FLD7 GENMASK(111, 96) +#define WRMEM1_130_FLD8 GENMASK(127, 112) + +/* WRMEM1_131 register fields */ +#define WRMEM1_131_FLD1 GENMASK(15, 0) +#define WRMEM1_131_FLD2 GENMASK(31, 16) +#define WRMEM1_131_FLD3 GENMASK(47, 32) +#define WRMEM1_131_FLD4 GENMASK(63, 48) +#define WRMEM1_131_FLD5 GENMASK(79, 64) +#define WRMEM1_131_FLD6 GENMASK(95, 80) +#define WRMEM1_131_FLD7 GENMASK(111, 96) +#define WRMEM1_131_FLD8 GENMASK(127, 112) + +/* WRMEM1_132 register fields */ +#define WRMEM1_132_FLD1 GENMASK(15, 0) +#define WRMEM1_132_FLD2 GENMASK(31, 16) +#define WRMEM1_132_FLD3 GENMASK(47, 32) +#define WRMEM1_132_FLD4 GENMASK(63, 48) +#define WRMEM1_132_FLD5 GENMASK(79, 64) +#define WRMEM1_132_FLD6 GENMASK(95, 80) +#define WRMEM1_132_FLD7 GENMASK(111, 96) +#define WRMEM1_132_FLD8 GENMASK(127, 112) + +/* WRMEM1_133 register fields */ +#define WRMEM1_133_FLD1 GENMASK(15, 0) +#define WRMEM1_133_FLD2 GENMASK(31, 16) +#define WRMEM1_133_FLD3 GENMASK(47, 32) +#define WRMEM1_133_FLD4 GENMASK(63, 48) +#define WRMEM1_133_FLD5 GENMASK(79, 64) +#define WRMEM1_133_FLD6 GENMASK(95, 80) +#define WRMEM1_133_FLD7 GENMASK(111, 96) +#define WRMEM1_133_FLD8 GENMASK(127, 112) + +/* WRMEM1_134 register fields */ +#define WRMEM1_134_FLD1 GENMASK(15, 0) +#define WRMEM1_134_FLD2 GENMASK(31, 16) +#define WRMEM1_134_FLD3 GENMASK(47, 32) +#define WRMEM1_134_FLD4 GENMASK(63, 48) +#define WRMEM1_134_FLD5 GENMASK(79, 64) +#define WRMEM1_134_FLD6 GENMASK(95, 80) +#define WRMEM1_134_FLD7 GENMASK(111, 96) +#define WRMEM1_134_FLD8 GENMASK(127, 112) + +/* WRMEM1_135 register fields */ +#define WRMEM1_135_FLD1 GENMASK(15, 0) +#define WRMEM1_135_FLD2 GENMASK(31, 16) +#define WRMEM1_135_FLD3 GENMASK(47, 32) +#define WRMEM1_135_FLD4 GENMASK(63, 48) +#define WRMEM1_135_FLD5 GENMASK(79, 64) +#define WRMEM1_135_FLD6 GENMASK(95, 80) +#define WRMEM1_135_FLD7 GENMASK(111, 96) +#define WRMEM1_135_FLD8 GENMASK(127, 112) + +/* WRMEM1_136 register fields */ +#define WRMEM1_136_FLD1 GENMASK(15, 0) +#define WRMEM1_136_FLD2 GENMASK(31, 16) +#define WRMEM1_136_FLD3 GENMASK(47, 32) +#define WRMEM1_136_FLD4 GENMASK(63, 48) +#define WRMEM1_136_FLD5 GENMASK(79, 64) +#define WRMEM1_136_FLD6 GENMASK(95, 80) +#define WRMEM1_136_FLD7 GENMASK(111, 96) +#define WRMEM1_136_FLD8 GENMASK(127, 112) + +/* WRMEM1_137 register fields */ +#define WRMEM1_137_FLD1 GENMASK(15, 0) +#define WRMEM1_137_FLD2 GENMASK(31, 16) +#define WRMEM1_137_FLD3 GENMASK(47, 32) +#define WRMEM1_137_FLD4 GENMASK(63, 48) +#define WRMEM1_137_FLD5 GENMASK(79, 64) +#define WRMEM1_137_FLD6 GENMASK(95, 80) +#define WRMEM1_137_FLD7 GENMASK(111, 96) +#define WRMEM1_137_FLD8 GENMASK(127, 112) + +/* WRMEM1_138 register fields */ +#define WRMEM1_138_FLD1 GENMASK(15, 0) +#define WRMEM1_138_FLD2 GENMASK(31, 16) +#define WRMEM1_138_FLD3 GENMASK(47, 32) +#define WRMEM1_138_FLD4 GENMASK(63, 48) +#define WRMEM1_138_FLD5 GENMASK(79, 64) +#define WRMEM1_138_FLD6 GENMASK(95, 80) +#define WRMEM1_138_FLD7 GENMASK(111, 96) +#define WRMEM1_138_FLD8 GENMASK(127, 112) + +/* WRMEM1_139 register fields */ +#define WRMEM1_139_FLD1 GENMASK(15, 0) +#define WRMEM1_139_FLD2 GENMASK(31, 16) +#define WRMEM1_139_FLD3 GENMASK(47, 32) +#define WRMEM1_139_FLD4 GENMASK(63, 48) +#define WRMEM1_139_FLD5 GENMASK(79, 64) +#define WRMEM1_139_FLD6 GENMASK(95, 80) +#define WRMEM1_139_FLD7 GENMASK(111, 96) +#define WRMEM1_139_FLD8 GENMASK(127, 112) + +/* WRMEM1_140 register fields */ +#define WRMEM1_140_FLD1 GENMASK(15, 0) +#define WRMEM1_140_FLD2 GENMASK(31, 16) +#define WRMEM1_140_FLD3 GENMASK(47, 32) +#define WRMEM1_140_FLD4 GENMASK(63, 48) +#define WRMEM1_140_FLD5 GENMASK(79, 64) +#define WRMEM1_140_FLD6 GENMASK(95, 80) +#define WRMEM1_140_FLD7 GENMASK(111, 96) +#define WRMEM1_140_FLD8 GENMASK(127, 112) + +/* WRMEM1_141 register fields */ +#define WRMEM1_141_FLD1 GENMASK(15, 0) +#define WRMEM1_141_FLD2 GENMASK(31, 16) +#define WRMEM1_141_FLD3 GENMASK(47, 32) +#define WRMEM1_141_FLD4 GENMASK(63, 48) +#define WRMEM1_141_FLD5 GENMASK(79, 64) +#define WRMEM1_141_FLD6 GENMASK(95, 80) +#define WRMEM1_141_FLD7 GENMASK(111, 96) +#define WRMEM1_141_FLD8 GENMASK(127, 112) + +/* WRMEM1_142 register fields */ +#define WRMEM1_142_FLD1 GENMASK(15, 0) +#define WRMEM1_142_FLD2 GENMASK(31, 16) +#define WRMEM1_142_FLD3 GENMASK(47, 32) +#define WRMEM1_142_FLD4 GENMASK(63, 48) +#define WRMEM1_142_FLD5 GENMASK(79, 64) +#define WRMEM1_142_FLD6 GENMASK(95, 80) +#define WRMEM1_142_FLD7 GENMASK(111, 96) +#define WRMEM1_142_FLD8 GENMASK(127, 112) + +/* WRMEM1_143 register fields */ +#define WRMEM1_143_FLD1 GENMASK(15, 0) +#define WRMEM1_143_FLD2 GENMASK(31, 16) +#define WRMEM1_143_FLD3 GENMASK(47, 32) +#define WRMEM1_143_FLD4 GENMASK(63, 48) +#define WRMEM1_143_FLD5 GENMASK(79, 64) +#define WRMEM1_143_FLD6 GENMASK(95, 80) +#define WRMEM1_143_FLD7 GENMASK(111, 96) +#define WRMEM1_143_FLD8 GENMASK(127, 112) + +/* WRMEM1_144 register fields */ +#define WRMEM1_144_FLD1 GENMASK(15, 0) +#define WRMEM1_144_FLD2 GENMASK(31, 16) +#define WRMEM1_144_FLD3 GENMASK(47, 32) +#define WRMEM1_144_FLD4 GENMASK(63, 48) +#define WRMEM1_144_FLD5 GENMASK(79, 64) +#define WRMEM1_144_FLD6 GENMASK(95, 80) +#define WRMEM1_144_FLD7 GENMASK(111, 96) +#define WRMEM1_144_FLD8 GENMASK(127, 112) + +/* WRMEM1_145 register fields */ +#define WRMEM1_145_FLD1 GENMASK(15, 0) +#define WRMEM1_145_FLD2 GENMASK(31, 16) +#define WRMEM1_145_FLD3 GENMASK(47, 32) +#define WRMEM1_145_FLD4 GENMASK(63, 48) +#define WRMEM1_145_FLD5 GENMASK(79, 64) +#define WRMEM1_145_FLD6 GENMASK(95, 80) +#define WRMEM1_145_FLD7 GENMASK(111, 96) +#define WRMEM1_145_FLD8 GENMASK(127, 112) + +/* WRMEM1_146 register fields */ +#define WRMEM1_146_FLD1 GENMASK(15, 0) +#define WRMEM1_146_FLD2 GENMASK(31, 16) +#define WRMEM1_146_FLD3 GENMASK(47, 32) +#define WRMEM1_146_FLD4 GENMASK(63, 48) +#define WRMEM1_146_FLD5 GENMASK(79, 64) +#define WRMEM1_146_FLD6 GENMASK(95, 80) +#define WRMEM1_146_FLD7 GENMASK(111, 96) +#define WRMEM1_146_FLD8 GENMASK(127, 112) + +/* WRMEM1_147 register fields */ +#define WRMEM1_147_FLD1 GENMASK(15, 0) +#define WRMEM1_147_FLD2 GENMASK(31, 16) +#define WRMEM1_147_FLD3 GENMASK(47, 32) +#define WRMEM1_147_FLD4 GENMASK(63, 48) +#define WRMEM1_147_FLD5 GENMASK(79, 64) +#define WRMEM1_147_FLD6 GENMASK(95, 80) +#define WRMEM1_147_FLD7 GENMASK(111, 96) +#define WRMEM1_147_FLD8 GENMASK(127, 112) + +/* WRMEM1_148 register fields */ +#define WRMEM1_148_FLD1 GENMASK(15, 0) +#define WRMEM1_148_FLD2 GENMASK(31, 16) +#define WRMEM1_148_FLD3 GENMASK(47, 32) +#define WRMEM1_148_FLD4 GENMASK(63, 48) +#define WRMEM1_148_FLD5 GENMASK(79, 64) +#define WRMEM1_148_FLD6 GENMASK(95, 80) +#define WRMEM1_148_FLD7 GENMASK(111, 96) +#define WRMEM1_148_FLD8 GENMASK(127, 112) + +/* WRMEM1_149 register fields */ +#define WRMEM1_149_FLD1 GENMASK(15, 0) +#define WRMEM1_149_FLD2 GENMASK(31, 16) +#define WRMEM1_149_FLD3 GENMASK(47, 32) +#define WRMEM1_149_FLD4 GENMASK(63, 48) +#define WRMEM1_149_FLD5 GENMASK(79, 64) +#define WRMEM1_149_FLD6 GENMASK(95, 80) +#define WRMEM1_149_FLD7 GENMASK(111, 96) +#define WRMEM1_149_FLD8 GENMASK(127, 112) + +/* WRMEM1_150 register fields */ +#define WRMEM1_150_FLD1 GENMASK(15, 0) +#define WRMEM1_150_FLD2 GENMASK(31, 16) +#define WRMEM1_150_FLD3 GENMASK(47, 32) +#define WRMEM1_150_FLD4 GENMASK(63, 48) +#define WRMEM1_150_FLD5 GENMASK(79, 64) +#define WRMEM1_150_FLD6 GENMASK(95, 80) +#define WRMEM1_150_FLD7 GENMASK(111, 96) +#define WRMEM1_150_FLD8 GENMASK(127, 112) + +/* WRMEM1_151 register fields */ +#define WRMEM1_151_FLD1 GENMASK(15, 0) +#define WRMEM1_151_FLD2 GENMASK(31, 16) +#define WRMEM1_151_FLD3 GENMASK(47, 32) +#define WRMEM1_151_FLD4 GENMASK(63, 48) +#define WRMEM1_151_FLD5 GENMASK(79, 64) +#define WRMEM1_151_FLD6 GENMASK(95, 80) +#define WRMEM1_151_FLD7 GENMASK(111, 96) +#define WRMEM1_151_FLD8 GENMASK(127, 112) + +/* WRMEM1_152 register fields */ +#define WRMEM1_152_FLD1 GENMASK(15, 0) +#define WRMEM1_152_FLD2 GENMASK(31, 16) +#define WRMEM1_152_FLD3 GENMASK(47, 32) +#define WRMEM1_152_FLD4 GENMASK(63, 48) +#define WRMEM1_152_FLD5 GENMASK(79, 64) +#define WRMEM1_152_FLD6 GENMASK(95, 80) +#define WRMEM1_152_FLD7 GENMASK(111, 96) +#define WRMEM1_152_FLD8 GENMASK(127, 112) + +/* WRMEM1_153 register fields */ +#define WRMEM1_153_FLD1 GENMASK(15, 0) +#define WRMEM1_153_FLD2 GENMASK(31, 16) +#define WRMEM1_153_FLD3 GENMASK(47, 32) +#define WRMEM1_153_FLD4 GENMASK(63, 48) +#define WRMEM1_153_FLD5 GENMASK(79, 64) +#define WRMEM1_153_FLD6 GENMASK(95, 80) +#define WRMEM1_153_FLD7 GENMASK(111, 96) +#define WRMEM1_153_FLD8 GENMASK(127, 112) + +/* WRMEM1_154 register fields */ +#define WRMEM1_154_FLD1 GENMASK(15, 0) +#define WRMEM1_154_FLD2 GENMASK(31, 16) +#define WRMEM1_154_FLD3 GENMASK(47, 32) +#define WRMEM1_154_FLD4 GENMASK(63, 48) +#define WRMEM1_154_FLD5 GENMASK(79, 64) +#define WRMEM1_154_FLD6 GENMASK(95, 80) +#define WRMEM1_154_FLD7 GENMASK(111, 96) +#define WRMEM1_154_FLD8 GENMASK(127, 112) + +/* WRMEM1_155 register fields */ +#define WRMEM1_155_FLD1 GENMASK(15, 0) +#define WRMEM1_155_FLD2 GENMASK(31, 16) +#define WRMEM1_155_FLD3 GENMASK(47, 32) +#define WRMEM1_155_FLD4 GENMASK(63, 48) +#define WRMEM1_155_FLD5 GENMASK(79, 64) +#define WRMEM1_155_FLD6 GENMASK(95, 80) +#define WRMEM1_155_FLD7 GENMASK(111, 96) +#define WRMEM1_155_FLD8 GENMASK(127, 112) + +/* WRMEM1_156 register fields */ +#define WRMEM1_156_FLD1 GENMASK(15, 0) +#define WRMEM1_156_FLD2 GENMASK(31, 16) +#define WRMEM1_156_FLD3 GENMASK(47, 32) +#define WRMEM1_156_FLD4 GENMASK(63, 48) +#define WRMEM1_156_FLD5 GENMASK(79, 64) +#define WRMEM1_156_FLD6 GENMASK(95, 80) +#define WRMEM1_156_FLD7 GENMASK(111, 96) +#define WRMEM1_156_FLD8 GENMASK(127, 112) + +/* WRMEM1_157 register fields */ +#define WRMEM1_157_FLD1 GENMASK(15, 0) +#define WRMEM1_157_FLD2 GENMASK(31, 16) +#define WRMEM1_157_FLD3 GENMASK(47, 32) +#define WRMEM1_157_FLD4 GENMASK(63, 48) +#define WRMEM1_157_FLD5 GENMASK(79, 64) +#define WRMEM1_157_FLD6 GENMASK(95, 80) +#define WRMEM1_157_FLD7 GENMASK(111, 96) +#define WRMEM1_157_FLD8 GENMASK(127, 112) + +/* WRMEM1_158 register fields */ +#define WRMEM1_158_FLD1 GENMASK(15, 0) +#define WRMEM1_158_FLD2 GENMASK(31, 16) +#define WRMEM1_158_FLD3 GENMASK(47, 32) +#define WRMEM1_158_FLD4 GENMASK(63, 48) +#define WRMEM1_158_FLD5 GENMASK(79, 64) +#define WRMEM1_158_FLD6 GENMASK(95, 80) +#define WRMEM1_158_FLD7 GENMASK(111, 96) +#define WRMEM1_158_FLD8 GENMASK(127, 112) + +/* WRMEM1_159 register fields */ +#define WRMEM1_159_FLD1 GENMASK(15, 0) +#define WRMEM1_159_FLD2 GENMASK(31, 16) +#define WRMEM1_159_FLD3 GENMASK(47, 32) +#define WRMEM1_159_FLD4 GENMASK(63, 48) +#define WRMEM1_159_FLD5 GENMASK(79, 64) +#define WRMEM1_159_FLD6 GENMASK(95, 80) +#define WRMEM1_159_FLD7 GENMASK(111, 96) +#define WRMEM1_159_FLD8 GENMASK(127, 112) + +/* WRMEM1_160 register fields */ +#define WRMEM1_160_FLD1 GENMASK(15, 0) +#define WRMEM1_160_FLD2 GENMASK(31, 16) +#define WRMEM1_160_FLD3 GENMASK(47, 32) +#define WRMEM1_160_FLD4 GENMASK(63, 48) +#define WRMEM1_160_FLD5 GENMASK(79, 64) +#define WRMEM1_160_FLD6 GENMASK(95, 80) +#define WRMEM1_160_FLD7 GENMASK(111, 96) +#define WRMEM1_160_FLD8 GENMASK(127, 112) + +/* WRMEM1_161 register fields */ +#define WRMEM1_161_FLD1 GENMASK(15, 0) +#define WRMEM1_161_FLD2 GENMASK(31, 16) +#define WRMEM1_161_FLD3 GENMASK(47, 32) +#define WRMEM1_161_FLD4 GENMASK(63, 48) +#define WRMEM1_161_FLD5 GENMASK(79, 64) +#define WRMEM1_161_FLD6 GENMASK(95, 80) +#define WRMEM1_161_FLD7 GENMASK(111, 96) +#define WRMEM1_161_FLD8 GENMASK(127, 112) + +/* WRMEM1_162 register fields */ +#define WRMEM1_162_FLD1 GENMASK(15, 0) +#define WRMEM1_162_FLD2 GENMASK(31, 16) +#define WRMEM1_162_FLD3 GENMASK(47, 32) +#define WRMEM1_162_FLD4 GENMASK(63, 48) +#define WRMEM1_162_FLD5 GENMASK(79, 64) +#define WRMEM1_162_FLD6 GENMASK(95, 80) +#define WRMEM1_162_FLD7 GENMASK(111, 96) +#define WRMEM1_162_FLD8 GENMASK(127, 112) + +/* WRMEM1_163 register fields */ +#define WRMEM1_163_FLD1 GENMASK(15, 0) +#define WRMEM1_163_FLD2 GENMASK(31, 16) +#define WRMEM1_163_FLD3 GENMASK(47, 32) +#define WRMEM1_163_FLD4 GENMASK(63, 48) +#define WRMEM1_163_FLD5 GENMASK(79, 64) +#define WRMEM1_163_FLD6 GENMASK(95, 80) +#define WRMEM1_163_FLD7 GENMASK(111, 96) +#define WRMEM1_163_FLD8 GENMASK(127, 112) + +/* WRMEM1_164 register fields */ +#define WRMEM1_164_FLD1 GENMASK(15, 0) +#define WRMEM1_164_FLD2 GENMASK(31, 16) +#define WRMEM1_164_FLD3 GENMASK(47, 32) +#define WRMEM1_164_FLD4 GENMASK(63, 48) +#define WRMEM1_164_FLD5 GENMASK(79, 64) +#define WRMEM1_164_FLD6 GENMASK(95, 80) +#define WRMEM1_164_FLD7 GENMASK(111, 96) +#define WRMEM1_164_FLD8 GENMASK(127, 112) + +/* WRMEM1_165 register fields */ +#define WRMEM1_165_FLD1 GENMASK(15, 0) +#define WRMEM1_165_FLD2 GENMASK(31, 16) +#define WRMEM1_165_FLD3 GENMASK(47, 32) +#define WRMEM1_165_FLD4 GENMASK(63, 48) +#define WRMEM1_165_FLD5 GENMASK(79, 64) +#define WRMEM1_165_FLD6 GENMASK(95, 80) +#define WRMEM1_165_FLD7 GENMASK(111, 96) +#define WRMEM1_165_FLD8 GENMASK(127, 112) + +/* WRMEM1_166 register fields */ +#define WRMEM1_166_FLD1 GENMASK(15, 0) +#define WRMEM1_166_FLD2 GENMASK(31, 16) +#define WRMEM1_166_FLD3 GENMASK(47, 32) +#define WRMEM1_166_FLD4 GENMASK(63, 48) +#define WRMEM1_166_FLD5 GENMASK(79, 64) +#define WRMEM1_166_FLD6 GENMASK(95, 80) +#define WRMEM1_166_FLD7 GENMASK(111, 96) +#define WRMEM1_166_FLD8 GENMASK(127, 112) + +/* WRMEM1_167 register fields */ +#define WRMEM1_167_FLD1 GENMASK(15, 0) +#define WRMEM1_167_FLD2 GENMASK(31, 16) +#define WRMEM1_167_FLD3 GENMASK(47, 32) +#define WRMEM1_167_FLD4 GENMASK(63, 48) +#define WRMEM1_167_FLD5 GENMASK(79, 64) +#define WRMEM1_167_FLD6 GENMASK(95, 80) +#define WRMEM1_167_FLD7 GENMASK(111, 96) +#define WRMEM1_167_FLD8 GENMASK(127, 112) + +/* WRMEM1_168 register fields */ +#define WRMEM1_168_FLD1 GENMASK(15, 0) +#define WRMEM1_168_FLD2 GENMASK(31, 16) +#define WRMEM1_168_FLD3 GENMASK(47, 32) +#define WRMEM1_168_FLD4 GENMASK(63, 48) +#define WRMEM1_168_FLD5 GENMASK(79, 64) +#define WRMEM1_168_FLD6 GENMASK(95, 80) +#define WRMEM1_168_FLD7 GENMASK(111, 96) +#define WRMEM1_168_FLD8 GENMASK(127, 112) + +/* WRMEM1_169 register fields */ +#define WRMEM1_169_FLD1 GENMASK(15, 0) +#define WRMEM1_169_FLD2 GENMASK(31, 16) +#define WRMEM1_169_FLD3 GENMASK(47, 32) +#define WRMEM1_169_FLD4 GENMASK(63, 48) +#define WRMEM1_169_FLD5 GENMASK(79, 64) +#define WRMEM1_169_FLD6 GENMASK(95, 80) +#define WRMEM1_169_FLD7 GENMASK(111, 96) +#define WRMEM1_169_FLD8 GENMASK(127, 112) + +/* WRMEM1_170 register fields */ +#define WRMEM1_170_FLD1 GENMASK(15, 0) +#define WRMEM1_170_FLD2 GENMASK(31, 16) +#define WRMEM1_170_FLD3 GENMASK(47, 32) +#define WRMEM1_170_FLD4 GENMASK(63, 48) +#define WRMEM1_170_FLD5 GENMASK(79, 64) +#define WRMEM1_170_FLD6 GENMASK(95, 80) +#define WRMEM1_170_FLD7 GENMASK(111, 96) +#define WRMEM1_170_FLD8 GENMASK(127, 112) + +/* WRMEM1_171 register fields */ +#define WRMEM1_171_FLD1 GENMASK(15, 0) +#define WRMEM1_171_FLD2 GENMASK(31, 16) +#define WRMEM1_171_FLD3 GENMASK(47, 32) +#define WRMEM1_171_FLD4 GENMASK(63, 48) +#define WRMEM1_171_FLD5 GENMASK(79, 64) +#define WRMEM1_171_FLD6 GENMASK(95, 80) +#define WRMEM1_171_FLD7 GENMASK(111, 96) +#define WRMEM1_171_FLD8 GENMASK(127, 112) + +/* WRMEM1_172 register fields */ +#define WRMEM1_172_FLD1 GENMASK(15, 0) +#define WRMEM1_172_FLD2 GENMASK(31, 16) +#define WRMEM1_172_FLD3 GENMASK(47, 32) +#define WRMEM1_172_FLD4 GENMASK(63, 48) +#define WRMEM1_172_FLD5 GENMASK(79, 64) +#define WRMEM1_172_FLD6 GENMASK(95, 80) +#define WRMEM1_172_FLD7 GENMASK(111, 96) +#define WRMEM1_172_FLD8 GENMASK(127, 112) + +/* WRMEM1_173 register fields */ +#define WRMEM1_173_FLD1 GENMASK(15, 0) +#define WRMEM1_173_FLD2 GENMASK(31, 16) +#define WRMEM1_173_FLD3 GENMASK(47, 32) +#define WRMEM1_173_FLD4 GENMASK(63, 48) +#define WRMEM1_173_FLD5 GENMASK(79, 64) +#define WRMEM1_173_FLD6 GENMASK(95, 80) +#define WRMEM1_173_FLD7 GENMASK(111, 96) +#define WRMEM1_173_FLD8 GENMASK(127, 112) + +/* WRMEM1_174 register fields */ +#define WRMEM1_174_FLD1 GENMASK(15, 0) +#define WRMEM1_174_FLD2 GENMASK(31, 16) +#define WRMEM1_174_FLD3 GENMASK(47, 32) +#define WRMEM1_174_FLD4 GENMASK(63, 48) +#define WRMEM1_174_FLD5 GENMASK(79, 64) +#define WRMEM1_174_FLD6 GENMASK(95, 80) +#define WRMEM1_174_FLD7 GENMASK(111, 96) +#define WRMEM1_174_FLD8 GENMASK(127, 112) + +/* WRMEM1_175 register fields */ +#define WRMEM1_175_FLD1 GENMASK(15, 0) +#define WRMEM1_175_FLD2 GENMASK(31, 16) +#define WRMEM1_175_FLD3 GENMASK(47, 32) +#define WRMEM1_175_FLD4 GENMASK(63, 48) +#define WRMEM1_175_FLD5 GENMASK(79, 64) +#define WRMEM1_175_FLD6 GENMASK(95, 80) +#define WRMEM1_175_FLD7 GENMASK(111, 96) +#define WRMEM1_175_FLD8 GENMASK(127, 112) + +/* WRMEM1_176 register fields */ +#define WRMEM1_176_FLD1 GENMASK(15, 0) +#define WRMEM1_176_FLD2 GENMASK(31, 16) +#define WRMEM1_176_FLD3 GENMASK(47, 32) +#define WRMEM1_176_FLD4 GENMASK(63, 48) +#define WRMEM1_176_FLD5 GENMASK(79, 64) +#define WRMEM1_176_FLD6 GENMASK(95, 80) +#define WRMEM1_176_FLD7 GENMASK(111, 96) +#define WRMEM1_176_FLD8 GENMASK(127, 112) + +/* WRMEM1_177 register fields */ +#define WRMEM1_177_FLD1 GENMASK(15, 0) +#define WRMEM1_177_FLD2 GENMASK(31, 16) +#define WRMEM1_177_FLD3 GENMASK(47, 32) +#define WRMEM1_177_FLD4 GENMASK(63, 48) +#define WRMEM1_177_FLD5 GENMASK(79, 64) +#define WRMEM1_177_FLD6 GENMASK(95, 80) +#define WRMEM1_177_FLD7 GENMASK(111, 96) +#define WRMEM1_177_FLD8 GENMASK(127, 112) + +/* WRMEM1_178 register fields */ +#define WRMEM1_178_FLD1 GENMASK(15, 0) +#define WRMEM1_178_FLD2 GENMASK(31, 16) +#define WRMEM1_178_FLD3 GENMASK(47, 32) +#define WRMEM1_178_FLD4 GENMASK(63, 48) +#define WRMEM1_178_FLD5 GENMASK(79, 64) +#define WRMEM1_178_FLD6 GENMASK(95, 80) +#define WRMEM1_178_FLD7 GENMASK(111, 96) +#define WRMEM1_178_FLD8 GENMASK(127, 112) + +/* WRMEM1_179 register fields */ +#define WRMEM1_179_FLD1 GENMASK(15, 0) +#define WRMEM1_179_FLD2 GENMASK(31, 16) +#define WRMEM1_179_FLD3 GENMASK(47, 32) +#define WRMEM1_179_FLD4 GENMASK(63, 48) +#define WRMEM1_179_FLD5 GENMASK(79, 64) +#define WRMEM1_179_FLD6 GENMASK(95, 80) +#define WRMEM1_179_FLD7 GENMASK(111, 96) +#define WRMEM1_179_FLD8 GENMASK(127, 112) + +/* WRMEM1_180 register fields */ +#define WRMEM1_180_FLD1 GENMASK(15, 0) +#define WRMEM1_180_FLD2 GENMASK(31, 16) +#define WRMEM1_180_FLD3 GENMASK(47, 32) +#define WRMEM1_180_FLD4 GENMASK(63, 48) +#define WRMEM1_180_FLD5 GENMASK(79, 64) +#define WRMEM1_180_FLD6 GENMASK(95, 80) +#define WRMEM1_180_FLD7 GENMASK(111, 96) +#define WRMEM1_180_FLD8 GENMASK(127, 112) + +/* WRMEM1_181 register fields */ +#define WRMEM1_181_FLD1 GENMASK(15, 0) +#define WRMEM1_181_FLD2 GENMASK(31, 16) +#define WRMEM1_181_FLD3 GENMASK(47, 32) +#define WRMEM1_181_FLD4 GENMASK(63, 48) +#define WRMEM1_181_FLD5 GENMASK(79, 64) +#define WRMEM1_181_FLD6 GENMASK(95, 80) +#define WRMEM1_181_FLD7 GENMASK(111, 96) +#define WRMEM1_181_FLD8 GENMASK(127, 112) + +/* WRMEM1_182 register fields */ +#define WRMEM1_182_FLD1 GENMASK(15, 0) +#define WRMEM1_182_FLD2 GENMASK(31, 16) +#define WRMEM1_182_FLD3 GENMASK(47, 32) +#define WRMEM1_182_FLD4 GENMASK(63, 48) +#define WRMEM1_182_FLD5 GENMASK(79, 64) +#define WRMEM1_182_FLD6 GENMASK(95, 80) +#define WRMEM1_182_FLD7 GENMASK(111, 96) +#define WRMEM1_182_FLD8 GENMASK(127, 112) + +/* WRMEM1_183 register fields */ +#define WRMEM1_183_FLD1 GENMASK(15, 0) +#define WRMEM1_183_FLD2 GENMASK(31, 16) +#define WRMEM1_183_FLD3 GENMASK(47, 32) +#define WRMEM1_183_FLD4 GENMASK(63, 48) +#define WRMEM1_183_FLD5 GENMASK(79, 64) +#define WRMEM1_183_FLD6 GENMASK(95, 80) +#define WRMEM1_183_FLD7 GENMASK(111, 96) +#define WRMEM1_183_FLD8 GENMASK(127, 112) + +/* WRMEM1_184 register fields */ +#define WRMEM1_184_FLD1 GENMASK(15, 0) +#define WRMEM1_184_FLD2 GENMASK(31, 16) +#define WRMEM1_184_FLD3 GENMASK(47, 32) +#define WRMEM1_184_FLD4 GENMASK(63, 48) +#define WRMEM1_184_FLD5 GENMASK(79, 64) +#define WRMEM1_184_FLD6 GENMASK(95, 80) +#define WRMEM1_184_FLD7 GENMASK(111, 96) +#define WRMEM1_184_FLD8 GENMASK(127, 112) + +/* WRMEM1_185 register fields */ +#define WRMEM1_185_FLD1 GENMASK(15, 0) +#define WRMEM1_185_FLD2 GENMASK(31, 16) +#define WRMEM1_185_FLD3 GENMASK(47, 32) +#define WRMEM1_185_FLD4 GENMASK(63, 48) +#define WRMEM1_185_FLD5 GENMASK(79, 64) +#define WRMEM1_185_FLD6 GENMASK(95, 80) +#define WRMEM1_185_FLD7 GENMASK(111, 96) +#define WRMEM1_185_FLD8 GENMASK(127, 112) + +/* WRMEM1_186 register fields */ +#define WRMEM1_186_FLD1 GENMASK(15, 0) +#define WRMEM1_186_FLD2 GENMASK(31, 16) +#define WRMEM1_186_FLD3 GENMASK(47, 32) +#define WRMEM1_186_FLD4 GENMASK(63, 48) +#define WRMEM1_186_FLD5 GENMASK(79, 64) +#define WRMEM1_186_FLD6 GENMASK(95, 80) +#define WRMEM1_186_FLD7 GENMASK(111, 96) +#define WRMEM1_186_FLD8 GENMASK(127, 112) + +/* WRMEM1_187 register fields */ +#define WRMEM1_187_FLD1 GENMASK(15, 0) +#define WRMEM1_187_FLD2 GENMASK(31, 16) +#define WRMEM1_187_FLD3 GENMASK(47, 32) +#define WRMEM1_187_FLD4 GENMASK(63, 48) +#define WRMEM1_187_FLD5 GENMASK(79, 64) +#define WRMEM1_187_FLD6 GENMASK(95, 80) +#define WRMEM1_187_FLD7 GENMASK(111, 96) +#define WRMEM1_187_FLD8 GENMASK(127, 112) + +/* WRMEM1_188 register fields */ +#define WRMEM1_188_FLD1 GENMASK(15, 0) +#define WRMEM1_188_FLD2 GENMASK(31, 16) +#define WRMEM1_188_FLD3 GENMASK(47, 32) +#define WRMEM1_188_FLD4 GENMASK(63, 48) +#define WRMEM1_188_FLD5 GENMASK(79, 64) +#define WRMEM1_188_FLD6 GENMASK(95, 80) +#define WRMEM1_188_FLD7 GENMASK(111, 96) +#define WRMEM1_188_FLD8 GENMASK(127, 112) + +/* WRMEM1_189 register fields */ +#define WRMEM1_189_FLD1 GENMASK(15, 0) +#define WRMEM1_189_FLD2 GENMASK(31, 16) +#define WRMEM1_189_FLD3 GENMASK(47, 32) +#define WRMEM1_189_FLD4 GENMASK(63, 48) +#define WRMEM1_189_FLD5 GENMASK(79, 64) +#define WRMEM1_189_FLD6 GENMASK(95, 80) +#define WRMEM1_189_FLD7 GENMASK(111, 96) +#define WRMEM1_189_FLD8 GENMASK(127, 112) + +/* WRMEM1_190 register fields */ +#define WRMEM1_190_FLD1 GENMASK(15, 0) +#define WRMEM1_190_FLD2 GENMASK(31, 16) +#define WRMEM1_190_FLD3 GENMASK(47, 32) +#define WRMEM1_190_FLD4 GENMASK(63, 48) +#define WRMEM1_190_FLD5 GENMASK(79, 64) +#define WRMEM1_190_FLD6 GENMASK(95, 80) +#define WRMEM1_190_FLD7 GENMASK(111, 96) +#define WRMEM1_190_FLD8 GENMASK(127, 112) + +/* WRMEM1_191 register fields */ +#define WRMEM1_191_FLD1 GENMASK(15, 0) +#define WRMEM1_191_FLD2 GENMASK(31, 16) +#define WRMEM1_191_FLD3 GENMASK(47, 32) +#define WRMEM1_191_FLD4 GENMASK(63, 48) +#define WRMEM1_191_FLD5 GENMASK(79, 64) +#define WRMEM1_191_FLD6 GENMASK(95, 80) +#define WRMEM1_191_FLD7 GENMASK(111, 96) +#define WRMEM1_191_FLD8 GENMASK(127, 112) + +/* WRMEM1_192 register fields */ +#define WRMEM1_192_FLD1 GENMASK(15, 0) +#define WRMEM1_192_FLD2 GENMASK(31, 16) +#define WRMEM1_192_FLD3 GENMASK(47, 32) +#define WRMEM1_192_FLD4 GENMASK(63, 48) +#define WRMEM1_192_FLD5 GENMASK(79, 64) +#define WRMEM1_192_FLD6 GENMASK(95, 80) +#define WRMEM1_192_FLD7 GENMASK(111, 96) +#define WRMEM1_192_FLD8 GENMASK(127, 112) + +/* WRMEM1_193 register fields */ +#define WRMEM1_193_FLD1 GENMASK(15, 0) +#define WRMEM1_193_FLD2 GENMASK(31, 16) +#define WRMEM1_193_FLD3 GENMASK(47, 32) +#define WRMEM1_193_FLD4 GENMASK(63, 48) +#define WRMEM1_193_FLD5 GENMASK(79, 64) +#define WRMEM1_193_FLD6 GENMASK(95, 80) +#define WRMEM1_193_FLD7 GENMASK(111, 96) +#define WRMEM1_193_FLD8 GENMASK(127, 112) + +/* WRMEM1_194 register fields */ +#define WRMEM1_194_FLD1 GENMASK(15, 0) +#define WRMEM1_194_FLD2 GENMASK(31, 16) +#define WRMEM1_194_FLD3 GENMASK(47, 32) +#define WRMEM1_194_FLD4 GENMASK(63, 48) +#define WRMEM1_194_FLD5 GENMASK(79, 64) +#define WRMEM1_194_FLD6 GENMASK(95, 80) +#define WRMEM1_194_FLD7 GENMASK(111, 96) +#define WRMEM1_194_FLD8 GENMASK(127, 112) + +/* WRMEM1_195 register fields */ +#define WRMEM1_195_FLD1 GENMASK(15, 0) +#define WRMEM1_195_FLD2 GENMASK(31, 16) +#define WRMEM1_195_FLD3 GENMASK(47, 32) +#define WRMEM1_195_FLD4 GENMASK(63, 48) +#define WRMEM1_195_FLD5 GENMASK(79, 64) +#define WRMEM1_195_FLD6 GENMASK(95, 80) +#define WRMEM1_195_FLD7 GENMASK(111, 96) +#define WRMEM1_195_FLD8 GENMASK(127, 112) + +/* WRMEM1_196 register fields */ +#define WRMEM1_196_FLD1 GENMASK(15, 0) +#define WRMEM1_196_FLD2 GENMASK(31, 16) +#define WRMEM1_196_FLD3 GENMASK(47, 32) +#define WRMEM1_196_FLD4 GENMASK(63, 48) +#define WRMEM1_196_FLD5 GENMASK(79, 64) +#define WRMEM1_196_FLD6 GENMASK(95, 80) +#define WRMEM1_196_FLD7 GENMASK(111, 96) +#define WRMEM1_196_FLD8 GENMASK(127, 112) + +/* WRMEM1_197 register fields */ +#define WRMEM1_197_FLD1 GENMASK(15, 0) +#define WRMEM1_197_FLD2 GENMASK(31, 16) +#define WRMEM1_197_FLD3 GENMASK(47, 32) +#define WRMEM1_197_FLD4 GENMASK(63, 48) +#define WRMEM1_197_FLD5 GENMASK(79, 64) +#define WRMEM1_197_FLD6 GENMASK(95, 80) +#define WRMEM1_197_FLD7 GENMASK(111, 96) +#define WRMEM1_197_FLD8 GENMASK(127, 112) + +/* WRMEM1_198 register fields */ +#define WRMEM1_198_FLD1 GENMASK(15, 0) +#define WRMEM1_198_FLD2 GENMASK(31, 16) +#define WRMEM1_198_FLD3 GENMASK(47, 32) +#define WRMEM1_198_FLD4 GENMASK(63, 48) +#define WRMEM1_198_FLD5 GENMASK(79, 64) +#define WRMEM1_198_FLD6 GENMASK(95, 80) +#define WRMEM1_198_FLD7 GENMASK(111, 96) +#define WRMEM1_198_FLD8 GENMASK(127, 112) + +/* WRMEM1_199 register fields */ +#define WRMEM1_199_FLD1 GENMASK(15, 0) +#define WRMEM1_199_FLD2 GENMASK(31, 16) +#define WRMEM1_199_FLD3 GENMASK(47, 32) +#define WRMEM1_199_FLD4 GENMASK(63, 48) +#define WRMEM1_199_FLD5 GENMASK(79, 64) +#define WRMEM1_199_FLD6 GENMASK(95, 80) +#define WRMEM1_199_FLD7 GENMASK(111, 96) +#define WRMEM1_199_FLD8 GENMASK(127, 112) + +/* WRMEM1_200 register fields */ +#define WRMEM1_200_FLD1 GENMASK(15, 0) +#define WRMEM1_200_FLD2 GENMASK(31, 16) +#define WRMEM1_200_FLD3 GENMASK(47, 32) +#define WRMEM1_200_FLD4 GENMASK(63, 48) +#define WRMEM1_200_FLD5 GENMASK(79, 64) +#define WRMEM1_200_FLD6 GENMASK(95, 80) +#define WRMEM1_200_FLD7 GENMASK(111, 96) +#define WRMEM1_200_FLD8 GENMASK(127, 112) + +/* WRMEM1_201 register fields */ +#define WRMEM1_201_FLD1 GENMASK(15, 0) +#define WRMEM1_201_FLD2 GENMASK(31, 16) +#define WRMEM1_201_FLD3 GENMASK(47, 32) +#define WRMEM1_201_FLD4 GENMASK(63, 48) +#define WRMEM1_201_FLD5 GENMASK(79, 64) +#define WRMEM1_201_FLD6 GENMASK(95, 80) +#define WRMEM1_201_FLD7 GENMASK(111, 96) +#define WRMEM1_201_FLD8 GENMASK(127, 112) + +/* WRMEM1_202 register fields */ +#define WRMEM1_202_FLD1 GENMASK(15, 0) +#define WRMEM1_202_FLD2 GENMASK(31, 16) +#define WRMEM1_202_FLD3 GENMASK(47, 32) +#define WRMEM1_202_FLD4 GENMASK(63, 48) +#define WRMEM1_202_FLD5 GENMASK(79, 64) +#define WRMEM1_202_FLD6 GENMASK(95, 80) +#define WRMEM1_202_FLD7 GENMASK(111, 96) +#define WRMEM1_202_FLD8 GENMASK(127, 112) + +/* WRMEM1_203 register fields */ +#define WRMEM1_203_FLD1 GENMASK(15, 0) +#define WRMEM1_203_FLD2 GENMASK(31, 16) +#define WRMEM1_203_FLD3 GENMASK(47, 32) +#define WRMEM1_203_FLD4 GENMASK(63, 48) +#define WRMEM1_203_FLD5 GENMASK(79, 64) +#define WRMEM1_203_FLD6 GENMASK(95, 80) +#define WRMEM1_203_FLD7 GENMASK(111, 96) +#define WRMEM1_203_FLD8 GENMASK(127, 112) + +/* WRMEM1_204 register fields */ +#define WRMEM1_204_FLD1 GENMASK(15, 0) +#define WRMEM1_204_FLD2 GENMASK(31, 16) +#define WRMEM1_204_FLD3 GENMASK(47, 32) +#define WRMEM1_204_FLD4 GENMASK(63, 48) +#define WRMEM1_204_FLD5 GENMASK(79, 64) +#define WRMEM1_204_FLD6 GENMASK(95, 80) +#define WRMEM1_204_FLD7 GENMASK(111, 96) +#define WRMEM1_204_FLD8 GENMASK(127, 112) + +/* WRMEM1_205 register fields */ +#define WRMEM1_205_FLD1 GENMASK(15, 0) +#define WRMEM1_205_FLD2 GENMASK(31, 16) +#define WRMEM1_205_FLD3 GENMASK(47, 32) +#define WRMEM1_205_FLD4 GENMASK(63, 48) +#define WRMEM1_205_FLD5 GENMASK(79, 64) +#define WRMEM1_205_FLD6 GENMASK(95, 80) +#define WRMEM1_205_FLD7 GENMASK(111, 96) +#define WRMEM1_205_FLD8 GENMASK(127, 112) + +/* WRMEM1_206 register fields */ +#define WRMEM1_206_FLD1 GENMASK(15, 0) +#define WRMEM1_206_FLD2 GENMASK(31, 16) +#define WRMEM1_206_FLD3 GENMASK(47, 32) +#define WRMEM1_206_FLD4 GENMASK(63, 48) +#define WRMEM1_206_FLD5 GENMASK(79, 64) +#define WRMEM1_206_FLD6 GENMASK(95, 80) +#define WRMEM1_206_FLD7 GENMASK(111, 96) +#define WRMEM1_206_FLD8 GENMASK(127, 112) + +/* WRMEM1_207 register fields */ +#define WRMEM1_207_FLD1 GENMASK(15, 0) +#define WRMEM1_207_FLD2 GENMASK(31, 16) +#define WRMEM1_207_FLD3 GENMASK(47, 32) +#define WRMEM1_207_FLD4 GENMASK(63, 48) +#define WRMEM1_207_FLD5 GENMASK(79, 64) +#define WRMEM1_207_FLD6 GENMASK(95, 80) +#define WRMEM1_207_FLD7 GENMASK(111, 96) +#define WRMEM1_207_FLD8 GENMASK(127, 112) + +/* WRMEM1_208 register fields */ +#define WRMEM1_208_FLD1 GENMASK(15, 0) +#define WRMEM1_208_FLD2 GENMASK(31, 16) +#define WRMEM1_208_FLD3 GENMASK(47, 32) +#define WRMEM1_208_FLD4 GENMASK(63, 48) +#define WRMEM1_208_FLD5 GENMASK(79, 64) +#define WRMEM1_208_FLD6 GENMASK(95, 80) +#define WRMEM1_208_FLD7 GENMASK(111, 96) +#define WRMEM1_208_FLD8 GENMASK(127, 112) + +/* WRMEM1_209 register fields */ +#define WRMEM1_209_FLD1 GENMASK(15, 0) +#define WRMEM1_209_FLD2 GENMASK(31, 16) +#define WRMEM1_209_FLD3 GENMASK(47, 32) +#define WRMEM1_209_FLD4 GENMASK(63, 48) +#define WRMEM1_209_FLD5 GENMASK(79, 64) +#define WRMEM1_209_FLD6 GENMASK(95, 80) +#define WRMEM1_209_FLD7 GENMASK(111, 96) +#define WRMEM1_209_FLD8 GENMASK(127, 112) + +/* WRMEM1_210 register fields */ +#define WRMEM1_210_FLD1 GENMASK(15, 0) +#define WRMEM1_210_FLD2 GENMASK(31, 16) +#define WRMEM1_210_FLD3 GENMASK(47, 32) +#define WRMEM1_210_FLD4 GENMASK(63, 48) +#define WRMEM1_210_FLD5 GENMASK(79, 64) +#define WRMEM1_210_FLD6 GENMASK(95, 80) +#define WRMEM1_210_FLD7 GENMASK(111, 96) +#define WRMEM1_210_FLD8 GENMASK(127, 112) + +/* WRMEM1_211 register fields */ +#define WRMEM1_211_FLD1 GENMASK(15, 0) +#define WRMEM1_211_FLD2 GENMASK(31, 16) +#define WRMEM1_211_FLD3 GENMASK(47, 32) +#define WRMEM1_211_FLD4 GENMASK(63, 48) +#define WRMEM1_211_FLD5 GENMASK(79, 64) +#define WRMEM1_211_FLD6 GENMASK(95, 80) +#define WRMEM1_211_FLD7 GENMASK(111, 96) +#define WRMEM1_211_FLD8 GENMASK(127, 112) + +/* WRMEM1_212 register fields */ +#define WRMEM1_212_FLD1 GENMASK(15, 0) +#define WRMEM1_212_FLD2 GENMASK(31, 16) +#define WRMEM1_212_FLD3 GENMASK(47, 32) +#define WRMEM1_212_FLD4 GENMASK(63, 48) +#define WRMEM1_212_FLD5 GENMASK(79, 64) +#define WRMEM1_212_FLD6 GENMASK(95, 80) +#define WRMEM1_212_FLD7 GENMASK(111, 96) +#define WRMEM1_212_FLD8 GENMASK(127, 112) + +/* WRMEM1_213 register fields */ +#define WRMEM1_213_FLD1 GENMASK(15, 0) +#define WRMEM1_213_FLD2 GENMASK(31, 16) +#define WRMEM1_213_FLD3 GENMASK(47, 32) +#define WRMEM1_213_FLD4 GENMASK(63, 48) +#define WRMEM1_213_FLD5 GENMASK(79, 64) +#define WRMEM1_213_FLD6 GENMASK(95, 80) +#define WRMEM1_213_FLD7 GENMASK(111, 96) +#define WRMEM1_213_FLD8 GENMASK(127, 112) + +/* WRMEM1_214 register fields */ +#define WRMEM1_214_FLD1 GENMASK(15, 0) +#define WRMEM1_214_FLD2 GENMASK(31, 16) +#define WRMEM1_214_FLD3 GENMASK(47, 32) +#define WRMEM1_214_FLD4 GENMASK(63, 48) +#define WRMEM1_214_FLD5 GENMASK(79, 64) +#define WRMEM1_214_FLD6 GENMASK(95, 80) +#define WRMEM1_214_FLD7 GENMASK(111, 96) +#define WRMEM1_214_FLD8 GENMASK(127, 112) + +/* WRMEM1_215 register fields */ +#define WRMEM1_215_FLD1 GENMASK(15, 0) +#define WRMEM1_215_FLD2 GENMASK(31, 16) +#define WRMEM1_215_FLD3 GENMASK(47, 32) +#define WRMEM1_215_FLD4 GENMASK(63, 48) +#define WRMEM1_215_FLD5 GENMASK(79, 64) +#define WRMEM1_215_FLD6 GENMASK(95, 80) +#define WRMEM1_215_FLD7 GENMASK(111, 96) +#define WRMEM1_215_FLD8 GENMASK(127, 112) + +/* WRMEM1_216 register fields */ +#define WRMEM1_216_FLD1 GENMASK(15, 0) +#define WRMEM1_216_FLD2 GENMASK(31, 16) +#define WRMEM1_216_FLD3 GENMASK(47, 32) +#define WRMEM1_216_FLD4 GENMASK(63, 48) +#define WRMEM1_216_FLD5 GENMASK(79, 64) +#define WRMEM1_216_FLD6 GENMASK(95, 80) +#define WRMEM1_216_FLD7 GENMASK(111, 96) +#define WRMEM1_216_FLD8 GENMASK(127, 112) + +/* WRMEM1_217 register fields */ +#define WRMEM1_217_FLD1 GENMASK(15, 0) +#define WRMEM1_217_FLD2 GENMASK(31, 16) +#define WRMEM1_217_FLD3 GENMASK(47, 32) +#define WRMEM1_217_FLD4 GENMASK(63, 48) +#define WRMEM1_217_FLD5 GENMASK(79, 64) +#define WRMEM1_217_FLD6 GENMASK(95, 80) +#define WRMEM1_217_FLD7 GENMASK(111, 96) +#define WRMEM1_217_FLD8 GENMASK(127, 112) + +/* WRMEM1_218 register fields */ +#define WRMEM1_218_FLD1 GENMASK(15, 0) +#define WRMEM1_218_FLD2 GENMASK(31, 16) +#define WRMEM1_218_FLD3 GENMASK(47, 32) +#define WRMEM1_218_FLD4 GENMASK(63, 48) +#define WRMEM1_218_FLD5 GENMASK(79, 64) +#define WRMEM1_218_FLD6 GENMASK(95, 80) +#define WRMEM1_218_FLD7 GENMASK(111, 96) +#define WRMEM1_218_FLD8 GENMASK(127, 112) + +/* WRMEM1_219 register fields */ +#define WRMEM1_219_FLD1 GENMASK(15, 0) +#define WRMEM1_219_FLD2 GENMASK(31, 16) +#define WRMEM1_219_FLD3 GENMASK(47, 32) +#define WRMEM1_219_FLD4 GENMASK(63, 48) +#define WRMEM1_219_FLD5 GENMASK(79, 64) +#define WRMEM1_219_FLD6 GENMASK(95, 80) +#define WRMEM1_219_FLD7 GENMASK(111, 96) +#define WRMEM1_219_FLD8 GENMASK(127, 112) + +/* WRMEM1_220 register fields */ +#define WRMEM1_220_FLD1 GENMASK(15, 0) +#define WRMEM1_220_FLD2 GENMASK(31, 16) +#define WRMEM1_220_FLD3 GENMASK(47, 32) +#define WRMEM1_220_FLD4 GENMASK(63, 48) +#define WRMEM1_220_FLD5 GENMASK(79, 64) +#define WRMEM1_220_FLD6 GENMASK(95, 80) +#define WRMEM1_220_FLD7 GENMASK(111, 96) +#define WRMEM1_220_FLD8 GENMASK(127, 112) + +/* WRMEM1_221 register fields */ +#define WRMEM1_221_FLD1 GENMASK(15, 0) +#define WRMEM1_221_FLD2 GENMASK(31, 16) +#define WRMEM1_221_FLD3 GENMASK(47, 32) +#define WRMEM1_221_FLD4 GENMASK(63, 48) +#define WRMEM1_221_FLD5 GENMASK(79, 64) +#define WRMEM1_221_FLD6 GENMASK(95, 80) +#define WRMEM1_221_FLD7 GENMASK(111, 96) +#define WRMEM1_221_FLD8 GENMASK(127, 112) + +/* WRMEM1_222 register fields */ +#define WRMEM1_222_FLD1 GENMASK(15, 0) +#define WRMEM1_222_FLD2 GENMASK(31, 16) +#define WRMEM1_222_FLD3 GENMASK(47, 32) +#define WRMEM1_222_FLD4 GENMASK(63, 48) +#define WRMEM1_222_FLD5 GENMASK(79, 64) +#define WRMEM1_222_FLD6 GENMASK(95, 80) +#define WRMEM1_222_FLD7 GENMASK(111, 96) +#define WRMEM1_222_FLD8 GENMASK(127, 112) + +/* WRMEM1_223 register fields */ +#define WRMEM1_223_FLD1 GENMASK(15, 0) +#define WRMEM1_223_FLD2 GENMASK(31, 16) +#define WRMEM1_223_FLD3 GENMASK(47, 32) +#define WRMEM1_223_FLD4 GENMASK(63, 48) +#define WRMEM1_223_FLD5 GENMASK(79, 64) +#define WRMEM1_223_FLD6 GENMASK(95, 80) +#define WRMEM1_223_FLD7 GENMASK(111, 96) +#define WRMEM1_223_FLD8 GENMASK(127, 112) + +/* WRMEM1_224 register fields */ +#define WRMEM1_224_FLD1 GENMASK(15, 0) +#define WRMEM1_224_FLD2 GENMASK(31, 16) +#define WRMEM1_224_FLD3 GENMASK(47, 32) +#define WRMEM1_224_FLD4 GENMASK(63, 48) +#define WRMEM1_224_FLD5 GENMASK(79, 64) +#define WRMEM1_224_FLD6 GENMASK(95, 80) +#define WRMEM1_224_FLD7 GENMASK(111, 96) +#define WRMEM1_224_FLD8 GENMASK(127, 112) + +/* WRMEM1_225 register fields */ +#define WRMEM1_225_FLD1 GENMASK(15, 0) +#define WRMEM1_225_FLD2 GENMASK(31, 16) +#define WRMEM1_225_FLD3 GENMASK(47, 32) +#define WRMEM1_225_FLD4 GENMASK(63, 48) +#define WRMEM1_225_FLD5 GENMASK(79, 64) +#define WRMEM1_225_FLD6 GENMASK(95, 80) +#define WRMEM1_225_FLD7 GENMASK(111, 96) +#define WRMEM1_225_FLD8 GENMASK(127, 112) + +/* WRMEM1_226 register fields */ +#define WRMEM1_226_FLD1 GENMASK(15, 0) +#define WRMEM1_226_FLD2 GENMASK(31, 16) +#define WRMEM1_226_FLD3 GENMASK(47, 32) +#define WRMEM1_226_FLD4 GENMASK(63, 48) +#define WRMEM1_226_FLD5 GENMASK(79, 64) +#define WRMEM1_226_FLD6 GENMASK(95, 80) +#define WRMEM1_226_FLD7 GENMASK(111, 96) +#define WRMEM1_226_FLD8 GENMASK(127, 112) + +/* WRMEM1_227 register fields */ +#define WRMEM1_227_FLD1 GENMASK(15, 0) +#define WRMEM1_227_FLD2 GENMASK(31, 16) +#define WRMEM1_227_FLD3 GENMASK(47, 32) +#define WRMEM1_227_FLD4 GENMASK(63, 48) +#define WRMEM1_227_FLD5 GENMASK(79, 64) +#define WRMEM1_227_FLD6 GENMASK(95, 80) +#define WRMEM1_227_FLD7 GENMASK(111, 96) +#define WRMEM1_227_FLD8 GENMASK(127, 112) + +/* WRMEM1_228 register fields */ +#define WRMEM1_228_FLD1 GENMASK(15, 0) +#define WRMEM1_228_FLD2 GENMASK(31, 16) +#define WRMEM1_228_FLD3 GENMASK(47, 32) +#define WRMEM1_228_FLD4 GENMASK(63, 48) +#define WRMEM1_228_FLD5 GENMASK(79, 64) +#define WRMEM1_228_FLD6 GENMASK(95, 80) +#define WRMEM1_228_FLD7 GENMASK(111, 96) +#define WRMEM1_228_FLD8 GENMASK(127, 112) + +/* WRMEM1_229 register fields */ +#define WRMEM1_229_FLD1 GENMASK(15, 0) +#define WRMEM1_229_FLD2 GENMASK(31, 16) +#define WRMEM1_229_FLD3 GENMASK(47, 32) +#define WRMEM1_229_FLD4 GENMASK(63, 48) +#define WRMEM1_229_FLD5 GENMASK(79, 64) +#define WRMEM1_229_FLD6 GENMASK(95, 80) +#define WRMEM1_229_FLD7 GENMASK(111, 96) +#define WRMEM1_229_FLD8 GENMASK(127, 112) + +/* WRMEM1_230 register fields */ +#define WRMEM1_230_FLD1 GENMASK(15, 0) +#define WRMEM1_230_FLD2 GENMASK(31, 16) +#define WRMEM1_230_FLD3 GENMASK(47, 32) +#define WRMEM1_230_FLD4 GENMASK(63, 48) +#define WRMEM1_230_FLD5 GENMASK(79, 64) +#define WRMEM1_230_FLD6 GENMASK(95, 80) +#define WRMEM1_230_FLD7 GENMASK(111, 96) +#define WRMEM1_230_FLD8 GENMASK(127, 112) + +/* WRMEM1_231 register fields */ +#define WRMEM1_231_FLD1 GENMASK(15, 0) +#define WRMEM1_231_FLD2 GENMASK(31, 16) +#define WRMEM1_231_FLD3 GENMASK(47, 32) +#define WRMEM1_231_FLD4 GENMASK(63, 48) +#define WRMEM1_231_FLD5 GENMASK(79, 64) +#define WRMEM1_231_FLD6 GENMASK(95, 80) +#define WRMEM1_231_FLD7 GENMASK(111, 96) +#define WRMEM1_231_FLD8 GENMASK(127, 112) + +/* WRMEM1_232 register fields */ +#define WRMEM1_232_FLD1 GENMASK(15, 0) +#define WRMEM1_232_FLD2 GENMASK(31, 16) +#define WRMEM1_232_FLD3 GENMASK(47, 32) +#define WRMEM1_232_FLD4 GENMASK(63, 48) +#define WRMEM1_232_FLD5 GENMASK(79, 64) +#define WRMEM1_232_FLD6 GENMASK(95, 80) +#define WRMEM1_232_FLD7 GENMASK(111, 96) +#define WRMEM1_232_FLD8 GENMASK(127, 112) + +/* WRMEM1_233 register fields */ +#define WRMEM1_233_FLD1 GENMASK(15, 0) +#define WRMEM1_233_FLD2 GENMASK(31, 16) +#define WRMEM1_233_FLD3 GENMASK(47, 32) +#define WRMEM1_233_FLD4 GENMASK(63, 48) +#define WRMEM1_233_FLD5 GENMASK(79, 64) +#define WRMEM1_233_FLD6 GENMASK(95, 80) +#define WRMEM1_233_FLD7 GENMASK(111, 96) +#define WRMEM1_233_FLD8 GENMASK(127, 112) + +/* WRMEM1_234 register fields */ +#define WRMEM1_234_FLD1 GENMASK(15, 0) +#define WRMEM1_234_FLD2 GENMASK(31, 16) +#define WRMEM1_234_FLD3 GENMASK(47, 32) +#define WRMEM1_234_FLD4 GENMASK(63, 48) +#define WRMEM1_234_FLD5 GENMASK(79, 64) +#define WRMEM1_234_FLD6 GENMASK(95, 80) +#define WRMEM1_234_FLD7 GENMASK(111, 96) +#define WRMEM1_234_FLD8 GENMASK(127, 112) + +/* WRMEM1_235 register fields */ +#define WRMEM1_235_FLD1 GENMASK(15, 0) +#define WRMEM1_235_FLD2 GENMASK(31, 16) +#define WRMEM1_235_FLD3 GENMASK(47, 32) +#define WRMEM1_235_FLD4 GENMASK(63, 48) +#define WRMEM1_235_FLD5 GENMASK(79, 64) +#define WRMEM1_235_FLD6 GENMASK(95, 80) +#define WRMEM1_235_FLD7 GENMASK(111, 96) +#define WRMEM1_235_FLD8 GENMASK(127, 112) + +/* WRMEM1_236 register fields */ +#define WRMEM1_236_FLD1 GENMASK(15, 0) +#define WRMEM1_236_FLD2 GENMASK(31, 16) +#define WRMEM1_236_FLD3 GENMASK(47, 32) +#define WRMEM1_236_FLD4 GENMASK(63, 48) +#define WRMEM1_236_FLD5 GENMASK(79, 64) +#define WRMEM1_236_FLD6 GENMASK(95, 80) +#define WRMEM1_236_FLD7 GENMASK(111, 96) +#define WRMEM1_236_FLD8 GENMASK(127, 112) + +/* WRMEM1_237 register fields */ +#define WRMEM1_237_FLD1 GENMASK(15, 0) +#define WRMEM1_237_FLD2 GENMASK(31, 16) +#define WRMEM1_237_FLD3 GENMASK(47, 32) +#define WRMEM1_237_FLD4 GENMASK(63, 48) +#define WRMEM1_237_FLD5 GENMASK(79, 64) +#define WRMEM1_237_FLD6 GENMASK(95, 80) +#define WRMEM1_237_FLD7 GENMASK(111, 96) +#define WRMEM1_237_FLD8 GENMASK(127, 112) + +/* WRMEM1_238 register fields */ +#define WRMEM1_238_FLD1 GENMASK(15, 0) +#define WRMEM1_238_FLD2 GENMASK(31, 16) +#define WRMEM1_238_FLD3 GENMASK(47, 32) +#define WRMEM1_238_FLD4 GENMASK(63, 48) +#define WRMEM1_238_FLD5 GENMASK(79, 64) +#define WRMEM1_238_FLD6 GENMASK(95, 80) +#define WRMEM1_238_FLD7 GENMASK(111, 96) +#define WRMEM1_238_FLD8 GENMASK(127, 112) + +/* WRMEM1_239 register fields */ +#define WRMEM1_239_FLD1 GENMASK(15, 0) +#define WRMEM1_239_FLD2 GENMASK(31, 16) +#define WRMEM1_239_FLD3 GENMASK(47, 32) +#define WRMEM1_239_FLD4 GENMASK(63, 48) +#define WRMEM1_239_FLD5 GENMASK(79, 64) +#define WRMEM1_239_FLD6 GENMASK(95, 80) +#define WRMEM1_239_FLD7 GENMASK(111, 96) +#define WRMEM1_239_FLD8 GENMASK(127, 112) + +/* WRMEM1_240 register fields */ +#define WRMEM1_240_FLD1 GENMASK(15, 0) +#define WRMEM1_240_FLD2 GENMASK(31, 16) +#define WRMEM1_240_FLD3 GENMASK(47, 32) +#define WRMEM1_240_FLD4 GENMASK(63, 48) +#define WRMEM1_240_FLD5 GENMASK(79, 64) +#define WRMEM1_240_FLD6 GENMASK(95, 80) +#define WRMEM1_240_FLD7 GENMASK(111, 96) +#define WRMEM1_240_FLD8 GENMASK(127, 112) + +/* WRMEM1_241 register fields */ +#define WRMEM1_241_FLD1 GENMASK(15, 0) +#define WRMEM1_241_FLD2 GENMASK(31, 16) +#define WRMEM1_241_FLD3 GENMASK(47, 32) +#define WRMEM1_241_FLD4 GENMASK(63, 48) +#define WRMEM1_241_FLD5 GENMASK(79, 64) +#define WRMEM1_241_FLD6 GENMASK(95, 80) +#define WRMEM1_241_FLD7 GENMASK(111, 96) +#define WRMEM1_241_FLD8 GENMASK(127, 112) + +/* WRMEM1_242 register fields */ +#define WRMEM1_242_FLD1 GENMASK(15, 0) +#define WRMEM1_242_FLD2 GENMASK(31, 16) +#define WRMEM1_242_FLD3 GENMASK(47, 32) +#define WRMEM1_242_FLD4 GENMASK(63, 48) +#define WRMEM1_242_FLD5 GENMASK(79, 64) +#define WRMEM1_242_FLD6 GENMASK(95, 80) +#define WRMEM1_242_FLD7 GENMASK(111, 96) +#define WRMEM1_242_FLD8 GENMASK(127, 112) + +/* WRMEM1_243 register fields */ +#define WRMEM1_243_FLD1 GENMASK(15, 0) +#define WRMEM1_243_FLD2 GENMASK(31, 16) +#define WRMEM1_243_FLD3 GENMASK(47, 32) +#define WRMEM1_243_FLD4 GENMASK(63, 48) +#define WRMEM1_243_FLD5 GENMASK(79, 64) +#define WRMEM1_243_FLD6 GENMASK(95, 80) +#define WRMEM1_243_FLD7 GENMASK(111, 96) +#define WRMEM1_243_FLD8 GENMASK(127, 112) + +/* WRMEM1_244 register fields */ +#define WRMEM1_244_FLD1 GENMASK(15, 0) +#define WRMEM1_244_FLD2 GENMASK(31, 16) +#define WRMEM1_244_FLD3 GENMASK(47, 32) +#define WRMEM1_244_FLD4 GENMASK(63, 48) +#define WRMEM1_244_FLD5 GENMASK(79, 64) +#define WRMEM1_244_FLD6 GENMASK(95, 80) +#define WRMEM1_244_FLD7 GENMASK(111, 96) +#define WRMEM1_244_FLD8 GENMASK(127, 112) + +/* WRMEM1_245 register fields */ +#define WRMEM1_245_FLD1 GENMASK(15, 0) +#define WRMEM1_245_FLD2 GENMASK(31, 16) +#define WRMEM1_245_FLD3 GENMASK(47, 32) +#define WRMEM1_245_FLD4 GENMASK(63, 48) +#define WRMEM1_245_FLD5 GENMASK(79, 64) +#define WRMEM1_245_FLD6 GENMASK(95, 80) +#define WRMEM1_245_FLD7 GENMASK(111, 96) +#define WRMEM1_245_FLD8 GENMASK(127, 112) + +/* WRMEM1_246 register fields */ +#define WRMEM1_246_FLD1 GENMASK(15, 0) +#define WRMEM1_246_FLD2 GENMASK(31, 16) +#define WRMEM1_246_FLD3 GENMASK(47, 32) +#define WRMEM1_246_FLD4 GENMASK(63, 48) +#define WRMEM1_246_FLD5 GENMASK(79, 64) +#define WRMEM1_246_FLD6 GENMASK(95, 80) +#define WRMEM1_246_FLD7 GENMASK(111, 96) +#define WRMEM1_246_FLD8 GENMASK(127, 112) + +/* WRMEM1_247 register fields */ +#define WRMEM1_247_FLD1 GENMASK(15, 0) +#define WRMEM1_247_FLD2 GENMASK(31, 16) +#define WRMEM1_247_FLD3 GENMASK(47, 32) +#define WRMEM1_247_FLD4 GENMASK(63, 48) +#define WRMEM1_247_FLD5 GENMASK(79, 64) +#define WRMEM1_247_FLD6 GENMASK(95, 80) +#define WRMEM1_247_FLD7 GENMASK(111, 96) +#define WRMEM1_247_FLD8 GENMASK(127, 112) + +/* WRMEM1_248 register fields */ +#define WRMEM1_248_FLD1 GENMASK(15, 0) +#define WRMEM1_248_FLD2 GENMASK(31, 16) +#define WRMEM1_248_FLD3 GENMASK(47, 32) +#define WRMEM1_248_FLD4 GENMASK(63, 48) +#define WRMEM1_248_FLD5 GENMASK(79, 64) +#define WRMEM1_248_FLD6 GENMASK(95, 80) +#define WRMEM1_248_FLD7 GENMASK(111, 96) +#define WRMEM1_248_FLD8 GENMASK(127, 112) + +/* WRMEM1_249 register fields */ +#define WRMEM1_249_FLD1 GENMASK(15, 0) +#define WRMEM1_249_FLD2 GENMASK(31, 16) +#define WRMEM1_249_FLD3 GENMASK(47, 32) +#define WRMEM1_249_FLD4 GENMASK(63, 48) +#define WRMEM1_249_FLD5 GENMASK(79, 64) +#define WRMEM1_249_FLD6 GENMASK(95, 80) +#define WRMEM1_249_FLD7 GENMASK(111, 96) +#define WRMEM1_249_FLD8 GENMASK(127, 112) + +/* WRMEM1_250 register fields */ +#define WRMEM1_250_FLD1 GENMASK(15, 0) +#define WRMEM1_250_FLD2 GENMASK(31, 16) +#define WRMEM1_250_FLD3 GENMASK(47, 32) +#define WRMEM1_250_FLD4 GENMASK(63, 48) +#define WRMEM1_250_FLD5 GENMASK(79, 64) +#define WRMEM1_250_FLD6 GENMASK(95, 80) +#define WRMEM1_250_FLD7 GENMASK(111, 96) +#define WRMEM1_250_FLD8 GENMASK(127, 112) + +/* WRMEM1_251 register fields */ +#define WRMEM1_251_FLD1 GENMASK(15, 0) +#define WRMEM1_251_FLD2 GENMASK(31, 16) +#define WRMEM1_251_FLD3 GENMASK(47, 32) +#define WRMEM1_251_FLD4 GENMASK(63, 48) +#define WRMEM1_251_FLD5 GENMASK(79, 64) +#define WRMEM1_251_FLD6 GENMASK(95, 80) +#define WRMEM1_251_FLD7 GENMASK(111, 96) +#define WRMEM1_251_FLD8 GENMASK(127, 112) + +/* WRMEM1_252 register fields */ +#define WRMEM1_252_FLD1 GENMASK(15, 0) +#define WRMEM1_252_FLD2 GENMASK(31, 16) +#define WRMEM1_252_FLD3 GENMASK(47, 32) +#define WRMEM1_252_FLD4 GENMASK(63, 48) +#define WRMEM1_252_FLD5 GENMASK(79, 64) +#define WRMEM1_252_FLD6 GENMASK(95, 80) +#define WRMEM1_252_FLD7 GENMASK(111, 96) +#define WRMEM1_252_FLD8 GENMASK(127, 112) + +/* WRMEM1_253 register fields */ +#define WRMEM1_253_FLD1 GENMASK(15, 0) +#define WRMEM1_253_FLD2 GENMASK(31, 16) +#define WRMEM1_253_FLD3 GENMASK(47, 32) +#define WRMEM1_253_FLD4 GENMASK(63, 48) +#define WRMEM1_253_FLD5 GENMASK(79, 64) +#define WRMEM1_253_FLD6 GENMASK(95, 80) +#define WRMEM1_253_FLD7 GENMASK(111, 96) +#define WRMEM1_253_FLD8 GENMASK(127, 112) + +/* WRMEM1_254 register fields */ +#define WRMEM1_254_FLD1 GENMASK(15, 0) +#define WRMEM1_254_FLD2 GENMASK(31, 16) +#define WRMEM1_254_FLD3 GENMASK(47, 32) +#define WRMEM1_254_FLD4 GENMASK(63, 48) +#define WRMEM1_254_FLD5 GENMASK(79, 64) +#define WRMEM1_254_FLD6 GENMASK(95, 80) +#define WRMEM1_254_FLD7 GENMASK(111, 96) +#define WRMEM1_254_FLD8 GENMASK(127, 112) + +/* WRMEM1_255 register fields */ +#define WRMEM1_255_FLD1 GENMASK(15, 0) +#define WRMEM1_255_FLD2 GENMASK(31, 16) +#define WRMEM1_255_FLD3 GENMASK(47, 32) +#define WRMEM1_255_FLD4 GENMASK(63, 48) +#define WRMEM1_255_FLD5 GENMASK(79, 64) +#define WRMEM1_255_FLD6 GENMASK(95, 80) +#define WRMEM1_255_FLD7 GENMASK(111, 96) +#define WRMEM1_255_FLD8 GENMASK(127, 112) + +/* WRMEM1_256 register fields */ +#define WRMEM1_256_FLD1 GENMASK(15, 0) +#define WRMEM1_256_FLD2 GENMASK(31, 16) +#define WRMEM1_256_FLD3 GENMASK(47, 32) +#define WRMEM1_256_FLD4 GENMASK(63, 48) +#define WRMEM1_256_FLD5 GENMASK(79, 64) +#define WRMEM1_256_FLD6 GENMASK(95, 80) +#define WRMEM1_256_FLD7 GENMASK(111, 96) +#define WRMEM1_256_FLD8 GENMASK(127, 112) + +/* WRMEM1_257 register fields */ +#define WRMEM1_257_FLD1 GENMASK(15, 0) +#define WRMEM1_257_FLD2 GENMASK(31, 16) +#define WRMEM1_257_FLD3 GENMASK(47, 32) +#define WRMEM1_257_FLD4 GENMASK(63, 48) +#define WRMEM1_257_FLD5 GENMASK(79, 64) +#define WRMEM1_257_FLD6 GENMASK(95, 80) +#define WRMEM1_257_FLD7 GENMASK(111, 96) +#define WRMEM1_257_FLD8 GENMASK(127, 112) + +/* WRMEM1_258 register fields */ +#define WRMEM1_258_FLD1 GENMASK(15, 0) +#define WRMEM1_258_FLD2 GENMASK(31, 16) +#define WRMEM1_258_FLD3 GENMASK(47, 32) +#define WRMEM1_258_FLD4 GENMASK(63, 48) +#define WRMEM1_258_FLD5 GENMASK(79, 64) +#define WRMEM1_258_FLD6 GENMASK(95, 80) +#define WRMEM1_258_FLD7 GENMASK(111, 96) +#define WRMEM1_258_FLD8 GENMASK(127, 112) + +/* WRMEM1_259 register fields */ +#define WRMEM1_259_FLD1 GENMASK(15, 0) +#define WRMEM1_259_FLD2 GENMASK(31, 16) +#define WRMEM1_259_FLD3 GENMASK(47, 32) +#define WRMEM1_259_FLD4 GENMASK(63, 48) +#define WRMEM1_259_FLD5 GENMASK(79, 64) +#define WRMEM1_259_FLD6 GENMASK(95, 80) +#define WRMEM1_259_FLD7 GENMASK(111, 96) +#define WRMEM1_259_FLD8 GENMASK(127, 112) + +/* WRMEM1_260 register fields */ +#define WRMEM1_260_FLD1 GENMASK(15, 0) +#define WRMEM1_260_FLD2 GENMASK(31, 16) +#define WRMEM1_260_FLD3 GENMASK(47, 32) +#define WRMEM1_260_FLD4 GENMASK(63, 48) +#define WRMEM1_260_FLD5 GENMASK(79, 64) +#define WRMEM1_260_FLD6 GENMASK(95, 80) +#define WRMEM1_260_FLD7 GENMASK(111, 96) +#define WRMEM1_260_FLD8 GENMASK(127, 112) + +/* WRMEM1_261 register fields */ +#define WRMEM1_261_FLD1 GENMASK(15, 0) +#define WRMEM1_261_FLD2 GENMASK(31, 16) +#define WRMEM1_261_FLD3 GENMASK(47, 32) +#define WRMEM1_261_FLD4 GENMASK(63, 48) +#define WRMEM1_261_FLD5 GENMASK(79, 64) +#define WRMEM1_261_FLD6 GENMASK(95, 80) +#define WRMEM1_261_FLD7 GENMASK(111, 96) +#define WRMEM1_261_FLD8 GENMASK(127, 112) + +/* WRMEM1_262 register fields */ +#define WRMEM1_262_FLD1 GENMASK(15, 0) +#define WRMEM1_262_FLD2 GENMASK(31, 16) +#define WRMEM1_262_FLD3 GENMASK(47, 32) +#define WRMEM1_262_FLD4 GENMASK(63, 48) +#define WRMEM1_262_FLD5 GENMASK(79, 64) +#define WRMEM1_262_FLD6 GENMASK(95, 80) +#define WRMEM1_262_FLD7 GENMASK(111, 96) +#define WRMEM1_262_FLD8 GENMASK(127, 112) + +/* WRMEM1_263 register fields */ +#define WRMEM1_263_FLD1 GENMASK(15, 0) +#define WRMEM1_263_FLD2 GENMASK(31, 16) +#define WRMEM1_263_FLD3 GENMASK(47, 32) +#define WRMEM1_263_FLD4 GENMASK(63, 48) +#define WRMEM1_263_FLD5 GENMASK(79, 64) +#define WRMEM1_263_FLD6 GENMASK(95, 80) +#define WRMEM1_263_FLD7 GENMASK(111, 96) +#define WRMEM1_263_FLD8 GENMASK(127, 112) + +/* WRMEM1_264 register fields */ +#define WRMEM1_264_FLD1 GENMASK(15, 0) +#define WRMEM1_264_FLD2 GENMASK(31, 16) +#define WRMEM1_264_FLD3 GENMASK(47, 32) +#define WRMEM1_264_FLD4 GENMASK(63, 48) +#define WRMEM1_264_FLD5 GENMASK(79, 64) +#define WRMEM1_264_FLD6 GENMASK(95, 80) +#define WRMEM1_264_FLD7 GENMASK(111, 96) +#define WRMEM1_264_FLD8 GENMASK(127, 112) + +/* WRMEM1_265 register fields */ +#define WRMEM1_265_FLD1 GENMASK(15, 0) +#define WRMEM1_265_FLD2 GENMASK(31, 16) +#define WRMEM1_265_FLD3 GENMASK(47, 32) +#define WRMEM1_265_FLD4 GENMASK(63, 48) +#define WRMEM1_265_FLD5 GENMASK(79, 64) +#define WRMEM1_265_FLD6 GENMASK(95, 80) +#define WRMEM1_265_FLD7 GENMASK(111, 96) +#define WRMEM1_265_FLD8 GENMASK(127, 112) + +/* WRMEM1_266 register fields */ +#define WRMEM1_266_FLD1 GENMASK(15, 0) +#define WRMEM1_266_FLD2 GENMASK(31, 16) +#define WRMEM1_266_FLD3 GENMASK(47, 32) +#define WRMEM1_266_FLD4 GENMASK(63, 48) +#define WRMEM1_266_FLD5 GENMASK(79, 64) +#define WRMEM1_266_FLD6 GENMASK(95, 80) +#define WRMEM1_266_FLD7 GENMASK(111, 96) +#define WRMEM1_266_FLD8 GENMASK(127, 112) + +/* WRMEM1_267 register fields */ +#define WRMEM1_267_FLD1 GENMASK(15, 0) +#define WRMEM1_267_FLD2 GENMASK(31, 16) +#define WRMEM1_267_FLD3 GENMASK(47, 32) +#define WRMEM1_267_FLD4 GENMASK(63, 48) +#define WRMEM1_267_FLD5 GENMASK(79, 64) +#define WRMEM1_267_FLD6 GENMASK(95, 80) +#define WRMEM1_267_FLD7 GENMASK(111, 96) +#define WRMEM1_267_FLD8 GENMASK(127, 112) + +/* WRMEM1_268 register fields */ +#define WRMEM1_268_FLD1 GENMASK(15, 0) +#define WRMEM1_268_FLD2 GENMASK(31, 16) +#define WRMEM1_268_FLD3 GENMASK(47, 32) +#define WRMEM1_268_FLD4 GENMASK(63, 48) +#define WRMEM1_268_FLD5 GENMASK(79, 64) +#define WRMEM1_268_FLD6 GENMASK(95, 80) +#define WRMEM1_268_FLD7 GENMASK(111, 96) +#define WRMEM1_268_FLD8 GENMASK(127, 112) + +/* WRMEM1_269 register fields */ +#define WRMEM1_269_FLD1 GENMASK(15, 0) +#define WRMEM1_269_FLD2 GENMASK(31, 16) +#define WRMEM1_269_FLD3 GENMASK(47, 32) +#define WRMEM1_269_FLD4 GENMASK(63, 48) +#define WRMEM1_269_FLD5 GENMASK(79, 64) +#define WRMEM1_269_FLD6 GENMASK(95, 80) +#define WRMEM1_269_FLD7 GENMASK(111, 96) +#define WRMEM1_269_FLD8 GENMASK(127, 112) + +/* WRMEM1_270 register fields */ +#define WRMEM1_270_FLD1 GENMASK(15, 0) +#define WRMEM1_270_FLD2 GENMASK(31, 16) +#define WRMEM1_270_FLD3 GENMASK(47, 32) +#define WRMEM1_270_FLD4 GENMASK(63, 48) +#define WRMEM1_270_FLD5 GENMASK(79, 64) +#define WRMEM1_270_FLD6 GENMASK(95, 80) +#define WRMEM1_270_FLD7 GENMASK(111, 96) +#define WRMEM1_270_FLD8 GENMASK(127, 112) + +/* WRMEM1_271 register fields */ +#define WRMEM1_271_FLD1 GENMASK(15, 0) +#define WRMEM1_271_FLD2 GENMASK(31, 16) +#define WRMEM1_271_FLD3 GENMASK(47, 32) +#define WRMEM1_271_FLD4 GENMASK(63, 48) +#define WRMEM1_271_FLD5 GENMASK(79, 64) +#define WRMEM1_271_FLD6 GENMASK(95, 80) +#define WRMEM1_271_FLD7 GENMASK(111, 96) +#define WRMEM1_271_FLD8 GENMASK(127, 112) + +/* WRMEM1_272 register fields */ +#define WRMEM1_272_FLD1 GENMASK(15, 0) +#define WRMEM1_272_FLD2 GENMASK(31, 16) +#define WRMEM1_272_FLD3 GENMASK(47, 32) +#define WRMEM1_272_FLD4 GENMASK(63, 48) +#define WRMEM1_272_FLD5 GENMASK(79, 64) +#define WRMEM1_272_FLD6 GENMASK(95, 80) +#define WRMEM1_272_FLD7 GENMASK(111, 96) +#define WRMEM1_272_FLD8 GENMASK(127, 112) + +/* WRMEM1_273 register fields */ +#define WRMEM1_273_FLD1 GENMASK(15, 0) +#define WRMEM1_273_FLD2 GENMASK(31, 16) +#define WRMEM1_273_FLD3 GENMASK(47, 32) +#define WRMEM1_273_FLD4 GENMASK(63, 48) +#define WRMEM1_273_FLD5 GENMASK(79, 64) +#define WRMEM1_273_FLD6 GENMASK(95, 80) +#define WRMEM1_273_FLD7 GENMASK(111, 96) +#define WRMEM1_273_FLD8 GENMASK(127, 112) + +/* WRMEM1_274 register fields */ +#define WRMEM1_274_FLD1 GENMASK(15, 0) +#define WRMEM1_274_FLD2 GENMASK(31, 16) +#define WRMEM1_274_FLD3 GENMASK(47, 32) +#define WRMEM1_274_FLD4 GENMASK(63, 48) +#define WRMEM1_274_FLD5 GENMASK(79, 64) +#define WRMEM1_274_FLD6 GENMASK(95, 80) +#define WRMEM1_274_FLD7 GENMASK(111, 96) +#define WRMEM1_274_FLD8 GENMASK(127, 112) + +/* WRMEM1_275 register fields */ +#define WRMEM1_275_FLD1 GENMASK(15, 0) +#define WRMEM1_275_FLD2 GENMASK(31, 16) +#define WRMEM1_275_FLD3 GENMASK(47, 32) +#define WRMEM1_275_FLD4 GENMASK(63, 48) +#define WRMEM1_275_FLD5 GENMASK(79, 64) +#define WRMEM1_275_FLD6 GENMASK(95, 80) +#define WRMEM1_275_FLD7 GENMASK(111, 96) +#define WRMEM1_275_FLD8 GENMASK(127, 112) + +/* WRMEM1_276 register fields */ +#define WRMEM1_276_FLD1 GENMASK(15, 0) +#define WRMEM1_276_FLD2 GENMASK(31, 16) +#define WRMEM1_276_FLD3 GENMASK(47, 32) +#define WRMEM1_276_FLD4 GENMASK(63, 48) +#define WRMEM1_276_FLD5 GENMASK(79, 64) +#define WRMEM1_276_FLD6 GENMASK(95, 80) +#define WRMEM1_276_FLD7 GENMASK(111, 96) +#define WRMEM1_276_FLD8 GENMASK(127, 112) + +/* WRMEM1_277 register fields */ +#define WRMEM1_277_FLD1 GENMASK(15, 0) +#define WRMEM1_277_FLD2 GENMASK(31, 16) +#define WRMEM1_277_FLD3 GENMASK(47, 32) +#define WRMEM1_277_FLD4 GENMASK(63, 48) +#define WRMEM1_277_FLD5 GENMASK(79, 64) +#define WRMEM1_277_FLD6 GENMASK(95, 80) +#define WRMEM1_277_FLD7 GENMASK(111, 96) +#define WRMEM1_277_FLD8 GENMASK(127, 112) + +/* WRMEM1_278 register fields */ +#define WRMEM1_278_FLD1 GENMASK(15, 0) +#define WRMEM1_278_FLD2 GENMASK(31, 16) +#define WRMEM1_278_FLD3 GENMASK(47, 32) +#define WRMEM1_278_FLD4 GENMASK(63, 48) +#define WRMEM1_278_FLD5 GENMASK(79, 64) +#define WRMEM1_278_FLD6 GENMASK(95, 80) +#define WRMEM1_278_FLD7 GENMASK(111, 96) +#define WRMEM1_278_FLD8 GENMASK(127, 112) + +/* WRMEM1_279 register fields */ +#define WRMEM1_279_FLD1 GENMASK(15, 0) +#define WRMEM1_279_FLD2 GENMASK(31, 16) +#define WRMEM1_279_FLD3 GENMASK(47, 32) +#define WRMEM1_279_FLD4 GENMASK(63, 48) +#define WRMEM1_279_FLD5 GENMASK(79, 64) +#define WRMEM1_279_FLD6 GENMASK(95, 80) +#define WRMEM1_279_FLD7 GENMASK(111, 96) +#define WRMEM1_279_FLD8 GENMASK(127, 112) + +/* WRMEM1_280 register fields */ +#define WRMEM1_280_FLD1 GENMASK(15, 0) +#define WRMEM1_280_FLD2 GENMASK(31, 16) +#define WRMEM1_280_FLD3 GENMASK(47, 32) +#define WRMEM1_280_FLD4 GENMASK(63, 48) +#define WRMEM1_280_FLD5 GENMASK(79, 64) +#define WRMEM1_280_FLD6 GENMASK(95, 80) +#define WRMEM1_280_FLD7 GENMASK(111, 96) +#define WRMEM1_280_FLD8 GENMASK(127, 112) + +/* WRMEM1_281 register fields */ +#define WRMEM1_281_FLD1 GENMASK(15, 0) +#define WRMEM1_281_FLD2 GENMASK(31, 16) +#define WRMEM1_281_FLD3 GENMASK(47, 32) +#define WRMEM1_281_FLD4 GENMASK(63, 48) +#define WRMEM1_281_FLD5 GENMASK(79, 64) +#define WRMEM1_281_FLD6 GENMASK(95, 80) +#define WRMEM1_281_FLD7 GENMASK(111, 96) +#define WRMEM1_281_FLD8 GENMASK(127, 112) + +/* WRMEM1_282 register fields */ +#define WRMEM1_282_FLD1 GENMASK(15, 0) +#define WRMEM1_282_FLD2 GENMASK(31, 16) +#define WRMEM1_282_FLD3 GENMASK(47, 32) +#define WRMEM1_282_FLD4 GENMASK(63, 48) +#define WRMEM1_282_FLD5 GENMASK(79, 64) +#define WRMEM1_282_FLD6 GENMASK(95, 80) +#define WRMEM1_282_FLD7 GENMASK(111, 96) +#define WRMEM1_282_FLD8 GENMASK(127, 112) + +/* WRMEM1_283 register fields */ +#define WRMEM1_283_FLD1 GENMASK(15, 0) +#define WRMEM1_283_FLD2 GENMASK(31, 16) +#define WRMEM1_283_FLD3 GENMASK(47, 32) +#define WRMEM1_283_FLD4 GENMASK(63, 48) +#define WRMEM1_283_FLD5 GENMASK(79, 64) +#define WRMEM1_283_FLD6 GENMASK(95, 80) +#define WRMEM1_283_FLD7 GENMASK(111, 96) +#define WRMEM1_283_FLD8 GENMASK(127, 112) + +/* WRMEM1_284 register fields */ +#define WRMEM1_284_FLD1 GENMASK(15, 0) +#define WRMEM1_284_FLD2 GENMASK(31, 16) +#define WRMEM1_284_FLD3 GENMASK(47, 32) +#define WRMEM1_284_FLD4 GENMASK(63, 48) +#define WRMEM1_284_FLD5 GENMASK(79, 64) +#define WRMEM1_284_FLD6 GENMASK(95, 80) +#define WRMEM1_284_FLD7 GENMASK(111, 96) +#define WRMEM1_284_FLD8 GENMASK(127, 112) + +/* WRMEM1_285 register fields */ +#define WRMEM1_285_FLD1 GENMASK(15, 0) +#define WRMEM1_285_FLD2 GENMASK(31, 16) +#define WRMEM1_285_FLD3 GENMASK(47, 32) +#define WRMEM1_285_FLD4 GENMASK(63, 48) +#define WRMEM1_285_FLD5 GENMASK(79, 64) +#define WRMEM1_285_FLD6 GENMASK(95, 80) +#define WRMEM1_285_FLD7 GENMASK(111, 96) +#define WRMEM1_285_FLD8 GENMASK(127, 112) + +/* WRMEM1_286 register fields */ +#define WRMEM1_286_FLD1 GENMASK(15, 0) +#define WRMEM1_286_FLD2 GENMASK(31, 16) +#define WRMEM1_286_FLD3 GENMASK(47, 32) +#define WRMEM1_286_FLD4 GENMASK(63, 48) +#define WRMEM1_286_FLD5 GENMASK(79, 64) +#define WRMEM1_286_FLD6 GENMASK(95, 80) +#define WRMEM1_286_FLD7 GENMASK(111, 96) +#define WRMEM1_286_FLD8 GENMASK(127, 112) + +/* WRMEM1_287 register fields */ +#define WRMEM1_287_FLD1 GENMASK(15, 0) +#define WRMEM1_287_FLD2 GENMASK(31, 16) +#define WRMEM1_287_FLD3 GENMASK(47, 32) +#define WRMEM1_287_FLD4 GENMASK(63, 48) +#define WRMEM1_287_FLD5 GENMASK(79, 64) +#define WRMEM1_287_FLD6 GENMASK(95, 80) +#define WRMEM1_287_FLD7 GENMASK(111, 96) +#define WRMEM1_287_FLD8 GENMASK(127, 112) + +/* WRMEM1_288 register fields */ +#define WRMEM1_288_FLD1 GENMASK(15, 0) +#define WRMEM1_288_FLD2 GENMASK(31, 16) +#define WRMEM1_288_FLD3 GENMASK(47, 32) +#define WRMEM1_288_FLD4 GENMASK(63, 48) +#define WRMEM1_288_FLD5 GENMASK(79, 64) +#define WRMEM1_288_FLD6 GENMASK(95, 80) +#define WRMEM1_288_FLD7 GENMASK(111, 96) +#define WRMEM1_288_FLD8 GENMASK(127, 112) + +/* WRMEM1_289 register fields */ +#define WRMEM1_289_FLD1 GENMASK(15, 0) +#define WRMEM1_289_FLD2 GENMASK(31, 16) +#define WRMEM1_289_FLD3 GENMASK(47, 32) +#define WRMEM1_289_FLD4 GENMASK(63, 48) +#define WRMEM1_289_FLD5 GENMASK(79, 64) +#define WRMEM1_289_FLD6 GENMASK(95, 80) +#define WRMEM1_289_FLD7 GENMASK(111, 96) +#define WRMEM1_289_FLD8 GENMASK(127, 112) + +/* WRMEM1_290 register fields */ +#define WRMEM1_290_FLD1 GENMASK(15, 0) +#define WRMEM1_290_FLD2 GENMASK(31, 16) +#define WRMEM1_290_FLD3 GENMASK(47, 32) +#define WRMEM1_290_FLD4 GENMASK(63, 48) +#define WRMEM1_290_FLD5 GENMASK(79, 64) +#define WRMEM1_290_FLD6 GENMASK(95, 80) +#define WRMEM1_290_FLD7 GENMASK(111, 96) +#define WRMEM1_290_FLD8 GENMASK(127, 112) + +/* WRMEM1_291 register fields */ +#define WRMEM1_291_FLD1 GENMASK(15, 0) +#define WRMEM1_291_FLD2 GENMASK(31, 16) +#define WRMEM1_291_FLD3 GENMASK(47, 32) +#define WRMEM1_291_FLD4 GENMASK(63, 48) +#define WRMEM1_291_FLD5 GENMASK(79, 64) +#define WRMEM1_291_FLD6 GENMASK(95, 80) +#define WRMEM1_291_FLD7 GENMASK(111, 96) +#define WRMEM1_291_FLD8 GENMASK(127, 112) + +/* WRMEM1_292 register fields */ +#define WRMEM1_292_FLD1 GENMASK(15, 0) +#define WRMEM1_292_FLD2 GENMASK(31, 16) +#define WRMEM1_292_FLD3 GENMASK(47, 32) +#define WRMEM1_292_FLD4 GENMASK(63, 48) +#define WRMEM1_292_FLD5 GENMASK(79, 64) +#define WRMEM1_292_FLD6 GENMASK(95, 80) +#define WRMEM1_292_FLD7 GENMASK(111, 96) +#define WRMEM1_292_FLD8 GENMASK(127, 112) + +/* WRMEM1_293 register fields */ +#define WRMEM1_293_FLD1 GENMASK(15, 0) +#define WRMEM1_293_FLD2 GENMASK(31, 16) +#define WRMEM1_293_FLD3 GENMASK(47, 32) +#define WRMEM1_293_FLD4 GENMASK(63, 48) +#define WRMEM1_293_FLD5 GENMASK(79, 64) +#define WRMEM1_293_FLD6 GENMASK(95, 80) +#define WRMEM1_293_FLD7 GENMASK(111, 96) +#define WRMEM1_293_FLD8 GENMASK(127, 112) + +/* WRMEM1_294 register fields */ +#define WRMEM1_294_FLD1 GENMASK(15, 0) +#define WRMEM1_294_FLD2 GENMASK(31, 16) +#define WRMEM1_294_FLD3 GENMASK(47, 32) +#define WRMEM1_294_FLD4 GENMASK(63, 48) +#define WRMEM1_294_FLD5 GENMASK(79, 64) +#define WRMEM1_294_FLD6 GENMASK(95, 80) +#define WRMEM1_294_FLD7 GENMASK(111, 96) +#define WRMEM1_294_FLD8 GENMASK(127, 112) + +/* WRMEM1_295 register fields */ +#define WRMEM1_295_FLD1 GENMASK(15, 0) +#define WRMEM1_295_FLD2 GENMASK(31, 16) +#define WRMEM1_295_FLD3 GENMASK(47, 32) +#define WRMEM1_295_FLD4 GENMASK(63, 48) +#define WRMEM1_295_FLD5 GENMASK(79, 64) +#define WRMEM1_295_FLD6 GENMASK(95, 80) +#define WRMEM1_295_FLD7 GENMASK(111, 96) +#define WRMEM1_295_FLD8 GENMASK(127, 112) + +/* WRMEM1_296 register fields */ +#define WRMEM1_296_FLD1 GENMASK(15, 0) +#define WRMEM1_296_FLD2 GENMASK(31, 16) +#define WRMEM1_296_FLD3 GENMASK(47, 32) +#define WRMEM1_296_FLD4 GENMASK(63, 48) +#define WRMEM1_296_FLD5 GENMASK(79, 64) +#define WRMEM1_296_FLD6 GENMASK(95, 80) +#define WRMEM1_296_FLD7 GENMASK(111, 96) +#define WRMEM1_296_FLD8 GENMASK(127, 112) + +/* WRMEM1_297 register fields */ +#define WRMEM1_297_FLD1 GENMASK(15, 0) +#define WRMEM1_297_FLD2 GENMASK(31, 16) +#define WRMEM1_297_FLD3 GENMASK(47, 32) +#define WRMEM1_297_FLD4 GENMASK(63, 48) +#define WRMEM1_297_FLD5 GENMASK(79, 64) +#define WRMEM1_297_FLD6 GENMASK(95, 80) +#define WRMEM1_297_FLD7 GENMASK(111, 96) +#define WRMEM1_297_FLD8 GENMASK(127, 112) + +/* WRMEM1_298 register fields */ +#define WRMEM1_298_FLD1 GENMASK(15, 0) +#define WRMEM1_298_FLD2 GENMASK(31, 16) +#define WRMEM1_298_FLD3 GENMASK(47, 32) +#define WRMEM1_298_FLD4 GENMASK(63, 48) +#define WRMEM1_298_FLD5 GENMASK(79, 64) +#define WRMEM1_298_FLD6 GENMASK(95, 80) +#define WRMEM1_298_FLD7 GENMASK(111, 96) +#define WRMEM1_298_FLD8 GENMASK(127, 112) + +/* WRMEM1_299 register fields */ +#define WRMEM1_299_FLD1 GENMASK(15, 0) +#define WRMEM1_299_FLD2 GENMASK(31, 16) +#define WRMEM1_299_FLD3 GENMASK(47, 32) +#define WRMEM1_299_FLD4 GENMASK(63, 48) +#define WRMEM1_299_FLD5 GENMASK(79, 64) +#define WRMEM1_299_FLD6 GENMASK(95, 80) +#define WRMEM1_299_FLD7 GENMASK(111, 96) +#define WRMEM1_299_FLD8 GENMASK(127, 112) + +#endif diff --git a/test/basic_tests/rdl_write_enable/golden/output.h b/test/basic_tests/rdl_write_enable/golden/output.h new file mode 100644 index 0000000..4151c87 --- /dev/null +++ b/test/basic_tests/rdl_write_enable/golden/output.h @@ -0,0 +1,63 @@ +// Ordt 230719.01 autogenerated file +// Input: ./rdl_write_enable/test.rdl +// Parms: ./rdl_write_enable/test.parms +// Date: Thu Jul 20 13:47:02 EDT 2023 +// + +#ifndef __FOO_REGISTER_MAP__ +#define __FOO_REGISTER_MAP__ + +#include + +/* FOO_REGISTERS memory map */ +enum FOO_REGS { + INTR_REG = 0x0, + LOG_REG = 0x4, + BIGREG = 0x8, + CHILDMAP_32B_ARRAY_REG_0 = 0x100, + CHILDMAP_32B_ARRAY_REG_1 = 0x104, + CHILDMAP_32B_ARRAY_REG_2 = 0x108, + CHILDMAP_32B_ARRAY_REG_3 = 0x10c, + CHILDMAP_32B_ARRAY_REG_4 = 0x110, + CHILDMAP_32B_ARRAY_REG_5 = 0x114, + CHILDMAP_32B_ARRAY_REG_6 = 0x118, + CHILDMAP_32B_ARRAY_REG_7 = 0x11c +}; + +/* INTR_REG register fields */ +#define INTR_REG_COUNT_FLD GENMASK(7, 0) +#define INTR_REG_INTR1 BIT(8) +#define INTR_REG_INTR2 BIT(9) + +/* LOG_REG register fields */ +#define LOG_REG_LOG_ERR GENMASK(7, 0) +#define LOG_REG_LOG_VALUE GENMASK(15, 8) + +/* BIGREG register fields */ +#define BIGREG_FIELD64 GENMASK(63, 0) + +/* CHILDMAP_32B_ARRAY_REG_0 register fields */ +#define CHILDMAP_32B_ARRAY_REG_0_FIELD32 GENMASK(31, 0) + +/* CHILDMAP_32B_ARRAY_REG_1 register fields */ +#define CHILDMAP_32B_ARRAY_REG_1_FIELD32 GENMASK(31, 0) + +/* CHILDMAP_32B_ARRAY_REG_2 register fields */ +#define CHILDMAP_32B_ARRAY_REG_2_FIELD32 GENMASK(31, 0) + +/* CHILDMAP_32B_ARRAY_REG_3 register fields */ +#define CHILDMAP_32B_ARRAY_REG_3_FIELD32 GENMASK(31, 0) + +/* CHILDMAP_32B_ARRAY_REG_4 register fields */ +#define CHILDMAP_32B_ARRAY_REG_4_FIELD32 GENMASK(31, 0) + +/* CHILDMAP_32B_ARRAY_REG_5 register fields */ +#define CHILDMAP_32B_ARRAY_REG_5_FIELD32 GENMASK(31, 0) + +/* CHILDMAP_32B_ARRAY_REG_6 register fields */ +#define CHILDMAP_32B_ARRAY_REG_6_FIELD32 GENMASK(31, 0) + +/* CHILDMAP_32B_ARRAY_REG_7 register fields */ +#define CHILDMAP_32B_ARRAY_REG_7_FIELD32 GENMASK(31, 0) + +#endif diff --git a/test/scripts/makeallgold b/test/scripts/makeallgold index f714de8..0f9bea3 100755 --- a/test/scripts/makeallgold +++ b/test/scripts/makeallgold @@ -79,6 +79,6 @@ for full_test_name in $tests_dir/*; do if [ -d $full_test_name ]; then test_name=`basename $full_test_name` #echo "-------- test=$test_name ..." - makegold $all_golden $clear_golden $v_golden $sv_golden $uvm_golden $rdl_golden $js_golden $reglist_golden $xml_golden $py_golden $cpp_golden $c_header_golden $test_name + makegold $all_golden $clear_golden $v_golden $sv_golden $uvm_golden $rdl_golden $js_golden $reglist_golden $xml_golden $py_golden $cpp_golden $c_header_golden $test_name fi done diff --git a/test/scripts/makegold b/test/scripts/makegold index db61d8c..902af68 100755 --- a/test/scripts/makegold +++ b/test/scripts/makegold @@ -46,7 +46,7 @@ while getopts "d:azvsurjlxcph" opt; do ;; c) cpp_golden=1 ;; - h) cpp_header_golden=1 + h) c_header_golden=1 ;; esac done