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microprocessor-verilog.qsf
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microprocessor-verilog.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2022 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
# Date created = 21:46:04 March 02, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Ass01_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:46:04 MARCH 02, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "DE1-SoC Board"
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ns" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME alu_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id alu_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME alu_tb -section_id alu_tb
set_global_assignment -name EDA_TEST_BENCH_NAME rom_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id rom_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME rom_tb -section_id rom_tb
set_global_assignment -name EDA_TEST_BENCH_NAME counter_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id counter_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME counter_tb -section_id counter_tb
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_NAME top_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id top_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb
set_global_assignment -name EDA_TEST_BENCH_NAME data_path_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id data_path_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME data_path_tb -section_id data_path_tb
set_global_assignment -name EDA_TEST_BENCH_FILE test/data_path_tb.v -section_id data_path_tb
set_global_assignment -name EDA_TEST_BENCH_FILE test/alu_tb.v -section_id alu_tb
set_global_assignment -name EDA_TEST_BENCH_FILE test/rom_tb.v -section_id rom_tb
set_global_assignment -name EDA_TEST_BENCH_FILE test/counter_tb.v -section_id counter_tb
set_global_assignment -name EDA_TEST_BENCH_FILE test/top_tb.v -section_id top_tb
set_global_assignment -name VERILOG_FILE src/top.v
set_global_assignment -name VERILOG_FILE src/rom.v
set_global_assignment -name VERILOG_FILE src/register.v
set_global_assignment -name VERILOG_FILE src/mux_2to1.v
set_global_assignment -name VERILOG_FILE src/decoder_2to4.v
set_global_assignment -name VERILOG_FILE src/data_path.v
set_global_assignment -name VERILOG_FILE src/counter.v
set_global_assignment -name VERILOG_FILE src/control_logic.v
set_global_assignment -name VERILOG_FILE src/alu.v
set_global_assignment -name VERILOG_FILE src/adder.v
set_global_assignment -name VERILOG_FILE test/top_tb.v
set_global_assignment -name VERILOG_FILE test/rom_tb.v
set_global_assignment -name VERILOG_FILE test/data_path_tb.v
set_global_assignment -name VERILOG_FILE test/counter_tb.v
set_global_assignment -name VERILOG_FILE test/alu_tb.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top