From c53aa32b7b64b7ebbb4fbf26445b03cb04c5223e Mon Sep 17 00:00:00 2001
From: Yu Chongbing <bd8ejk@foxmail.com>
Date: Wed, 9 Oct 2024 19:06:56 +0800
Subject: [PATCH] feat(smhc): add smhc peripheral pins and fix some issues.

+ Add smhc peripheral sdc0~2 pins in d1.rs.
+ Fix fmt and document annotations issues.

Signed-off-by: Yu Chongbing <bd8ejk@foxmail.com>
---
 src/ccu.rs      | 11 ++++-------
 src/gpio.rs     |  2 +-
 src/smhc.rs     |  8 ++++----
 src/wafer/d1.rs | 13 ++++++++++++-
 4 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/ccu.rs b/src/ccu.rs
index 88dc328..82a1aeb 100644
--- a/src/ccu.rs
+++ b/src/ccu.rs
@@ -813,17 +813,14 @@ impl ClockGate for DRAM {
     #[inline]
     unsafe fn reset(ccu: &ccu::RegisterBlock) {
         let dram_bgr = ccu.dram_bgr.read();
-        ccu.dram_bgr
-            .write(dram_bgr.gate_mask().assert_reset());
+        ccu.dram_bgr.write(dram_bgr.gate_mask().assert_reset());
         let dram_bgr = ccu.dram_bgr.read();
-        ccu.dram_bgr
-            .write(dram_bgr.gate_pass().deassert_reset());
+        ccu.dram_bgr.write(dram_bgr.gate_pass().deassert_reset());
     }
     #[inline]
     unsafe fn free(ccu: &ccu::RegisterBlock) {
         let dram_bgr = ccu.dram_bgr.read();
-        ccu.dram_bgr
-            .write(dram_bgr.gate_mask().assert_reset());
+        ccu.dram_bgr.write(dram_bgr.gate_mask().assert_reset());
     }
 }
 
@@ -842,7 +839,7 @@ impl ClockConfig for DRAM {
             dram_clk
                 .set_clock_source(source)
                 .set_factor_m(factor_m)
-                .set_factor_n(factor_n)
+                .set_factor_n(factor_n),
         )
     }
 }
diff --git a/src/gpio.rs b/src/gpio.rs
index 4fb62df..c5ec974 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -359,7 +359,7 @@ impl<'a, const P: char, const N: u8> Disabled<'a, P, N> {
         set_mode(self)
     }
 
-    // Internal constructor for ROM runtime. Do not use.
+    /// Internal constructor for ROM runtime. Do not use.
     #[doc(hidden)]
     #[inline(always)]
     pub const unsafe fn __new(gpio: &'a RegisterBlock) -> Self {
diff --git a/src/smhc.rs b/src/smhc.rs
index f24c5f4..e943a4a 100644
--- a/src/smhc.rs
+++ b/src/smhc.rs
@@ -63,18 +63,18 @@ pub struct GlobalControl(u32);
 /// FIFO access mode.
 #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum AccessMode {
-    // Dma bus.
+    /// Dma bus.
     Dma,
-    // Ahb bus.
+    /// Ahb bus.
     Ahb,
 }
 
 /// DDR mode.
 #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum DdrMode {
-    // SDR mode.
+    /// SDR mode.
     Sdr,
-    // DDR mode.
+    /// DDR mode.
     Ddr,
 }
 
diff --git a/src/wafer/d1.rs b/src/wafer/d1.rs
index 1d271c1..2e2bfa4 100644
--- a/src/wafer/d1.rs
+++ b/src/wafer/d1.rs
@@ -174,7 +174,18 @@ impl_pins_trait! {
     ('F', 3, 2): smhc::Cmd;
     ('F', 4, 2): smhc::Data<3>;
     ('F', 5, 2): smhc::Data<2>;
-    // TODO other SDC{0,1,2} pins. Please refer to Section 9.7.3.2 'GPIO Multiplex Function'.
+    ('G', 0, 2): smhc::Clk;
+    ('G', 1, 2): smhc::Cmd;
+    ('G', 2, 2): smhc::Data<0>;
+    ('G', 3, 2): smhc::Data<1>;
+    ('G', 4, 2): smhc::Data<2>;
+    ('G', 5, 2): smhc::Data<3>;
+    ('C', 2, 3): smhc::Clk;
+    ('C', 3, 3): smhc::Cmd;
+    ('C', 4, 3): smhc::Data<2>;
+    ('C', 5, 3): smhc::Data<1>;
+    ('C', 6, 3): smhc::Data<0>;
+    ('C', 7, 3): smhc::Data<3>;
 }
 
 /// Allwinner D1 interrupts.