Typos found #5
Comments
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Page 4-2, the code block, line 4, the comment should be '32 bits wide', not '5 bits wide' |
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Page 4-3, second paragraph of section 4.5, "misinterpretatio" |
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Page 4-12, the first paragraph lists what lines in the preceding code segment are doing what, all of them need to have 1 added to them, ie: "Line 1" becomes "Line 2", "Lines 5-7" becomes "Lines 6-8" |
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Also on 4-12, the last paragraph has "SystgemVerilog" |
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Page 4-15, first sentence has "insruction" |
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Page 4-16, in 4.13.1, the last sentence has "advqnced" |
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Page 4-17, second to last sentence has "sub-epressions" instead of "sub-expressions" |
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Page 5-4, in the Note, last paragraph, "beteen" should be "between" |
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Page 6-3, in the second paragraph all of the line numbers listed need to have 2 subtracted from them. |
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Page 6-13, in the second paragraph, line numbers 16, 17 and 18 should be 21, 22 and 23. |
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Page 6-16, paragraph before the exercise block, line 45 should be line 55 |
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Page 7-3, paragraph after the figure, "meaninful" should be "meaningful" |
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Page 7-6, the identifier "pc" is "rg_pc" in the example above. |
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Page 7-10, last paragraph, pop_o() is used but pop_O() is used in the following code examples. |
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Page 7-12, second paragraph, starts with "The the CPU", guessing it should be "Then the CPU" |
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7-13, Figure 7.2 and the two following paragraphs do not agree wrt mkBypassFIFOF and mkPipelineFIFOF |
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Page 6-15, second paragraph, "ˇ2" instead of "v2" |
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Page 10-3, second paragraph, "desribed" should be "described" |
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10-11, last paragraph, "mememory" should be "memory" |
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10-13, last paragraph, "imput" should be "input" |
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10-14, in the note, "value value", should only be one "value' |
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Page 11-2, 4th paragraph, "Unversal" should be "Universal" |
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Page 12-2, "(such as rdtime and rdcycle," should have a closing parenthesis. |
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Page 12-9, first bullet, "withoug" should be "without" |
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Page 13-11, first paragraph in 13.8.1, "thqt" instead of "that" |
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Page 16-6, second bullet, "enqueuethe" should be "enqueue the" |
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Page 16-32, paragraph after the bullets, "optizationw" should be "optimizations" |
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Page 17-8, section 17.5.2. The code example is mkPipelineFIFOF instead of mkBypassFIFOF |
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Page 18-2, second paragraph, "Trqnslation" should be "Translation" |
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Page 18-5, paragraph between the first two code examples, "It writes it output" should be "It writes its output" |
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Page 18-6, first paragraph in 18.3.2, "module module", extra module |
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Page 18-7, third paragraph, "mimicing" should be "mimicking" |
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Page 18-13, first paragraph, “mimicing” should be "mimicking" |
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Page 18-13, third paragraph "abtracted" should be "abstracted" |
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Appendix C-2, CReg is unbolded |
On page 3-2, when describing what the options are, just after the Verilog example, "-e" is listed twice, when the second should be "-o".
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