From 5cd0dbb81448e9bb2004c09ee3a908d31b4dfc07 Mon Sep 17 00:00:00 2001 From: Wilfried Chauveau Date: Tue, 7 Dec 2021 22:32:29 +0000 Subject: [PATCH] regenerate with svd2rust 0.20.0 --- src/adc/cs.rs | 28 ++++- src/adc/div.rs | 2 + src/adc/fcs.rs | 10 ++ src/adc/fifo.rs | 2 + src/adc/inte.rs | 7 +- src/adc/intf.rs | 7 +- src/adc/intr.rs | 4 +- src/adc/ints.rs | 4 +- src/adc/result.rs | 1 + src/busctrl/bus_priority.rs | 4 + src/busctrl/bus_priority_ack.rs | 5 +- src/busctrl/perfctr0.rs | 9 +- src/busctrl/perfctr1.rs | 9 +- src/busctrl/perfctr2.rs | 9 +- src/busctrl/perfctr3.rs | 9 +- src/busctrl/perfsel0.rs | 1 + src/busctrl/perfsel1.rs | 1 + src/busctrl/perfsel2.rs | 1 + src/busctrl/perfsel3.rs | 1 + src/clocks/clk_adc_ctrl.rs | 17 ++- src/clocks/clk_adc_div.rs | 1 + src/clocks/clk_gpout0_ctrl.rs | 18 ++- src/clocks/clk_gpout0_div.rs | 2 + src/clocks/clk_gpout1_ctrl.rs | 18 ++- src/clocks/clk_gpout1_div.rs | 2 + src/clocks/clk_gpout2_ctrl.rs | 18 ++- src/clocks/clk_gpout2_div.rs | 2 + src/clocks/clk_gpout3_ctrl.rs | 18 ++- src/clocks/clk_gpout3_div.rs | 2 + src/clocks/clk_peri_ctrl.rs | 3 + src/clocks/clk_ref_ctrl.rs | 2 + src/clocks/clk_ref_div.rs | 1 + src/clocks/clk_rtc_ctrl.rs | 17 ++- src/clocks/clk_rtc_div.rs | 2 + src/clocks/clk_sys_ctrl.rs | 2 + src/clocks/clk_sys_div.rs | 2 + src/clocks/clk_sys_resus_ctrl.rs | 10 +- src/clocks/clk_sys_resus_status.rs | 1 + src/clocks/clk_usb_ctrl.rs | 17 ++- src/clocks/clk_usb_div.rs | 1 + src/clocks/enabled0.rs | 32 ++++++ src/clocks/enabled1.rs | 15 +++ src/clocks/fc0_delay.rs | 1 + src/clocks/fc0_interval.rs | 1 + src/clocks/fc0_max_khz.rs | 1 + src/clocks/fc0_min_khz.rs | 1 + src/clocks/fc0_ref_khz.rs | 1 + src/clocks/fc0_result.rs | 2 + src/clocks/fc0_src.rs | 1 + src/clocks/fc0_status.rs | 8 ++ src/clocks/inte.rs | 1 + src/clocks/intf.rs | 1 + src/clocks/intr.rs | 1 + src/clocks/ints.rs | 1 + src/clocks/sleep_en0.rs | 32 ++++++ src/clocks/sleep_en1.rs | 15 +++ src/clocks/wake_en0.rs | 32 ++++++ src/clocks/wake_en1.rs | 15 +++ src/dma/ch/ch_al1_ctrl.rs | 112 +++++++++++++----- src/dma/ch/ch_al2_ctrl.rs | 112 +++++++++++++----- src/dma/ch/ch_al3_ctrl.rs | 112 +++++++++++++----- src/dma/ch/ch_ctrl_trig.rs | 112 +++++++++++++----- src/dma/ch0_dbg_ctdreq.rs | 1 + src/dma/ch10_dbg_ctdreq.rs | 1 + src/dma/ch11_dbg_ctdreq.rs | 1 + src/dma/ch1_dbg_ctdreq.rs | 1 + src/dma/ch2_dbg_ctdreq.rs | 1 + src/dma/ch3_dbg_ctdreq.rs | 1 + src/dma/ch4_dbg_ctdreq.rs | 1 + src/dma/ch5_dbg_ctdreq.rs | 1 + src/dma/ch6_dbg_ctdreq.rs | 1 + src/dma/ch7_dbg_ctdreq.rs | 1 + src/dma/ch8_dbg_ctdreq.rs | 1 + src/dma/ch9_dbg_ctdreq.rs | 1 + src/dma/chan_abort.rs | 9 +- src/dma/fifo_levels.rs | 3 + src/dma/inte0.rs | 1 + src/dma/inte1.rs | 1 + src/dma/intf0.rs | 1 + src/dma/intf1.rs | 1 + src/dma/intr.rs | 9 +- src/dma/ints0.rs | 7 +- src/dma/ints1.rs | 7 +- src/dma/multi_chan_trigger.rs | 1 + src/dma/n_channels.rs | 1 + src/dma/sniff_ctrl.rs | 14 ++- src/dma/timer0.rs | 2 + src/dma/timer1.rs | 2 + src/dma/timer2.rs | 2 + src/dma/timer3.rs | 2 + src/i2c0/ic_ack_general_call.rs | 1 + src/i2c0/ic_clr_activity.rs | 5 +- src/i2c0/ic_clr_gen_call.rs | 5 +- src/i2c0/ic_clr_intr.rs | 5 +- src/i2c0/ic_clr_rd_req.rs | 5 +- src/i2c0/ic_clr_restart_det.rs | 5 +- src/i2c0/ic_clr_rx_done.rs | 5 +- src/i2c0/ic_clr_rx_over.rs | 5 +- src/i2c0/ic_clr_rx_under.rs | 5 +- src/i2c0/ic_clr_start_det.rs | 5 +- src/i2c0/ic_clr_stop_det.rs | 5 +- src/i2c0/ic_clr_tx_abrt.rs | 5 +- src/i2c0/ic_clr_tx_over.rs | 5 +- src/i2c0/ic_comp_param_1.rs | 8 ++ src/i2c0/ic_comp_type.rs | 1 + src/i2c0/ic_comp_version.rs | 1 + src/i2c0/ic_con.rs | 86 +++++++++++--- src/i2c0/ic_data_cmd.rs | 67 +++++++++-- src/i2c0/ic_dma_cr.rs | 2 + src/i2c0/ic_dma_rdlr.rs | 9 +- src/i2c0/ic_dma_tdlr.rs | 9 +- src/i2c0/ic_enable.rs | 31 ++++- src/i2c0/ic_enable_status.rs | 39 ++++++- src/i2c0/ic_fs_scl_hcnt.rs | 17 ++- src/i2c0/ic_fs_scl_lcnt.rs | 21 +++- src/i2c0/ic_fs_spklen.rs | 1 + src/i2c0/ic_intr_mask.rs | 117 ++++++++++++++----- src/i2c0/ic_intr_stat.rs | 65 ++++++++--- src/i2c0/ic_raw_intr_stat.rs | 71 +++++++++--- src/i2c0/ic_rx_tl.rs | 9 +- src/i2c0/ic_rxflr.rs | 5 +- src/i2c0/ic_sar.rs | 17 ++- src/i2c0/ic_sda_hold.rs | 18 ++- src/i2c0/ic_sda_setup.rs | 1 + src/i2c0/ic_slv_data_nack_only.rs | 9 +- src/i2c0/ic_ss_scl_hcnt.rs | 21 +++- src/i2c0/ic_ss_scl_lcnt.rs | 17 ++- src/i2c0/ic_status.rs | 11 +- src/i2c0/ic_tar.rs | 11 +- src/i2c0/ic_tx_abrt_source.rs | 126 ++++++++++++++++++--- src/i2c0/ic_tx_tl.rs | 9 +- src/i2c0/ic_txflr.rs | 5 +- src/io_bank0/dormant_wake_inte.rs | 32 ++++++ src/io_bank0/dormant_wake_intf.rs | 32 ++++++ src/io_bank0/dormant_wake_ints.rs | 32 ++++++ src/io_bank0/gpio/gpio_ctrl.rs | 11 +- src/io_bank0/gpio/gpio_status.rs | 8 ++ src/io_bank0/intr.rs | 32 ++++++ src/io_bank0/proc0_inte.rs | 32 ++++++ src/io_bank0/proc0_intf.rs | 32 ++++++ src/io_bank0/proc0_ints.rs | 32 ++++++ src/io_bank0/proc1_inte.rs | 32 ++++++ src/io_bank0/proc1_intf.rs | 32 ++++++ src/io_bank0/proc1_ints.rs | 32 ++++++ src/io_qspi/dormant_wake_inte.rs | 24 ++++ src/io_qspi/dormant_wake_intf.rs | 24 ++++ src/io_qspi/dormant_wake_ints.rs | 24 ++++ src/io_qspi/gpio_qspi/gpio_ctrl.rs | 11 +- src/io_qspi/gpio_qspi/gpio_status.rs | 8 ++ src/io_qspi/intr.rs | 24 ++++ src/io_qspi/proc0_inte.rs | 24 ++++ src/io_qspi/proc0_intf.rs | 24 ++++ src/io_qspi/proc0_ints.rs | 24 ++++ src/io_qspi/proc1_inte.rs | 24 ++++ src/io_qspi/proc1_intf.rs | 24 ++++ src/io_qspi/proc1_ints.rs | 24 ++++ src/lib.rs | 85 +++++++++++++- src/pads_bank0/gpio.rs | 7 ++ src/pads_bank0/swclk.rs | 7 ++ src/pads_bank0/swd.rs | 7 ++ src/pads_bank0/voltage_select.rs | 1 + src/pads_qspi/gpio_qspi_sclk.rs | 7 ++ src/pads_qspi/gpio_qspi_sd0.rs | 7 ++ src/pads_qspi/gpio_qspi_sd1.rs | 7 ++ src/pads_qspi/gpio_qspi_sd2.rs | 7 ++ src/pads_qspi/gpio_qspi_sd3.rs | 7 ++ src/pads_qspi/gpio_qspi_ss.rs | 7 ++ src/pads_qspi/voltage_select.rs | 1 + src/pio0/ctrl.rs | 23 +++- src/pio0/dbg_cfginfo.rs | 7 +- src/pio0/fdebug.rs | 4 + src/pio0/flevel.rs | 8 ++ src/pio0/fstat.rs | 4 + src/pio0/intr.rs | 12 ++ src/pio0/irq.rs | 1 + src/pio0/sm/sm_addr.rs | 1 + src/pio0/sm/sm_clkdiv.rs | 8 +- src/pio0/sm/sm_execctrl.rs | 27 ++++- src/pio0/sm/sm_instr.rs | 1 + src/pio0/sm/sm_pinctrl.rs | 7 ++ src/pio0/sm/sm_shiftctrl.rs | 36 ++++-- src/pio0/sm_irq/irq_inte.rs | 12 ++ src/pio0/sm_irq/irq_intf.rs | 12 ++ src/pio0/sm_irq/irq_ints.rs | 12 ++ src/pll_sys/cs.rs | 11 +- src/pll_sys/fbdiv_int.rs | 1 + src/pll_sys/prim.rs | 2 + src/pll_sys/pwr.rs | 28 +++-- src/ppb/aircr.rs | 15 ++- src/ppb/ccr.rs | 2 + src/ppb/cpuid.rs | 14 ++- src/ppb/icsr.rs | 91 +++++++++++++-- src/ppb/mpu_ctrl.rs | 33 +++++- src/ppb/mpu_rasr.rs | 22 +++- src/ppb/mpu_rbar.rs | 23 +++- src/ppb/mpu_rnr.rs | 7 +- src/ppb/mpu_type.rs | 3 + src/ppb/nvic_icer.rs | 17 ++- src/ppb/nvic_icpr.rs | 17 ++- src/ppb/nvic_ipr0.rs | 4 + src/ppb/nvic_ipr1.rs | 4 + src/ppb/nvic_ipr2.rs | 4 + src/ppb/nvic_ipr3.rs | 4 + src/ppb/nvic_ipr4.rs | 4 + src/ppb/nvic_ipr5.rs | 4 + src/ppb/nvic_ipr6.rs | 4 + src/ppb/nvic_ipr7.rs | 4 + src/ppb/nvic_iser.rs | 17 ++- src/ppb/nvic_ispr.rs | 23 +++- src/ppb/scr.rs | 35 +++++- src/ppb/shcsr.rs | 1 + src/ppb/shpr2.rs | 1 + src/ppb/shpr3.rs | 2 + src/ppb/syst_calib.rs | 3 + src/ppb/syst_csr.rs | 30 ++++- src/ppb/syst_cvr.rs | 1 + src/ppb/syst_rvr.rs | 1 + src/ppb/vtor.rs | 1 + src/psm/done.rs | 17 +++ src/psm/frce_off.rs | 17 +++ src/psm/frce_on.rs | 17 +++ src/psm/wdsel.rs | 17 +++ src/pwm/ch/cc.rs | 2 + src/pwm/ch/csr.rs | 21 +++- src/pwm/ch/ctr.rs | 1 + src/pwm/ch/div.rs | 2 + src/pwm/ch/top.rs | 1 + src/pwm/en.rs | 8 ++ src/pwm/inte.rs | 8 ++ src/pwm/intf.rs | 8 ++ src/pwm/intr.rs | 8 ++ src/pwm/ints.rs | 8 ++ src/resets/reset.rs | 25 ++++ src/resets/reset_done.rs | 25 ++++ src/resets/wdsel.rs | 25 ++++ src/rosc/ctrl.rs | 28 ++++- src/rosc/div.rs | 13 ++- src/rosc/freqa.rs | 11 +- src/rosc/freqb.rs | 11 +- src/rosc/phase.rs | 30 +++-- src/rosc/randombit.rs | 1 + src/rosc/status.rs | 3 + src/rtc/clkdiv_m1.rs | 1 + src/rtc/ctrl.rs | 10 +- src/rtc/inte.rs | 1 + src/rtc/intf.rs | 1 + src/rtc/intr.rs | 1 + src/rtc/ints.rs | 1 + src/rtc/irq_setup_0.rs | 8 ++ src/rtc/irq_setup_1.rs | 8 ++ src/rtc/rtc_0.rs | 4 + src/rtc/rtc_1.rs | 3 + src/rtc/setup_0.rs | 3 + src/rtc/setup_1.rs | 4 + src/sio/div_csr.rs | 13 ++- src/sio/fifo_st.rs | 4 + src/sio/gpio_hi_in.rs | 1 + src/sio/gpio_hi_oe.rs | 13 ++- src/sio/gpio_hi_out.rs | 13 ++- src/sio/gpio_in.rs | 1 + src/sio/gpio_oe.rs | 13 ++- src/sio/gpio_out.rs | 13 ++- src/sio/interp0_accum0_add.rs | 1 + src/sio/interp0_accum1_add.rs | 1 + src/sio/interp0_ctrl_lane0.rs | 54 +++++++-- src/sio/interp0_ctrl_lane1.rs | 34 ++++-- src/sio/interp1_accum0_add.rs | 1 + src/sio/interp1_accum1_add.rs | 1 + src/sio/interp1_ctrl_lane0.rs | 48 ++++++-- src/sio/interp1_ctrl_lane1.rs | 34 ++++-- src/spi0/sspcpsr.rs | 1 + src/spi0/sspcr0.rs | 5 + src/spi0/sspcr1.rs | 4 + src/spi0/sspdmacr.rs | 2 + src/spi0/sspdr.rs | 1 + src/spi0/sspicr.rs | 2 + src/spi0/sspimsc.rs | 4 + src/spi0/sspmis.rs | 4 + src/spi0/ssppcellid0.rs | 1 + src/spi0/ssppcellid1.rs | 1 + src/spi0/ssppcellid2.rs | 1 + src/spi0/ssppcellid3.rs | 1 + src/spi0/sspperiphid0.rs | 1 + src/spi0/sspperiphid1.rs | 2 + src/spi0/sspperiphid2.rs | 2 + src/spi0/sspperiphid3.rs | 1 + src/spi0/sspris.rs | 4 + src/spi0/sspsr.rs | 5 + src/syscfg/dbgforce.rs | 8 ++ src/syscfg/mempowerdown.rs | 8 ++ src/syscfg/proc_config.rs | 20 +++- src/syscfg/proc_in_sync_bypass.rs | 1 + src/syscfg/proc_in_sync_bypass_hi.rs | 1 + src/sysinfo/chip_id.rs | 3 + src/sysinfo/platform.rs | 2 + src/tbman/platform.rs | 2 + src/timer/armed.rs | 1 + src/timer/dbgpause.rs | 2 + src/timer/inte.rs | 4 + src/timer/intf.rs | 4 + src/timer/intr.rs | 4 + src/timer/ints.rs | 4 + src/timer/pause.rs | 1 + src/uart0/uartcr.rs | 12 ++ src/uart0/uartdmacr.rs | 3 + src/uart0/uartdr.rs | 5 + src/uart0/uartfbrd.rs | 1 + src/uart0/uartfr.rs | 9 ++ src/uart0/uartibrd.rs | 1 + src/uart0/uarticr.rs | 11 ++ src/uart0/uartifls.rs | 2 + src/uart0/uartilpr.rs | 1 + src/uart0/uartimsc.rs | 11 ++ src/uart0/uartlcr_h.rs | 7 ++ src/uart0/uartmis.rs | 11 ++ src/uart0/uartpcellid0.rs | 1 + src/uart0/uartpcellid1.rs | 1 + src/uart0/uartpcellid2.rs | 1 + src/uart0/uartpcellid3.rs | 1 + src/uart0/uartperiphid0.rs | 1 + src/uart0/uartperiphid1.rs | 2 + src/uart0/uartperiphid2.rs | 2 + src/uart0/uartperiphid3.rs | 1 + src/uart0/uartris.rs | 11 ++ src/uart0/uartrsr.rs | 4 + src/usbctrl_dpram/ep_buffer_control.rs | 19 +++- src/usbctrl_dpram/ep_control.rs | 8 ++ src/usbctrl_dpram/setup_packet_high.rs | 2 + src/usbctrl_dpram/setup_packet_low.rs | 3 + src/usbctrl_regs/addr_endp.rs | 2 + src/usbctrl_regs/addr_endp1.rs | 4 + src/usbctrl_regs/addr_endp10.rs | 4 + src/usbctrl_regs/addr_endp11.rs | 4 + src/usbctrl_regs/addr_endp12.rs | 4 + src/usbctrl_regs/addr_endp13.rs | 4 + src/usbctrl_regs/addr_endp14.rs | 4 + src/usbctrl_regs/addr_endp15.rs | 4 + src/usbctrl_regs/addr_endp2.rs | 4 + src/usbctrl_regs/addr_endp3.rs | 4 + src/usbctrl_regs/addr_endp4.rs | 4 + src/usbctrl_regs/addr_endp5.rs | 4 + src/usbctrl_regs/addr_endp6.rs | 4 + src/usbctrl_regs/addr_endp7.rs | 4 + src/usbctrl_regs/addr_endp8.rs | 4 + src/usbctrl_regs/addr_endp9.rs | 4 + src/usbctrl_regs/buff_cpu_should_handle.rs | 32 ++++++ src/usbctrl_regs/buff_status.rs | 32 ++++++ src/usbctrl_regs/ep_abort.rs | 32 ++++++ src/usbctrl_regs/ep_abort_done.rs | 32 ++++++ src/usbctrl_regs/ep_stall_arm.rs | 2 + src/usbctrl_regs/ep_status_stall_nak.rs | 32 ++++++ src/usbctrl_regs/int_ep_ctrl.rs | 1 + src/usbctrl_regs/inte.rs | 20 ++++ src/usbctrl_regs/intf.rs | 20 ++++ src/usbctrl_regs/intr.rs | 20 ++++ src/usbctrl_regs/ints.rs | 20 ++++ src/usbctrl_regs/main_ctrl.rs | 3 + src/usbctrl_regs/nak_poll.rs | 2 + src/usbctrl_regs/sie_ctrl.rs | 24 ++++ src/usbctrl_regs/sie_status.rs | 58 +++++++++- src/usbctrl_regs/sof_rd.rs | 1 + src/usbctrl_regs/usb_muxing.rs | 4 + src/usbctrl_regs/usb_pwr.rs | 6 + src/usbctrl_regs/usbphy_direct.rs | 57 ++++++++-- src/usbctrl_regs/usbphy_direct_override.rs | 14 +++ src/usbctrl_regs/usbphy_trim.rs | 18 ++- src/vreg_and_chip_reset/bod.rs | 44 ++++++- src/vreg_and_chip_reset/chip_reset.rs | 12 +- src/vreg_and_chip_reset/vreg.rs | 45 ++++++-- src/watchdog/ctrl.rs | 6 + src/watchdog/reason.rs | 2 + src/watchdog/tick.rs | 4 + src/xip_ctrl/ctrl.rs | 43 ++++++- src/xip_ctrl/flush.rs | 13 ++- src/xip_ctrl/stat.rs | 11 +- src/xip_ctrl/stream_addr.rs | 9 +- src/xip_ctrl/stream_ctr.rs | 19 +++- src/xip_ssi/baudr.rs | 1 + src/xip_ssi/ctrlr0.rs | 23 +++- src/xip_ssi/ctrlr1.rs | 1 + src/xip_ssi/dmacr.rs | 2 + src/xip_ssi/dmardlr.rs | 1 + src/xip_ssi/dmatdlr.rs | 1 + src/xip_ssi/dr0.rs | 1 + src/xip_ssi/icr.rs | 1 + src/xip_ssi/idr.rs | 1 + src/xip_ssi/imr.rs | 6 + src/xip_ssi/isr.rs | 6 + src/xip_ssi/msticr.rs | 1 + src/xip_ssi/mwcr.rs | 3 + src/xip_ssi/risr.rs | 6 + src/xip_ssi/rx_sample_dly.rs | 1 + src/xip_ssi/rxflr.rs | 1 + src/xip_ssi/rxftlr.rs | 1 + src/xip_ssi/rxoicr.rs | 1 + src/xip_ssi/rxuicr.rs | 1 + src/xip_ssi/ser.rs | 9 +- src/xip_ssi/spi_ctrlr0.rs | 8 ++ src/xip_ssi/sr.rs | 7 ++ src/xip_ssi/ssi_version_id.rs | 1 + src/xip_ssi/ssienr.rs | 1 + src/xip_ssi/txd_drive_edge.rs | 1 + src/xip_ssi/txflr.rs | 1 + src/xip_ssi/txftlr.rs | 1 + src/xip_ssi/txoicr.rs | 1 + src/xosc/ctrl.rs | 10 +- src/xosc/startup.rs | 2 + src/xosc/status.rs | 4 + update.sh | 2 +- 409 files changed, 4281 insertions(+), 536 deletions(-) diff --git a/src/adc/cs.rs b/src/adc/cs.rs index d6ba0f1e0..d6056e492 100644 --- a/src/adc/cs.rs +++ b/src/adc/cs.rs @@ -40,6 +40,7 @@ impl From> for W { AINSEL will be updated after each conversion with the newly-selected channel."] pub struct RROBIN_R(crate::FieldReader); impl RROBIN_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RROBIN_R(crate::FieldReader::new(bits)) } @@ -69,6 +70,7 @@ impl<'a> RROBIN_W<'a> { #[doc = "Field `AINSEL` reader - Select analog mux input. Updated automatically in round-robin mode."] pub struct AINSEL_R(crate::FieldReader); impl AINSEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AINSEL_R(crate::FieldReader::new(bits)) } @@ -95,6 +97,7 @@ impl<'a> AINSEL_W<'a> { #[doc = "Field `ERR_STICKY` reader - Some past ADC conversion encountered an error. Write 1 to clear."] pub struct ERR_STICKY_R(crate::FieldReader); impl ERR_STICKY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERR_STICKY_R(crate::FieldReader::new(bits)) } @@ -131,6 +134,7 @@ impl<'a> ERR_STICKY_W<'a> { #[doc = "Field `ERR` reader - The most recent ADC conversion encountered an error; result is undefined or noisy."] pub struct ERR_R(crate::FieldReader); impl ERR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERR_R(crate::FieldReader::new(bits)) } @@ -146,6 +150,7 @@ impl core::ops::Deref for ERR_R { 0 whilst conversion in progress."] pub struct READY_R(crate::FieldReader); impl READY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { READY_R(crate::FieldReader::new(bits)) } @@ -160,6 +165,7 @@ impl core::ops::Deref for READY_R { #[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] pub struct START_MANY_R(crate::FieldReader); impl START_MANY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { START_MANY_R(crate::FieldReader::new(bits)) } @@ -196,6 +202,7 @@ impl<'a> START_MANY_W<'a> { #[doc = "Field `START_ONCE` reader - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] pub struct START_ONCE_R(crate::FieldReader); impl START_ONCE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { START_ONCE_R(crate::FieldReader::new(bits)) } @@ -232,6 +239,7 @@ impl<'a> START_ONCE_W<'a> { #[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."] pub struct TS_EN_R(crate::FieldReader); impl TS_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TS_EN_R(crate::FieldReader::new(bits)) } @@ -269,6 +277,7 @@ impl<'a> TS_EN_W<'a> { 1 - enabled. 0 - disabled."] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -304,7 +313,10 @@ impl<'a> EN_W<'a> { } } impl R { - #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] + #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel."] #[inline(always)] pub fn rrobin(&self) -> RROBIN_R { RROBIN_R::new(((self.bits >> 16) & 0x1f) as u8) @@ -324,7 +336,8 @@ impl R { pub fn err(&self) -> ERR_R { ERR_R::new(((self.bits >> 9) & 0x01) != 0) } - #[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."] + #[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. + 0 whilst conversion in progress."] #[inline(always)] pub fn ready(&self) -> READY_R { READY_R::new(((self.bits >> 8) & 0x01) != 0) @@ -344,14 +357,18 @@ impl R { pub fn ts_en(&self) -> TS_EN_R { TS_EN_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] + #[doc = "Bit 0 - Power on ADC and enable its clock. + 1 - enabled. 0 - disabled."] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] + #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel."] #[inline(always)] pub fn rrobin(&mut self) -> RROBIN_W { RROBIN_W { w: self } @@ -381,7 +398,8 @@ impl W { pub fn ts_en(&mut self) -> TS_EN_W { TS_EN_W { w: self } } - #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] + #[doc = "Bit 0 - Power on ADC and enable its clock. + 1 - enabled. 0 - disabled."] #[inline(always)] pub fn en(&mut self) -> EN_W { EN_W { w: self } diff --git a/src/adc/div.rs b/src/adc/div.rs index cee868732..e83604dac 100644 --- a/src/adc/div.rs +++ b/src/adc/div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer part of clock divisor."] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - Fractional part of clock divisor. First-order delta-sigma."] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/adc/fcs.rs b/src/adc/fcs.rs index 9ecb5cc9a..ed80e522c 100644 --- a/src/adc/fcs.rs +++ b/src/adc/fcs.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `THRESH` reader - DREQ/IRQ asserted when level >= threshold"] pub struct THRESH_R(crate::FieldReader); impl THRESH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { THRESH_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> THRESH_W<'a> { #[doc = "Field `LEVEL` reader - The number of conversion results currently waiting in the FIFO"] pub struct LEVEL_R(crate::FieldReader); impl LEVEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { LEVEL_R(crate::FieldReader::new(bits)) } @@ -77,6 +79,7 @@ impl core::ops::Deref for LEVEL_R { #[doc = "Field `OVER` reader - 1 if the FIFO has been overflowed. Write 1 to clear."] pub struct OVER_R(crate::FieldReader); impl OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVER_R(crate::FieldReader::new(bits)) } @@ -113,6 +116,7 @@ impl<'a> OVER_W<'a> { #[doc = "Field `UNDER` reader - 1 if the FIFO has been underflowed. Write 1 to clear."] pub struct UNDER_R(crate::FieldReader); impl UNDER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UNDER_R(crate::FieldReader::new(bits)) } @@ -149,6 +153,7 @@ impl<'a> UNDER_W<'a> { #[doc = "Field `FULL` reader - "] pub struct FULL_R(crate::FieldReader); impl FULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FULL_R(crate::FieldReader::new(bits)) } @@ -163,6 +168,7 @@ impl core::ops::Deref for FULL_R { #[doc = "Field `EMPTY` reader - "] pub struct EMPTY_R(crate::FieldReader); impl EMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EMPTY_R(crate::FieldReader::new(bits)) } @@ -177,6 +183,7 @@ impl core::ops::Deref for EMPTY_R { #[doc = "Field `DREQ_EN` reader - If 1: assert DMA requests when FIFO contains data"] pub struct DREQ_EN_R(crate::FieldReader); impl DREQ_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DREQ_EN_R(crate::FieldReader::new(bits)) } @@ -213,6 +220,7 @@ impl<'a> DREQ_EN_W<'a> { #[doc = "Field `ERR` reader - If 1: conversion error bit appears in the FIFO alongside the result"] pub struct ERR_R(crate::FieldReader); impl ERR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERR_R(crate::FieldReader::new(bits)) } @@ -249,6 +257,7 @@ impl<'a> ERR_W<'a> { #[doc = "Field `SHIFT` reader - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."] pub struct SHIFT_R(crate::FieldReader); impl SHIFT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SHIFT_R(crate::FieldReader::new(bits)) } @@ -285,6 +294,7 @@ impl<'a> SHIFT_W<'a> { #[doc = "Field `EN` reader - If 1: write result to the FIFO after each conversion."] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } diff --git a/src/adc/fifo.rs b/src/adc/fifo.rs index 5c3faff22..cb350f587 100644 --- a/src/adc/fifo.rs +++ b/src/adc/fifo.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted."] pub struct ERR_R(crate::FieldReader); impl ERR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERR_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for ERR_R { #[doc = "Field `VAL` reader - "] pub struct VAL_R(crate::FieldReader); impl VAL_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { VAL_R(crate::FieldReader::new(bits)) } diff --git a/src/adc/inte.rs b/src/adc/inte.rs index 0a2a89e2f..5a7e57a94 100644 --- a/src/adc/inte.rs +++ b/src/adc/inte.rs @@ -38,6 +38,7 @@ impl From> for W { This level can be programmed via the FCS_THRESH field."] pub struct FIFO_R(crate::FieldReader); impl FIFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FIFO_R(crate::FieldReader::new(bits)) } @@ -73,14 +74,16 @@ impl<'a> FIFO_W<'a> { } } impl R { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&self) -> FIFO_R { FIFO_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&mut self) -> FIFO_W { FIFO_W { w: self } diff --git a/src/adc/intf.rs b/src/adc/intf.rs index 2ea3641ed..084891310 100644 --- a/src/adc/intf.rs +++ b/src/adc/intf.rs @@ -38,6 +38,7 @@ impl From> for W { This level can be programmed via the FCS_THRESH field."] pub struct FIFO_R(crate::FieldReader); impl FIFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FIFO_R(crate::FieldReader::new(bits)) } @@ -73,14 +74,16 @@ impl<'a> FIFO_W<'a> { } } impl R { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&self) -> FIFO_R { FIFO_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&mut self) -> FIFO_W { FIFO_W { w: self } diff --git a/src/adc/intr.rs b/src/adc/intr.rs index 1e957a113..dbd030973 100644 --- a/src/adc/intr.rs +++ b/src/adc/intr.rs @@ -17,6 +17,7 @@ impl From> for R { This level can be programmed via the FCS_THRESH field."] pub struct FIFO_R(crate::FieldReader); impl FIFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FIFO_R(crate::FieldReader::new(bits)) } @@ -29,7 +30,8 @@ impl core::ops::Deref for FIFO_R { } } impl R { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&self) -> FIFO_R { FIFO_R::new((self.bits & 0x01) != 0) diff --git a/src/adc/ints.rs b/src/adc/ints.rs index 5767c4702..abf9c693e 100644 --- a/src/adc/ints.rs +++ b/src/adc/ints.rs @@ -17,6 +17,7 @@ impl From> for R { This level can be programmed via the FCS_THRESH field."] pub struct FIFO_R(crate::FieldReader); impl FIFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FIFO_R(crate::FieldReader::new(bits)) } @@ -29,7 +30,8 @@ impl core::ops::Deref for FIFO_R { } } impl R { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&self) -> FIFO_R { FIFO_R::new((self.bits & 0x01) != 0) diff --git a/src/adc/result.rs b/src/adc/result.rs index 5141d9cb2..7e16cfdcd 100644 --- a/src/adc/result.rs +++ b/src/adc/result.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RESULT` reader - "] pub struct RESULT_R(crate::FieldReader); impl RESULT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { RESULT_R(crate::FieldReader::new(bits)) } diff --git a/src/busctrl/bus_priority.rs b/src/busctrl/bus_priority.rs index 9a333d6a8..9c5326079 100644 --- a/src/busctrl/bus_priority.rs +++ b/src/busctrl/bus_priority.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DMA_W` reader - 0 - low priority, 1 - high priority"] pub struct DMA_W_R(crate::FieldReader); impl DMA_W_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DMA_W_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> DMA_W_W<'a> { #[doc = "Field `DMA_R` reader - 0 - low priority, 1 - high priority"] pub struct DMA_R_R(crate::FieldReader); impl DMA_R_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DMA_R_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> DMA_R_W<'a> { #[doc = "Field `PROC1` reader - 0 - low priority, 1 - high priority"] pub struct PROC1_R(crate::FieldReader); impl PROC1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> PROC1_W<'a> { #[doc = "Field `PROC0` reader - 0 - low priority, 1 - high priority"] pub struct PROC0_R(crate::FieldReader); impl PROC0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_R(crate::FieldReader::new(bits)) } diff --git a/src/busctrl/bus_priority_ack.rs b/src/busctrl/bus_priority_ack.rs index 20755eceb..577366a8c 100644 --- a/src/busctrl/bus_priority_ack.rs +++ b/src/busctrl/bus_priority_ack.rs @@ -18,6 +18,7 @@ impl From> for R { In normal circumstances this will happen almost immediately."] pub struct BUS_PRIORITY_ACK_R(crate::FieldReader); impl BUS_PRIORITY_ACK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUS_PRIORITY_ACK_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for BUS_PRIORITY_ACK_R { } } impl R { - #[doc = "Bit 0 - Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately."] + #[doc = "Bit 0 - Goes to 1 once all arbiters have registered the new global priority levels. + Arbiters update their local priority when servicing a new nonsequential access. + In normal circumstances this will happen almost immediately."] #[inline(always)] pub fn bus_priority_ack(&self) -> BUS_PRIORITY_ACK_R { BUS_PRIORITY_ACK_R::new((self.bits & 0x01) != 0) diff --git a/src/busctrl/perfctr0.rs b/src/busctrl/perfctr0.rs index c0d6d71d2..e5d82f785 100644 --- a/src/busctrl/perfctr0.rs +++ b/src/busctrl/perfctr0.rs @@ -39,6 +39,7 @@ impl From> for W { Write any value to clear. Select an event to count using PERFSEL0"] pub struct PERFCTR0_R(crate::FieldReader); impl PERFCTR0_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { PERFCTR0_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> PERFCTR0_W<'a> { } } impl R { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL0"] #[inline(always)] pub fn perfctr0(&self) -> PERFCTR0_R { PERFCTR0_R::new((self.bits & 0x00ff_ffff) as u32) } } impl W { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL0"] #[inline(always)] pub fn perfctr0(&mut self) -> PERFCTR0_W { PERFCTR0_W { w: self } diff --git a/src/busctrl/perfctr1.rs b/src/busctrl/perfctr1.rs index 76da4f123..266e60543 100644 --- a/src/busctrl/perfctr1.rs +++ b/src/busctrl/perfctr1.rs @@ -39,6 +39,7 @@ impl From> for W { Write any value to clear. Select an event to count using PERFSEL1"] pub struct PERFCTR1_R(crate::FieldReader); impl PERFCTR1_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { PERFCTR1_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> PERFCTR1_W<'a> { } } impl R { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL1"] #[inline(always)] pub fn perfctr1(&self) -> PERFCTR1_R { PERFCTR1_R::new((self.bits & 0x00ff_ffff) as u32) } } impl W { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL1"] #[inline(always)] pub fn perfctr1(&mut self) -> PERFCTR1_W { PERFCTR1_W { w: self } diff --git a/src/busctrl/perfctr2.rs b/src/busctrl/perfctr2.rs index 620c451fe..e4c890e57 100644 --- a/src/busctrl/perfctr2.rs +++ b/src/busctrl/perfctr2.rs @@ -39,6 +39,7 @@ impl From> for W { Write any value to clear. Select an event to count using PERFSEL2"] pub struct PERFCTR2_R(crate::FieldReader); impl PERFCTR2_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { PERFCTR2_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> PERFCTR2_W<'a> { } } impl R { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL2"] #[inline(always)] pub fn perfctr2(&self) -> PERFCTR2_R { PERFCTR2_R::new((self.bits & 0x00ff_ffff) as u32) } } impl W { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL2"] #[inline(always)] pub fn perfctr2(&mut self) -> PERFCTR2_W { PERFCTR2_W { w: self } diff --git a/src/busctrl/perfctr3.rs b/src/busctrl/perfctr3.rs index ca07ab1d3..39ea1606b 100644 --- a/src/busctrl/perfctr3.rs +++ b/src/busctrl/perfctr3.rs @@ -39,6 +39,7 @@ impl From> for W { Write any value to clear. Select an event to count using PERFSEL3"] pub struct PERFCTR3_R(crate::FieldReader); impl PERFCTR3_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { PERFCTR3_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> PERFCTR3_W<'a> { } } impl R { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL3"] #[inline(always)] pub fn perfctr3(&self) -> PERFCTR3_R { PERFCTR3_R::new((self.bits & 0x00ff_ffff) as u32) } } impl W { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL3"] #[inline(always)] pub fn perfctr3(&mut self) -> PERFCTR3_W { PERFCTR3_W { w: self } diff --git a/src/busctrl/perfsel0.rs b/src/busctrl/perfsel0.rs index 4dea4539a..2f188d88b 100644 --- a/src/busctrl/perfsel0.rs +++ b/src/busctrl/perfsel0.rs @@ -90,6 +90,7 @@ impl From for u8 { #[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] pub struct PERFSEL0_R(crate::FieldReader); impl PERFSEL0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PERFSEL0_R(crate::FieldReader::new(bits)) } diff --git a/src/busctrl/perfsel1.rs b/src/busctrl/perfsel1.rs index cc0406f44..4767c8925 100644 --- a/src/busctrl/perfsel1.rs +++ b/src/busctrl/perfsel1.rs @@ -90,6 +90,7 @@ impl From for u8 { #[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] pub struct PERFSEL1_R(crate::FieldReader); impl PERFSEL1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PERFSEL1_R(crate::FieldReader::new(bits)) } diff --git a/src/busctrl/perfsel2.rs b/src/busctrl/perfsel2.rs index 2c122c3ca..2cc7b4130 100644 --- a/src/busctrl/perfsel2.rs +++ b/src/busctrl/perfsel2.rs @@ -90,6 +90,7 @@ impl From for u8 { #[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] pub struct PERFSEL2_R(crate::FieldReader); impl PERFSEL2_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PERFSEL2_R(crate::FieldReader::new(bits)) } diff --git a/src/busctrl/perfsel3.rs b/src/busctrl/perfsel3.rs index 33e2e139b..fc5db12cf 100644 --- a/src/busctrl/perfsel3.rs +++ b/src/busctrl/perfsel3.rs @@ -90,6 +90,7 @@ impl From for u8 { #[doc = "Field `PERFSEL3` reader - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] pub struct PERFSEL3_R(crate::FieldReader); impl PERFSEL3_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PERFSEL3_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_adc_ctrl.rs b/src/clocks/clk_adc_ctrl.rs index f376a96a1..965e8616a 100644 --- a/src/clocks/clk_adc_ctrl.rs +++ b/src/clocks/clk_adc_ctrl.rs @@ -38,6 +38,7 @@ impl From> for W { This can be done at any time"] pub struct NUDGE_R(crate::FieldReader); impl NUDGE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NUDGE_R(crate::FieldReader::new(bits)) } @@ -76,6 +77,7 @@ impl<'a> NUDGE_W<'a> { This must be set before the clock is enabled to have any effect"] pub struct PHASE_R(crate::FieldReader); impl PHASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PHASE_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> PHASE_W<'a> { #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -139,6 +142,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub struct KILL_R(crate::FieldReader); impl KILL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KILL_R(crate::FieldReader::new(bits)) } @@ -200,6 +204,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -302,12 +307,14 @@ impl<'a> AUXSRC_W<'a> { } } impl R { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 0x01) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 0x03) as u8) @@ -329,12 +336,14 @@ impl R { } } impl W { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W { w: self } } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&mut self) -> PHASE_W { PHASE_W { w: self } diff --git a/src/clocks/clk_adc_div.rs b/src/clocks/clk_adc_div.rs index 0bbe8a3c3..b20465c53 100644 --- a/src/clocks/clk_adc_div.rs +++ b/src/clocks/clk_adc_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { INT_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_gpout0_ctrl.rs b/src/clocks/clk_gpout0_ctrl.rs index aa4ed3b51..1fe8b73f3 100644 --- a/src/clocks/clk_gpout0_ctrl.rs +++ b/src/clocks/clk_gpout0_ctrl.rs @@ -38,6 +38,7 @@ impl From> for W { This can be done at any time"] pub struct NUDGE_R(crate::FieldReader); impl NUDGE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NUDGE_R(crate::FieldReader::new(bits)) } @@ -76,6 +77,7 @@ impl<'a> NUDGE_W<'a> { This must be set before the clock is enabled to have any effect"] pub struct PHASE_R(crate::FieldReader); impl PHASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PHASE_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> PHASE_W<'a> { #[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"] pub struct DC50_R(crate::FieldReader); impl DC50_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DC50_R(crate::FieldReader::new(bits)) } @@ -139,6 +142,7 @@ impl<'a> DC50_W<'a> { #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -175,6 +179,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub struct KILL_R(crate::FieldReader); impl KILL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KILL_R(crate::FieldReader::new(bits)) } @@ -246,6 +251,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -403,12 +409,14 @@ impl<'a> AUXSRC_W<'a> { } } impl R { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 0x01) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 0x03) as u8) @@ -435,12 +443,14 @@ impl R { } } impl W { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W { w: self } } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&mut self) -> PHASE_W { PHASE_W { w: self } diff --git a/src/clocks/clk_gpout0_div.rs b/src/clocks/clk_gpout0_div.rs index 00c456c0e..c8458d78d 100644 --- a/src/clocks/clk_gpout0_div.rs +++ b/src/clocks/clk_gpout0_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_gpout1_ctrl.rs b/src/clocks/clk_gpout1_ctrl.rs index b59167e6d..2c1a2134a 100644 --- a/src/clocks/clk_gpout1_ctrl.rs +++ b/src/clocks/clk_gpout1_ctrl.rs @@ -38,6 +38,7 @@ impl From> for W { This can be done at any time"] pub struct NUDGE_R(crate::FieldReader); impl NUDGE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NUDGE_R(crate::FieldReader::new(bits)) } @@ -76,6 +77,7 @@ impl<'a> NUDGE_W<'a> { This must be set before the clock is enabled to have any effect"] pub struct PHASE_R(crate::FieldReader); impl PHASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PHASE_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> PHASE_W<'a> { #[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"] pub struct DC50_R(crate::FieldReader); impl DC50_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DC50_R(crate::FieldReader::new(bits)) } @@ -139,6 +142,7 @@ impl<'a> DC50_W<'a> { #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -175,6 +179,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub struct KILL_R(crate::FieldReader); impl KILL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KILL_R(crate::FieldReader::new(bits)) } @@ -246,6 +251,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -403,12 +409,14 @@ impl<'a> AUXSRC_W<'a> { } } impl R { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 0x01) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 0x03) as u8) @@ -435,12 +443,14 @@ impl R { } } impl W { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W { w: self } } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&mut self) -> PHASE_W { PHASE_W { w: self } diff --git a/src/clocks/clk_gpout1_div.rs b/src/clocks/clk_gpout1_div.rs index ceab243ef..c4986f07e 100644 --- a/src/clocks/clk_gpout1_div.rs +++ b/src/clocks/clk_gpout1_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_gpout2_ctrl.rs b/src/clocks/clk_gpout2_ctrl.rs index 66e3054f7..906b8bf7f 100644 --- a/src/clocks/clk_gpout2_ctrl.rs +++ b/src/clocks/clk_gpout2_ctrl.rs @@ -38,6 +38,7 @@ impl From> for W { This can be done at any time"] pub struct NUDGE_R(crate::FieldReader); impl NUDGE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NUDGE_R(crate::FieldReader::new(bits)) } @@ -76,6 +77,7 @@ impl<'a> NUDGE_W<'a> { This must be set before the clock is enabled to have any effect"] pub struct PHASE_R(crate::FieldReader); impl PHASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PHASE_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> PHASE_W<'a> { #[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"] pub struct DC50_R(crate::FieldReader); impl DC50_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DC50_R(crate::FieldReader::new(bits)) } @@ -139,6 +142,7 @@ impl<'a> DC50_W<'a> { #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -175,6 +179,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub struct KILL_R(crate::FieldReader); impl KILL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KILL_R(crate::FieldReader::new(bits)) } @@ -246,6 +251,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -403,12 +409,14 @@ impl<'a> AUXSRC_W<'a> { } } impl R { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 0x01) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 0x03) as u8) @@ -435,12 +443,14 @@ impl R { } } impl W { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W { w: self } } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&mut self) -> PHASE_W { PHASE_W { w: self } diff --git a/src/clocks/clk_gpout2_div.rs b/src/clocks/clk_gpout2_div.rs index 78608b969..99ab25673 100644 --- a/src/clocks/clk_gpout2_div.rs +++ b/src/clocks/clk_gpout2_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_gpout3_ctrl.rs b/src/clocks/clk_gpout3_ctrl.rs index b25b455e3..26584e1d5 100644 --- a/src/clocks/clk_gpout3_ctrl.rs +++ b/src/clocks/clk_gpout3_ctrl.rs @@ -38,6 +38,7 @@ impl From> for W { This can be done at any time"] pub struct NUDGE_R(crate::FieldReader); impl NUDGE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NUDGE_R(crate::FieldReader::new(bits)) } @@ -76,6 +77,7 @@ impl<'a> NUDGE_W<'a> { This must be set before the clock is enabled to have any effect"] pub struct PHASE_R(crate::FieldReader); impl PHASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PHASE_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> PHASE_W<'a> { #[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors"] pub struct DC50_R(crate::FieldReader); impl DC50_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DC50_R(crate::FieldReader::new(bits)) } @@ -139,6 +142,7 @@ impl<'a> DC50_W<'a> { #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -175,6 +179,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub struct KILL_R(crate::FieldReader); impl KILL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KILL_R(crate::FieldReader::new(bits)) } @@ -246,6 +251,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -403,12 +409,14 @@ impl<'a> AUXSRC_W<'a> { } } impl R { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 0x01) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 0x03) as u8) @@ -435,12 +443,14 @@ impl R { } } impl W { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W { w: self } } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&mut self) -> PHASE_W { PHASE_W { w: self } diff --git a/src/clocks/clk_gpout3_div.rs b/src/clocks/clk_gpout3_div.rs index 2f4f48d26..34b41c9d6 100644 --- a/src/clocks/clk_gpout3_div.rs +++ b/src/clocks/clk_gpout3_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_peri_ctrl.rs b/src/clocks/clk_peri_ctrl.rs index a881f7746..cf5d529aa 100644 --- a/src/clocks/clk_peri_ctrl.rs +++ b/src/clocks/clk_peri_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub struct KILL_R(crate::FieldReader); impl KILL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KILL_R(crate::FieldReader::new(bits)) } @@ -136,6 +138,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_ref_ctrl.rs b/src/clocks/clk_ref_ctrl.rs index 09a1210a8..55b827d9a 100644 --- a/src/clocks/clk_ref_ctrl.rs +++ b/src/clocks/clk_ref_ctrl.rs @@ -56,6 +56,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -146,6 +147,7 @@ impl From for u8 { #[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] pub struct SRC_R(crate::FieldReader); impl SRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SRC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_ref_div.rs b/src/clocks/clk_ref_div.rs index bc4c46a32..d30ac5d63 100644 --- a/src/clocks/clk_ref_div.rs +++ b/src/clocks/clk_ref_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { INT_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_rtc_ctrl.rs b/src/clocks/clk_rtc_ctrl.rs index b5a7ab4d0..b88a00f9e 100644 --- a/src/clocks/clk_rtc_ctrl.rs +++ b/src/clocks/clk_rtc_ctrl.rs @@ -38,6 +38,7 @@ impl From> for W { This can be done at any time"] pub struct NUDGE_R(crate::FieldReader); impl NUDGE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NUDGE_R(crate::FieldReader::new(bits)) } @@ -76,6 +77,7 @@ impl<'a> NUDGE_W<'a> { This must be set before the clock is enabled to have any effect"] pub struct PHASE_R(crate::FieldReader); impl PHASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PHASE_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> PHASE_W<'a> { #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -139,6 +142,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub struct KILL_R(crate::FieldReader); impl KILL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KILL_R(crate::FieldReader::new(bits)) } @@ -200,6 +204,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -302,12 +307,14 @@ impl<'a> AUXSRC_W<'a> { } } impl R { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 0x01) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 0x03) as u8) @@ -329,12 +336,14 @@ impl R { } } impl W { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W { w: self } } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&mut self) -> PHASE_W { PHASE_W { w: self } diff --git a/src/clocks/clk_rtc_div.rs b/src/clocks/clk_rtc_div.rs index e57d1d47a..df406cf26 100644 --- a/src/clocks/clk_rtc_div.rs +++ b/src/clocks/clk_rtc_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_sys_ctrl.rs b/src/clocks/clk_sys_ctrl.rs index 419a75890..2f5301404 100644 --- a/src/clocks/clk_sys_ctrl.rs +++ b/src/clocks/clk_sys_ctrl.rs @@ -62,6 +62,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -182,6 +183,7 @@ impl From for bool { #[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] pub struct SRC_R(crate::FieldReader); impl SRC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_sys_div.rs b/src/clocks/clk_sys_div.rs index d41b278b5..c97458c63 100644 --- a/src/clocks/clk_sys_div.rs +++ b/src/clocks/clk_sys_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - Fractional component of the divisor"] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_sys_resus_ctrl.rs b/src/clocks/clk_sys_resus_ctrl.rs index a3741e451..3e8a4c085 100644 --- a/src/clocks/clk_sys_resus_ctrl.rs +++ b/src/clocks/clk_sys_resus_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CLEAR` reader - For clearing the resus after the fault that triggered it has been corrected"] pub struct CLEAR_R(crate::FieldReader); impl CLEAR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLEAR_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CLEAR_W<'a> { #[doc = "Field `FRCE` reader - Force a resus, for test purposes only"] pub struct FRCE_R(crate::FieldReader); impl FRCE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FRCE_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> FRCE_W<'a> { #[doc = "Field `ENABLE` reader - Enable resus"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -146,6 +149,7 @@ impl<'a> ENABLE_W<'a> { and must be >= 2x clk_ref_freq/min_clk_tst_freq"] pub struct TIMEOUT_R(crate::FieldReader); impl TIMEOUT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TIMEOUT_R(crate::FieldReader::new(bits)) } @@ -186,7 +190,8 @@ impl R { pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 8) & 0x01) != 0) } - #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] + #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq"] #[inline(always)] pub fn timeout(&self) -> TIMEOUT_R { TIMEOUT_R::new((self.bits & 0xff) as u8) @@ -208,7 +213,8 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } } - #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] + #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq"] #[inline(always)] pub fn timeout(&mut self) -> TIMEOUT_W { TIMEOUT_W { w: self } diff --git a/src/clocks/clk_sys_resus_status.rs b/src/clocks/clk_sys_resus_status.rs index 3879ca050..989d17487 100644 --- a/src/clocks/clk_sys_resus_status.rs +++ b/src/clocks/clk_sys_resus_status.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RESUSSED` reader - Clock has been resuscitated, correct the error then send ctrl_clear=1"] pub struct RESUSSED_R(crate::FieldReader); impl RESUSSED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESUSSED_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/clk_usb_ctrl.rs b/src/clocks/clk_usb_ctrl.rs index 483d8d42f..59c1413eb 100644 --- a/src/clocks/clk_usb_ctrl.rs +++ b/src/clocks/clk_usb_ctrl.rs @@ -38,6 +38,7 @@ impl From> for W { This can be done at any time"] pub struct NUDGE_R(crate::FieldReader); impl NUDGE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NUDGE_R(crate::FieldReader::new(bits)) } @@ -76,6 +77,7 @@ impl<'a> NUDGE_W<'a> { This must be set before the clock is enabled to have any effect"] pub struct PHASE_R(crate::FieldReader); impl PHASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PHASE_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> PHASE_W<'a> { #[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -139,6 +142,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `KILL` reader - Asynchronously kills the clock generator"] pub struct KILL_R(crate::FieldReader); impl KILL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KILL_R(crate::FieldReader::new(bits)) } @@ -200,6 +204,7 @@ impl From for u8 { #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] pub struct AUXSRC_R(crate::FieldReader); impl AUXSRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { AUXSRC_R(crate::FieldReader::new(bits)) } @@ -302,12 +307,14 @@ impl<'a> AUXSRC_W<'a> { } } impl R { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 0x01) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 0x03) as u8) @@ -329,12 +336,14 @@ impl R { } } impl W { - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time"] #[inline(always)] pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W { w: self } } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&mut self) -> PHASE_W { PHASE_W { w: self } diff --git a/src/clocks/clk_usb_div.rs b/src/clocks/clk_usb_div.rs index f9d74983f..b5b1429c1 100644 --- a/src/clocks/clk_usb_div.rs +++ b/src/clocks/clk_usb_div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { INT_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/enabled0.rs b/src/clocks/enabled0.rs index 20b182b3b..f125bf506 100644 --- a/src/clocks/enabled0.rs +++ b/src/clocks/enabled0.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `clk_sys_sram3` reader - "] pub struct CLK_SYS_SRAM3_R(crate::FieldReader); impl CLK_SYS_SRAM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM3_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for CLK_SYS_SRAM3_R { #[doc = "Field `clk_sys_sram2` reader - "] pub struct CLK_SYS_SRAM2_R(crate::FieldReader); impl CLK_SYS_SRAM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM2_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for CLK_SYS_SRAM2_R { #[doc = "Field `clk_sys_sram1` reader - "] pub struct CLK_SYS_SRAM1_R(crate::FieldReader); impl CLK_SYS_SRAM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM1_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for CLK_SYS_SRAM1_R { #[doc = "Field `clk_sys_sram0` reader - "] pub struct CLK_SYS_SRAM0_R(crate::FieldReader); impl CLK_SYS_SRAM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM0_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for CLK_SYS_SRAM0_R { #[doc = "Field `clk_sys_spi1` reader - "] pub struct CLK_SYS_SPI1_R(crate::FieldReader); impl CLK_SYS_SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SPI1_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for CLK_SYS_SPI1_R { #[doc = "Field `clk_peri_spi1` reader - "] pub struct CLK_PERI_SPI1_R(crate::FieldReader); impl CLK_PERI_SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_SPI1_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for CLK_PERI_SPI1_R { #[doc = "Field `clk_sys_spi0` reader - "] pub struct CLK_SYS_SPI0_R(crate::FieldReader); impl CLK_SYS_SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SPI0_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for CLK_SYS_SPI0_R { #[doc = "Field `clk_peri_spi0` reader - "] pub struct CLK_PERI_SPI0_R(crate::FieldReader); impl CLK_PERI_SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_SPI0_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for CLK_PERI_SPI0_R { #[doc = "Field `clk_sys_sio` reader - "] pub struct CLK_SYS_SIO_R(crate::FieldReader); impl CLK_SYS_SIO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SIO_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for CLK_SYS_SIO_R { #[doc = "Field `clk_sys_rtc` reader - "] pub struct CLK_SYS_RTC_R(crate::FieldReader); impl CLK_SYS_RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RTC_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for CLK_SYS_RTC_R { #[doc = "Field `clk_rtc_rtc` reader - "] pub struct CLK_RTC_RTC_R(crate::FieldReader); impl CLK_RTC_RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_RTC_RTC_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for CLK_RTC_RTC_R { #[doc = "Field `clk_sys_rosc` reader - "] pub struct CLK_SYS_ROSC_R(crate::FieldReader); impl CLK_SYS_ROSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ROSC_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for CLK_SYS_ROSC_R { #[doc = "Field `clk_sys_rom` reader - "] pub struct CLK_SYS_ROM_R(crate::FieldReader); impl CLK_SYS_ROM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ROM_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for CLK_SYS_ROM_R { #[doc = "Field `clk_sys_resets` reader - "] pub struct CLK_SYS_RESETS_R(crate::FieldReader); impl CLK_SYS_RESETS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RESETS_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for CLK_SYS_RESETS_R { #[doc = "Field `clk_sys_pwm` reader - "] pub struct CLK_SYS_PWM_R(crate::FieldReader); impl CLK_SYS_PWM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PWM_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for CLK_SYS_PWM_R { #[doc = "Field `clk_sys_psm` reader - "] pub struct CLK_SYS_PSM_R(crate::FieldReader); impl CLK_SYS_PSM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PSM_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for CLK_SYS_PSM_R { #[doc = "Field `clk_sys_pll_usb` reader - "] pub struct CLK_SYS_PLL_USB_R(crate::FieldReader); impl CLK_SYS_PLL_USB_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PLL_USB_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for CLK_SYS_PLL_USB_R { #[doc = "Field `clk_sys_pll_sys` reader - "] pub struct CLK_SYS_PLL_SYS_R(crate::FieldReader); impl CLK_SYS_PLL_SYS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PLL_SYS_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for CLK_SYS_PLL_SYS_R { #[doc = "Field `clk_sys_pio1` reader - "] pub struct CLK_SYS_PIO1_R(crate::FieldReader); impl CLK_SYS_PIO1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PIO1_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for CLK_SYS_PIO1_R { #[doc = "Field `clk_sys_pio0` reader - "] pub struct CLK_SYS_PIO0_R(crate::FieldReader); impl CLK_SYS_PIO0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PIO0_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for CLK_SYS_PIO0_R { #[doc = "Field `clk_sys_pads` reader - "] pub struct CLK_SYS_PADS_R(crate::FieldReader); impl CLK_SYS_PADS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PADS_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for CLK_SYS_PADS_R { #[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "] pub struct CLK_SYS_VREG_AND_CHIP_RESET_R(crate::FieldReader); impl CLK_SYS_VREG_AND_CHIP_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_VREG_AND_CHIP_RESET_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for CLK_SYS_VREG_AND_CHIP_RESET_R { #[doc = "Field `clk_sys_jtag` reader - "] pub struct CLK_SYS_JTAG_R(crate::FieldReader); impl CLK_SYS_JTAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_JTAG_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for CLK_SYS_JTAG_R { #[doc = "Field `clk_sys_io` reader - "] pub struct CLK_SYS_IO_R(crate::FieldReader); impl CLK_SYS_IO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_IO_R(crate::FieldReader::new(bits)) } @@ -352,6 +376,7 @@ impl core::ops::Deref for CLK_SYS_IO_R { #[doc = "Field `clk_sys_i2c1` reader - "] pub struct CLK_SYS_I2C1_R(crate::FieldReader); impl CLK_SYS_I2C1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_I2C1_R(crate::FieldReader::new(bits)) } @@ -366,6 +391,7 @@ impl core::ops::Deref for CLK_SYS_I2C1_R { #[doc = "Field `clk_sys_i2c0` reader - "] pub struct CLK_SYS_I2C0_R(crate::FieldReader); impl CLK_SYS_I2C0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_I2C0_R(crate::FieldReader::new(bits)) } @@ -380,6 +406,7 @@ impl core::ops::Deref for CLK_SYS_I2C0_R { #[doc = "Field `clk_sys_dma` reader - "] pub struct CLK_SYS_DMA_R(crate::FieldReader); impl CLK_SYS_DMA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_DMA_R(crate::FieldReader::new(bits)) } @@ -394,6 +421,7 @@ impl core::ops::Deref for CLK_SYS_DMA_R { #[doc = "Field `clk_sys_busfabric` reader - "] pub struct CLK_SYS_BUSFABRIC_R(crate::FieldReader); impl CLK_SYS_BUSFABRIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_BUSFABRIC_R(crate::FieldReader::new(bits)) } @@ -408,6 +436,7 @@ impl core::ops::Deref for CLK_SYS_BUSFABRIC_R { #[doc = "Field `clk_sys_busctrl` reader - "] pub struct CLK_SYS_BUSCTRL_R(crate::FieldReader); impl CLK_SYS_BUSCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_BUSCTRL_R(crate::FieldReader::new(bits)) } @@ -422,6 +451,7 @@ impl core::ops::Deref for CLK_SYS_BUSCTRL_R { #[doc = "Field `clk_sys_adc` reader - "] pub struct CLK_SYS_ADC_R(crate::FieldReader); impl CLK_SYS_ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ADC_R(crate::FieldReader::new(bits)) } @@ -436,6 +466,7 @@ impl core::ops::Deref for CLK_SYS_ADC_R { #[doc = "Field `clk_adc_adc` reader - "] pub struct CLK_ADC_ADC_R(crate::FieldReader); impl CLK_ADC_ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_ADC_ADC_R(crate::FieldReader::new(bits)) } @@ -450,6 +481,7 @@ impl core::ops::Deref for CLK_ADC_ADC_R { #[doc = "Field `clk_sys_clocks` reader - "] pub struct CLK_SYS_CLOCKS_R(crate::FieldReader); impl CLK_SYS_CLOCKS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_CLOCKS_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/enabled1.rs b/src/clocks/enabled1.rs index f069f8c15..adec3bbd5 100644 --- a/src/clocks/enabled1.rs +++ b/src/clocks/enabled1.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `clk_sys_xosc` reader - "] pub struct CLK_SYS_XOSC_R(crate::FieldReader); impl CLK_SYS_XOSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_XOSC_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for CLK_SYS_XOSC_R { #[doc = "Field `clk_sys_xip` reader - "] pub struct CLK_SYS_XIP_R(crate::FieldReader); impl CLK_SYS_XIP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_XIP_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for CLK_SYS_XIP_R { #[doc = "Field `clk_sys_watchdog` reader - "] pub struct CLK_SYS_WATCHDOG_R(crate::FieldReader); impl CLK_SYS_WATCHDOG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_WATCHDOG_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for CLK_SYS_WATCHDOG_R { #[doc = "Field `clk_usb_usbctrl` reader - "] pub struct CLK_USB_USBCTRL_R(crate::FieldReader); impl CLK_USB_USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_USB_USBCTRL_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for CLK_USB_USBCTRL_R { #[doc = "Field `clk_sys_usbctrl` reader - "] pub struct CLK_SYS_USBCTRL_R(crate::FieldReader); impl CLK_SYS_USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_USBCTRL_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for CLK_SYS_USBCTRL_R { #[doc = "Field `clk_sys_uart1` reader - "] pub struct CLK_SYS_UART1_R(crate::FieldReader); impl CLK_SYS_UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_UART1_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for CLK_SYS_UART1_R { #[doc = "Field `clk_peri_uart1` reader - "] pub struct CLK_PERI_UART1_R(crate::FieldReader); impl CLK_PERI_UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_UART1_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for CLK_PERI_UART1_R { #[doc = "Field `clk_sys_uart0` reader - "] pub struct CLK_SYS_UART0_R(crate::FieldReader); impl CLK_SYS_UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_UART0_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for CLK_SYS_UART0_R { #[doc = "Field `clk_peri_uart0` reader - "] pub struct CLK_PERI_UART0_R(crate::FieldReader); impl CLK_PERI_UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_UART0_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for CLK_PERI_UART0_R { #[doc = "Field `clk_sys_timer` reader - "] pub struct CLK_SYS_TIMER_R(crate::FieldReader); impl CLK_SYS_TIMER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_TIMER_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for CLK_SYS_TIMER_R { #[doc = "Field `clk_sys_tbman` reader - "] pub struct CLK_SYS_TBMAN_R(crate::FieldReader); impl CLK_SYS_TBMAN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_TBMAN_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for CLK_SYS_TBMAN_R { #[doc = "Field `clk_sys_sysinfo` reader - "] pub struct CLK_SYS_SYSINFO_R(crate::FieldReader); impl CLK_SYS_SYSINFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SYSINFO_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for CLK_SYS_SYSINFO_R { #[doc = "Field `clk_sys_syscfg` reader - "] pub struct CLK_SYS_SYSCFG_R(crate::FieldReader); impl CLK_SYS_SYSCFG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SYSCFG_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for CLK_SYS_SYSCFG_R { #[doc = "Field `clk_sys_sram5` reader - "] pub struct CLK_SYS_SRAM5_R(crate::FieldReader); impl CLK_SYS_SRAM5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM5_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for CLK_SYS_SRAM5_R { #[doc = "Field `clk_sys_sram4` reader - "] pub struct CLK_SYS_SRAM4_R(crate::FieldReader); impl CLK_SYS_SRAM4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM4_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/fc0_delay.rs b/src/clocks/fc0_delay.rs index 8ad9812ea..91f2f4934 100644 --- a/src/clocks/fc0_delay.rs +++ b/src/clocks/fc0_delay.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `FC0_DELAY` reader - "] pub struct FC0_DELAY_R(crate::FieldReader); impl FC0_DELAY_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FC0_DELAY_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/fc0_interval.rs b/src/clocks/fc0_interval.rs index 90d57b715..d43ea6be9 100644 --- a/src/clocks/fc0_interval.rs +++ b/src/clocks/fc0_interval.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `FC0_INTERVAL` reader - "] pub struct FC0_INTERVAL_R(crate::FieldReader); impl FC0_INTERVAL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FC0_INTERVAL_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/fc0_max_khz.rs b/src/clocks/fc0_max_khz.rs index df25320db..e92ea5099 100644 --- a/src/clocks/fc0_max_khz.rs +++ b/src/clocks/fc0_max_khz.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `FC0_MAX_KHZ` reader - "] pub struct FC0_MAX_KHZ_R(crate::FieldReader); impl FC0_MAX_KHZ_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { FC0_MAX_KHZ_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/fc0_min_khz.rs b/src/clocks/fc0_min_khz.rs index 36f08f512..a7fdf42c2 100644 --- a/src/clocks/fc0_min_khz.rs +++ b/src/clocks/fc0_min_khz.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `FC0_MIN_KHZ` reader - "] pub struct FC0_MIN_KHZ_R(crate::FieldReader); impl FC0_MIN_KHZ_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { FC0_MIN_KHZ_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/fc0_ref_khz.rs b/src/clocks/fc0_ref_khz.rs index 29f9546d5..62bc008e1 100644 --- a/src/clocks/fc0_ref_khz.rs +++ b/src/clocks/fc0_ref_khz.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `FC0_REF_KHZ` reader - "] pub struct FC0_REF_KHZ_R(crate::FieldReader); impl FC0_REF_KHZ_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { FC0_REF_KHZ_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/fc0_result.rs b/src/clocks/fc0_result.rs index b99fde42a..dbaee8c17 100644 --- a/src/clocks/fc0_result.rs +++ b/src/clocks/fc0_result.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `KHZ` reader - "] pub struct KHZ_R(crate::FieldReader); impl KHZ_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { KHZ_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for KHZ_R { #[doc = "Field `FRAC` reader - "] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/fc0_src.rs b/src/clocks/fc0_src.rs index 4ba1fd3ed..c284b4cdb 100644 --- a/src/clocks/fc0_src.rs +++ b/src/clocks/fc0_src.rs @@ -78,6 +78,7 @@ impl From for u8 { #[doc = "Field `FC0_SRC` reader - "] pub struct FC0_SRC_R(crate::FieldReader); impl FC0_SRC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FC0_SRC_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/fc0_status.rs b/src/clocks/fc0_status.rs index 2dbf97953..4fc00a442 100644 --- a/src/clocks/fc0_status.rs +++ b/src/clocks/fc0_status.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `DIED` reader - Test clock stopped during test"] pub struct DIED_R(crate::FieldReader); impl DIED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DIED_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for DIED_R { #[doc = "Field `FAST` reader - Test clock faster than expected, only valid when status_done=1"] pub struct FAST_R(crate::FieldReader); impl FAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FAST_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for FAST_R { #[doc = "Field `SLOW` reader - Test clock slower than expected, only valid when status_done=1"] pub struct SLOW_R(crate::FieldReader); impl SLOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLOW_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for SLOW_R { #[doc = "Field `FAIL` reader - Test failed"] pub struct FAIL_R(crate::FieldReader); impl FAIL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FAIL_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for FAIL_R { #[doc = "Field `WAITING` reader - Waiting for test clock to start"] pub struct WAITING_R(crate::FieldReader); impl WAITING_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { WAITING_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for WAITING_R { #[doc = "Field `RUNNING` reader - Test running"] pub struct RUNNING_R(crate::FieldReader); impl RUNNING_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RUNNING_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for RUNNING_R { #[doc = "Field `DONE` reader - Test complete"] pub struct DONE_R(crate::FieldReader); impl DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DONE_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for DONE_R { #[doc = "Field `PASS` reader - Test passed"] pub struct PASS_R(crate::FieldReader); impl PASS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PASS_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/inte.rs b/src/clocks/inte.rs index e6bec2957..4f3c9cdcc 100644 --- a/src/clocks/inte.rs +++ b/src/clocks/inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CLK_SYS_RESUS` reader - "] pub struct CLK_SYS_RESUS_R(crate::FieldReader); impl CLK_SYS_RESUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RESUS_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/intf.rs b/src/clocks/intf.rs index 080a2989c..baab18767 100644 --- a/src/clocks/intf.rs +++ b/src/clocks/intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CLK_SYS_RESUS` reader - "] pub struct CLK_SYS_RESUS_R(crate::FieldReader); impl CLK_SYS_RESUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RESUS_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/intr.rs b/src/clocks/intr.rs index 7cc9dabbc..5d499e66d 100644 --- a/src/clocks/intr.rs +++ b/src/clocks/intr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `CLK_SYS_RESUS` reader - "] pub struct CLK_SYS_RESUS_R(crate::FieldReader); impl CLK_SYS_RESUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RESUS_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/ints.rs b/src/clocks/ints.rs index 701c1d542..3cb556bc1 100644 --- a/src/clocks/ints.rs +++ b/src/clocks/ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `CLK_SYS_RESUS` reader - "] pub struct CLK_SYS_RESUS_R(crate::FieldReader); impl CLK_SYS_RESUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RESUS_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/sleep_en0.rs b/src/clocks/sleep_en0.rs index e0f4dd8e9..d9f77f26e 100644 --- a/src/clocks/sleep_en0.rs +++ b/src/clocks/sleep_en0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `clk_sys_sram3` reader - "] pub struct CLK_SYS_SRAM3_R(crate::FieldReader); impl CLK_SYS_SRAM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM3_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CLK_SYS_SRAM3_W<'a> { #[doc = "Field `clk_sys_sram2` reader - "] pub struct CLK_SYS_SRAM2_R(crate::FieldReader); impl CLK_SYS_SRAM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM2_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> CLK_SYS_SRAM2_W<'a> { #[doc = "Field `clk_sys_sram1` reader - "] pub struct CLK_SYS_SRAM1_R(crate::FieldReader); impl CLK_SYS_SRAM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> CLK_SYS_SRAM1_W<'a> { #[doc = "Field `clk_sys_sram0` reader - "] pub struct CLK_SYS_SRAM0_R(crate::FieldReader); impl CLK_SYS_SRAM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM0_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> CLK_SYS_SRAM0_W<'a> { #[doc = "Field `clk_sys_spi1` reader - "] pub struct CLK_SYS_SPI1_R(crate::FieldReader); impl CLK_SYS_SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SPI1_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> CLK_SYS_SPI1_W<'a> { #[doc = "Field `clk_peri_spi1` reader - "] pub struct CLK_PERI_SPI1_R(crate::FieldReader); impl CLK_PERI_SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_SPI1_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> CLK_PERI_SPI1_W<'a> { #[doc = "Field `clk_sys_spi0` reader - "] pub struct CLK_SYS_SPI0_R(crate::FieldReader); impl CLK_SYS_SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SPI0_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> CLK_SYS_SPI0_W<'a> { #[doc = "Field `clk_peri_spi0` reader - "] pub struct CLK_PERI_SPI0_R(crate::FieldReader); impl CLK_PERI_SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_SPI0_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> CLK_PERI_SPI0_W<'a> { #[doc = "Field `clk_sys_sio` reader - "] pub struct CLK_SYS_SIO_R(crate::FieldReader); impl CLK_SYS_SIO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SIO_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> CLK_SYS_SIO_W<'a> { #[doc = "Field `clk_sys_rtc` reader - "] pub struct CLK_SYS_RTC_R(crate::FieldReader); impl CLK_SYS_RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RTC_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> CLK_SYS_RTC_W<'a> { #[doc = "Field `clk_rtc_rtc` reader - "] pub struct CLK_RTC_RTC_R(crate::FieldReader); impl CLK_RTC_RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_RTC_RTC_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> CLK_RTC_RTC_W<'a> { #[doc = "Field `clk_sys_rosc` reader - "] pub struct CLK_SYS_ROSC_R(crate::FieldReader); impl CLK_SYS_ROSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ROSC_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> CLK_SYS_ROSC_W<'a> { #[doc = "Field `clk_sys_rom` reader - "] pub struct CLK_SYS_ROM_R(crate::FieldReader); impl CLK_SYS_ROM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ROM_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> CLK_SYS_ROM_W<'a> { #[doc = "Field `clk_sys_resets` reader - "] pub struct CLK_SYS_RESETS_R(crate::FieldReader); impl CLK_SYS_RESETS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RESETS_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> CLK_SYS_RESETS_W<'a> { #[doc = "Field `clk_sys_pwm` reader - "] pub struct CLK_SYS_PWM_R(crate::FieldReader); impl CLK_SYS_PWM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PWM_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> CLK_SYS_PWM_W<'a> { #[doc = "Field `clk_sys_psm` reader - "] pub struct CLK_SYS_PSM_R(crate::FieldReader); impl CLK_SYS_PSM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PSM_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> CLK_SYS_PSM_W<'a> { #[doc = "Field `clk_sys_pll_usb` reader - "] pub struct CLK_SYS_PLL_USB_R(crate::FieldReader); impl CLK_SYS_PLL_USB_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PLL_USB_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> CLK_SYS_PLL_USB_W<'a> { #[doc = "Field `clk_sys_pll_sys` reader - "] pub struct CLK_SYS_PLL_SYS_R(crate::FieldReader); impl CLK_SYS_PLL_SYS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PLL_SYS_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> CLK_SYS_PLL_SYS_W<'a> { #[doc = "Field `clk_sys_pio1` reader - "] pub struct CLK_SYS_PIO1_R(crate::FieldReader); impl CLK_SYS_PIO1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PIO1_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> CLK_SYS_PIO1_W<'a> { #[doc = "Field `clk_sys_pio0` reader - "] pub struct CLK_SYS_PIO0_R(crate::FieldReader); impl CLK_SYS_PIO0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PIO0_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> CLK_SYS_PIO0_W<'a> { #[doc = "Field `clk_sys_pads` reader - "] pub struct CLK_SYS_PADS_R(crate::FieldReader); impl CLK_SYS_PADS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PADS_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> CLK_SYS_PADS_W<'a> { #[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "] pub struct CLK_SYS_VREG_AND_CHIP_RESET_R(crate::FieldReader); impl CLK_SYS_VREG_AND_CHIP_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_VREG_AND_CHIP_RESET_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> CLK_SYS_VREG_AND_CHIP_RESET_W<'a> { #[doc = "Field `clk_sys_jtag` reader - "] pub struct CLK_SYS_JTAG_R(crate::FieldReader); impl CLK_SYS_JTAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_JTAG_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> CLK_SYS_JTAG_W<'a> { #[doc = "Field `clk_sys_io` reader - "] pub struct CLK_SYS_IO_R(crate::FieldReader); impl CLK_SYS_IO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_IO_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> CLK_SYS_IO_W<'a> { #[doc = "Field `clk_sys_i2c1` reader - "] pub struct CLK_SYS_I2C1_R(crate::FieldReader); impl CLK_SYS_I2C1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_I2C1_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> CLK_SYS_I2C1_W<'a> { #[doc = "Field `clk_sys_i2c0` reader - "] pub struct CLK_SYS_I2C0_R(crate::FieldReader); impl CLK_SYS_I2C0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_I2C0_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> CLK_SYS_I2C0_W<'a> { #[doc = "Field `clk_sys_dma` reader - "] pub struct CLK_SYS_DMA_R(crate::FieldReader); impl CLK_SYS_DMA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_DMA_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> CLK_SYS_DMA_W<'a> { #[doc = "Field `clk_sys_busfabric` reader - "] pub struct CLK_SYS_BUSFABRIC_R(crate::FieldReader); impl CLK_SYS_BUSFABRIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_BUSFABRIC_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> CLK_SYS_BUSFABRIC_W<'a> { #[doc = "Field `clk_sys_busctrl` reader - "] pub struct CLK_SYS_BUSCTRL_R(crate::FieldReader); impl CLK_SYS_BUSCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_BUSCTRL_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> CLK_SYS_BUSCTRL_W<'a> { #[doc = "Field `clk_sys_adc` reader - "] pub struct CLK_SYS_ADC_R(crate::FieldReader); impl CLK_SYS_ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ADC_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> CLK_SYS_ADC_W<'a> { #[doc = "Field `clk_adc_adc` reader - "] pub struct CLK_ADC_ADC_R(crate::FieldReader); impl CLK_ADC_ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_ADC_ADC_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> CLK_ADC_ADC_W<'a> { #[doc = "Field `clk_sys_clocks` reader - "] pub struct CLK_SYS_CLOCKS_R(crate::FieldReader); impl CLK_SYS_CLOCKS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_CLOCKS_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/sleep_en1.rs b/src/clocks/sleep_en1.rs index e1e3c664f..a68341e04 100644 --- a/src/clocks/sleep_en1.rs +++ b/src/clocks/sleep_en1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `clk_sys_xosc` reader - "] pub struct CLK_SYS_XOSC_R(crate::FieldReader); impl CLK_SYS_XOSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_XOSC_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CLK_SYS_XOSC_W<'a> { #[doc = "Field `clk_sys_xip` reader - "] pub struct CLK_SYS_XIP_R(crate::FieldReader); impl CLK_SYS_XIP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_XIP_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> CLK_SYS_XIP_W<'a> { #[doc = "Field `clk_sys_watchdog` reader - "] pub struct CLK_SYS_WATCHDOG_R(crate::FieldReader); impl CLK_SYS_WATCHDOG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_WATCHDOG_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> CLK_SYS_WATCHDOG_W<'a> { #[doc = "Field `clk_usb_usbctrl` reader - "] pub struct CLK_USB_USBCTRL_R(crate::FieldReader); impl CLK_USB_USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_USB_USBCTRL_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> CLK_USB_USBCTRL_W<'a> { #[doc = "Field `clk_sys_usbctrl` reader - "] pub struct CLK_SYS_USBCTRL_R(crate::FieldReader); impl CLK_SYS_USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_USBCTRL_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> CLK_SYS_USBCTRL_W<'a> { #[doc = "Field `clk_sys_uart1` reader - "] pub struct CLK_SYS_UART1_R(crate::FieldReader); impl CLK_SYS_UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_UART1_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> CLK_SYS_UART1_W<'a> { #[doc = "Field `clk_peri_uart1` reader - "] pub struct CLK_PERI_UART1_R(crate::FieldReader); impl CLK_PERI_UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_UART1_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> CLK_PERI_UART1_W<'a> { #[doc = "Field `clk_sys_uart0` reader - "] pub struct CLK_SYS_UART0_R(crate::FieldReader); impl CLK_SYS_UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_UART0_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> CLK_SYS_UART0_W<'a> { #[doc = "Field `clk_peri_uart0` reader - "] pub struct CLK_PERI_UART0_R(crate::FieldReader); impl CLK_PERI_UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_UART0_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> CLK_PERI_UART0_W<'a> { #[doc = "Field `clk_sys_timer` reader - "] pub struct CLK_SYS_TIMER_R(crate::FieldReader); impl CLK_SYS_TIMER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_TIMER_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> CLK_SYS_TIMER_W<'a> { #[doc = "Field `clk_sys_tbman` reader - "] pub struct CLK_SYS_TBMAN_R(crate::FieldReader); impl CLK_SYS_TBMAN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_TBMAN_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> CLK_SYS_TBMAN_W<'a> { #[doc = "Field `clk_sys_sysinfo` reader - "] pub struct CLK_SYS_SYSINFO_R(crate::FieldReader); impl CLK_SYS_SYSINFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SYSINFO_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> CLK_SYS_SYSINFO_W<'a> { #[doc = "Field `clk_sys_syscfg` reader - "] pub struct CLK_SYS_SYSCFG_R(crate::FieldReader); impl CLK_SYS_SYSCFG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SYSCFG_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> CLK_SYS_SYSCFG_W<'a> { #[doc = "Field `clk_sys_sram5` reader - "] pub struct CLK_SYS_SRAM5_R(crate::FieldReader); impl CLK_SYS_SRAM5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM5_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> CLK_SYS_SRAM5_W<'a> { #[doc = "Field `clk_sys_sram4` reader - "] pub struct CLK_SYS_SRAM4_R(crate::FieldReader); impl CLK_SYS_SRAM4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM4_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/wake_en0.rs b/src/clocks/wake_en0.rs index d315ac621..1ba2914b0 100644 --- a/src/clocks/wake_en0.rs +++ b/src/clocks/wake_en0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `clk_sys_sram3` reader - "] pub struct CLK_SYS_SRAM3_R(crate::FieldReader); impl CLK_SYS_SRAM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM3_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CLK_SYS_SRAM3_W<'a> { #[doc = "Field `clk_sys_sram2` reader - "] pub struct CLK_SYS_SRAM2_R(crate::FieldReader); impl CLK_SYS_SRAM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM2_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> CLK_SYS_SRAM2_W<'a> { #[doc = "Field `clk_sys_sram1` reader - "] pub struct CLK_SYS_SRAM1_R(crate::FieldReader); impl CLK_SYS_SRAM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> CLK_SYS_SRAM1_W<'a> { #[doc = "Field `clk_sys_sram0` reader - "] pub struct CLK_SYS_SRAM0_R(crate::FieldReader); impl CLK_SYS_SRAM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM0_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> CLK_SYS_SRAM0_W<'a> { #[doc = "Field `clk_sys_spi1` reader - "] pub struct CLK_SYS_SPI1_R(crate::FieldReader); impl CLK_SYS_SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SPI1_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> CLK_SYS_SPI1_W<'a> { #[doc = "Field `clk_peri_spi1` reader - "] pub struct CLK_PERI_SPI1_R(crate::FieldReader); impl CLK_PERI_SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_SPI1_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> CLK_PERI_SPI1_W<'a> { #[doc = "Field `clk_sys_spi0` reader - "] pub struct CLK_SYS_SPI0_R(crate::FieldReader); impl CLK_SYS_SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SPI0_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> CLK_SYS_SPI0_W<'a> { #[doc = "Field `clk_peri_spi0` reader - "] pub struct CLK_PERI_SPI0_R(crate::FieldReader); impl CLK_PERI_SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_SPI0_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> CLK_PERI_SPI0_W<'a> { #[doc = "Field `clk_sys_sio` reader - "] pub struct CLK_SYS_SIO_R(crate::FieldReader); impl CLK_SYS_SIO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SIO_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> CLK_SYS_SIO_W<'a> { #[doc = "Field `clk_sys_rtc` reader - "] pub struct CLK_SYS_RTC_R(crate::FieldReader); impl CLK_SYS_RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RTC_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> CLK_SYS_RTC_W<'a> { #[doc = "Field `clk_rtc_rtc` reader - "] pub struct CLK_RTC_RTC_R(crate::FieldReader); impl CLK_RTC_RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_RTC_RTC_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> CLK_RTC_RTC_W<'a> { #[doc = "Field `clk_sys_rosc` reader - "] pub struct CLK_SYS_ROSC_R(crate::FieldReader); impl CLK_SYS_ROSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ROSC_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> CLK_SYS_ROSC_W<'a> { #[doc = "Field `clk_sys_rom` reader - "] pub struct CLK_SYS_ROM_R(crate::FieldReader); impl CLK_SYS_ROM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ROM_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> CLK_SYS_ROM_W<'a> { #[doc = "Field `clk_sys_resets` reader - "] pub struct CLK_SYS_RESETS_R(crate::FieldReader); impl CLK_SYS_RESETS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_RESETS_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> CLK_SYS_RESETS_W<'a> { #[doc = "Field `clk_sys_pwm` reader - "] pub struct CLK_SYS_PWM_R(crate::FieldReader); impl CLK_SYS_PWM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PWM_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> CLK_SYS_PWM_W<'a> { #[doc = "Field `clk_sys_psm` reader - "] pub struct CLK_SYS_PSM_R(crate::FieldReader); impl CLK_SYS_PSM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PSM_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> CLK_SYS_PSM_W<'a> { #[doc = "Field `clk_sys_pll_usb` reader - "] pub struct CLK_SYS_PLL_USB_R(crate::FieldReader); impl CLK_SYS_PLL_USB_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PLL_USB_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> CLK_SYS_PLL_USB_W<'a> { #[doc = "Field `clk_sys_pll_sys` reader - "] pub struct CLK_SYS_PLL_SYS_R(crate::FieldReader); impl CLK_SYS_PLL_SYS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PLL_SYS_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> CLK_SYS_PLL_SYS_W<'a> { #[doc = "Field `clk_sys_pio1` reader - "] pub struct CLK_SYS_PIO1_R(crate::FieldReader); impl CLK_SYS_PIO1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PIO1_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> CLK_SYS_PIO1_W<'a> { #[doc = "Field `clk_sys_pio0` reader - "] pub struct CLK_SYS_PIO0_R(crate::FieldReader); impl CLK_SYS_PIO0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PIO0_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> CLK_SYS_PIO0_W<'a> { #[doc = "Field `clk_sys_pads` reader - "] pub struct CLK_SYS_PADS_R(crate::FieldReader); impl CLK_SYS_PADS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_PADS_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> CLK_SYS_PADS_W<'a> { #[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "] pub struct CLK_SYS_VREG_AND_CHIP_RESET_R(crate::FieldReader); impl CLK_SYS_VREG_AND_CHIP_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_VREG_AND_CHIP_RESET_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> CLK_SYS_VREG_AND_CHIP_RESET_W<'a> { #[doc = "Field `clk_sys_jtag` reader - "] pub struct CLK_SYS_JTAG_R(crate::FieldReader); impl CLK_SYS_JTAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_JTAG_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> CLK_SYS_JTAG_W<'a> { #[doc = "Field `clk_sys_io` reader - "] pub struct CLK_SYS_IO_R(crate::FieldReader); impl CLK_SYS_IO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_IO_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> CLK_SYS_IO_W<'a> { #[doc = "Field `clk_sys_i2c1` reader - "] pub struct CLK_SYS_I2C1_R(crate::FieldReader); impl CLK_SYS_I2C1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_I2C1_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> CLK_SYS_I2C1_W<'a> { #[doc = "Field `clk_sys_i2c0` reader - "] pub struct CLK_SYS_I2C0_R(crate::FieldReader); impl CLK_SYS_I2C0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_I2C0_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> CLK_SYS_I2C0_W<'a> { #[doc = "Field `clk_sys_dma` reader - "] pub struct CLK_SYS_DMA_R(crate::FieldReader); impl CLK_SYS_DMA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_DMA_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> CLK_SYS_DMA_W<'a> { #[doc = "Field `clk_sys_busfabric` reader - "] pub struct CLK_SYS_BUSFABRIC_R(crate::FieldReader); impl CLK_SYS_BUSFABRIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_BUSFABRIC_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> CLK_SYS_BUSFABRIC_W<'a> { #[doc = "Field `clk_sys_busctrl` reader - "] pub struct CLK_SYS_BUSCTRL_R(crate::FieldReader); impl CLK_SYS_BUSCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_BUSCTRL_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> CLK_SYS_BUSCTRL_W<'a> { #[doc = "Field `clk_sys_adc` reader - "] pub struct CLK_SYS_ADC_R(crate::FieldReader); impl CLK_SYS_ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_ADC_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> CLK_SYS_ADC_W<'a> { #[doc = "Field `clk_adc_adc` reader - "] pub struct CLK_ADC_ADC_R(crate::FieldReader); impl CLK_ADC_ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_ADC_ADC_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> CLK_ADC_ADC_W<'a> { #[doc = "Field `clk_sys_clocks` reader - "] pub struct CLK_SYS_CLOCKS_R(crate::FieldReader); impl CLK_SYS_CLOCKS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_CLOCKS_R(crate::FieldReader::new(bits)) } diff --git a/src/clocks/wake_en1.rs b/src/clocks/wake_en1.rs index 690a3e37a..488e66933 100644 --- a/src/clocks/wake_en1.rs +++ b/src/clocks/wake_en1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `clk_sys_xosc` reader - "] pub struct CLK_SYS_XOSC_R(crate::FieldReader); impl CLK_SYS_XOSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_XOSC_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CLK_SYS_XOSC_W<'a> { #[doc = "Field `clk_sys_xip` reader - "] pub struct CLK_SYS_XIP_R(crate::FieldReader); impl CLK_SYS_XIP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_XIP_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> CLK_SYS_XIP_W<'a> { #[doc = "Field `clk_sys_watchdog` reader - "] pub struct CLK_SYS_WATCHDOG_R(crate::FieldReader); impl CLK_SYS_WATCHDOG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_WATCHDOG_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> CLK_SYS_WATCHDOG_W<'a> { #[doc = "Field `clk_usb_usbctrl` reader - "] pub struct CLK_USB_USBCTRL_R(crate::FieldReader); impl CLK_USB_USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_USB_USBCTRL_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> CLK_USB_USBCTRL_W<'a> { #[doc = "Field `clk_sys_usbctrl` reader - "] pub struct CLK_SYS_USBCTRL_R(crate::FieldReader); impl CLK_SYS_USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_USBCTRL_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> CLK_SYS_USBCTRL_W<'a> { #[doc = "Field `clk_sys_uart1` reader - "] pub struct CLK_SYS_UART1_R(crate::FieldReader); impl CLK_SYS_UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_UART1_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> CLK_SYS_UART1_W<'a> { #[doc = "Field `clk_peri_uart1` reader - "] pub struct CLK_PERI_UART1_R(crate::FieldReader); impl CLK_PERI_UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_UART1_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> CLK_PERI_UART1_W<'a> { #[doc = "Field `clk_sys_uart0` reader - "] pub struct CLK_SYS_UART0_R(crate::FieldReader); impl CLK_SYS_UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_UART0_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> CLK_SYS_UART0_W<'a> { #[doc = "Field `clk_peri_uart0` reader - "] pub struct CLK_PERI_UART0_R(crate::FieldReader); impl CLK_PERI_UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_PERI_UART0_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> CLK_PERI_UART0_W<'a> { #[doc = "Field `clk_sys_timer` reader - "] pub struct CLK_SYS_TIMER_R(crate::FieldReader); impl CLK_SYS_TIMER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_TIMER_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> CLK_SYS_TIMER_W<'a> { #[doc = "Field `clk_sys_tbman` reader - "] pub struct CLK_SYS_TBMAN_R(crate::FieldReader); impl CLK_SYS_TBMAN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_TBMAN_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> CLK_SYS_TBMAN_W<'a> { #[doc = "Field `clk_sys_sysinfo` reader - "] pub struct CLK_SYS_SYSINFO_R(crate::FieldReader); impl CLK_SYS_SYSINFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SYSINFO_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> CLK_SYS_SYSINFO_W<'a> { #[doc = "Field `clk_sys_syscfg` reader - "] pub struct CLK_SYS_SYSCFG_R(crate::FieldReader); impl CLK_SYS_SYSCFG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SYSCFG_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> CLK_SYS_SYSCFG_W<'a> { #[doc = "Field `clk_sys_sram5` reader - "] pub struct CLK_SYS_SRAM5_R(crate::FieldReader); impl CLK_SYS_SRAM5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM5_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> CLK_SYS_SRAM5_W<'a> { #[doc = "Field `clk_sys_sram4` reader - "] pub struct CLK_SYS_SRAM4_R(crate::FieldReader); impl CLK_SYS_SRAM4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLK_SYS_SRAM4_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch/ch_al1_ctrl.rs b/src/dma/ch/ch_al1_ctrl.rs index 2dbfc2c95..9fcfb07b8 100644 --- a/src/dma/ch/ch_al1_ctrl.rs +++ b/src/dma/ch/ch_al1_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub struct AHB_ERROR_R(crate::FieldReader); impl AHB_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { AHB_ERROR_R(crate::FieldReader::new(bits)) } @@ -52,6 +53,7 @@ impl core::ops::Deref for AHB_ERROR_R { READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] pub struct READ_ERROR_R(crate::FieldReader); impl READ_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { READ_ERROR_R(crate::FieldReader::new(bits)) } @@ -90,6 +92,7 @@ impl<'a> READ_ERROR_W<'a> { WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] pub struct WRITE_ERROR_R(crate::FieldReader); impl WRITE_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { WRITE_ERROR_R(crate::FieldReader::new(bits)) } @@ -129,6 +132,7 @@ impl<'a> WRITE_ERROR_W<'a> { To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] pub struct BUSY_R(crate::FieldReader); impl BUSY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSY_R(crate::FieldReader::new(bits)) } @@ -145,6 +149,7 @@ impl core::ops::Deref for BUSY_R { This allows checksum to be enabled or disabled on a per-control- block basis."] pub struct SNIFF_EN_R(crate::FieldReader); impl SNIFF_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SNIFF_EN_R(crate::FieldReader::new(bits)) } @@ -184,6 +189,7 @@ impl<'a> SNIFF_EN_W<'a> { For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub struct BSWAP_R(crate::FieldReader); impl BSWAP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BSWAP_R(crate::FieldReader::new(bits)) } @@ -223,6 +229,7 @@ impl<'a> BSWAP_W<'a> { This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub struct IRQ_QUIET_R(crate::FieldReader); impl IRQ_QUIET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IRQ_QUIET_R(crate::FieldReader::new(bits)) } @@ -288,6 +295,7 @@ impl From for u8 { 0x0 to 0x3a -> select DREQ n as TREQ"] pub struct TREQ_SEL_R(crate::FieldReader); impl TREQ_SEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TREQ_SEL_R(crate::FieldReader::new(bits)) } @@ -384,6 +392,7 @@ impl<'a> TREQ_SEL_W<'a> { Reset value is equal to channel number (0)."] pub struct CHAIN_TO_R(crate::FieldReader); impl CHAIN_TO_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CHAIN_TO_R(crate::FieldReader::new(bits)) } @@ -412,6 +421,7 @@ impl<'a> CHAIN_TO_W<'a> { If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub struct RING_SEL_R(crate::FieldReader); impl RING_SEL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RING_SEL_R(crate::FieldReader::new(bits)) } @@ -468,6 +478,7 @@ impl From for u8 { Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub struct RING_SIZE_R(crate::FieldReader); impl RING_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RING_SIZE_R(crate::FieldReader::new(bits)) } @@ -521,6 +532,7 @@ impl<'a> RING_SIZE_W<'a> { Generally this should be disabled for memory-to-peripheral transfers."] pub struct INCR_WRITE_R(crate::FieldReader); impl INCR_WRITE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INCR_WRITE_R(crate::FieldReader::new(bits)) } @@ -561,6 +573,7 @@ impl<'a> INCR_WRITE_W<'a> { Generally this should be disabled for peripheral-to-memory transfers."] pub struct INCR_READ_R(crate::FieldReader); impl INCR_READ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INCR_READ_R(crate::FieldReader::new(bits)) } @@ -618,6 +631,7 @@ impl From for u8 { #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] pub struct DATA_SIZE_R(crate::FieldReader); impl DATA_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DATA_SIZE_R(crate::FieldReader::new(bits)) } @@ -691,6 +705,7 @@ impl<'a> DATA_SIZE_W<'a> { This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub struct HIGH_PRIORITY_R(crate::FieldReader); impl HIGH_PRIORITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HIGH_PRIORITY_R(crate::FieldReader::new(bits)) } @@ -730,6 +745,7 @@ impl<'a> HIGH_PRIORITY_W<'a> { When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -770,62 +786,81 @@ impl R { pub fn ahb_error(&self) -> AHB_ERROR_R { AHB_ERROR_R::new(((self.bits >> 31) & 0x01) != 0) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&self) -> READ_ERROR_R { READ_ERROR_R::new(((self.bits >> 30) & 0x01) != 0) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&self) -> WRITE_ERROR_R { WRITE_ERROR_R::new(((self.bits >> 29) & 0x01) != 0) } - #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 24) & 0x01) != 0) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&self) -> SNIFF_EN_R { SNIFF_EN_R::new(((self.bits >> 23) & 0x01) != 0) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 22) & 0x01) != 0) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&self) -> IRQ_QUIET_R { IRQ_QUIET_R::new(((self.bits >> 21) & 0x01) != 0) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&self) -> TREQ_SEL_R { TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8) } - #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0)."] + #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is equal to channel number (0)."] #[inline(always)] pub fn chain_to(&self) -> CHAIN_TO_R { CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&self) -> RING_SEL_R { RING_SEL_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&self) -> RING_SIZE_R { RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&self) -> INCR_WRITE_R { INCR_WRITE_R::new(((self.bits >> 5) & 0x01) != 0) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&self) -> INCR_READ_R { INCR_READ_R::new(((self.bits >> 4) & 0x01) != 0) @@ -835,69 +870,89 @@ impl R { pub fn data_size(&self) -> DATA_SIZE_R { DATA_SIZE_R::new(((self.bits >> 2) & 0x03) as u8) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&self) -> HIGH_PRIORITY_R { HIGH_PRIORITY_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W { w: self } } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W { w: self } } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W { w: self } } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W { w: self } } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W { w: self } } - #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W { w: self } } - #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0)."] + #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is equal to channel number (0)."] #[inline(always)] pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W { w: self } } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&mut self) -> RING_SEL_W { RING_SEL_W { w: self } } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W { w: self } } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W { w: self } } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W { w: self } @@ -907,12 +962,15 @@ impl W { pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W { w: self } } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { HIGH_PRIORITY_W { w: self } } - #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&mut self) -> EN_W { EN_W { w: self } diff --git a/src/dma/ch/ch_al2_ctrl.rs b/src/dma/ch/ch_al2_ctrl.rs index 9b44c2c56..c0697cf66 100644 --- a/src/dma/ch/ch_al2_ctrl.rs +++ b/src/dma/ch/ch_al2_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub struct AHB_ERROR_R(crate::FieldReader); impl AHB_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { AHB_ERROR_R(crate::FieldReader::new(bits)) } @@ -52,6 +53,7 @@ impl core::ops::Deref for AHB_ERROR_R { READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] pub struct READ_ERROR_R(crate::FieldReader); impl READ_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { READ_ERROR_R(crate::FieldReader::new(bits)) } @@ -90,6 +92,7 @@ impl<'a> READ_ERROR_W<'a> { WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] pub struct WRITE_ERROR_R(crate::FieldReader); impl WRITE_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { WRITE_ERROR_R(crate::FieldReader::new(bits)) } @@ -129,6 +132,7 @@ impl<'a> WRITE_ERROR_W<'a> { To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] pub struct BUSY_R(crate::FieldReader); impl BUSY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSY_R(crate::FieldReader::new(bits)) } @@ -145,6 +149,7 @@ impl core::ops::Deref for BUSY_R { This allows checksum to be enabled or disabled on a per-control- block basis."] pub struct SNIFF_EN_R(crate::FieldReader); impl SNIFF_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SNIFF_EN_R(crate::FieldReader::new(bits)) } @@ -184,6 +189,7 @@ impl<'a> SNIFF_EN_W<'a> { For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub struct BSWAP_R(crate::FieldReader); impl BSWAP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BSWAP_R(crate::FieldReader::new(bits)) } @@ -223,6 +229,7 @@ impl<'a> BSWAP_W<'a> { This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub struct IRQ_QUIET_R(crate::FieldReader); impl IRQ_QUIET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IRQ_QUIET_R(crate::FieldReader::new(bits)) } @@ -288,6 +295,7 @@ impl From for u8 { 0x0 to 0x3a -> select DREQ n as TREQ"] pub struct TREQ_SEL_R(crate::FieldReader); impl TREQ_SEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TREQ_SEL_R(crate::FieldReader::new(bits)) } @@ -384,6 +392,7 @@ impl<'a> TREQ_SEL_W<'a> { Reset value is equal to channel number (0)."] pub struct CHAIN_TO_R(crate::FieldReader); impl CHAIN_TO_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CHAIN_TO_R(crate::FieldReader::new(bits)) } @@ -412,6 +421,7 @@ impl<'a> CHAIN_TO_W<'a> { If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub struct RING_SEL_R(crate::FieldReader); impl RING_SEL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RING_SEL_R(crate::FieldReader::new(bits)) } @@ -468,6 +478,7 @@ impl From for u8 { Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub struct RING_SIZE_R(crate::FieldReader); impl RING_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RING_SIZE_R(crate::FieldReader::new(bits)) } @@ -521,6 +532,7 @@ impl<'a> RING_SIZE_W<'a> { Generally this should be disabled for memory-to-peripheral transfers."] pub struct INCR_WRITE_R(crate::FieldReader); impl INCR_WRITE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INCR_WRITE_R(crate::FieldReader::new(bits)) } @@ -561,6 +573,7 @@ impl<'a> INCR_WRITE_W<'a> { Generally this should be disabled for peripheral-to-memory transfers."] pub struct INCR_READ_R(crate::FieldReader); impl INCR_READ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INCR_READ_R(crate::FieldReader::new(bits)) } @@ -618,6 +631,7 @@ impl From for u8 { #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] pub struct DATA_SIZE_R(crate::FieldReader); impl DATA_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DATA_SIZE_R(crate::FieldReader::new(bits)) } @@ -691,6 +705,7 @@ impl<'a> DATA_SIZE_W<'a> { This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub struct HIGH_PRIORITY_R(crate::FieldReader); impl HIGH_PRIORITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HIGH_PRIORITY_R(crate::FieldReader::new(bits)) } @@ -730,6 +745,7 @@ impl<'a> HIGH_PRIORITY_W<'a> { When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -770,62 +786,81 @@ impl R { pub fn ahb_error(&self) -> AHB_ERROR_R { AHB_ERROR_R::new(((self.bits >> 31) & 0x01) != 0) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&self) -> READ_ERROR_R { READ_ERROR_R::new(((self.bits >> 30) & 0x01) != 0) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&self) -> WRITE_ERROR_R { WRITE_ERROR_R::new(((self.bits >> 29) & 0x01) != 0) } - #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 24) & 0x01) != 0) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&self) -> SNIFF_EN_R { SNIFF_EN_R::new(((self.bits >> 23) & 0x01) != 0) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 22) & 0x01) != 0) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&self) -> IRQ_QUIET_R { IRQ_QUIET_R::new(((self.bits >> 21) & 0x01) != 0) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&self) -> TREQ_SEL_R { TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8) } - #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0)."] + #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is equal to channel number (0)."] #[inline(always)] pub fn chain_to(&self) -> CHAIN_TO_R { CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&self) -> RING_SEL_R { RING_SEL_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&self) -> RING_SIZE_R { RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&self) -> INCR_WRITE_R { INCR_WRITE_R::new(((self.bits >> 5) & 0x01) != 0) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&self) -> INCR_READ_R { INCR_READ_R::new(((self.bits >> 4) & 0x01) != 0) @@ -835,69 +870,89 @@ impl R { pub fn data_size(&self) -> DATA_SIZE_R { DATA_SIZE_R::new(((self.bits >> 2) & 0x03) as u8) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&self) -> HIGH_PRIORITY_R { HIGH_PRIORITY_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W { w: self } } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W { w: self } } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W { w: self } } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W { w: self } } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W { w: self } } - #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W { w: self } } - #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0)."] + #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is equal to channel number (0)."] #[inline(always)] pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W { w: self } } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&mut self) -> RING_SEL_W { RING_SEL_W { w: self } } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W { w: self } } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W { w: self } } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W { w: self } @@ -907,12 +962,15 @@ impl W { pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W { w: self } } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { HIGH_PRIORITY_W { w: self } } - #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&mut self) -> EN_W { EN_W { w: self } diff --git a/src/dma/ch/ch_al3_ctrl.rs b/src/dma/ch/ch_al3_ctrl.rs index 57deec96a..ddec4598d 100644 --- a/src/dma/ch/ch_al3_ctrl.rs +++ b/src/dma/ch/ch_al3_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub struct AHB_ERROR_R(crate::FieldReader); impl AHB_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { AHB_ERROR_R(crate::FieldReader::new(bits)) } @@ -52,6 +53,7 @@ impl core::ops::Deref for AHB_ERROR_R { READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] pub struct READ_ERROR_R(crate::FieldReader); impl READ_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { READ_ERROR_R(crate::FieldReader::new(bits)) } @@ -90,6 +92,7 @@ impl<'a> READ_ERROR_W<'a> { WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] pub struct WRITE_ERROR_R(crate::FieldReader); impl WRITE_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { WRITE_ERROR_R(crate::FieldReader::new(bits)) } @@ -129,6 +132,7 @@ impl<'a> WRITE_ERROR_W<'a> { To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] pub struct BUSY_R(crate::FieldReader); impl BUSY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSY_R(crate::FieldReader::new(bits)) } @@ -145,6 +149,7 @@ impl core::ops::Deref for BUSY_R { This allows checksum to be enabled or disabled on a per-control- block basis."] pub struct SNIFF_EN_R(crate::FieldReader); impl SNIFF_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SNIFF_EN_R(crate::FieldReader::new(bits)) } @@ -184,6 +189,7 @@ impl<'a> SNIFF_EN_W<'a> { For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub struct BSWAP_R(crate::FieldReader); impl BSWAP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BSWAP_R(crate::FieldReader::new(bits)) } @@ -223,6 +229,7 @@ impl<'a> BSWAP_W<'a> { This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub struct IRQ_QUIET_R(crate::FieldReader); impl IRQ_QUIET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IRQ_QUIET_R(crate::FieldReader::new(bits)) } @@ -288,6 +295,7 @@ impl From for u8 { 0x0 to 0x3a -> select DREQ n as TREQ"] pub struct TREQ_SEL_R(crate::FieldReader); impl TREQ_SEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TREQ_SEL_R(crate::FieldReader::new(bits)) } @@ -384,6 +392,7 @@ impl<'a> TREQ_SEL_W<'a> { Reset value is equal to channel number (0)."] pub struct CHAIN_TO_R(crate::FieldReader); impl CHAIN_TO_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CHAIN_TO_R(crate::FieldReader::new(bits)) } @@ -412,6 +421,7 @@ impl<'a> CHAIN_TO_W<'a> { If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub struct RING_SEL_R(crate::FieldReader); impl RING_SEL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RING_SEL_R(crate::FieldReader::new(bits)) } @@ -468,6 +478,7 @@ impl From for u8 { Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub struct RING_SIZE_R(crate::FieldReader); impl RING_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RING_SIZE_R(crate::FieldReader::new(bits)) } @@ -521,6 +532,7 @@ impl<'a> RING_SIZE_W<'a> { Generally this should be disabled for memory-to-peripheral transfers."] pub struct INCR_WRITE_R(crate::FieldReader); impl INCR_WRITE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INCR_WRITE_R(crate::FieldReader::new(bits)) } @@ -561,6 +573,7 @@ impl<'a> INCR_WRITE_W<'a> { Generally this should be disabled for peripheral-to-memory transfers."] pub struct INCR_READ_R(crate::FieldReader); impl INCR_READ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INCR_READ_R(crate::FieldReader::new(bits)) } @@ -618,6 +631,7 @@ impl From for u8 { #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] pub struct DATA_SIZE_R(crate::FieldReader); impl DATA_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DATA_SIZE_R(crate::FieldReader::new(bits)) } @@ -691,6 +705,7 @@ impl<'a> DATA_SIZE_W<'a> { This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub struct HIGH_PRIORITY_R(crate::FieldReader); impl HIGH_PRIORITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HIGH_PRIORITY_R(crate::FieldReader::new(bits)) } @@ -730,6 +745,7 @@ impl<'a> HIGH_PRIORITY_W<'a> { When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -770,62 +786,81 @@ impl R { pub fn ahb_error(&self) -> AHB_ERROR_R { AHB_ERROR_R::new(((self.bits >> 31) & 0x01) != 0) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&self) -> READ_ERROR_R { READ_ERROR_R::new(((self.bits >> 30) & 0x01) != 0) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&self) -> WRITE_ERROR_R { WRITE_ERROR_R::new(((self.bits >> 29) & 0x01) != 0) } - #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 24) & 0x01) != 0) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&self) -> SNIFF_EN_R { SNIFF_EN_R::new(((self.bits >> 23) & 0x01) != 0) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 22) & 0x01) != 0) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&self) -> IRQ_QUIET_R { IRQ_QUIET_R::new(((self.bits >> 21) & 0x01) != 0) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&self) -> TREQ_SEL_R { TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8) } - #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0)."] + #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is equal to channel number (0)."] #[inline(always)] pub fn chain_to(&self) -> CHAIN_TO_R { CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&self) -> RING_SEL_R { RING_SEL_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&self) -> RING_SIZE_R { RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&self) -> INCR_WRITE_R { INCR_WRITE_R::new(((self.bits >> 5) & 0x01) != 0) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&self) -> INCR_READ_R { INCR_READ_R::new(((self.bits >> 4) & 0x01) != 0) @@ -835,69 +870,89 @@ impl R { pub fn data_size(&self) -> DATA_SIZE_R { DATA_SIZE_R::new(((self.bits >> 2) & 0x03) as u8) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&self) -> HIGH_PRIORITY_R { HIGH_PRIORITY_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W { w: self } } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W { w: self } } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W { w: self } } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W { w: self } } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W { w: self } } - #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W { w: self } } - #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0)."] + #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is equal to channel number (0)."] #[inline(always)] pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W { w: self } } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&mut self) -> RING_SEL_W { RING_SEL_W { w: self } } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W { w: self } } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W { w: self } } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W { w: self } @@ -907,12 +962,15 @@ impl W { pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W { w: self } } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { HIGH_PRIORITY_W { w: self } } - #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&mut self) -> EN_W { EN_W { w: self } diff --git a/src/dma/ch/ch_ctrl_trig.rs b/src/dma/ch/ch_ctrl_trig.rs index 994d5b6d2..edf52d8e5 100644 --- a/src/dma/ch/ch_ctrl_trig.rs +++ b/src/dma/ch/ch_ctrl_trig.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub struct AHB_ERROR_R(crate::FieldReader); impl AHB_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { AHB_ERROR_R(crate::FieldReader::new(bits)) } @@ -52,6 +53,7 @@ impl core::ops::Deref for AHB_ERROR_R { READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] pub struct READ_ERROR_R(crate::FieldReader); impl READ_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { READ_ERROR_R(crate::FieldReader::new(bits)) } @@ -90,6 +92,7 @@ impl<'a> READ_ERROR_W<'a> { WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] pub struct WRITE_ERROR_R(crate::FieldReader); impl WRITE_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { WRITE_ERROR_R(crate::FieldReader::new(bits)) } @@ -129,6 +132,7 @@ impl<'a> WRITE_ERROR_W<'a> { To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] pub struct BUSY_R(crate::FieldReader); impl BUSY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSY_R(crate::FieldReader::new(bits)) } @@ -145,6 +149,7 @@ impl core::ops::Deref for BUSY_R { This allows checksum to be enabled or disabled on a per-control- block basis."] pub struct SNIFF_EN_R(crate::FieldReader); impl SNIFF_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SNIFF_EN_R(crate::FieldReader::new(bits)) } @@ -184,6 +189,7 @@ impl<'a> SNIFF_EN_W<'a> { For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub struct BSWAP_R(crate::FieldReader); impl BSWAP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BSWAP_R(crate::FieldReader::new(bits)) } @@ -223,6 +229,7 @@ impl<'a> BSWAP_W<'a> { This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub struct IRQ_QUIET_R(crate::FieldReader); impl IRQ_QUIET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IRQ_QUIET_R(crate::FieldReader::new(bits)) } @@ -288,6 +295,7 @@ impl From for u8 { 0x0 to 0x3a -> select DREQ n as TREQ"] pub struct TREQ_SEL_R(crate::FieldReader); impl TREQ_SEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TREQ_SEL_R(crate::FieldReader::new(bits)) } @@ -384,6 +392,7 @@ impl<'a> TREQ_SEL_W<'a> { Reset value is equal to channel number (0)."] pub struct CHAIN_TO_R(crate::FieldReader); impl CHAIN_TO_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CHAIN_TO_R(crate::FieldReader::new(bits)) } @@ -412,6 +421,7 @@ impl<'a> CHAIN_TO_W<'a> { If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub struct RING_SEL_R(crate::FieldReader); impl RING_SEL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RING_SEL_R(crate::FieldReader::new(bits)) } @@ -468,6 +478,7 @@ impl From for u8 { Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub struct RING_SIZE_R(crate::FieldReader); impl RING_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RING_SIZE_R(crate::FieldReader::new(bits)) } @@ -521,6 +532,7 @@ impl<'a> RING_SIZE_W<'a> { Generally this should be disabled for memory-to-peripheral transfers."] pub struct INCR_WRITE_R(crate::FieldReader); impl INCR_WRITE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INCR_WRITE_R(crate::FieldReader::new(bits)) } @@ -561,6 +573,7 @@ impl<'a> INCR_WRITE_W<'a> { Generally this should be disabled for peripheral-to-memory transfers."] pub struct INCR_READ_R(crate::FieldReader); impl INCR_READ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INCR_READ_R(crate::FieldReader::new(bits)) } @@ -618,6 +631,7 @@ impl From for u8 { #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] pub struct DATA_SIZE_R(crate::FieldReader); impl DATA_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DATA_SIZE_R(crate::FieldReader::new(bits)) } @@ -691,6 +705,7 @@ impl<'a> DATA_SIZE_W<'a> { This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub struct HIGH_PRIORITY_R(crate::FieldReader); impl HIGH_PRIORITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HIGH_PRIORITY_R(crate::FieldReader::new(bits)) } @@ -730,6 +745,7 @@ impl<'a> HIGH_PRIORITY_W<'a> { When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -770,62 +786,81 @@ impl R { pub fn ahb_error(&self) -> AHB_ERROR_R { AHB_ERROR_R::new(((self.bits >> 31) & 0x01) != 0) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&self) -> READ_ERROR_R { READ_ERROR_R::new(((self.bits >> 30) & 0x01) != 0) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&self) -> WRITE_ERROR_R { WRITE_ERROR_R::new(((self.bits >> 29) & 0x01) != 0) } - #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 24) & 0x01) != 0) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&self) -> SNIFF_EN_R { SNIFF_EN_R::new(((self.bits >> 23) & 0x01) != 0) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 22) & 0x01) != 0) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&self) -> IRQ_QUIET_R { IRQ_QUIET_R::new(((self.bits >> 21) & 0x01) != 0) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&self) -> TREQ_SEL_R { TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8) } - #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0)."] + #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is equal to channel number (0)."] #[inline(always)] pub fn chain_to(&self) -> CHAIN_TO_R { CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&self) -> RING_SEL_R { RING_SEL_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&self) -> RING_SIZE_R { RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&self) -> INCR_WRITE_R { INCR_WRITE_R::new(((self.bits >> 5) & 0x01) != 0) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&self) -> INCR_READ_R { INCR_READ_R::new(((self.bits >> 4) & 0x01) != 0) @@ -835,69 +870,89 @@ impl R { pub fn data_size(&self) -> DATA_SIZE_R { DATA_SIZE_R::new(((self.bits >> 2) & 0x03) as u8) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&self) -> HIGH_PRIORITY_R { HIGH_PRIORITY_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W { w: self } } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W { w: self } } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W { w: self } } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W { w: self } } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W { w: self } } - #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W { w: self } } - #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0)."] + #[doc = "Bits 11:14 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is equal to channel number (0)."] #[inline(always)] pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W { w: self } } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&mut self) -> RING_SEL_W { RING_SEL_W { w: self } } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W { w: self } } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W { w: self } } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W { w: self } @@ -907,12 +962,15 @@ impl W { pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W { w: self } } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { HIGH_PRIORITY_W { w: self } } - #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&mut self) -> EN_W { EN_W { w: self } diff --git a/src/dma/ch0_dbg_ctdreq.rs b/src/dma/ch0_dbg_ctdreq.rs index 6bcf9cdb1..26d94025a 100644 --- a/src/dma/ch0_dbg_ctdreq.rs +++ b/src/dma/ch0_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH0_DBG_CTDREQ` reader - "] pub struct CH0_DBG_CTDREQ_R(crate::FieldReader); impl CH0_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH0_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch10_dbg_ctdreq.rs b/src/dma/ch10_dbg_ctdreq.rs index 5d6505c88..791e0af32 100644 --- a/src/dma/ch10_dbg_ctdreq.rs +++ b/src/dma/ch10_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH10_DBG_CTDREQ` reader - "] pub struct CH10_DBG_CTDREQ_R(crate::FieldReader); impl CH10_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH10_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch11_dbg_ctdreq.rs b/src/dma/ch11_dbg_ctdreq.rs index b636acd00..bd0d0ab2a 100644 --- a/src/dma/ch11_dbg_ctdreq.rs +++ b/src/dma/ch11_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH11_DBG_CTDREQ` reader - "] pub struct CH11_DBG_CTDREQ_R(crate::FieldReader); impl CH11_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH11_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch1_dbg_ctdreq.rs b/src/dma/ch1_dbg_ctdreq.rs index 8c214b3db..38d5a0aff 100644 --- a/src/dma/ch1_dbg_ctdreq.rs +++ b/src/dma/ch1_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH1_DBG_CTDREQ` reader - "] pub struct CH1_DBG_CTDREQ_R(crate::FieldReader); impl CH1_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH1_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch2_dbg_ctdreq.rs b/src/dma/ch2_dbg_ctdreq.rs index 230a314ec..b544b5a14 100644 --- a/src/dma/ch2_dbg_ctdreq.rs +++ b/src/dma/ch2_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH2_DBG_CTDREQ` reader - "] pub struct CH2_DBG_CTDREQ_R(crate::FieldReader); impl CH2_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH2_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch3_dbg_ctdreq.rs b/src/dma/ch3_dbg_ctdreq.rs index 12658d58f..5d57c73ee 100644 --- a/src/dma/ch3_dbg_ctdreq.rs +++ b/src/dma/ch3_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH3_DBG_CTDREQ` reader - "] pub struct CH3_DBG_CTDREQ_R(crate::FieldReader); impl CH3_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH3_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch4_dbg_ctdreq.rs b/src/dma/ch4_dbg_ctdreq.rs index f3ae8a0e4..d490acf61 100644 --- a/src/dma/ch4_dbg_ctdreq.rs +++ b/src/dma/ch4_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH4_DBG_CTDREQ` reader - "] pub struct CH4_DBG_CTDREQ_R(crate::FieldReader); impl CH4_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH4_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch5_dbg_ctdreq.rs b/src/dma/ch5_dbg_ctdreq.rs index 382ce9bdc..800ae05ca 100644 --- a/src/dma/ch5_dbg_ctdreq.rs +++ b/src/dma/ch5_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH5_DBG_CTDREQ` reader - "] pub struct CH5_DBG_CTDREQ_R(crate::FieldReader); impl CH5_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH5_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch6_dbg_ctdreq.rs b/src/dma/ch6_dbg_ctdreq.rs index 98484cefd..15f6e810c 100644 --- a/src/dma/ch6_dbg_ctdreq.rs +++ b/src/dma/ch6_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH6_DBG_CTDREQ` reader - "] pub struct CH6_DBG_CTDREQ_R(crate::FieldReader); impl CH6_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH6_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch7_dbg_ctdreq.rs b/src/dma/ch7_dbg_ctdreq.rs index 9a9b02d91..0109beead 100644 --- a/src/dma/ch7_dbg_ctdreq.rs +++ b/src/dma/ch7_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH7_DBG_CTDREQ` reader - "] pub struct CH7_DBG_CTDREQ_R(crate::FieldReader); impl CH7_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH7_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch8_dbg_ctdreq.rs b/src/dma/ch8_dbg_ctdreq.rs index 2d5d2fd1e..7380a2a3d 100644 --- a/src/dma/ch8_dbg_ctdreq.rs +++ b/src/dma/ch8_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH8_DBG_CTDREQ` reader - "] pub struct CH8_DBG_CTDREQ_R(crate::FieldReader); impl CH8_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH8_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/ch9_dbg_ctdreq.rs b/src/dma/ch9_dbg_ctdreq.rs index 9d8edfcce..a78d63f2f 100644 --- a/src/dma/ch9_dbg_ctdreq.rs +++ b/src/dma/ch9_dbg_ctdreq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH9_DBG_CTDREQ` reader - "] pub struct CH9_DBG_CTDREQ_R(crate::FieldReader); impl CH9_DBG_CTDREQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CH9_DBG_CTDREQ_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/chan_abort.rs b/src/dma/chan_abort.rs index b996e3b59..bb5094e8a 100644 --- a/src/dma/chan_abort.rs +++ b/src/dma/chan_abort.rs @@ -39,6 +39,7 @@ impl From> for W { After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] pub struct CHAN_ABORT_R(crate::FieldReader); impl CHAN_ABORT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { CHAN_ABORT_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> CHAN_ABORT_W<'a> { } } impl R { - #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] + #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] #[inline(always)] pub fn chan_abort(&self) -> CHAN_ABORT_R { CHAN_ABORT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] + #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] #[inline(always)] pub fn chan_abort(&mut self) -> CHAN_ABORT_W { CHAN_ABORT_W { w: self } diff --git a/src/dma/fifo_levels.rs b/src/dma/fifo_levels.rs index 20825ec50..22dfd441f 100644 --- a/src/dma/fifo_levels.rs +++ b/src/dma/fifo_levels.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RAF_LVL` reader - Current Read-Address-FIFO fill level"] pub struct RAF_LVL_R(crate::FieldReader); impl RAF_LVL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RAF_LVL_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for RAF_LVL_R { #[doc = "Field `WAF_LVL` reader - Current Write-Address-FIFO fill level"] pub struct WAF_LVL_R(crate::FieldReader); impl WAF_LVL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { WAF_LVL_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for WAF_LVL_R { #[doc = "Field `TDF_LVL` reader - Current Transfer-Data-FIFO fill level"] pub struct TDF_LVL_R(crate::FieldReader); impl TDF_LVL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TDF_LVL_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/inte0.rs b/src/dma/inte0.rs index 9cd0abaf2..83696193c 100644 --- a/src/dma/inte0.rs +++ b/src/dma/inte0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTE0` reader - Set bit n to pass interrupts from channel n to DMA IRQ 0."] pub struct INTE0_R(crate::FieldReader); impl INTE0_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INTE0_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/inte1.rs b/src/dma/inte1.rs index c450a3d34..a379f7bf5 100644 --- a/src/dma/inte1.rs +++ b/src/dma/inte1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTE1` reader - Set bit n to pass interrupts from channel n to DMA IRQ 1."] pub struct INTE1_R(crate::FieldReader); impl INTE1_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INTE1_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/intf0.rs b/src/dma/intf0.rs index 60138a0ef..5454d764d 100644 --- a/src/dma/intf0.rs +++ b/src/dma/intf0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTF0` reader - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] pub struct INTF0_R(crate::FieldReader); impl INTF0_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INTF0_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/intf1.rs b/src/dma/intf1.rs index daa92c0e3..5ee9ca274 100644 --- a/src/dma/intf1.rs +++ b/src/dma/intf1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTF1` reader - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared."] pub struct INTF1_R(crate::FieldReader); impl INTF1_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INTF1_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/intr.rs b/src/dma/intr.rs index afbbf2db7..dcf7ea7db 100644 --- a/src/dma/intr.rs +++ b/src/dma/intr.rs @@ -22,6 +22,7 @@ impl From> for R { It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] pub struct INTR_R(crate::FieldReader); impl INTR_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INTR_R(crate::FieldReader::new(bits)) } @@ -34,7 +35,13 @@ impl core::ops::Deref for INTR_R { } } impl R { - #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. + + Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. + + This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. + + It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] #[inline(always)] pub fn intr(&self) -> INTR_R { INTR_R::new((self.bits & 0xffff) as u16) diff --git a/src/dma/ints0.rs b/src/dma/ints0.rs index ce9752fcb..0f72ddcad 100644 --- a/src/dma/ints0.rs +++ b/src/dma/ints0.rs @@ -38,6 +38,7 @@ impl From> for W { Channel interrupts can be cleared by writing a bit mask here."] pub struct INTS0_R(crate::FieldReader); impl INTS0_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INTS0_R(crate::FieldReader::new(bits)) } @@ -63,14 +64,16 @@ impl<'a> INTS0_W<'a> { } } impl R { - #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] pub fn ints0(&self) -> INTS0_R { INTS0_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] pub fn ints0(&mut self) -> INTS0_W { INTS0_W { w: self } diff --git a/src/dma/ints1.rs b/src/dma/ints1.rs index 87591493c..a5819bc51 100644 --- a/src/dma/ints1.rs +++ b/src/dma/ints1.rs @@ -38,6 +38,7 @@ impl From> for W { Channel interrupts can be cleared by writing a bit mask here."] pub struct INTS1_R(crate::FieldReader); impl INTS1_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INTS1_R(crate::FieldReader::new(bits)) } @@ -63,14 +64,16 @@ impl<'a> INTS1_W<'a> { } } impl R { - #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] pub fn ints1(&self) -> INTS1_R { INTS1_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] pub fn ints1(&mut self) -> INTS1_W { INTS1_W { w: self } diff --git a/src/dma/multi_chan_trigger.rs b/src/dma/multi_chan_trigger.rs index 73d3110f2..b5867639b 100644 --- a/src/dma/multi_chan_trigger.rs +++ b/src/dma/multi_chan_trigger.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `MULTI_CHAN_TRIGGER` reader - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] pub struct MULTI_CHAN_TRIGGER_R(crate::FieldReader); impl MULTI_CHAN_TRIGGER_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { MULTI_CHAN_TRIGGER_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/n_channels.rs b/src/dma/n_channels.rs index 50e1a8d46..1b028a11c 100644 --- a/src/dma/n_channels.rs +++ b/src/dma/n_channels.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `N_CHANNELS` reader - "] pub struct N_CHANNELS_R(crate::FieldReader); impl N_CHANNELS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { N_CHANNELS_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/sniff_ctrl.rs b/src/dma/sniff_ctrl.rs index ffa9bdb36..241fab767 100644 --- a/src/dma/sniff_ctrl.rs +++ b/src/dma/sniff_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OUT_INV` reader - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] pub struct OUT_INV_R(crate::FieldReader); impl OUT_INV_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUT_INV_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OUT_INV_W<'a> { #[doc = "Field `OUT_REV` reader - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] pub struct OUT_REV_R(crate::FieldReader); impl OUT_REV_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUT_REV_R(crate::FieldReader::new(bits)) } @@ -111,6 +113,7 @@ impl<'a> OUT_REV_W<'a> { Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] pub struct BSWAP_R(crate::FieldReader); impl BSWAP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BSWAP_R(crate::FieldReader::new(bits)) } @@ -174,6 +177,7 @@ impl From for u8 { #[doc = "Field `CALC` reader - "] pub struct CALC_R(crate::FieldReader); impl CALC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CALC_R(crate::FieldReader::new(bits)) } @@ -278,6 +282,7 @@ impl<'a> CALC_W<'a> { #[doc = "Field `DMACH` reader - DMA channel for Sniffer to observe"] pub struct DMACH_R(crate::FieldReader); impl DMACH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DMACH_R(crate::FieldReader::new(bits)) } @@ -304,6 +309,7 @@ impl<'a> DMACH_W<'a> { #[doc = "Field `EN` reader - Enable sniffer"] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -348,7 +354,9 @@ impl R { pub fn out_rev(&self) -> OUT_REV_R { OUT_REV_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] + #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 9) & 0x01) != 0) @@ -380,7 +388,9 @@ impl W { pub fn out_rev(&mut self) -> OUT_REV_W { OUT_REV_W { w: self } } - #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] + #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] #[inline(always)] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W { w: self } diff --git a/src/dma/timer0.rs b/src/dma/timer0.rs index cab6d2a7b..b35791a61 100644 --- a/src/dma/timer0.rs +++ b/src/dma/timer0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] pub struct X_R(crate::FieldReader); impl X_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { X_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> X_W<'a> { #[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] pub struct Y_R(crate::FieldReader); impl Y_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { Y_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/timer1.rs b/src/dma/timer1.rs index afb129d24..c4703b7ce 100644 --- a/src/dma/timer1.rs +++ b/src/dma/timer1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] pub struct X_R(crate::FieldReader); impl X_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { X_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> X_W<'a> { #[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] pub struct Y_R(crate::FieldReader); impl Y_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { Y_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/timer2.rs b/src/dma/timer2.rs index 7a9e91c86..023dc2486 100644 --- a/src/dma/timer2.rs +++ b/src/dma/timer2.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] pub struct X_R(crate::FieldReader); impl X_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { X_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> X_W<'a> { #[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] pub struct Y_R(crate::FieldReader); impl Y_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { Y_R(crate::FieldReader::new(bits)) } diff --git a/src/dma/timer3.rs b/src/dma/timer3.rs index fe7f5e5b4..8f4b93131 100644 --- a/src/dma/timer3.rs +++ b/src/dma/timer3.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] pub struct X_R(crate::FieldReader); impl X_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { X_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> X_W<'a> { #[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] pub struct Y_R(crate::FieldReader); impl Y_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { Y_R(crate::FieldReader::new(bits)) } diff --git a/src/i2c0/ic_ack_general_call.rs b/src/i2c0/ic_ack_general_call.rs index e07d10c33..13cc9ca3b 100644 --- a/src/i2c0/ic_ack_general_call.rs +++ b/src/i2c0/ic_ack_general_call.rs @@ -53,6 +53,7 @@ impl From for bool { #[doc = "Field `ACK_GEN_CALL` reader - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] pub struct ACK_GEN_CALL_R(crate::FieldReader); impl ACK_GEN_CALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ACK_GEN_CALL_R(crate::FieldReader::new(bits)) } diff --git a/src/i2c0/ic_clr_activity.rs b/src/i2c0/ic_clr_activity.rs index d54c27972..609dc2e52 100644 --- a/src/i2c0/ic_clr_activity.rs +++ b/src/i2c0/ic_clr_activity.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_ACTIVITY_R(crate::FieldReader); impl CLR_ACTIVITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_ACTIVITY_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_ACTIVITY_R { } } impl R { - #[doc = "Bit 0 - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_activity(&self) -> CLR_ACTIVITY_R { CLR_ACTIVITY_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_gen_call.rs b/src/i2c0/ic_clr_gen_call.rs index 654fdc275..c288b0d0d 100644 --- a/src/i2c0/ic_clr_gen_call.rs +++ b/src/i2c0/ic_clr_gen_call.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_GEN_CALL_R(crate::FieldReader); impl CLR_GEN_CALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_GEN_CALL_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_GEN_CALL_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_gen_call(&self) -> CLR_GEN_CALL_R { CLR_GEN_CALL_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_intr.rs b/src/i2c0/ic_clr_intr.rs index cce771f71..dcbea3a9a 100644 --- a/src/i2c0/ic_clr_intr.rs +++ b/src/i2c0/ic_clr_intr.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_INTR_R(crate::FieldReader); impl CLR_INTR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_INTR_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_INTR_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0"] #[inline(always)] pub fn clr_intr(&self) -> CLR_INTR_R { CLR_INTR_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_rd_req.rs b/src/i2c0/ic_clr_rd_req.rs index a80d72167..5619b0e25 100644 --- a/src/i2c0/ic_clr_rd_req.rs +++ b/src/i2c0/ic_clr_rd_req.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_RD_REQ_R(crate::FieldReader); impl CLR_RD_REQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_RD_REQ_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_RD_REQ_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_rd_req(&self) -> CLR_RD_REQ_R { CLR_RD_REQ_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_restart_det.rs b/src/i2c0/ic_clr_restart_det.rs index e73036ecf..5b7d09456 100644 --- a/src/i2c0/ic_clr_restart_det.rs +++ b/src/i2c0/ic_clr_restart_det.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_RESTART_DET_R(crate::FieldReader); impl CLR_RESTART_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_RESTART_DET_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_RESTART_DET_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_restart_det(&self) -> CLR_RESTART_DET_R { CLR_RESTART_DET_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_rx_done.rs b/src/i2c0/ic_clr_rx_done.rs index 9246aa441..4e0fc8d7d 100644 --- a/src/i2c0/ic_clr_rx_done.rs +++ b/src/i2c0/ic_clr_rx_done.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_RX_DONE_R(crate::FieldReader); impl CLR_RX_DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_RX_DONE_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_RX_DONE_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_rx_done(&self) -> CLR_RX_DONE_R { CLR_RX_DONE_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_rx_over.rs b/src/i2c0/ic_clr_rx_over.rs index 7a71501f3..48677bc94 100644 --- a/src/i2c0/ic_clr_rx_over.rs +++ b/src/i2c0/ic_clr_rx_over.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_RX_OVER_R(crate::FieldReader); impl CLR_RX_OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_RX_OVER_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_RX_OVER_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_rx_over(&self) -> CLR_RX_OVER_R { CLR_RX_OVER_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_rx_under.rs b/src/i2c0/ic_clr_rx_under.rs index 5502f5e26..02a39b23f 100644 --- a/src/i2c0/ic_clr_rx_under.rs +++ b/src/i2c0/ic_clr_rx_under.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_RX_UNDER_R(crate::FieldReader); impl CLR_RX_UNDER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_RX_UNDER_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_RX_UNDER_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_rx_under(&self) -> CLR_RX_UNDER_R { CLR_RX_UNDER_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_start_det.rs b/src/i2c0/ic_clr_start_det.rs index cd797e59d..15611c84e 100644 --- a/src/i2c0/ic_clr_start_det.rs +++ b/src/i2c0/ic_clr_start_det.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_START_DET_R(crate::FieldReader); impl CLR_START_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_START_DET_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_START_DET_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_start_det(&self) -> CLR_START_DET_R { CLR_START_DET_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_stop_det.rs b/src/i2c0/ic_clr_stop_det.rs index 74e11426b..6a9247ce4 100644 --- a/src/i2c0/ic_clr_stop_det.rs +++ b/src/i2c0/ic_clr_stop_det.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_STOP_DET_R(crate::FieldReader); impl CLR_STOP_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_STOP_DET_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_STOP_DET_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_stop_det(&self) -> CLR_STOP_DET_R { CLR_STOP_DET_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_tx_abrt.rs b/src/i2c0/ic_clr_tx_abrt.rs index b0901abb9..e32768231 100644 --- a/src/i2c0/ic_clr_tx_abrt.rs +++ b/src/i2c0/ic_clr_tx_abrt.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_TX_ABRT_R(crate::FieldReader); impl CLR_TX_ABRT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_TX_ABRT_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_TX_ABRT_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0"] #[inline(always)] pub fn clr_tx_abrt(&self) -> CLR_TX_ABRT_R { CLR_TX_ABRT_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_clr_tx_over.rs b/src/i2c0/ic_clr_tx_over.rs index 3dcaf2c5a..2a738568d 100644 --- a/src/i2c0/ic_clr_tx_over.rs +++ b/src/i2c0/ic_clr_tx_over.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct CLR_TX_OVER_R(crate::FieldReader); impl CLR_TX_OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLR_TX_OVER_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for CLR_TX_OVER_R { } } impl R { - #[doc = "Bit 0 - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn clr_tx_over(&self) -> CLR_TX_OVER_R { CLR_TX_OVER_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_comp_param_1.rs b/src/i2c0/ic_comp_param_1.rs index f6982a0b9..08342b0b1 100644 --- a/src/i2c0/ic_comp_param_1.rs +++ b/src/i2c0/ic_comp_param_1.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `TX_BUFFER_DEPTH` reader - TX Buffer Depth = 16"] pub struct TX_BUFFER_DEPTH_R(crate::FieldReader); impl TX_BUFFER_DEPTH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TX_BUFFER_DEPTH_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for TX_BUFFER_DEPTH_R { #[doc = "Field `RX_BUFFER_DEPTH` reader - RX Buffer Depth = 16"] pub struct RX_BUFFER_DEPTH_R(crate::FieldReader); impl RX_BUFFER_DEPTH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RX_BUFFER_DEPTH_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for RX_BUFFER_DEPTH_R { #[doc = "Field `ADD_ENCODED_PARAMS` reader - Encoded parameters not visible"] pub struct ADD_ENCODED_PARAMS_R(crate::FieldReader); impl ADD_ENCODED_PARAMS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ADD_ENCODED_PARAMS_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for ADD_ENCODED_PARAMS_R { #[doc = "Field `HAS_DMA` reader - DMA handshaking signals are enabled"] pub struct HAS_DMA_R(crate::FieldReader); impl HAS_DMA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HAS_DMA_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for HAS_DMA_R { #[doc = "Field `INTR_IO` reader - COMBINED Interrupt outputs"] pub struct INTR_IO_R(crate::FieldReader); impl INTR_IO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTR_IO_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for INTR_IO_R { #[doc = "Field `HC_COUNT_VALUES` reader - Programmable count values for each mode."] pub struct HC_COUNT_VALUES_R(crate::FieldReader); impl HC_COUNT_VALUES_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HC_COUNT_VALUES_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for HC_COUNT_VALUES_R { #[doc = "Field `MAX_SPEED_MODE` reader - MAX SPEED MODE = FAST MODE"] pub struct MAX_SPEED_MODE_R(crate::FieldReader); impl MAX_SPEED_MODE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MAX_SPEED_MODE_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for MAX_SPEED_MODE_R { #[doc = "Field `APB_DATA_WIDTH` reader - APB data bus width is 32 bits"] pub struct APB_DATA_WIDTH_R(crate::FieldReader); impl APB_DATA_WIDTH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { APB_DATA_WIDTH_R(crate::FieldReader::new(bits)) } diff --git a/src/i2c0/ic_comp_type.rs b/src/i2c0/ic_comp_type.rs index 1a39bd0c3..edc82728b 100644 --- a/src/i2c0/ic_comp_type.rs +++ b/src/i2c0/ic_comp_type.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `IC_COMP_TYPE` reader - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number."] pub struct IC_COMP_TYPE_R(crate::FieldReader); impl IC_COMP_TYPE_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { IC_COMP_TYPE_R(crate::FieldReader::new(bits)) } diff --git a/src/i2c0/ic_comp_version.rs b/src/i2c0/ic_comp_version.rs index 1e0eb2326..7021abdff 100644 --- a/src/i2c0/ic_comp_version.rs +++ b/src/i2c0/ic_comp_version.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `IC_COMP_VERSION` reader - "] pub struct IC_COMP_VERSION_R(crate::FieldReader); impl IC_COMP_VERSION_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { IC_COMP_VERSION_R(crate::FieldReader::new(bits)) } diff --git a/src/i2c0/ic_con.rs b/src/i2c0/ic_con.rs index f986fb3e6..c3f5377e7 100644 --- a/src/i2c0/ic_con.rs +++ b/src/i2c0/ic_con.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `STOP_DET_IF_MASTER_ACTIVE` reader - Master issues the STOP_DET interrupt irrespective of whether master is active or not"] pub struct STOP_DET_IF_MASTER_ACTIVE_R(crate::FieldReader); impl STOP_DET_IF_MASTER_ACTIVE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STOP_DET_IF_MASTER_ACTIVE_R(crate::FieldReader::new(bits)) } @@ -71,6 +72,7 @@ impl From for bool { Reset value: 0x0."] pub struct RX_FIFO_FULL_HLD_CTRL_R(crate::FieldReader); impl RX_FIFO_FULL_HLD_CTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_FIFO_FULL_HLD_CTRL_R(crate::FieldReader::new(bits)) } @@ -162,6 +164,7 @@ impl From for bool { Reset value: 0x0."] pub struct TX_EMPTY_CTRL_R(crate::FieldReader); impl TX_EMPTY_CTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_EMPTY_CTRL_R(crate::FieldReader::new(bits)) } @@ -253,6 +256,7 @@ impl From for bool { NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] pub struct STOP_DET_IFADDRESSED_R(crate::FieldReader); impl STOP_DET_IFADDRESSED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STOP_DET_IFADDRESSED_R(crate::FieldReader::new(bits)) } @@ -348,6 +352,7 @@ impl From for bool { NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] pub struct IC_SLAVE_DISABLE_R(crate::FieldReader); impl IC_SLAVE_DISABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IC_SLAVE_DISABLE_R(crate::FieldReader::new(bits)) } @@ -441,6 +446,7 @@ impl From for bool { Reset value: ENABLED"] pub struct IC_RESTART_EN_R(crate::FieldReader); impl IC_RESTART_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IC_RESTART_EN_R(crate::FieldReader::new(bits)) } @@ -528,6 +534,7 @@ impl From for bool { #[doc = "Field `IC_10BITADDR_MASTER` reader - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] pub struct IC_10BITADDR_MASTER_R(crate::FieldReader); impl IC_10BITADDR_MASTER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IC_10BITADDR_MASTER_R(crate::FieldReader::new(bits)) } @@ -613,6 +620,7 @@ impl From for bool { #[doc = "Field `IC_10BITADDR_SLAVE` reader - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] pub struct IC_10BITADDR_SLAVE_R(crate::FieldReader); impl IC_10BITADDR_SLAVE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IC_10BITADDR_SLAVE_R(crate::FieldReader::new(bits)) } @@ -721,6 +729,7 @@ impl From for u8 { Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] pub struct SPEED_R(crate::FieldReader); impl SPEED_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SPEED_R(crate::FieldReader::new(bits)) } @@ -822,6 +831,7 @@ impl From for bool { NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] pub struct MASTER_MODE_R(crate::FieldReader); impl MASTER_MODE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MASTER_MODE_R(crate::FieldReader::new(bits)) } @@ -896,27 +906,39 @@ impl R { pub fn stop_det_if_master_active(&self) -> STOP_DET_IF_MASTER_ACTIVE_R { STOP_DET_IF_MASTER_ACTIVE_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] + #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0."] #[inline(always)] pub fn rx_fifo_full_hld_ctrl(&self) -> RX_FIFO_FULL_HLD_CTRL_R { RX_FIFO_FULL_HLD_CTRL_R::new(((self.bits >> 9) & 0x01) != 0) } - #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] + #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0."] #[inline(always)] pub fn tx_empty_ctrl(&self) -> TX_EMPTY_CTRL_R { TX_EMPTY_CTRL_R::new(((self.bits >> 8) & 0x01) != 0) } - #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] + #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] #[inline(always)] pub fn stop_det_ifaddressed(&self) -> STOP_DET_IFADDRESSED_R { STOP_DET_IFADDRESSED_R::new(((self.bits >> 7) & 0x01) != 0) } - #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] + #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] #[inline(always)] pub fn ic_slave_disable(&self) -> IC_SLAVE_DISABLE_R { IC_SLAVE_DISABLE_R::new(((self.bits >> 6) & 0x01) != 0) } - #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] + #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED"] #[inline(always)] pub fn ic_restart_en(&self) -> IC_RESTART_EN_R { IC_RESTART_EN_R::new(((self.bits >> 5) & 0x01) != 0) @@ -931,39 +953,63 @@ impl R { pub fn ic_10bitaddr_slave(&self) -> IC_10BITADDR_SLAVE_R { IC_10BITADDR_SLAVE_R::new(((self.bits >> 3) & 0x01) != 0) } - #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] + #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] #[inline(always)] pub fn speed(&self) -> SPEED_R { SPEED_R::new(((self.bits >> 1) & 0x03) as u8) } - #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] + #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] #[inline(always)] pub fn master_mode(&self) -> MASTER_MODE_R { MASTER_MODE_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] + #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0."] #[inline(always)] pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { RX_FIFO_FULL_HLD_CTRL_W { w: self } } - #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] + #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0."] #[inline(always)] pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { TX_EMPTY_CTRL_W { w: self } } - #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] + #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] #[inline(always)] pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { STOP_DET_IFADDRESSED_W { w: self } } - #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] + #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] #[inline(always)] pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W { IC_SLAVE_DISABLE_W { w: self } } - #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] + #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED"] #[inline(always)] pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W { IC_RESTART_EN_W { w: self } @@ -978,12 +1024,24 @@ impl W { pub fn ic_10bitaddr_slave(&mut self) -> IC_10BITADDR_SLAVE_W { IC_10BITADDR_SLAVE_W { w: self } } - #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] + #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] #[inline(always)] pub fn speed(&mut self) -> SPEED_W { SPEED_W { w: self } } - #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] + #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] #[inline(always)] pub fn master_mode(&mut self) -> MASTER_MODE_W { MASTER_MODE_W { w: self } diff --git a/src/i2c0/ic_data_cmd.rs b/src/i2c0/ic_data_cmd.rs index 15bc1cf8e..7e78415ab 100644 --- a/src/i2c0/ic_data_cmd.rs +++ b/src/i2c0/ic_data_cmd.rs @@ -79,6 +79,7 @@ impl From for bool { (offset 0x11) if not interested in FIRST_DATA_BYTE status."] pub struct FIRST_DATA_BYTE_R(crate::FieldReader); impl FIRST_DATA_BYTE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FIRST_DATA_BYTE_R(crate::FieldReader::new(bits)) } @@ -139,6 +140,7 @@ impl From for bool { Reset value: 0x0"] pub struct RESTART_R(crate::FieldReader); impl RESTART_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESTART_R(crate::FieldReader::new(bits)) } @@ -234,6 +236,7 @@ impl From for bool { - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] pub struct STOP_R(crate::FieldReader); impl STOP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STOP_R(crate::FieldReader::new(bits)) } @@ -333,6 +336,7 @@ impl From for bool { Reset value: 0x0"] pub struct CMD_R(crate::FieldReader); impl CMD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CMD_R(crate::FieldReader::new(bits)) } @@ -410,6 +414,7 @@ impl<'a> CMD_W<'a> { Reset value: 0x0"] pub struct DAT_R(crate::FieldReader); impl DAT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DAT_R(crate::FieldReader::new(bits)) } @@ -436,52 +441,94 @@ impl<'a> DAT_W<'a> { } } impl R { - #[doc = "Bit 11 - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] + #[doc = "Bit 11 - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] (offset 0x10) and then perform the second read \\[15:8\\] -(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] +(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] (offset 0x11) if not interested in FIRST_DATA_BYTE status."] #[inline(always)] pub fn first_data_byte(&self) -> FIRST_DATA_BYTE_R { FIRST_DATA_BYTE_R::new(((self.bits >> 11) & 0x01) != 0) } - #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"] + #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0"] #[inline(always)] pub fn restart(&self) -> RESTART_R { RESTART_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] + #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] #[inline(always)] pub fn stop(&self) -> STOP_R { STOP_R::new(((self.bits >> 9) & 0x01) != 0) } - #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"] + #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0"] #[inline(always)] pub fn cmd(&self) -> CMD_R { CMD_R::new(((self.bits >> 8) & 0x01) != 0) } - #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] + #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0"] #[inline(always)] pub fn dat(&self) -> DAT_R { DAT_R::new((self.bits & 0xff) as u8) } } impl W { - #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"] + #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0"] #[inline(always)] pub fn restart(&mut self) -> RESTART_W { RESTART_W { w: self } } - #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] + #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] #[inline(always)] pub fn stop(&mut self) -> STOP_W { STOP_W { w: self } } - #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"] + #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0"] #[inline(always)] pub fn cmd(&mut self) -> CMD_W { CMD_W { w: self } } - #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] + #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0"] #[inline(always)] pub fn dat(&mut self) -> DAT_W { DAT_W { w: self } diff --git a/src/i2c0/ic_dma_cr.rs b/src/i2c0/ic_dma_cr.rs index df71fc255..ae29b6a10 100644 --- a/src/i2c0/ic_dma_cr.rs +++ b/src/i2c0/ic_dma_cr.rs @@ -53,6 +53,7 @@ impl From for bool { #[doc = "Field `TDMAE` reader - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] pub struct TDMAE_R(crate::FieldReader); impl TDMAE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TDMAE_R(crate::FieldReader::new(bits)) } @@ -138,6 +139,7 @@ impl From for bool { #[doc = "Field `RDMAE` reader - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] pub struct RDMAE_R(crate::FieldReader); impl RDMAE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RDMAE_R(crate::FieldReader::new(bits)) } diff --git a/src/i2c0/ic_dma_rdlr.rs b/src/i2c0/ic_dma_rdlr.rs index 86da50d59..f95c6df53 100644 --- a/src/i2c0/ic_dma_rdlr.rs +++ b/src/i2c0/ic_dma_rdlr.rs @@ -39,6 +39,7 @@ impl From> for W { Reset value: 0x0"] pub struct DMARDL_R(crate::FieldReader); impl DMARDL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DMARDL_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> DMARDL_W<'a> { } } impl R { - #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] + #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0"] #[inline(always)] pub fn dmardl(&self) -> DMARDL_R { DMARDL_R::new((self.bits & 0x0f) as u8) } } impl W { - #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] + #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0"] #[inline(always)] pub fn dmardl(&mut self) -> DMARDL_W { DMARDL_W { w: self } diff --git a/src/i2c0/ic_dma_tdlr.rs b/src/i2c0/ic_dma_tdlr.rs index d89af1b70..d19cf206a 100644 --- a/src/i2c0/ic_dma_tdlr.rs +++ b/src/i2c0/ic_dma_tdlr.rs @@ -39,6 +39,7 @@ impl From> for W { Reset value: 0x0"] pub struct DMATDL_R(crate::FieldReader); impl DMATDL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DMATDL_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> DMATDL_W<'a> { } } impl R { - #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] + #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0"] #[inline(always)] pub fn dmatdl(&self) -> DMATDL_R { DMATDL_R::new((self.bits & 0x0f) as u8) } } impl W { - #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] + #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0"] #[inline(always)] pub fn dmatdl(&mut self) -> DMATDL_W { DMATDL_W { w: self } diff --git a/src/i2c0/ic_enable.rs b/src/i2c0/ic_enable.rs index 91364de2e..4e5b7f6b2 100644 --- a/src/i2c0/ic_enable.rs +++ b/src/i2c0/ic_enable.rs @@ -55,6 +55,7 @@ impl From for bool { == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] pub struct TX_CMD_BLOCK_R(crate::FieldReader); impl TX_CMD_BLOCK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_CMD_BLOCK_R(crate::FieldReader::new(bits)) } @@ -149,6 +150,7 @@ impl From for bool { Reset value: 0x0"] pub struct ABORT_R(crate::FieldReader); impl ABORT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABORT_R(crate::FieldReader::new(bits)) } @@ -250,6 +252,7 @@ impl From for bool { Reset value: 0x0"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -329,12 +332,22 @@ impl R { pub fn tx_cmd_block(&self) -> TX_CMD_BLOCK_R { TX_CMD_BLOCK_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] + #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0"] #[inline(always)] pub fn abort(&self) -> ABORT_R { ABORT_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] + #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0"] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new((self.bits & 0x01) != 0) @@ -347,12 +360,22 @@ impl W { pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W { TX_CMD_BLOCK_W { w: self } } - #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] + #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0"] #[inline(always)] pub fn abort(&mut self) -> ABORT_W { ABORT_W { w: self } } - #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] + #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0"] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } diff --git a/src/i2c0/ic_enable_status.rs b/src/i2c0/ic_enable_status.rs index de98af4e1..5ff8701f9 100644 --- a/src/i2c0/ic_enable_status.rs +++ b/src/i2c0/ic_enable_status.rs @@ -50,6 +50,7 @@ has been set to 0, then this bit is also set to 1. Reset value: 0x0"] pub struct SLV_RX_DATA_LOST_R(crate::FieldReader); impl SLV_RX_DATA_LOST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLV_RX_DATA_LOST_R(crate::FieldReader::new(bits)) } @@ -132,6 +133,7 @@ has been set to 0, then this bit will also be set to 1. Reset value: 0x0"] pub struct SLV_DISABLED_WHILE_BUSY_R(crate::FieldReader); impl SLV_DISABLED_WHILE_BUSY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLV_DISABLED_WHILE_BUSY_R(crate::FieldReader::new(bits)) } @@ -184,6 +186,7 @@ impl From for bool { Reset value: 0x0"] pub struct IC_EN_R(crate::FieldReader); impl IC_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IC_EN_R(crate::FieldReader::new(bits)) } @@ -214,19 +217,45 @@ impl core::ops::Deref for IC_EN_R { } } impl R { - #[doc = "Bit 2 - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] + #[doc = "Bit 2 - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0"] #[inline(always)] pub fn slv_rx_data_lost(&self) -> SLV_RX_DATA_LOST_R { SLV_RX_DATA_LOST_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] + #[doc = "Bit 1 - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0"] #[inline(always)] pub fn slv_disabled_while_busy(&self) -> SLV_DISABLED_WHILE_BUSY_R { SLV_DISABLED_WHILE_BUSY_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0"] + #[doc = "Bit 0 - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0"] #[inline(always)] pub fn ic_en(&self) -> IC_EN_R { IC_EN_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_fs_scl_hcnt.rs b/src/i2c0/ic_fs_scl_hcnt.rs index 07d692831..12fde1417 100644 --- a/src/i2c0/ic_fs_scl_hcnt.rs +++ b/src/i2c0/ic_fs_scl_hcnt.rs @@ -42,6 +42,7 @@ register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] pub struct IC_FS_SCL_HCNT_R(crate::FieldReader); impl IC_FS_SCL_HCNT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { IC_FS_SCL_HCNT_R(crate::FieldReader::new(bits)) } @@ -71,16 +72,24 @@ impl<'a> IC_FS_SCL_HCNT_W<'a> { } } impl R { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] #[inline(always)] pub fn ic_fs_scl_hcnt(&self) -> IC_FS_SCL_HCNT_R { IC_FS_SCL_HCNT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] #[inline(always)] pub fn ic_fs_scl_hcnt(&mut self) -> IC_FS_SCL_HCNT_W { IC_FS_SCL_HCNT_W { w: self } diff --git a/src/i2c0/ic_fs_scl_lcnt.rs b/src/i2c0/ic_fs_scl_lcnt.rs index 36f4eda60..2059e405a 100644 --- a/src/i2c0/ic_fs_scl_lcnt.rs +++ b/src/i2c0/ic_fs_scl_lcnt.rs @@ -44,6 +44,7 @@ register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] pub struct IC_FS_SCL_LCNT_R(crate::FieldReader); impl IC_FS_SCL_LCNT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { IC_FS_SCL_LCNT_R(crate::FieldReader::new(bits)) } @@ -75,16 +76,28 @@ impl<'a> IC_FS_SCL_LCNT_W<'a> { } } impl R { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] #[inline(always)] pub fn ic_fs_scl_lcnt(&self) -> IC_FS_SCL_LCNT_R { IC_FS_SCL_LCNT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] #[inline(always)] pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W { IC_FS_SCL_LCNT_W { w: self } diff --git a/src/i2c0/ic_fs_spklen.rs b/src/i2c0/ic_fs_spklen.rs index fb0f810ee..ffd89dab2 100644 --- a/src/i2c0/ic_fs_spklen.rs +++ b/src/i2c0/ic_fs_spklen.rs @@ -38,6 +38,7 @@ impl From> for W { register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] pub struct IC_FS_SPKLEN_R(crate::FieldReader); impl IC_FS_SPKLEN_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IC_FS_SPKLEN_R(crate::FieldReader::new(bits)) } diff --git a/src/i2c0/ic_intr_mask.rs b/src/i2c0/ic_intr_mask.rs index c2fe1f14f..05b2d3132 100644 --- a/src/i2c0/ic_intr_mask.rs +++ b/src/i2c0/ic_intr_mask.rs @@ -57,6 +57,7 @@ impl From for bool { Reset value: 0x0"] pub struct M_RESTART_DET_R(crate::FieldReader); impl M_RESTART_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_RESTART_DET_R(crate::FieldReader::new(bits)) } @@ -148,6 +149,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_GEN_CALL_R(crate::FieldReader); impl M_GEN_CALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_GEN_CALL_R(crate::FieldReader::new(bits)) } @@ -239,6 +241,7 @@ impl From for bool { Reset value: 0x0"] pub struct M_START_DET_R(crate::FieldReader); impl M_START_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_START_DET_R(crate::FieldReader::new(bits)) } @@ -330,6 +333,7 @@ impl From for bool { Reset value: 0x0"] pub struct M_STOP_DET_R(crate::FieldReader); impl M_STOP_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_STOP_DET_R(crate::FieldReader::new(bits)) } @@ -421,6 +425,7 @@ impl From for bool { Reset value: 0x0"] pub struct M_ACTIVITY_R(crate::FieldReader); impl M_ACTIVITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_ACTIVITY_R(crate::FieldReader::new(bits)) } @@ -512,6 +517,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_RX_DONE_R(crate::FieldReader); impl M_RX_DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_RX_DONE_R(crate::FieldReader::new(bits)) } @@ -603,6 +609,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_TX_ABRT_R(crate::FieldReader); impl M_TX_ABRT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_TX_ABRT_R(crate::FieldReader::new(bits)) } @@ -694,6 +701,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_RD_REQ_R(crate::FieldReader); impl M_RD_REQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_RD_REQ_R(crate::FieldReader::new(bits)) } @@ -785,6 +793,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_TX_EMPTY_R(crate::FieldReader); impl M_TX_EMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_TX_EMPTY_R(crate::FieldReader::new(bits)) } @@ -876,6 +885,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_TX_OVER_R(crate::FieldReader); impl M_TX_OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_TX_OVER_R(crate::FieldReader::new(bits)) } @@ -967,6 +977,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_RX_FULL_R(crate::FieldReader); impl M_RX_FULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_RX_FULL_R(crate::FieldReader::new(bits)) } @@ -1058,6 +1069,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_RX_OVER_R(crate::FieldReader); impl M_RX_OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_RX_OVER_R(crate::FieldReader::new(bits)) } @@ -1149,6 +1161,7 @@ impl From for bool { Reset value: 0x1"] pub struct M_RX_UNDER_R(crate::FieldReader); impl M_RX_UNDER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { M_RX_UNDER_R(crate::FieldReader::new(bits)) } @@ -1218,134 +1231,186 @@ impl<'a> M_RX_UNDER_W<'a> { } } impl R { - #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn m_restart_det(&self) -> M_RESTART_DET_R { M_RESTART_DET_R::new(((self.bits >> 12) & 0x01) != 0) } - #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_gen_call(&self) -> M_GEN_CALL_R { M_GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) } - #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn m_start_det(&self) -> M_START_DET_R { M_START_DET_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn m_stop_det(&self) -> M_STOP_DET_R { M_STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) } - #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn m_activity(&self) -> M_ACTIVITY_R { M_ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) } - #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rx_done(&self) -> M_RX_DONE_R { M_RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) } - #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_tx_abrt(&self) -> M_TX_ABRT_R { M_TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) } - #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rd_req(&self) -> M_RD_REQ_R { M_RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) } - #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_tx_empty(&self) -> M_TX_EMPTY_R { M_TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) } - #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_tx_over(&self) -> M_TX_OVER_R { M_TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) } - #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rx_full(&self) -> M_RX_FULL_R { M_RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rx_over(&self) -> M_RX_OVER_R { M_RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rx_under(&self) -> M_RX_UNDER_R { M_RX_UNDER_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn m_restart_det(&mut self) -> M_RESTART_DET_W { M_RESTART_DET_W { w: self } } - #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_gen_call(&mut self) -> M_GEN_CALL_W { M_GEN_CALL_W { w: self } } - #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn m_start_det(&mut self) -> M_START_DET_W { M_START_DET_W { w: self } } - #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn m_stop_det(&mut self) -> M_STOP_DET_W { M_STOP_DET_W { w: self } } - #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] #[inline(always)] pub fn m_activity(&mut self) -> M_ACTIVITY_W { M_ACTIVITY_W { w: self } } - #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rx_done(&mut self) -> M_RX_DONE_W { M_RX_DONE_W { w: self } } - #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W { M_TX_ABRT_W { w: self } } - #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rd_req(&mut self) -> M_RD_REQ_W { M_RD_REQ_W { w: self } } - #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W { M_TX_EMPTY_W { w: self } } - #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_tx_over(&mut self) -> M_TX_OVER_W { M_TX_OVER_W { w: self } } - #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rx_full(&mut self) -> M_RX_FULL_W { M_RX_FULL_W { w: self } } - #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rx_over(&mut self) -> M_RX_OVER_W { M_RX_OVER_W { w: self } } - #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] #[inline(always)] pub fn m_rx_under(&mut self) -> M_RX_UNDER_W { M_RX_UNDER_W { w: self } diff --git a/src/i2c0/ic_intr_stat.rs b/src/i2c0/ic_intr_stat.rs index 9de5f702f..5b075d7dc 100644 --- a/src/i2c0/ic_intr_stat.rs +++ b/src/i2c0/ic_intr_stat.rs @@ -36,6 +36,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_RESTART_DET_R(crate::FieldReader); impl R_RESTART_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_RESTART_DET_R(crate::FieldReader::new(bits)) } @@ -88,6 +89,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_GEN_CALL_R(crate::FieldReader); impl R_GEN_CALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_GEN_CALL_R(crate::FieldReader::new(bits)) } @@ -140,6 +142,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_START_DET_R(crate::FieldReader); impl R_START_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_START_DET_R(crate::FieldReader::new(bits)) } @@ -192,6 +195,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_STOP_DET_R(crate::FieldReader); impl R_STOP_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_STOP_DET_R(crate::FieldReader::new(bits)) } @@ -244,6 +248,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_ACTIVITY_R(crate::FieldReader); impl R_ACTIVITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_ACTIVITY_R(crate::FieldReader::new(bits)) } @@ -296,6 +301,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_RX_DONE_R(crate::FieldReader); impl R_RX_DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_RX_DONE_R(crate::FieldReader::new(bits)) } @@ -348,6 +354,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_TX_ABRT_R(crate::FieldReader); impl R_TX_ABRT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_TX_ABRT_R(crate::FieldReader::new(bits)) } @@ -400,6 +407,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_RD_REQ_R(crate::FieldReader); impl R_RD_REQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_RD_REQ_R(crate::FieldReader::new(bits)) } @@ -452,6 +460,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_TX_EMPTY_R(crate::FieldReader); impl R_TX_EMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_TX_EMPTY_R(crate::FieldReader::new(bits)) } @@ -504,6 +513,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_TX_OVER_R(crate::FieldReader); impl R_TX_OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_TX_OVER_R(crate::FieldReader::new(bits)) } @@ -556,6 +566,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_RX_FULL_R(crate::FieldReader); impl R_RX_FULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_RX_FULL_R(crate::FieldReader::new(bits)) } @@ -608,6 +619,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_RX_OVER_R(crate::FieldReader); impl R_RX_OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_RX_OVER_R(crate::FieldReader::new(bits)) } @@ -660,6 +672,7 @@ impl From for bool { Reset value: 0x0"] pub struct R_RX_UNDER_R(crate::FieldReader); impl R_RX_UNDER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { R_RX_UNDER_R(crate::FieldReader::new(bits)) } @@ -690,67 +703,93 @@ impl core::ops::Deref for R_RX_UNDER_R { } } impl R { - #[doc = "Bit 12 - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0"] + #[doc = "Bit 12 - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_restart_det(&self) -> R_RESTART_DET_R { R_RESTART_DET_R::new(((self.bits >> 12) & 0x01) != 0) } - #[doc = "Bit 11 - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0"] + #[doc = "Bit 11 - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_gen_call(&self) -> R_GEN_CALL_R { R_GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) } - #[doc = "Bit 10 - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0"] + #[doc = "Bit 10 - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_start_det(&self) -> R_START_DET_R { R_START_DET_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bit 9 - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0"] + #[doc = "Bit 9 - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_stop_det(&self) -> R_STOP_DET_R { R_STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) } - #[doc = "Bit 8 - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0"] + #[doc = "Bit 8 - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_activity(&self) -> R_ACTIVITY_R { R_ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) } - #[doc = "Bit 7 - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0"] + #[doc = "Bit 7 - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_rx_done(&self) -> R_RX_DONE_R { R_RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) } - #[doc = "Bit 6 - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0"] + #[doc = "Bit 6 - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_tx_abrt(&self) -> R_TX_ABRT_R { R_TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) } - #[doc = "Bit 5 - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0"] + #[doc = "Bit 5 - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_rd_req(&self) -> R_RD_REQ_R { R_RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) } - #[doc = "Bit 4 - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0"] + #[doc = "Bit 4 - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_tx_empty(&self) -> R_TX_EMPTY_R { R_TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) } - #[doc = "Bit 3 - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0"] + #[doc = "Bit 3 - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_tx_over(&self) -> R_TX_OVER_R { R_TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) } - #[doc = "Bit 2 - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0"] + #[doc = "Bit 2 - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_rx_full(&self) -> R_RX_FULL_R { R_RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0"] + #[doc = "Bit 1 - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_rx_over(&self) -> R_RX_OVER_R { R_RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0"] + #[doc = "Bit 0 - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0"] #[inline(always)] pub fn r_rx_under(&self) -> R_RX_UNDER_R { R_RX_UNDER_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_raw_intr_stat.rs b/src/i2c0/ic_raw_intr_stat.rs index a45200dc4..9bd3877f0 100644 --- a/src/i2c0/ic_raw_intr_stat.rs +++ b/src/i2c0/ic_raw_intr_stat.rs @@ -40,6 +40,7 @@ impl From for bool { Reset value: 0x0"] pub struct RESTART_DET_R(crate::FieldReader); impl RESTART_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESTART_DET_R(crate::FieldReader::new(bits)) } @@ -92,6 +93,7 @@ impl From for bool { Reset value: 0x0"] pub struct GEN_CALL_R(crate::FieldReader); impl GEN_CALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GEN_CALL_R(crate::FieldReader::new(bits)) } @@ -144,6 +146,7 @@ impl From for bool { Reset value: 0x0"] pub struct START_DET_R(crate::FieldReader); impl START_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { START_DET_R(crate::FieldReader::new(bits)) } @@ -196,6 +199,7 @@ impl From for bool { In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] pub struct STOP_DET_R(crate::FieldReader); impl STOP_DET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STOP_DET_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl From for bool { Reset value: 0x0"] pub struct ACTIVITY_R(crate::FieldReader); impl ACTIVITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ACTIVITY_R(crate::FieldReader::new(bits)) } @@ -300,6 +305,7 @@ impl From for bool { Reset value: 0x0"] pub struct RX_DONE_R(crate::FieldReader); impl RX_DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_DONE_R(crate::FieldReader::new(bits)) } @@ -356,6 +362,7 @@ impl From for bool { Reset value: 0x0"] pub struct TX_ABRT_R(crate::FieldReader); impl TX_ABRT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_ABRT_R(crate::FieldReader::new(bits)) } @@ -408,6 +415,7 @@ impl From for bool { Reset value: 0x0"] pub struct RD_REQ_R(crate::FieldReader); impl RD_REQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RD_REQ_R(crate::FieldReader::new(bits)) } @@ -462,6 +470,7 @@ is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks l Reset value: 0x0."] pub struct TX_EMPTY_R(crate::FieldReader); impl TX_EMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_EMPTY_R(crate::FieldReader::new(bits)) } @@ -514,6 +523,7 @@ impl From for bool { Reset value: 0x0"] pub struct TX_OVER_R(crate::FieldReader); impl TX_OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_OVER_R(crate::FieldReader::new(bits)) } @@ -566,6 +576,7 @@ impl From for bool { Reset value: 0x0"] pub struct RX_FULL_R(crate::FieldReader); impl RX_FULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_FULL_R(crate::FieldReader::new(bits)) } @@ -622,6 +633,7 @@ impl From for bool { Reset value: 0x0"] pub struct RX_OVER_R(crate::FieldReader); impl RX_OVER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_OVER_R(crate::FieldReader::new(bits)) } @@ -674,6 +686,7 @@ impl From for bool { Reset value: 0x0"] pub struct RX_UNDER_R(crate::FieldReader); impl RX_UNDER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_UNDER_R(crate::FieldReader::new(bits)) } @@ -704,68 +717,100 @@ impl core::ops::Deref for RX_UNDER_R { } } impl R { - #[doc = "Bit 12 - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0"] + #[doc = "Bit 12 - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0"] #[inline(always)] pub fn restart_det(&self) -> RESTART_DET_R { RESTART_DET_R::new(((self.bits >> 12) & 0x01) != 0) } - #[doc = "Bit 11 - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0"] + #[doc = "Bit 11 - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0"] #[inline(always)] pub fn gen_call(&self) -> GEN_CALL_R { GEN_CALL_R::new(((self.bits >> 11) & 0x01) != 0) } - #[doc = "Bit 10 - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0"] + #[doc = "Bit 10 - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0"] #[inline(always)] pub fn start_det(&self) -> START_DET_R { START_DET_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bit 9 - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] + #[doc = "Bit 9 - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] #[inline(always)] pub fn stop_det(&self) -> STOP_DET_R { STOP_DET_R::new(((self.bits >> 9) & 0x01) != 0) } - #[doc = "Bit 8 - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0"] + #[doc = "Bit 8 - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0"] #[inline(always)] pub fn activity(&self) -> ACTIVITY_R { ACTIVITY_R::new(((self.bits >> 8) & 0x01) != 0) } - #[doc = "Bit 7 - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0"] + #[doc = "Bit 7 - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0"] #[inline(always)] pub fn rx_done(&self) -> RX_DONE_R { RX_DONE_R::new(((self.bits >> 7) & 0x01) != 0) } - #[doc = "Bit 6 - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0"] + #[doc = "Bit 6 - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0"] #[inline(always)] pub fn tx_abrt(&self) -> TX_ABRT_R { TX_ABRT_R::new(((self.bits >> 6) & 0x01) != 0) } - #[doc = "Bit 5 - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0"] + #[doc = "Bit 5 - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0"] #[inline(always)] pub fn rd_req(&self) -> RD_REQ_R { RD_REQ_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bit 4 - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] -is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0."] +is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0."] #[inline(always)] pub fn tx_empty(&self) -> TX_EMPTY_R { TX_EMPTY_R::new(((self.bits >> 4) & 0x01) != 0) } - #[doc = "Bit 3 - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] + #[doc = "Bit 3 - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0"] #[inline(always)] pub fn tx_over(&self) -> TX_OVER_R { TX_OVER_R::new(((self.bits >> 3) & 0x01) != 0) } - #[doc = "Bit 2 - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0"] + #[doc = "Bit 2 - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0"] #[inline(always)] pub fn rx_full(&self) -> RX_FULL_R { RX_FULL_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0"] + #[doc = "Bit 1 - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0"] #[inline(always)] pub fn rx_over(&self) -> RX_OVER_R { RX_OVER_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] + #[doc = "Bit 0 - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0"] #[inline(always)] pub fn rx_under(&self) -> RX_UNDER_R { RX_UNDER_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_rx_tl.rs b/src/i2c0/ic_rx_tl.rs index adb166397..f7c76c228 100644 --- a/src/i2c0/ic_rx_tl.rs +++ b/src/i2c0/ic_rx_tl.rs @@ -39,6 +39,7 @@ impl From> for W { Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] pub struct RX_TL_R(crate::FieldReader); impl RX_TL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RX_TL_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> RX_TL_W<'a> { } } impl R { - #[doc = "Bits 0:7 - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] + #[doc = "Bits 0:7 - Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] #[inline(always)] pub fn rx_tl(&self) -> RX_TL_R { RX_TL_R::new((self.bits & 0xff) as u8) } } impl W { - #[doc = "Bits 0:7 - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] + #[doc = "Bits 0:7 - Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] #[inline(always)] pub fn rx_tl(&mut self) -> RX_TL_W { RX_TL_W { w: self } diff --git a/src/i2c0/ic_rxflr.rs b/src/i2c0/ic_rxflr.rs index b9bdaa982..e7083ef1a 100644 --- a/src/i2c0/ic_rxflr.rs +++ b/src/i2c0/ic_rxflr.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct RXFLR_R(crate::FieldReader); impl RXFLR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RXFLR_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for RXFLR_R { } } impl R { - #[doc = "Bits 0:4 - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0"] + #[doc = "Bits 0:4 - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. + + Reset value: 0x0"] #[inline(always)] pub fn rxflr(&self) -> RXFLR_R { RXFLR_R::new((self.bits & 0x1f) as u8) diff --git a/src/i2c0/ic_sar.rs b/src/i2c0/ic_sar.rs index 48e2bb4c2..fe125fc72 100644 --- a/src/i2c0/ic_sar.rs +++ b/src/i2c0/ic_sar.rs @@ -43,6 +43,7 @@ register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <> for a complete list of these reserved values."] pub struct IC_SAR_R(crate::FieldReader); impl IC_SAR_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { IC_SAR_R(crate::FieldReader::new(bits)) } @@ -74,8 +75,12 @@ impl<'a> IC_SAR_W<'a> { } impl R { #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] -is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <> for a complete list of these reserved values."] +is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <> for a complete list of these reserved values."] #[inline(always)] pub fn ic_sar(&self) -> IC_SAR_R { IC_SAR_R::new((self.bits & 0x03ff) as u16) @@ -83,8 +88,12 @@ register being set to 0. Writes at other times have no effect. Note: The default } impl W { #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] -is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <> for a complete list of these reserved values."] +is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <> for a complete list of these reserved values."] #[inline(always)] pub fn ic_sar(&mut self) -> IC_SAR_W { IC_SAR_W { w: self } diff --git a/src/i2c0/ic_sda_hold.rs b/src/i2c0/ic_sda_hold.rs index ec893c16a..ca5511706 100644 --- a/src/i2c0/ic_sda_hold.rs +++ b/src/i2c0/ic_sda_hold.rs @@ -39,6 +39,7 @@ impl From> for W { Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] pub struct IC_SDA_RX_HOLD_R(crate::FieldReader); impl IC_SDA_RX_HOLD_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IC_SDA_RX_HOLD_R(crate::FieldReader::new(bits)) } @@ -69,6 +70,7 @@ impl<'a> IC_SDA_RX_HOLD_W<'a> { Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] pub struct IC_SDA_TX_HOLD_R(crate::FieldReader); impl IC_SDA_TX_HOLD_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { IC_SDA_TX_HOLD_R(crate::FieldReader::new(bits)) } @@ -95,24 +97,32 @@ impl<'a> IC_SDA_TX_HOLD_W<'a> { } } impl R { - #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] + #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] #[inline(always)] pub fn ic_sda_rx_hold(&self) -> IC_SDA_RX_HOLD_R { IC_SDA_RX_HOLD_R::new(((self.bits >> 16) & 0xff) as u8) } - #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] + #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] #[inline(always)] pub fn ic_sda_tx_hold(&self) -> IC_SDA_TX_HOLD_R { IC_SDA_TX_HOLD_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] + #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] #[inline(always)] pub fn ic_sda_rx_hold(&mut self) -> IC_SDA_RX_HOLD_W { IC_SDA_RX_HOLD_W { w: self } } - #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] + #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] #[inline(always)] pub fn ic_sda_tx_hold(&mut self) -> IC_SDA_TX_HOLD_W { IC_SDA_TX_HOLD_W { w: self } diff --git a/src/i2c0/ic_sda_setup.rs b/src/i2c0/ic_sda_setup.rs index c370113bc..7ae837ee4 100644 --- a/src/i2c0/ic_sda_setup.rs +++ b/src/i2c0/ic_sda_setup.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SDA_SETUP` reader - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] pub struct SDA_SETUP_R(crate::FieldReader); impl SDA_SETUP_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SDA_SETUP_R(crate::FieldReader::new(bits)) } diff --git a/src/i2c0/ic_slv_data_nack_only.rs b/src/i2c0/ic_slv_data_nack_only.rs index 71f4f0830..66993c206 100644 --- a/src/i2c0/ic_slv_data_nack_only.rs +++ b/src/i2c0/ic_slv_data_nack_only.rs @@ -57,6 +57,7 @@ impl From for bool { When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] pub struct NACK_R(crate::FieldReader); impl NACK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NACK_R(crate::FieldReader::new(bits)) } @@ -126,14 +127,18 @@ impl<'a> NACK_W<'a> { } } impl R { - #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] + #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] #[inline(always)] pub fn nack(&self) -> NACK_R { NACK_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] + #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] #[inline(always)] pub fn nack(&mut self) -> NACK_W { NACK_W { w: self } diff --git a/src/i2c0/ic_ss_scl_hcnt.rs b/src/i2c0/ic_ss_scl_hcnt.rs index 2e58b5609..ad0d94074 100644 --- a/src/i2c0/ic_ss_scl_hcnt.rs +++ b/src/i2c0/ic_ss_scl_hcnt.rs @@ -44,6 +44,7 @@ register being set to 0. Writes at other times have no effect. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] pub struct IC_SS_SCL_HCNT_R(crate::FieldReader); impl IC_SS_SCL_HCNT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { IC_SS_SCL_HCNT_R(crate::FieldReader::new(bits)) } @@ -75,16 +76,28 @@ impl<'a> IC_SS_SCL_HCNT_W<'a> { } } impl R { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] #[inline(always)] pub fn ic_ss_scl_hcnt(&self) -> IC_SS_SCL_HCNT_R { IC_SS_SCL_HCNT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] #[inline(always)] pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W { IC_SS_SCL_HCNT_W { w: self } diff --git a/src/i2c0/ic_ss_scl_lcnt.rs b/src/i2c0/ic_ss_scl_lcnt.rs index a3b47a325..d144cb410 100644 --- a/src/i2c0/ic_ss_scl_lcnt.rs +++ b/src/i2c0/ic_ss_scl_lcnt.rs @@ -42,6 +42,7 @@ register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] pub struct IC_SS_SCL_LCNT_R(crate::FieldReader); impl IC_SS_SCL_LCNT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { IC_SS_SCL_LCNT_R(crate::FieldReader::new(bits)) } @@ -71,16 +72,24 @@ impl<'a> IC_SS_SCL_LCNT_W<'a> { } } impl R { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] #[inline(always)] pub fn ic_ss_scl_lcnt(&self) -> IC_SS_SCL_LCNT_R { IC_SS_SCL_LCNT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] #[inline(always)] pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W { IC_SS_SCL_LCNT_W { w: self } diff --git a/src/i2c0/ic_status.rs b/src/i2c0/ic_status.rs index 02019952a..4b5ccc792 100644 --- a/src/i2c0/ic_status.rs +++ b/src/i2c0/ic_status.rs @@ -32,6 +32,7 @@ impl From for bool { #[doc = "Field `SLV_ACTIVITY` reader - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0"] pub struct SLV_ACTIVITY_R(crate::FieldReader); impl SLV_ACTIVITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLV_ACTIVITY_R(crate::FieldReader::new(bits)) } @@ -84,6 +85,7 @@ impl From for bool { Reset value: 0x0"] pub struct MST_ACTIVITY_R(crate::FieldReader); impl MST_ACTIVITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MST_ACTIVITY_R(crate::FieldReader::new(bits)) } @@ -132,6 +134,7 @@ impl From for bool { #[doc = "Field `RFF` reader - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0"] pub struct RFF_R(crate::FieldReader); impl RFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RFF_R(crate::FieldReader::new(bits)) } @@ -180,6 +183,7 @@ impl From for bool { #[doc = "Field `RFNE` reader - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0"] pub struct RFNE_R(crate::FieldReader); impl RFNE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RFNE_R(crate::FieldReader::new(bits)) } @@ -228,6 +232,7 @@ impl From for bool { #[doc = "Field `TFE` reader - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1"] pub struct TFE_R(crate::FieldReader); impl TFE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TFE_R(crate::FieldReader::new(bits)) } @@ -276,6 +281,7 @@ impl From for bool { #[doc = "Field `TFNF` reader - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1"] pub struct TFNF_R(crate::FieldReader); impl TFNF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TFNF_R(crate::FieldReader::new(bits)) } @@ -324,6 +330,7 @@ impl From for bool { #[doc = "Field `ACTIVITY` reader - I2C Activity Status. Reset value: 0x0"] pub struct ACTIVITY_R(crate::FieldReader); impl ACTIVITY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ACTIVITY_R(crate::FieldReader::new(bits)) } @@ -359,7 +366,9 @@ impl R { pub fn slv_activity(&self) -> SLV_ACTIVITY_R { SLV_ACTIVITY_R::new(((self.bits >> 6) & 0x01) != 0) } - #[doc = "Bit 5 - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0"] + #[doc = "Bit 5 - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0"] #[inline(always)] pub fn mst_activity(&self) -> MST_ACTIVITY_R { MST_ACTIVITY_R::new(((self.bits >> 5) & 0x01) != 0) diff --git a/src/i2c0/ic_tar.rs b/src/i2c0/ic_tar.rs index 0d3dee909..db6989a7b 100644 --- a/src/i2c0/ic_tar.rs +++ b/src/i2c0/ic_tar.rs @@ -53,6 +53,7 @@ impl From for bool { #[doc = "Field `SPECIAL` reader - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] pub struct SPECIAL_R(crate::FieldReader); impl SPECIAL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPECIAL_R(crate::FieldReader::new(bits)) } @@ -138,6 +139,7 @@ impl From for bool { #[doc = "Field `GC_OR_START` reader - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] pub struct GC_OR_START_R(crate::FieldReader); impl GC_OR_START_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GC_OR_START_R(crate::FieldReader::new(bits)) } @@ -209,6 +211,7 @@ impl<'a> GC_OR_START_W<'a> { If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] pub struct IC_TAR_R(crate::FieldReader); impl IC_TAR_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { IC_TAR_R(crate::FieldReader::new(bits)) } @@ -245,7 +248,9 @@ impl R { pub fn gc_or_start(&self) -> GC_OR_START_R { GC_OR_START_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] + #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] #[inline(always)] pub fn ic_tar(&self) -> IC_TAR_R { IC_TAR_R::new((self.bits & 0x03ff) as u16) @@ -262,7 +267,9 @@ impl W { pub fn gc_or_start(&mut self) -> GC_OR_START_W { GC_OR_START_W { w: self } } - #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] + #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] #[inline(always)] pub fn ic_tar(&mut self) -> IC_TAR_W { IC_TAR_W { w: self } diff --git a/src/i2c0/ic_tx_abrt_source.rs b/src/i2c0/ic_tx_abrt_source.rs index 0a58af2df..5e119dc7d 100644 --- a/src/i2c0/ic_tx_abrt_source.rs +++ b/src/i2c0/ic_tx_abrt_source.rs @@ -20,6 +20,7 @@ impl From> for R { Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] pub struct TX_FLUSH_CNT_R(crate::FieldReader); impl TX_FLUSH_CNT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { TX_FLUSH_CNT_R(crate::FieldReader::new(bits)) } @@ -58,6 +59,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Transmitter"] pub struct ABRT_USER_ABRT_R(crate::FieldReader); impl ABRT_USER_ABRT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_USER_ABRT_R(crate::FieldReader::new(bits)) } @@ -114,6 +116,7 @@ impl From for bool { Role of DW_apb_i2c: Slave-Transmitter"] pub struct ABRT_SLVRD_INTX_R(crate::FieldReader); impl ABRT_SLVRD_INTX_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_SLVRD_INTX_R(crate::FieldReader::new(bits)) } @@ -172,6 +175,7 @@ is set at the same time. Note: Even though the slave never 'owns' the bus, somet Role of DW_apb_i2c: Slave-Transmitter"] pub struct ABRT_SLV_ARBLOST_R(crate::FieldReader); impl ABRT_SLV_ARBLOST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_SLV_ARBLOST_R(crate::FieldReader::new(bits)) } @@ -228,6 +232,7 @@ impl From for bool { Role of DW_apb_i2c: Slave-Transmitter"] pub struct ABRT_SLVFLUSH_TXFIFO_R(crate::FieldReader); impl ABRT_SLVFLUSH_TXFIFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_SLVFLUSH_TXFIFO_R(crate::FieldReader::new(bits)) } @@ -286,6 +291,7 @@ is also set, then the slave transmitter has lost arbitration. Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] pub struct ARB_LOST_R(crate::FieldReader); impl ARB_LOST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ARB_LOST_R(crate::FieldReader::new(bits)) } @@ -342,6 +348,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub struct ABRT_MASTER_DIS_R(crate::FieldReader); impl ABRT_MASTER_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_MASTER_DIS_R(crate::FieldReader::new(bits)) } @@ -398,6 +405,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Receiver"] pub struct ABRT_10B_RD_NORSTRT_R(crate::FieldReader); impl ABRT_10B_RD_NORSTRT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_10B_RD_NORSTRT_R(crate::FieldReader::new(bits)) } @@ -454,6 +462,7 @@ impl From for bool { Role of DW_apb_i2c: Master"] pub struct ABRT_SBYTE_NORSTRT_R(crate::FieldReader); impl ABRT_SBYTE_NORSTRT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_SBYTE_NORSTRT_R(crate::FieldReader::new(bits)) } @@ -510,6 +519,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub struct ABRT_HS_NORSTRT_R(crate::FieldReader); impl ABRT_HS_NORSTRT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_HS_NORSTRT_R(crate::FieldReader::new(bits)) } @@ -566,6 +576,7 @@ impl From for bool { Role of DW_apb_i2c: Master"] pub struct ABRT_SBYTE_ACKDET_R(crate::FieldReader); impl ABRT_SBYTE_ACKDET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_SBYTE_ACKDET_R(crate::FieldReader::new(bits)) } @@ -622,6 +633,7 @@ impl From for bool { Role of DW_apb_i2c: Master"] pub struct ABRT_HS_ACKDET_R(crate::FieldReader); impl ABRT_HS_ACKDET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_HS_ACKDET_R(crate::FieldReader::new(bits)) } @@ -680,6 +692,7 @@ is set to 1). Role of DW_apb_i2c: Master-Transmitter"] pub struct ABRT_GCALL_READ_R(crate::FieldReader); impl ABRT_GCALL_READ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_GCALL_READ_R(crate::FieldReader::new(bits)) } @@ -736,6 +749,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Transmitter"] pub struct ABRT_GCALL_NOACK_R(crate::FieldReader); impl ABRT_GCALL_NOACK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_GCALL_NOACK_R(crate::FieldReader::new(bits)) } @@ -792,6 +806,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Transmitter"] pub struct ABRT_TXDATA_NOACK_R(crate::FieldReader); impl ABRT_TXDATA_NOACK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_TXDATA_NOACK_R(crate::FieldReader::new(bits)) } @@ -848,6 +863,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub struct ABRT_10ADDR2_NOACK_R(crate::FieldReader); impl ABRT_10ADDR2_NOACK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_10ADDR2_NOACK_R(crate::FieldReader::new(bits)) } @@ -904,6 +920,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub struct ABRT_10ADDR1_NOACK_R(crate::FieldReader); impl ABRT_10ADDR1_NOACK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_10ADDR1_NOACK_R(crate::FieldReader::new(bits)) } @@ -960,6 +977,7 @@ impl From for bool { Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub struct ABRT_7B_ADDR_NOACK_R(crate::FieldReader); impl ABRT_7B_ADDR_NOACK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABRT_7B_ADDR_NOACK_R(crate::FieldReader::new(bits)) } @@ -990,95 +1008,167 @@ impl core::ops::Deref for ABRT_7B_ADDR_NOACK_R { } } impl R { - #[doc = "Bits 23:31 - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] + #[doc = "Bits 23:31 - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] #[inline(always)] pub fn tx_flush_cnt(&self) -> TX_FLUSH_CNT_R { TX_FLUSH_CNT_R::new(((self.bits >> 23) & 0x01ff) as u16) } - #[doc = "Bit 16 - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] + #[doc = "Bit 16 - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter"] #[inline(always)] pub fn abrt_user_abrt(&self) -> ABRT_USER_ABRT_R { ABRT_USER_ABRT_R::new(((self.bits >> 16) & 0x01) != 0) } - #[doc = "Bit 15 - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] + #[doc = "Bit 15 - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter"] #[inline(always)] pub fn abrt_slvrd_intx(&self) -> ABRT_SLVRD_INTX_R { ABRT_SLVRD_INTX_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bit 14 - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] -is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] +is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter"] #[inline(always)] pub fn abrt_slv_arblost(&self) -> ABRT_SLV_ARBLOST_R { ABRT_SLV_ARBLOST_R::new(((self.bits >> 14) & 0x01) != 0) } - #[doc = "Bit 13 - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] + #[doc = "Bit 13 - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter"] #[inline(always)] pub fn abrt_slvflush_txfifo(&self) -> ABRT_SLVFLUSH_TXFIFO_R { ABRT_SLVFLUSH_TXFIFO_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bit 12 - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] -is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] +is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] #[inline(always)] pub fn arb_lost(&self) -> ARB_LOST_R { ARB_LOST_R::new(((self.bits >> 12) & 0x01) != 0) } - #[doc = "Bit 11 - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 11 - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_master_dis(&self) -> ABRT_MASTER_DIS_R { ABRT_MASTER_DIS_R::new(((self.bits >> 11) & 0x01) != 0) } - #[doc = "Bit 10 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver"] + #[doc = "Bit 10 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver"] #[inline(always)] pub fn abrt_10b_rd_norstrt(&self) -> ABRT_10B_RD_NORSTRT_R { ABRT_10B_RD_NORSTRT_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bit 9 - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master"] + #[doc = "Bit 9 - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master"] #[inline(always)] pub fn abrt_sbyte_norstrt(&self) -> ABRT_SBYTE_NORSTRT_R { ABRT_SBYTE_NORSTRT_R::new(((self.bits >> 9) & 0x01) != 0) } - #[doc = "Bit 8 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 8 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_hs_norstrt(&self) -> ABRT_HS_NORSTRT_R { ABRT_HS_NORSTRT_R::new(((self.bits >> 8) & 0x01) != 0) } - #[doc = "Bit 7 - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] + #[doc = "Bit 7 - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master"] #[inline(always)] pub fn abrt_sbyte_ackdet(&self) -> ABRT_SBYTE_ACKDET_R { ABRT_SBYTE_ACKDET_R::new(((self.bits >> 7) & 0x01) != 0) } - #[doc = "Bit 6 - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] + #[doc = "Bit 6 - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master"] #[inline(always)] pub fn abrt_hs_ackdet(&self) -> ABRT_HS_ACKDET_R { ABRT_HS_ACKDET_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 5 - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] -is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] +is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter"] #[inline(always)] pub fn abrt_gcall_read(&self) -> ABRT_GCALL_READ_R { ABRT_GCALL_READ_R::new(((self.bits >> 5) & 0x01) != 0) } - #[doc = "Bit 4 - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] + #[doc = "Bit 4 - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter"] #[inline(always)] pub fn abrt_gcall_noack(&self) -> ABRT_GCALL_NOACK_R { ABRT_GCALL_NOACK_R::new(((self.bits >> 4) & 0x01) != 0) } - #[doc = "Bit 3 - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] + #[doc = "Bit 3 - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter"] #[inline(always)] pub fn abrt_txdata_noack(&self) -> ABRT_TXDATA_NOACK_R { ABRT_TXDATA_NOACK_R::new(((self.bits >> 3) & 0x01) != 0) } - #[doc = "Bit 2 - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 2 - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_10addr2_noack(&self) -> ABRT_10ADDR2_NOACK_R { ABRT_10ADDR2_NOACK_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 1 - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_10addr1_noack(&self) -> ABRT_10ADDR1_NOACK_R { ABRT_10ADDR1_NOACK_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 0 - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_7b_addr_noack(&self) -> ABRT_7B_ADDR_NOACK_R { ABRT_7B_ADDR_NOACK_R::new((self.bits & 0x01) != 0) diff --git a/src/i2c0/ic_tx_tl.rs b/src/i2c0/ic_tx_tl.rs index 93a34f8df..695edfda7 100644 --- a/src/i2c0/ic_tx_tl.rs +++ b/src/i2c0/ic_tx_tl.rs @@ -39,6 +39,7 @@ impl From> for W { Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] pub struct TX_TL_R(crate::FieldReader); impl TX_TL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TX_TL_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> TX_TL_W<'a> { } } impl R { - #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] + #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] #[inline(always)] pub fn tx_tl(&self) -> TX_TL_R { TX_TL_R::new((self.bits & 0xff) as u8) } } impl W { - #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] + #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] #[inline(always)] pub fn tx_tl(&mut self) -> TX_TL_W { TX_TL_W { w: self } diff --git a/src/i2c0/ic_txflr.rs b/src/i2c0/ic_txflr.rs index 9027e9290..a1f55d6be 100644 --- a/src/i2c0/ic_txflr.rs +++ b/src/i2c0/ic_txflr.rs @@ -18,6 +18,7 @@ impl From> for R { Reset value: 0x0"] pub struct TXFLR_R(crate::FieldReader); impl TXFLR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TXFLR_R(crate::FieldReader::new(bits)) } @@ -30,7 +31,9 @@ impl core::ops::Deref for TXFLR_R { } } impl R { - #[doc = "Bits 0:4 - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0"] + #[doc = "Bits 0:4 - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. + + Reset value: 0x0"] #[inline(always)] pub fn txflr(&self) -> TXFLR_R { TXFLR_R::new((self.bits & 0x1f) as u8) diff --git a/src/io_bank0/dormant_wake_inte.rs b/src/io_bank0/dormant_wake_inte.rs index 7c341f162..585af06ba 100644 --- a/src/io_bank0/dormant_wake_inte.rs +++ b/src/io_bank0/dormant_wake_inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO7_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO7_EDGE_LOW_W<'a> { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO7_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO7_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO6_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO6_EDGE_LOW_W<'a> { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO6_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO6_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO5_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO5_EDGE_LOW_W<'a> { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO5_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO5_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO4_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO4_EDGE_LOW_W<'a> { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO4_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO4_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> GPIO2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> GPIO1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> GPIO1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> GPIO1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> GPIO1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> GPIO0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> GPIO0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> GPIO0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/dormant_wake_intf.rs b/src/io_bank0/dormant_wake_intf.rs index 37b5c3800..1eb2b8922 100644 --- a/src/io_bank0/dormant_wake_intf.rs +++ b/src/io_bank0/dormant_wake_intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO7_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO7_EDGE_LOW_W<'a> { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO7_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO7_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO6_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO6_EDGE_LOW_W<'a> { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO6_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO6_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO5_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO5_EDGE_LOW_W<'a> { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO5_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO5_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO4_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO4_EDGE_LOW_W<'a> { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO4_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO4_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> GPIO2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> GPIO1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> GPIO1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> GPIO1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> GPIO1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> GPIO0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> GPIO0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> GPIO0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/dormant_wake_ints.rs b/src/io_bank0/dormant_wake_ints.rs index 8fcf83694..7d8c4a2bb 100644 --- a/src/io_bank0/dormant_wake_ints.rs +++ b/src/io_bank0/dormant_wake_ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for GPIO7_EDGE_HIGH_R { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for GPIO7_EDGE_LOW_R { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for GPIO7_LEVEL_HIGH_R { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for GPIO7_LEVEL_LOW_R { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for GPIO6_EDGE_HIGH_R { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for GPIO6_EDGE_LOW_R { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for GPIO6_LEVEL_HIGH_R { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for GPIO6_LEVEL_LOW_R { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for GPIO5_EDGE_HIGH_R { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for GPIO5_EDGE_LOW_R { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for GPIO5_LEVEL_HIGH_R { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for GPIO5_LEVEL_LOW_R { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for GPIO4_EDGE_HIGH_R { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for GPIO4_EDGE_LOW_R { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for GPIO4_LEVEL_HIGH_R { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for GPIO4_LEVEL_LOW_R { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for GPIO3_EDGE_HIGH_R { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for GPIO3_EDGE_LOW_R { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for GPIO3_LEVEL_HIGH_R { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for GPIO3_LEVEL_LOW_R { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for GPIO2_EDGE_HIGH_R { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for GPIO2_EDGE_LOW_R { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for GPIO2_LEVEL_HIGH_R { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -352,6 +376,7 @@ impl core::ops::Deref for GPIO2_LEVEL_LOW_R { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -366,6 +391,7 @@ impl core::ops::Deref for GPIO1_EDGE_HIGH_R { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -380,6 +406,7 @@ impl core::ops::Deref for GPIO1_EDGE_LOW_R { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -394,6 +421,7 @@ impl core::ops::Deref for GPIO1_LEVEL_HIGH_R { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -408,6 +436,7 @@ impl core::ops::Deref for GPIO1_LEVEL_LOW_R { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -422,6 +451,7 @@ impl core::ops::Deref for GPIO0_EDGE_HIGH_R { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -436,6 +466,7 @@ impl core::ops::Deref for GPIO0_EDGE_LOW_R { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -450,6 +481,7 @@ impl core::ops::Deref for GPIO0_LEVEL_HIGH_R { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/gpio/gpio_ctrl.rs b/src/io_bank0/gpio/gpio_ctrl.rs index 7b842cc7f..432310a97 100644 --- a/src/io_bank0/gpio/gpio_ctrl.rs +++ b/src/io_bank0/gpio/gpio_ctrl.rs @@ -58,6 +58,7 @@ impl From for u8 { #[doc = "Field `IRQOVER` reader - "] pub struct IRQOVER_R(crate::FieldReader); impl IRQOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IRQOVER_R(crate::FieldReader::new(bits)) } @@ -161,6 +162,7 @@ impl From for u8 { #[doc = "Field `INOVER` reader - "] pub struct INOVER_R(crate::FieldReader); impl INOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { INOVER_R(crate::FieldReader::new(bits)) } @@ -264,6 +266,7 @@ impl From for u8 { #[doc = "Field `OEOVER` reader - "] pub struct OEOVER_R(crate::FieldReader); impl OEOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { OEOVER_R(crate::FieldReader::new(bits)) } @@ -367,6 +370,7 @@ impl From for u8 { #[doc = "Field `OUTOVER` reader - "] pub struct OUTOVER_R(crate::FieldReader); impl OUTOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { OUTOVER_R(crate::FieldReader::new(bits)) } @@ -484,6 +488,7 @@ impl From for u8 { 31 == NULL"] pub struct FUNCSEL_R(crate::FieldReader); impl FUNCSEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FUNCSEL_R(crate::FieldReader::new(bits)) } @@ -651,7 +656,8 @@ impl R { pub fn outover(&self) -> OUTOVER_R { OUTOVER_R::new(((self.bits >> 8) & 0x03) as u8) } - #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table + 31 == NULL"] #[inline(always)] pub fn funcsel(&self) -> FUNCSEL_R { FUNCSEL_R::new((self.bits & 0x1f) as u8) @@ -678,7 +684,8 @@ impl W { pub fn outover(&mut self) -> OUTOVER_W { OUTOVER_W { w: self } } - #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table + 31 == NULL"] #[inline(always)] pub fn funcsel(&mut self) -> FUNCSEL_W { FUNCSEL_W { w: self } diff --git a/src/io_bank0/gpio/gpio_status.rs b/src/io_bank0/gpio/gpio_status.rs index d7b155d8d..f689ec745 100644 --- a/src/io_bank0/gpio/gpio_status.rs +++ b/src/io_bank0/gpio/gpio_status.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `IRQTOPROC` reader - interrupt to processors, after override is applied"] pub struct IRQTOPROC_R(crate::FieldReader); impl IRQTOPROC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IRQTOPROC_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for IRQTOPROC_R { #[doc = "Field `IRQFROMPAD` reader - interrupt from pad before override is applied"] pub struct IRQFROMPAD_R(crate::FieldReader); impl IRQFROMPAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IRQFROMPAD_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for IRQFROMPAD_R { #[doc = "Field `INTOPERI` reader - input signal to peripheral, after override is applied"] pub struct INTOPERI_R(crate::FieldReader); impl INTOPERI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTOPERI_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for INTOPERI_R { #[doc = "Field `INFROMPAD` reader - input signal from pad, before override is applied"] pub struct INFROMPAD_R(crate::FieldReader); impl INFROMPAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INFROMPAD_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for INFROMPAD_R { #[doc = "Field `OETOPAD` reader - output enable to pad after register override is applied"] pub struct OETOPAD_R(crate::FieldReader); impl OETOPAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OETOPAD_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for OETOPAD_R { #[doc = "Field `OEFROMPERI` reader - output enable from selected peripheral, before register override is applied"] pub struct OEFROMPERI_R(crate::FieldReader); impl OEFROMPERI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OEFROMPERI_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for OEFROMPERI_R { #[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] pub struct OUTTOPAD_R(crate::FieldReader); impl OUTTOPAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUTTOPAD_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for OUTTOPAD_R { #[doc = "Field `OUTFROMPERI` reader - output signal from selected peripheral, before register override is applied"] pub struct OUTFROMPERI_R(crate::FieldReader); impl OUTFROMPERI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUTFROMPERI_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/intr.rs b/src/io_bank0/intr.rs index 87aaaa88b..addc725f1 100644 --- a/src/io_bank0/intr.rs +++ b/src/io_bank0/intr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO7_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO7_EDGE_LOW_W<'a> { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -123,6 +126,7 @@ impl core::ops::Deref for GPIO7_LEVEL_HIGH_R { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -137,6 +141,7 @@ impl core::ops::Deref for GPIO7_LEVEL_LOW_R { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -173,6 +178,7 @@ impl<'a> GPIO6_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -209,6 +215,7 @@ impl<'a> GPIO6_EDGE_LOW_W<'a> { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -223,6 +230,7 @@ impl core::ops::Deref for GPIO6_LEVEL_HIGH_R { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -237,6 +245,7 @@ impl core::ops::Deref for GPIO6_LEVEL_LOW_R { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -273,6 +282,7 @@ impl<'a> GPIO5_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -309,6 +319,7 @@ impl<'a> GPIO5_EDGE_LOW_W<'a> { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -323,6 +334,7 @@ impl core::ops::Deref for GPIO5_LEVEL_HIGH_R { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -337,6 +349,7 @@ impl core::ops::Deref for GPIO5_LEVEL_LOW_R { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -373,6 +386,7 @@ impl<'a> GPIO4_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -409,6 +423,7 @@ impl<'a> GPIO4_EDGE_LOW_W<'a> { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -423,6 +438,7 @@ impl core::ops::Deref for GPIO4_LEVEL_HIGH_R { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -437,6 +453,7 @@ impl core::ops::Deref for GPIO4_LEVEL_LOW_R { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -473,6 +490,7 @@ impl<'a> GPIO3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -509,6 +527,7 @@ impl<'a> GPIO3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -523,6 +542,7 @@ impl core::ops::Deref for GPIO3_LEVEL_HIGH_R { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -537,6 +557,7 @@ impl core::ops::Deref for GPIO3_LEVEL_LOW_R { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -573,6 +594,7 @@ impl<'a> GPIO2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -609,6 +631,7 @@ impl<'a> GPIO2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -623,6 +646,7 @@ impl core::ops::Deref for GPIO2_LEVEL_HIGH_R { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -637,6 +661,7 @@ impl core::ops::Deref for GPIO2_LEVEL_LOW_R { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -673,6 +698,7 @@ impl<'a> GPIO1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -709,6 +735,7 @@ impl<'a> GPIO1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -723,6 +750,7 @@ impl core::ops::Deref for GPIO1_LEVEL_HIGH_R { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -737,6 +765,7 @@ impl core::ops::Deref for GPIO1_LEVEL_LOW_R { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -773,6 +802,7 @@ impl<'a> GPIO0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -809,6 +839,7 @@ impl<'a> GPIO0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -823,6 +854,7 @@ impl core::ops::Deref for GPIO0_LEVEL_HIGH_R { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/proc0_inte.rs b/src/io_bank0/proc0_inte.rs index 029635eec..5be56cf3e 100644 --- a/src/io_bank0/proc0_inte.rs +++ b/src/io_bank0/proc0_inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO7_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO7_EDGE_LOW_W<'a> { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO7_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO7_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO6_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO6_EDGE_LOW_W<'a> { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO6_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO6_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO5_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO5_EDGE_LOW_W<'a> { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO5_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO5_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO4_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO4_EDGE_LOW_W<'a> { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO4_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO4_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> GPIO2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> GPIO1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> GPIO1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> GPIO1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> GPIO1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> GPIO0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> GPIO0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> GPIO0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/proc0_intf.rs b/src/io_bank0/proc0_intf.rs index a65c182a7..2c4629358 100644 --- a/src/io_bank0/proc0_intf.rs +++ b/src/io_bank0/proc0_intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO7_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO7_EDGE_LOW_W<'a> { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO7_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO7_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO6_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO6_EDGE_LOW_W<'a> { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO6_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO6_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO5_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO5_EDGE_LOW_W<'a> { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO5_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO5_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO4_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO4_EDGE_LOW_W<'a> { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO4_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO4_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> GPIO2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> GPIO1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> GPIO1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> GPIO1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> GPIO1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> GPIO0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> GPIO0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> GPIO0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/proc0_ints.rs b/src/io_bank0/proc0_ints.rs index f9be6e12f..5de8ebbd9 100644 --- a/src/io_bank0/proc0_ints.rs +++ b/src/io_bank0/proc0_ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for GPIO7_EDGE_HIGH_R { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for GPIO7_EDGE_LOW_R { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for GPIO7_LEVEL_HIGH_R { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for GPIO7_LEVEL_LOW_R { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for GPIO6_EDGE_HIGH_R { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for GPIO6_EDGE_LOW_R { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for GPIO6_LEVEL_HIGH_R { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for GPIO6_LEVEL_LOW_R { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for GPIO5_EDGE_HIGH_R { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for GPIO5_EDGE_LOW_R { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for GPIO5_LEVEL_HIGH_R { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for GPIO5_LEVEL_LOW_R { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for GPIO4_EDGE_HIGH_R { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for GPIO4_EDGE_LOW_R { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for GPIO4_LEVEL_HIGH_R { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for GPIO4_LEVEL_LOW_R { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for GPIO3_EDGE_HIGH_R { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for GPIO3_EDGE_LOW_R { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for GPIO3_LEVEL_HIGH_R { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for GPIO3_LEVEL_LOW_R { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for GPIO2_EDGE_HIGH_R { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for GPIO2_EDGE_LOW_R { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for GPIO2_LEVEL_HIGH_R { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -352,6 +376,7 @@ impl core::ops::Deref for GPIO2_LEVEL_LOW_R { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -366,6 +391,7 @@ impl core::ops::Deref for GPIO1_EDGE_HIGH_R { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -380,6 +406,7 @@ impl core::ops::Deref for GPIO1_EDGE_LOW_R { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -394,6 +421,7 @@ impl core::ops::Deref for GPIO1_LEVEL_HIGH_R { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -408,6 +436,7 @@ impl core::ops::Deref for GPIO1_LEVEL_LOW_R { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -422,6 +451,7 @@ impl core::ops::Deref for GPIO0_EDGE_HIGH_R { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -436,6 +466,7 @@ impl core::ops::Deref for GPIO0_EDGE_LOW_R { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -450,6 +481,7 @@ impl core::ops::Deref for GPIO0_LEVEL_HIGH_R { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/proc1_inte.rs b/src/io_bank0/proc1_inte.rs index 8e29e7ce8..d3abfc825 100644 --- a/src/io_bank0/proc1_inte.rs +++ b/src/io_bank0/proc1_inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO7_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO7_EDGE_LOW_W<'a> { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO7_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO7_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO6_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO6_EDGE_LOW_W<'a> { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO6_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO6_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO5_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO5_EDGE_LOW_W<'a> { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO5_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO5_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO4_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO4_EDGE_LOW_W<'a> { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO4_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO4_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> GPIO2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> GPIO1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> GPIO1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> GPIO1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> GPIO1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> GPIO0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> GPIO0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> GPIO0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/proc1_intf.rs b/src/io_bank0/proc1_intf.rs index fd88fb2c2..4d9576ff2 100644 --- a/src/io_bank0/proc1_intf.rs +++ b/src/io_bank0/proc1_intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO7_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO7_EDGE_LOW_W<'a> { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO7_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO7_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO6_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO6_EDGE_LOW_W<'a> { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO6_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO6_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO5_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO5_EDGE_LOW_W<'a> { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO5_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO5_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO4_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO4_EDGE_LOW_W<'a> { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO4_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO4_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> GPIO2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> GPIO1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> GPIO1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> GPIO1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> GPIO1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> GPIO0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> GPIO0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> GPIO0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_bank0/proc1_ints.rs b/src/io_bank0/proc1_ints.rs index f3b6aded3..249803004 100644 --- a/src/io_bank0/proc1_ints.rs +++ b/src/io_bank0/proc1_ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `GPIO7_EDGE_HIGH` reader - "] pub struct GPIO7_EDGE_HIGH_R(crate::FieldReader); impl GPIO7_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for GPIO7_EDGE_HIGH_R { #[doc = "Field `GPIO7_EDGE_LOW` reader - "] pub struct GPIO7_EDGE_LOW_R(crate::FieldReader); impl GPIO7_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for GPIO7_EDGE_LOW_R { #[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] pub struct GPIO7_LEVEL_HIGH_R(crate::FieldReader); impl GPIO7_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for GPIO7_LEVEL_HIGH_R { #[doc = "Field `GPIO7_LEVEL_LOW` reader - "] pub struct GPIO7_LEVEL_LOW_R(crate::FieldReader); impl GPIO7_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO7_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for GPIO7_LEVEL_LOW_R { #[doc = "Field `GPIO6_EDGE_HIGH` reader - "] pub struct GPIO6_EDGE_HIGH_R(crate::FieldReader); impl GPIO6_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for GPIO6_EDGE_HIGH_R { #[doc = "Field `GPIO6_EDGE_LOW` reader - "] pub struct GPIO6_EDGE_LOW_R(crate::FieldReader); impl GPIO6_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for GPIO6_EDGE_LOW_R { #[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] pub struct GPIO6_LEVEL_HIGH_R(crate::FieldReader); impl GPIO6_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for GPIO6_LEVEL_HIGH_R { #[doc = "Field `GPIO6_LEVEL_LOW` reader - "] pub struct GPIO6_LEVEL_LOW_R(crate::FieldReader); impl GPIO6_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO6_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for GPIO6_LEVEL_LOW_R { #[doc = "Field `GPIO5_EDGE_HIGH` reader - "] pub struct GPIO5_EDGE_HIGH_R(crate::FieldReader); impl GPIO5_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for GPIO5_EDGE_HIGH_R { #[doc = "Field `GPIO5_EDGE_LOW` reader - "] pub struct GPIO5_EDGE_LOW_R(crate::FieldReader); impl GPIO5_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for GPIO5_EDGE_LOW_R { #[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] pub struct GPIO5_LEVEL_HIGH_R(crate::FieldReader); impl GPIO5_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for GPIO5_LEVEL_HIGH_R { #[doc = "Field `GPIO5_LEVEL_LOW` reader - "] pub struct GPIO5_LEVEL_LOW_R(crate::FieldReader); impl GPIO5_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO5_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for GPIO5_LEVEL_LOW_R { #[doc = "Field `GPIO4_EDGE_HIGH` reader - "] pub struct GPIO4_EDGE_HIGH_R(crate::FieldReader); impl GPIO4_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for GPIO4_EDGE_HIGH_R { #[doc = "Field `GPIO4_EDGE_LOW` reader - "] pub struct GPIO4_EDGE_LOW_R(crate::FieldReader); impl GPIO4_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for GPIO4_EDGE_LOW_R { #[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] pub struct GPIO4_LEVEL_HIGH_R(crate::FieldReader); impl GPIO4_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for GPIO4_LEVEL_HIGH_R { #[doc = "Field `GPIO4_LEVEL_LOW` reader - "] pub struct GPIO4_LEVEL_LOW_R(crate::FieldReader); impl GPIO4_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO4_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for GPIO4_LEVEL_LOW_R { #[doc = "Field `GPIO3_EDGE_HIGH` reader - "] pub struct GPIO3_EDGE_HIGH_R(crate::FieldReader); impl GPIO3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for GPIO3_EDGE_HIGH_R { #[doc = "Field `GPIO3_EDGE_LOW` reader - "] pub struct GPIO3_EDGE_LOW_R(crate::FieldReader); impl GPIO3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for GPIO3_EDGE_LOW_R { #[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] pub struct GPIO3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for GPIO3_LEVEL_HIGH_R { #[doc = "Field `GPIO3_LEVEL_LOW` reader - "] pub struct GPIO3_LEVEL_LOW_R(crate::FieldReader); impl GPIO3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for GPIO3_LEVEL_LOW_R { #[doc = "Field `GPIO2_EDGE_HIGH` reader - "] pub struct GPIO2_EDGE_HIGH_R(crate::FieldReader); impl GPIO2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for GPIO2_EDGE_HIGH_R { #[doc = "Field `GPIO2_EDGE_LOW` reader - "] pub struct GPIO2_EDGE_LOW_R(crate::FieldReader); impl GPIO2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for GPIO2_EDGE_LOW_R { #[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] pub struct GPIO2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for GPIO2_LEVEL_HIGH_R { #[doc = "Field `GPIO2_LEVEL_LOW` reader - "] pub struct GPIO2_LEVEL_LOW_R(crate::FieldReader); impl GPIO2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -352,6 +376,7 @@ impl core::ops::Deref for GPIO2_LEVEL_LOW_R { #[doc = "Field `GPIO1_EDGE_HIGH` reader - "] pub struct GPIO1_EDGE_HIGH_R(crate::FieldReader); impl GPIO1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -366,6 +391,7 @@ impl core::ops::Deref for GPIO1_EDGE_HIGH_R { #[doc = "Field `GPIO1_EDGE_LOW` reader - "] pub struct GPIO1_EDGE_LOW_R(crate::FieldReader); impl GPIO1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -380,6 +406,7 @@ impl core::ops::Deref for GPIO1_EDGE_LOW_R { #[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] pub struct GPIO1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -394,6 +421,7 @@ impl core::ops::Deref for GPIO1_LEVEL_HIGH_R { #[doc = "Field `GPIO1_LEVEL_LOW` reader - "] pub struct GPIO1_LEVEL_LOW_R(crate::FieldReader); impl GPIO1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -408,6 +436,7 @@ impl core::ops::Deref for GPIO1_LEVEL_LOW_R { #[doc = "Field `GPIO0_EDGE_HIGH` reader - "] pub struct GPIO0_EDGE_HIGH_R(crate::FieldReader); impl GPIO0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -422,6 +451,7 @@ impl core::ops::Deref for GPIO0_EDGE_HIGH_R { #[doc = "Field `GPIO0_EDGE_LOW` reader - "] pub struct GPIO0_EDGE_LOW_R(crate::FieldReader); impl GPIO0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -436,6 +466,7 @@ impl core::ops::Deref for GPIO0_EDGE_LOW_R { #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] pub struct GPIO0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -450,6 +481,7 @@ impl core::ops::Deref for GPIO0_LEVEL_HIGH_R { #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub struct GPIO0_LEVEL_LOW_R(crate::FieldReader); impl GPIO0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/dormant_wake_inte.rs b/src/io_qspi/dormant_wake_inte.rs index b8aa53ca9..3b442e70f 100644 --- a/src/io_qspi/dormant_wake_inte.rs +++ b/src/io_qspi/dormant_wake_inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/dormant_wake_intf.rs b/src/io_qspi/dormant_wake_intf.rs index 726f47b09..4d1d91f51 100644 --- a/src/io_qspi/dormant_wake_intf.rs +++ b/src/io_qspi/dormant_wake_intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/dormant_wake_ints.rs b/src/io_qspi/dormant_wake_ints.rs index c780cd063..d95c89e98 100644 --- a/src/io_qspi/dormant_wake_ints.rs +++ b/src/io_qspi/dormant_wake_ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/io_qspi/gpio_qspi/gpio_ctrl.rs index 6d170dcb1..6a3d64d90 100644 --- a/src/io_qspi/gpio_qspi/gpio_ctrl.rs +++ b/src/io_qspi/gpio_qspi/gpio_ctrl.rs @@ -58,6 +58,7 @@ impl From for u8 { #[doc = "Field `IRQOVER` reader - "] pub struct IRQOVER_R(crate::FieldReader); impl IRQOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IRQOVER_R(crate::FieldReader::new(bits)) } @@ -161,6 +162,7 @@ impl From for u8 { #[doc = "Field `INOVER` reader - "] pub struct INOVER_R(crate::FieldReader); impl INOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { INOVER_R(crate::FieldReader::new(bits)) } @@ -264,6 +266,7 @@ impl From for u8 { #[doc = "Field `OEOVER` reader - "] pub struct OEOVER_R(crate::FieldReader); impl OEOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { OEOVER_R(crate::FieldReader::new(bits)) } @@ -367,6 +370,7 @@ impl From for u8 { #[doc = "Field `OUTOVER` reader - "] pub struct OUTOVER_R(crate::FieldReader); impl OUTOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { OUTOVER_R(crate::FieldReader::new(bits)) } @@ -470,6 +474,7 @@ impl From for u8 { 31 == NULL"] pub struct FUNCSEL_R(crate::FieldReader); impl FUNCSEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FUNCSEL_R(crate::FieldReader::new(bits)) } @@ -560,7 +565,8 @@ impl R { pub fn outover(&self) -> OUTOVER_R { OUTOVER_R::new(((self.bits >> 8) & 0x03) as u8) } - #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table + 31 == NULL"] #[inline(always)] pub fn funcsel(&self) -> FUNCSEL_R { FUNCSEL_R::new((self.bits & 0x1f) as u8) @@ -587,7 +593,8 @@ impl W { pub fn outover(&mut self) -> OUTOVER_W { OUTOVER_W { w: self } } - #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table + 31 == NULL"] #[inline(always)] pub fn funcsel(&mut self) -> FUNCSEL_W { FUNCSEL_W { w: self } diff --git a/src/io_qspi/gpio_qspi/gpio_status.rs b/src/io_qspi/gpio_qspi/gpio_status.rs index d7b155d8d..f689ec745 100644 --- a/src/io_qspi/gpio_qspi/gpio_status.rs +++ b/src/io_qspi/gpio_qspi/gpio_status.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `IRQTOPROC` reader - interrupt to processors, after override is applied"] pub struct IRQTOPROC_R(crate::FieldReader); impl IRQTOPROC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IRQTOPROC_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for IRQTOPROC_R { #[doc = "Field `IRQFROMPAD` reader - interrupt from pad before override is applied"] pub struct IRQFROMPAD_R(crate::FieldReader); impl IRQFROMPAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IRQFROMPAD_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for IRQFROMPAD_R { #[doc = "Field `INTOPERI` reader - input signal to peripheral, after override is applied"] pub struct INTOPERI_R(crate::FieldReader); impl INTOPERI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTOPERI_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for INTOPERI_R { #[doc = "Field `INFROMPAD` reader - input signal from pad, before override is applied"] pub struct INFROMPAD_R(crate::FieldReader); impl INFROMPAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INFROMPAD_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for INFROMPAD_R { #[doc = "Field `OETOPAD` reader - output enable to pad after register override is applied"] pub struct OETOPAD_R(crate::FieldReader); impl OETOPAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OETOPAD_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for OETOPAD_R { #[doc = "Field `OEFROMPERI` reader - output enable from selected peripheral, before register override is applied"] pub struct OEFROMPERI_R(crate::FieldReader); impl OEFROMPERI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OEFROMPERI_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for OEFROMPERI_R { #[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] pub struct OUTTOPAD_R(crate::FieldReader); impl OUTTOPAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUTTOPAD_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for OUTTOPAD_R { #[doc = "Field `OUTFROMPERI` reader - output signal from selected peripheral, before register override is applied"] pub struct OUTFROMPERI_R(crate::FieldReader); impl OUTFROMPERI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUTFROMPERI_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/intr.rs b/src/io_qspi/intr.rs index 406600bda..819b84294 100644 --- a/src/io_qspi/intr.rs +++ b/src/io_qspi/intr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -123,6 +126,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -137,6 +141,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -173,6 +178,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -209,6 +215,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -223,6 +230,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -237,6 +245,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -273,6 +282,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -309,6 +319,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -323,6 +334,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -337,6 +349,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -373,6 +386,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -409,6 +423,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -423,6 +438,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -437,6 +453,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -473,6 +490,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -509,6 +527,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -523,6 +542,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -537,6 +557,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -573,6 +594,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -609,6 +631,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -623,6 +646,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/proc0_inte.rs b/src/io_qspi/proc0_inte.rs index 622bb49b6..a8cc6a98d 100644 --- a/src/io_qspi/proc0_inte.rs +++ b/src/io_qspi/proc0_inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/proc0_intf.rs b/src/io_qspi/proc0_intf.rs index 6cdf10899..58b0b81a1 100644 --- a/src/io_qspi/proc0_intf.rs +++ b/src/io_qspi/proc0_intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/proc0_ints.rs b/src/io_qspi/proc0_ints.rs index 2863f293d..0925006c7 100644 --- a/src/io_qspi/proc0_ints.rs +++ b/src/io_qspi/proc0_ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/proc1_inte.rs b/src/io_qspi/proc1_inte.rs index f2caeda26..23858c550 100644 --- a/src/io_qspi/proc1_inte.rs +++ b/src/io_qspi/proc1_inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/proc1_intf.rs b/src/io_qspi/proc1_intf.rs index 3619814de..e3521694b 100644 --- a/src/io_qspi/proc1_intf.rs +++ b/src/io_qspi/proc1_intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> GPIO_QSPI_SD3_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> GPIO_QSPI_SD3_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> GPIO_QSPI_SD2_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> GPIO_QSPI_SD2_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> GPIO_QSPI_SD1_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> GPIO_QSPI_SD1_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> GPIO_QSPI_SD0_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> GPIO_QSPI_SD0_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> GPIO_QSPI_SS_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> GPIO_QSPI_SS_LEVEL_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> GPIO_QSPI_SCLK_EDGE_LOW_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a> { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/io_qspi/proc1_ints.rs b/src/io_qspi/proc1_ints.rs index a986b483b..51835dae9 100644 --- a/src/io_qspi/proc1_ints.rs +++ b/src/io_qspi/proc1_ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD3_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD3_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for GPIO_QSPI_SD3_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD2_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD2_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for GPIO_QSPI_SD2_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD1_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD1_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for GPIO_QSPI_SD1_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SD0_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SD0_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for GPIO_QSPI_SD0_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SS_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SS_LEVEL_LOW_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for GPIO_QSPI_SS_LEVEL_LOW_R { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_HIGH_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_EDGE_HIGH_R { #[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] pub struct GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_EDGE_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_EDGE_LOW_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_EDGE_LOW_R { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_HIGH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_HIGH_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for GPIO_QSPI_SCLK_LEVEL_HIGH_R { #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub struct GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader); impl GPIO_QSPI_SCLK_LEVEL_LOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { GPIO_QSPI_SCLK_LEVEL_LOW_R(crate::FieldReader::new(bits)) } diff --git a/src/lib.rs b/src/lib.rs index 748eb9bb2..8c5fb9d24 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,11 +1,11 @@ -#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.19.0 ( )) +#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.20.0 ( )) You can find an overview of the generated API [here]. API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`. -[here]: https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api +[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api [next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased [repository]: https://github.com/rust-embedded/svd2rust"] #![deny(const_err)] @@ -649,6 +649,8 @@ impl core::fmt::Debug for PLL_USB { f.debug_struct("PLL_USB").finish() } } +#[doc = "PLL_USB"] +pub use pll_sys as pll_usb; #[doc = "Register block for busfabric control signals and performance counters"] pub struct BUSCTRL { _marker: PhantomData<*const ()>, @@ -731,6 +733,8 @@ impl core::fmt::Debug for UART1 { f.debug_struct("UART1").finish() } } +#[doc = "UART1"] +pub use uart0 as uart1; #[doc = "SPI0"] pub struct SPI0 { _marker: PhantomData<*const ()>, @@ -785,6 +789,8 @@ impl core::fmt::Debug for SPI1 { f.debug_struct("SPI1").finish() } } +#[doc = "SPI1"] +pub use spi0 as spi1; #[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): @@ -1052,6 +1058,79 @@ impl core::fmt::Debug for I2C1 { f.debug_struct("I2C1").finish() } } +#[doc = "DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16"] +pub use i2c0 as i2c1; #[doc = "Control and data interface to SAR ADC"] pub struct ADC { _marker: PhantomData<*const ()>, @@ -1432,6 +1511,8 @@ impl core::fmt::Debug for PIO1 { f.debug_struct("PIO1").finish() } } +#[doc = "Programmable IO block"] +pub use pio0 as pio1; #[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] pub struct SIO { diff --git a/src/pads_bank0/gpio.rs b/src/pads_bank0/gpio.rs index 1a0bac07e..ce763144a 100644 --- a/src/pads_bank0/gpio.rs +++ b/src/pads_bank0/gpio.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_bank0/swclk.rs b/src/pads_bank0/swclk.rs index df6e13108..ef94ed06d 100644 --- a/src/pads_bank0/swclk.rs +++ b/src/pads_bank0/swclk.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_bank0/swd.rs b/src/pads_bank0/swd.rs index 27a03f070..ccdb9655c 100644 --- a/src/pads_bank0/swd.rs +++ b/src/pads_bank0/swd.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_bank0/voltage_select.rs b/src/pads_bank0/voltage_select.rs index 3be42c99a..bce2a3cc3 100644 --- a/src/pads_bank0/voltage_select.rs +++ b/src/pads_bank0/voltage_select.rs @@ -53,6 +53,7 @@ impl From for bool { #[doc = "Field `VOLTAGE_SELECT` reader - "] pub struct VOLTAGE_SELECT_R(crate::FieldReader); impl VOLTAGE_SELECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VOLTAGE_SELECT_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_qspi/gpio_qspi_sclk.rs b/src/pads_qspi/gpio_qspi_sclk.rs index 55f510f43..11202abe4 100644 --- a/src/pads_qspi/gpio_qspi_sclk.rs +++ b/src/pads_qspi/gpio_qspi_sclk.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_qspi/gpio_qspi_sd0.rs b/src/pads_qspi/gpio_qspi_sd0.rs index 4fc7543e7..fc5d96146 100644 --- a/src/pads_qspi/gpio_qspi_sd0.rs +++ b/src/pads_qspi/gpio_qspi_sd0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_qspi/gpio_qspi_sd1.rs b/src/pads_qspi/gpio_qspi_sd1.rs index 27335e30b..4576f48c6 100644 --- a/src/pads_qspi/gpio_qspi_sd1.rs +++ b/src/pads_qspi/gpio_qspi_sd1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_qspi/gpio_qspi_sd2.rs b/src/pads_qspi/gpio_qspi_sd2.rs index 6a84bc64d..a73d69e7c 100644 --- a/src/pads_qspi/gpio_qspi_sd2.rs +++ b/src/pads_qspi/gpio_qspi_sd2.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_qspi/gpio_qspi_sd3.rs b/src/pads_qspi/gpio_qspi_sd3.rs index a4b55b737..a719e58a2 100644 --- a/src/pads_qspi/gpio_qspi_sd3.rs +++ b/src/pads_qspi/gpio_qspi_sd3.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_qspi/gpio_qspi_ss.rs b/src/pads_qspi/gpio_qspi_ss.rs index 151fbb697..ec277c92c 100644 --- a/src/pads_qspi/gpio_qspi_ss.rs +++ b/src/pads_qspi/gpio_qspi_ss.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] pub struct OD_R(crate::FieldReader); impl OD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OD_W<'a> { #[doc = "Field `IE` reader - Input enable"] pub struct IE_R(crate::FieldReader); impl IE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IE_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl From for u8 { #[doc = "Field `DRIVE` reader - Drive strength."] pub struct DRIVE_R(crate::FieldReader); impl DRIVE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DRIVE_R(crate::FieldReader::new(bits)) } @@ -212,6 +215,7 @@ impl<'a> DRIVE_W<'a> { #[doc = "Field `PUE` reader - Pull up enable"] pub struct PUE_R(crate::FieldReader); impl PUE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PUE_R(crate::FieldReader::new(bits)) } @@ -248,6 +252,7 @@ impl<'a> PUE_W<'a> { #[doc = "Field `PDE` reader - Pull down enable"] pub struct PDE_R(crate::FieldReader); impl PDE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PDE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> PDE_W<'a> { #[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] pub struct SCHMITT_R(crate::FieldReader); impl SCHMITT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCHMITT_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> SCHMITT_W<'a> { #[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] pub struct SLEWFAST_R(crate::FieldReader); impl SLEWFAST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEWFAST_R(crate::FieldReader::new(bits)) } diff --git a/src/pads_qspi/voltage_select.rs b/src/pads_qspi/voltage_select.rs index 3be42c99a..bce2a3cc3 100644 --- a/src/pads_qspi/voltage_select.rs +++ b/src/pads_qspi/voltage_select.rs @@ -53,6 +53,7 @@ impl From for bool { #[doc = "Field `VOLTAGE_SELECT` reader - "] pub struct VOLTAGE_SELECT_R(crate::FieldReader); impl VOLTAGE_SELECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VOLTAGE_SELECT_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/ctrl.rs b/src/pio0/ctrl.rs index 92a90e046..08e490598 100644 --- a/src/pio0/ctrl.rs +++ b/src/pio0/ctrl.rs @@ -41,6 +41,7 @@ impl From> for W { Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] pub struct CLKDIV_RESTART_R(crate::FieldReader); impl CLKDIV_RESTART_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CLKDIV_RESTART_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CLKDIV_RESTART_W<'a> { Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY."] pub struct SM_RESTART_R(crate::FieldReader); impl SM_RESTART_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SM_RESTART_R(crate::FieldReader::new(bits)) } @@ -101,6 +103,7 @@ impl<'a> SM_RESTART_W<'a> { #[doc = "Field `SM_ENABLE` reader - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] pub struct SM_ENABLE_R(crate::FieldReader); impl SM_ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SM_ENABLE_R(crate::FieldReader::new(bits)) } @@ -125,12 +128,18 @@ impl<'a> SM_ENABLE_W<'a> { } } impl R { - #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] + #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] #[inline(always)] pub fn clkdiv_restart(&self) -> CLKDIV_RESTART_R { CLKDIV_RESTART_R::new(((self.bits >> 8) & 0x0f) as u8) } - #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY."] + #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY."] #[inline(always)] pub fn sm_restart(&self) -> SM_RESTART_R { SM_RESTART_R::new(((self.bits >> 4) & 0x0f) as u8) @@ -142,12 +151,18 @@ impl R { } } impl W { - #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] + #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] #[inline(always)] pub fn clkdiv_restart(&mut self) -> CLKDIV_RESTART_W { CLKDIV_RESTART_W { w: self } } - #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY."] + #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY."] #[inline(always)] pub fn sm_restart(&mut self) -> SM_RESTART_W { SM_RESTART_W { w: self } diff --git a/src/pio0/dbg_cfginfo.rs b/src/pio0/dbg_cfginfo.rs index 0c76213db..543a3218c 100644 --- a/src/pio0/dbg_cfginfo.rs +++ b/src/pio0/dbg_cfginfo.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `IMEM_SIZE` reader - The size of the instruction memory, measured in units of one instruction"] pub struct IMEM_SIZE_R(crate::FieldReader); impl IMEM_SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IMEM_SIZE_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for IMEM_SIZE_R { #[doc = "Field `SM_COUNT` reader - The number of state machines this PIO instance is equipped with."] pub struct SM_COUNT_R(crate::FieldReader); impl SM_COUNT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SM_COUNT_R(crate::FieldReader::new(bits)) } @@ -46,6 +48,7 @@ impl core::ops::Deref for SM_COUNT_R { this depth."] pub struct FIFO_DEPTH_R(crate::FieldReader); impl FIFO_DEPTH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FIFO_DEPTH_R(crate::FieldReader::new(bits)) } @@ -68,7 +71,9 @@ impl R { pub fn sm_count(&self) -> SM_COUNT_R { SM_COUNT_R::new(((self.bits >> 8) & 0x0f) as u8) } - #[doc = "Bits 0:5 - The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."] + #[doc = "Bits 0:5 - The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth."] #[inline(always)] pub fn fifo_depth(&self) -> FIFO_DEPTH_R { FIFO_DEPTH_R::new((self.bits & 0x3f) as u8) diff --git a/src/pio0/fdebug.rs b/src/pio0/fdebug.rs index d78d0d2a0..bb405a0a6 100644 --- a/src/pio0/fdebug.rs +++ b/src/pio0/fdebug.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TXSTALL` reader - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."] pub struct TXSTALL_R(crate::FieldReader); impl TXSTALL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TXSTALL_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> TXSTALL_W<'a> { #[doc = "Field `TXOVER` reader - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."] pub struct TXOVER_R(crate::FieldReader); impl TXOVER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TXOVER_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> TXOVER_W<'a> { #[doc = "Field `RXUNDER` reader - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."] pub struct RXUNDER_R(crate::FieldReader); impl RXUNDER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RXUNDER_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> RXUNDER_W<'a> { #[doc = "Field `RXSTALL` reader - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] pub struct RXSTALL_R(crate::FieldReader); impl RXSTALL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RXSTALL_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/flevel.rs b/src/pio0/flevel.rs index 306d74457..2de2a87e6 100644 --- a/src/pio0/flevel.rs +++ b/src/pio0/flevel.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RX3` reader - "] pub struct RX3_R(crate::FieldReader); impl RX3_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RX3_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for RX3_R { #[doc = "Field `TX3` reader - "] pub struct TX3_R(crate::FieldReader); impl TX3_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TX3_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for TX3_R { #[doc = "Field `RX2` reader - "] pub struct RX2_R(crate::FieldReader); impl RX2_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RX2_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RX2_R { #[doc = "Field `TX2` reader - "] pub struct TX2_R(crate::FieldReader); impl TX2_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TX2_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for TX2_R { #[doc = "Field `RX1` reader - "] pub struct RX1_R(crate::FieldReader); impl RX1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RX1_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for RX1_R { #[doc = "Field `TX1` reader - "] pub struct TX1_R(crate::FieldReader); impl TX1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TX1_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for TX1_R { #[doc = "Field `RX0` reader - "] pub struct RX0_R(crate::FieldReader); impl RX0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RX0_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for RX0_R { #[doc = "Field `TX0` reader - "] pub struct TX0_R(crate::FieldReader); impl TX0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TX0_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/fstat.rs b/src/pio0/fstat.rs index 7cb8c69f6..ed6f29f42 100644 --- a/src/pio0/fstat.rs +++ b/src/pio0/fstat.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `TXEMPTY` reader - State machine TX FIFO is empty"] pub struct TXEMPTY_R(crate::FieldReader); impl TXEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TXEMPTY_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for TXEMPTY_R { #[doc = "Field `TXFULL` reader - State machine TX FIFO is full"] pub struct TXFULL_R(crate::FieldReader); impl TXFULL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TXFULL_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for TXFULL_R { #[doc = "Field `RXEMPTY` reader - State machine RX FIFO is empty"] pub struct RXEMPTY_R(crate::FieldReader); impl RXEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RXEMPTY_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RXEMPTY_R { #[doc = "Field `RXFULL` reader - State machine RX FIFO is full"] pub struct RXFULL_R(crate::FieldReader); impl RXFULL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RXFULL_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/intr.rs b/src/pio0/intr.rs index 79447a9b9..a1da40f82 100644 --- a/src/pio0/intr.rs +++ b/src/pio0/intr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `SM3` reader - "] pub struct SM3_R(crate::FieldReader); impl SM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for SM3_R { #[doc = "Field `SM2` reader - "] pub struct SM2_R(crate::FieldReader); impl SM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for SM2_R { #[doc = "Field `SM1` reader - "] pub struct SM1_R(crate::FieldReader); impl SM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for SM1_R { #[doc = "Field `SM0` reader - "] pub struct SM0_R(crate::FieldReader); impl SM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for SM0_R { #[doc = "Field `SM3_TXNFULL` reader - "] pub struct SM3_TXNFULL_R(crate::FieldReader); impl SM3_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for SM3_TXNFULL_R { #[doc = "Field `SM2_TXNFULL` reader - "] pub struct SM2_TXNFULL_R(crate::FieldReader); impl SM2_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for SM2_TXNFULL_R { #[doc = "Field `SM1_TXNFULL` reader - "] pub struct SM1_TXNFULL_R(crate::FieldReader); impl SM1_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for SM1_TXNFULL_R { #[doc = "Field `SM0_TXNFULL` reader - "] pub struct SM0_TXNFULL_R(crate::FieldReader); impl SM0_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for SM0_TXNFULL_R { #[doc = "Field `SM3_RXNEMPTY` reader - "] pub struct SM3_RXNEMPTY_R(crate::FieldReader); impl SM3_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for SM3_RXNEMPTY_R { #[doc = "Field `SM2_RXNEMPTY` reader - "] pub struct SM2_RXNEMPTY_R(crate::FieldReader); impl SM2_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for SM2_RXNEMPTY_R { #[doc = "Field `SM1_RXNEMPTY` reader - "] pub struct SM1_RXNEMPTY_R(crate::FieldReader); impl SM1_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for SM1_RXNEMPTY_R { #[doc = "Field `SM0_RXNEMPTY` reader - "] pub struct SM0_RXNEMPTY_R(crate::FieldReader); impl SM0_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_RXNEMPTY_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/irq.rs b/src/pio0/irq.rs index 851837649..591fda94d 100644 --- a/src/pio0/irq.rs +++ b/src/pio0/irq.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IRQ` reader - "] pub struct IRQ_R(crate::FieldReader); impl IRQ_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IRQ_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/sm/sm_addr.rs b/src/pio0/sm/sm_addr.rs index d9725535d..66c94ad38 100644 --- a/src/pio0/sm/sm_addr.rs +++ b/src/pio0/sm/sm_addr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `SM0_ADDR` reader - "] pub struct SM0_ADDR_R(crate::FieldReader); impl SM0_ADDR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SM0_ADDR_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/sm/sm_clkdiv.rs b/src/pio0/sm/sm_clkdiv.rs index 0d963bd76..424e98499 100644 --- a/src/pio0/sm/sm_clkdiv.rs +++ b/src/pio0/sm/sm_clkdiv.rs @@ -38,6 +38,7 @@ impl From> for W { Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -65,6 +66,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - Fractional part of clock divisor"] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } @@ -89,7 +91,8 @@ impl<'a> FRAC_W<'a> { } } impl R { - #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] + #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] #[inline(always)] pub fn int(&self) -> INT_R { INT_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -101,7 +104,8 @@ impl R { } } impl W { - #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] + #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] #[inline(always)] pub fn int(&mut self) -> INT_W { INT_W { w: self } diff --git a/src/pio0/sm/sm_execctrl.rs b/src/pio0/sm/sm_execctrl.rs index 8d9ac3968..3bb6adf56 100644 --- a/src/pio0/sm/sm_execctrl.rs +++ b/src/pio0/sm/sm_execctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EXEC_STALLED` reader - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."] pub struct EXEC_STALLED_R(crate::FieldReader); impl EXEC_STALLED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EXEC_STALLED_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for EXEC_STALLED_R { #[doc = "Field `SIDE_EN` reader - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."] pub struct SIDE_EN_R(crate::FieldReader); impl SIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIDE_EN_R(crate::FieldReader::new(bits)) } @@ -87,6 +89,7 @@ impl<'a> SIDE_EN_W<'a> { #[doc = "Field `SIDE_PINDIR` reader - If 1, side-set data is asserted to pin directions, instead of pin values"] pub struct SIDE_PINDIR_R(crate::FieldReader); impl SIDE_PINDIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIDE_PINDIR_R(crate::FieldReader::new(bits)) } @@ -123,6 +126,7 @@ impl<'a> SIDE_PINDIR_W<'a> { #[doc = "Field `JMP_PIN` reader - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."] pub struct JMP_PIN_R(crate::FieldReader); impl JMP_PIN_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { JMP_PIN_R(crate::FieldReader::new(bits)) } @@ -149,6 +153,7 @@ impl<'a> JMP_PIN_W<'a> { #[doc = "Field `OUT_EN_SEL` reader - Which data bit to use for inline OUT enable"] pub struct OUT_EN_SEL_R(crate::FieldReader); impl OUT_EN_SEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { OUT_EN_SEL_R(crate::FieldReader::new(bits)) } @@ -178,6 +183,7 @@ impl<'a> OUT_EN_SEL_W<'a> { due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] pub struct INLINE_OUT_EN_R(crate::FieldReader); impl INLINE_OUT_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INLINE_OUT_EN_R(crate::FieldReader::new(bits)) } @@ -217,6 +223,7 @@ impl<'a> INLINE_OUT_EN_W<'a> { #[doc = "Field `OUT_STICKY` reader - Continuously assert the most recent OUT/SET to the pins"] pub struct OUT_STICKY_R(crate::FieldReader); impl OUT_STICKY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUT_STICKY_R(crate::FieldReader::new(bits)) } @@ -254,6 +261,7 @@ impl<'a> OUT_STICKY_W<'a> { If the instruction is a jump, and the jump condition is true, the jump takes priority."] pub struct WRAP_TOP_R(crate::FieldReader); impl WRAP_TOP_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { WRAP_TOP_R(crate::FieldReader::new(bits)) } @@ -281,6 +289,7 @@ impl<'a> WRAP_TOP_W<'a> { #[doc = "Field `WRAP_BOTTOM` reader - After reaching wrap_top, execution is wrapped to this address."] pub struct WRAP_BOTTOM_R(crate::FieldReader); impl WRAP_BOTTOM_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { WRAP_BOTTOM_R(crate::FieldReader::new(bits)) } @@ -323,6 +332,7 @@ impl From for bool { #[doc = "Field `STATUS_SEL` reader - Comparison used for the MOV x, STATUS instruction."] pub struct STATUS_SEL_R(crate::FieldReader); impl STATUS_SEL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STATUS_SEL_R(crate::FieldReader::new(bits)) } @@ -392,6 +402,7 @@ impl<'a> STATUS_SEL_W<'a> { #[doc = "Field `STATUS_N` reader - Comparison level for the MOV x, STATUS instruction"] pub struct STATUS_N_R(crate::FieldReader); impl STATUS_N_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { STATUS_N_R(crate::FieldReader::new(bits)) } @@ -441,7 +452,10 @@ impl R { pub fn out_en_sel(&self) -> OUT_EN_SEL_R { OUT_EN_SEL_R::new(((self.bits >> 19) & 0x1f) as u8) } - #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] + #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] #[inline(always)] pub fn inline_out_en(&self) -> INLINE_OUT_EN_R { INLINE_OUT_EN_R::new(((self.bits >> 18) & 0x01) != 0) @@ -451,7 +465,8 @@ impl R { pub fn out_sticky(&self) -> OUT_STICKY_R { OUT_STICKY_R::new(((self.bits >> 17) & 0x01) != 0) } - #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] + #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority."] #[inline(always)] pub fn wrap_top(&self) -> WRAP_TOP_R { WRAP_TOP_R::new(((self.bits >> 12) & 0x1f) as u8) @@ -493,7 +508,10 @@ impl W { pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W { OUT_EN_SEL_W { w: self } } - #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] + #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] #[inline(always)] pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W { INLINE_OUT_EN_W { w: self } @@ -503,7 +521,8 @@ impl W { pub fn out_sticky(&mut self) -> OUT_STICKY_W { OUT_STICKY_W { w: self } } - #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] + #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority."] #[inline(always)] pub fn wrap_top(&mut self) -> WRAP_TOP_W { WRAP_TOP_W { w: self } diff --git a/src/pio0/sm/sm_instr.rs b/src/pio0/sm/sm_instr.rs index cb536628a..d11964508 100644 --- a/src/pio0/sm/sm_instr.rs +++ b/src/pio0/sm/sm_instr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SM0_INSTR` reader - "] pub struct SM0_INSTR_R(crate::FieldReader); impl SM0_INSTR_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { SM0_INSTR_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/sm/sm_pinctrl.rs b/src/pio0/sm/sm_pinctrl.rs index 7fcddd407..2836fc181 100644 --- a/src/pio0/sm/sm_pinctrl.rs +++ b/src/pio0/sm/sm_pinctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SIDESET_COUNT` reader - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."] pub struct SIDESET_COUNT_R(crate::FieldReader); impl SIDESET_COUNT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SIDESET_COUNT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> SIDESET_COUNT_W<'a> { #[doc = "Field `SET_COUNT` reader - The number of pins asserted by a SET. In the range 0 to 5 inclusive."] pub struct SET_COUNT_R(crate::FieldReader); impl SET_COUNT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SET_COUNT_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> SET_COUNT_W<'a> { #[doc = "Field `OUT_COUNT` reader - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."] pub struct OUT_COUNT_R(crate::FieldReader); impl OUT_COUNT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { OUT_COUNT_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> OUT_COUNT_W<'a> { #[doc = "Field `IN_BASE` reader - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."] pub struct IN_BASE_R(crate::FieldReader); impl IN_BASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IN_BASE_R(crate::FieldReader::new(bits)) } @@ -141,6 +145,7 @@ impl<'a> IN_BASE_W<'a> { #[doc = "Field `SIDESET_BASE` reader - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."] pub struct SIDESET_BASE_R(crate::FieldReader); impl SIDESET_BASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SIDESET_BASE_R(crate::FieldReader::new(bits)) } @@ -167,6 +172,7 @@ impl<'a> SIDESET_BASE_W<'a> { #[doc = "Field `SET_BASE` reader - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."] pub struct SET_BASE_R(crate::FieldReader); impl SET_BASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SET_BASE_R(crate::FieldReader::new(bits)) } @@ -193,6 +199,7 @@ impl<'a> SET_BASE_W<'a> { #[doc = "Field `OUT_BASE` reader - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] pub struct OUT_BASE_R(crate::FieldReader); impl OUT_BASE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { OUT_BASE_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/sm/sm_shiftctrl.rs b/src/pio0/sm/sm_shiftctrl.rs index bf4525c5e..6f31a3fb5 100644 --- a/src/pio0/sm/sm_shiftctrl.rs +++ b/src/pio0/sm/sm_shiftctrl.rs @@ -39,6 +39,7 @@ impl From> for W { FIFOs are flushed when this bit is changed."] pub struct FJOIN_RX_R(crate::FieldReader); impl FJOIN_RX_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FJOIN_RX_R(crate::FieldReader::new(bits)) } @@ -79,6 +80,7 @@ impl<'a> FJOIN_RX_W<'a> { FIFOs are flushed when this bit is changed."] pub struct FJOIN_TX_R(crate::FieldReader); impl FJOIN_TX_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FJOIN_TX_R(crate::FieldReader::new(bits)) } @@ -118,6 +120,7 @@ impl<'a> FJOIN_TX_W<'a> { Write 0 for value of 32."] pub struct PULL_THRESH_R(crate::FieldReader); impl PULL_THRESH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PULL_THRESH_R(crate::FieldReader::new(bits)) } @@ -146,6 +149,7 @@ impl<'a> PULL_THRESH_W<'a> { Write 0 for value of 32."] pub struct PUSH_THRESH_R(crate::FieldReader); impl PUSH_THRESH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PUSH_THRESH_R(crate::FieldReader::new(bits)) } @@ -173,6 +177,7 @@ impl<'a> PUSH_THRESH_W<'a> { #[doc = "Field `OUT_SHIFTDIR` reader - 1 = shift out of output shift register to right. 0 = to left."] pub struct OUT_SHIFTDIR_R(crate::FieldReader); impl OUT_SHIFTDIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUT_SHIFTDIR_R(crate::FieldReader::new(bits)) } @@ -209,6 +214,7 @@ impl<'a> OUT_SHIFTDIR_W<'a> { #[doc = "Field `IN_SHIFTDIR` reader - 1 = shift input shift register to right (data enters from left). 0 = to left."] pub struct IN_SHIFTDIR_R(crate::FieldReader); impl IN_SHIFTDIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IN_SHIFTDIR_R(crate::FieldReader::new(bits)) } @@ -245,6 +251,7 @@ impl<'a> IN_SHIFTDIR_W<'a> { #[doc = "Field `AUTOPULL` reader - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."] pub struct AUTOPULL_R(crate::FieldReader); impl AUTOPULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { AUTOPULL_R(crate::FieldReader::new(bits)) } @@ -281,6 +288,7 @@ impl<'a> AUTOPULL_W<'a> { #[doc = "Field `AUTOPUSH` reader - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] pub struct AUTOPUSH_R(crate::FieldReader); impl AUTOPUSH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { AUTOPUSH_R(crate::FieldReader::new(bits)) } @@ -315,22 +323,28 @@ impl<'a> AUTOPUSH_W<'a> { } } impl R { - #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] + #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed."] #[inline(always)] pub fn fjoin_rx(&self) -> FJOIN_RX_R { FJOIN_RX_R::new(((self.bits >> 31) & 0x01) != 0) } - #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] + #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed."] #[inline(always)] pub fn fjoin_tx(&self) -> FJOIN_TX_R { FJOIN_TX_R::new(((self.bits >> 30) & 0x01) != 0) } - #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] + #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32."] #[inline(always)] pub fn pull_thresh(&self) -> PULL_THRESH_R { PULL_THRESH_R::new(((self.bits >> 25) & 0x1f) as u8) } - #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] + #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32."] #[inline(always)] pub fn push_thresh(&self) -> PUSH_THRESH_R { PUSH_THRESH_R::new(((self.bits >> 20) & 0x1f) as u8) @@ -357,22 +371,28 @@ impl R { } } impl W { - #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] + #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed."] #[inline(always)] pub fn fjoin_rx(&mut self) -> FJOIN_RX_W { FJOIN_RX_W { w: self } } - #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] + #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed."] #[inline(always)] pub fn fjoin_tx(&mut self) -> FJOIN_TX_W { FJOIN_TX_W { w: self } } - #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] + #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32."] #[inline(always)] pub fn pull_thresh(&mut self) -> PULL_THRESH_W { PULL_THRESH_W { w: self } } - #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] + #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32."] #[inline(always)] pub fn push_thresh(&mut self) -> PUSH_THRESH_W { PUSH_THRESH_W { w: self } diff --git a/src/pio0/sm_irq/irq_inte.rs b/src/pio0/sm_irq/irq_inte.rs index 197fd4127..0879d8f7c 100644 --- a/src/pio0/sm_irq/irq_inte.rs +++ b/src/pio0/sm_irq/irq_inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SM3` reader - "] pub struct SM3_R(crate::FieldReader); impl SM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> SM3_W<'a> { #[doc = "Field `SM2` reader - "] pub struct SM2_R(crate::FieldReader); impl SM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> SM2_W<'a> { #[doc = "Field `SM1` reader - "] pub struct SM1_R(crate::FieldReader); impl SM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> SM1_W<'a> { #[doc = "Field `SM0` reader - "] pub struct SM0_R(crate::FieldReader); impl SM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> SM0_W<'a> { #[doc = "Field `SM3_TXNFULL` reader - "] pub struct SM3_TXNFULL_R(crate::FieldReader); impl SM3_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> SM3_TXNFULL_W<'a> { #[doc = "Field `SM2_TXNFULL` reader - "] pub struct SM2_TXNFULL_R(crate::FieldReader); impl SM2_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> SM2_TXNFULL_W<'a> { #[doc = "Field `SM1_TXNFULL` reader - "] pub struct SM1_TXNFULL_R(crate::FieldReader); impl SM1_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> SM1_TXNFULL_W<'a> { #[doc = "Field `SM0_TXNFULL` reader - "] pub struct SM0_TXNFULL_R(crate::FieldReader); impl SM0_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> SM0_TXNFULL_W<'a> { #[doc = "Field `SM3_RXNEMPTY` reader - "] pub struct SM3_RXNEMPTY_R(crate::FieldReader); impl SM3_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> SM3_RXNEMPTY_W<'a> { #[doc = "Field `SM2_RXNEMPTY` reader - "] pub struct SM2_RXNEMPTY_R(crate::FieldReader); impl SM2_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> SM2_RXNEMPTY_W<'a> { #[doc = "Field `SM1_RXNEMPTY` reader - "] pub struct SM1_RXNEMPTY_R(crate::FieldReader); impl SM1_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> SM1_RXNEMPTY_W<'a> { #[doc = "Field `SM0_RXNEMPTY` reader - "] pub struct SM0_RXNEMPTY_R(crate::FieldReader); impl SM0_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_RXNEMPTY_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/sm_irq/irq_intf.rs b/src/pio0/sm_irq/irq_intf.rs index 496ad9729..d5624ccd0 100644 --- a/src/pio0/sm_irq/irq_intf.rs +++ b/src/pio0/sm_irq/irq_intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SM3` reader - "] pub struct SM3_R(crate::FieldReader); impl SM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> SM3_W<'a> { #[doc = "Field `SM2` reader - "] pub struct SM2_R(crate::FieldReader); impl SM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> SM2_W<'a> { #[doc = "Field `SM1` reader - "] pub struct SM1_R(crate::FieldReader); impl SM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> SM1_W<'a> { #[doc = "Field `SM0` reader - "] pub struct SM0_R(crate::FieldReader); impl SM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> SM0_W<'a> { #[doc = "Field `SM3_TXNFULL` reader - "] pub struct SM3_TXNFULL_R(crate::FieldReader); impl SM3_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> SM3_TXNFULL_W<'a> { #[doc = "Field `SM2_TXNFULL` reader - "] pub struct SM2_TXNFULL_R(crate::FieldReader); impl SM2_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> SM2_TXNFULL_W<'a> { #[doc = "Field `SM1_TXNFULL` reader - "] pub struct SM1_TXNFULL_R(crate::FieldReader); impl SM1_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> SM1_TXNFULL_W<'a> { #[doc = "Field `SM0_TXNFULL` reader - "] pub struct SM0_TXNFULL_R(crate::FieldReader); impl SM0_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> SM0_TXNFULL_W<'a> { #[doc = "Field `SM3_RXNEMPTY` reader - "] pub struct SM3_RXNEMPTY_R(crate::FieldReader); impl SM3_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> SM3_RXNEMPTY_W<'a> { #[doc = "Field `SM2_RXNEMPTY` reader - "] pub struct SM2_RXNEMPTY_R(crate::FieldReader); impl SM2_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> SM2_RXNEMPTY_W<'a> { #[doc = "Field `SM1_RXNEMPTY` reader - "] pub struct SM1_RXNEMPTY_R(crate::FieldReader); impl SM1_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> SM1_RXNEMPTY_W<'a> { #[doc = "Field `SM0_RXNEMPTY` reader - "] pub struct SM0_RXNEMPTY_R(crate::FieldReader); impl SM0_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_RXNEMPTY_R(crate::FieldReader::new(bits)) } diff --git a/src/pio0/sm_irq/irq_ints.rs b/src/pio0/sm_irq/irq_ints.rs index 99da080b1..3d81170ee 100644 --- a/src/pio0/sm_irq/irq_ints.rs +++ b/src/pio0/sm_irq/irq_ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `SM3` reader - "] pub struct SM3_R(crate::FieldReader); impl SM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for SM3_R { #[doc = "Field `SM2` reader - "] pub struct SM2_R(crate::FieldReader); impl SM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for SM2_R { #[doc = "Field `SM1` reader - "] pub struct SM1_R(crate::FieldReader); impl SM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for SM1_R { #[doc = "Field `SM0` reader - "] pub struct SM0_R(crate::FieldReader); impl SM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for SM0_R { #[doc = "Field `SM3_TXNFULL` reader - "] pub struct SM3_TXNFULL_R(crate::FieldReader); impl SM3_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for SM3_TXNFULL_R { #[doc = "Field `SM2_TXNFULL` reader - "] pub struct SM2_TXNFULL_R(crate::FieldReader); impl SM2_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for SM2_TXNFULL_R { #[doc = "Field `SM1_TXNFULL` reader - "] pub struct SM1_TXNFULL_R(crate::FieldReader); impl SM1_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for SM1_TXNFULL_R { #[doc = "Field `SM0_TXNFULL` reader - "] pub struct SM0_TXNFULL_R(crate::FieldReader); impl SM0_TXNFULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_TXNFULL_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for SM0_TXNFULL_R { #[doc = "Field `SM3_RXNEMPTY` reader - "] pub struct SM3_RXNEMPTY_R(crate::FieldReader); impl SM3_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM3_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for SM3_RXNEMPTY_R { #[doc = "Field `SM2_RXNEMPTY` reader - "] pub struct SM2_RXNEMPTY_R(crate::FieldReader); impl SM2_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM2_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for SM2_RXNEMPTY_R { #[doc = "Field `SM1_RXNEMPTY` reader - "] pub struct SM1_RXNEMPTY_R(crate::FieldReader); impl SM1_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM1_RXNEMPTY_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for SM1_RXNEMPTY_R { #[doc = "Field `SM0_RXNEMPTY` reader - "] pub struct SM0_RXNEMPTY_R(crate::FieldReader); impl SM0_RXNEMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SM0_RXNEMPTY_R(crate::FieldReader::new(bits)) } diff --git a/src/pll_sys/cs.rs b/src/pll_sys/cs.rs index 1b935f147..b35975830 100644 --- a/src/pll_sys/cs.rs +++ b/src/pll_sys/cs.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `LOCK` reader - PLL is locked"] pub struct LOCK_R(crate::FieldReader); impl LOCK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { LOCK_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for LOCK_R { #[doc = "Field `BYPASS` reader - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] pub struct BYPASS_R(crate::FieldReader); impl BYPASS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BYPASS_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> BYPASS_W<'a> { PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] pub struct REFDIV_R(crate::FieldReader); impl REFDIV_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { REFDIV_R(crate::FieldReader::new(bits)) } @@ -125,7 +128,9 @@ impl R { pub fn bypass(&self) -> BYPASS_R { BYPASS_R::new(((self.bits >> 8) & 0x01) != 0) } - #[doc = "Bits 0:5 - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] + #[doc = "Bits 0:5 - Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] #[inline(always)] pub fn refdiv(&self) -> REFDIV_R { REFDIV_R::new((self.bits & 0x3f) as u8) @@ -137,7 +142,9 @@ impl W { pub fn bypass(&mut self) -> BYPASS_W { BYPASS_W { w: self } } - #[doc = "Bits 0:5 - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] + #[doc = "Bits 0:5 - Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] #[inline(always)] pub fn refdiv(&mut self) -> REFDIV_W { REFDIV_W { w: self } diff --git a/src/pll_sys/fbdiv_int.rs b/src/pll_sys/fbdiv_int.rs index e02f9bdc5..8e6308bf7 100644 --- a/src/pll_sys/fbdiv_int.rs +++ b/src/pll_sys/fbdiv_int.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `FBDIV_INT` reader - see ctrl reg description for constraints"] pub struct FBDIV_INT_R(crate::FieldReader); impl FBDIV_INT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { FBDIV_INT_R(crate::FieldReader::new(bits)) } diff --git a/src/pll_sys/prim.rs b/src/pll_sys/prim.rs index 4e701f1a4..c507e0863 100644 --- a/src/pll_sys/prim.rs +++ b/src/pll_sys/prim.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `POSTDIV1` reader - divide by 1-7"] pub struct POSTDIV1_R(crate::FieldReader); impl POSTDIV1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { POSTDIV1_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> POSTDIV1_W<'a> { #[doc = "Field `POSTDIV2` reader - divide by 1-7"] pub struct POSTDIV2_R(crate::FieldReader); impl POSTDIV2_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { POSTDIV2_R(crate::FieldReader::new(bits)) } diff --git a/src/pll_sys/pwr.rs b/src/pll_sys/pwr.rs index 42cbac871..0a394e25f 100644 --- a/src/pll_sys/pwr.rs +++ b/src/pll_sys/pwr.rs @@ -38,6 +38,7 @@ impl From> for W { To save power set high when PLL output not required or bypass=1."] pub struct VCOPD_R(crate::FieldReader); impl VCOPD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VCOPD_R(crate::FieldReader::new(bits)) } @@ -76,6 +77,7 @@ impl<'a> VCOPD_W<'a> { To save power set high when PLL output not required or bypass=1."] pub struct POSTDIVPD_R(crate::FieldReader); impl POSTDIVPD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { POSTDIVPD_R(crate::FieldReader::new(bits)) } @@ -114,6 +116,7 @@ impl<'a> POSTDIVPD_W<'a> { Nothing is achieved by setting this low."] pub struct DSMPD_R(crate::FieldReader); impl DSMPD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DSMPD_R(crate::FieldReader::new(bits)) } @@ -152,6 +155,7 @@ impl<'a> DSMPD_W<'a> { To save power set high when PLL output not required."] pub struct PD_R(crate::FieldReader); impl PD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PD_R(crate::FieldReader::new(bits)) } @@ -187,44 +191,52 @@ impl<'a> PD_W<'a> { } } impl R { - #[doc = "Bit 5 - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] + #[doc = "Bit 5 - PLL VCO powerdown + To save power set high when PLL output not required or bypass=1."] #[inline(always)] pub fn vcopd(&self) -> VCOPD_R { VCOPD_R::new(((self.bits >> 5) & 0x01) != 0) } - #[doc = "Bit 3 - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] + #[doc = "Bit 3 - PLL post divider powerdown + To save power set high when PLL output not required or bypass=1."] #[inline(always)] pub fn postdivpd(&self) -> POSTDIVPD_R { POSTDIVPD_R::new(((self.bits >> 3) & 0x01) != 0) } - #[doc = "Bit 2 - PLL DSM powerdown Nothing is achieved by setting this low."] + #[doc = "Bit 2 - PLL DSM powerdown + Nothing is achieved by setting this low."] #[inline(always)] pub fn dsmpd(&self) -> DSMPD_R { DSMPD_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 0 - PLL powerdown To save power set high when PLL output not required."] + #[doc = "Bit 0 - PLL powerdown + To save power set high when PLL output not required."] #[inline(always)] pub fn pd(&self) -> PD_R { PD_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 5 - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] + #[doc = "Bit 5 - PLL VCO powerdown + To save power set high when PLL output not required or bypass=1."] #[inline(always)] pub fn vcopd(&mut self) -> VCOPD_W { VCOPD_W { w: self } } - #[doc = "Bit 3 - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] + #[doc = "Bit 3 - PLL post divider powerdown + To save power set high when PLL output not required or bypass=1."] #[inline(always)] pub fn postdivpd(&mut self) -> POSTDIVPD_W { POSTDIVPD_W { w: self } } - #[doc = "Bit 2 - PLL DSM powerdown Nothing is achieved by setting this low."] + #[doc = "Bit 2 - PLL DSM powerdown + Nothing is achieved by setting this low."] #[inline(always)] pub fn dsmpd(&mut self) -> DSMPD_W { DSMPD_W { w: self } } - #[doc = "Bit 0 - PLL powerdown To save power set high when PLL output not required."] + #[doc = "Bit 0 - PLL powerdown + To save power set high when PLL output not required."] #[inline(always)] pub fn pd(&mut self) -> PD_W { PD_W { w: self } diff --git a/src/ppb/aircr.rs b/src/ppb/aircr.rs index 6a8972d08..f8078e663 100644 --- a/src/ppb/aircr.rs +++ b/src/ppb/aircr.rs @@ -39,6 +39,7 @@ impl From> for W { On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] pub struct VECTKEY_R(crate::FieldReader); impl VECTKEY_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { VECTKEY_R(crate::FieldReader::new(bits)) } @@ -68,6 +69,7 @@ impl<'a> VECTKEY_W<'a> { 0 = Little-endian."] pub struct ENDIANESS_R(crate::FieldReader); impl ENDIANESS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENDIANESS_R(crate::FieldReader::new(bits)) } @@ -82,6 +84,7 @@ impl core::ops::Deref for ENDIANESS_R { #[doc = "Field `SYSRESETREQ` reader - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] pub struct SYSRESETREQ_R(crate::FieldReader); impl SYSRESETREQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SYSRESETREQ_R(crate::FieldReader::new(bits)) } @@ -118,6 +121,7 @@ impl<'a> SYSRESETREQ_W<'a> { #[doc = "Field `VECTCLRACTIVE` reader - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] pub struct VECTCLRACTIVE_R(crate::FieldReader); impl VECTCLRACTIVE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VECTCLRACTIVE_R(crate::FieldReader::new(bits)) } @@ -152,12 +156,15 @@ impl<'a> VECTCLRACTIVE_W<'a> { } } impl R { - #[doc = "Bits 16:31 - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] + #[doc = "Bits 16:31 - Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] #[inline(always)] pub fn vectkey(&self) -> VECTKEY_R { VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) } - #[doc = "Bit 15 - Data endianness implemented: 0 = Little-endian."] + #[doc = "Bit 15 - Data endianness implemented: + 0 = Little-endian."] #[inline(always)] pub fn endianess(&self) -> ENDIANESS_R { ENDIANESS_R::new(((self.bits >> 15) & 0x01) != 0) @@ -174,7 +181,9 @@ impl R { } } impl W { - #[doc = "Bits 16:31 - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] + #[doc = "Bits 16:31 - Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] #[inline(always)] pub fn vectkey(&mut self) -> VECTKEY_W { VECTKEY_W { w: self } diff --git a/src/ppb/ccr.rs b/src/ppb/ccr.rs index f2e563b72..31ec45b2a 100644 --- a/src/ppb/ccr.rs +++ b/src/ppb/ccr.rs @@ -17,6 +17,7 @@ impl From> for R { of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment."] pub struct STKALIGN_R(crate::FieldReader); impl STKALIGN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STKALIGN_R(crate::FieldReader::new(bits)) } @@ -31,6 +32,7 @@ impl core::ops::Deref for STKALIGN_R { #[doc = "Field `UNALIGN_TRP` reader - Always reads as one, indicates that all unaligned accesses generate a HardFault."] pub struct UNALIGN_TRP_R(crate::FieldReader); impl UNALIGN_TRP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UNALIGN_TRP_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/cpuid.rs b/src/ppb/cpuid.rs index 48a6ae0fd..ae2b8c3ba 100644 --- a/src/ppb/cpuid.rs +++ b/src/ppb/cpuid.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `IMPLEMENTER` reader - Implementor code: 0x41 = ARM"] pub struct IMPLEMENTER_R(crate::FieldReader); impl IMPLEMENTER_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IMPLEMENTER_R(crate::FieldReader::new(bits)) } @@ -31,6 +32,7 @@ impl core::ops::Deref for IMPLEMENTER_R { 0x0 = Revision 0."] pub struct VARIANT_R(crate::FieldReader); impl VARIANT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { VARIANT_R(crate::FieldReader::new(bits)) } @@ -46,6 +48,7 @@ impl core::ops::Deref for VARIANT_R { 0xC = ARMv6-M architecture."] pub struct ARCHITECTURE_R(crate::FieldReader); impl ARCHITECTURE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ARCHITECTURE_R(crate::FieldReader::new(bits)) } @@ -60,6 +63,7 @@ impl core::ops::Deref for ARCHITECTURE_R { #[doc = "Field `PARTNO` reader - Number of processor within family: 0xC60 = Cortex-M0+"] pub struct PARTNO_R(crate::FieldReader); impl PARTNO_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { PARTNO_R(crate::FieldReader::new(bits)) } @@ -75,6 +79,7 @@ impl core::ops::Deref for PARTNO_R { 0x1 = Patch 1."] pub struct REVISION_R(crate::FieldReader); impl REVISION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { REVISION_R(crate::FieldReader::new(bits)) } @@ -92,12 +97,14 @@ impl R { pub fn implementer(&self) -> IMPLEMENTER_R { IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) } - #[doc = "Bits 20:23 - Major revision number n in the rnpm revision status: 0x0 = Revision 0."] + #[doc = "Bits 20:23 - Major revision number n in the rnpm revision status: + 0x0 = Revision 0."] #[inline(always)] pub fn variant(&self) -> VARIANT_R { VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) } - #[doc = "Bits 16:19 - Constant that defines the architecture of the processor: 0xC = ARMv6-M architecture."] + #[doc = "Bits 16:19 - Constant that defines the architecture of the processor: + 0xC = ARMv6-M architecture."] #[inline(always)] pub fn architecture(&self) -> ARCHITECTURE_R { ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) @@ -107,7 +114,8 @@ impl R { pub fn partno(&self) -> PARTNO_R { PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) } - #[doc = "Bits 0:3 - Minor revision number m in the rnpm revision status: 0x1 = Patch 1."] + #[doc = "Bits 0:3 - Minor revision number m in the rnpm revision status: + 0x1 = Patch 1."] #[inline(always)] pub fn revision(&self) -> REVISION_R { REVISION_R::new((self.bits & 0x0f) as u8) diff --git a/src/ppb/icsr.rs b/src/ppb/icsr.rs index d0559e1f0..61afcaef1 100644 --- a/src/ppb/icsr.rs +++ b/src/ppb/icsr.rs @@ -48,6 +48,7 @@ impl From> for W { NMI signal is reasserted while the processor is executing that handler."] pub struct NMIPENDSET_R(crate::FieldReader); impl NMIPENDSET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NMIPENDSET_R(crate::FieldReader::new(bits)) } @@ -102,6 +103,7 @@ impl<'a> NMIPENDSET_W<'a> { Writing 1 to this bit is the only way to set the PendSV exception state to pending."] pub struct PENDSVSET_R(crate::FieldReader); impl PENDSVSET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PENDSVSET_R(crate::FieldReader::new(bits)) } @@ -148,6 +150,7 @@ impl<'a> PENDSVSET_W<'a> { 1 = Removes the pending state from the PendSV exception."] pub struct PENDSVCLR_R(crate::FieldReader); impl PENDSVCLR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PENDSVCLR_R(crate::FieldReader::new(bits)) } @@ -193,6 +196,7 @@ impl<'a> PENDSVCLR_W<'a> { 1 = SysTick exception is pending."] pub struct PENDSTSET_R(crate::FieldReader); impl PENDSTSET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PENDSTSET_R(crate::FieldReader::new(bits)) } @@ -239,6 +243,7 @@ impl<'a> PENDSTSET_W<'a> { This bit is WO. On a register read its value is Unknown."] pub struct PENDSTCLR_R(crate::FieldReader); impl PENDSTCLR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PENDSTCLR_R(crate::FieldReader::new(bits)) } @@ -279,6 +284,7 @@ impl<'a> PENDSTCLR_W<'a> { #[doc = "Field `ISRPREEMPT` reader - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced."] pub struct ISRPREEMPT_R(crate::FieldReader); impl ISRPREEMPT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ISRPREEMPT_R(crate::FieldReader::new(bits)) } @@ -293,6 +299,7 @@ impl core::ops::Deref for ISRPREEMPT_R { #[doc = "Field `ISRPENDING` reader - External interrupt pending flag"] pub struct ISRPENDING_R(crate::FieldReader); impl ISRPENDING_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ISRPENDING_R(crate::FieldReader::new(bits)) } @@ -307,6 +314,7 @@ impl core::ops::Deref for ISRPENDING_R { #[doc = "Field `VECTPENDING` reader - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier."] pub struct VECTPENDING_R(crate::FieldReader); impl VECTPENDING_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { VECTPENDING_R(crate::FieldReader::new(bits)) } @@ -321,6 +329,7 @@ impl core::ops::Deref for VECTPENDING_R { #[doc = "Field `VECTACTIVE` reader - Active exception number field. Reset clears the VECTACTIVE field."] pub struct VECTACTIVE_R(crate::FieldReader); impl VECTACTIVE_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { VECTACTIVE_R(crate::FieldReader::new(bits)) } @@ -333,27 +342,58 @@ impl core::ops::Deref for VECTACTIVE_R { } } impl R { - #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler."] + #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. + NMI set-pending bit. + Write: + 0 = No effect. + 1 = Changes NMI exception state to pending. + Read: + 0 = NMI exception is not pending. + 1 = NMI exception is pending. + Because NMI is the highest-priority exception, normally the processor enters the NMI + exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears + this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the + NMI signal is reasserted while the processor is executing that handler."] #[inline(always)] pub fn nmipendset(&self) -> NMIPENDSET_R { NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) } - #[doc = "Bit 28 - PendSV set-pending bit. Write: 0 = No effect. 1 = Changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending."] + #[doc = "Bit 28 - PendSV set-pending bit. + Write: + 0 = No effect. + 1 = Changes PendSV exception state to pending. + Read: + 0 = PendSV exception is not pending. + 1 = PendSV exception is pending. + Writing 1 to this bit is the only way to set the PendSV exception state to pending."] #[inline(always)] pub fn pendsvset(&self) -> PENDSVSET_R { PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) } - #[doc = "Bit 27 - PendSV clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception."] + #[doc = "Bit 27 - PendSV clear-pending bit. + Write: + 0 = No effect. + 1 = Removes the pending state from the PendSV exception."] #[inline(always)] pub fn pendsvclr(&self) -> PENDSVCLR_R { PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) } - #[doc = "Bit 26 - SysTick exception set-pending bit. Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending."] + #[doc = "Bit 26 - SysTick exception set-pending bit. + Write: + 0 = No effect. + 1 = Changes SysTick exception state to pending. + Read: + 0 = SysTick exception is not pending. + 1 = SysTick exception is pending."] #[inline(always)] pub fn pendstset(&self) -> PENDSTSET_R { PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) } - #[doc = "Bit 25 - SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown."] + #[doc = "Bit 25 - SysTick exception clear-pending bit. + Write: + 0 = No effect. + 1 = Removes the pending state from the SysTick exception. + This bit is WO. On a register read its value is Unknown."] #[inline(always)] pub fn pendstclr(&self) -> PENDSTCLR_R { PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) @@ -380,27 +420,58 @@ impl R { } } impl W { - #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler."] + #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. + NMI set-pending bit. + Write: + 0 = No effect. + 1 = Changes NMI exception state to pending. + Read: + 0 = NMI exception is not pending. + 1 = NMI exception is pending. + Because NMI is the highest-priority exception, normally the processor enters the NMI + exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears + this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the + NMI signal is reasserted while the processor is executing that handler."] #[inline(always)] pub fn nmipendset(&mut self) -> NMIPENDSET_W { NMIPENDSET_W { w: self } } - #[doc = "Bit 28 - PendSV set-pending bit. Write: 0 = No effect. 1 = Changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending."] + #[doc = "Bit 28 - PendSV set-pending bit. + Write: + 0 = No effect. + 1 = Changes PendSV exception state to pending. + Read: + 0 = PendSV exception is not pending. + 1 = PendSV exception is pending. + Writing 1 to this bit is the only way to set the PendSV exception state to pending."] #[inline(always)] pub fn pendsvset(&mut self) -> PENDSVSET_W { PENDSVSET_W { w: self } } - #[doc = "Bit 27 - PendSV clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception."] + #[doc = "Bit 27 - PendSV clear-pending bit. + Write: + 0 = No effect. + 1 = Removes the pending state from the PendSV exception."] #[inline(always)] pub fn pendsvclr(&mut self) -> PENDSVCLR_W { PENDSVCLR_W { w: self } } - #[doc = "Bit 26 - SysTick exception set-pending bit. Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending."] + #[doc = "Bit 26 - SysTick exception set-pending bit. + Write: + 0 = No effect. + 1 = Changes SysTick exception state to pending. + Read: + 0 = SysTick exception is not pending. + 1 = SysTick exception is pending."] #[inline(always)] pub fn pendstset(&mut self) -> PENDSTSET_W { PENDSTSET_W { w: self } } - #[doc = "Bit 25 - SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown."] + #[doc = "Bit 25 - SysTick exception clear-pending bit. + Write: + 0 = No effect. + 1 = Removes the pending state from the SysTick exception. + This bit is WO. On a register read its value is Unknown."] #[inline(always)] pub fn pendstclr(&mut self) -> PENDSTCLR_W { PENDSTCLR_W { w: self } diff --git a/src/ppb/mpu_ctrl.rs b/src/ppb/mpu_ctrl.rs index d2f0f6efd..900d44f0e 100644 --- a/src/ppb/mpu_ctrl.rs +++ b/src/ppb/mpu_ctrl.rs @@ -41,6 +41,7 @@ impl From> for W { When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] pub struct PRIVDEFENA_R(crate::FieldReader); impl PRIVDEFENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PRIVDEFENA_R(crate::FieldReader::new(bits)) } @@ -84,6 +85,7 @@ impl<'a> PRIVDEFENA_W<'a> { 1 = the MPU is enabled during HardFault and NMI handlers."] pub struct HFNMIENA_R(crate::FieldReader); impl HFNMIENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HFNMIENA_R(crate::FieldReader::new(bits)) } @@ -125,6 +127,7 @@ impl<'a> HFNMIENA_W<'a> { 1 = MPU enabled."] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -161,34 +164,52 @@ impl<'a> ENABLE_W<'a> { } } impl R { - #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] + #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. + 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not + covered by any enabled region causes a fault. + 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. + When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] #[inline(always)] pub fn privdefena(&self) -> PRIVDEFENA_R { PRIVDEFENA_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers."] + #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. + When the MPU is enabled: + 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. + 1 = the MPU is enabled during HardFault and NMI handlers."] #[inline(always)] pub fn hfnmiena(&self) -> HFNMIENA_R { HFNMIENA_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled."] + #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. + 0 = MPU disabled. + 1 = MPU enabled."] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] + #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. + 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not + covered by any enabled region causes a fault. + 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. + When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] #[inline(always)] pub fn privdefena(&mut self) -> PRIVDEFENA_W { PRIVDEFENA_W { w: self } } - #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers."] + #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. + When the MPU is enabled: + 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. + 1 = the MPU is enabled during HardFault and NMI handlers."] #[inline(always)] pub fn hfnmiena(&mut self) -> HFNMIENA_W { HFNMIENA_W { w: self } } - #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled."] + #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. + 0 = MPU disabled. + 1 = MPU enabled."] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } diff --git a/src/ppb/mpu_rasr.rs b/src/ppb/mpu_rasr.rs index dd335e9f3..e72393617 100644 --- a/src/ppb/mpu_rasr.rs +++ b/src/ppb/mpu_rasr.rs @@ -44,6 +44,7 @@ impl From> for W { 16 = B: Bufferable bit"] pub struct ATTRS_R(crate::FieldReader); impl ATTRS_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { ATTRS_R(crate::FieldReader::new(bits)) } @@ -77,6 +78,7 @@ impl<'a> ATTRS_W<'a> { #[doc = "Field `SRD` reader - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."] pub struct SRD_R(crate::FieldReader); impl SRD_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SRD_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> SRD_W<'a> { #[doc = "Field `SIZE` reader - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes"] pub struct SIZE_R(crate::FieldReader); impl SIZE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SIZE_R(crate::FieldReader::new(bits)) } @@ -129,6 +132,7 @@ impl<'a> SIZE_W<'a> { #[doc = "Field `ENABLE` reader - Enables the region."] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -163,7 +167,14 @@ impl<'a> ENABLE_W<'a> { } } impl R { - #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. 26:24 = AP: Access permission field 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit"] + #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. + 28 = XN: Instruction access disable bit: + 0 = Instruction fetches enabled. + 1 = Instruction fetches disabled. + 26:24 = AP: Access permission field + 18 = S: Shareable bit + 17 = C: Cacheable bit + 16 = B: Bufferable bit"] #[inline(always)] pub fn attrs(&self) -> ATTRS_R { ATTRS_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -185,7 +196,14 @@ impl R { } } impl W { - #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. 26:24 = AP: Access permission field 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit"] + #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. + 28 = XN: Instruction access disable bit: + 0 = Instruction fetches enabled. + 1 = Instruction fetches disabled. + 26:24 = AP: Access permission field + 18 = S: Shareable bit + 17 = C: Cacheable bit + 16 = B: Bufferable bit"] #[inline(always)] pub fn attrs(&mut self) -> ATTRS_W { ATTRS_W { w: self } diff --git a/src/ppb/mpu_rbar.rs b/src/ppb/mpu_rbar.rs index 23f06d5be..a6d512e5d 100644 --- a/src/ppb/mpu_rbar.rs +++ b/src/ppb/mpu_rbar.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ADDR` reader - Base address of the region."] pub struct ADDR_R(crate::FieldReader); impl ADDR_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { ADDR_R(crate::FieldReader::new(bits)) } @@ -71,6 +72,7 @@ impl<'a> ADDR_W<'a> { Always reads as zero."] pub struct VALID_R(crate::FieldReader); impl VALID_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VALID_R(crate::FieldReader::new(bits)) } @@ -116,6 +118,7 @@ impl<'a> VALID_W<'a> { of MPU_RNR."] pub struct REGION_R(crate::FieldReader); impl REGION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { REGION_R(crate::FieldReader::new(bits)) } @@ -146,7 +149,15 @@ impl R { pub fn addr(&self) -> ADDR_R { ADDR_R::new(((self.bits >> 8) & 0x00ff_ffff) as u32) } - #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero."] + #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. + Write: + 0 = MPU_RNR not changed, and the processor: + Updates the base address for the region specified in the MPU_RNR. + Ignores the value of the REGION field. + 1 = The processor: + Updates the value of the MPU_RNR to the value of the REGION field. + Updates the base address for the region specified in the REGION field. + Always reads as zero."] #[inline(always)] pub fn valid(&self) -> VALID_R { VALID_R::new(((self.bits >> 4) & 0x01) != 0) @@ -164,7 +175,15 @@ impl W { pub fn addr(&mut self) -> ADDR_W { ADDR_W { w: self } } - #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero."] + #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. + Write: + 0 = MPU_RNR not changed, and the processor: + Updates the base address for the region specified in the MPU_RNR. + Ignores the value of the REGION field. + 1 = The processor: + Updates the value of the MPU_RNR to the value of the REGION field. + Updates the base address for the region specified in the REGION field. + Always reads as zero."] #[inline(always)] pub fn valid(&mut self) -> VALID_W { VALID_W { w: self } diff --git a/src/ppb/mpu_rnr.rs b/src/ppb/mpu_rnr.rs index 188df7feb..356b75636 100644 --- a/src/ppb/mpu_rnr.rs +++ b/src/ppb/mpu_rnr.rs @@ -38,6 +38,7 @@ impl From> for W { The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] pub struct REGION_R(crate::FieldReader); impl REGION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { REGION_R(crate::FieldReader::new(bits)) } @@ -63,14 +64,16 @@ impl<'a> REGION_W<'a> { } } impl R { - #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] + #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. + The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] #[inline(always)] pub fn region(&self) -> REGION_R { REGION_R::new((self.bits & 0x0f) as u8) } } impl W { - #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] + #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. + The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] #[inline(always)] pub fn region(&mut self) -> REGION_W { REGION_W { w: self } diff --git a/src/ppb/mpu_type.rs b/src/ppb/mpu_type.rs index aeac6e7be..47f221e1f 100644 --- a/src/ppb/mpu_type.rs +++ b/src/ppb/mpu_type.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `IREGION` reader - Instruction region. Reads as zero as ARMv6-M only supports a unified MPU."] pub struct IREGION_R(crate::FieldReader); impl IREGION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IREGION_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for IREGION_R { #[doc = "Field `DREGION` reader - Number of regions supported by the MPU."] pub struct DREGION_R(crate::FieldReader); impl DREGION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DREGION_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for DREGION_R { #[doc = "Field `SEPARATE` reader - Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU."] pub struct SEPARATE_R(crate::FieldReader); impl SEPARATE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SEPARATE_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_icer.rs b/src/ppb/nvic_icer.rs index d303b2b72..a10d7629e 100644 --- a/src/ppb/nvic_icer.rs +++ b/src/ppb/nvic_icer.rs @@ -43,6 +43,7 @@ impl From> for W { 1 = Interrupt enabled."] pub struct CLRENA_R(crate::FieldReader); impl CLRENA_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { CLRENA_R(crate::FieldReader::new(bits)) } @@ -73,14 +74,26 @@ impl<'a> CLRENA_W<'a> { } } impl R { - #[doc = "Bits 0:31 - Interrupt clear-enable bits. Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] + #[doc = "Bits 0:31 - Interrupt clear-enable bits. + Write: + 0 = No effect. + 1 = Disable interrupt. + Read: + 0 = Interrupt disabled. + 1 = Interrupt enabled."] #[inline(always)] pub fn clrena(&self) -> CLRENA_R { CLRENA_R::new((self.bits & 0xffff_ffff) as u32) } } impl W { - #[doc = "Bits 0:31 - Interrupt clear-enable bits. Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] + #[doc = "Bits 0:31 - Interrupt clear-enable bits. + Write: + 0 = No effect. + 1 = Disable interrupt. + Read: + 0 = Interrupt disabled. + 1 = Interrupt enabled."] #[inline(always)] pub fn clrena(&mut self) -> CLRENA_W { CLRENA_W { w: self } diff --git a/src/ppb/nvic_icpr.rs b/src/ppb/nvic_icpr.rs index dcb1973c9..c641955c3 100644 --- a/src/ppb/nvic_icpr.rs +++ b/src/ppb/nvic_icpr.rs @@ -43,6 +43,7 @@ impl From> for W { 1 = Interrupt is pending."] pub struct CLRPEND_R(crate::FieldReader); impl CLRPEND_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { CLRPEND_R(crate::FieldReader::new(bits)) } @@ -73,14 +74,26 @@ impl<'a> CLRPEND_W<'a> { } } impl R { - #[doc = "Bits 0:31 - Interrupt clear-pending bits. Write: 0 = No effect. 1 = Removes pending state and interrupt. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending."] + #[doc = "Bits 0:31 - Interrupt clear-pending bits. + Write: + 0 = No effect. + 1 = Removes pending state and interrupt. + Read: + 0 = Interrupt is not pending. + 1 = Interrupt is pending."] #[inline(always)] pub fn clrpend(&self) -> CLRPEND_R { CLRPEND_R::new((self.bits & 0xffff_ffff) as u32) } } impl W { - #[doc = "Bits 0:31 - Interrupt clear-pending bits. Write: 0 = No effect. 1 = Removes pending state and interrupt. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending."] + #[doc = "Bits 0:31 - Interrupt clear-pending bits. + Write: + 0 = No effect. + 1 = Removes pending state and interrupt. + Read: + 0 = Interrupt is not pending. + 1 = Interrupt is pending."] #[inline(always)] pub fn clrpend(&mut self) -> CLRPEND_W { CLRPEND_W { w: self } diff --git a/src/ppb/nvic_ipr0.rs b/src/ppb/nvic_ipr0.rs index 79cf27eac..b26605ff0 100644 --- a/src/ppb/nvic_ipr0.rs +++ b/src/ppb/nvic_ipr0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IP_3` reader - Priority of interrupt 3"] pub struct IP_3_R(crate::FieldReader); impl IP_3_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_3_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> IP_3_W<'a> { #[doc = "Field `IP_2` reader - Priority of interrupt 2"] pub struct IP_2_R(crate::FieldReader); impl IP_2_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_2_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> IP_2_W<'a> { #[doc = "Field `IP_1` reader - Priority of interrupt 1"] pub struct IP_1_R(crate::FieldReader); impl IP_1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_1_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> IP_1_W<'a> { #[doc = "Field `IP_0` reader - Priority of interrupt 0"] pub struct IP_0_R(crate::FieldReader); impl IP_0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_0_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_ipr1.rs b/src/ppb/nvic_ipr1.rs index 238a006cc..5674b211a 100644 --- a/src/ppb/nvic_ipr1.rs +++ b/src/ppb/nvic_ipr1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IP_7` reader - Priority of interrupt 7"] pub struct IP_7_R(crate::FieldReader); impl IP_7_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_7_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> IP_7_W<'a> { #[doc = "Field `IP_6` reader - Priority of interrupt 6"] pub struct IP_6_R(crate::FieldReader); impl IP_6_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_6_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> IP_6_W<'a> { #[doc = "Field `IP_5` reader - Priority of interrupt 5"] pub struct IP_5_R(crate::FieldReader); impl IP_5_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_5_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> IP_5_W<'a> { #[doc = "Field `IP_4` reader - Priority of interrupt 4"] pub struct IP_4_R(crate::FieldReader); impl IP_4_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_4_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_ipr2.rs b/src/ppb/nvic_ipr2.rs index 7c92e12c5..39a21f2f1 100644 --- a/src/ppb/nvic_ipr2.rs +++ b/src/ppb/nvic_ipr2.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IP_11` reader - Priority of interrupt 11"] pub struct IP_11_R(crate::FieldReader); impl IP_11_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_11_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> IP_11_W<'a> { #[doc = "Field `IP_10` reader - Priority of interrupt 10"] pub struct IP_10_R(crate::FieldReader); impl IP_10_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_10_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> IP_10_W<'a> { #[doc = "Field `IP_9` reader - Priority of interrupt 9"] pub struct IP_9_R(crate::FieldReader); impl IP_9_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_9_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> IP_9_W<'a> { #[doc = "Field `IP_8` reader - Priority of interrupt 8"] pub struct IP_8_R(crate::FieldReader); impl IP_8_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_8_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_ipr3.rs b/src/ppb/nvic_ipr3.rs index 3a0850b18..424fd85c0 100644 --- a/src/ppb/nvic_ipr3.rs +++ b/src/ppb/nvic_ipr3.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IP_15` reader - Priority of interrupt 15"] pub struct IP_15_R(crate::FieldReader); impl IP_15_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_15_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> IP_15_W<'a> { #[doc = "Field `IP_14` reader - Priority of interrupt 14"] pub struct IP_14_R(crate::FieldReader); impl IP_14_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_14_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> IP_14_W<'a> { #[doc = "Field `IP_13` reader - Priority of interrupt 13"] pub struct IP_13_R(crate::FieldReader); impl IP_13_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_13_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> IP_13_W<'a> { #[doc = "Field `IP_12` reader - Priority of interrupt 12"] pub struct IP_12_R(crate::FieldReader); impl IP_12_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_12_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_ipr4.rs b/src/ppb/nvic_ipr4.rs index 4e57cfb90..75dfdfadb 100644 --- a/src/ppb/nvic_ipr4.rs +++ b/src/ppb/nvic_ipr4.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IP_19` reader - Priority of interrupt 19"] pub struct IP_19_R(crate::FieldReader); impl IP_19_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_19_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> IP_19_W<'a> { #[doc = "Field `IP_18` reader - Priority of interrupt 18"] pub struct IP_18_R(crate::FieldReader); impl IP_18_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_18_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> IP_18_W<'a> { #[doc = "Field `IP_17` reader - Priority of interrupt 17"] pub struct IP_17_R(crate::FieldReader); impl IP_17_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_17_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> IP_17_W<'a> { #[doc = "Field `IP_16` reader - Priority of interrupt 16"] pub struct IP_16_R(crate::FieldReader); impl IP_16_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_16_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_ipr5.rs b/src/ppb/nvic_ipr5.rs index 6dcd40231..35fab226f 100644 --- a/src/ppb/nvic_ipr5.rs +++ b/src/ppb/nvic_ipr5.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IP_23` reader - Priority of interrupt 23"] pub struct IP_23_R(crate::FieldReader); impl IP_23_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_23_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> IP_23_W<'a> { #[doc = "Field `IP_22` reader - Priority of interrupt 22"] pub struct IP_22_R(crate::FieldReader); impl IP_22_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_22_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> IP_22_W<'a> { #[doc = "Field `IP_21` reader - Priority of interrupt 21"] pub struct IP_21_R(crate::FieldReader); impl IP_21_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_21_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> IP_21_W<'a> { #[doc = "Field `IP_20` reader - Priority of interrupt 20"] pub struct IP_20_R(crate::FieldReader); impl IP_20_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_20_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_ipr6.rs b/src/ppb/nvic_ipr6.rs index be05c4e73..8c06f6589 100644 --- a/src/ppb/nvic_ipr6.rs +++ b/src/ppb/nvic_ipr6.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IP_27` reader - Priority of interrupt 27"] pub struct IP_27_R(crate::FieldReader); impl IP_27_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_27_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> IP_27_W<'a> { #[doc = "Field `IP_26` reader - Priority of interrupt 26"] pub struct IP_26_R(crate::FieldReader); impl IP_26_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_26_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> IP_26_W<'a> { #[doc = "Field `IP_25` reader - Priority of interrupt 25"] pub struct IP_25_R(crate::FieldReader); impl IP_25_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_25_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> IP_25_W<'a> { #[doc = "Field `IP_24` reader - Priority of interrupt 24"] pub struct IP_24_R(crate::FieldReader); impl IP_24_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_24_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_ipr7.rs b/src/ppb/nvic_ipr7.rs index 50ee57efd..2ae8d327e 100644 --- a/src/ppb/nvic_ipr7.rs +++ b/src/ppb/nvic_ipr7.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `IP_31` reader - Priority of interrupt 31"] pub struct IP_31_R(crate::FieldReader); impl IP_31_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_31_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> IP_31_W<'a> { #[doc = "Field `IP_30` reader - Priority of interrupt 30"] pub struct IP_30_R(crate::FieldReader); impl IP_30_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_30_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> IP_30_W<'a> { #[doc = "Field `IP_29` reader - Priority of interrupt 29"] pub struct IP_29_R(crate::FieldReader); impl IP_29_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_29_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> IP_29_W<'a> { #[doc = "Field `IP_28` reader - Priority of interrupt 28"] pub struct IP_28_R(crate::FieldReader); impl IP_28_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { IP_28_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/nvic_iser.rs b/src/ppb/nvic_iser.rs index 27286b269..75f29ea64 100644 --- a/src/ppb/nvic_iser.rs +++ b/src/ppb/nvic_iser.rs @@ -43,6 +43,7 @@ impl From> for W { 1 = Interrupt enabled."] pub struct SETENA_R(crate::FieldReader); impl SETENA_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { SETENA_R(crate::FieldReader::new(bits)) } @@ -73,14 +74,26 @@ impl<'a> SETENA_W<'a> { } } impl R { - #[doc = "Bits 0:31 - Interrupt set-enable bits. Write: 0 = No effect. 1 = Enable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] + #[doc = "Bits 0:31 - Interrupt set-enable bits. + Write: + 0 = No effect. + 1 = Enable interrupt. + Read: + 0 = Interrupt disabled. + 1 = Interrupt enabled."] #[inline(always)] pub fn setena(&self) -> SETENA_R { SETENA_R::new((self.bits & 0xffff_ffff) as u32) } } impl W { - #[doc = "Bits 0:31 - Interrupt set-enable bits. Write: 0 = No effect. 1 = Enable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] + #[doc = "Bits 0:31 - Interrupt set-enable bits. + Write: + 0 = No effect. + 1 = Enable interrupt. + Read: + 0 = Interrupt disabled. + 1 = Interrupt enabled."] #[inline(always)] pub fn setena(&mut self) -> SETENA_W { SETENA_W { w: self } diff --git a/src/ppb/nvic_ispr.rs b/src/ppb/nvic_ispr.rs index 723c27b9c..3f1162db2 100644 --- a/src/ppb/nvic_ispr.rs +++ b/src/ppb/nvic_ispr.rs @@ -46,6 +46,7 @@ impl From> for W { A disabled interrupt sets the state of that interrupt to pending."] pub struct SETPEND_R(crate::FieldReader); impl SETPEND_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { SETPEND_R(crate::FieldReader::new(bits)) } @@ -79,14 +80,32 @@ impl<'a> SETPEND_W<'a> { } } impl R { - #[doc = "Bits 0:31 - Interrupt set-pending bits. Write: 0 = No effect. 1 = Changes interrupt state to pending. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending."] + #[doc = "Bits 0:31 - Interrupt set-pending bits. + Write: + 0 = No effect. + 1 = Changes interrupt state to pending. + Read: + 0 = Interrupt is not pending. + 1 = Interrupt is pending. + Note: Writing 1 to the NVIC_ISPR bit corresponding to: + An interrupt that is pending has no effect. + A disabled interrupt sets the state of that interrupt to pending."] #[inline(always)] pub fn setpend(&self) -> SETPEND_R { SETPEND_R::new((self.bits & 0xffff_ffff) as u32) } } impl W { - #[doc = "Bits 0:31 - Interrupt set-pending bits. Write: 0 = No effect. 1 = Changes interrupt state to pending. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending."] + #[doc = "Bits 0:31 - Interrupt set-pending bits. + Write: + 0 = No effect. + 1 = Changes interrupt state to pending. + Read: + 0 = Interrupt is not pending. + 1 = Interrupt is pending. + Note: Writing 1 to the NVIC_ISPR bit corresponding to: + An interrupt that is pending has no effect. + A disabled interrupt sets the state of that interrupt to pending."] #[inline(always)] pub fn setpend(&mut self) -> SETPEND_W { SETPEND_W { w: self } diff --git a/src/ppb/scr.rs b/src/ppb/scr.rs index 09d4983c4..dded0dbe9 100644 --- a/src/ppb/scr.rs +++ b/src/ppb/scr.rs @@ -42,6 +42,7 @@ impl From> for W { The processor also wakes up on execution of an SEV instruction or an external event."] pub struct SEVONPEND_R(crate::FieldReader); impl SEVONPEND_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SEVONPEND_R(crate::FieldReader::new(bits)) } @@ -85,6 +86,7 @@ impl<'a> SEVONPEND_W<'a> { 1 = Deep sleep."] pub struct SLEEPDEEP_R(crate::FieldReader); impl SLEEPDEEP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEEPDEEP_R(crate::FieldReader::new(bits)) } @@ -126,6 +128,7 @@ impl<'a> SLEEPDEEP_W<'a> { Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] pub struct SLEEPONEXIT_R(crate::FieldReader); impl SLEEPONEXIT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLEEPONEXIT_R(crate::FieldReader::new(bits)) } @@ -163,34 +166,54 @@ impl<'a> SLEEPONEXIT_W<'a> { } } impl R { - #[doc = "Bit 4 - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] + #[doc = "Bit 4 - Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event."] #[inline(always)] pub fn sevonpend(&self) -> SEVONPEND_R { SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) } - #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] + #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep."] #[inline(always)] pub fn sleepdeep(&self) -> SLEEPDEEP_R { SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] + #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] #[inline(always)] pub fn sleeponexit(&self) -> SLEEPONEXIT_R { SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) } } impl W { - #[doc = "Bit 4 - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] + #[doc = "Bit 4 - Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event."] #[inline(always)] pub fn sevonpend(&mut self) -> SEVONPEND_W { SEVONPEND_W { w: self } } - #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] + #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep."] #[inline(always)] pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { SLEEPDEEP_W { w: self } } - #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] + #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] #[inline(always)] pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { SLEEPONEXIT_W { w: self } diff --git a/src/ppb/shcsr.rs b/src/ppb/shcsr.rs index cb23f3118..4bf63c79e 100644 --- a/src/ppb/shcsr.rs +++ b/src/ppb/shcsr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SVCALLPENDED` reader - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall."] pub struct SVCALLPENDED_R(crate::FieldReader); impl SVCALLPENDED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SVCALLPENDED_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/shpr2.rs b/src/ppb/shpr2.rs index 3c804a773..db855b285 100644 --- a/src/ppb/shpr2.rs +++ b/src/ppb/shpr2.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] pub struct PRI_11_R(crate::FieldReader); impl PRI_11_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PRI_11_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/shpr3.rs b/src/ppb/shpr3.rs index 4ea22f82e..3c9912493 100644 --- a/src/ppb/shpr3.rs +++ b/src/ppb/shpr3.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick"] pub struct PRI_15_R(crate::FieldReader); impl PRI_15_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PRI_15_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> PRI_15_W<'a> { #[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] pub struct PRI_14_R(crate::FieldReader); impl PRI_14_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PRI_14_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/syst_calib.rs b/src/ppb/syst_calib.rs index d4ec3b350..45c780ccb 100644 --- a/src/ppb/syst_calib.rs +++ b/src/ppb/syst_calib.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `NOREF` reader - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0."] pub struct NOREF_R(crate::FieldReader); impl NOREF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NOREF_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for NOREF_R { #[doc = "Field `SKEW` reader - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)."] pub struct SKEW_R(crate::FieldReader); impl SKEW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SKEW_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for SKEW_R { #[doc = "Field `TENMS` reader - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known."] pub struct TENMS_R(crate::FieldReader); impl TENMS_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { TENMS_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/syst_csr.rs b/src/ppb/syst_csr.rs index a57b93808..897f75b29 100644 --- a/src/ppb/syst_csr.rs +++ b/src/ppb/syst_csr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `COUNTFLAG` reader - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger."] pub struct COUNTFLAG_R(crate::FieldReader); impl COUNTFLAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { COUNTFLAG_R(crate::FieldReader::new(bits)) } @@ -54,6 +55,7 @@ impl core::ops::Deref for COUNTFLAG_R { 1 = Processor clock."] pub struct CLKSOURCE_R(crate::FieldReader); impl CLKSOURCE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLKSOURCE_R(crate::FieldReader::new(bits)) } @@ -95,6 +97,7 @@ impl<'a> CLKSOURCE_W<'a> { 1 = Counting down to zero to asserts the SysTick exception request."] pub struct TICKINT_R(crate::FieldReader); impl TICKINT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TICKINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> TICKINT_W<'a> { 1 = Counter enabled."] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -176,34 +180,48 @@ impl R { pub fn countflag(&self) -> COUNTFLAG_R { COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) } - #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] + #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock."] #[inline(always)] pub fn clksource(&self) -> CLKSOURCE_R { CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bit 1 - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] + #[doc = "Bit 1 - Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request."] #[inline(always)] pub fn tickint(&self) -> TICKINT_R { TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] + #[doc = "Bit 0 - Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled."] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] + #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock."] #[inline(always)] pub fn clksource(&mut self) -> CLKSOURCE_W { CLKSOURCE_W { w: self } } - #[doc = "Bit 1 - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] + #[doc = "Bit 1 - Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request."] #[inline(always)] pub fn tickint(&mut self) -> TICKINT_W { TICKINT_W { w: self } } - #[doc = "Bit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] + #[doc = "Bit 0 - Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled."] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } diff --git a/src/ppb/syst_cvr.rs b/src/ppb/syst_cvr.rs index 54a5516cf..375073a4d 100644 --- a/src/ppb/syst_cvr.rs +++ b/src/ppb/syst_cvr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CURRENT` reader - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] pub struct CURRENT_R(crate::FieldReader); impl CURRENT_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { CURRENT_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/syst_rvr.rs b/src/ppb/syst_rvr.rs index 5f26ed57f..2ad9be4a4 100644 --- a/src/ppb/syst_rvr.rs +++ b/src/ppb/syst_rvr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0."] pub struct RELOAD_R(crate::FieldReader); impl RELOAD_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { RELOAD_R(crate::FieldReader::new(bits)) } diff --git a/src/ppb/vtor.rs b/src/ppb/vtor.rs index 34b96b871..e9f5b1d2e 100644 --- a/src/ppb/vtor.rs +++ b/src/ppb/vtor.rs @@ -38,6 +38,7 @@ impl From> for W { of the indicate the vector table offset address."] pub struct TBLOFF_R(crate::FieldReader); impl TBLOFF_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { TBLOFF_R(crate::FieldReader::new(bits)) } diff --git a/src/psm/done.rs b/src/psm/done.rs index 15f71728c..7aaf33345 100644 --- a/src/psm/done.rs +++ b/src/psm/done.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `proc1` reader - "] pub struct PROC1_R(crate::FieldReader); impl PROC1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for PROC1_R { #[doc = "Field `proc0` reader - "] pub struct PROC0_R(crate::FieldReader); impl PROC0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for PROC0_R { #[doc = "Field `sio` reader - "] pub struct SIO_R(crate::FieldReader); impl SIO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIO_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for SIO_R { #[doc = "Field `vreg_and_chip_reset` reader - "] pub struct VREG_AND_CHIP_RESET_R(crate::FieldReader); impl VREG_AND_CHIP_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VREG_AND_CHIP_RESET_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for VREG_AND_CHIP_RESET_R { #[doc = "Field `xip` reader - "] pub struct XIP_R(crate::FieldReader); impl XIP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { XIP_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for XIP_R { #[doc = "Field `sram5` reader - "] pub struct SRAM5_R(crate::FieldReader); impl SRAM5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM5_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for SRAM5_R { #[doc = "Field `sram4` reader - "] pub struct SRAM4_R(crate::FieldReader); impl SRAM4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM4_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for SRAM4_R { #[doc = "Field `sram3` reader - "] pub struct SRAM3_R(crate::FieldReader); impl SRAM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM3_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for SRAM3_R { #[doc = "Field `sram2` reader - "] pub struct SRAM2_R(crate::FieldReader); impl SRAM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM2_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for SRAM2_R { #[doc = "Field `sram1` reader - "] pub struct SRAM1_R(crate::FieldReader); impl SRAM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM1_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for SRAM1_R { #[doc = "Field `sram0` reader - "] pub struct SRAM0_R(crate::FieldReader); impl SRAM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM0_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for SRAM0_R { #[doc = "Field `rom` reader - "] pub struct ROM_R(crate::FieldReader); impl ROM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROM_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for ROM_R { #[doc = "Field `busfabric` reader - "] pub struct BUSFABRIC_R(crate::FieldReader); impl BUSFABRIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSFABRIC_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for BUSFABRIC_R { #[doc = "Field `resets` reader - "] pub struct RESETS_R(crate::FieldReader); impl RESETS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESETS_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for RESETS_R { #[doc = "Field `clocks` reader - "] pub struct CLOCKS_R(crate::FieldReader); impl CLOCKS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLOCKS_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for CLOCKS_R { #[doc = "Field `xosc` reader - "] pub struct XOSC_R(crate::FieldReader); impl XOSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { XOSC_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for XOSC_R { #[doc = "Field `rosc` reader - "] pub struct ROSC_R(crate::FieldReader); impl ROSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROSC_R(crate::FieldReader::new(bits)) } diff --git a/src/psm/frce_off.rs b/src/psm/frce_off.rs index ab391efb6..3adce1467 100644 --- a/src/psm/frce_off.rs +++ b/src/psm/frce_off.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `proc1` reader - "] pub struct PROC1_R(crate::FieldReader); impl PROC1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> PROC1_W<'a> { #[doc = "Field `proc0` reader - "] pub struct PROC0_R(crate::FieldReader); impl PROC0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> PROC0_W<'a> { #[doc = "Field `sio` reader - "] pub struct SIO_R(crate::FieldReader); impl SIO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIO_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> SIO_W<'a> { #[doc = "Field `vreg_and_chip_reset` reader - "] pub struct VREG_AND_CHIP_RESET_R(crate::FieldReader); impl VREG_AND_CHIP_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VREG_AND_CHIP_RESET_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> VREG_AND_CHIP_RESET_W<'a> { #[doc = "Field `xip` reader - "] pub struct XIP_R(crate::FieldReader); impl XIP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { XIP_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> XIP_W<'a> { #[doc = "Field `sram5` reader - "] pub struct SRAM5_R(crate::FieldReader); impl SRAM5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM5_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> SRAM5_W<'a> { #[doc = "Field `sram4` reader - "] pub struct SRAM4_R(crate::FieldReader); impl SRAM4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM4_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> SRAM4_W<'a> { #[doc = "Field `sram3` reader - "] pub struct SRAM3_R(crate::FieldReader); impl SRAM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM3_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> SRAM3_W<'a> { #[doc = "Field `sram2` reader - "] pub struct SRAM2_R(crate::FieldReader); impl SRAM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM2_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> SRAM2_W<'a> { #[doc = "Field `sram1` reader - "] pub struct SRAM1_R(crate::FieldReader); impl SRAM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM1_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> SRAM1_W<'a> { #[doc = "Field `sram0` reader - "] pub struct SRAM0_R(crate::FieldReader); impl SRAM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM0_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> SRAM0_W<'a> { #[doc = "Field `rom` reader - "] pub struct ROM_R(crate::FieldReader); impl ROM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROM_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> ROM_W<'a> { #[doc = "Field `busfabric` reader - "] pub struct BUSFABRIC_R(crate::FieldReader); impl BUSFABRIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSFABRIC_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> BUSFABRIC_W<'a> { #[doc = "Field `resets` reader - "] pub struct RESETS_R(crate::FieldReader); impl RESETS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESETS_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> RESETS_W<'a> { #[doc = "Field `clocks` reader - "] pub struct CLOCKS_R(crate::FieldReader); impl CLOCKS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLOCKS_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> CLOCKS_W<'a> { #[doc = "Field `xosc` reader - "] pub struct XOSC_R(crate::FieldReader); impl XOSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { XOSC_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> XOSC_W<'a> { #[doc = "Field `rosc` reader - "] pub struct ROSC_R(crate::FieldReader); impl ROSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROSC_R(crate::FieldReader::new(bits)) } diff --git a/src/psm/frce_on.rs b/src/psm/frce_on.rs index b8b8bf717..9cfc0ecbf 100644 --- a/src/psm/frce_on.rs +++ b/src/psm/frce_on.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `proc1` reader - "] pub struct PROC1_R(crate::FieldReader); impl PROC1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> PROC1_W<'a> { #[doc = "Field `proc0` reader - "] pub struct PROC0_R(crate::FieldReader); impl PROC0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> PROC0_W<'a> { #[doc = "Field `sio` reader - "] pub struct SIO_R(crate::FieldReader); impl SIO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIO_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> SIO_W<'a> { #[doc = "Field `vreg_and_chip_reset` reader - "] pub struct VREG_AND_CHIP_RESET_R(crate::FieldReader); impl VREG_AND_CHIP_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VREG_AND_CHIP_RESET_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> VREG_AND_CHIP_RESET_W<'a> { #[doc = "Field `xip` reader - "] pub struct XIP_R(crate::FieldReader); impl XIP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { XIP_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> XIP_W<'a> { #[doc = "Field `sram5` reader - "] pub struct SRAM5_R(crate::FieldReader); impl SRAM5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM5_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> SRAM5_W<'a> { #[doc = "Field `sram4` reader - "] pub struct SRAM4_R(crate::FieldReader); impl SRAM4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM4_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> SRAM4_W<'a> { #[doc = "Field `sram3` reader - "] pub struct SRAM3_R(crate::FieldReader); impl SRAM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM3_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> SRAM3_W<'a> { #[doc = "Field `sram2` reader - "] pub struct SRAM2_R(crate::FieldReader); impl SRAM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM2_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> SRAM2_W<'a> { #[doc = "Field `sram1` reader - "] pub struct SRAM1_R(crate::FieldReader); impl SRAM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM1_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> SRAM1_W<'a> { #[doc = "Field `sram0` reader - "] pub struct SRAM0_R(crate::FieldReader); impl SRAM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM0_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> SRAM0_W<'a> { #[doc = "Field `rom` reader - "] pub struct ROM_R(crate::FieldReader); impl ROM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROM_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> ROM_W<'a> { #[doc = "Field `busfabric` reader - "] pub struct BUSFABRIC_R(crate::FieldReader); impl BUSFABRIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSFABRIC_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> BUSFABRIC_W<'a> { #[doc = "Field `resets` reader - "] pub struct RESETS_R(crate::FieldReader); impl RESETS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESETS_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> RESETS_W<'a> { #[doc = "Field `clocks` reader - "] pub struct CLOCKS_R(crate::FieldReader); impl CLOCKS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLOCKS_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> CLOCKS_W<'a> { #[doc = "Field `xosc` reader - "] pub struct XOSC_R(crate::FieldReader); impl XOSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { XOSC_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> XOSC_W<'a> { #[doc = "Field `rosc` reader - "] pub struct ROSC_R(crate::FieldReader); impl ROSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROSC_R(crate::FieldReader::new(bits)) } diff --git a/src/psm/wdsel.rs b/src/psm/wdsel.rs index 3212e3a95..8a4832681 100644 --- a/src/psm/wdsel.rs +++ b/src/psm/wdsel.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `proc1` reader - "] pub struct PROC1_R(crate::FieldReader); impl PROC1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> PROC1_W<'a> { #[doc = "Field `proc0` reader - "] pub struct PROC0_R(crate::FieldReader); impl PROC0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> PROC0_W<'a> { #[doc = "Field `sio` reader - "] pub struct SIO_R(crate::FieldReader); impl SIO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIO_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> SIO_W<'a> { #[doc = "Field `vreg_and_chip_reset` reader - "] pub struct VREG_AND_CHIP_RESET_R(crate::FieldReader); impl VREG_AND_CHIP_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VREG_AND_CHIP_RESET_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> VREG_AND_CHIP_RESET_W<'a> { #[doc = "Field `xip` reader - "] pub struct XIP_R(crate::FieldReader); impl XIP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { XIP_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> XIP_W<'a> { #[doc = "Field `sram5` reader - "] pub struct SRAM5_R(crate::FieldReader); impl SRAM5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM5_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> SRAM5_W<'a> { #[doc = "Field `sram4` reader - "] pub struct SRAM4_R(crate::FieldReader); impl SRAM4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM4_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> SRAM4_W<'a> { #[doc = "Field `sram3` reader - "] pub struct SRAM3_R(crate::FieldReader); impl SRAM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM3_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> SRAM3_W<'a> { #[doc = "Field `sram2` reader - "] pub struct SRAM2_R(crate::FieldReader); impl SRAM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM2_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> SRAM2_W<'a> { #[doc = "Field `sram1` reader - "] pub struct SRAM1_R(crate::FieldReader); impl SRAM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM1_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> SRAM1_W<'a> { #[doc = "Field `sram0` reader - "] pub struct SRAM0_R(crate::FieldReader); impl SRAM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM0_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> SRAM0_W<'a> { #[doc = "Field `rom` reader - "] pub struct ROM_R(crate::FieldReader); impl ROM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROM_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> ROM_W<'a> { #[doc = "Field `busfabric` reader - "] pub struct BUSFABRIC_R(crate::FieldReader); impl BUSFABRIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSFABRIC_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> BUSFABRIC_W<'a> { #[doc = "Field `resets` reader - "] pub struct RESETS_R(crate::FieldReader); impl RESETS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESETS_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> RESETS_W<'a> { #[doc = "Field `clocks` reader - "] pub struct CLOCKS_R(crate::FieldReader); impl CLOCKS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLOCKS_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> CLOCKS_W<'a> { #[doc = "Field `xosc` reader - "] pub struct XOSC_R(crate::FieldReader); impl XOSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { XOSC_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> XOSC_W<'a> { #[doc = "Field `rosc` reader - "] pub struct ROSC_R(crate::FieldReader); impl ROSC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROSC_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/ch/cc.rs b/src/pwm/ch/cc.rs index d0275f191..a2d4bb159 100644 --- a/src/pwm/ch/cc.rs +++ b/src/pwm/ch/cc.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `B` reader - "] pub struct B_R(crate::FieldReader); impl B_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { B_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> B_W<'a> { #[doc = "Field `A` reader - "] pub struct A_R(crate::FieldReader); impl A_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { A_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/ch/csr.rs b/src/pwm/ch/csr.rs index 4f7505604..e734504e3 100644 --- a/src/pwm/ch/csr.rs +++ b/src/pwm/ch/csr.rs @@ -39,6 +39,7 @@ impl From> for W { at less than full speed (div_int + div_frac / 16 > 1)"] pub struct PH_ADV_R(crate::FieldReader); impl PH_ADV_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PH_ADV_R(crate::FieldReader::new(bits)) } @@ -78,6 +79,7 @@ impl<'a> PH_ADV_W<'a> { Self-clearing. Write a 1, and poll until low. Counter must be running."] pub struct PH_RET_R(crate::FieldReader); impl PH_RET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PH_RET_R(crate::FieldReader::new(bits)) } @@ -136,6 +138,7 @@ impl From for u8 { #[doc = "Field `DIVMODE` reader - "] pub struct DIVMODE_R(crate::FieldReader); impl DIVMODE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DIVMODE_R(crate::FieldReader::new(bits)) } @@ -218,6 +221,7 @@ impl<'a> DIVMODE_W<'a> { #[doc = "Field `B_INV` reader - Invert output B"] pub struct B_INV_R(crate::FieldReader); impl B_INV_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { B_INV_R(crate::FieldReader::new(bits)) } @@ -254,6 +258,7 @@ impl<'a> B_INV_W<'a> { #[doc = "Field `A_INV` reader - Invert output A"] pub struct A_INV_R(crate::FieldReader); impl A_INV_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { A_INV_R(crate::FieldReader::new(bits)) } @@ -290,6 +295,7 @@ impl<'a> A_INV_W<'a> { #[doc = "Field `PH_CORRECT` reader - 1: Enable phase-correct modulation. 0: Trailing-edge"] pub struct PH_CORRECT_R(crate::FieldReader); impl PH_CORRECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PH_CORRECT_R(crate::FieldReader::new(bits)) } @@ -326,6 +332,7 @@ impl<'a> PH_CORRECT_W<'a> { #[doc = "Field `EN` reader - Enable the PWM channel."] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -360,12 +367,15 @@ impl<'a> EN_W<'a> { } } impl R { - #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"] + #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1)"] #[inline(always)] pub fn ph_adv(&self) -> PH_ADV_R { PH_ADV_R::new(((self.bits >> 7) & 0x01) != 0) } - #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."] + #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running."] #[inline(always)] pub fn ph_ret(&self) -> PH_RET_R { PH_RET_R::new(((self.bits >> 6) & 0x01) != 0) @@ -397,12 +407,15 @@ impl R { } } impl W { - #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"] + #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1)"] #[inline(always)] pub fn ph_adv(&mut self) -> PH_ADV_W { PH_ADV_W { w: self } } - #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."] + #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running."] #[inline(always)] pub fn ph_ret(&mut self) -> PH_RET_W { PH_RET_W { w: self } diff --git a/src/pwm/ch/ctr.rs b/src/pwm/ch/ctr.rs index dd170d191..1de6c91e9 100644 --- a/src/pwm/ch/ctr.rs +++ b/src/pwm/ch/ctr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CTR` reader - "] pub struct CTR_R(crate::FieldReader); impl CTR_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { CTR_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/ch/div.rs b/src/pwm/ch/div.rs index e92d75b53..1141f9179 100644 --- a/src/pwm/ch/div.rs +++ b/src/pwm/ch/div.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT` reader - "] pub struct INT_R(crate::FieldReader); impl INT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { INT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> INT_W<'a> { #[doc = "Field `FRAC` reader - "] pub struct FRAC_R(crate::FieldReader); impl FRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/ch/top.rs b/src/pwm/ch/top.rs index cd96377f3..0e7c17a60 100644 --- a/src/pwm/ch/top.rs +++ b/src/pwm/ch/top.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TOP` reader - "] pub struct TOP_R(crate::FieldReader); impl TOP_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { TOP_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/en.rs b/src/pwm/en.rs index 43cf41c2d..d0c263f28 100644 --- a/src/pwm/en.rs +++ b/src/pwm/en.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH7` reader - "] pub struct CH7_R(crate::FieldReader); impl CH7_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH7_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CH7_W<'a> { #[doc = "Field `CH6` reader - "] pub struct CH6_R(crate::FieldReader); impl CH6_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH6_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> CH6_W<'a> { #[doc = "Field `CH5` reader - "] pub struct CH5_R(crate::FieldReader); impl CH5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH5_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> CH5_W<'a> { #[doc = "Field `CH4` reader - "] pub struct CH4_R(crate::FieldReader); impl CH4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH4_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> CH4_W<'a> { #[doc = "Field `CH3` reader - "] pub struct CH3_R(crate::FieldReader); impl CH3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH3_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> CH3_W<'a> { #[doc = "Field `CH2` reader - "] pub struct CH2_R(crate::FieldReader); impl CH2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH2_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> CH2_W<'a> { #[doc = "Field `CH1` reader - "] pub struct CH1_R(crate::FieldReader); impl CH1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH1_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> CH1_W<'a> { #[doc = "Field `CH0` reader - "] pub struct CH0_R(crate::FieldReader); impl CH0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH0_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/inte.rs b/src/pwm/inte.rs index 2238f1e47..d9518bafd 100644 --- a/src/pwm/inte.rs +++ b/src/pwm/inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH7` reader - "] pub struct CH7_R(crate::FieldReader); impl CH7_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH7_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CH7_W<'a> { #[doc = "Field `CH6` reader - "] pub struct CH6_R(crate::FieldReader); impl CH6_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH6_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> CH6_W<'a> { #[doc = "Field `CH5` reader - "] pub struct CH5_R(crate::FieldReader); impl CH5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH5_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> CH5_W<'a> { #[doc = "Field `CH4` reader - "] pub struct CH4_R(crate::FieldReader); impl CH4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH4_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> CH4_W<'a> { #[doc = "Field `CH3` reader - "] pub struct CH3_R(crate::FieldReader); impl CH3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH3_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> CH3_W<'a> { #[doc = "Field `CH2` reader - "] pub struct CH2_R(crate::FieldReader); impl CH2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH2_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> CH2_W<'a> { #[doc = "Field `CH1` reader - "] pub struct CH1_R(crate::FieldReader); impl CH1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH1_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> CH1_W<'a> { #[doc = "Field `CH0` reader - "] pub struct CH0_R(crate::FieldReader); impl CH0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH0_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/intf.rs b/src/pwm/intf.rs index 268525744..a6da9a4a8 100644 --- a/src/pwm/intf.rs +++ b/src/pwm/intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH7` reader - "] pub struct CH7_R(crate::FieldReader); impl CH7_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH7_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CH7_W<'a> { #[doc = "Field `CH6` reader - "] pub struct CH6_R(crate::FieldReader); impl CH6_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH6_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> CH6_W<'a> { #[doc = "Field `CH5` reader - "] pub struct CH5_R(crate::FieldReader); impl CH5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH5_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> CH5_W<'a> { #[doc = "Field `CH4` reader - "] pub struct CH4_R(crate::FieldReader); impl CH4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH4_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> CH4_W<'a> { #[doc = "Field `CH3` reader - "] pub struct CH3_R(crate::FieldReader); impl CH3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH3_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> CH3_W<'a> { #[doc = "Field `CH2` reader - "] pub struct CH2_R(crate::FieldReader); impl CH2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH2_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> CH2_W<'a> { #[doc = "Field `CH1` reader - "] pub struct CH1_R(crate::FieldReader); impl CH1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH1_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> CH1_W<'a> { #[doc = "Field `CH0` reader - "] pub struct CH0_R(crate::FieldReader); impl CH0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH0_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/intr.rs b/src/pwm/intr.rs index 9566de020..479b37c9e 100644 --- a/src/pwm/intr.rs +++ b/src/pwm/intr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CH7` reader - "] pub struct CH7_R(crate::FieldReader); impl CH7_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH7_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CH7_W<'a> { #[doc = "Field `CH6` reader - "] pub struct CH6_R(crate::FieldReader); impl CH6_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH6_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> CH6_W<'a> { #[doc = "Field `CH5` reader - "] pub struct CH5_R(crate::FieldReader); impl CH5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH5_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> CH5_W<'a> { #[doc = "Field `CH4` reader - "] pub struct CH4_R(crate::FieldReader); impl CH4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH4_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> CH4_W<'a> { #[doc = "Field `CH3` reader - "] pub struct CH3_R(crate::FieldReader); impl CH3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH3_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> CH3_W<'a> { #[doc = "Field `CH2` reader - "] pub struct CH2_R(crate::FieldReader); impl CH2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH2_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> CH2_W<'a> { #[doc = "Field `CH1` reader - "] pub struct CH1_R(crate::FieldReader); impl CH1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH1_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> CH1_W<'a> { #[doc = "Field `CH0` reader - "] pub struct CH0_R(crate::FieldReader); impl CH0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH0_R(crate::FieldReader::new(bits)) } diff --git a/src/pwm/ints.rs b/src/pwm/ints.rs index d800a2ffe..fd74ad3ab 100644 --- a/src/pwm/ints.rs +++ b/src/pwm/ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `CH7` reader - "] pub struct CH7_R(crate::FieldReader); impl CH7_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH7_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for CH7_R { #[doc = "Field `CH6` reader - "] pub struct CH6_R(crate::FieldReader); impl CH6_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH6_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for CH6_R { #[doc = "Field `CH5` reader - "] pub struct CH5_R(crate::FieldReader); impl CH5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH5_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for CH5_R { #[doc = "Field `CH4` reader - "] pub struct CH4_R(crate::FieldReader); impl CH4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH4_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for CH4_R { #[doc = "Field `CH3` reader - "] pub struct CH3_R(crate::FieldReader); impl CH3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH3_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for CH3_R { #[doc = "Field `CH2` reader - "] pub struct CH2_R(crate::FieldReader); impl CH2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH2_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for CH2_R { #[doc = "Field `CH1` reader - "] pub struct CH1_R(crate::FieldReader); impl CH1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH1_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for CH1_R { #[doc = "Field `CH0` reader - "] pub struct CH0_R(crate::FieldReader); impl CH0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CH0_R(crate::FieldReader::new(bits)) } diff --git a/src/resets/reset.rs b/src/resets/reset.rs index 5d39fffb7..54773b28a 100644 --- a/src/resets/reset.rs +++ b/src/resets/reset.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `usbctrl` reader - "] pub struct USBCTRL_R(crate::FieldReader); impl USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { USBCTRL_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> USBCTRL_W<'a> { #[doc = "Field `uart1` reader - "] pub struct UART1_R(crate::FieldReader); impl UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UART1_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> UART1_W<'a> { #[doc = "Field `uart0` reader - "] pub struct UART0_R(crate::FieldReader); impl UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UART0_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> UART0_W<'a> { #[doc = "Field `timer` reader - "] pub struct TIMER_R(crate::FieldReader); impl TIMER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TIMER_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> TIMER_W<'a> { #[doc = "Field `tbman` reader - "] pub struct TBMAN_R(crate::FieldReader); impl TBMAN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TBMAN_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> TBMAN_W<'a> { #[doc = "Field `sysinfo` reader - "] pub struct SYSINFO_R(crate::FieldReader); impl SYSINFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SYSINFO_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> SYSINFO_W<'a> { #[doc = "Field `syscfg` reader - "] pub struct SYSCFG_R(crate::FieldReader); impl SYSCFG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SYSCFG_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> SYSCFG_W<'a> { #[doc = "Field `spi1` reader - "] pub struct SPI1_R(crate::FieldReader); impl SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPI1_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> SPI1_W<'a> { #[doc = "Field `spi0` reader - "] pub struct SPI0_R(crate::FieldReader); impl SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPI0_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> SPI0_W<'a> { #[doc = "Field `rtc` reader - "] pub struct RTC_R(crate::FieldReader); impl RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> RTC_W<'a> { #[doc = "Field `pwm` reader - "] pub struct PWM_R(crate::FieldReader); impl PWM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PWM_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> PWM_W<'a> { #[doc = "Field `pll_usb` reader - "] pub struct PLL_USB_R(crate::FieldReader); impl PLL_USB_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PLL_USB_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> PLL_USB_W<'a> { #[doc = "Field `pll_sys` reader - "] pub struct PLL_SYS_R(crate::FieldReader); impl PLL_SYS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PLL_SYS_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> PLL_SYS_W<'a> { #[doc = "Field `pio1` reader - "] pub struct PIO1_R(crate::FieldReader); impl PIO1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PIO1_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> PIO1_W<'a> { #[doc = "Field `pio0` reader - "] pub struct PIO0_R(crate::FieldReader); impl PIO0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PIO0_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> PIO0_W<'a> { #[doc = "Field `pads_qspi` reader - "] pub struct PADS_QSPI_R(crate::FieldReader); impl PADS_QSPI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PADS_QSPI_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> PADS_QSPI_W<'a> { #[doc = "Field `pads_bank0` reader - "] pub struct PADS_BANK0_R(crate::FieldReader); impl PADS_BANK0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PADS_BANK0_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> PADS_BANK0_W<'a> { #[doc = "Field `jtag` reader - "] pub struct JTAG_R(crate::FieldReader); impl JTAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { JTAG_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> JTAG_W<'a> { #[doc = "Field `io_qspi` reader - "] pub struct IO_QSPI_R(crate::FieldReader); impl IO_QSPI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IO_QSPI_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> IO_QSPI_W<'a> { #[doc = "Field `io_bank0` reader - "] pub struct IO_BANK0_R(crate::FieldReader); impl IO_BANK0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IO_BANK0_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> IO_BANK0_W<'a> { #[doc = "Field `i2c1` reader - "] pub struct I2C1_R(crate::FieldReader); impl I2C1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { I2C1_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> I2C1_W<'a> { #[doc = "Field `i2c0` reader - "] pub struct I2C0_R(crate::FieldReader); impl I2C0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { I2C0_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> I2C0_W<'a> { #[doc = "Field `dma` reader - "] pub struct DMA_R(crate::FieldReader); impl DMA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DMA_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> DMA_W<'a> { #[doc = "Field `busctrl` reader - "] pub struct BUSCTRL_R(crate::FieldReader); impl BUSCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSCTRL_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> BUSCTRL_W<'a> { #[doc = "Field `adc` reader - "] pub struct ADC_R(crate::FieldReader); impl ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ADC_R(crate::FieldReader::new(bits)) } diff --git a/src/resets/reset_done.rs b/src/resets/reset_done.rs index d14b1d547..61d963c83 100644 --- a/src/resets/reset_done.rs +++ b/src/resets/reset_done.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `usbctrl` reader - "] pub struct USBCTRL_R(crate::FieldReader); impl USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { USBCTRL_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for USBCTRL_R { #[doc = "Field `uart1` reader - "] pub struct UART1_R(crate::FieldReader); impl UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UART1_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for UART1_R { #[doc = "Field `uart0` reader - "] pub struct UART0_R(crate::FieldReader); impl UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UART0_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for UART0_R { #[doc = "Field `timer` reader - "] pub struct TIMER_R(crate::FieldReader); impl TIMER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TIMER_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for TIMER_R { #[doc = "Field `tbman` reader - "] pub struct TBMAN_R(crate::FieldReader); impl TBMAN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TBMAN_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for TBMAN_R { #[doc = "Field `sysinfo` reader - "] pub struct SYSINFO_R(crate::FieldReader); impl SYSINFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SYSINFO_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for SYSINFO_R { #[doc = "Field `syscfg` reader - "] pub struct SYSCFG_R(crate::FieldReader); impl SYSCFG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SYSCFG_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for SYSCFG_R { #[doc = "Field `spi1` reader - "] pub struct SPI1_R(crate::FieldReader); impl SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPI1_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for SPI1_R { #[doc = "Field `spi0` reader - "] pub struct SPI0_R(crate::FieldReader); impl SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPI0_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for SPI0_R { #[doc = "Field `rtc` reader - "] pub struct RTC_R(crate::FieldReader); impl RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for RTC_R { #[doc = "Field `pwm` reader - "] pub struct PWM_R(crate::FieldReader); impl PWM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PWM_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for PWM_R { #[doc = "Field `pll_usb` reader - "] pub struct PLL_USB_R(crate::FieldReader); impl PLL_USB_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PLL_USB_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for PLL_USB_R { #[doc = "Field `pll_sys` reader - "] pub struct PLL_SYS_R(crate::FieldReader); impl PLL_SYS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PLL_SYS_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for PLL_SYS_R { #[doc = "Field `pio1` reader - "] pub struct PIO1_R(crate::FieldReader); impl PIO1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PIO1_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for PIO1_R { #[doc = "Field `pio0` reader - "] pub struct PIO0_R(crate::FieldReader); impl PIO0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PIO0_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for PIO0_R { #[doc = "Field `pads_qspi` reader - "] pub struct PADS_QSPI_R(crate::FieldReader); impl PADS_QSPI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PADS_QSPI_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for PADS_QSPI_R { #[doc = "Field `pads_bank0` reader - "] pub struct PADS_BANK0_R(crate::FieldReader); impl PADS_BANK0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PADS_BANK0_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for PADS_BANK0_R { #[doc = "Field `jtag` reader - "] pub struct JTAG_R(crate::FieldReader); impl JTAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { JTAG_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for JTAG_R { #[doc = "Field `io_qspi` reader - "] pub struct IO_QSPI_R(crate::FieldReader); impl IO_QSPI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IO_QSPI_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for IO_QSPI_R { #[doc = "Field `io_bank0` reader - "] pub struct IO_BANK0_R(crate::FieldReader); impl IO_BANK0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IO_BANK0_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for IO_BANK0_R { #[doc = "Field `i2c1` reader - "] pub struct I2C1_R(crate::FieldReader); impl I2C1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { I2C1_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for I2C1_R { #[doc = "Field `i2c0` reader - "] pub struct I2C0_R(crate::FieldReader); impl I2C0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { I2C0_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for I2C0_R { #[doc = "Field `dma` reader - "] pub struct DMA_R(crate::FieldReader); impl DMA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DMA_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for DMA_R { #[doc = "Field `busctrl` reader - "] pub struct BUSCTRL_R(crate::FieldReader); impl BUSCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSCTRL_R(crate::FieldReader::new(bits)) } @@ -352,6 +376,7 @@ impl core::ops::Deref for BUSCTRL_R { #[doc = "Field `adc` reader - "] pub struct ADC_R(crate::FieldReader); impl ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ADC_R(crate::FieldReader::new(bits)) } diff --git a/src/resets/wdsel.rs b/src/resets/wdsel.rs index ecbbb1450..a838b908e 100644 --- a/src/resets/wdsel.rs +++ b/src/resets/wdsel.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `usbctrl` reader - "] pub struct USBCTRL_R(crate::FieldReader); impl USBCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { USBCTRL_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> USBCTRL_W<'a> { #[doc = "Field `uart1` reader - "] pub struct UART1_R(crate::FieldReader); impl UART1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UART1_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> UART1_W<'a> { #[doc = "Field `uart0` reader - "] pub struct UART0_R(crate::FieldReader); impl UART0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UART0_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> UART0_W<'a> { #[doc = "Field `timer` reader - "] pub struct TIMER_R(crate::FieldReader); impl TIMER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TIMER_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> TIMER_W<'a> { #[doc = "Field `tbman` reader - "] pub struct TBMAN_R(crate::FieldReader); impl TBMAN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TBMAN_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> TBMAN_W<'a> { #[doc = "Field `sysinfo` reader - "] pub struct SYSINFO_R(crate::FieldReader); impl SYSINFO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SYSINFO_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> SYSINFO_W<'a> { #[doc = "Field `syscfg` reader - "] pub struct SYSCFG_R(crate::FieldReader); impl SYSCFG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SYSCFG_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> SYSCFG_W<'a> { #[doc = "Field `spi1` reader - "] pub struct SPI1_R(crate::FieldReader); impl SPI1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPI1_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> SPI1_W<'a> { #[doc = "Field `spi0` reader - "] pub struct SPI0_R(crate::FieldReader); impl SPI0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPI0_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> SPI0_W<'a> { #[doc = "Field `rtc` reader - "] pub struct RTC_R(crate::FieldReader); impl RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> RTC_W<'a> { #[doc = "Field `pwm` reader - "] pub struct PWM_R(crate::FieldReader); impl PWM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PWM_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> PWM_W<'a> { #[doc = "Field `pll_usb` reader - "] pub struct PLL_USB_R(crate::FieldReader); impl PLL_USB_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PLL_USB_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> PLL_USB_W<'a> { #[doc = "Field `pll_sys` reader - "] pub struct PLL_SYS_R(crate::FieldReader); impl PLL_SYS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PLL_SYS_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> PLL_SYS_W<'a> { #[doc = "Field `pio1` reader - "] pub struct PIO1_R(crate::FieldReader); impl PIO1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PIO1_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> PIO1_W<'a> { #[doc = "Field `pio0` reader - "] pub struct PIO0_R(crate::FieldReader); impl PIO0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PIO0_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> PIO0_W<'a> { #[doc = "Field `pads_qspi` reader - "] pub struct PADS_QSPI_R(crate::FieldReader); impl PADS_QSPI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PADS_QSPI_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> PADS_QSPI_W<'a> { #[doc = "Field `pads_bank0` reader - "] pub struct PADS_BANK0_R(crate::FieldReader); impl PADS_BANK0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PADS_BANK0_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> PADS_BANK0_W<'a> { #[doc = "Field `jtag` reader - "] pub struct JTAG_R(crate::FieldReader); impl JTAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { JTAG_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> JTAG_W<'a> { #[doc = "Field `io_qspi` reader - "] pub struct IO_QSPI_R(crate::FieldReader); impl IO_QSPI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IO_QSPI_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> IO_QSPI_W<'a> { #[doc = "Field `io_bank0` reader - "] pub struct IO_BANK0_R(crate::FieldReader); impl IO_BANK0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { IO_BANK0_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> IO_BANK0_W<'a> { #[doc = "Field `i2c1` reader - "] pub struct I2C1_R(crate::FieldReader); impl I2C1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { I2C1_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> I2C1_W<'a> { #[doc = "Field `i2c0` reader - "] pub struct I2C0_R(crate::FieldReader); impl I2C0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { I2C0_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> I2C0_W<'a> { #[doc = "Field `dma` reader - "] pub struct DMA_R(crate::FieldReader); impl DMA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DMA_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> DMA_W<'a> { #[doc = "Field `busctrl` reader - "] pub struct BUSCTRL_R(crate::FieldReader); impl BUSCTRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSCTRL_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> BUSCTRL_W<'a> { #[doc = "Field `adc` reader - "] pub struct ADC_R(crate::FieldReader); impl ADC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ADC_R(crate::FieldReader::new(bits)) } diff --git a/src/rosc/ctrl.rs b/src/rosc/ctrl.rs index f59e73eca..57420a530 100644 --- a/src/rosc/ctrl.rs +++ b/src/rosc/ctrl.rs @@ -58,6 +58,7 @@ impl From for u16 { The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -155,6 +156,7 @@ impl From for u16 { Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] pub struct FREQ_RANGE_R(crate::FieldReader); impl FREQ_RANGE_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { FREQ_RANGE_R(crate::FieldReader::new(bits)) } @@ -242,24 +244,42 @@ impl<'a> FREQ_RANGE_W<'a> { } } impl R { - #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 12) & 0x0fff) as u16) } - #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 HIGH uses stages 0 to 3 TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] + #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 0 to 5 + HIGH uses stages 0 to 3 + TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] #[inline(always)] pub fn freq_range(&self) -> FREQ_RANGE_R { FREQ_RANGE_R::new((self.bits & 0x0fff) as u16) } } impl W { - #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } } - #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 HIGH uses stages 0 to 3 TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] + #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 0 to 5 + HIGH uses stages 0 to 3 + TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] #[inline(always)] pub fn freq_range(&mut self) -> FREQ_RANGE_W { FREQ_RANGE_W { w: self } diff --git a/src/rosc/div.rs b/src/rosc/div.rs index ae80a1a8b..195e20bb4 100644 --- a/src/rosc/div.rs +++ b/src/rosc/div.rs @@ -60,6 +60,7 @@ impl From for u16 { this register resets to div=16"] pub struct DIV_R(crate::FieldReader); impl DIV_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { DIV_R(crate::FieldReader::new(bits)) } @@ -111,14 +112,22 @@ impl<'a> DIV_W<'a> { } } impl R { - #[doc = "Bits 0:11 - set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16"] + #[doc = "Bits 0:11 - set to 0xaa0 + div where + div = 0 divides by 32 + div = 1-31 divides by div + any other value sets div=31 + this register resets to div=16"] #[inline(always)] pub fn div(&self) -> DIV_R { DIV_R::new((self.bits & 0x0fff) as u16) } } impl W { - #[doc = "Bits 0:11 - set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16"] + #[doc = "Bits 0:11 - set to 0xaa0 + div where + div = 0 divides by 32 + div = 1-31 divides by div + any other value sets div=31 + this register resets to div=16"] #[inline(always)] pub fn div(&mut self) -> DIV_W { DIV_W { w: self } diff --git a/src/rosc/freqa.rs b/src/rosc/freqa.rs index 6b75b95fe..c62789c9a 100644 --- a/src/rosc/freqa.rs +++ b/src/rosc/freqa.rs @@ -54,6 +54,7 @@ impl From for u16 { Any other value in this field will set all drive strengths to 0"] pub struct PASSWD_R(crate::FieldReader); impl PASSWD_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { PASSWD_R(crate::FieldReader::new(bits)) } @@ -104,6 +105,7 @@ impl<'a> PASSWD_W<'a> { #[doc = "Field `DS3` reader - Stage 3 drive strength"] pub struct DS3_R(crate::FieldReader); impl DS3_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DS3_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl<'a> DS3_W<'a> { #[doc = "Field `DS2` reader - Stage 2 drive strength"] pub struct DS2_R(crate::FieldReader); impl DS2_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DS2_R(crate::FieldReader::new(bits)) } @@ -156,6 +159,7 @@ impl<'a> DS2_W<'a> { #[doc = "Field `DS1` reader - Stage 1 drive strength"] pub struct DS1_R(crate::FieldReader); impl DS1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DS1_R(crate::FieldReader::new(bits)) } @@ -182,6 +186,7 @@ impl<'a> DS1_W<'a> { #[doc = "Field `DS0` reader - Stage 0 drive strength"] pub struct DS0_R(crate::FieldReader); impl DS0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DS0_R(crate::FieldReader::new(bits)) } @@ -206,7 +211,8 @@ impl<'a> DS0_W<'a> { } } impl R { - #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0"] #[inline(always)] pub fn passwd(&self) -> PASSWD_R { PASSWD_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -233,7 +239,8 @@ impl R { } } impl W { - #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0"] #[inline(always)] pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W { w: self } diff --git a/src/rosc/freqb.rs b/src/rosc/freqb.rs index 85fb29f15..70d052ded 100644 --- a/src/rosc/freqb.rs +++ b/src/rosc/freqb.rs @@ -54,6 +54,7 @@ impl From for u16 { Any other value in this field will set all drive strengths to 0"] pub struct PASSWD_R(crate::FieldReader); impl PASSWD_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { PASSWD_R(crate::FieldReader::new(bits)) } @@ -104,6 +105,7 @@ impl<'a> PASSWD_W<'a> { #[doc = "Field `DS7` reader - Stage 7 drive strength"] pub struct DS7_R(crate::FieldReader); impl DS7_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DS7_R(crate::FieldReader::new(bits)) } @@ -130,6 +132,7 @@ impl<'a> DS7_W<'a> { #[doc = "Field `DS6` reader - Stage 6 drive strength"] pub struct DS6_R(crate::FieldReader); impl DS6_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DS6_R(crate::FieldReader::new(bits)) } @@ -156,6 +159,7 @@ impl<'a> DS6_W<'a> { #[doc = "Field `DS5` reader - Stage 5 drive strength"] pub struct DS5_R(crate::FieldReader); impl DS5_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DS5_R(crate::FieldReader::new(bits)) } @@ -182,6 +186,7 @@ impl<'a> DS5_W<'a> { #[doc = "Field `DS4` reader - Stage 4 drive strength"] pub struct DS4_R(crate::FieldReader); impl DS4_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DS4_R(crate::FieldReader::new(bits)) } @@ -206,7 +211,8 @@ impl<'a> DS4_W<'a> { } } impl R { - #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0"] #[inline(always)] pub fn passwd(&self) -> PASSWD_R { PASSWD_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -233,7 +239,8 @@ impl R { } } impl W { - #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0"] #[inline(always)] pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W { w: self } diff --git a/src/rosc/phase.rs b/src/rosc/phase.rs index 2b431b54b..7ede3108a 100644 --- a/src/rosc/phase.rs +++ b/src/rosc/phase.rs @@ -38,6 +38,7 @@ impl From> for W { any other value enables the output with shift=0"] pub struct PASSWD_R(crate::FieldReader); impl PASSWD_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PASSWD_R(crate::FieldReader::new(bits)) } @@ -66,6 +67,7 @@ impl<'a> PASSWD_W<'a> { this can be changed on-the-fly"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -104,6 +106,7 @@ impl<'a> ENABLE_W<'a> { this is ignored when div=1"] pub struct FLIP_R(crate::FieldReader); impl FLIP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FLIP_R(crate::FieldReader::new(bits)) } @@ -143,6 +146,7 @@ impl<'a> FLIP_W<'a> { must be set to 0 before setting div=1"] pub struct SHIFT_R(crate::FieldReader); impl SHIFT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SHIFT_R(crate::FieldReader::new(bits)) } @@ -169,44 +173,54 @@ impl<'a> SHIFT_W<'a> { } } impl R { - #[doc = "Bits 4:11 - set to 0xaa any other value enables the output with shift=0"] + #[doc = "Bits 4:11 - set to 0xaa + any other value enables the output with shift=0"] #[inline(always)] pub fn passwd(&self) -> PASSWD_R { PASSWD_R::new(((self.bits >> 4) & 0xff) as u8) } - #[doc = "Bit 3 - enable the phase-shifted output this can be changed on-the-fly"] + #[doc = "Bit 3 - enable the phase-shifted output + this can be changed on-the-fly"] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 3) & 0x01) != 0) } - #[doc = "Bit 2 - invert the phase-shifted output this is ignored when div=1"] + #[doc = "Bit 2 - invert the phase-shifted output + this is ignored when div=1"] #[inline(always)] pub fn flip(&self) -> FLIP_R { FLIP_R::new(((self.bits >> 2) & 0x01) != 0) } - #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] + #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1"] #[inline(always)] pub fn shift(&self) -> SHIFT_R { SHIFT_R::new((self.bits & 0x03) as u8) } } impl W { - #[doc = "Bits 4:11 - set to 0xaa any other value enables the output with shift=0"] + #[doc = "Bits 4:11 - set to 0xaa + any other value enables the output with shift=0"] #[inline(always)] pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W { w: self } } - #[doc = "Bit 3 - enable the phase-shifted output this can be changed on-the-fly"] + #[doc = "Bit 3 - enable the phase-shifted output + this can be changed on-the-fly"] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } } - #[doc = "Bit 2 - invert the phase-shifted output this is ignored when div=1"] + #[doc = "Bit 2 - invert the phase-shifted output + this is ignored when div=1"] #[inline(always)] pub fn flip(&mut self) -> FLIP_W { FLIP_W { w: self } } - #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] + #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1"] #[inline(always)] pub fn shift(&mut self) -> SHIFT_W { SHIFT_W { w: self } diff --git a/src/rosc/randombit.rs b/src/rosc/randombit.rs index 78084d4ac..dba974143 100644 --- a/src/rosc/randombit.rs +++ b/src/rosc/randombit.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RANDOMBIT` reader - "] pub struct RANDOMBIT_R(crate::FieldReader); impl RANDOMBIT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RANDOMBIT_R(crate::FieldReader::new(bits)) } diff --git a/src/rosc/status.rs b/src/rosc/status.rs index d5866745f..1f406482c 100644 --- a/src/rosc/status.rs +++ b/src/rosc/status.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `STABLE` reader - Oscillator is running and stable"] pub struct STABLE_R(crate::FieldReader); impl STABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STABLE_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for STABLE_R { #[doc = "Field `DIV_RUNNING` reader - post-divider is running this resets to 0 but transitions to 1 during chip startup"] pub struct DIV_RUNNING_R(crate::FieldReader); impl DIV_RUNNING_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DIV_RUNNING_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for DIV_RUNNING_R { #[doc = "Field `ENABLED` reader - Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup"] pub struct ENABLED_R(crate::FieldReader); impl ENABLED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLED_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/clkdiv_m1.rs b/src/rtc/clkdiv_m1.rs index 1240a2c8d..9eb12d7de 100644 --- a/src/rtc/clkdiv_m1.rs +++ b/src/rtc/clkdiv_m1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CLKDIV_M1` reader - "] pub struct CLKDIV_M1_R(crate::FieldReader); impl CLKDIV_M1_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { CLKDIV_M1_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/ctrl.rs b/src/rtc/ctrl.rs index e67ba8f01..f8c64086c 100644 --- a/src/rtc/ctrl.rs +++ b/src/rtc/ctrl.rs @@ -38,6 +38,7 @@ impl From> for W { Useful for years divisible by 100 but not by 400"] pub struct FORCE_NOTLEAPYEAR_R(crate::FieldReader); impl FORCE_NOTLEAPYEAR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FORCE_NOTLEAPYEAR_R(crate::FieldReader::new(bits)) } @@ -75,6 +76,7 @@ impl<'a> FORCE_NOTLEAPYEAR_W<'a> { #[doc = "Field `LOAD` reader - Load RTC"] pub struct LOAD_R(crate::FieldReader); impl LOAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { LOAD_R(crate::FieldReader::new(bits)) } @@ -111,6 +113,7 @@ impl<'a> LOAD_W<'a> { #[doc = "Field `RTC_ACTIVE` reader - RTC enabled (running)"] pub struct RTC_ACTIVE_R(crate::FieldReader); impl RTC_ACTIVE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_ACTIVE_R(crate::FieldReader::new(bits)) } @@ -125,6 +128,7 @@ impl core::ops::Deref for RTC_ACTIVE_R { #[doc = "Field `RTC_ENABLE` reader - Enable RTC"] pub struct RTC_ENABLE_R(crate::FieldReader); impl RTC_ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_ENABLE_R(crate::FieldReader::new(bits)) } @@ -159,7 +163,8 @@ impl<'a> RTC_ENABLE_W<'a> { } } impl R { - #[doc = "Bit 8 - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] + #[doc = "Bit 8 - If set, leapyear is forced off. + Useful for years divisible by 100 but not by 400"] #[inline(always)] pub fn force_notleapyear(&self) -> FORCE_NOTLEAPYEAR_R { FORCE_NOTLEAPYEAR_R::new(((self.bits >> 8) & 0x01) != 0) @@ -181,7 +186,8 @@ impl R { } } impl W { - #[doc = "Bit 8 - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] + #[doc = "Bit 8 - If set, leapyear is forced off. + Useful for years divisible by 100 but not by 400"] #[inline(always)] pub fn force_notleapyear(&mut self) -> FORCE_NOTLEAPYEAR_W { FORCE_NOTLEAPYEAR_W { w: self } diff --git a/src/rtc/inte.rs b/src/rtc/inte.rs index f37ef57e2..829c1979c 100644 --- a/src/rtc/inte.rs +++ b/src/rtc/inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `RTC` reader - "] pub struct RTC_R(crate::FieldReader); impl RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/intf.rs b/src/rtc/intf.rs index fe58d8291..fd64678f6 100644 --- a/src/rtc/intf.rs +++ b/src/rtc/intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `RTC` reader - "] pub struct RTC_R(crate::FieldReader); impl RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/intr.rs b/src/rtc/intr.rs index 2b3b0d377..c96a3127f 100644 --- a/src/rtc/intr.rs +++ b/src/rtc/intr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RTC` reader - "] pub struct RTC_R(crate::FieldReader); impl RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/ints.rs b/src/rtc/ints.rs index 4a32dece8..6848dd78f 100644 --- a/src/rtc/ints.rs +++ b/src/rtc/ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RTC` reader - "] pub struct RTC_R(crate::FieldReader); impl RTC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTC_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/irq_setup_0.rs b/src/rtc/irq_setup_0.rs index cfe3dad15..598c36f54 100644 --- a/src/rtc/irq_setup_0.rs +++ b/src/rtc/irq_setup_0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `MATCH_ACTIVE` reader - "] pub struct MATCH_ACTIVE_R(crate::FieldReader); impl MATCH_ACTIVE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MATCH_ACTIVE_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for MATCH_ACTIVE_R { #[doc = "Field `MATCH_ENA` reader - Global match enable. Don't change any other value while this one is enabled"] pub struct MATCH_ENA_R(crate::FieldReader); impl MATCH_ENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MATCH_ENA_R(crate::FieldReader::new(bits)) } @@ -87,6 +89,7 @@ impl<'a> MATCH_ENA_W<'a> { #[doc = "Field `YEAR_ENA` reader - Enable year matching"] pub struct YEAR_ENA_R(crate::FieldReader); impl YEAR_ENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { YEAR_ENA_R(crate::FieldReader::new(bits)) } @@ -123,6 +126,7 @@ impl<'a> YEAR_ENA_W<'a> { #[doc = "Field `MONTH_ENA` reader - Enable month matching"] pub struct MONTH_ENA_R(crate::FieldReader); impl MONTH_ENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MONTH_ENA_R(crate::FieldReader::new(bits)) } @@ -159,6 +163,7 @@ impl<'a> MONTH_ENA_W<'a> { #[doc = "Field `DAY_ENA` reader - Enable day matching"] pub struct DAY_ENA_R(crate::FieldReader); impl DAY_ENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DAY_ENA_R(crate::FieldReader::new(bits)) } @@ -195,6 +200,7 @@ impl<'a> DAY_ENA_W<'a> { #[doc = "Field `YEAR` reader - Year"] pub struct YEAR_R(crate::FieldReader); impl YEAR_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { YEAR_R(crate::FieldReader::new(bits)) } @@ -221,6 +227,7 @@ impl<'a> YEAR_W<'a> { #[doc = "Field `MONTH` reader - Month (1..12)"] pub struct MONTH_R(crate::FieldReader); impl MONTH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MONTH_R(crate::FieldReader::new(bits)) } @@ -247,6 +254,7 @@ impl<'a> MONTH_W<'a> { #[doc = "Field `DAY` reader - Day of the month (1..31)"] pub struct DAY_R(crate::FieldReader); impl DAY_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DAY_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/irq_setup_1.rs b/src/rtc/irq_setup_1.rs index 935d474de..4c60cae92 100644 --- a/src/rtc/irq_setup_1.rs +++ b/src/rtc/irq_setup_1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DOTW_ENA` reader - Enable day of the week matching"] pub struct DOTW_ENA_R(crate::FieldReader); impl DOTW_ENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DOTW_ENA_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> DOTW_ENA_W<'a> { #[doc = "Field `HOUR_ENA` reader - Enable hour matching"] pub struct HOUR_ENA_R(crate::FieldReader); impl HOUR_ENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOUR_ENA_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> HOUR_ENA_W<'a> { #[doc = "Field `MIN_ENA` reader - Enable minute matching"] pub struct MIN_ENA_R(crate::FieldReader); impl MIN_ENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MIN_ENA_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> MIN_ENA_W<'a> { #[doc = "Field `SEC_ENA` reader - Enable second matching"] pub struct SEC_ENA_R(crate::FieldReader); impl SEC_ENA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SEC_ENA_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> SEC_ENA_W<'a> { #[doc = "Field `DOTW` reader - Day of the week"] pub struct DOTW_R(crate::FieldReader); impl DOTW_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DOTW_R(crate::FieldReader::new(bits)) } @@ -207,6 +212,7 @@ impl<'a> DOTW_W<'a> { #[doc = "Field `HOUR` reader - Hours"] pub struct HOUR_R(crate::FieldReader); impl HOUR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { HOUR_R(crate::FieldReader::new(bits)) } @@ -233,6 +239,7 @@ impl<'a> HOUR_W<'a> { #[doc = "Field `MIN` reader - Minutes"] pub struct MIN_R(crate::FieldReader); impl MIN_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MIN_R(crate::FieldReader::new(bits)) } @@ -259,6 +266,7 @@ impl<'a> MIN_W<'a> { #[doc = "Field `SEC` reader - Seconds"] pub struct SEC_R(crate::FieldReader); impl SEC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SEC_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/rtc_0.rs b/src/rtc/rtc_0.rs index 63a42f688..094cc261b 100644 --- a/src/rtc/rtc_0.rs +++ b/src/rtc/rtc_0.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `DOTW` reader - Day of the week"] pub struct DOTW_R(crate::FieldReader); impl DOTW_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DOTW_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for DOTW_R { #[doc = "Field `HOUR` reader - Hours"] pub struct HOUR_R(crate::FieldReader); impl HOUR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { HOUR_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for HOUR_R { #[doc = "Field `MIN` reader - Minutes"] pub struct MIN_R(crate::FieldReader); impl MIN_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MIN_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for MIN_R { #[doc = "Field `SEC` reader - Seconds"] pub struct SEC_R(crate::FieldReader); impl SEC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SEC_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/rtc_1.rs b/src/rtc/rtc_1.rs index b3055e2b2..e87c4cc72 100644 --- a/src/rtc/rtc_1.rs +++ b/src/rtc/rtc_1.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `YEAR` reader - Year"] pub struct YEAR_R(crate::FieldReader); impl YEAR_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { YEAR_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for YEAR_R { #[doc = "Field `MONTH` reader - Month (1..12)"] pub struct MONTH_R(crate::FieldReader); impl MONTH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MONTH_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for MONTH_R { #[doc = "Field `DAY` reader - Day of the month (1..31)"] pub struct DAY_R(crate::FieldReader); impl DAY_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DAY_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/setup_0.rs b/src/rtc/setup_0.rs index f773ea5d0..7a60a3e85 100644 --- a/src/rtc/setup_0.rs +++ b/src/rtc/setup_0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `YEAR` reader - Year"] pub struct YEAR_R(crate::FieldReader); impl YEAR_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { YEAR_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> YEAR_W<'a> { #[doc = "Field `MONTH` reader - Month (1..12)"] pub struct MONTH_R(crate::FieldReader); impl MONTH_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MONTH_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> MONTH_W<'a> { #[doc = "Field `DAY` reader - Day of the month (1..31)"] pub struct DAY_R(crate::FieldReader); impl DAY_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DAY_R(crate::FieldReader::new(bits)) } diff --git a/src/rtc/setup_1.rs b/src/rtc/setup_1.rs index 4f815d045..7f7c96f5c 100644 --- a/src/rtc/setup_1.rs +++ b/src/rtc/setup_1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DOTW` reader - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7"] pub struct DOTW_R(crate::FieldReader); impl DOTW_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DOTW_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> DOTW_W<'a> { #[doc = "Field `HOUR` reader - Hours"] pub struct HOUR_R(crate::FieldReader); impl HOUR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { HOUR_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> HOUR_W<'a> { #[doc = "Field `MIN` reader - Minutes"] pub struct MIN_R(crate::FieldReader); impl MIN_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MIN_R(crate::FieldReader::new(bits)) } @@ -115,6 +118,7 @@ impl<'a> MIN_W<'a> { #[doc = "Field `SEC` reader - Seconds"] pub struct SEC_R(crate::FieldReader); impl SEC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SEC_R(crate::FieldReader::new(bits)) } diff --git a/src/sio/div_csr.rs b/src/sio/div_csr.rs index 0ad8f01a1..6ea61e9e7 100644 --- a/src/sio/div_csr.rs +++ b/src/sio/div_csr.rs @@ -19,6 +19,7 @@ impl From> for R { or REMAINDER and then QUOTIENT, to prevent data loss on context switch."] pub struct DIRTY_R(crate::FieldReader); impl DIRTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DIRTY_R(crate::FieldReader::new(bits)) } @@ -37,6 +38,7 @@ impl core::ops::Deref for DIRTY_R { and set the READY and DIRTY flags."] pub struct READY_R(crate::FieldReader); impl READY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { READY_R(crate::FieldReader::new(bits)) } @@ -49,12 +51,19 @@ impl core::ops::Deref for READY_R { } } impl R { - #[doc = "Bit 1 - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. Software can use this flag to make save/restore more efficient (skip if not DIRTY). If the flag is used in this way, it's recommended to either read QUOTIENT only, or REMAINDER and then QUOTIENT, to prevent data loss on context switch."] + #[doc = "Bit 1 - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. + Software can use this flag to make save/restore more efficient (skip if not DIRTY). + If the flag is used in this way, it's recommended to either read QUOTIENT only, + or REMAINDER and then QUOTIENT, to prevent data loss on context switch."] #[inline(always)] pub fn dirty(&self) -> DIRTY_R { DIRTY_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - Reads as 0 when a calculation is in progress, 1 otherwise. Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no matter if one is already in progress. Writing to a result register will immediately terminate any in-progress calculation and set the READY and DIRTY flags."] + #[doc = "Bit 0 - Reads as 0 when a calculation is in progress, 1 otherwise. + Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no + matter if one is already in progress. + Writing to a result register will immediately terminate any in-progress calculation + and set the READY and DIRTY flags."] #[inline(always)] pub fn ready(&self) -> READY_R { READY_R::new((self.bits & 0x01) != 0) diff --git a/src/sio/fifo_st.rs b/src/sio/fifo_st.rs index dd49c2d55..b91af1930 100644 --- a/src/sio/fifo_st.rs +++ b/src/sio/fifo_st.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ROE` reader - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."] pub struct ROE_R(crate::FieldReader); impl ROE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> ROE_W<'a> { #[doc = "Field `WOF` reader - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."] pub struct WOF_R(crate::FieldReader); impl WOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { WOF_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> WOF_W<'a> { #[doc = "Field `RDY` reader - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)"] pub struct RDY_R(crate::FieldReader); impl RDY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RDY_R(crate::FieldReader::new(bits)) } @@ -123,6 +126,7 @@ impl core::ops::Deref for RDY_R { #[doc = "Field `VLD` reader - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)"] pub struct VLD_R(crate::FieldReader); impl VLD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VLD_R(crate::FieldReader::new(bits)) } diff --git a/src/sio/gpio_hi_in.rs b/src/sio/gpio_hi_in.rs index fa1864ed1..18be82ff6 100644 --- a/src/sio/gpio_hi_in.rs +++ b/src/sio/gpio_hi_in.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `GPIO_HI_IN` reader - Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3"] pub struct GPIO_HI_IN_R(crate::FieldReader); impl GPIO_HI_IN_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { GPIO_HI_IN_R(crate::FieldReader::new(bits)) } diff --git a/src/sio/gpio_hi_oe.rs b/src/sio/gpio_hi_oe.rs index 5559ba44e..c6d019320 100644 --- a/src/sio/gpio_hi_oe.rs +++ b/src/sio/gpio_hi_oe.rs @@ -41,6 +41,7 @@ impl From> for W { and the write from core 1 was then applied to that intermediate result."] pub struct GPIO_HI_OE_R(crate::FieldReader); impl GPIO_HI_OE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { GPIO_HI_OE_R(crate::FieldReader::new(bits)) } @@ -69,14 +70,22 @@ impl<'a> GPIO_HI_OE_W<'a> { } } impl R { - #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. + Reading back gives the last value written. + If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_hi_oe(&self) -> GPIO_HI_OE_R { GPIO_HI_OE_R::new((self.bits & 0x3f) as u8) } } impl W { - #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. + Reading back gives the last value written. + If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_hi_oe(&mut self) -> GPIO_HI_OE_W { GPIO_HI_OE_W { w: self } diff --git a/src/sio/gpio_hi_out.rs b/src/sio/gpio_hi_out.rs index 9f9118ac3..868d47515 100644 --- a/src/sio/gpio_hi_out.rs +++ b/src/sio/gpio_hi_out.rs @@ -41,6 +41,7 @@ impl From> for W { and the write from core 1 was then applied to that intermediate result."] pub struct GPIO_HI_OUT_R(crate::FieldReader); impl GPIO_HI_OUT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { GPIO_HI_OUT_R(crate::FieldReader::new(bits)) } @@ -69,14 +70,22 @@ impl<'a> GPIO_HI_OUT_W<'a> { } } impl R { - #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. + Reading back gives the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_hi_out(&self) -> GPIO_HI_OUT_R { GPIO_HI_OUT_R::new((self.bits & 0x3f) as u8) } } impl W { - #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. + Reading back gives the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_hi_out(&mut self) -> GPIO_HI_OUT_W { GPIO_HI_OUT_W { w: self } diff --git a/src/sio/gpio_in.rs b/src/sio/gpio_in.rs index 227a55066..e45db7c3d 100644 --- a/src/sio/gpio_in.rs +++ b/src/sio/gpio_in.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `GPIO_IN` reader - Input value for GPIO0...29"] pub struct GPIO_IN_R(crate::FieldReader); impl GPIO_IN_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { GPIO_IN_R(crate::FieldReader::new(bits)) } diff --git a/src/sio/gpio_oe.rs b/src/sio/gpio_oe.rs index c8b4474cb..e4fdcb840 100644 --- a/src/sio/gpio_oe.rs +++ b/src/sio/gpio_oe.rs @@ -41,6 +41,7 @@ impl From> for W { and the write from core 1 was then applied to that intermediate result."] pub struct GPIO_OE_R(crate::FieldReader); impl GPIO_OE_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { GPIO_OE_R(crate::FieldReader::new(bits)) } @@ -69,14 +70,22 @@ impl<'a> GPIO_OE_W<'a> { } } impl R { - #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. + Reading back gives the last value written. + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_oe(&self) -> GPIO_OE_R { GPIO_OE_R::new((self.bits & 0x3fff_ffff) as u32) } } impl W { - #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. + Reading back gives the last value written. + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_oe(&mut self) -> GPIO_OE_W { GPIO_OE_W { w: self } diff --git a/src/sio/gpio_out.rs b/src/sio/gpio_out.rs index 401929098..095e91b52 100644 --- a/src/sio/gpio_out.rs +++ b/src/sio/gpio_out.rs @@ -41,6 +41,7 @@ impl From> for W { and the write from core 1 was then applied to that intermediate result."] pub struct GPIO_OUT_R(crate::FieldReader); impl GPIO_OUT_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { GPIO_OUT_R(crate::FieldReader::new(bits)) } @@ -69,14 +70,22 @@ impl<'a> GPIO_OUT_W<'a> { } } impl R { - #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. + Reading back gives the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_out(&self) -> GPIO_OUT_R { GPIO_OUT_R::new((self.bits & 0x3fff_ffff) as u32) } } impl W { - #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. + Reading back gives the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_out(&mut self) -> GPIO_OUT_W { GPIO_OUT_W { w: self } diff --git a/src/sio/interp0_accum0_add.rs b/src/sio/interp0_accum0_add.rs index 6ca898c63..2bd437cf9 100644 --- a/src/sio/interp0_accum0_add.rs +++ b/src/sio/interp0_accum0_add.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTERP0_ACCUM0_ADD` reader - "] pub struct INTERP0_ACCUM0_ADD_R(crate::FieldReader); impl INTERP0_ACCUM0_ADD_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INTERP0_ACCUM0_ADD_R(crate::FieldReader::new(bits)) } diff --git a/src/sio/interp0_accum1_add.rs b/src/sio/interp0_accum1_add.rs index 392366463..82df20546 100644 --- a/src/sio/interp0_accum1_add.rs +++ b/src/sio/interp0_accum1_add.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTERP0_ACCUM1_ADD` reader - "] pub struct INTERP0_ACCUM1_ADD_R(crate::FieldReader); impl INTERP0_ACCUM1_ADD_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INTERP0_ACCUM1_ADD_R(crate::FieldReader::new(bits)) } diff --git a/src/sio/interp0_ctrl_lane0.rs b/src/sio/interp0_ctrl_lane0.rs index f2a035127..a595020ea 100644 --- a/src/sio/interp0_ctrl_lane0.rs +++ b/src/sio/interp0_ctrl_lane0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OVERF` reader - Set if either OVERF0 or OVERF1 is set."] pub struct OVERF_R(crate::FieldReader); impl OVERF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVERF_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for OVERF_R { #[doc = "Field `OVERF1` reader - Indicates if any masked-off MSBs in ACCUM1 are set."] pub struct OVERF1_R(crate::FieldReader); impl OVERF1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVERF1_R(crate::FieldReader::new(bits)) } @@ -65,6 +67,7 @@ impl core::ops::Deref for OVERF1_R { #[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."] pub struct OVERF0_R(crate::FieldReader); impl OVERF0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVERF0_R(crate::FieldReader::new(bits)) } @@ -85,6 +88,7 @@ impl core::ops::Deref for OVERF0_R { LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] pub struct BLEND_R(crate::FieldReader); impl BLEND_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BLEND_R(crate::FieldReader::new(bits)) } @@ -129,6 +133,7 @@ impl<'a> BLEND_W<'a> { of pointers into flash or SRAM."] pub struct FORCE_MSB_R(crate::FieldReader); impl FORCE_MSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FORCE_MSB_R(crate::FieldReader::new(bits)) } @@ -157,6 +162,7 @@ impl<'a> FORCE_MSB_W<'a> { #[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] pub struct ADD_RAW_R(crate::FieldReader); impl ADD_RAW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ADD_RAW_R(crate::FieldReader::new(bits)) } @@ -193,6 +199,7 @@ impl<'a> ADD_RAW_W<'a> { #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub struct CROSS_RESULT_R(crate::FieldReader); impl CROSS_RESULT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CROSS_RESULT_R(crate::FieldReader::new(bits)) } @@ -230,6 +237,7 @@ impl<'a> CROSS_RESULT_W<'a> { Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub struct CROSS_INPUT_R(crate::FieldReader); impl CROSS_INPUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CROSS_INPUT_R(crate::FieldReader::new(bits)) } @@ -268,6 +276,7 @@ impl<'a> CROSS_INPUT_W<'a> { before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] pub struct SIGNED_R(crate::FieldReader); impl SIGNED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIGNED_R(crate::FieldReader::new(bits)) } @@ -306,6 +315,7 @@ impl<'a> SIGNED_W<'a> { Setting MSB < LSB may cause chip to turn inside-out"] pub struct MASK_MSB_R(crate::FieldReader); impl MASK_MSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MASK_MSB_R(crate::FieldReader::new(bits)) } @@ -333,6 +343,7 @@ impl<'a> MASK_MSB_W<'a> { #[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] pub struct MASK_LSB_R(crate::FieldReader); impl MASK_LSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MASK_LSB_R(crate::FieldReader::new(bits)) } @@ -359,6 +370,7 @@ impl<'a> MASK_LSB_W<'a> { #[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"] pub struct SHIFT_R(crate::FieldReader); impl SHIFT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SHIFT_R(crate::FieldReader::new(bits)) } @@ -398,12 +410,20 @@ impl R { pub fn overf0(&self) -> OVERF0_R { OVERF0_R::new(((self.bits >> 23) & 0x01) != 0) } - #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] + #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] #[inline(always)] pub fn blend(&self) -> BLEND_R { BLEND_R::new(((self.bits >> 21) & 0x01) != 0) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&self) -> FORCE_MSB_R { FORCE_MSB_R::new(((self.bits >> 19) & 0x03) as u8) @@ -418,17 +438,20 @@ impl R { pub fn cross_result(&self) -> CROSS_RESULT_R { CROSS_RESULT_R::new(((self.bits >> 17) & 0x01) != 0) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&self) -> CROSS_INPUT_R { CROSS_INPUT_R::new(((self.bits >> 16) & 0x01) != 0) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&self) -> SIGNED_R { SIGNED_R::new(((self.bits >> 15) & 0x01) != 0) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&self) -> MASK_MSB_R { MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) @@ -445,12 +468,20 @@ impl R { } } impl W { - #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] + #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] #[inline(always)] pub fn blend(&mut self) -> BLEND_W { BLEND_W { w: self } } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W { w: self } @@ -465,17 +496,20 @@ impl W { pub fn cross_result(&mut self) -> CROSS_RESULT_W { CROSS_RESULT_W { w: self } } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&mut self) -> CROSS_INPUT_W { CROSS_INPUT_W { w: self } } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&mut self) -> SIGNED_W { SIGNED_W { w: self } } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W { w: self } diff --git a/src/sio/interp0_ctrl_lane1.rs b/src/sio/interp0_ctrl_lane1.rs index cc35f0375..f237a7d63 100644 --- a/src/sio/interp0_ctrl_lane1.rs +++ b/src/sio/interp0_ctrl_lane1.rs @@ -39,6 +39,7 @@ impl From> for W { of pointers into flash or SRAM."] pub struct FORCE_MSB_R(crate::FieldReader); impl FORCE_MSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FORCE_MSB_R(crate::FieldReader::new(bits)) } @@ -67,6 +68,7 @@ impl<'a> FORCE_MSB_W<'a> { #[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] pub struct ADD_RAW_R(crate::FieldReader); impl ADD_RAW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ADD_RAW_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> ADD_RAW_W<'a> { #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub struct CROSS_RESULT_R(crate::FieldReader); impl CROSS_RESULT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CROSS_RESULT_R(crate::FieldReader::new(bits)) } @@ -140,6 +143,7 @@ impl<'a> CROSS_RESULT_W<'a> { Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub struct CROSS_INPUT_R(crate::FieldReader); impl CROSS_INPUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CROSS_INPUT_R(crate::FieldReader::new(bits)) } @@ -178,6 +182,7 @@ impl<'a> CROSS_INPUT_W<'a> { before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] pub struct SIGNED_R(crate::FieldReader); impl SIGNED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIGNED_R(crate::FieldReader::new(bits)) } @@ -216,6 +221,7 @@ impl<'a> SIGNED_W<'a> { Setting MSB < LSB may cause chip to turn inside-out"] pub struct MASK_MSB_R(crate::FieldReader); impl MASK_MSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MASK_MSB_R(crate::FieldReader::new(bits)) } @@ -243,6 +249,7 @@ impl<'a> MASK_MSB_W<'a> { #[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] pub struct MASK_LSB_R(crate::FieldReader); impl MASK_LSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MASK_LSB_R(crate::FieldReader::new(bits)) } @@ -269,6 +276,7 @@ impl<'a> MASK_LSB_W<'a> { #[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"] pub struct SHIFT_R(crate::FieldReader); impl SHIFT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SHIFT_R(crate::FieldReader::new(bits)) } @@ -293,7 +301,9 @@ impl<'a> SHIFT_W<'a> { } } impl R { - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&self) -> FORCE_MSB_R { FORCE_MSB_R::new(((self.bits >> 19) & 0x03) as u8) @@ -308,17 +318,20 @@ impl R { pub fn cross_result(&self) -> CROSS_RESULT_R { CROSS_RESULT_R::new(((self.bits >> 17) & 0x01) != 0) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&self) -> CROSS_INPUT_R { CROSS_INPUT_R::new(((self.bits >> 16) & 0x01) != 0) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&self) -> SIGNED_R { SIGNED_R::new(((self.bits >> 15) & 0x01) != 0) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&self) -> MASK_MSB_R { MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) @@ -335,7 +348,9 @@ impl R { } } impl W { - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W { w: self } @@ -350,17 +365,20 @@ impl W { pub fn cross_result(&mut self) -> CROSS_RESULT_W { CROSS_RESULT_W { w: self } } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&mut self) -> CROSS_INPUT_W { CROSS_INPUT_W { w: self } } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&mut self) -> SIGNED_W { SIGNED_W { w: self } } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W { w: self } diff --git a/src/sio/interp1_accum0_add.rs b/src/sio/interp1_accum0_add.rs index a29495540..db1fb840f 100644 --- a/src/sio/interp1_accum0_add.rs +++ b/src/sio/interp1_accum0_add.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTERP1_ACCUM0_ADD` reader - "] pub struct INTERP1_ACCUM0_ADD_R(crate::FieldReader); impl INTERP1_ACCUM0_ADD_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INTERP1_ACCUM0_ADD_R(crate::FieldReader::new(bits)) } diff --git a/src/sio/interp1_accum1_add.rs b/src/sio/interp1_accum1_add.rs index 03ea79983..9af7c2211 100644 --- a/src/sio/interp1_accum1_add.rs +++ b/src/sio/interp1_accum1_add.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTERP1_ACCUM1_ADD` reader - "] pub struct INTERP1_ACCUM1_ADD_R(crate::FieldReader); impl INTERP1_ACCUM1_ADD_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { INTERP1_ACCUM1_ADD_R(crate::FieldReader::new(bits)) } diff --git a/src/sio/interp1_ctrl_lane0.rs b/src/sio/interp1_ctrl_lane0.rs index 3aa37c01e..58922c219 100644 --- a/src/sio/interp1_ctrl_lane0.rs +++ b/src/sio/interp1_ctrl_lane0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OVERF` reader - Set if either OVERF0 or OVERF1 is set."] pub struct OVERF_R(crate::FieldReader); impl OVERF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVERF_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for OVERF_R { #[doc = "Field `OVERF1` reader - Indicates if any masked-off MSBs in ACCUM1 are set."] pub struct OVERF1_R(crate::FieldReader); impl OVERF1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVERF1_R(crate::FieldReader::new(bits)) } @@ -65,6 +67,7 @@ impl core::ops::Deref for OVERF1_R { #[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."] pub struct OVERF0_R(crate::FieldReader); impl OVERF0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVERF0_R(crate::FieldReader::new(bits)) } @@ -82,6 +85,7 @@ impl core::ops::Deref for OVERF0_R { - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] pub struct CLAMP_R(crate::FieldReader); impl CLAMP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CLAMP_R(crate::FieldReader::new(bits)) } @@ -123,6 +127,7 @@ impl<'a> CLAMP_W<'a> { of pointers into flash or SRAM."] pub struct FORCE_MSB_R(crate::FieldReader); impl FORCE_MSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FORCE_MSB_R(crate::FieldReader::new(bits)) } @@ -151,6 +156,7 @@ impl<'a> FORCE_MSB_W<'a> { #[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] pub struct ADD_RAW_R(crate::FieldReader); impl ADD_RAW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ADD_RAW_R(crate::FieldReader::new(bits)) } @@ -187,6 +193,7 @@ impl<'a> ADD_RAW_W<'a> { #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub struct CROSS_RESULT_R(crate::FieldReader); impl CROSS_RESULT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CROSS_RESULT_R(crate::FieldReader::new(bits)) } @@ -224,6 +231,7 @@ impl<'a> CROSS_RESULT_W<'a> { Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub struct CROSS_INPUT_R(crate::FieldReader); impl CROSS_INPUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CROSS_INPUT_R(crate::FieldReader::new(bits)) } @@ -262,6 +270,7 @@ impl<'a> CROSS_INPUT_W<'a> { before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] pub struct SIGNED_R(crate::FieldReader); impl SIGNED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIGNED_R(crate::FieldReader::new(bits)) } @@ -300,6 +309,7 @@ impl<'a> SIGNED_W<'a> { Setting MSB < LSB may cause chip to turn inside-out"] pub struct MASK_MSB_R(crate::FieldReader); impl MASK_MSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MASK_MSB_R(crate::FieldReader::new(bits)) } @@ -327,6 +337,7 @@ impl<'a> MASK_MSB_W<'a> { #[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] pub struct MASK_LSB_R(crate::FieldReader); impl MASK_LSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MASK_LSB_R(crate::FieldReader::new(bits)) } @@ -353,6 +364,7 @@ impl<'a> MASK_LSB_W<'a> { #[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"] pub struct SHIFT_R(crate::FieldReader); impl SHIFT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SHIFT_R(crate::FieldReader::new(bits)) } @@ -392,12 +404,17 @@ impl R { pub fn overf0(&self) -> OVERF0_R { OVERF0_R::new(((self.bits >> 23) & 0x01) != 0) } - #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] + #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] #[inline(always)] pub fn clamp(&self) -> CLAMP_R { CLAMP_R::new(((self.bits >> 22) & 0x01) != 0) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&self) -> FORCE_MSB_R { FORCE_MSB_R::new(((self.bits >> 19) & 0x03) as u8) @@ -412,17 +429,20 @@ impl R { pub fn cross_result(&self) -> CROSS_RESULT_R { CROSS_RESULT_R::new(((self.bits >> 17) & 0x01) != 0) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&self) -> CROSS_INPUT_R { CROSS_INPUT_R::new(((self.bits >> 16) & 0x01) != 0) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&self) -> SIGNED_R { SIGNED_R::new(((self.bits >> 15) & 0x01) != 0) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&self) -> MASK_MSB_R { MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) @@ -439,12 +459,17 @@ impl R { } } impl W { - #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] + #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] #[inline(always)] pub fn clamp(&mut self) -> CLAMP_W { CLAMP_W { w: self } } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W { w: self } @@ -459,17 +484,20 @@ impl W { pub fn cross_result(&mut self) -> CROSS_RESULT_W { CROSS_RESULT_W { w: self } } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&mut self) -> CROSS_INPUT_W { CROSS_INPUT_W { w: self } } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&mut self) -> SIGNED_W { SIGNED_W { w: self } } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W { w: self } diff --git a/src/sio/interp1_ctrl_lane1.rs b/src/sio/interp1_ctrl_lane1.rs index f0e7ab775..f6024dc5f 100644 --- a/src/sio/interp1_ctrl_lane1.rs +++ b/src/sio/interp1_ctrl_lane1.rs @@ -39,6 +39,7 @@ impl From> for W { of pointers into flash or SRAM."] pub struct FORCE_MSB_R(crate::FieldReader); impl FORCE_MSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FORCE_MSB_R(crate::FieldReader::new(bits)) } @@ -67,6 +68,7 @@ impl<'a> FORCE_MSB_W<'a> { #[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] pub struct ADD_RAW_R(crate::FieldReader); impl ADD_RAW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ADD_RAW_R(crate::FieldReader::new(bits)) } @@ -103,6 +105,7 @@ impl<'a> ADD_RAW_W<'a> { #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub struct CROSS_RESULT_R(crate::FieldReader); impl CROSS_RESULT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CROSS_RESULT_R(crate::FieldReader::new(bits)) } @@ -140,6 +143,7 @@ impl<'a> CROSS_RESULT_W<'a> { Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub struct CROSS_INPUT_R(crate::FieldReader); impl CROSS_INPUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CROSS_INPUT_R(crate::FieldReader::new(bits)) } @@ -178,6 +182,7 @@ impl<'a> CROSS_INPUT_W<'a> { before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] pub struct SIGNED_R(crate::FieldReader); impl SIGNED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIGNED_R(crate::FieldReader::new(bits)) } @@ -216,6 +221,7 @@ impl<'a> SIGNED_W<'a> { Setting MSB < LSB may cause chip to turn inside-out"] pub struct MASK_MSB_R(crate::FieldReader); impl MASK_MSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MASK_MSB_R(crate::FieldReader::new(bits)) } @@ -243,6 +249,7 @@ impl<'a> MASK_MSB_W<'a> { #[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] pub struct MASK_LSB_R(crate::FieldReader); impl MASK_LSB_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { MASK_LSB_R(crate::FieldReader::new(bits)) } @@ -269,6 +276,7 @@ impl<'a> MASK_LSB_W<'a> { #[doc = "Field `SHIFT` reader - Logical right-shift applied to accumulator before masking"] pub struct SHIFT_R(crate::FieldReader); impl SHIFT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SHIFT_R(crate::FieldReader::new(bits)) } @@ -293,7 +301,9 @@ impl<'a> SHIFT_W<'a> { } } impl R { - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&self) -> FORCE_MSB_R { FORCE_MSB_R::new(((self.bits >> 19) & 0x03) as u8) @@ -308,17 +318,20 @@ impl R { pub fn cross_result(&self) -> CROSS_RESULT_R { CROSS_RESULT_R::new(((self.bits >> 17) & 0x01) != 0) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&self) -> CROSS_INPUT_R { CROSS_INPUT_R::new(((self.bits >> 16) & 0x01) != 0) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&self) -> SIGNED_R { SIGNED_R::new(((self.bits >> 15) & 0x01) != 0) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&self) -> MASK_MSB_R { MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) @@ -335,7 +348,9 @@ impl R { } } impl W { - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W { w: self } @@ -350,17 +365,20 @@ impl W { pub fn cross_result(&mut self) -> CROSS_RESULT_W { CROSS_RESULT_W { w: self } } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&mut self) -> CROSS_INPUT_W { CROSS_INPUT_W { w: self } } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&mut self) -> SIGNED_W { SIGNED_W { w: self } } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W { w: self } diff --git a/src/spi0/sspcpsr.rs b/src/spi0/sspcpsr.rs index fec52e320..29ad3933c 100644 --- a/src/spi0/sspcpsr.rs +++ b/src/spi0/sspcpsr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CPSDVSR` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub struct CPSDVSR_R(crate::FieldReader); impl CPSDVSR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CPSDVSR_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspcr0.rs b/src/spi0/sspcr0.rs index 4488f7fe4..1fd9cc2b8 100644 --- a/src/spi0/sspcr0.rs +++ b/src/spi0/sspcr0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SCR` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."] pub struct SCR_R(crate::FieldReader); impl SCR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SCR_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> SCR_W<'a> { #[doc = "Field `SPH` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] pub struct SPH_R(crate::FieldReader); impl SPH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPH_R(crate::FieldReader::new(bits)) } @@ -99,6 +101,7 @@ impl<'a> SPH_W<'a> { #[doc = "Field `SPO` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] pub struct SPO_R(crate::FieldReader); impl SPO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPO_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> SPO_W<'a> { #[doc = "Field `FRF` reader - Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation."] pub struct FRF_R(crate::FieldReader); impl FRF_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRF_R(crate::FieldReader::new(bits)) } @@ -161,6 +165,7 @@ impl<'a> FRF_W<'a> { #[doc = "Field `DSS` reader - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] pub struct DSS_R(crate::FieldReader); impl DSS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DSS_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspcr1.rs b/src/spi0/sspcr1.rs index e00f72617..88539cdba 100644 --- a/src/spi0/sspcr1.rs +++ b/src/spi0/sspcr1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SOD` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."] pub struct SOD_R(crate::FieldReader); impl SOD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SOD_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> SOD_W<'a> { #[doc = "Field `MS` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."] pub struct MS_R(crate::FieldReader); impl MS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MS_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> MS_W<'a> { #[doc = "Field `SSE` reader - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."] pub struct SSE_R(crate::FieldReader); impl SSE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SSE_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> SSE_W<'a> { #[doc = "Field `LBM` reader - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] pub struct LBM_R(crate::FieldReader); impl LBM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { LBM_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspdmacr.rs b/src/spi0/sspdmacr.rs index 01c6e51a3..01d4fc7d0 100644 --- a/src/spi0/sspdmacr.rs +++ b/src/spi0/sspdmacr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TXDMAE` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub struct TXDMAE_R(crate::FieldReader); impl TXDMAE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXDMAE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> TXDMAE_W<'a> { #[doc = "Field `RXDMAE` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub struct RXDMAE_R(crate::FieldReader); impl RXDMAE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXDMAE_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspdr.rs b/src/spi0/sspdr.rs index b1402772c..87d44f16c 100644 --- a/src/spi0/sspdr.rs +++ b/src/spi0/sspdr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DATA` reader - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub struct DATA_R(crate::FieldReader); impl DATA_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { DATA_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspicr.rs b/src/spi0/sspicr.rs index 1cb6fc9b0..07d27aac5 100644 --- a/src/spi0/sspicr.rs +++ b/src/spi0/sspicr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `RTIC` reader - Clears the SSPRTINTR interrupt"] pub struct RTIC_R(crate::FieldReader); impl RTIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTIC_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> RTIC_W<'a> { #[doc = "Field `RORIC` reader - Clears the SSPRORINTR interrupt"] pub struct RORIC_R(crate::FieldReader); impl RORIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RORIC_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspimsc.rs b/src/spi0/sspimsc.rs index 496591f72..e3c461d49 100644 --- a/src/spi0/sspimsc.rs +++ b/src/spi0/sspimsc.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TXIM` reader - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."] pub struct TXIM_R(crate::FieldReader); impl TXIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXIM_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> TXIM_W<'a> { #[doc = "Field `RXIM` reader - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."] pub struct RXIM_R(crate::FieldReader); impl RXIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXIM_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> RXIM_W<'a> { #[doc = "Field `RTIM` reader - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."] pub struct RTIM_R(crate::FieldReader); impl RTIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTIM_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> RTIM_W<'a> { #[doc = "Field `RORIM` reader - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] pub struct RORIM_R(crate::FieldReader); impl RORIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RORIM_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspmis.rs b/src/spi0/sspmis.rs index 37f5cf90d..0c548ee65 100644 --- a/src/spi0/sspmis.rs +++ b/src/spi0/sspmis.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `TXMIS` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] pub struct TXMIS_R(crate::FieldReader); impl TXMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXMIS_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for TXMIS_R { #[doc = "Field `RXMIS` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] pub struct RXMIS_R(crate::FieldReader); impl RXMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXMIS_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for RXMIS_R { #[doc = "Field `RTMIS` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] pub struct RTMIS_R(crate::FieldReader); impl RTMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTMIS_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RTMIS_R { #[doc = "Field `RORMIS` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] pub struct RORMIS_R(crate::FieldReader); impl RORMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RORMIS_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/ssppcellid0.rs b/src/spi0/ssppcellid0.rs index 6f78aea26..9310bfe58 100644 --- a/src/spi0/ssppcellid0.rs +++ b/src/spi0/ssppcellid0.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `SSPPCELLID0` reader - These bits read back as 0x0D"] pub struct SSPPCELLID0_R(crate::FieldReader); impl SSPPCELLID0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SSPPCELLID0_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/ssppcellid1.rs b/src/spi0/ssppcellid1.rs index 335fd4da2..49ece2ce0 100644 --- a/src/spi0/ssppcellid1.rs +++ b/src/spi0/ssppcellid1.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `SSPPCELLID1` reader - These bits read back as 0xF0"] pub struct SSPPCELLID1_R(crate::FieldReader); impl SSPPCELLID1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SSPPCELLID1_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/ssppcellid2.rs b/src/spi0/ssppcellid2.rs index cd5123ca1..f6ffa5ab0 100644 --- a/src/spi0/ssppcellid2.rs +++ b/src/spi0/ssppcellid2.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `SSPPCELLID2` reader - These bits read back as 0x05"] pub struct SSPPCELLID2_R(crate::FieldReader); impl SSPPCELLID2_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SSPPCELLID2_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/ssppcellid3.rs b/src/spi0/ssppcellid3.rs index 1cebab47f..4ba6fbddd 100644 --- a/src/spi0/ssppcellid3.rs +++ b/src/spi0/ssppcellid3.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `SSPPCELLID3` reader - These bits read back as 0xB1"] pub struct SSPPCELLID3_R(crate::FieldReader); impl SSPPCELLID3_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SSPPCELLID3_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspperiphid0.rs b/src/spi0/sspperiphid0.rs index 2199988a1..bf7b8e03c 100644 --- a/src/spi0/sspperiphid0.rs +++ b/src/spi0/sspperiphid0.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `PARTNUMBER0` reader - These bits read back as 0x22"] pub struct PARTNUMBER0_R(crate::FieldReader); impl PARTNUMBER0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PARTNUMBER0_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspperiphid1.rs b/src/spi0/sspperiphid1.rs index 028eb9eca..7f5c4aef8 100644 --- a/src/spi0/sspperiphid1.rs +++ b/src/spi0/sspperiphid1.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `DESIGNER0` reader - These bits read back as 0x1"] pub struct DESIGNER0_R(crate::FieldReader); impl DESIGNER0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DESIGNER0_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for DESIGNER0_R { #[doc = "Field `PARTNUMBER1` reader - These bits read back as 0x0"] pub struct PARTNUMBER1_R(crate::FieldReader); impl PARTNUMBER1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PARTNUMBER1_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspperiphid2.rs b/src/spi0/sspperiphid2.rs index bd045d78b..ba33507a8 100644 --- a/src/spi0/sspperiphid2.rs +++ b/src/spi0/sspperiphid2.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `REVISION` reader - These bits return the peripheral revision"] pub struct REVISION_R(crate::FieldReader); impl REVISION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { REVISION_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for REVISION_R { #[doc = "Field `DESIGNER1` reader - These bits read back as 0x4"] pub struct DESIGNER1_R(crate::FieldReader); impl DESIGNER1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DESIGNER1_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspperiphid3.rs b/src/spi0/sspperiphid3.rs index 9a9cc4f63..8c8bb5c1a 100644 --- a/src/spi0/sspperiphid3.rs +++ b/src/spi0/sspperiphid3.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `CONFIGURATION` reader - These bits read back as 0x00"] pub struct CONFIGURATION_R(crate::FieldReader); impl CONFIGURATION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CONFIGURATION_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspris.rs b/src/spi0/sspris.rs index 2c98a20b5..b1d16a3ef 100644 --- a/src/spi0/sspris.rs +++ b/src/spi0/sspris.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `TXRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] pub struct TXRIS_R(crate::FieldReader); impl TXRIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXRIS_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for TXRIS_R { #[doc = "Field `RXRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] pub struct RXRIS_R(crate::FieldReader); impl RXRIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXRIS_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for RXRIS_R { #[doc = "Field `RTRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] pub struct RTRIS_R(crate::FieldReader); impl RTRIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTRIS_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RTRIS_R { #[doc = "Field `RORRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] pub struct RORRIS_R(crate::FieldReader); impl RORRIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RORRIS_R(crate::FieldReader::new(bits)) } diff --git a/src/spi0/sspsr.rs b/src/spi0/sspsr.rs index fc4ffce63..c60835ef5 100644 --- a/src/spi0/sspsr.rs +++ b/src/spi0/sspsr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `BSY` reader - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] pub struct BSY_R(crate::FieldReader); impl BSY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BSY_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for BSY_R { #[doc = "Field `RFF` reader - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full."] pub struct RFF_R(crate::FieldReader); impl RFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RFF_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for RFF_R { #[doc = "Field `RNE` reader - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty."] pub struct RNE_R(crate::FieldReader); impl RNE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RNE_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RNE_R { #[doc = "Field `TNF` reader - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full."] pub struct TNF_R(crate::FieldReader); impl TNF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TNF_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for TNF_R { #[doc = "Field `TFE` reader - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty."] pub struct TFE_R(crate::FieldReader); impl TFE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TFE_R(crate::FieldReader::new(bits)) } diff --git a/src/syscfg/dbgforce.rs b/src/syscfg/dbgforce.rs index 79ba822b0..89dddc338 100644 --- a/src/syscfg/dbgforce.rs +++ b/src/syscfg/dbgforce.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `PROC1_ATTACH` reader - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads."] pub struct PROC1_ATTACH_R(crate::FieldReader); impl PROC1_ATTACH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_ATTACH_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> PROC1_ATTACH_W<'a> { #[doc = "Field `PROC1_SWCLK` reader - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set"] pub struct PROC1_SWCLK_R(crate::FieldReader); impl PROC1_SWCLK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_SWCLK_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> PROC1_SWCLK_W<'a> { #[doc = "Field `PROC1_SWDI` reader - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set"] pub struct PROC1_SWDI_R(crate::FieldReader); impl PROC1_SWDI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_SWDI_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> PROC1_SWDI_W<'a> { #[doc = "Field `PROC1_SWDO` reader - Observe the value of processor 1 SWDIO output."] pub struct PROC1_SWDO_R(crate::FieldReader); impl PROC1_SWDO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_SWDO_R(crate::FieldReader::new(bits)) } @@ -159,6 +163,7 @@ impl core::ops::Deref for PROC1_SWDO_R { #[doc = "Field `PROC0_ATTACH` reader - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads."] pub struct PROC0_ATTACH_R(crate::FieldReader); impl PROC0_ATTACH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_ATTACH_R(crate::FieldReader::new(bits)) } @@ -195,6 +200,7 @@ impl<'a> PROC0_ATTACH_W<'a> { #[doc = "Field `PROC0_SWCLK` reader - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set"] pub struct PROC0_SWCLK_R(crate::FieldReader); impl PROC0_SWCLK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_SWCLK_R(crate::FieldReader::new(bits)) } @@ -231,6 +237,7 @@ impl<'a> PROC0_SWCLK_W<'a> { #[doc = "Field `PROC0_SWDI` reader - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set"] pub struct PROC0_SWDI_R(crate::FieldReader); impl PROC0_SWDI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_SWDI_R(crate::FieldReader::new(bits)) } @@ -267,6 +274,7 @@ impl<'a> PROC0_SWDI_W<'a> { #[doc = "Field `PROC0_SWDO` reader - Observe the value of processor 0 SWDIO output."] pub struct PROC0_SWDO_R(crate::FieldReader); impl PROC0_SWDO_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_SWDO_R(crate::FieldReader::new(bits)) } diff --git a/src/syscfg/mempowerdown.rs b/src/syscfg/mempowerdown.rs index 6f7798ac2..121d47fab 100644 --- a/src/syscfg/mempowerdown.rs +++ b/src/syscfg/mempowerdown.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ROM` reader - "] pub struct ROM_R(crate::FieldReader); impl ROM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROM_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> ROM_W<'a> { #[doc = "Field `USB` reader - "] pub struct USB_R(crate::FieldReader); impl USB_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { USB_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> USB_W<'a> { #[doc = "Field `SRAM5` reader - "] pub struct SRAM5_R(crate::FieldReader); impl SRAM5_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM5_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> SRAM5_W<'a> { #[doc = "Field `SRAM4` reader - "] pub struct SRAM4_R(crate::FieldReader); impl SRAM4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM4_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> SRAM4_W<'a> { #[doc = "Field `SRAM3` reader - "] pub struct SRAM3_R(crate::FieldReader); impl SRAM3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM3_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> SRAM3_W<'a> { #[doc = "Field `SRAM2` reader - "] pub struct SRAM2_R(crate::FieldReader); impl SRAM2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM2_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> SRAM2_W<'a> { #[doc = "Field `SRAM1` reader - "] pub struct SRAM1_R(crate::FieldReader); impl SRAM1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM1_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> SRAM1_W<'a> { #[doc = "Field `SRAM0` reader - "] pub struct SRAM0_R(crate::FieldReader); impl SRAM0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRAM0_R(crate::FieldReader::new(bits)) } diff --git a/src/syscfg/proc_config.rs b/src/syscfg/proc_config.rs index b0ce808a9..51c6fb3bb 100644 --- a/src/syscfg/proc_config.rs +++ b/src/syscfg/proc_config.rs @@ -39,6 +39,7 @@ impl From> for W { WARNING: do not set to 15 as this is reserved for RescueDP"] pub struct PROC1_DAP_INSTID_R(crate::FieldReader); impl PROC1_DAP_INSTID_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PROC1_DAP_INSTID_R(crate::FieldReader::new(bits)) } @@ -69,6 +70,7 @@ impl<'a> PROC1_DAP_INSTID_W<'a> { WARNING: do not set to 15 as this is reserved for RescueDP"] pub struct PROC0_DAP_INSTID_R(crate::FieldReader); impl PROC0_DAP_INSTID_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PROC0_DAP_INSTID_R(crate::FieldReader::new(bits)) } @@ -97,6 +99,7 @@ impl<'a> PROC0_DAP_INSTID_W<'a> { #[doc = "Field `PROC1_HALTED` reader - Indication that proc1 has halted"] pub struct PROC1_HALTED_R(crate::FieldReader); impl PROC1_HALTED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC1_HALTED_R(crate::FieldReader::new(bits)) } @@ -111,6 +114,7 @@ impl core::ops::Deref for PROC1_HALTED_R { #[doc = "Field `PROC0_HALTED` reader - Indication that proc0 has halted"] pub struct PROC0_HALTED_R(crate::FieldReader); impl PROC0_HALTED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PROC0_HALTED_R(crate::FieldReader::new(bits)) } @@ -123,12 +127,16 @@ impl core::ops::Deref for PROC0_HALTED_R { } } impl R { - #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] + #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. + Recommend that this is NOT changed until you require debug access in multi-chip environment + WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] pub fn proc1_dap_instid(&self) -> PROC1_DAP_INSTID_R { PROC1_DAP_INSTID_R::new(((self.bits >> 28) & 0x0f) as u8) } - #[doc = "Bits 24:27 - Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] + #[doc = "Bits 24:27 - Configure proc0 DAP instance ID. + Recommend that this is NOT changed until you require debug access in multi-chip environment + WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] pub fn proc0_dap_instid(&self) -> PROC0_DAP_INSTID_R { PROC0_DAP_INSTID_R::new(((self.bits >> 24) & 0x0f) as u8) @@ -145,12 +153,16 @@ impl R { } } impl W { - #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] + #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. + Recommend that this is NOT changed until you require debug access in multi-chip environment + WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] pub fn proc1_dap_instid(&mut self) -> PROC1_DAP_INSTID_W { PROC1_DAP_INSTID_W { w: self } } - #[doc = "Bits 24:27 - Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] + #[doc = "Bits 24:27 - Configure proc0 DAP instance ID. + Recommend that this is NOT changed until you require debug access in multi-chip environment + WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] pub fn proc0_dap_instid(&mut self) -> PROC0_DAP_INSTID_W { PROC0_DAP_INSTID_W { w: self } diff --git a/src/syscfg/proc_in_sync_bypass.rs b/src/syscfg/proc_in_sync_bypass.rs index 0903ef8a7..bfed26ec2 100644 --- a/src/syscfg/proc_in_sync_bypass.rs +++ b/src/syscfg/proc_in_sync_bypass.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `PROC_IN_SYNC_BYPASS` reader - "] pub struct PROC_IN_SYNC_BYPASS_R(crate::FieldReader); impl PROC_IN_SYNC_BYPASS_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { PROC_IN_SYNC_BYPASS_R(crate::FieldReader::new(bits)) } diff --git a/src/syscfg/proc_in_sync_bypass_hi.rs b/src/syscfg/proc_in_sync_bypass_hi.rs index be4f31e4e..ebbf0bc1a 100644 --- a/src/syscfg/proc_in_sync_bypass_hi.rs +++ b/src/syscfg/proc_in_sync_bypass_hi.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `PROC_IN_SYNC_BYPASS_HI` reader - "] pub struct PROC_IN_SYNC_BYPASS_HI_R(crate::FieldReader); impl PROC_IN_SYNC_BYPASS_HI_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PROC_IN_SYNC_BYPASS_HI_R(crate::FieldReader::new(bits)) } diff --git a/src/sysinfo/chip_id.rs b/src/sysinfo/chip_id.rs index b26ce5f5a..507eec407 100644 --- a/src/sysinfo/chip_id.rs +++ b/src/sysinfo/chip_id.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `REVISION` reader - "] pub struct REVISION_R(crate::FieldReader); impl REVISION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { REVISION_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for REVISION_R { #[doc = "Field `PART` reader - "] pub struct PART_R(crate::FieldReader); impl PART_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { PART_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for PART_R { #[doc = "Field `MANUFACTURER` reader - "] pub struct MANUFACTURER_R(crate::FieldReader); impl MANUFACTURER_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { MANUFACTURER_R(crate::FieldReader::new(bits)) } diff --git a/src/sysinfo/platform.rs b/src/sysinfo/platform.rs index dc04a6b89..3244b12b0 100644 --- a/src/sysinfo/platform.rs +++ b/src/sysinfo/platform.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `ASIC` reader - "] pub struct ASIC_R(crate::FieldReader); impl ASIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ASIC_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for ASIC_R { #[doc = "Field `FPGA` reader - "] pub struct FPGA_R(crate::FieldReader); impl FPGA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FPGA_R(crate::FieldReader::new(bits)) } diff --git a/src/tbman/platform.rs b/src/tbman/platform.rs index b7e296bad..3d4a1137d 100644 --- a/src/tbman/platform.rs +++ b/src/tbman/platform.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `FPGA` reader - Indicates the platform is an FPGA"] pub struct FPGA_R(crate::FieldReader); impl FPGA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FPGA_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for FPGA_R { #[doc = "Field `ASIC` reader - Indicates the platform is an ASIC"] pub struct ASIC_R(crate::FieldReader); impl ASIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ASIC_R(crate::FieldReader::new(bits)) } diff --git a/src/timer/armed.rs b/src/timer/armed.rs index dfe678f8b..a8fd9f1ec 100644 --- a/src/timer/armed.rs +++ b/src/timer/armed.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ARMED` reader - "] pub struct ARMED_R(crate::FieldReader); impl ARMED_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ARMED_R(crate::FieldReader::new(bits)) } diff --git a/src/timer/dbgpause.rs b/src/timer/dbgpause.rs index f4fd7c5d0..17d49d17b 100644 --- a/src/timer/dbgpause.rs +++ b/src/timer/dbgpause.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DBG1` reader - Pause when processor 1 is in debug mode"] pub struct DBG1_R(crate::FieldReader); impl DBG1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DBG1_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> DBG1_W<'a> { #[doc = "Field `DBG0` reader - Pause when processor 0 is in debug mode"] pub struct DBG0_R(crate::FieldReader); impl DBG0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DBG0_R(crate::FieldReader::new(bits)) } diff --git a/src/timer/inte.rs b/src/timer/inte.rs index 1d14cf881..80cbe1a59 100644 --- a/src/timer/inte.rs +++ b/src/timer/inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ALARM_3` reader - "] pub struct ALARM_3_R(crate::FieldReader); impl ALARM_3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_3_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> ALARM_3_W<'a> { #[doc = "Field `ALARM_2` reader - "] pub struct ALARM_2_R(crate::FieldReader); impl ALARM_2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_2_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> ALARM_2_W<'a> { #[doc = "Field `ALARM_1` reader - "] pub struct ALARM_1_R(crate::FieldReader); impl ALARM_1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> ALARM_1_W<'a> { #[doc = "Field `ALARM_0` reader - "] pub struct ALARM_0_R(crate::FieldReader); impl ALARM_0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_0_R(crate::FieldReader::new(bits)) } diff --git a/src/timer/intf.rs b/src/timer/intf.rs index 0860f57c3..fc0abf71f 100644 --- a/src/timer/intf.rs +++ b/src/timer/intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ALARM_3` reader - "] pub struct ALARM_3_R(crate::FieldReader); impl ALARM_3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_3_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> ALARM_3_W<'a> { #[doc = "Field `ALARM_2` reader - "] pub struct ALARM_2_R(crate::FieldReader); impl ALARM_2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_2_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> ALARM_2_W<'a> { #[doc = "Field `ALARM_1` reader - "] pub struct ALARM_1_R(crate::FieldReader); impl ALARM_1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> ALARM_1_W<'a> { #[doc = "Field `ALARM_0` reader - "] pub struct ALARM_0_R(crate::FieldReader); impl ALARM_0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_0_R(crate::FieldReader::new(bits)) } diff --git a/src/timer/intr.rs b/src/timer/intr.rs index 1f5c8f680..6c7c2bc1f 100644 --- a/src/timer/intr.rs +++ b/src/timer/intr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ALARM_3` reader - "] pub struct ALARM_3_R(crate::FieldReader); impl ALARM_3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_3_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> ALARM_3_W<'a> { #[doc = "Field `ALARM_2` reader - "] pub struct ALARM_2_R(crate::FieldReader); impl ALARM_2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_2_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> ALARM_2_W<'a> { #[doc = "Field `ALARM_1` reader - "] pub struct ALARM_1_R(crate::FieldReader); impl ALARM_1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> ALARM_1_W<'a> { #[doc = "Field `ALARM_0` reader - "] pub struct ALARM_0_R(crate::FieldReader); impl ALARM_0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_0_R(crate::FieldReader::new(bits)) } diff --git a/src/timer/ints.rs b/src/timer/ints.rs index 5af644e3f..b1c407c17 100644 --- a/src/timer/ints.rs +++ b/src/timer/ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `ALARM_3` reader - "] pub struct ALARM_3_R(crate::FieldReader); impl ALARM_3_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_3_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for ALARM_3_R { #[doc = "Field `ALARM_2` reader - "] pub struct ALARM_2_R(crate::FieldReader); impl ALARM_2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_2_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for ALARM_2_R { #[doc = "Field `ALARM_1` reader - "] pub struct ALARM_1_R(crate::FieldReader); impl ALARM_1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_1_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for ALARM_1_R { #[doc = "Field `ALARM_0` reader - "] pub struct ALARM_0_R(crate::FieldReader); impl ALARM_0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ALARM_0_R(crate::FieldReader::new(bits)) } diff --git a/src/timer/pause.rs b/src/timer/pause.rs index fc1181b98..20eed377f 100644 --- a/src/timer/pause.rs +++ b/src/timer/pause.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `PAUSE` reader - "] pub struct PAUSE_R(crate::FieldReader); impl PAUSE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PAUSE_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartcr.rs b/src/uart0/uartcr.rs index 445b34fba..5bed0ac8f 100644 --- a/src/uart0/uartcr.rs +++ b/src/uart0/uartcr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `CTSEN` reader - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."] pub struct CTSEN_R(crate::FieldReader); impl CTSEN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CTSEN_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> CTSEN_W<'a> { #[doc = "Field `RTSEN` reader - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."] pub struct RTSEN_R(crate::FieldReader); impl RTSEN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTSEN_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> RTSEN_W<'a> { #[doc = "Field `OUT2` reader - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."] pub struct OUT2_R(crate::FieldReader); impl OUT2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUT2_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> OUT2_W<'a> { #[doc = "Field `OUT1` reader - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."] pub struct OUT1_R(crate::FieldReader); impl OUT1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OUT1_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> OUT1_W<'a> { #[doc = "Field `RTS` reader - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."] pub struct RTS_R(crate::FieldReader); impl RTS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTS_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> RTS_W<'a> { #[doc = "Field `DTR` reader - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."] pub struct DTR_R(crate::FieldReader); impl DTR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DTR_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> DTR_W<'a> { #[doc = "Field `RXE` reader - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."] pub struct RXE_R(crate::FieldReader); impl RXE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXE_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> RXE_W<'a> { #[doc = "Field `TXE` reader - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."] pub struct TXE_R(crate::FieldReader); impl TXE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXE_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> TXE_W<'a> { #[doc = "Field `LBE` reader - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."] pub struct LBE_R(crate::FieldReader); impl LBE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { LBE_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> LBE_W<'a> { #[doc = "Field `SIRLP` reader - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."] pub struct SIRLP_R(crate::FieldReader); impl SIRLP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIRLP_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> SIRLP_W<'a> { #[doc = "Field `SIREN` reader - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."] pub struct SIREN_R(crate::FieldReader); impl SIREN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIREN_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> SIREN_W<'a> { #[doc = "Field `UARTEN` reader - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] pub struct UARTEN_R(crate::FieldReader); impl UARTEN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { UARTEN_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartdmacr.rs b/src/uart0/uartdmacr.rs index 8b0079267..9867a94f5 100644 --- a/src/uart0/uartdmacr.rs +++ b/src/uart0/uartdmacr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DMAONERR` reader - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."] pub struct DMAONERR_R(crate::FieldReader); impl DMAONERR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DMAONERR_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> DMAONERR_W<'a> { #[doc = "Field `TXDMAE` reader - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub struct TXDMAE_R(crate::FieldReader); impl TXDMAE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXDMAE_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> TXDMAE_W<'a> { #[doc = "Field `RXDMAE` reader - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub struct RXDMAE_R(crate::FieldReader); impl RXDMAE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXDMAE_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartdr.rs b/src/uart0/uartdr.rs index 79d2b5ee1..11fb25e2f 100644 --- a/src/uart0/uartdr.rs +++ b/src/uart0/uartdr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OE` reader - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it."] pub struct OE_R(crate::FieldReader); impl OE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OE_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for OE_R { #[doc = "Field `BE` reader - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received."] pub struct BE_R(crate::FieldReader); impl BE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BE_R(crate::FieldReader::new(bits)) } @@ -65,6 +67,7 @@ impl core::ops::Deref for BE_R { #[doc = "Field `PE` reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO."] pub struct PE_R(crate::FieldReader); impl PE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PE_R(crate::FieldReader::new(bits)) } @@ -79,6 +82,7 @@ impl core::ops::Deref for PE_R { #[doc = "Field `FE` reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO."] pub struct FE_R(crate::FieldReader); impl FE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FE_R(crate::FieldReader::new(bits)) } @@ -93,6 +97,7 @@ impl core::ops::Deref for FE_R { #[doc = "Field `DATA` reader - Receive (read) data character. Transmit (write) data character."] pub struct DATA_R(crate::FieldReader); impl DATA_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DATA_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartfbrd.rs b/src/uart0/uartfbrd.rs index 3ba8329c1..ba76af003 100644 --- a/src/uart0/uartfbrd.rs +++ b/src/uart0/uartfbrd.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `BAUD_DIVFRAC` reader - The fractional baud rate divisor. These bits are cleared to 0 on reset."] pub struct BAUD_DIVFRAC_R(crate::FieldReader); impl BAUD_DIVFRAC_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { BAUD_DIVFRAC_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartfr.rs b/src/uart0/uartfr.rs index 4efff7d28..f7007fa49 100644 --- a/src/uart0/uartfr.rs +++ b/src/uart0/uartfr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RI` reader - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."] pub struct RI_R(crate::FieldReader); impl RI_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RI_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for RI_R { #[doc = "Field `TXFE` reader - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."] pub struct TXFE_R(crate::FieldReader); impl TXFE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXFE_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for TXFE_R { #[doc = "Field `RXFF` reader - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."] pub struct RXFF_R(crate::FieldReader); impl RXFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXFF_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RXFF_R { #[doc = "Field `TXFF` reader - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."] pub struct TXFF_R(crate::FieldReader); impl TXFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXFF_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for TXFF_R { #[doc = "Field `RXFE` reader - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."] pub struct RXFE_R(crate::FieldReader); impl RXFE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXFE_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for RXFE_R { #[doc = "Field `BUSY` reader - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."] pub struct BUSY_R(crate::FieldReader); impl BUSY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSY_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for BUSY_R { #[doc = "Field `DCD` reader - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."] pub struct DCD_R(crate::FieldReader); impl DCD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DCD_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for DCD_R { #[doc = "Field `DSR` reader - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."] pub struct DSR_R(crate::FieldReader); impl DSR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DSR_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for DSR_R { #[doc = "Field `CTS` reader - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."] pub struct CTS_R(crate::FieldReader); impl CTS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CTS_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartibrd.rs b/src/uart0/uartibrd.rs index 491323b4a..1f0d9692b 100644 --- a/src/uart0/uartibrd.rs +++ b/src/uart0/uartibrd.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `BAUD_DIVINT` reader - The integer baud rate divisor. These bits are cleared to 0 on reset."] pub struct BAUD_DIVINT_R(crate::FieldReader); impl BAUD_DIVINT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { BAUD_DIVINT_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uarticr.rs b/src/uart0/uarticr.rs index 21aa62fe6..eedf3010a 100644 --- a/src/uart0/uarticr.rs +++ b/src/uart0/uarticr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OEIC` reader - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."] pub struct OEIC_R(crate::FieldReader); impl OEIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OEIC_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OEIC_W<'a> { #[doc = "Field `BEIC` reader - Break error interrupt clear. Clears the UARTBEINTR interrupt."] pub struct BEIC_R(crate::FieldReader); impl BEIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BEIC_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> BEIC_W<'a> { #[doc = "Field `PEIC` reader - Parity error interrupt clear. Clears the UARTPEINTR interrupt."] pub struct PEIC_R(crate::FieldReader); impl PEIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PEIC_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> PEIC_W<'a> { #[doc = "Field `FEIC` reader - Framing error interrupt clear. Clears the UARTFEINTR interrupt."] pub struct FEIC_R(crate::FieldReader); impl FEIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FEIC_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> FEIC_W<'a> { #[doc = "Field `RTIC` reader - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."] pub struct RTIC_R(crate::FieldReader); impl RTIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTIC_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> RTIC_W<'a> { #[doc = "Field `TXIC` reader - Transmit interrupt clear. Clears the UARTTXINTR interrupt."] pub struct TXIC_R(crate::FieldReader); impl TXIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXIC_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> TXIC_W<'a> { #[doc = "Field `RXIC` reader - Receive interrupt clear. Clears the UARTRXINTR interrupt."] pub struct RXIC_R(crate::FieldReader); impl RXIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXIC_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> RXIC_W<'a> { #[doc = "Field `DSRMIC` reader - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."] pub struct DSRMIC_R(crate::FieldReader); impl DSRMIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DSRMIC_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> DSRMIC_W<'a> { #[doc = "Field `DCDMIC` reader - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."] pub struct DCDMIC_R(crate::FieldReader); impl DCDMIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DCDMIC_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> DCDMIC_W<'a> { #[doc = "Field `CTSMIC` reader - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."] pub struct CTSMIC_R(crate::FieldReader); impl CTSMIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CTSMIC_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> CTSMIC_W<'a> { #[doc = "Field `RIMIC` reader - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] pub struct RIMIC_R(crate::FieldReader); impl RIMIC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RIMIC_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartifls.rs b/src/uart0/uartifls.rs index 814746682..dffdcc709 100644 --- a/src/uart0/uartifls.rs +++ b/src/uart0/uartifls.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `RXIFLSEL` reader - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."] pub struct RXIFLSEL_R(crate::FieldReader); impl RXIFLSEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RXIFLSEL_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> RXIFLSEL_W<'a> { #[doc = "Field `TXIFLSEL` reader - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] pub struct TXIFLSEL_R(crate::FieldReader); impl TXIFLSEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TXIFLSEL_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartilpr.rs b/src/uart0/uartilpr.rs index 02cb1315f..0dc3b2d76 100644 --- a/src/uart0/uartilpr.rs +++ b/src/uart0/uartilpr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ILPDVSR` reader - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] pub struct ILPDVSR_R(crate::FieldReader); impl ILPDVSR_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ILPDVSR_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartimsc.rs b/src/uart0/uartimsc.rs index 527d09592..1abb17a07 100644 --- a/src/uart0/uartimsc.rs +++ b/src/uart0/uartimsc.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OEIM` reader - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."] pub struct OEIM_R(crate::FieldReader); impl OEIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OEIM_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OEIM_W<'a> { #[doc = "Field `BEIM` reader - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."] pub struct BEIM_R(crate::FieldReader); impl BEIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BEIM_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> BEIM_W<'a> { #[doc = "Field `PEIM` reader - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."] pub struct PEIM_R(crate::FieldReader); impl PEIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PEIM_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> PEIM_W<'a> { #[doc = "Field `FEIM` reader - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."] pub struct FEIM_R(crate::FieldReader); impl FEIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FEIM_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> FEIM_W<'a> { #[doc = "Field `RTIM` reader - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."] pub struct RTIM_R(crate::FieldReader); impl RTIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTIM_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> RTIM_W<'a> { #[doc = "Field `TXIM` reader - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."] pub struct TXIM_R(crate::FieldReader); impl TXIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXIM_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> TXIM_W<'a> { #[doc = "Field `RXIM` reader - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."] pub struct RXIM_R(crate::FieldReader); impl RXIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXIM_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> RXIM_W<'a> { #[doc = "Field `DSRMIM` reader - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."] pub struct DSRMIM_R(crate::FieldReader); impl DSRMIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DSRMIM_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> DSRMIM_W<'a> { #[doc = "Field `DCDMIM` reader - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."] pub struct DCDMIM_R(crate::FieldReader); impl DCDMIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DCDMIM_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> DCDMIM_W<'a> { #[doc = "Field `CTSMIM` reader - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."] pub struct CTSMIM_R(crate::FieldReader); impl CTSMIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CTSMIM_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> CTSMIM_W<'a> { #[doc = "Field `RIMIM` reader - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] pub struct RIMIM_R(crate::FieldReader); impl RIMIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RIMIM_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartlcr_h.rs b/src/uart0/uartlcr_h.rs index 8e6f47a14..153394023 100644 --- a/src/uart0/uartlcr_h.rs +++ b/src/uart0/uartlcr_h.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SPS` reader - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."] pub struct SPS_R(crate::FieldReader); impl SPS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPS_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> SPS_W<'a> { #[doc = "Field `WLEN` reader - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."] pub struct WLEN_R(crate::FieldReader); impl WLEN_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { WLEN_R(crate::FieldReader::new(bits)) } @@ -99,6 +101,7 @@ impl<'a> WLEN_W<'a> { #[doc = "Field `FEN` reader - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."] pub struct FEN_R(crate::FieldReader); impl FEN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FEN_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> FEN_W<'a> { #[doc = "Field `STP2` reader - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."] pub struct STP2_R(crate::FieldReader); impl STP2_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STP2_R(crate::FieldReader::new(bits)) } @@ -171,6 +175,7 @@ impl<'a> STP2_W<'a> { #[doc = "Field `EPS` reader - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."] pub struct EPS_R(crate::FieldReader); impl EPS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EPS_R(crate::FieldReader::new(bits)) } @@ -207,6 +212,7 @@ impl<'a> EPS_W<'a> { #[doc = "Field `PEN` reader - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."] pub struct PEN_R(crate::FieldReader); impl PEN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PEN_R(crate::FieldReader::new(bits)) } @@ -243,6 +249,7 @@ impl<'a> PEN_W<'a> { #[doc = "Field `BRK` reader - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] pub struct BRK_R(crate::FieldReader); impl BRK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BRK_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartmis.rs b/src/uart0/uartmis.rs index 90bd9e5d3..426a0c1a0 100644 --- a/src/uart0/uartmis.rs +++ b/src/uart0/uartmis.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `OEMIS` reader - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt."] pub struct OEMIS_R(crate::FieldReader); impl OEMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OEMIS_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for OEMIS_R { #[doc = "Field `BEMIS` reader - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt."] pub struct BEMIS_R(crate::FieldReader); impl BEMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BEMIS_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for BEMIS_R { #[doc = "Field `PEMIS` reader - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt."] pub struct PEMIS_R(crate::FieldReader); impl PEMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PEMIS_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for PEMIS_R { #[doc = "Field `FEMIS` reader - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt."] pub struct FEMIS_R(crate::FieldReader); impl FEMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FEMIS_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for FEMIS_R { #[doc = "Field `RTMIS` reader - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt."] pub struct RTMIS_R(crate::FieldReader); impl RTMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTMIS_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for RTMIS_R { #[doc = "Field `TXMIS` reader - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt."] pub struct TXMIS_R(crate::FieldReader); impl TXMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXMIS_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for TXMIS_R { #[doc = "Field `RXMIS` reader - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt."] pub struct RXMIS_R(crate::FieldReader); impl RXMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXMIS_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for RXMIS_R { #[doc = "Field `DSRMMIS` reader - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt."] pub struct DSRMMIS_R(crate::FieldReader); impl DSRMMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DSRMMIS_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for DSRMMIS_R { #[doc = "Field `DCDMMIS` reader - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt."] pub struct DCDMMIS_R(crate::FieldReader); impl DCDMMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DCDMMIS_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for DCDMMIS_R { #[doc = "Field `CTSMMIS` reader - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt."] pub struct CTSMMIS_R(crate::FieldReader); impl CTSMMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CTSMMIS_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for CTSMMIS_R { #[doc = "Field `RIMMIS` reader - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt."] pub struct RIMMIS_R(crate::FieldReader); impl RIMMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RIMMIS_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartpcellid0.rs b/src/uart0/uartpcellid0.rs index 0e901dfd7..94da96c9c 100644 --- a/src/uart0/uartpcellid0.rs +++ b/src/uart0/uartpcellid0.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `UARTPCELLID0` reader - These bits read back as 0x0D"] pub struct UARTPCELLID0_R(crate::FieldReader); impl UARTPCELLID0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { UARTPCELLID0_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartpcellid1.rs b/src/uart0/uartpcellid1.rs index 1175ac7c6..6267ea647 100644 --- a/src/uart0/uartpcellid1.rs +++ b/src/uart0/uartpcellid1.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `UARTPCELLID1` reader - These bits read back as 0xF0"] pub struct UARTPCELLID1_R(crate::FieldReader); impl UARTPCELLID1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { UARTPCELLID1_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartpcellid2.rs b/src/uart0/uartpcellid2.rs index 0d02fec52..6a2defbbe 100644 --- a/src/uart0/uartpcellid2.rs +++ b/src/uart0/uartpcellid2.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `UARTPCELLID2` reader - These bits read back as 0x05"] pub struct UARTPCELLID2_R(crate::FieldReader); impl UARTPCELLID2_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { UARTPCELLID2_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartpcellid3.rs b/src/uart0/uartpcellid3.rs index 1fa29da18..86f4399f7 100644 --- a/src/uart0/uartpcellid3.rs +++ b/src/uart0/uartpcellid3.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `UARTPCELLID3` reader - These bits read back as 0xB1"] pub struct UARTPCELLID3_R(crate::FieldReader); impl UARTPCELLID3_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { UARTPCELLID3_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartperiphid0.rs b/src/uart0/uartperiphid0.rs index 7060f26b0..0b221ec1d 100644 --- a/src/uart0/uartperiphid0.rs +++ b/src/uart0/uartperiphid0.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `PARTNUMBER0` reader - These bits read back as 0x11"] pub struct PARTNUMBER0_R(crate::FieldReader); impl PARTNUMBER0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PARTNUMBER0_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartperiphid1.rs b/src/uart0/uartperiphid1.rs index dc0e9c515..f852b7374 100644 --- a/src/uart0/uartperiphid1.rs +++ b/src/uart0/uartperiphid1.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `DESIGNER0` reader - These bits read back as 0x1"] pub struct DESIGNER0_R(crate::FieldReader); impl DESIGNER0_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DESIGNER0_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for DESIGNER0_R { #[doc = "Field `PARTNUMBER1` reader - These bits read back as 0x0"] pub struct PARTNUMBER1_R(crate::FieldReader); impl PARTNUMBER1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { PARTNUMBER1_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartperiphid2.rs b/src/uart0/uartperiphid2.rs index 6c78b17ec..582f3b103 100644 --- a/src/uart0/uartperiphid2.rs +++ b/src/uart0/uartperiphid2.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `REVISION` reader - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"] pub struct REVISION_R(crate::FieldReader); impl REVISION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { REVISION_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for REVISION_R { #[doc = "Field `DESIGNER1` reader - These bits read back as 0x4"] pub struct DESIGNER1_R(crate::FieldReader); impl DESIGNER1_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DESIGNER1_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartperiphid3.rs b/src/uart0/uartperiphid3.rs index bc57bfadc..ad21270b7 100644 --- a/src/uart0/uartperiphid3.rs +++ b/src/uart0/uartperiphid3.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `CONFIGURATION` reader - These bits read back as 0x00"] pub struct CONFIGURATION_R(crate::FieldReader); impl CONFIGURATION_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CONFIGURATION_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartris.rs b/src/uart0/uartris.rs index 928539cd8..1ee5a109f 100644 --- a/src/uart0/uartris.rs +++ b/src/uart0/uartris.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `OERIS` reader - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt."] pub struct OERIS_R(crate::FieldReader); impl OERIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OERIS_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for OERIS_R { #[doc = "Field `BERIS` reader - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt."] pub struct BERIS_R(crate::FieldReader); impl BERIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BERIS_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for BERIS_R { #[doc = "Field `PERIS` reader - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt."] pub struct PERIS_R(crate::FieldReader); impl PERIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PERIS_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for PERIS_R { #[doc = "Field `FERIS` reader - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt."] pub struct FERIS_R(crate::FieldReader); impl FERIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FERIS_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for FERIS_R { #[doc = "Field `RTRIS` reader - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a"] pub struct RTRIS_R(crate::FieldReader); impl RTRIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RTRIS_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for RTRIS_R { #[doc = "Field `TXRIS` reader - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt."] pub struct TXRIS_R(crate::FieldReader); impl TXRIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXRIS_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for TXRIS_R { #[doc = "Field `RXRIS` reader - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt."] pub struct RXRIS_R(crate::FieldReader); impl RXRIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXRIS_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for RXRIS_R { #[doc = "Field `DSRRMIS` reader - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt."] pub struct DSRRMIS_R(crate::FieldReader); impl DSRRMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DSRRMIS_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for DSRRMIS_R { #[doc = "Field `DCDRMIS` reader - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt."] pub struct DCDRMIS_R(crate::FieldReader); impl DCDRMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DCDRMIS_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for DCDRMIS_R { #[doc = "Field `CTSRMIS` reader - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt."] pub struct CTSRMIS_R(crate::FieldReader); impl CTSRMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CTSRMIS_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for CTSRMIS_R { #[doc = "Field `RIRMIS` reader - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt."] pub struct RIRMIS_R(crate::FieldReader); impl RIRMIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RIRMIS_R(crate::FieldReader::new(bits)) } diff --git a/src/uart0/uartrsr.rs b/src/uart0/uartrsr.rs index 70b655c50..ff9d431ca 100644 --- a/src/uart0/uartrsr.rs +++ b/src/uart0/uartrsr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OE` reader - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."] pub struct OE_R(crate::FieldReader); impl OE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OE_W<'a> { #[doc = "Field `BE` reader - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."] pub struct BE_R(crate::FieldReader); impl BE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BE_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> BE_W<'a> { #[doc = "Field `PE` reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] pub struct PE_R(crate::FieldReader); impl PE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PE_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> PE_W<'a> { #[doc = "Field `FE` reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] pub struct FE_R(crate::FieldReader); impl FE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FE_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_dpram/ep_buffer_control.rs b/src/usbctrl_dpram/ep_buffer_control.rs index 6e8f10d60..184d4ad77 100644 --- a/src/usbctrl_dpram/ep_buffer_control.rs +++ b/src/usbctrl_dpram/ep_buffer_control.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `FULL_1` reader - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] pub struct FULL_1_R(crate::FieldReader); impl FULL_1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FULL_1_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> FULL_1_W<'a> { #[doc = "Field `LAST_1` reader - Buffer 1 is the last buffer of the transfer."] pub struct LAST_1_R(crate::FieldReader); impl LAST_1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { LAST_1_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> LAST_1_W<'a> { #[doc = "Field `PID_1` reader - The data pid of buffer 1."] pub struct PID_1_R(crate::FieldReader); impl PID_1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PID_1_R(crate::FieldReader::new(bits)) } @@ -168,6 +171,7 @@ impl From for u8 { For a non Isochronous endpoint the offset is always 64 bytes."] pub struct DOUBLE_BUFFER_ISO_OFFSET_R(crate::FieldReader); impl DOUBLE_BUFFER_ISO_OFFSET_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DOUBLE_BUFFER_ISO_OFFSET_R(crate::FieldReader::new(bits)) } @@ -251,6 +255,7 @@ impl<'a> DOUBLE_BUFFER_ISO_OFFSET_W<'a> { #[doc = "Field `AVAILABLE_1` reader - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] pub struct AVAILABLE_1_R(crate::FieldReader); impl AVAILABLE_1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { AVAILABLE_1_R(crate::FieldReader::new(bits)) } @@ -287,6 +292,7 @@ impl<'a> AVAILABLE_1_W<'a> { #[doc = "Field `LENGTH_1` reader - The length of the data in buffer 1."] pub struct LENGTH_1_R(crate::FieldReader); impl LENGTH_1_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { LENGTH_1_R(crate::FieldReader::new(bits)) } @@ -313,6 +319,7 @@ impl<'a> LENGTH_1_W<'a> { #[doc = "Field `FULL_0` reader - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] pub struct FULL_0_R(crate::FieldReader); impl FULL_0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FULL_0_R(crate::FieldReader::new(bits)) } @@ -349,6 +356,7 @@ impl<'a> FULL_0_W<'a> { #[doc = "Field `LAST_0` reader - Buffer 0 is the last buffer of the transfer."] pub struct LAST_0_R(crate::FieldReader); impl LAST_0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { LAST_0_R(crate::FieldReader::new(bits)) } @@ -385,6 +393,7 @@ impl<'a> LAST_0_W<'a> { #[doc = "Field `PID_0` reader - The data pid of buffer 0."] pub struct PID_0_R(crate::FieldReader); impl PID_0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PID_0_R(crate::FieldReader::new(bits)) } @@ -421,6 +430,7 @@ impl<'a> PID_0_W<'a> { #[doc = "Field `RESET` reader - Reset the buffer selector to buffer 0."] pub struct RESET_R(crate::FieldReader); impl RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESET_R(crate::FieldReader::new(bits)) } @@ -457,6 +467,7 @@ impl<'a> RESET_W<'a> { #[doc = "Field `STALL` reader - Reply with a stall (valid for both buffers)."] pub struct STALL_R(crate::FieldReader); impl STALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STALL_R(crate::FieldReader::new(bits)) } @@ -493,6 +504,7 @@ impl<'a> STALL_W<'a> { #[doc = "Field `AVAILABLE_0` reader - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] pub struct AVAILABLE_0_R(crate::FieldReader); impl AVAILABLE_0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { AVAILABLE_0_R(crate::FieldReader::new(bits)) } @@ -529,6 +541,7 @@ impl<'a> AVAILABLE_0_W<'a> { #[doc = "Field `LENGTH_0` reader - The length of the data in buffer 0."] pub struct LENGTH_0_R(crate::FieldReader); impl LENGTH_0_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { LENGTH_0_R(crate::FieldReader::new(bits)) } @@ -568,7 +581,8 @@ impl R { pub fn pid_1(&self) -> PID_1_R { PID_1_R::new(((self.bits >> 29) & 0x01) != 0) } - #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] + #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes."] #[inline(always)] pub fn double_buffer_iso_offset(&self) -> DOUBLE_BUFFER_ISO_OFFSET_R { DOUBLE_BUFFER_ISO_OFFSET_R::new(((self.bits >> 27) & 0x03) as u8) @@ -635,7 +649,8 @@ impl W { pub fn pid_1(&mut self) -> PID_1_W { PID_1_W { w: self } } - #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] + #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes."] #[inline(always)] pub fn double_buffer_iso_offset(&mut self) -> DOUBLE_BUFFER_ISO_OFFSET_W { DOUBLE_BUFFER_ISO_OFFSET_W { w: self } diff --git a/src/usbctrl_dpram/ep_control.rs b/src/usbctrl_dpram/ep_control.rs index b064efd5a..d91d5e7ef 100644 --- a/src/usbctrl_dpram/ep_control.rs +++ b/src/usbctrl_dpram/ep_control.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ENABLE` reader - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `DOUBLE_BUFFERED` reader - This endpoint is double buffered."] pub struct DOUBLE_BUFFERED_R(crate::FieldReader); impl DOUBLE_BUFFERED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DOUBLE_BUFFERED_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> DOUBLE_BUFFERED_W<'a> { #[doc = "Field `INTERRUPT_PER_BUFF` reader - Trigger an interrupt each time a buffer is done."] pub struct INTERRUPT_PER_BUFF_R(crate::FieldReader); impl INTERRUPT_PER_BUFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTERRUPT_PER_BUFF_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> INTERRUPT_PER_BUFF_W<'a> { #[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` reader - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] pub struct INTERRUPT_PER_DOUBLE_BUFF_R(crate::FieldReader); impl INTERRUPT_PER_DOUBLE_BUFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTERRUPT_PER_DOUBLE_BUFF_R(crate::FieldReader::new(bits)) } @@ -202,6 +206,7 @@ impl From for u8 { #[doc = "Field `ENDPOINT_TYPE` reader - "] pub struct ENDPOINT_TYPE_R(crate::FieldReader); impl ENDPOINT_TYPE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_TYPE_R(crate::FieldReader::new(bits)) } @@ -284,6 +289,7 @@ impl<'a> ENDPOINT_TYPE_W<'a> { #[doc = "Field `INTERRUPT_ON_STALL` reader - Trigger an interrupt if a STALL is sent. Intended for debug only."] pub struct INTERRUPT_ON_STALL_R(crate::FieldReader); impl INTERRUPT_ON_STALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTERRUPT_ON_STALL_R(crate::FieldReader::new(bits)) } @@ -320,6 +326,7 @@ impl<'a> INTERRUPT_ON_STALL_W<'a> { #[doc = "Field `INTERRUPT_ON_NAK` reader - Trigger an interrupt if a NAK is sent. Intended for debug only."] pub struct INTERRUPT_ON_NAK_R(crate::FieldReader); impl INTERRUPT_ON_NAK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTERRUPT_ON_NAK_R(crate::FieldReader::new(bits)) } @@ -356,6 +363,7 @@ impl<'a> INTERRUPT_ON_NAK_W<'a> { #[doc = "Field `BUFFER_ADDRESS` reader - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] pub struct BUFFER_ADDRESS_R(crate::FieldReader); impl BUFFER_ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { BUFFER_ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_dpram/setup_packet_high.rs b/src/usbctrl_dpram/setup_packet_high.rs index edb053688..dc984cb79 100644 --- a/src/usbctrl_dpram/setup_packet_high.rs +++ b/src/usbctrl_dpram/setup_packet_high.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `WLENGTH` reader - "] pub struct WLENGTH_R(crate::FieldReader); impl WLENGTH_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { WLENGTH_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> WLENGTH_W<'a> { #[doc = "Field `WINDEX` reader - "] pub struct WINDEX_R(crate::FieldReader); impl WINDEX_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { WINDEX_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_dpram/setup_packet_low.rs b/src/usbctrl_dpram/setup_packet_low.rs index 64ba0e212..adbc12847 100644 --- a/src/usbctrl_dpram/setup_packet_low.rs +++ b/src/usbctrl_dpram/setup_packet_low.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `WVALUE` reader - "] pub struct WVALUE_R(crate::FieldReader); impl WVALUE_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { WVALUE_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> WVALUE_W<'a> { #[doc = "Field `BREQUEST` reader - "] pub struct BREQUEST_R(crate::FieldReader); impl BREQUEST_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { BREQUEST_R(crate::FieldReader::new(bits)) } @@ -89,6 +91,7 @@ impl<'a> BREQUEST_W<'a> { #[doc = "Field `BMREQUESTTYPE` reader - "] pub struct BMREQUESTTYPE_R(crate::FieldReader); impl BMREQUESTTYPE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { BMREQUESTTYPE_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp.rs b/src/usbctrl_regs/addr_endp.rs index ae9a0187f..4b4f335c5 100644 --- a/src/usbctrl_regs/addr_endp.rs +++ b/src/usbctrl_regs/addr_endp.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `ENDPOINT` reader - Device endpoint to send data to. Only valid for HOST mode."] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp1.rs b/src/usbctrl_regs/addr_endp1.rs index 1b96b0f51..076de2924 100644 --- a/src/usbctrl_regs/addr_endp1.rs +++ b/src/usbctrl_regs/addr_endp1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp10.rs b/src/usbctrl_regs/addr_endp10.rs index 9a0b5ef96..b6f3a8f5b 100644 --- a/src/usbctrl_regs/addr_endp10.rs +++ b/src/usbctrl_regs/addr_endp10.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp11.rs b/src/usbctrl_regs/addr_endp11.rs index f2dd874f0..410c51c4f 100644 --- a/src/usbctrl_regs/addr_endp11.rs +++ b/src/usbctrl_regs/addr_endp11.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp12.rs b/src/usbctrl_regs/addr_endp12.rs index 197da9f30..b7b886217 100644 --- a/src/usbctrl_regs/addr_endp12.rs +++ b/src/usbctrl_regs/addr_endp12.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp13.rs b/src/usbctrl_regs/addr_endp13.rs index ad5c7a389..fa0e325f6 100644 --- a/src/usbctrl_regs/addr_endp13.rs +++ b/src/usbctrl_regs/addr_endp13.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp14.rs b/src/usbctrl_regs/addr_endp14.rs index f70f17cab..07543612d 100644 --- a/src/usbctrl_regs/addr_endp14.rs +++ b/src/usbctrl_regs/addr_endp14.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp15.rs b/src/usbctrl_regs/addr_endp15.rs index 6c5862d81..96b5f4331 100644 --- a/src/usbctrl_regs/addr_endp15.rs +++ b/src/usbctrl_regs/addr_endp15.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp2.rs b/src/usbctrl_regs/addr_endp2.rs index 55b3bea71..59716b1a3 100644 --- a/src/usbctrl_regs/addr_endp2.rs +++ b/src/usbctrl_regs/addr_endp2.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp3.rs b/src/usbctrl_regs/addr_endp3.rs index 8d224b9a3..936ddf3c1 100644 --- a/src/usbctrl_regs/addr_endp3.rs +++ b/src/usbctrl_regs/addr_endp3.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp4.rs b/src/usbctrl_regs/addr_endp4.rs index 9aabd578b..f068d8f00 100644 --- a/src/usbctrl_regs/addr_endp4.rs +++ b/src/usbctrl_regs/addr_endp4.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp5.rs b/src/usbctrl_regs/addr_endp5.rs index 6f140368b..e1978dc3a 100644 --- a/src/usbctrl_regs/addr_endp5.rs +++ b/src/usbctrl_regs/addr_endp5.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp6.rs b/src/usbctrl_regs/addr_endp6.rs index 4fd2a39e1..030d61a04 100644 --- a/src/usbctrl_regs/addr_endp6.rs +++ b/src/usbctrl_regs/addr_endp6.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp7.rs b/src/usbctrl_regs/addr_endp7.rs index 58175763f..37468f654 100644 --- a/src/usbctrl_regs/addr_endp7.rs +++ b/src/usbctrl_regs/addr_endp7.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp8.rs b/src/usbctrl_regs/addr_endp8.rs index d0317d316..80febb444 100644 --- a/src/usbctrl_regs/addr_endp8.rs +++ b/src/usbctrl_regs/addr_endp8.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/addr_endp9.rs b/src/usbctrl_regs/addr_endp9.rs index 04be02367..c3d5af5aa 100644 --- a/src/usbctrl_regs/addr_endp9.rs +++ b/src/usbctrl_regs/addr_endp9.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] pub struct INTEP_PREAMBLE_R(crate::FieldReader); impl INTEP_PREAMBLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_PREAMBLE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> INTEP_PREAMBLE_W<'a> { #[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] pub struct INTEP_DIR_R(crate::FieldReader); impl INTEP_DIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INTEP_DIR_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> INTEP_DIR_W<'a> { #[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] pub struct ENDPOINT_R(crate::FieldReader); impl ENDPOINT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ENDPOINT_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> ENDPOINT_W<'a> { #[doc = "Field `ADDRESS` reader - Device address"] pub struct ADDRESS_R(crate::FieldReader); impl ADDRESS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDRESS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/buff_cpu_should_handle.rs b/src/usbctrl_regs/buff_cpu_should_handle.rs index 5a2abb42e..c97177651 100644 --- a/src/usbctrl_regs/buff_cpu_should_handle.rs +++ b/src/usbctrl_regs/buff_cpu_should_handle.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `EP15_OUT` reader - "] pub struct EP15_OUT_R(crate::FieldReader); impl EP15_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_OUT_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for EP15_OUT_R { #[doc = "Field `EP15_IN` reader - "] pub struct EP15_IN_R(crate::FieldReader); impl EP15_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_IN_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for EP15_IN_R { #[doc = "Field `EP14_OUT` reader - "] pub struct EP14_OUT_R(crate::FieldReader); impl EP14_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_OUT_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for EP14_OUT_R { #[doc = "Field `EP14_IN` reader - "] pub struct EP14_IN_R(crate::FieldReader); impl EP14_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_IN_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for EP14_IN_R { #[doc = "Field `EP13_OUT` reader - "] pub struct EP13_OUT_R(crate::FieldReader); impl EP13_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_OUT_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for EP13_OUT_R { #[doc = "Field `EP13_IN` reader - "] pub struct EP13_IN_R(crate::FieldReader); impl EP13_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_IN_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for EP13_IN_R { #[doc = "Field `EP12_OUT` reader - "] pub struct EP12_OUT_R(crate::FieldReader); impl EP12_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_OUT_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for EP12_OUT_R { #[doc = "Field `EP12_IN` reader - "] pub struct EP12_IN_R(crate::FieldReader); impl EP12_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_IN_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for EP12_IN_R { #[doc = "Field `EP11_OUT` reader - "] pub struct EP11_OUT_R(crate::FieldReader); impl EP11_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_OUT_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for EP11_OUT_R { #[doc = "Field `EP11_IN` reader - "] pub struct EP11_IN_R(crate::FieldReader); impl EP11_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_IN_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for EP11_IN_R { #[doc = "Field `EP10_OUT` reader - "] pub struct EP10_OUT_R(crate::FieldReader); impl EP10_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_OUT_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for EP10_OUT_R { #[doc = "Field `EP10_IN` reader - "] pub struct EP10_IN_R(crate::FieldReader); impl EP10_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_IN_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for EP10_IN_R { #[doc = "Field `EP9_OUT` reader - "] pub struct EP9_OUT_R(crate::FieldReader); impl EP9_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_OUT_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for EP9_OUT_R { #[doc = "Field `EP9_IN` reader - "] pub struct EP9_IN_R(crate::FieldReader); impl EP9_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_IN_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for EP9_IN_R { #[doc = "Field `EP8_OUT` reader - "] pub struct EP8_OUT_R(crate::FieldReader); impl EP8_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_OUT_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for EP8_OUT_R { #[doc = "Field `EP8_IN` reader - "] pub struct EP8_IN_R(crate::FieldReader); impl EP8_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_IN_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for EP8_IN_R { #[doc = "Field `EP7_OUT` reader - "] pub struct EP7_OUT_R(crate::FieldReader); impl EP7_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_OUT_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for EP7_OUT_R { #[doc = "Field `EP7_IN` reader - "] pub struct EP7_IN_R(crate::FieldReader); impl EP7_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_IN_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for EP7_IN_R { #[doc = "Field `EP6_OUT` reader - "] pub struct EP6_OUT_R(crate::FieldReader); impl EP6_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_OUT_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for EP6_OUT_R { #[doc = "Field `EP6_IN` reader - "] pub struct EP6_IN_R(crate::FieldReader); impl EP6_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_IN_R(crate::FieldReader::new(bits)) } @@ -296,6 +316,7 @@ impl core::ops::Deref for EP6_IN_R { #[doc = "Field `EP5_OUT` reader - "] pub struct EP5_OUT_R(crate::FieldReader); impl EP5_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_OUT_R(crate::FieldReader::new(bits)) } @@ -310,6 +331,7 @@ impl core::ops::Deref for EP5_OUT_R { #[doc = "Field `EP5_IN` reader - "] pub struct EP5_IN_R(crate::FieldReader); impl EP5_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_IN_R(crate::FieldReader::new(bits)) } @@ -324,6 +346,7 @@ impl core::ops::Deref for EP5_IN_R { #[doc = "Field `EP4_OUT` reader - "] pub struct EP4_OUT_R(crate::FieldReader); impl EP4_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_OUT_R(crate::FieldReader::new(bits)) } @@ -338,6 +361,7 @@ impl core::ops::Deref for EP4_OUT_R { #[doc = "Field `EP4_IN` reader - "] pub struct EP4_IN_R(crate::FieldReader); impl EP4_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_IN_R(crate::FieldReader::new(bits)) } @@ -352,6 +376,7 @@ impl core::ops::Deref for EP4_IN_R { #[doc = "Field `EP3_OUT` reader - "] pub struct EP3_OUT_R(crate::FieldReader); impl EP3_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_OUT_R(crate::FieldReader::new(bits)) } @@ -366,6 +391,7 @@ impl core::ops::Deref for EP3_OUT_R { #[doc = "Field `EP3_IN` reader - "] pub struct EP3_IN_R(crate::FieldReader); impl EP3_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_IN_R(crate::FieldReader::new(bits)) } @@ -380,6 +406,7 @@ impl core::ops::Deref for EP3_IN_R { #[doc = "Field `EP2_OUT` reader - "] pub struct EP2_OUT_R(crate::FieldReader); impl EP2_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_OUT_R(crate::FieldReader::new(bits)) } @@ -394,6 +421,7 @@ impl core::ops::Deref for EP2_OUT_R { #[doc = "Field `EP2_IN` reader - "] pub struct EP2_IN_R(crate::FieldReader); impl EP2_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_IN_R(crate::FieldReader::new(bits)) } @@ -408,6 +436,7 @@ impl core::ops::Deref for EP2_IN_R { #[doc = "Field `EP1_OUT` reader - "] pub struct EP1_OUT_R(crate::FieldReader); impl EP1_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_OUT_R(crate::FieldReader::new(bits)) } @@ -422,6 +451,7 @@ impl core::ops::Deref for EP1_OUT_R { #[doc = "Field `EP1_IN` reader - "] pub struct EP1_IN_R(crate::FieldReader); impl EP1_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_IN_R(crate::FieldReader::new(bits)) } @@ -436,6 +466,7 @@ impl core::ops::Deref for EP1_IN_R { #[doc = "Field `EP0_OUT` reader - "] pub struct EP0_OUT_R(crate::FieldReader); impl EP0_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_OUT_R(crate::FieldReader::new(bits)) } @@ -450,6 +481,7 @@ impl core::ops::Deref for EP0_OUT_R { #[doc = "Field `EP0_IN` reader - "] pub struct EP0_IN_R(crate::FieldReader); impl EP0_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_IN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/buff_status.rs b/src/usbctrl_regs/buff_status.rs index fa512d43e..9f2eb22e5 100644 --- a/src/usbctrl_regs/buff_status.rs +++ b/src/usbctrl_regs/buff_status.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EP15_OUT` reader - "] pub struct EP15_OUT_R(crate::FieldReader); impl EP15_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_OUT_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> EP15_OUT_W<'a> { #[doc = "Field `EP15_IN` reader - "] pub struct EP15_IN_R(crate::FieldReader); impl EP15_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_IN_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> EP15_IN_W<'a> { #[doc = "Field `EP14_OUT` reader - "] pub struct EP14_OUT_R(crate::FieldReader); impl EP14_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_OUT_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> EP14_OUT_W<'a> { #[doc = "Field `EP14_IN` reader - "] pub struct EP14_IN_R(crate::FieldReader); impl EP14_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_IN_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> EP14_IN_W<'a> { #[doc = "Field `EP13_OUT` reader - "] pub struct EP13_OUT_R(crate::FieldReader); impl EP13_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_OUT_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> EP13_OUT_W<'a> { #[doc = "Field `EP13_IN` reader - "] pub struct EP13_IN_R(crate::FieldReader); impl EP13_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_IN_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> EP13_IN_W<'a> { #[doc = "Field `EP12_OUT` reader - "] pub struct EP12_OUT_R(crate::FieldReader); impl EP12_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_OUT_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> EP12_OUT_W<'a> { #[doc = "Field `EP12_IN` reader - "] pub struct EP12_IN_R(crate::FieldReader); impl EP12_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_IN_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> EP12_IN_W<'a> { #[doc = "Field `EP11_OUT` reader - "] pub struct EP11_OUT_R(crate::FieldReader); impl EP11_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_OUT_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> EP11_OUT_W<'a> { #[doc = "Field `EP11_IN` reader - "] pub struct EP11_IN_R(crate::FieldReader); impl EP11_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_IN_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> EP11_IN_W<'a> { #[doc = "Field `EP10_OUT` reader - "] pub struct EP10_OUT_R(crate::FieldReader); impl EP10_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_OUT_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> EP10_OUT_W<'a> { #[doc = "Field `EP10_IN` reader - "] pub struct EP10_IN_R(crate::FieldReader); impl EP10_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_IN_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> EP10_IN_W<'a> { #[doc = "Field `EP9_OUT` reader - "] pub struct EP9_OUT_R(crate::FieldReader); impl EP9_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_OUT_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> EP9_OUT_W<'a> { #[doc = "Field `EP9_IN` reader - "] pub struct EP9_IN_R(crate::FieldReader); impl EP9_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_IN_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> EP9_IN_W<'a> { #[doc = "Field `EP8_OUT` reader - "] pub struct EP8_OUT_R(crate::FieldReader); impl EP8_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_OUT_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> EP8_OUT_W<'a> { #[doc = "Field `EP8_IN` reader - "] pub struct EP8_IN_R(crate::FieldReader); impl EP8_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_IN_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> EP8_IN_W<'a> { #[doc = "Field `EP7_OUT` reader - "] pub struct EP7_OUT_R(crate::FieldReader); impl EP7_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_OUT_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> EP7_OUT_W<'a> { #[doc = "Field `EP7_IN` reader - "] pub struct EP7_IN_R(crate::FieldReader); impl EP7_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_IN_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> EP7_IN_W<'a> { #[doc = "Field `EP6_OUT` reader - "] pub struct EP6_OUT_R(crate::FieldReader); impl EP6_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_OUT_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> EP6_OUT_W<'a> { #[doc = "Field `EP6_IN` reader - "] pub struct EP6_IN_R(crate::FieldReader); impl EP6_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_IN_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> EP6_IN_W<'a> { #[doc = "Field `EP5_OUT` reader - "] pub struct EP5_OUT_R(crate::FieldReader); impl EP5_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_OUT_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> EP5_OUT_W<'a> { #[doc = "Field `EP5_IN` reader - "] pub struct EP5_IN_R(crate::FieldReader); impl EP5_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_IN_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> EP5_IN_W<'a> { #[doc = "Field `EP4_OUT` reader - "] pub struct EP4_OUT_R(crate::FieldReader); impl EP4_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_OUT_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> EP4_OUT_W<'a> { #[doc = "Field `EP4_IN` reader - "] pub struct EP4_IN_R(crate::FieldReader); impl EP4_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_IN_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> EP4_IN_W<'a> { #[doc = "Field `EP3_OUT` reader - "] pub struct EP3_OUT_R(crate::FieldReader); impl EP3_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_OUT_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> EP3_OUT_W<'a> { #[doc = "Field `EP3_IN` reader - "] pub struct EP3_IN_R(crate::FieldReader); impl EP3_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_IN_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> EP3_IN_W<'a> { #[doc = "Field `EP2_OUT` reader - "] pub struct EP2_OUT_R(crate::FieldReader); impl EP2_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_OUT_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> EP2_OUT_W<'a> { #[doc = "Field `EP2_IN` reader - "] pub struct EP2_IN_R(crate::FieldReader); impl EP2_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_IN_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> EP2_IN_W<'a> { #[doc = "Field `EP1_OUT` reader - "] pub struct EP1_OUT_R(crate::FieldReader); impl EP1_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_OUT_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> EP1_OUT_W<'a> { #[doc = "Field `EP1_IN` reader - "] pub struct EP1_IN_R(crate::FieldReader); impl EP1_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_IN_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> EP1_IN_W<'a> { #[doc = "Field `EP0_OUT` reader - "] pub struct EP0_OUT_R(crate::FieldReader); impl EP0_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_OUT_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> EP0_OUT_W<'a> { #[doc = "Field `EP0_IN` reader - "] pub struct EP0_IN_R(crate::FieldReader); impl EP0_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_IN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/ep_abort.rs b/src/usbctrl_regs/ep_abort.rs index f64a5f385..e51948039 100644 --- a/src/usbctrl_regs/ep_abort.rs +++ b/src/usbctrl_regs/ep_abort.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EP15_OUT` reader - "] pub struct EP15_OUT_R(crate::FieldReader); impl EP15_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_OUT_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> EP15_OUT_W<'a> { #[doc = "Field `EP15_IN` reader - "] pub struct EP15_IN_R(crate::FieldReader); impl EP15_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_IN_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> EP15_IN_W<'a> { #[doc = "Field `EP14_OUT` reader - "] pub struct EP14_OUT_R(crate::FieldReader); impl EP14_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_OUT_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> EP14_OUT_W<'a> { #[doc = "Field `EP14_IN` reader - "] pub struct EP14_IN_R(crate::FieldReader); impl EP14_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_IN_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> EP14_IN_W<'a> { #[doc = "Field `EP13_OUT` reader - "] pub struct EP13_OUT_R(crate::FieldReader); impl EP13_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_OUT_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> EP13_OUT_W<'a> { #[doc = "Field `EP13_IN` reader - "] pub struct EP13_IN_R(crate::FieldReader); impl EP13_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_IN_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> EP13_IN_W<'a> { #[doc = "Field `EP12_OUT` reader - "] pub struct EP12_OUT_R(crate::FieldReader); impl EP12_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_OUT_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> EP12_OUT_W<'a> { #[doc = "Field `EP12_IN` reader - "] pub struct EP12_IN_R(crate::FieldReader); impl EP12_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_IN_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> EP12_IN_W<'a> { #[doc = "Field `EP11_OUT` reader - "] pub struct EP11_OUT_R(crate::FieldReader); impl EP11_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_OUT_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> EP11_OUT_W<'a> { #[doc = "Field `EP11_IN` reader - "] pub struct EP11_IN_R(crate::FieldReader); impl EP11_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_IN_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> EP11_IN_W<'a> { #[doc = "Field `EP10_OUT` reader - "] pub struct EP10_OUT_R(crate::FieldReader); impl EP10_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_OUT_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> EP10_OUT_W<'a> { #[doc = "Field `EP10_IN` reader - "] pub struct EP10_IN_R(crate::FieldReader); impl EP10_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_IN_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> EP10_IN_W<'a> { #[doc = "Field `EP9_OUT` reader - "] pub struct EP9_OUT_R(crate::FieldReader); impl EP9_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_OUT_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> EP9_OUT_W<'a> { #[doc = "Field `EP9_IN` reader - "] pub struct EP9_IN_R(crate::FieldReader); impl EP9_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_IN_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> EP9_IN_W<'a> { #[doc = "Field `EP8_OUT` reader - "] pub struct EP8_OUT_R(crate::FieldReader); impl EP8_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_OUT_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> EP8_OUT_W<'a> { #[doc = "Field `EP8_IN` reader - "] pub struct EP8_IN_R(crate::FieldReader); impl EP8_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_IN_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> EP8_IN_W<'a> { #[doc = "Field `EP7_OUT` reader - "] pub struct EP7_OUT_R(crate::FieldReader); impl EP7_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_OUT_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> EP7_OUT_W<'a> { #[doc = "Field `EP7_IN` reader - "] pub struct EP7_IN_R(crate::FieldReader); impl EP7_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_IN_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> EP7_IN_W<'a> { #[doc = "Field `EP6_OUT` reader - "] pub struct EP6_OUT_R(crate::FieldReader); impl EP6_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_OUT_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> EP6_OUT_W<'a> { #[doc = "Field `EP6_IN` reader - "] pub struct EP6_IN_R(crate::FieldReader); impl EP6_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_IN_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> EP6_IN_W<'a> { #[doc = "Field `EP5_OUT` reader - "] pub struct EP5_OUT_R(crate::FieldReader); impl EP5_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_OUT_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> EP5_OUT_W<'a> { #[doc = "Field `EP5_IN` reader - "] pub struct EP5_IN_R(crate::FieldReader); impl EP5_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_IN_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> EP5_IN_W<'a> { #[doc = "Field `EP4_OUT` reader - "] pub struct EP4_OUT_R(crate::FieldReader); impl EP4_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_OUT_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> EP4_OUT_W<'a> { #[doc = "Field `EP4_IN` reader - "] pub struct EP4_IN_R(crate::FieldReader); impl EP4_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_IN_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> EP4_IN_W<'a> { #[doc = "Field `EP3_OUT` reader - "] pub struct EP3_OUT_R(crate::FieldReader); impl EP3_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_OUT_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> EP3_OUT_W<'a> { #[doc = "Field `EP3_IN` reader - "] pub struct EP3_IN_R(crate::FieldReader); impl EP3_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_IN_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> EP3_IN_W<'a> { #[doc = "Field `EP2_OUT` reader - "] pub struct EP2_OUT_R(crate::FieldReader); impl EP2_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_OUT_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> EP2_OUT_W<'a> { #[doc = "Field `EP2_IN` reader - "] pub struct EP2_IN_R(crate::FieldReader); impl EP2_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_IN_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> EP2_IN_W<'a> { #[doc = "Field `EP1_OUT` reader - "] pub struct EP1_OUT_R(crate::FieldReader); impl EP1_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_OUT_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> EP1_OUT_W<'a> { #[doc = "Field `EP1_IN` reader - "] pub struct EP1_IN_R(crate::FieldReader); impl EP1_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_IN_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> EP1_IN_W<'a> { #[doc = "Field `EP0_OUT` reader - "] pub struct EP0_OUT_R(crate::FieldReader); impl EP0_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_OUT_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> EP0_OUT_W<'a> { #[doc = "Field `EP0_IN` reader - "] pub struct EP0_IN_R(crate::FieldReader); impl EP0_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_IN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/ep_abort_done.rs b/src/usbctrl_regs/ep_abort_done.rs index ddfba65d3..ae3f57b56 100644 --- a/src/usbctrl_regs/ep_abort_done.rs +++ b/src/usbctrl_regs/ep_abort_done.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EP15_OUT` reader - "] pub struct EP15_OUT_R(crate::FieldReader); impl EP15_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_OUT_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> EP15_OUT_W<'a> { #[doc = "Field `EP15_IN` reader - "] pub struct EP15_IN_R(crate::FieldReader); impl EP15_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_IN_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> EP15_IN_W<'a> { #[doc = "Field `EP14_OUT` reader - "] pub struct EP14_OUT_R(crate::FieldReader); impl EP14_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_OUT_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> EP14_OUT_W<'a> { #[doc = "Field `EP14_IN` reader - "] pub struct EP14_IN_R(crate::FieldReader); impl EP14_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_IN_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> EP14_IN_W<'a> { #[doc = "Field `EP13_OUT` reader - "] pub struct EP13_OUT_R(crate::FieldReader); impl EP13_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_OUT_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> EP13_OUT_W<'a> { #[doc = "Field `EP13_IN` reader - "] pub struct EP13_IN_R(crate::FieldReader); impl EP13_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_IN_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> EP13_IN_W<'a> { #[doc = "Field `EP12_OUT` reader - "] pub struct EP12_OUT_R(crate::FieldReader); impl EP12_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_OUT_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> EP12_OUT_W<'a> { #[doc = "Field `EP12_IN` reader - "] pub struct EP12_IN_R(crate::FieldReader); impl EP12_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_IN_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> EP12_IN_W<'a> { #[doc = "Field `EP11_OUT` reader - "] pub struct EP11_OUT_R(crate::FieldReader); impl EP11_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_OUT_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> EP11_OUT_W<'a> { #[doc = "Field `EP11_IN` reader - "] pub struct EP11_IN_R(crate::FieldReader); impl EP11_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_IN_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> EP11_IN_W<'a> { #[doc = "Field `EP10_OUT` reader - "] pub struct EP10_OUT_R(crate::FieldReader); impl EP10_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_OUT_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> EP10_OUT_W<'a> { #[doc = "Field `EP10_IN` reader - "] pub struct EP10_IN_R(crate::FieldReader); impl EP10_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_IN_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> EP10_IN_W<'a> { #[doc = "Field `EP9_OUT` reader - "] pub struct EP9_OUT_R(crate::FieldReader); impl EP9_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_OUT_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> EP9_OUT_W<'a> { #[doc = "Field `EP9_IN` reader - "] pub struct EP9_IN_R(crate::FieldReader); impl EP9_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_IN_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> EP9_IN_W<'a> { #[doc = "Field `EP8_OUT` reader - "] pub struct EP8_OUT_R(crate::FieldReader); impl EP8_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_OUT_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> EP8_OUT_W<'a> { #[doc = "Field `EP8_IN` reader - "] pub struct EP8_IN_R(crate::FieldReader); impl EP8_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_IN_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> EP8_IN_W<'a> { #[doc = "Field `EP7_OUT` reader - "] pub struct EP7_OUT_R(crate::FieldReader); impl EP7_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_OUT_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> EP7_OUT_W<'a> { #[doc = "Field `EP7_IN` reader - "] pub struct EP7_IN_R(crate::FieldReader); impl EP7_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_IN_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> EP7_IN_W<'a> { #[doc = "Field `EP6_OUT` reader - "] pub struct EP6_OUT_R(crate::FieldReader); impl EP6_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_OUT_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> EP6_OUT_W<'a> { #[doc = "Field `EP6_IN` reader - "] pub struct EP6_IN_R(crate::FieldReader); impl EP6_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_IN_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> EP6_IN_W<'a> { #[doc = "Field `EP5_OUT` reader - "] pub struct EP5_OUT_R(crate::FieldReader); impl EP5_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_OUT_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> EP5_OUT_W<'a> { #[doc = "Field `EP5_IN` reader - "] pub struct EP5_IN_R(crate::FieldReader); impl EP5_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_IN_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> EP5_IN_W<'a> { #[doc = "Field `EP4_OUT` reader - "] pub struct EP4_OUT_R(crate::FieldReader); impl EP4_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_OUT_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> EP4_OUT_W<'a> { #[doc = "Field `EP4_IN` reader - "] pub struct EP4_IN_R(crate::FieldReader); impl EP4_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_IN_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> EP4_IN_W<'a> { #[doc = "Field `EP3_OUT` reader - "] pub struct EP3_OUT_R(crate::FieldReader); impl EP3_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_OUT_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> EP3_OUT_W<'a> { #[doc = "Field `EP3_IN` reader - "] pub struct EP3_IN_R(crate::FieldReader); impl EP3_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_IN_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> EP3_IN_W<'a> { #[doc = "Field `EP2_OUT` reader - "] pub struct EP2_OUT_R(crate::FieldReader); impl EP2_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_OUT_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> EP2_OUT_W<'a> { #[doc = "Field `EP2_IN` reader - "] pub struct EP2_IN_R(crate::FieldReader); impl EP2_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_IN_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> EP2_IN_W<'a> { #[doc = "Field `EP1_OUT` reader - "] pub struct EP1_OUT_R(crate::FieldReader); impl EP1_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_OUT_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> EP1_OUT_W<'a> { #[doc = "Field `EP1_IN` reader - "] pub struct EP1_IN_R(crate::FieldReader); impl EP1_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_IN_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> EP1_IN_W<'a> { #[doc = "Field `EP0_OUT` reader - "] pub struct EP0_OUT_R(crate::FieldReader); impl EP0_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_OUT_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> EP0_OUT_W<'a> { #[doc = "Field `EP0_IN` reader - "] pub struct EP0_IN_R(crate::FieldReader); impl EP0_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_IN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/ep_stall_arm.rs b/src/usbctrl_regs/ep_stall_arm.rs index 2f37fe9a4..7a75ff1d0 100644 --- a/src/usbctrl_regs/ep_stall_arm.rs +++ b/src/usbctrl_regs/ep_stall_arm.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EP0_OUT` reader - "] pub struct EP0_OUT_R(crate::FieldReader); impl EP0_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_OUT_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> EP0_OUT_W<'a> { #[doc = "Field `EP0_IN` reader - "] pub struct EP0_IN_R(crate::FieldReader); impl EP0_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_IN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/ep_status_stall_nak.rs b/src/usbctrl_regs/ep_status_stall_nak.rs index e7ef94b8b..44b500e0a 100644 --- a/src/usbctrl_regs/ep_status_stall_nak.rs +++ b/src/usbctrl_regs/ep_status_stall_nak.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EP15_OUT` reader - "] pub struct EP15_OUT_R(crate::FieldReader); impl EP15_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_OUT_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> EP15_OUT_W<'a> { #[doc = "Field `EP15_IN` reader - "] pub struct EP15_IN_R(crate::FieldReader); impl EP15_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP15_IN_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> EP15_IN_W<'a> { #[doc = "Field `EP14_OUT` reader - "] pub struct EP14_OUT_R(crate::FieldReader); impl EP14_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_OUT_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> EP14_OUT_W<'a> { #[doc = "Field `EP14_IN` reader - "] pub struct EP14_IN_R(crate::FieldReader); impl EP14_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP14_IN_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> EP14_IN_W<'a> { #[doc = "Field `EP13_OUT` reader - "] pub struct EP13_OUT_R(crate::FieldReader); impl EP13_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_OUT_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> EP13_OUT_W<'a> { #[doc = "Field `EP13_IN` reader - "] pub struct EP13_IN_R(crate::FieldReader); impl EP13_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP13_IN_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> EP13_IN_W<'a> { #[doc = "Field `EP12_OUT` reader - "] pub struct EP12_OUT_R(crate::FieldReader); impl EP12_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_OUT_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> EP12_OUT_W<'a> { #[doc = "Field `EP12_IN` reader - "] pub struct EP12_IN_R(crate::FieldReader); impl EP12_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP12_IN_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> EP12_IN_W<'a> { #[doc = "Field `EP11_OUT` reader - "] pub struct EP11_OUT_R(crate::FieldReader); impl EP11_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_OUT_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> EP11_OUT_W<'a> { #[doc = "Field `EP11_IN` reader - "] pub struct EP11_IN_R(crate::FieldReader); impl EP11_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP11_IN_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> EP11_IN_W<'a> { #[doc = "Field `EP10_OUT` reader - "] pub struct EP10_OUT_R(crate::FieldReader); impl EP10_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_OUT_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> EP10_OUT_W<'a> { #[doc = "Field `EP10_IN` reader - "] pub struct EP10_IN_R(crate::FieldReader); impl EP10_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP10_IN_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> EP10_IN_W<'a> { #[doc = "Field `EP9_OUT` reader - "] pub struct EP9_OUT_R(crate::FieldReader); impl EP9_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_OUT_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> EP9_OUT_W<'a> { #[doc = "Field `EP9_IN` reader - "] pub struct EP9_IN_R(crate::FieldReader); impl EP9_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP9_IN_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> EP9_IN_W<'a> { #[doc = "Field `EP8_OUT` reader - "] pub struct EP8_OUT_R(crate::FieldReader); impl EP8_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_OUT_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> EP8_OUT_W<'a> { #[doc = "Field `EP8_IN` reader - "] pub struct EP8_IN_R(crate::FieldReader); impl EP8_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP8_IN_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> EP8_IN_W<'a> { #[doc = "Field `EP7_OUT` reader - "] pub struct EP7_OUT_R(crate::FieldReader); impl EP7_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_OUT_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> EP7_OUT_W<'a> { #[doc = "Field `EP7_IN` reader - "] pub struct EP7_IN_R(crate::FieldReader); impl EP7_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP7_IN_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> EP7_IN_W<'a> { #[doc = "Field `EP6_OUT` reader - "] pub struct EP6_OUT_R(crate::FieldReader); impl EP6_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_OUT_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> EP6_OUT_W<'a> { #[doc = "Field `EP6_IN` reader - "] pub struct EP6_IN_R(crate::FieldReader); impl EP6_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP6_IN_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> EP6_IN_W<'a> { #[doc = "Field `EP5_OUT` reader - "] pub struct EP5_OUT_R(crate::FieldReader); impl EP5_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_OUT_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> EP5_OUT_W<'a> { #[doc = "Field `EP5_IN` reader - "] pub struct EP5_IN_R(crate::FieldReader); impl EP5_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP5_IN_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> EP5_IN_W<'a> { #[doc = "Field `EP4_OUT` reader - "] pub struct EP4_OUT_R(crate::FieldReader); impl EP4_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_OUT_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> EP4_OUT_W<'a> { #[doc = "Field `EP4_IN` reader - "] pub struct EP4_IN_R(crate::FieldReader); impl EP4_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP4_IN_R(crate::FieldReader::new(bits)) } @@ -901,6 +925,7 @@ impl<'a> EP4_IN_W<'a> { #[doc = "Field `EP3_OUT` reader - "] pub struct EP3_OUT_R(crate::FieldReader); impl EP3_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_OUT_R(crate::FieldReader::new(bits)) } @@ -937,6 +962,7 @@ impl<'a> EP3_OUT_W<'a> { #[doc = "Field `EP3_IN` reader - "] pub struct EP3_IN_R(crate::FieldReader); impl EP3_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP3_IN_R(crate::FieldReader::new(bits)) } @@ -973,6 +999,7 @@ impl<'a> EP3_IN_W<'a> { #[doc = "Field `EP2_OUT` reader - "] pub struct EP2_OUT_R(crate::FieldReader); impl EP2_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_OUT_R(crate::FieldReader::new(bits)) } @@ -1009,6 +1036,7 @@ impl<'a> EP2_OUT_W<'a> { #[doc = "Field `EP2_IN` reader - "] pub struct EP2_IN_R(crate::FieldReader); impl EP2_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP2_IN_R(crate::FieldReader::new(bits)) } @@ -1045,6 +1073,7 @@ impl<'a> EP2_IN_W<'a> { #[doc = "Field `EP1_OUT` reader - "] pub struct EP1_OUT_R(crate::FieldReader); impl EP1_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_OUT_R(crate::FieldReader::new(bits)) } @@ -1081,6 +1110,7 @@ impl<'a> EP1_OUT_W<'a> { #[doc = "Field `EP1_IN` reader - "] pub struct EP1_IN_R(crate::FieldReader); impl EP1_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP1_IN_R(crate::FieldReader::new(bits)) } @@ -1117,6 +1147,7 @@ impl<'a> EP1_IN_W<'a> { #[doc = "Field `EP0_OUT` reader - "] pub struct EP0_OUT_R(crate::FieldReader); impl EP0_OUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_OUT_R(crate::FieldReader::new(bits)) } @@ -1153,6 +1184,7 @@ impl<'a> EP0_OUT_W<'a> { #[doc = "Field `EP0_IN` reader - "] pub struct EP0_IN_R(crate::FieldReader); impl EP0_IN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_IN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/int_ep_ctrl.rs b/src/usbctrl_regs/int_ep_ctrl.rs index d9f714e6e..fef73aa68 100644 --- a/src/usbctrl_regs/int_ep_ctrl.rs +++ b/src/usbctrl_regs/int_ep_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `INT_EP_ACTIVE` reader - Host: Enable interrupt endpoint 1 -> 15"] pub struct INT_EP_ACTIVE_R(crate::FieldReader); impl INT_EP_ACTIVE_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { INT_EP_ACTIVE_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/inte.rs b/src/usbctrl_regs/inte.rs index 4bd239647..46a56be5c 100644 --- a/src/usbctrl_regs/inte.rs +++ b/src/usbctrl_regs/inte.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] pub struct EP_STALL_NAK_R(crate::FieldReader); impl EP_STALL_NAK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP_STALL_NAK_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> EP_STALL_NAK_W<'a> { #[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] pub struct ABORT_DONE_R(crate::FieldReader); impl ABORT_DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABORT_DONE_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> ABORT_DONE_W<'a> { #[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] pub struct DEV_SOF_R(crate::FieldReader); impl DEV_SOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_SOF_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> DEV_SOF_W<'a> { #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub struct SETUP_REQ_R(crate::FieldReader); impl SETUP_REQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SETUP_REQ_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> SETUP_REQ_W<'a> { #[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] pub struct DEV_RESUME_FROM_HOST_R(crate::FieldReader); impl DEV_RESUME_FROM_HOST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_RESUME_FROM_HOST_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> DEV_RESUME_FROM_HOST_W<'a> { #[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub struct DEV_SUSPEND_R(crate::FieldReader); impl DEV_SUSPEND_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_SUSPEND_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> DEV_SUSPEND_W<'a> { #[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] pub struct DEV_CONN_DIS_R(crate::FieldReader); impl DEV_CONN_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_CONN_DIS_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> DEV_CONN_DIS_W<'a> { #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub struct BUS_RESET_R(crate::FieldReader); impl BUS_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUS_RESET_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> BUS_RESET_W<'a> { #[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] pub struct VBUS_DETECT_R(crate::FieldReader); impl VBUS_DETECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_DETECT_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> VBUS_DETECT_W<'a> { #[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] pub struct STALL_R(crate::FieldReader); impl STALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STALL_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> STALL_W<'a> { #[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] pub struct ERROR_CRC_R(crate::FieldReader); impl ERROR_CRC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_CRC_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> ERROR_CRC_W<'a> { #[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] pub struct ERROR_BIT_STUFF_R(crate::FieldReader); impl ERROR_BIT_STUFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_BIT_STUFF_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> ERROR_BIT_STUFF_W<'a> { #[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] pub struct ERROR_RX_OVERFLOW_R(crate::FieldReader); impl ERROR_RX_OVERFLOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_RX_OVERFLOW_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> ERROR_RX_OVERFLOW_W<'a> { #[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] pub struct ERROR_RX_TIMEOUT_R(crate::FieldReader); impl ERROR_RX_TIMEOUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_RX_TIMEOUT_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> ERROR_RX_TIMEOUT_W<'a> { #[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] pub struct ERROR_DATA_SEQ_R(crate::FieldReader); impl ERROR_DATA_SEQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_DATA_SEQ_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> ERROR_DATA_SEQ_W<'a> { #[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] pub struct BUFF_STATUS_R(crate::FieldReader); impl BUFF_STATUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUFF_STATUS_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> BUFF_STATUS_W<'a> { #[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] pub struct TRANS_COMPLETE_R(crate::FieldReader); impl TRANS_COMPLETE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TRANS_COMPLETE_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> TRANS_COMPLETE_W<'a> { #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub struct HOST_SOF_R(crate::FieldReader); impl HOST_SOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_SOF_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> HOST_SOF_W<'a> { #[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] pub struct HOST_RESUME_R(crate::FieldReader); impl HOST_RESUME_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_RESUME_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> HOST_RESUME_W<'a> { #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub struct HOST_CONN_DIS_R(crate::FieldReader); impl HOST_CONN_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_CONN_DIS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/intf.rs b/src/usbctrl_regs/intf.rs index 7dbc56ce9..a09e9557d 100644 --- a/src/usbctrl_regs/intf.rs +++ b/src/usbctrl_regs/intf.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] pub struct EP_STALL_NAK_R(crate::FieldReader); impl EP_STALL_NAK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP_STALL_NAK_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> EP_STALL_NAK_W<'a> { #[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] pub struct ABORT_DONE_R(crate::FieldReader); impl ABORT_DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABORT_DONE_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> ABORT_DONE_W<'a> { #[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] pub struct DEV_SOF_R(crate::FieldReader); impl DEV_SOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_SOF_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> DEV_SOF_W<'a> { #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub struct SETUP_REQ_R(crate::FieldReader); impl SETUP_REQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SETUP_REQ_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> SETUP_REQ_W<'a> { #[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] pub struct DEV_RESUME_FROM_HOST_R(crate::FieldReader); impl DEV_RESUME_FROM_HOST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_RESUME_FROM_HOST_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> DEV_RESUME_FROM_HOST_W<'a> { #[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub struct DEV_SUSPEND_R(crate::FieldReader); impl DEV_SUSPEND_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_SUSPEND_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> DEV_SUSPEND_W<'a> { #[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] pub struct DEV_CONN_DIS_R(crate::FieldReader); impl DEV_CONN_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_CONN_DIS_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> DEV_CONN_DIS_W<'a> { #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub struct BUS_RESET_R(crate::FieldReader); impl BUS_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUS_RESET_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> BUS_RESET_W<'a> { #[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] pub struct VBUS_DETECT_R(crate::FieldReader); impl VBUS_DETECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_DETECT_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> VBUS_DETECT_W<'a> { #[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] pub struct STALL_R(crate::FieldReader); impl STALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STALL_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> STALL_W<'a> { #[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] pub struct ERROR_CRC_R(crate::FieldReader); impl ERROR_CRC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_CRC_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> ERROR_CRC_W<'a> { #[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] pub struct ERROR_BIT_STUFF_R(crate::FieldReader); impl ERROR_BIT_STUFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_BIT_STUFF_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> ERROR_BIT_STUFF_W<'a> { #[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] pub struct ERROR_RX_OVERFLOW_R(crate::FieldReader); impl ERROR_RX_OVERFLOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_RX_OVERFLOW_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> ERROR_RX_OVERFLOW_W<'a> { #[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] pub struct ERROR_RX_TIMEOUT_R(crate::FieldReader); impl ERROR_RX_TIMEOUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_RX_TIMEOUT_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> ERROR_RX_TIMEOUT_W<'a> { #[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] pub struct ERROR_DATA_SEQ_R(crate::FieldReader); impl ERROR_DATA_SEQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_DATA_SEQ_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> ERROR_DATA_SEQ_W<'a> { #[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] pub struct BUFF_STATUS_R(crate::FieldReader); impl BUFF_STATUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUFF_STATUS_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> BUFF_STATUS_W<'a> { #[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] pub struct TRANS_COMPLETE_R(crate::FieldReader); impl TRANS_COMPLETE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TRANS_COMPLETE_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> TRANS_COMPLETE_W<'a> { #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub struct HOST_SOF_R(crate::FieldReader); impl HOST_SOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_SOF_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> HOST_SOF_W<'a> { #[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] pub struct HOST_RESUME_R(crate::FieldReader); impl HOST_RESUME_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_RESUME_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> HOST_RESUME_W<'a> { #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub struct HOST_CONN_DIS_R(crate::FieldReader); impl HOST_CONN_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_CONN_DIS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/intr.rs b/src/usbctrl_regs/intr.rs index 8f31dfb3d..34ea7f6fc 100644 --- a/src/usbctrl_regs/intr.rs +++ b/src/usbctrl_regs/intr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] pub struct EP_STALL_NAK_R(crate::FieldReader); impl EP_STALL_NAK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP_STALL_NAK_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for EP_STALL_NAK_R { #[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] pub struct ABORT_DONE_R(crate::FieldReader); impl ABORT_DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABORT_DONE_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for ABORT_DONE_R { #[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] pub struct DEV_SOF_R(crate::FieldReader); impl DEV_SOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_SOF_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for DEV_SOF_R { #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub struct SETUP_REQ_R(crate::FieldReader); impl SETUP_REQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SETUP_REQ_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for SETUP_REQ_R { #[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] pub struct DEV_RESUME_FROM_HOST_R(crate::FieldReader); impl DEV_RESUME_FROM_HOST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_RESUME_FROM_HOST_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for DEV_RESUME_FROM_HOST_R { #[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub struct DEV_SUSPEND_R(crate::FieldReader); impl DEV_SUSPEND_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_SUSPEND_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for DEV_SUSPEND_R { #[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] pub struct DEV_CONN_DIS_R(crate::FieldReader); impl DEV_CONN_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_CONN_DIS_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for DEV_CONN_DIS_R { #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub struct BUS_RESET_R(crate::FieldReader); impl BUS_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUS_RESET_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for BUS_RESET_R { #[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] pub struct VBUS_DETECT_R(crate::FieldReader); impl VBUS_DETECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_DETECT_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for VBUS_DETECT_R { #[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] pub struct STALL_R(crate::FieldReader); impl STALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STALL_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for STALL_R { #[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] pub struct ERROR_CRC_R(crate::FieldReader); impl ERROR_CRC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_CRC_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for ERROR_CRC_R { #[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] pub struct ERROR_BIT_STUFF_R(crate::FieldReader); impl ERROR_BIT_STUFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_BIT_STUFF_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for ERROR_BIT_STUFF_R { #[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] pub struct ERROR_RX_OVERFLOW_R(crate::FieldReader); impl ERROR_RX_OVERFLOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_RX_OVERFLOW_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for ERROR_RX_OVERFLOW_R { #[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] pub struct ERROR_RX_TIMEOUT_R(crate::FieldReader); impl ERROR_RX_TIMEOUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_RX_TIMEOUT_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for ERROR_RX_TIMEOUT_R { #[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] pub struct ERROR_DATA_SEQ_R(crate::FieldReader); impl ERROR_DATA_SEQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_DATA_SEQ_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for ERROR_DATA_SEQ_R { #[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] pub struct BUFF_STATUS_R(crate::FieldReader); impl BUFF_STATUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUFF_STATUS_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for BUFF_STATUS_R { #[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] pub struct TRANS_COMPLETE_R(crate::FieldReader); impl TRANS_COMPLETE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TRANS_COMPLETE_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for TRANS_COMPLETE_R { #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub struct HOST_SOF_R(crate::FieldReader); impl HOST_SOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_SOF_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for HOST_SOF_R { #[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] pub struct HOST_RESUME_R(crate::FieldReader); impl HOST_RESUME_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_RESUME_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for HOST_RESUME_R { #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub struct HOST_CONN_DIS_R(crate::FieldReader); impl HOST_CONN_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_CONN_DIS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/ints.rs b/src/usbctrl_regs/ints.rs index 7160388b6..cec8c4e31 100644 --- a/src/usbctrl_regs/ints.rs +++ b/src/usbctrl_regs/ints.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] pub struct EP_STALL_NAK_R(crate::FieldReader); impl EP_STALL_NAK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP_STALL_NAK_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for EP_STALL_NAK_R { #[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] pub struct ABORT_DONE_R(crate::FieldReader); impl ABORT_DONE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ABORT_DONE_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for ABORT_DONE_R { #[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] pub struct DEV_SOF_R(crate::FieldReader); impl DEV_SOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_SOF_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for DEV_SOF_R { #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub struct SETUP_REQ_R(crate::FieldReader); impl SETUP_REQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SETUP_REQ_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for SETUP_REQ_R { #[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] pub struct DEV_RESUME_FROM_HOST_R(crate::FieldReader); impl DEV_RESUME_FROM_HOST_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_RESUME_FROM_HOST_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for DEV_RESUME_FROM_HOST_R { #[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub struct DEV_SUSPEND_R(crate::FieldReader); impl DEV_SUSPEND_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_SUSPEND_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for DEV_SUSPEND_R { #[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] pub struct DEV_CONN_DIS_R(crate::FieldReader); impl DEV_CONN_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DEV_CONN_DIS_R(crate::FieldReader::new(bits)) } @@ -114,6 +121,7 @@ impl core::ops::Deref for DEV_CONN_DIS_R { #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub struct BUS_RESET_R(crate::FieldReader); impl BUS_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUS_RESET_R(crate::FieldReader::new(bits)) } @@ -128,6 +136,7 @@ impl core::ops::Deref for BUS_RESET_R { #[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] pub struct VBUS_DETECT_R(crate::FieldReader); impl VBUS_DETECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_DETECT_R(crate::FieldReader::new(bits)) } @@ -142,6 +151,7 @@ impl core::ops::Deref for VBUS_DETECT_R { #[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] pub struct STALL_R(crate::FieldReader); impl STALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STALL_R(crate::FieldReader::new(bits)) } @@ -156,6 +166,7 @@ impl core::ops::Deref for STALL_R { #[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] pub struct ERROR_CRC_R(crate::FieldReader); impl ERROR_CRC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_CRC_R(crate::FieldReader::new(bits)) } @@ -170,6 +181,7 @@ impl core::ops::Deref for ERROR_CRC_R { #[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] pub struct ERROR_BIT_STUFF_R(crate::FieldReader); impl ERROR_BIT_STUFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_BIT_STUFF_R(crate::FieldReader::new(bits)) } @@ -184,6 +196,7 @@ impl core::ops::Deref for ERROR_BIT_STUFF_R { #[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] pub struct ERROR_RX_OVERFLOW_R(crate::FieldReader); impl ERROR_RX_OVERFLOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_RX_OVERFLOW_R(crate::FieldReader::new(bits)) } @@ -198,6 +211,7 @@ impl core::ops::Deref for ERROR_RX_OVERFLOW_R { #[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] pub struct ERROR_RX_TIMEOUT_R(crate::FieldReader); impl ERROR_RX_TIMEOUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_RX_TIMEOUT_R(crate::FieldReader::new(bits)) } @@ -212,6 +226,7 @@ impl core::ops::Deref for ERROR_RX_TIMEOUT_R { #[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] pub struct ERROR_DATA_SEQ_R(crate::FieldReader); impl ERROR_DATA_SEQ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERROR_DATA_SEQ_R(crate::FieldReader::new(bits)) } @@ -226,6 +241,7 @@ impl core::ops::Deref for ERROR_DATA_SEQ_R { #[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] pub struct BUFF_STATUS_R(crate::FieldReader); impl BUFF_STATUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUFF_STATUS_R(crate::FieldReader::new(bits)) } @@ -240,6 +256,7 @@ impl core::ops::Deref for BUFF_STATUS_R { #[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] pub struct TRANS_COMPLETE_R(crate::FieldReader); impl TRANS_COMPLETE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TRANS_COMPLETE_R(crate::FieldReader::new(bits)) } @@ -254,6 +271,7 @@ impl core::ops::Deref for TRANS_COMPLETE_R { #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub struct HOST_SOF_R(crate::FieldReader); impl HOST_SOF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_SOF_R(crate::FieldReader::new(bits)) } @@ -268,6 +286,7 @@ impl core::ops::Deref for HOST_SOF_R { #[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] pub struct HOST_RESUME_R(crate::FieldReader); impl HOST_RESUME_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_RESUME_R(crate::FieldReader::new(bits)) } @@ -282,6 +301,7 @@ impl core::ops::Deref for HOST_RESUME_R { #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub struct HOST_CONN_DIS_R(crate::FieldReader); impl HOST_CONN_DIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_CONN_DIS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/main_ctrl.rs b/src/usbctrl_regs/main_ctrl.rs index 677073a03..cc19ab206 100644 --- a/src/usbctrl_regs/main_ctrl.rs +++ b/src/usbctrl_regs/main_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SIM_TIMING` reader - Reduced timings for simulation"] pub struct SIM_TIMING_R(crate::FieldReader); impl SIM_TIMING_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SIM_TIMING_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> SIM_TIMING_W<'a> { #[doc = "Field `HOST_NDEVICE` reader - Device mode = 0, Host mode = 1"] pub struct HOST_NDEVICE_R(crate::FieldReader); impl HOST_NDEVICE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HOST_NDEVICE_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> HOST_NDEVICE_W<'a> { #[doc = "Field `CONTROLLER_EN` reader - Enable controller"] pub struct CONTROLLER_EN_R(crate::FieldReader); impl CONTROLLER_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CONTROLLER_EN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/nak_poll.rs b/src/usbctrl_regs/nak_poll.rs index 5e807192c..cdeee73bc 100644 --- a/src/usbctrl_regs/nak_poll.rs +++ b/src/usbctrl_regs/nak_poll.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DELAY_FS` reader - NAK polling interval for a full speed device"] pub struct DELAY_FS_R(crate::FieldReader); impl DELAY_FS_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { DELAY_FS_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> DELAY_FS_W<'a> { #[doc = "Field `DELAY_LS` reader - NAK polling interval for a low speed device"] pub struct DELAY_LS_R(crate::FieldReader); impl DELAY_LS_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { DELAY_LS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/sie_ctrl.rs b/src/usbctrl_regs/sie_ctrl.rs index c24bc97b1..274ccd2af 100644 --- a/src/usbctrl_regs/sie_ctrl.rs +++ b/src/usbctrl_regs/sie_ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `EP0_INT_STALL` reader - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] pub struct EP0_INT_STALL_R(crate::FieldReader); impl EP0_INT_STALL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_INT_STALL_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> EP0_INT_STALL_W<'a> { #[doc = "Field `EP0_DOUBLE_BUF` reader - Device: EP0 single buffered = 0, double buffered = 1"] pub struct EP0_DOUBLE_BUF_R(crate::FieldReader); impl EP0_DOUBLE_BUF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_DOUBLE_BUF_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> EP0_DOUBLE_BUF_W<'a> { #[doc = "Field `EP0_INT_1BUF` reader - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"] pub struct EP0_INT_1BUF_R(crate::FieldReader); impl EP0_INT_1BUF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_INT_1BUF_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> EP0_INT_1BUF_W<'a> { #[doc = "Field `EP0_INT_2BUF` reader - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"] pub struct EP0_INT_2BUF_R(crate::FieldReader); impl EP0_INT_2BUF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_INT_2BUF_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> EP0_INT_2BUF_W<'a> { #[doc = "Field `EP0_INT_NAK` reader - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"] pub struct EP0_INT_NAK_R(crate::FieldReader); impl EP0_INT_NAK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EP0_INT_NAK_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> EP0_INT_NAK_W<'a> { #[doc = "Field `DIRECT_EN` reader - Direct bus drive enable"] pub struct DIRECT_EN_R(crate::FieldReader); impl DIRECT_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DIRECT_EN_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> DIRECT_EN_W<'a> { #[doc = "Field `DIRECT_DP` reader - Direct control of DP"] pub struct DIRECT_DP_R(crate::FieldReader); impl DIRECT_DP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DIRECT_DP_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> DIRECT_DP_W<'a> { #[doc = "Field `DIRECT_DM` reader - Direct control of DM"] pub struct DIRECT_DM_R(crate::FieldReader); impl DIRECT_DM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DIRECT_DM_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> DIRECT_DM_W<'a> { #[doc = "Field `TRANSCEIVER_PD` reader - Power down bus transceiver"] pub struct TRANSCEIVER_PD_R(crate::FieldReader); impl TRANSCEIVER_PD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TRANSCEIVER_PD_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> TRANSCEIVER_PD_W<'a> { #[doc = "Field `RPU_OPT` reader - Device: Pull-up strength (0=1K2, 1=2k3)"] pub struct RPU_OPT_R(crate::FieldReader); impl RPU_OPT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RPU_OPT_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> RPU_OPT_W<'a> { #[doc = "Field `PULLUP_EN` reader - Device: Enable pull up resistor"] pub struct PULLUP_EN_R(crate::FieldReader); impl PULLUP_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PULLUP_EN_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> PULLUP_EN_W<'a> { #[doc = "Field `PULLDOWN_EN` reader - Host: Enable pull down resistors"] pub struct PULLDOWN_EN_R(crate::FieldReader); impl PULLDOWN_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PULLDOWN_EN_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> PULLDOWN_EN_W<'a> { #[doc = "Field `RESET_BUS` reader - Host: Reset bus"] pub struct RESET_BUS_R(crate::FieldReader); impl RESET_BUS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESET_BUS_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> RESET_BUS_W<'a> { #[doc = "Field `RESUME` reader - Device: Remote wakeup. Device can initiate its own resume after suspend."] pub struct RESUME_R(crate::FieldReader); impl RESUME_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESUME_R(crate::FieldReader::new(bits)) } @@ -541,6 +555,7 @@ impl<'a> RESUME_W<'a> { #[doc = "Field `VBUS_EN` reader - Host: Enable VBUS"] pub struct VBUS_EN_R(crate::FieldReader); impl VBUS_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_EN_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> VBUS_EN_W<'a> { #[doc = "Field `KEEP_ALIVE_EN` reader - Host: Enable keep alive packet (for low speed bus)"] pub struct KEEP_ALIVE_EN_R(crate::FieldReader); impl KEEP_ALIVE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { KEEP_ALIVE_EN_R(crate::FieldReader::new(bits)) } @@ -613,6 +629,7 @@ impl<'a> KEEP_ALIVE_EN_W<'a> { #[doc = "Field `SOF_EN` reader - Host: Enable SOF generation (for full speed bus)"] pub struct SOF_EN_R(crate::FieldReader); impl SOF_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SOF_EN_R(crate::FieldReader::new(bits)) } @@ -649,6 +666,7 @@ impl<'a> SOF_EN_W<'a> { #[doc = "Field `SOF_SYNC` reader - Host: Delay packet(s) until after SOF"] pub struct SOF_SYNC_R(crate::FieldReader); impl SOF_SYNC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SOF_SYNC_R(crate::FieldReader::new(bits)) } @@ -685,6 +703,7 @@ impl<'a> SOF_SYNC_W<'a> { #[doc = "Field `PREAMBLE_EN` reader - Host: Preable enable for LS device on FS hub"] pub struct PREAMBLE_EN_R(crate::FieldReader); impl PREAMBLE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PREAMBLE_EN_R(crate::FieldReader::new(bits)) } @@ -721,6 +740,7 @@ impl<'a> PREAMBLE_EN_W<'a> { #[doc = "Field `STOP_TRANS` reader - Host: Stop transaction"] pub struct STOP_TRANS_R(crate::FieldReader); impl STOP_TRANS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STOP_TRANS_R(crate::FieldReader::new(bits)) } @@ -757,6 +777,7 @@ impl<'a> STOP_TRANS_W<'a> { #[doc = "Field `RECEIVE_DATA` reader - Host: Receive transaction (IN to host)"] pub struct RECEIVE_DATA_R(crate::FieldReader); impl RECEIVE_DATA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RECEIVE_DATA_R(crate::FieldReader::new(bits)) } @@ -793,6 +814,7 @@ impl<'a> RECEIVE_DATA_W<'a> { #[doc = "Field `SEND_DATA` reader - Host: Send transaction (OUT from host)"] pub struct SEND_DATA_R(crate::FieldReader); impl SEND_DATA_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SEND_DATA_R(crate::FieldReader::new(bits)) } @@ -829,6 +851,7 @@ impl<'a> SEND_DATA_W<'a> { #[doc = "Field `SEND_SETUP` reader - Host: Send Setup packet"] pub struct SEND_SETUP_R(crate::FieldReader); impl SEND_SETUP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SEND_SETUP_R(crate::FieldReader::new(bits)) } @@ -865,6 +888,7 @@ impl<'a> SEND_SETUP_W<'a> { #[doc = "Field `START_TRANS` reader - Host: Start transaction"] pub struct START_TRANS_R(crate::FieldReader); impl START_TRANS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { START_TRANS_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/sie_status.rs b/src/usbctrl_regs/sie_status.rs index ee05dd4ee..3ac8b39e1 100644 --- a/src/usbctrl_regs/sie_status.rs +++ b/src/usbctrl_regs/sie_status.rs @@ -45,6 +45,7 @@ impl From> for W { * An IN packet from the device has the wrong data PID"] pub struct DATA_SEQ_ERROR_R(crate::FieldReader); impl DATA_SEQ_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DATA_SEQ_ERROR_R(crate::FieldReader::new(bits)) } @@ -89,6 +90,7 @@ impl<'a> DATA_SEQ_ERROR_W<'a> { #[doc = "Field `ACK_REC` reader - ACK received. Raised by both host and device."] pub struct ACK_REC_R(crate::FieldReader); impl ACK_REC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ACK_REC_R(crate::FieldReader::new(bits)) } @@ -125,6 +127,7 @@ impl<'a> ACK_REC_W<'a> { #[doc = "Field `STALL_REC` reader - Host: STALL received"] pub struct STALL_REC_R(crate::FieldReader); impl STALL_REC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STALL_REC_R(crate::FieldReader::new(bits)) } @@ -161,6 +164,7 @@ impl<'a> STALL_REC_W<'a> { #[doc = "Field `NAK_REC` reader - Host: NAK received"] pub struct NAK_REC_R(crate::FieldReader); impl NAK_REC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { NAK_REC_R(crate::FieldReader::new(bits)) } @@ -197,6 +201,7 @@ impl<'a> NAK_REC_W<'a> { #[doc = "Field `RX_TIMEOUT` reader - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."] pub struct RX_TIMEOUT_R(crate::FieldReader); impl RX_TIMEOUT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_TIMEOUT_R(crate::FieldReader::new(bits)) } @@ -233,6 +238,7 @@ impl<'a> RX_TIMEOUT_W<'a> { #[doc = "Field `RX_OVERFLOW` reader - RX overflow is raised by the Serial RX engine if the incoming data is too fast."] pub struct RX_OVERFLOW_R(crate::FieldReader); impl RX_OVERFLOW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_OVERFLOW_R(crate::FieldReader::new(bits)) } @@ -269,6 +275,7 @@ impl<'a> RX_OVERFLOW_W<'a> { #[doc = "Field `BIT_STUFF_ERROR` reader - Bit Stuff Error. Raised by the Serial RX engine."] pub struct BIT_STUFF_ERROR_R(crate::FieldReader); impl BIT_STUFF_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BIT_STUFF_ERROR_R(crate::FieldReader::new(bits)) } @@ -305,6 +312,7 @@ impl<'a> BIT_STUFF_ERROR_W<'a> { #[doc = "Field `CRC_ERROR` reader - CRC Error. Raised by the Serial RX engine."] pub struct CRC_ERROR_R(crate::FieldReader); impl CRC_ERROR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CRC_ERROR_R(crate::FieldReader::new(bits)) } @@ -341,6 +349,7 @@ impl<'a> CRC_ERROR_W<'a> { #[doc = "Field `BUS_RESET` reader - Device: bus reset received"] pub struct BUS_RESET_R(crate::FieldReader); impl BUS_RESET_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUS_RESET_R(crate::FieldReader::new(bits)) } @@ -385,6 +394,7 @@ impl<'a> BUS_RESET_W<'a> { * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] pub struct TRANS_COMPLETE_R(crate::FieldReader); impl TRANS_COMPLETE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TRANS_COMPLETE_R(crate::FieldReader::new(bits)) } @@ -429,6 +439,7 @@ impl<'a> TRANS_COMPLETE_W<'a> { #[doc = "Field `SETUP_REC` reader - Device: Setup packet received"] pub struct SETUP_REC_R(crate::FieldReader); impl SETUP_REC_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SETUP_REC_R(crate::FieldReader::new(bits)) } @@ -465,6 +476,7 @@ impl<'a> SETUP_REC_W<'a> { #[doc = "Field `CONNECTED` reader - Device: connected"] pub struct CONNECTED_R(crate::FieldReader); impl CONNECTED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { CONNECTED_R(crate::FieldReader::new(bits)) } @@ -501,6 +513,7 @@ impl<'a> CONNECTED_W<'a> { #[doc = "Field `RESUME` reader - Host: Device has initiated a remote resume. Device: host has initiated a resume."] pub struct RESUME_R(crate::FieldReader); impl RESUME_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RESUME_R(crate::FieldReader::new(bits)) } @@ -537,6 +550,7 @@ impl<'a> RESUME_W<'a> { #[doc = "Field `VBUS_OVER_CURR` reader - VBUS over current detected"] pub struct VBUS_OVER_CURR_R(crate::FieldReader); impl VBUS_OVER_CURR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_OVER_CURR_R(crate::FieldReader::new(bits)) } @@ -551,6 +565,7 @@ impl core::ops::Deref for VBUS_OVER_CURR_R { #[doc = "Field `SPEED` reader - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] pub struct SPEED_R(crate::FieldReader); impl SPEED_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SPEED_R(crate::FieldReader::new(bits)) } @@ -577,6 +592,7 @@ impl<'a> SPEED_W<'a> { #[doc = "Field `SUSPENDED` reader - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled."] pub struct SUSPENDED_R(crate::FieldReader); impl SUSPENDED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SUSPENDED_R(crate::FieldReader::new(bits)) } @@ -634,6 +650,7 @@ impl From for u8 { #[doc = "Field `LINE_STATE` reader - USB bus line state"] pub struct LINE_STATE_R(crate::FieldReader); impl LINE_STATE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { LINE_STATE_R(crate::FieldReader::new(bits)) } @@ -679,6 +696,7 @@ impl core::ops::Deref for LINE_STATE_R { #[doc = "Field `VBUS_DETECTED` reader - Device: VBUS Detected"] pub struct VBUS_DETECTED_R(crate::FieldReader); impl VBUS_DETECTED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_DETECTED_R(crate::FieldReader::new(bits)) } @@ -691,7 +709,15 @@ impl core::ops::Deref for VBUS_DETECTED_R { } } impl R { - #[doc = "Bit 31 - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] + #[doc = "Bit 31 - Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID"] #[inline(always)] pub fn data_seq_error(&self) -> DATA_SEQ_ERROR_R { DATA_SEQ_ERROR_R::new(((self.bits >> 31) & 0x01) != 0) @@ -736,7 +762,15 @@ impl R { pub fn bus_reset(&self) -> BUS_RESET_R { BUS_RESET_R::new(((self.bits >> 19) & 0x01) != 0) } - #[doc = "Bit 18 - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] + #[doc = "Bit 18 - Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] #[inline(always)] pub fn trans_complete(&self) -> TRANS_COMPLETE_R { TRANS_COMPLETE_R::new(((self.bits >> 18) & 0x01) != 0) @@ -783,7 +817,15 @@ impl R { } } impl W { - #[doc = "Bit 31 - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] + #[doc = "Bit 31 - Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID"] #[inline(always)] pub fn data_seq_error(&mut self) -> DATA_SEQ_ERROR_W { DATA_SEQ_ERROR_W { w: self } @@ -828,7 +870,15 @@ impl W { pub fn bus_reset(&mut self) -> BUS_RESET_W { BUS_RESET_W { w: self } } - #[doc = "Bit 18 - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] + #[doc = "Bit 18 - Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] #[inline(always)] pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { TRANS_COMPLETE_W { w: self } diff --git a/src/usbctrl_regs/sof_rd.rs b/src/usbctrl_regs/sof_rd.rs index 66c9aac2c..61e831db2 100644 --- a/src/usbctrl_regs/sof_rd.rs +++ b/src/usbctrl_regs/sof_rd.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `COUNT` reader - "] pub struct COUNT_R(crate::FieldReader); impl COUNT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { COUNT_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/usb_muxing.rs b/src/usbctrl_regs/usb_muxing.rs index 8da71c258..68afb5388 100644 --- a/src/usbctrl_regs/usb_muxing.rs +++ b/src/usbctrl_regs/usb_muxing.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SOFTCON` reader - "] pub struct SOFTCON_R(crate::FieldReader); impl SOFTCON_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SOFTCON_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> SOFTCON_W<'a> { #[doc = "Field `TO_DIGITAL_PAD` reader - "] pub struct TO_DIGITAL_PAD_R(crate::FieldReader); impl TO_DIGITAL_PAD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TO_DIGITAL_PAD_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> TO_DIGITAL_PAD_W<'a> { #[doc = "Field `TO_EXTPHY` reader - "] pub struct TO_EXTPHY_R(crate::FieldReader); impl TO_EXTPHY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TO_EXTPHY_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> TO_EXTPHY_W<'a> { #[doc = "Field `TO_PHY` reader - "] pub struct TO_PHY_R(crate::FieldReader); impl TO_PHY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TO_PHY_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/usb_pwr.rs b/src/usbctrl_regs/usb_pwr.rs index 6f4543aee..827693ee0 100644 --- a/src/usbctrl_regs/usb_pwr.rs +++ b/src/usbctrl_regs/usb_pwr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `OVERCURR_DETECT_EN` reader - "] pub struct OVERCURR_DETECT_EN_R(crate::FieldReader); impl OVERCURR_DETECT_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVERCURR_DETECT_EN_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> OVERCURR_DETECT_EN_W<'a> { #[doc = "Field `OVERCURR_DETECT` reader - "] pub struct OVERCURR_DETECT_R(crate::FieldReader); impl OVERCURR_DETECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { OVERCURR_DETECT_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> OVERCURR_DETECT_W<'a> { #[doc = "Field `VBUS_DETECT_OVERRIDE_EN` reader - "] pub struct VBUS_DETECT_OVERRIDE_EN_R(crate::FieldReader); impl VBUS_DETECT_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_DETECT_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> VBUS_DETECT_OVERRIDE_EN_W<'a> { #[doc = "Field `VBUS_DETECT` reader - "] pub struct VBUS_DETECT_R(crate::FieldReader); impl VBUS_DETECT_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_DETECT_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> VBUS_DETECT_W<'a> { #[doc = "Field `VBUS_EN_OVERRIDE_EN` reader - "] pub struct VBUS_EN_OVERRIDE_EN_R(crate::FieldReader); impl VBUS_EN_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_EN_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> VBUS_EN_OVERRIDE_EN_W<'a> { #[doc = "Field `VBUS_EN` reader - "] pub struct VBUS_EN_R(crate::FieldReader); impl VBUS_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { VBUS_EN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/usbphy_direct.rs b/src/usbctrl_regs/usbphy_direct.rs index b5fac510c..6c9e4435b 100644 --- a/src/usbctrl_regs/usbphy_direct.rs +++ b/src/usbctrl_regs/usbphy_direct.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DM_OVV` reader - DM over voltage"] pub struct DM_OVV_R(crate::FieldReader); impl DM_OVV_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DM_OVV_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for DM_OVV_R { #[doc = "Field `DP_OVV` reader - DP over voltage"] pub struct DP_OVV_R(crate::FieldReader); impl DP_OVV_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DP_OVV_R(crate::FieldReader::new(bits)) } @@ -65,6 +67,7 @@ impl core::ops::Deref for DP_OVV_R { #[doc = "Field `DM_OVCN` reader - DM overcurrent"] pub struct DM_OVCN_R(crate::FieldReader); impl DM_OVCN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DM_OVCN_R(crate::FieldReader::new(bits)) } @@ -79,6 +82,7 @@ impl core::ops::Deref for DM_OVCN_R { #[doc = "Field `DP_OVCN` reader - DP overcurrent"] pub struct DP_OVCN_R(crate::FieldReader); impl DP_OVCN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DP_OVCN_R(crate::FieldReader::new(bits)) } @@ -93,6 +97,7 @@ impl core::ops::Deref for DP_OVCN_R { #[doc = "Field `RX_DM` reader - DPM pin state"] pub struct RX_DM_R(crate::FieldReader); impl RX_DM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_DM_R(crate::FieldReader::new(bits)) } @@ -107,6 +112,7 @@ impl core::ops::Deref for RX_DM_R { #[doc = "Field `RX_DP` reader - DPP pin state"] pub struct RX_DP_R(crate::FieldReader); impl RX_DP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_DP_R(crate::FieldReader::new(bits)) } @@ -121,6 +127,7 @@ impl core::ops::Deref for RX_DP_R { #[doc = "Field `RX_DD` reader - Differential RX"] pub struct RX_DD_R(crate::FieldReader); impl RX_DD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_DD_R(crate::FieldReader::new(bits)) } @@ -136,6 +143,7 @@ impl core::ops::Deref for RX_DD_R { TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] pub struct TX_DIFFMODE_R(crate::FieldReader); impl TX_DIFFMODE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DIFFMODE_R(crate::FieldReader::new(bits)) } @@ -174,6 +182,7 @@ impl<'a> TX_DIFFMODE_W<'a> { TX_FSSLEW=1: Full speed slew rate"] pub struct TX_FSSLEW_R(crate::FieldReader); impl TX_FSSLEW_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_FSSLEW_R(crate::FieldReader::new(bits)) } @@ -211,6 +220,7 @@ impl<'a> TX_FSSLEW_W<'a> { #[doc = "Field `TX_PD` reader - TX power down override (if override enable is set). 1 = powered down."] pub struct TX_PD_R(crate::FieldReader); impl TX_PD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_PD_R(crate::FieldReader::new(bits)) } @@ -247,6 +257,7 @@ impl<'a> TX_PD_W<'a> { #[doc = "Field `RX_PD` reader - RX power down override (if override enable is set). 1 = powered down."] pub struct RX_PD_R(crate::FieldReader); impl RX_PD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_PD_R(crate::FieldReader::new(bits)) } @@ -284,6 +295,7 @@ impl<'a> RX_PD_W<'a> { TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] pub struct TX_DM_R(crate::FieldReader); impl TX_DM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DM_R(crate::FieldReader::new(bits)) } @@ -322,6 +334,7 @@ impl<'a> TX_DM_W<'a> { If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] pub struct TX_DP_R(crate::FieldReader); impl TX_DP_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DP_R(crate::FieldReader::new(bits)) } @@ -360,6 +373,7 @@ impl<'a> TX_DP_W<'a> { If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] pub struct TX_DM_OE_R(crate::FieldReader); impl TX_DM_OE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DM_OE_R(crate::FieldReader::new(bits)) } @@ -398,6 +412,7 @@ impl<'a> TX_DM_OE_W<'a> { If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] pub struct TX_DP_OE_R(crate::FieldReader); impl TX_DP_OE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DP_OE_R(crate::FieldReader::new(bits)) } @@ -435,6 +450,7 @@ impl<'a> TX_DP_OE_W<'a> { #[doc = "Field `DM_PULLDN_EN` reader - DM pull down enable"] pub struct DM_PULLDN_EN_R(crate::FieldReader); impl DM_PULLDN_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DM_PULLDN_EN_R(crate::FieldReader::new(bits)) } @@ -471,6 +487,7 @@ impl<'a> DM_PULLDN_EN_W<'a> { #[doc = "Field `DM_PULLUP_EN` reader - DM pull up enable"] pub struct DM_PULLUP_EN_R(crate::FieldReader); impl DM_PULLUP_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DM_PULLUP_EN_R(crate::FieldReader::new(bits)) } @@ -507,6 +524,7 @@ impl<'a> DM_PULLUP_EN_W<'a> { #[doc = "Field `DM_PULLUP_HISEL` reader - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] pub struct DM_PULLUP_HISEL_R(crate::FieldReader); impl DM_PULLUP_HISEL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DM_PULLUP_HISEL_R(crate::FieldReader::new(bits)) } @@ -543,6 +561,7 @@ impl<'a> DM_PULLUP_HISEL_W<'a> { #[doc = "Field `DP_PULLDN_EN` reader - DP pull down enable"] pub struct DP_PULLDN_EN_R(crate::FieldReader); impl DP_PULLDN_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DP_PULLDN_EN_R(crate::FieldReader::new(bits)) } @@ -579,6 +598,7 @@ impl<'a> DP_PULLDN_EN_W<'a> { #[doc = "Field `DP_PULLUP_EN` reader - DP pull up enable"] pub struct DP_PULLUP_EN_R(crate::FieldReader); impl DP_PULLUP_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DP_PULLUP_EN_R(crate::FieldReader::new(bits)) } @@ -615,6 +635,7 @@ impl<'a> DP_PULLUP_EN_W<'a> { #[doc = "Field `DP_PULLUP_HISEL` reader - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] pub struct DP_PULLUP_HISEL_R(crate::FieldReader); impl DP_PULLUP_HISEL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DP_PULLUP_HISEL_R(crate::FieldReader::new(bits)) } @@ -684,12 +705,14 @@ impl R { pub fn rx_dd(&self) -> RX_DD_R { RX_DD_R::new(((self.bits >> 16) & 0x01) != 0) } - #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] + #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] #[inline(always)] pub fn tx_diffmode(&self) -> TX_DIFFMODE_R { TX_DIFFMODE_R::new(((self.bits >> 15) & 0x01) != 0) } - #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] + #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate + TX_FSSLEW=1: Full speed slew rate"] #[inline(always)] pub fn tx_fsslew(&self) -> TX_FSSLEW_R { TX_FSSLEW_R::new(((self.bits >> 14) & 0x01) != 0) @@ -704,22 +727,26 @@ impl R { pub fn rx_pd(&self) -> RX_PD_R { RX_PD_R::new(((self.bits >> 12) & 0x01) != 0) } - #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] + #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] #[inline(always)] pub fn tx_dm(&self) -> TX_DM_R { TX_DM_R::new(((self.bits >> 11) & 0x01) != 0) } - #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] + #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] #[inline(always)] pub fn tx_dp(&self) -> TX_DP_R { TX_DP_R::new(((self.bits >> 10) & 0x01) != 0) } - #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] + #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] #[inline(always)] pub fn tx_dm_oe(&self) -> TX_DM_OE_R { TX_DM_OE_R::new(((self.bits >> 9) & 0x01) != 0) } - #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] + #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] #[inline(always)] pub fn tx_dp_oe(&self) -> TX_DP_OE_R { TX_DP_OE_R::new(((self.bits >> 8) & 0x01) != 0) @@ -756,12 +783,14 @@ impl R { } } impl W { - #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] + #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] #[inline(always)] pub fn tx_diffmode(&mut self) -> TX_DIFFMODE_W { TX_DIFFMODE_W { w: self } } - #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] + #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate + TX_FSSLEW=1: Full speed slew rate"] #[inline(always)] pub fn tx_fsslew(&mut self) -> TX_FSSLEW_W { TX_FSSLEW_W { w: self } @@ -776,22 +805,26 @@ impl W { pub fn rx_pd(&mut self) -> RX_PD_W { RX_PD_W { w: self } } - #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] + #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] #[inline(always)] pub fn tx_dm(&mut self) -> TX_DM_W { TX_DM_W { w: self } } - #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] + #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] #[inline(always)] pub fn tx_dp(&mut self) -> TX_DP_W { TX_DP_W { w: self } } - #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] + #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] #[inline(always)] pub fn tx_dm_oe(&mut self) -> TX_DM_OE_W { TX_DM_OE_W { w: self } } - #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] + #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] #[inline(always)] pub fn tx_dp_oe(&mut self) -> TX_DP_OE_W { TX_DP_OE_W { w: self } diff --git a/src/usbctrl_regs/usbphy_direct_override.rs b/src/usbctrl_regs/usbphy_direct_override.rs index 0e46fb35e..dfdb8a3ae 100644 --- a/src/usbctrl_regs/usbphy_direct_override.rs +++ b/src/usbctrl_regs/usbphy_direct_override.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TX_DIFFMODE_OVERRIDE_EN` reader - "] pub struct TX_DIFFMODE_OVERRIDE_EN_R(crate::FieldReader); impl TX_DIFFMODE_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DIFFMODE_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> TX_DIFFMODE_OVERRIDE_EN_W<'a> { #[doc = "Field `DM_PULLUP_OVERRIDE_EN` reader - "] pub struct DM_PULLUP_OVERRIDE_EN_R(crate::FieldReader); impl DM_PULLUP_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DM_PULLUP_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> DM_PULLUP_OVERRIDE_EN_W<'a> { #[doc = "Field `TX_FSSLEW_OVERRIDE_EN` reader - "] pub struct TX_FSSLEW_OVERRIDE_EN_R(crate::FieldReader); impl TX_FSSLEW_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_FSSLEW_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> TX_FSSLEW_OVERRIDE_EN_W<'a> { #[doc = "Field `TX_PD_OVERRIDE_EN` reader - "] pub struct TX_PD_OVERRIDE_EN_R(crate::FieldReader); impl TX_PD_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_PD_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> TX_PD_OVERRIDE_EN_W<'a> { #[doc = "Field `RX_PD_OVERRIDE_EN` reader - "] pub struct RX_PD_OVERRIDE_EN_R(crate::FieldReader); impl RX_PD_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RX_PD_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> RX_PD_OVERRIDE_EN_W<'a> { #[doc = "Field `TX_DM_OVERRIDE_EN` reader - "] pub struct TX_DM_OVERRIDE_EN_R(crate::FieldReader); impl TX_DM_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DM_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -253,6 +259,7 @@ impl<'a> TX_DM_OVERRIDE_EN_W<'a> { #[doc = "Field `TX_DP_OVERRIDE_EN` reader - "] pub struct TX_DP_OVERRIDE_EN_R(crate::FieldReader); impl TX_DP_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DP_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -289,6 +296,7 @@ impl<'a> TX_DP_OVERRIDE_EN_W<'a> { #[doc = "Field `TX_DM_OE_OVERRIDE_EN` reader - "] pub struct TX_DM_OE_OVERRIDE_EN_R(crate::FieldReader); impl TX_DM_OE_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DM_OE_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -325,6 +333,7 @@ impl<'a> TX_DM_OE_OVERRIDE_EN_W<'a> { #[doc = "Field `TX_DP_OE_OVERRIDE_EN` reader - "] pub struct TX_DP_OE_OVERRIDE_EN_R(crate::FieldReader); impl TX_DP_OE_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TX_DP_OE_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -361,6 +370,7 @@ impl<'a> TX_DP_OE_OVERRIDE_EN_W<'a> { #[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` reader - "] pub struct DM_PULLDN_EN_OVERRIDE_EN_R(crate::FieldReader); impl DM_PULLDN_EN_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DM_PULLDN_EN_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -397,6 +407,7 @@ impl<'a> DM_PULLDN_EN_OVERRIDE_EN_W<'a> { #[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` reader - "] pub struct DP_PULLDN_EN_OVERRIDE_EN_R(crate::FieldReader); impl DP_PULLDN_EN_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DP_PULLDN_EN_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -433,6 +444,7 @@ impl<'a> DP_PULLDN_EN_OVERRIDE_EN_W<'a> { #[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` reader - "] pub struct DP_PULLUP_EN_OVERRIDE_EN_R(crate::FieldReader); impl DP_PULLUP_EN_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DP_PULLUP_EN_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -469,6 +481,7 @@ impl<'a> DP_PULLUP_EN_OVERRIDE_EN_W<'a> { #[doc = "Field `DM_PULLUP_HISEL_OVERRIDE_EN` reader - "] pub struct DM_PULLUP_HISEL_OVERRIDE_EN_R(crate::FieldReader); impl DM_PULLUP_HISEL_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DM_PULLUP_HISEL_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } @@ -505,6 +518,7 @@ impl<'a> DM_PULLUP_HISEL_OVERRIDE_EN_W<'a> { #[doc = "Field `DP_PULLUP_HISEL_OVERRIDE_EN` reader - "] pub struct DP_PULLUP_HISEL_OVERRIDE_EN_R(crate::FieldReader); impl DP_PULLUP_HISEL_OVERRIDE_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DP_PULLUP_HISEL_OVERRIDE_EN_R(crate::FieldReader::new(bits)) } diff --git a/src/usbctrl_regs/usbphy_trim.rs b/src/usbctrl_regs/usbphy_trim.rs index d2f755374..bb435d87d 100644 --- a/src/usbctrl_regs/usbphy_trim.rs +++ b/src/usbctrl_regs/usbphy_trim.rs @@ -39,6 +39,7 @@ impl From> for W { Experimental data suggests that the reset value will work, but this register allows adjustment if required"] pub struct DM_PULLDN_TRIM_R(crate::FieldReader); impl DM_PULLDN_TRIM_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DM_PULLDN_TRIM_R(crate::FieldReader::new(bits)) } @@ -69,6 +70,7 @@ impl<'a> DM_PULLDN_TRIM_W<'a> { Experimental data suggests that the reset value will work, but this register allows adjustment if required"] pub struct DP_PULLDN_TRIM_R(crate::FieldReader); impl DP_PULLDN_TRIM_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DP_PULLDN_TRIM_R(crate::FieldReader::new(bits)) } @@ -95,24 +97,32 @@ impl<'a> DP_PULLDN_TRIM_W<'a> { } } impl R { - #[doc = "Bits 8:12 - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[doc = "Bits 8:12 - Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] pub fn dm_pulldn_trim(&self) -> DM_PULLDN_TRIM_R { DM_PULLDN_TRIM_R::new(((self.bits >> 8) & 0x1f) as u8) } - #[doc = "Bits 0:4 - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[doc = "Bits 0:4 - Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] pub fn dp_pulldn_trim(&self) -> DP_PULLDN_TRIM_R { DP_PULLDN_TRIM_R::new((self.bits & 0x1f) as u8) } } impl W { - #[doc = "Bits 8:12 - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[doc = "Bits 8:12 - Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] pub fn dm_pulldn_trim(&mut self) -> DM_PULLDN_TRIM_W { DM_PULLDN_TRIM_W { w: self } } - #[doc = "Bits 0:4 - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[doc = "Bits 0:4 - Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] pub fn dp_pulldn_trim(&mut self) -> DP_PULLDN_TRIM_W { DP_PULLDN_TRIM_W { w: self } diff --git a/src/vreg_and_chip_reset/bod.rs b/src/vreg_and_chip_reset/bod.rs index 21c33e1cc..40975a5f9 100644 --- a/src/vreg_and_chip_reset/bod.rs +++ b/src/vreg_and_chip_reset/bod.rs @@ -53,6 +53,7 @@ impl From> for W { 1111 - 1.118V"] pub struct VSEL_R(crate::FieldReader); impl VSEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { VSEL_R(crate::FieldReader::new(bits)) } @@ -96,6 +97,7 @@ impl<'a> VSEL_W<'a> { 0=not enabled, 1=enabled"] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -131,24 +133,58 @@ impl<'a> EN_W<'a> { } } impl R { - #[doc = "Bits 4:7 - threshold select 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V"] + #[doc = "Bits 4:7 - threshold select + 0000 - 0.473V + 0001 - 0.516V + 0010 - 0.559V + 0011 - 0.602V + 0100 - 0.645V + 0101 - 0.688V + 0110 - 0.731V + 0111 - 0.774V + 1000 - 0.817V + 1001 - 0.860V (default) + 1010 - 0.903V + 1011 - 0.946V + 1100 - 0.989V + 1101 - 1.032V + 1110 - 1.075V + 1111 - 1.118V"] #[inline(always)] pub fn vsel(&self) -> VSEL_R { VSEL_R::new(((self.bits >> 4) & 0x0f) as u8) } - #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] + #[doc = "Bit 0 - enable + 0=not enabled, 1=enabled"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bits 4:7 - threshold select 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V"] + #[doc = "Bits 4:7 - threshold select + 0000 - 0.473V + 0001 - 0.516V + 0010 - 0.559V + 0011 - 0.602V + 0100 - 0.645V + 0101 - 0.688V + 0110 - 0.731V + 0111 - 0.774V + 1000 - 0.817V + 1001 - 0.860V (default) + 1010 - 0.903V + 1011 - 0.946V + 1100 - 0.989V + 1101 - 1.032V + 1110 - 1.075V + 1111 - 1.118V"] #[inline(always)] pub fn vsel(&mut self) -> VSEL_W { VSEL_W { w: self } } - #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] + #[doc = "Bit 0 - enable + 0=not enabled, 1=enabled"] #[inline(always)] pub fn en(&mut self) -> EN_W { EN_W { w: self } diff --git a/src/vreg_and_chip_reset/chip_reset.rs b/src/vreg_and_chip_reset/chip_reset.rs index 61cb1a41e..a5617f88f 100644 --- a/src/vreg_and_chip_reset/chip_reset.rs +++ b/src/vreg_and_chip_reset/chip_reset.rs @@ -39,6 +39,7 @@ impl From> for W { In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] pub struct PSM_RESTART_FLAG_R(crate::FieldReader); impl PSM_RESTART_FLAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PSM_RESTART_FLAG_R(crate::FieldReader::new(bits)) } @@ -77,6 +78,7 @@ impl<'a> PSM_RESTART_FLAG_W<'a> { #[doc = "Field `HAD_PSM_RESTART` reader - Last reset was from the debug port"] pub struct HAD_PSM_RESTART_R(crate::FieldReader); impl HAD_PSM_RESTART_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HAD_PSM_RESTART_R(crate::FieldReader::new(bits)) } @@ -91,6 +93,7 @@ impl core::ops::Deref for HAD_PSM_RESTART_R { #[doc = "Field `HAD_RUN` reader - Last reset was from the RUN pin"] pub struct HAD_RUN_R(crate::FieldReader); impl HAD_RUN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HAD_RUN_R(crate::FieldReader::new(bits)) } @@ -105,6 +108,7 @@ impl core::ops::Deref for HAD_RUN_R { #[doc = "Field `HAD_POR` reader - Last reset was from the power-on reset or brown-out detection blocks"] pub struct HAD_POR_R(crate::FieldReader); impl HAD_POR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HAD_POR_R(crate::FieldReader::new(bits)) } @@ -117,7 +121,9 @@ impl core::ops::Deref for HAD_POR_R { } } impl R { - #[doc = "Bit 24 - This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] + #[doc = "Bit 24 - This is set by psm_restart from the debugger. + Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. + In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] #[inline(always)] pub fn psm_restart_flag(&self) -> PSM_RESTART_FLAG_R { PSM_RESTART_FLAG_R::new(((self.bits >> 24) & 0x01) != 0) @@ -139,7 +145,9 @@ impl R { } } impl W { - #[doc = "Bit 24 - This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] + #[doc = "Bit 24 - This is set by psm_restart from the debugger. + Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. + In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] #[inline(always)] pub fn psm_restart_flag(&mut self) -> PSM_RESTART_FLAG_W { PSM_RESTART_FLAG_W { w: self } diff --git a/src/vreg_and_chip_reset/vreg.rs b/src/vreg_and_chip_reset/vreg.rs index 4b40db8ee..263abbe85 100644 --- a/src/vreg_and_chip_reset/vreg.rs +++ b/src/vreg_and_chip_reset/vreg.rs @@ -38,6 +38,7 @@ impl From> for W { 0=not in regulation, 1=in regulation"] pub struct ROK_R(crate::FieldReader); impl ROK_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ROK_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl core::ops::Deref for ROK_R { 1111 - 1.30V"] pub struct VSEL_R(crate::FieldReader); impl VSEL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { VSEL_R(crate::FieldReader::new(bits)) } @@ -101,6 +103,7 @@ impl<'a> VSEL_W<'a> { 0=not in high impedance mode, 1=in high impedance mode"] pub struct HIZ_R(crate::FieldReader); impl HIZ_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { HIZ_R(crate::FieldReader::new(bits)) } @@ -139,6 +142,7 @@ impl<'a> HIZ_W<'a> { 0=not enabled, 1=enabled"] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -174,39 +178,66 @@ impl<'a> EN_W<'a> { } } impl R { - #[doc = "Bit 12 - regulation status 0=not in regulation, 1=in regulation"] + #[doc = "Bit 12 - regulation status + 0=not in regulation, 1=in regulation"] #[inline(always)] pub fn rok(&self) -> ROK_R { ROK_R::new(((self.bits >> 12) & 0x01) != 0) } - #[doc = "Bits 4:7 - output voltage select 0000 to 0101 - 0.80V 0110 - 0.85V 0111 - 0.90V 1000 - 0.95V 1001 - 1.00V 1010 - 1.05V 1011 - 1.10V (default) 1100 - 1.15V 1101 - 1.20V 1110 - 1.25V 1111 - 1.30V"] + #[doc = "Bits 4:7 - output voltage select + 0000 to 0101 - 0.80V + 0110 - 0.85V + 0111 - 0.90V + 1000 - 0.95V + 1001 - 1.00V + 1010 - 1.05V + 1011 - 1.10V (default) + 1100 - 1.15V + 1101 - 1.20V + 1110 - 1.25V + 1111 - 1.30V"] #[inline(always)] pub fn vsel(&self) -> VSEL_R { VSEL_R::new(((self.bits >> 4) & 0x0f) as u8) } - #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] + #[doc = "Bit 1 - high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode"] #[inline(always)] pub fn hiz(&self) -> HIZ_R { HIZ_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] + #[doc = "Bit 0 - enable + 0=not enabled, 1=enabled"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bits 4:7 - output voltage select 0000 to 0101 - 0.80V 0110 - 0.85V 0111 - 0.90V 1000 - 0.95V 1001 - 1.00V 1010 - 1.05V 1011 - 1.10V (default) 1100 - 1.15V 1101 - 1.20V 1110 - 1.25V 1111 - 1.30V"] + #[doc = "Bits 4:7 - output voltage select + 0000 to 0101 - 0.80V + 0110 - 0.85V + 0111 - 0.90V + 1000 - 0.95V + 1001 - 1.00V + 1010 - 1.05V + 1011 - 1.10V (default) + 1100 - 1.15V + 1101 - 1.20V + 1110 - 1.25V + 1111 - 1.30V"] #[inline(always)] pub fn vsel(&mut self) -> VSEL_W { VSEL_W { w: self } } - #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] + #[doc = "Bit 1 - high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode"] #[inline(always)] pub fn hiz(&mut self) -> HIZ_W { HIZ_W { w: self } } - #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] + #[doc = "Bit 0 - enable + 0=not enabled, 1=enabled"] #[inline(always)] pub fn en(&mut self) -> EN_W { EN_W { w: self } diff --git a/src/watchdog/ctrl.rs b/src/watchdog/ctrl.rs index 836f3bd04..20f47161b 100644 --- a/src/watchdog/ctrl.rs +++ b/src/watchdog/ctrl.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TRIGGER` reader - Trigger a watchdog reset"] pub struct TRIGGER_R(crate::FieldReader); impl TRIGGER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TRIGGER_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> TRIGGER_W<'a> { #[doc = "Field `ENABLE` reader - When not enabled the watchdog timer is paused"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `PAUSE_DBG1` reader - Pause the watchdog timer when processor 1 is in debug mode"] pub struct PAUSE_DBG1_R(crate::FieldReader); impl PAUSE_DBG1_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PAUSE_DBG1_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> PAUSE_DBG1_W<'a> { #[doc = "Field `PAUSE_DBG0` reader - Pause the watchdog timer when processor 0 is in debug mode"] pub struct PAUSE_DBG0_R(crate::FieldReader); impl PAUSE_DBG0_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PAUSE_DBG0_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> PAUSE_DBG0_W<'a> { #[doc = "Field `PAUSE_JTAG` reader - Pause the watchdog timer when JTAG is accessing the bus fabric"] pub struct PAUSE_JTAG_R(crate::FieldReader); impl PAUSE_JTAG_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { PAUSE_JTAG_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> PAUSE_JTAG_W<'a> { #[doc = "Field `TIME` reader - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered"] pub struct TIME_R(crate::FieldReader); impl TIME_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { TIME_R(crate::FieldReader::new(bits)) } diff --git a/src/watchdog/reason.rs b/src/watchdog/reason.rs index 76a873669..6f4202b2d 100644 --- a/src/watchdog/reason.rs +++ b/src/watchdog/reason.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `FORCE` reader - "] pub struct FORCE_R(crate::FieldReader); impl FORCE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FORCE_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for FORCE_R { #[doc = "Field `TIMER` reader - "] pub struct TIMER_R(crate::FieldReader); impl TIMER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TIMER_R(crate::FieldReader::new(bits)) } diff --git a/src/watchdog/tick.rs b/src/watchdog/tick.rs index 77b638783..ad48305de 100644 --- a/src/watchdog/tick.rs +++ b/src/watchdog/tick.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `COUNT` reader - Count down timer: the remaining number clk_tick cycles before the next tick is generated."] pub struct COUNT_R(crate::FieldReader); impl COUNT_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { COUNT_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for COUNT_R { #[doc = "Field `RUNNING` reader - Is the tick generator running?"] pub struct RUNNING_R(crate::FieldReader); impl RUNNING_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RUNNING_R(crate::FieldReader::new(bits)) } @@ -65,6 +67,7 @@ impl core::ops::Deref for RUNNING_R { #[doc = "Field `ENABLE` reader - start / stop tick generation"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -101,6 +104,7 @@ impl<'a> ENABLE_W<'a> { #[doc = "Field `CYCLES` reader - Total number of clk_tick cycles before the next tick."] pub struct CYCLES_R(crate::FieldReader); impl CYCLES_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { CYCLES_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ctrl/ctrl.rs b/src/xip_ctrl/ctrl.rs index 74dd996bd..84af3f31d 100644 --- a/src/xip_ctrl/ctrl.rs +++ b/src/xip_ctrl/ctrl.rs @@ -42,6 +42,7 @@ impl From> for W { the cache is powered down."] pub struct POWER_DOWN_R(crate::FieldReader); impl POWER_DOWN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { POWER_DOWN_R(crate::FieldReader::new(bits)) } @@ -86,6 +87,7 @@ impl<'a> POWER_DOWN_W<'a> { as usual."] pub struct ERR_BADWRITE_R(crate::FieldReader); impl ERR_BADWRITE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ERR_BADWRITE_R(crate::FieldReader::new(bits)) } @@ -131,6 +133,7 @@ impl<'a> ERR_BADWRITE_W<'a> { cache data RAM, and will produce a bus error response."] pub struct EN_R(crate::FieldReader); impl EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { EN_R(crate::FieldReader::new(bits)) } @@ -171,34 +174,62 @@ impl<'a> EN_W<'a> { } } impl R { - #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down."] + #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, + but can not be accessed. This reduces static power dissipation. + Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot + be enabled when powered down. + Cache-as-SRAM accesses will produce a bus error response when + the cache is powered down."] #[inline(always)] pub fn power_down(&self) -> POWER_DOWN_R { POWER_DOWN_R::new(((self.bits >> 3) & 0x01) != 0) } - #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual."] + #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) + will produce a bus fault. When 0, these writes are silently ignored. + In either case, writes to the 0x0 alias will deallocate on tag match, + as usual."] #[inline(always)] pub fn err_badwrite(&self) -> ERR_BADWRITE_R { ERR_BADWRITE_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response."] + #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses + will go straight to the flash, without querying the cache. When enabled, + cacheable XIP accesses will query the cache, and the flash will + not be accessed if the tag matches and the valid bit is set. + + If the cache is enabled, cache-as-SRAM accesses have no effect on the + cache data RAM, and will produce a bus error response."] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down."] + #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, + but can not be accessed. This reduces static power dissipation. + Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot + be enabled when powered down. + Cache-as-SRAM accesses will produce a bus error response when + the cache is powered down."] #[inline(always)] pub fn power_down(&mut self) -> POWER_DOWN_W { POWER_DOWN_W { w: self } } - #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual."] + #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) + will produce a bus fault. When 0, these writes are silently ignored. + In either case, writes to the 0x0 alias will deallocate on tag match, + as usual."] #[inline(always)] pub fn err_badwrite(&mut self) -> ERR_BADWRITE_W { ERR_BADWRITE_W { w: self } } - #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response."] + #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses + will go straight to the flash, without querying the cache. When enabled, + cacheable XIP accesses will query the cache, and the flash will + not be accessed if the tag matches and the valid bit is set. + + If the cache is enabled, cache-as-SRAM accesses have no effect on the + cache data RAM, and will produce a bus error response."] #[inline(always)] pub fn en(&mut self) -> EN_W { EN_W { w: self } diff --git a/src/xip_ctrl/flush.rs b/src/xip_ctrl/flush.rs index 29d9ae96b..7af1725c6 100644 --- a/src/xip_ctrl/flush.rs +++ b/src/xip_ctrl/flush.rs @@ -41,6 +41,7 @@ impl From> for W { completes. Alternatively STAT can be polled until completion."] pub struct FLUSH_R(crate::FieldReader); impl FLUSH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FLUSH_R(crate::FieldReader::new(bits)) } @@ -79,14 +80,22 @@ impl<'a> FLUSH_W<'a> { } } impl R { - #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but the data memory retains its contents. (This means cache-as-SRAM contents is not affected by flush or reset.) Reading will hold the bus (stall the processor) until the flush completes. Alternatively STAT can be polled until completion."] + #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but + the data memory retains its contents. (This means cache-as-SRAM + contents is not affected by flush or reset.) + Reading will hold the bus (stall the processor) until the flush + completes. Alternatively STAT can be polled until completion."] #[inline(always)] pub fn flush(&self) -> FLUSH_R { FLUSH_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but the data memory retains its contents. (This means cache-as-SRAM contents is not affected by flush or reset.) Reading will hold the bus (stall the processor) until the flush completes. Alternatively STAT can be polled until completion."] + #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but + the data memory retains its contents. (This means cache-as-SRAM + contents is not affected by flush or reset.) + Reading will hold the bus (stall the processor) until the flush + completes. Alternatively STAT can be polled until completion."] #[inline(always)] pub fn flush(&mut self) -> FLUSH_W { FLUSH_W { w: self } diff --git a/src/xip_ctrl/stat.rs b/src/xip_ctrl/stat.rs index 211058598..96e6c44de 100644 --- a/src/xip_ctrl/stat.rs +++ b/src/xip_ctrl/stat.rs @@ -18,6 +18,7 @@ impl From> for R { flag allow its level to be ascertained."] pub struct FIFO_FULL_R(crate::FieldReader); impl FIFO_FULL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FIFO_FULL_R(crate::FieldReader::new(bits)) } @@ -32,6 +33,7 @@ impl core::ops::Deref for FIFO_FULL_R { #[doc = "Field `FIFO_EMPTY` reader - When 1, indicates the XIP streaming FIFO is completely empty."] pub struct FIFO_EMPTY_R(crate::FieldReader); impl FIFO_EMPTY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FIFO_EMPTY_R(crate::FieldReader::new(bits)) } @@ -48,6 +50,7 @@ impl core::ops::Deref for FIFO_EMPTY_R { when requested via the FLUSH register."] pub struct FLUSH_READY_R(crate::FieldReader); impl FLUSH_READY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { FLUSH_READY_R(crate::FieldReader::new(bits)) } @@ -60,7 +63,9 @@ impl core::ops::Deref for FLUSH_READY_R { } } impl R { - #[doc = "Bit 2 - When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained."] + #[doc = "Bit 2 - When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained."] #[inline(always)] pub fn fifo_full(&self) -> FIFO_FULL_R { FIFO_FULL_R::new(((self.bits >> 2) & 0x01) != 0) @@ -70,7 +75,9 @@ impl R { pub fn fifo_empty(&self) -> FIFO_EMPTY_R { FIFO_EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) } - #[doc = "Bit 0 - Reads as 0 while a cache flush is in progress, and 1 otherwise. The cache is flushed whenever the XIP block is reset, and also when requested via the FLUSH register."] + #[doc = "Bit 0 - Reads as 0 while a cache flush is in progress, and 1 otherwise. + The cache is flushed whenever the XIP block is reset, and also + when requested via the FLUSH register."] #[inline(always)] pub fn flush_ready(&self) -> FLUSH_READY_R { FLUSH_READY_R::new((self.bits & 0x01) != 0) diff --git a/src/xip_ctrl/stream_addr.rs b/src/xip_ctrl/stream_addr.rs index 27b9b790d..ef7e44706 100644 --- a/src/xip_ctrl/stream_addr.rs +++ b/src/xip_ctrl/stream_addr.rs @@ -39,6 +39,7 @@ impl From> for W { Write the initial access address here before starting a streaming read."] pub struct STREAM_ADDR_R(crate::FieldReader); impl STREAM_ADDR_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { STREAM_ADDR_R(crate::FieldReader::new(bits)) } @@ -65,14 +66,18 @@ impl<'a> STREAM_ADDR_W<'a> { } } impl R { - #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] + #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read."] #[inline(always)] pub fn stream_addr(&self) -> STREAM_ADDR_R { STREAM_ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) } } impl W { - #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] + #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read."] #[inline(always)] pub fn stream_addr(&mut self) -> STREAM_ADDR_W { STREAM_ADDR_W { w: self } diff --git a/src/xip_ctrl/stream_ctr.rs b/src/xip_ctrl/stream_ctr.rs index db9e22063..fa61e7345 100644 --- a/src/xip_ctrl/stream_ctr.rs +++ b/src/xip_ctrl/stream_ctr.rs @@ -44,6 +44,7 @@ impl From> for W { draining the FIFO and reinitialising STREAM_ADDR)"] pub struct STREAM_CTR_R(crate::FieldReader); impl STREAM_CTR_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { STREAM_CTR_R(crate::FieldReader::new(bits)) } @@ -75,14 +76,28 @@ impl<'a> STREAM_CTR_W<'a> { } } impl R { - #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] + #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR)"] #[inline(always)] pub fn stream_ctr(&self) -> STREAM_CTR_R { STREAM_CTR_R::new((self.bits & 0x003f_ffff) as u32) } } impl W { - #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] + #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR)"] #[inline(always)] pub fn stream_ctr(&mut self) -> STREAM_CTR_W { STREAM_CTR_W { w: self } diff --git a/src/xip_ssi/baudr.rs b/src/xip_ssi/baudr.rs index 0ac0d7d4a..047a8b611 100644 --- a/src/xip_ssi/baudr.rs +++ b/src/xip_ssi/baudr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SCKDV` reader - SSI clock divider"] pub struct SCKDV_R(crate::FieldReader); impl SCKDV_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { SCKDV_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/ctrlr0.rs b/src/xip_ssi/ctrlr0.rs index 1b9d9de00..685fdc99a 100644 --- a/src/xip_ssi/ctrlr0.rs +++ b/src/xip_ssi/ctrlr0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SSTE` reader - Slave select toggle enable"] pub struct SSTE_R(crate::FieldReader); impl SSTE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SSTE_R(crate::FieldReader::new(bits)) } @@ -92,6 +93,7 @@ impl From for u8 { #[doc = "Field `SPI_FRF` reader - SPI frame format"] pub struct SPI_FRF_R(crate::FieldReader); impl SPI_FRF_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { SPI_FRF_R(crate::FieldReader::new(bits)) } @@ -164,6 +166,7 @@ impl<'a> SPI_FRF_W<'a> { Value of n -> n+1 clocks per frame."] pub struct DFS_32_R(crate::FieldReader); impl DFS_32_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DFS_32_R(crate::FieldReader::new(bits)) } @@ -192,6 +195,7 @@ impl<'a> DFS_32_W<'a> { Value of n -> n+1 clocks per frame."] pub struct CFS_R(crate::FieldReader); impl CFS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { CFS_R(crate::FieldReader::new(bits)) } @@ -219,6 +223,7 @@ impl<'a> CFS_W<'a> { #[doc = "Field `SRL` reader - Shift register loop (test mode)"] pub struct SRL_R(crate::FieldReader); impl SRL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SRL_R(crate::FieldReader::new(bits)) } @@ -255,6 +260,7 @@ impl<'a> SRL_W<'a> { #[doc = "Field `SLV_OE` reader - Slave output enable"] pub struct SLV_OE_R(crate::FieldReader); impl SLV_OE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SLV_OE_R(crate::FieldReader::new(bits)) } @@ -312,6 +318,7 @@ impl From for u8 { #[doc = "Field `TMOD` reader - Transfer mode"] pub struct TMOD_R(crate::FieldReader); impl TMOD_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TMOD_R(crate::FieldReader::new(bits)) } @@ -394,6 +401,7 @@ impl<'a> TMOD_W<'a> { #[doc = "Field `SCPOL` reader - Serial clock polarity"] pub struct SCPOL_R(crate::FieldReader); impl SCPOL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCPOL_R(crate::FieldReader::new(bits)) } @@ -430,6 +438,7 @@ impl<'a> SCPOL_W<'a> { #[doc = "Field `SCPH` reader - Serial clock phase"] pub struct SCPH_R(crate::FieldReader); impl SCPH_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SCPH_R(crate::FieldReader::new(bits)) } @@ -466,6 +475,7 @@ impl<'a> SCPH_W<'a> { #[doc = "Field `FRF` reader - Frame format"] pub struct FRF_R(crate::FieldReader); impl FRF_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FRF_R(crate::FieldReader::new(bits)) } @@ -492,6 +502,7 @@ impl<'a> FRF_W<'a> { #[doc = "Field `DFS` reader - Data frame size"] pub struct DFS_R(crate::FieldReader); impl DFS_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DFS_R(crate::FieldReader::new(bits)) } @@ -526,12 +537,14 @@ impl R { pub fn spi_frf(&self) -> SPI_FRF_R { SPI_FRF_R::new(((self.bits >> 21) & 0x03) as u8) } - #[doc = "Bits 16:20 - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] + #[doc = "Bits 16:20 - Data frame size in 32b transfer mode + Value of n -> n+1 clocks per frame."] #[inline(always)] pub fn dfs_32(&self) -> DFS_32_R { DFS_32_R::new(((self.bits >> 16) & 0x1f) as u8) } - #[doc = "Bits 12:15 - Control frame size Value of n -> n+1 clocks per frame."] + #[doc = "Bits 12:15 - Control frame size + Value of n -> n+1 clocks per frame."] #[inline(always)] pub fn cfs(&self) -> CFS_R { CFS_R::new(((self.bits >> 12) & 0x0f) as u8) @@ -583,12 +596,14 @@ impl W { pub fn spi_frf(&mut self) -> SPI_FRF_W { SPI_FRF_W { w: self } } - #[doc = "Bits 16:20 - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] + #[doc = "Bits 16:20 - Data frame size in 32b transfer mode + Value of n -> n+1 clocks per frame."] #[inline(always)] pub fn dfs_32(&mut self) -> DFS_32_W { DFS_32_W { w: self } } - #[doc = "Bits 12:15 - Control frame size Value of n -> n+1 clocks per frame."] + #[doc = "Bits 12:15 - Control frame size + Value of n -> n+1 clocks per frame."] #[inline(always)] pub fn cfs(&mut self) -> CFS_W { CFS_W { w: self } diff --git a/src/xip_ssi/ctrlr1.rs b/src/xip_ssi/ctrlr1.rs index eb38a023a..848ec8fb1 100644 --- a/src/xip_ssi/ctrlr1.rs +++ b/src/xip_ssi/ctrlr1.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `NDF` reader - Number of data frames"] pub struct NDF_R(crate::FieldReader); impl NDF_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { NDF_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/dmacr.rs b/src/xip_ssi/dmacr.rs index cf0b152ed..11f7922b3 100644 --- a/src/xip_ssi/dmacr.rs +++ b/src/xip_ssi/dmacr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TDMAE` reader - Transmit DMA enable"] pub struct TDMAE_R(crate::FieldReader); impl TDMAE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TDMAE_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> TDMAE_W<'a> { #[doc = "Field `RDMAE` reader - Receive DMA enable"] pub struct RDMAE_R(crate::FieldReader); impl RDMAE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RDMAE_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/dmardlr.rs b/src/xip_ssi/dmardlr.rs index 3189e575b..b00a6455e 100644 --- a/src/xip_ssi/dmardlr.rs +++ b/src/xip_ssi/dmardlr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DMARDL` reader - Receive data watermark level (DMARDLR+1)"] pub struct DMARDL_R(crate::FieldReader); impl DMARDL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DMARDL_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/dmatdlr.rs b/src/xip_ssi/dmatdlr.rs index b4706f2c5..d9f492595 100644 --- a/src/xip_ssi/dmatdlr.rs +++ b/src/xip_ssi/dmatdlr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DMATDL` reader - Transmit data watermark level"] pub struct DMATDL_R(crate::FieldReader); impl DMATDL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { DMATDL_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/dr0.rs b/src/xip_ssi/dr0.rs index 373816098..245357f5e 100644 --- a/src/xip_ssi/dr0.rs +++ b/src/xip_ssi/dr0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `DR` reader - First data register of 36"] pub struct DR_R(crate::FieldReader); impl DR_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { DR_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/icr.rs b/src/xip_ssi/icr.rs index 7b10071a5..5d46f01a3 100644 --- a/src/xip_ssi/icr.rs +++ b/src/xip_ssi/icr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `ICR` reader - Clear-on-read all active interrupts"] pub struct ICR_R(crate::FieldReader); impl ICR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ICR_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/idr.rs b/src/xip_ssi/idr.rs index dbacfcba4..b3b5d8b98 100644 --- a/src/xip_ssi/idr.rs +++ b/src/xip_ssi/idr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `IDCODE` reader - Peripheral dentification code"] pub struct IDCODE_R(crate::FieldReader); impl IDCODE_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { IDCODE_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/imr.rs b/src/xip_ssi/imr.rs index 6b38c1550..7c6e3b66c 100644 --- a/src/xip_ssi/imr.rs +++ b/src/xip_ssi/imr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `MSTIM` reader - Multi-master contention interrupt mask"] pub struct MSTIM_R(crate::FieldReader); impl MSTIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MSTIM_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> MSTIM_W<'a> { #[doc = "Field `RXFIM` reader - Receive FIFO full interrupt mask"] pub struct RXFIM_R(crate::FieldReader); impl RXFIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXFIM_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> RXFIM_W<'a> { #[doc = "Field `RXOIM` reader - Receive FIFO overflow interrupt mask"] pub struct RXOIM_R(crate::FieldReader); impl RXOIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXOIM_R(crate::FieldReader::new(bits)) } @@ -145,6 +148,7 @@ impl<'a> RXOIM_W<'a> { #[doc = "Field `RXUIM` reader - Receive FIFO underflow interrupt mask"] pub struct RXUIM_R(crate::FieldReader); impl RXUIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXUIM_R(crate::FieldReader::new(bits)) } @@ -181,6 +185,7 @@ impl<'a> RXUIM_W<'a> { #[doc = "Field `TXOIM` reader - Transmit FIFO overflow interrupt mask"] pub struct TXOIM_R(crate::FieldReader); impl TXOIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXOIM_R(crate::FieldReader::new(bits)) } @@ -217,6 +222,7 @@ impl<'a> TXOIM_W<'a> { #[doc = "Field `TXEIM` reader - Transmit FIFO empty interrupt mask"] pub struct TXEIM_R(crate::FieldReader); impl TXEIM_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXEIM_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/isr.rs b/src/xip_ssi/isr.rs index 7877e9adf..a231d5b45 100644 --- a/src/xip_ssi/isr.rs +++ b/src/xip_ssi/isr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `MSTIS` reader - Multi-master contention interrupt status"] pub struct MSTIS_R(crate::FieldReader); impl MSTIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MSTIS_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for MSTIS_R { #[doc = "Field `RXFIS` reader - Receive FIFO full interrupt status"] pub struct RXFIS_R(crate::FieldReader); impl RXFIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXFIS_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for RXFIS_R { #[doc = "Field `RXOIS` reader - Receive FIFO overflow interrupt status"] pub struct RXOIS_R(crate::FieldReader); impl RXOIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXOIS_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RXOIS_R { #[doc = "Field `RXUIS` reader - Receive FIFO underflow interrupt status"] pub struct RXUIS_R(crate::FieldReader); impl RXUIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXUIS_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for RXUIS_R { #[doc = "Field `TXOIS` reader - Transmit FIFO overflow interrupt status"] pub struct TXOIS_R(crate::FieldReader); impl TXOIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXOIS_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for TXOIS_R { #[doc = "Field `TXEIS` reader - Transmit FIFO empty interrupt status"] pub struct TXEIS_R(crate::FieldReader); impl TXEIS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXEIS_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/msticr.rs b/src/xip_ssi/msticr.rs index 9abf1bdc0..17877b005 100644 --- a/src/xip_ssi/msticr.rs +++ b/src/xip_ssi/msticr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `MSTICR` reader - Clear-on-read multi-master contention interrupt"] pub struct MSTICR_R(crate::FieldReader); impl MSTICR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MSTICR_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/mwcr.rs b/src/xip_ssi/mwcr.rs index 47c1561dd..6d04e4e0a 100644 --- a/src/xip_ssi/mwcr.rs +++ b/src/xip_ssi/mwcr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `MHS` reader - Microwire handshaking"] pub struct MHS_R(crate::FieldReader); impl MHS_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MHS_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> MHS_W<'a> { #[doc = "Field `MDD` reader - Microwire control"] pub struct MDD_R(crate::FieldReader); impl MDD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MDD_R(crate::FieldReader::new(bits)) } @@ -109,6 +111,7 @@ impl<'a> MDD_W<'a> { #[doc = "Field `MWMOD` reader - Microwire transfer mode"] pub struct MWMOD_R(crate::FieldReader); impl MWMOD_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MWMOD_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/risr.rs b/src/xip_ssi/risr.rs index 9b816243c..1329c4844 100644 --- a/src/xip_ssi/risr.rs +++ b/src/xip_ssi/risr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `MSTIR` reader - Multi-master contention raw interrupt status"] pub struct MSTIR_R(crate::FieldReader); impl MSTIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { MSTIR_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for MSTIR_R { #[doc = "Field `RXFIR` reader - Receive FIFO full raw interrupt status"] pub struct RXFIR_R(crate::FieldReader); impl RXFIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXFIR_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for RXFIR_R { #[doc = "Field `RXOIR` reader - Receive FIFO overflow raw interrupt status"] pub struct RXOIR_R(crate::FieldReader); impl RXOIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXOIR_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RXOIR_R { #[doc = "Field `RXUIR` reader - Receive FIFO underflow raw interrupt status"] pub struct RXUIR_R(crate::FieldReader); impl RXUIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXUIR_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for RXUIR_R { #[doc = "Field `TXOIR` reader - Transmit FIFO overflow raw interrupt status"] pub struct TXOIR_R(crate::FieldReader); impl TXOIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXOIR_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for TXOIR_R { #[doc = "Field `TXEIR` reader - Transmit FIFO empty raw interrupt status"] pub struct TXEIR_R(crate::FieldReader); impl TXEIR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXEIR_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/rx_sample_dly.rs b/src/xip_ssi/rx_sample_dly.rs index a6e9a3ad1..8d801b74e 100644 --- a/src/xip_ssi/rx_sample_dly.rs +++ b/src/xip_ssi/rx_sample_dly.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `RSD` reader - RXD sample delay (in SCLK cycles)"] pub struct RSD_R(crate::FieldReader); impl RSD_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RSD_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/rxflr.rs b/src/xip_ssi/rxflr.rs index 2b89310d9..69842d586 100644 --- a/src/xip_ssi/rxflr.rs +++ b/src/xip_ssi/rxflr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RXTFL` reader - Receive FIFO level"] pub struct RXTFL_R(crate::FieldReader); impl RXTFL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RXTFL_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/rxftlr.rs b/src/xip_ssi/rxftlr.rs index ce165b5e9..877e91628 100644 --- a/src/xip_ssi/rxftlr.rs +++ b/src/xip_ssi/rxftlr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `RFT` reader - Receive FIFO threshold"] pub struct RFT_R(crate::FieldReader); impl RFT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { RFT_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/rxoicr.rs b/src/xip_ssi/rxoicr.rs index 746a7a10a..d59d2d592 100644 --- a/src/xip_ssi/rxoicr.rs +++ b/src/xip_ssi/rxoicr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RXOICR` reader - Clear-on-read receive FIFO overflow interrupt"] pub struct RXOICR_R(crate::FieldReader); impl RXOICR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXOICR_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/rxuicr.rs b/src/xip_ssi/rxuicr.rs index dfb7e2562..88f6be975 100644 --- a/src/xip_ssi/rxuicr.rs +++ b/src/xip_ssi/rxuicr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `RXUICR` reader - Clear-on-read receive FIFO underflow interrupt"] pub struct RXUICR_R(crate::FieldReader); impl RXUICR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RXUICR_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/ser.rs b/src/xip_ssi/ser.rs index f4f020bc9..eb8e54a27 100644 --- a/src/xip_ssi/ser.rs +++ b/src/xip_ssi/ser.rs @@ -39,6 +39,7 @@ impl From> for W { 1 -> slave selected"] pub struct SER_R(crate::FieldReader); impl SER_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SER_R(crate::FieldReader::new(bits)) } @@ -75,14 +76,18 @@ impl<'a> SER_W<'a> { } } impl R { - #[doc = "Bit 0 - For each bit: 0 -> slave not selected 1 -> slave selected"] + #[doc = "Bit 0 - For each bit: + 0 -> slave not selected + 1 -> slave selected"] #[inline(always)] pub fn ser(&self) -> SER_R { SER_R::new((self.bits & 0x01) != 0) } } impl W { - #[doc = "Bit 0 - For each bit: 0 -> slave not selected 1 -> slave selected"] + #[doc = "Bit 0 - For each bit: + 0 -> slave not selected + 1 -> slave selected"] #[inline(always)] pub fn ser(&mut self) -> SER_W { SER_W { w: self } diff --git a/src/xip_ssi/spi_ctrlr0.rs b/src/xip_ssi/spi_ctrlr0.rs index 91dbbc513..2f0834a9d 100644 --- a/src/xip_ssi/spi_ctrlr0.rs +++ b/src/xip_ssi/spi_ctrlr0.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `XIP_CMD` reader - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)"] pub struct XIP_CMD_R(crate::FieldReader); impl XIP_CMD_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { XIP_CMD_R(crate::FieldReader::new(bits)) } @@ -63,6 +64,7 @@ impl<'a> XIP_CMD_W<'a> { #[doc = "Field `SPI_RXDS_EN` reader - Read data strobe enable"] pub struct SPI_RXDS_EN_R(crate::FieldReader); impl SPI_RXDS_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPI_RXDS_EN_R(crate::FieldReader::new(bits)) } @@ -99,6 +101,7 @@ impl<'a> SPI_RXDS_EN_W<'a> { #[doc = "Field `INST_DDR_EN` reader - Instruction DDR transfer enable"] pub struct INST_DDR_EN_R(crate::FieldReader); impl INST_DDR_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { INST_DDR_EN_R(crate::FieldReader::new(bits)) } @@ -135,6 +138,7 @@ impl<'a> INST_DDR_EN_W<'a> { #[doc = "Field `SPI_DDR_EN` reader - SPI DDR transfer enable"] pub struct SPI_DDR_EN_R(crate::FieldReader); impl SPI_DDR_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SPI_DDR_EN_R(crate::FieldReader::new(bits)) } @@ -171,6 +175,7 @@ impl<'a> SPI_DDR_EN_W<'a> { #[doc = "Field `WAIT_CYCLES` reader - Wait cycles between control frame transmit and data reception (in SCLK cycles)"] pub struct WAIT_CYCLES_R(crate::FieldReader); impl WAIT_CYCLES_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { WAIT_CYCLES_R(crate::FieldReader::new(bits)) } @@ -218,6 +223,7 @@ impl From for u8 { #[doc = "Field `INST_L` reader - Instruction length (0/4/8/16b)"] pub struct INST_L_R(crate::FieldReader); impl INST_L_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { INST_L_R(crate::FieldReader::new(bits)) } @@ -300,6 +306,7 @@ impl<'a> INST_L_W<'a> { #[doc = "Field `ADDR_L` reader - Address length (0b-60b in 4b increments)"] pub struct ADDR_L_R(crate::FieldReader); impl ADDR_L_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { ADDR_L_R(crate::FieldReader::new(bits)) } @@ -345,6 +352,7 @@ impl From for u8 { #[doc = "Field `TRANS_TYPE` reader - Address and instruction transfer format"] pub struct TRANS_TYPE_R(crate::FieldReader); impl TRANS_TYPE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TRANS_TYPE_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/sr.rs b/src/xip_ssi/sr.rs index 8228172b6..817ca7272 100644 --- a/src/xip_ssi/sr.rs +++ b/src/xip_ssi/sr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `DCOL` reader - Data collision error"] pub struct DCOL_R(crate::FieldReader); impl DCOL_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { DCOL_R(crate::FieldReader::new(bits)) } @@ -30,6 +31,7 @@ impl core::ops::Deref for DCOL_R { #[doc = "Field `TXE` reader - Transmission error"] pub struct TXE_R(crate::FieldReader); impl TXE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXE_R(crate::FieldReader::new(bits)) } @@ -44,6 +46,7 @@ impl core::ops::Deref for TXE_R { #[doc = "Field `RFF` reader - Receive FIFO full"] pub struct RFF_R(crate::FieldReader); impl RFF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RFF_R(crate::FieldReader::new(bits)) } @@ -58,6 +61,7 @@ impl core::ops::Deref for RFF_R { #[doc = "Field `RFNE` reader - Receive FIFO not empty"] pub struct RFNE_R(crate::FieldReader); impl RFNE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { RFNE_R(crate::FieldReader::new(bits)) } @@ -72,6 +76,7 @@ impl core::ops::Deref for RFNE_R { #[doc = "Field `TFE` reader - Transmit FIFO empty"] pub struct TFE_R(crate::FieldReader); impl TFE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TFE_R(crate::FieldReader::new(bits)) } @@ -86,6 +91,7 @@ impl core::ops::Deref for TFE_R { #[doc = "Field `TFNF` reader - Transmit FIFO not full"] pub struct TFNF_R(crate::FieldReader); impl TFNF_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TFNF_R(crate::FieldReader::new(bits)) } @@ -100,6 +106,7 @@ impl core::ops::Deref for TFNF_R { #[doc = "Field `BUSY` reader - SSI busy flag"] pub struct BUSY_R(crate::FieldReader); impl BUSY_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BUSY_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/ssi_version_id.rs b/src/xip_ssi/ssi_version_id.rs index e86557f7a..df71a6e05 100644 --- a/src/xip_ssi/ssi_version_id.rs +++ b/src/xip_ssi/ssi_version_id.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `SSI_COMP_VERSION` reader - SNPS component version (format X.YY)"] pub struct SSI_COMP_VERSION_R(crate::FieldReader); impl SSI_COMP_VERSION_R { + #[inline(always)] pub(crate) fn new(bits: u32) -> Self { SSI_COMP_VERSION_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/ssienr.rs b/src/xip_ssi/ssienr.rs index 532cf8a98..a0cb72398 100644 --- a/src/xip_ssi/ssienr.rs +++ b/src/xip_ssi/ssienr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `SSI_EN` reader - SSI enable"] pub struct SSI_EN_R(crate::FieldReader); impl SSI_EN_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { SSI_EN_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/txd_drive_edge.rs b/src/xip_ssi/txd_drive_edge.rs index 276810626..875340ca2 100644 --- a/src/xip_ssi/txd_drive_edge.rs +++ b/src/xip_ssi/txd_drive_edge.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TDE` reader - TXD drive edge"] pub struct TDE_R(crate::FieldReader); impl TDE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TDE_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/txflr.rs b/src/xip_ssi/txflr.rs index 78705a76f..c4f595260 100644 --- a/src/xip_ssi/txflr.rs +++ b/src/xip_ssi/txflr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `TFTFL` reader - Transmit FIFO level"] pub struct TFTFL_R(crate::FieldReader); impl TFTFL_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TFTFL_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/txftlr.rs b/src/xip_ssi/txftlr.rs index 80575bc35..d5503de0f 100644 --- a/src/xip_ssi/txftlr.rs +++ b/src/xip_ssi/txftlr.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `TFT` reader - Transmit FIFO threshold"] pub struct TFT_R(crate::FieldReader); impl TFT_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { TFT_R(crate::FieldReader::new(bits)) } diff --git a/src/xip_ssi/txoicr.rs b/src/xip_ssi/txoicr.rs index 7c4e22566..139b89825 100644 --- a/src/xip_ssi/txoicr.rs +++ b/src/xip_ssi/txoicr.rs @@ -16,6 +16,7 @@ impl From> for R { #[doc = "Field `TXOICR` reader - Clear-on-read transmit FIFO overflow interrupt"] pub struct TXOICR_R(crate::FieldReader); impl TXOICR_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { TXOICR_R(crate::FieldReader::new(bits)) } diff --git a/src/xosc/ctrl.rs b/src/xosc/ctrl.rs index fcc7b1b19..d28004382 100644 --- a/src/xosc/ctrl.rs +++ b/src/xosc/ctrl.rs @@ -58,6 +58,7 @@ impl From for u16 { The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } @@ -141,6 +142,7 @@ impl From for u16 { #[doc = "Field `FREQ_RANGE` reader - Frequency range. This resets to 0xAA0 and cannot be changed."] pub struct FREQ_RANGE_R(crate::FieldReader); impl FREQ_RANGE_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { FREQ_RANGE_R(crate::FieldReader::new(bits)) } @@ -221,7 +223,9 @@ impl<'a> FREQ_RANGE_W<'a> { } } impl R { - #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 12) & 0x0fff) as u16) @@ -233,7 +237,9 @@ impl R { } } impl W { - #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } diff --git a/src/xosc/startup.rs b/src/xosc/startup.rs index e54dc0ed2..aa1750d02 100644 --- a/src/xosc/startup.rs +++ b/src/xosc/startup.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `X4` reader - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly."] pub struct X4_R(crate::FieldReader); impl X4_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { X4_R(crate::FieldReader::new(bits)) } @@ -73,6 +74,7 @@ impl<'a> X4_W<'a> { #[doc = "Field `DELAY` reader - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] pub struct DELAY_R(crate::FieldReader); impl DELAY_R { + #[inline(always)] pub(crate) fn new(bits: u16) -> Self { DELAY_R(crate::FieldReader::new(bits)) } diff --git a/src/xosc/status.rs b/src/xosc/status.rs index c09911c60..8d4f7e64e 100644 --- a/src/xosc/status.rs +++ b/src/xosc/status.rs @@ -37,6 +37,7 @@ impl From> for W { #[doc = "Field `STABLE` reader - Oscillator is running and stable"] pub struct STABLE_R(crate::FieldReader); impl STABLE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { STABLE_R(crate::FieldReader::new(bits)) } @@ -51,6 +52,7 @@ impl core::ops::Deref for STABLE_R { #[doc = "Field `BADWRITE` reader - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"] pub struct BADWRITE_R(crate::FieldReader); impl BADWRITE_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { BADWRITE_R(crate::FieldReader::new(bits)) } @@ -87,6 +89,7 @@ impl<'a> BADWRITE_W<'a> { #[doc = "Field `ENABLED` reader - Oscillator is enabled but not necessarily running and stable, resets to 0"] pub struct ENABLED_R(crate::FieldReader); impl ENABLED_R { + #[inline(always)] pub(crate) fn new(bits: bool) -> Self { ENABLED_R(crate::FieldReader::new(bits)) } @@ -122,6 +125,7 @@ impl From for u8 { #[doc = "Field `FREQ_RANGE` reader - The current frequency range setting, always reads 0"] pub struct FREQ_RANGE_R(crate::FieldReader); impl FREQ_RANGE_R { + #[inline(always)] pub(crate) fn new(bits: u8) -> Self { FREQ_RANGE_R(crate::FieldReader::new(bits)) } diff --git a/update.sh b/update.sh index c2a6ceae7..f1191fcaa 100755 --- a/update.sh +++ b/update.sh @@ -4,7 +4,7 @@ set -ex # NOTE: Last executed using Rust 1.49.0 -cargo install --version 0.19.0 svd2rust +cargo install --version 0.20.0 svd2rust cargo install --version 0.7.0 form rustup component add rustfmt pip3 install --upgrade --user "svdtools>=0.1.20"