diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 8881075..7d473e6 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -14,11 +14,11 @@ jobs:
   ci-linux:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.61.0
+        # All generated code should be running on stable now, MRSV is 1.75.0
         toolchain: 
         - stable
         - nightly
-        - 1.61.0
+        - 1.75.0
         cargo_flags:
           - "clint-backend"
         include:
diff --git a/README.md b/README.md
index ba375c5..fabae6f 100644
--- a/README.md
+++ b/README.md
@@ -1,2 +1,3 @@
-# riscv-slic
+# riscv-slic: Software-Level Interrupt Controller for RISC-V Microcontrollers
+
 Crate for enabling vectored handling of software interrupts for RISC-V targets inspired by PLIC.
diff --git a/riscv-slic/Cargo.toml b/riscv-slic/Cargo.toml
index d6dd34e..01184bc 100644
--- a/riscv-slic/Cargo.toml
+++ b/riscv-slic/Cargo.toml
@@ -1,9 +1,18 @@
 [package]
 name = "riscv-slic"
-version = "0.1.0"
+version = "0.1.1"
 edition = "2021"
 description = "RISC-V Software-Level Interrupt Controller"
 license = "MIT"
+readme = "README.md"
+repository = "https://github.com/romancardenas/riscv-slic"
+keywords = ["riscv", "software", "interrupts", "embedded"]
+categories = ["embedded", "hardware-support"]
+documentation = "https://docs.rs/riscv-slic"
+
+[package.metadata.docs.rs]
+targets = ["riscv32imc-unknown-none-elf"]
+features = ["clint-backend"]
 
 [dependencies]
 critical-section = "1.1.2"
diff --git a/riscv-slic/README.md b/riscv-slic/README.md
new file mode 100644
index 0000000..bf4ba63
--- /dev/null
+++ b/riscv-slic/README.md
@@ -0,0 +1,29 @@
+[![crates.io](https://img.shields.io/crates/d/riscv-slic.svg)](https://crates.io/crates/riscv-slic)
+[![crates.io](https://img.shields.io/crates/v/riscv-slic.svg)](https://crates.io/crates/riscv-slic)
+
+# `riscv-slic`
+
+Crate for enabling vectored handling of software interrupts for RISC-V targets inspired by PLIC.
+
+This crate creates a software interrupt vector with as many interrupt sources as requested by the user.
+Each software interrupt source can be enabled/disabled independently, and you can assign a different priority level to each of them.
+Priority level 0 is reserved to disable the interrupt. By default, all the software interrupt sources are set to priority level 0.
+The maximum allowed priority level is 255.
+Additionally, you can set a software interrupt priority threshold.
+Only interrupt sources with a priority level above the threshold will cause interrupts.
+A threshold of 0 means that all the active interrupt sources can cause an interrupt.
+Alternatively, a threshold of 255 implies that none of the interrupt sources will cause an interrupt.
+
+If you pend a software interrupt source with a priority higher than the current threshold, it will cause a software interrupt in your RISC-V processor.
+How software interrupts are triggered depends on your target, and you need to activate a proper feature when compiling this crate.
+If your target has a CLINT peripheral, you can activate the `clint-backend` feature.
+Currently, this is the only supported way to use this crate.
+Open an issue or a RFC in GitHub if you would like other particular target to work with `riscv-slic`.
+
+
+## [Documentation](https://docs.rs/crate/riscv-slic)
+
+## Minimum Supported Rust Version (MSRV)
+
+This crate is guaranteed to compile on stable Rust 1.75 and up.
+It *might* compile with older versions but that may change in any new patch release.