From 38700c02cbc85ec4d0850dc654e30a12e17003e2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Fri, 29 Dec 2023 12:17:14 +0100
Subject: [PATCH] update dependencies

---
 hifive1-test/Cargo.toml               | 5 ++---
 riscv-slic-macros/src/export/clint.rs | 4 ++--
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/hifive1-test/Cargo.toml b/hifive1-test/Cargo.toml
index 54a4749..77ebbad 100644
--- a/hifive1-test/Cargo.toml
+++ b/hifive1-test/Cargo.toml
@@ -7,10 +7,9 @@ edition = "2021"
 
 [dependencies]
 riscv-slic = {path = "../riscv-slic", features = ["clint-backend", "unsafe-assume-single-core"]}
-e310x = { git = "https://github.com/greenlsi/e310x.git", rev = "f22b4dd"}
-hifive1 = { git = "https://github.com/greenlsi/hifive1.git", branch = "rtc", features = ["board-redv"] }
+e310x = { git = "https://github.com/greenlsi/e310x.git", branch = "master"}
+hifive1 = { git = "https://github.com/romancardenas/hifive1.git", branch = "master", features = ["board-redv"] }
 bare-metal = "0.2"
 # riscv-rt = "0.11.0"
 riscv-rt = {git = "https://github.com/rust-embedded/riscv-rt.git", branch = "master"}
-# riscv-rt = {path = "../../../github/riscv-rt", features = ["atomic-emulation-trap"]}
 panic-halt = "0.2.0"
diff --git a/riscv-slic-macros/src/export/clint.rs b/riscv-slic-macros/src/export/clint.rs
index 80fa426..17bfc5c 100644
--- a/riscv-slic-macros/src/export/clint.rs
+++ b/riscv-slic-macros/src/export/clint.rs
@@ -53,7 +53,7 @@ pub fn export_quote(input: &CodegenInput) -> TokenStream {
         #[inline]
         #[no_mangle]
         pub unsafe fn __riscv_slic_swi_pend() {
-            let msip = #pac::CLINT::mswi().msip(#pac::clint::HartId::#hart_id);
+            let msip = #pac::CLINT::mswi().msip(#pac::HartId::#hart_id);
             msip.pend();
         }
 
@@ -65,7 +65,7 @@ pub fn export_quote(input: &CodegenInput) -> TokenStream {
         #[inline]
         #[no_mangle]
         pub unsafe fn __riscv_slic_swi_unpend() {
-            let msip = #pac::CLINT::mswi().msip(#pac::clint::HartId::#hart_id);
+            let msip = #pac::CLINT::mswi().msip(#pac::HartId::#hart_id);
             msip.unpend();
         }
     }