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sdb_fmt() to setf_asm() in /arch/pic|/riscv|/z80 #4130

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merged 8 commits into from
Jan 22, 2024
Merged

sdb_fmt() to setf_asm() in /arch/pic|/riscv|/z80 #4130

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b360bbb
sdbfmt to setfasm
HN026 Jan 19, 2024
6cb2328
Merge remote-tracking branch 'origin' into conv_from_sdbfmt_to_setfasm
HN026 Jan 22, 2024
8b71841
refactor: removed opbuf
HN026 Jan 22, 2024
a3a60aa
clang-format.py
HN026 Jan 22, 2024
3b272d1
Merge branch 'dev' into conv_from_sdbfmt_to_setfasm
HN026 Jan 22, 2024
bea05ae
filepermission
HN026 Jan 22, 2024
6ea0cc5
use rz_asm_op_set_asm on const char *
wargio Jan 22, 2024
dfa3c13
direct set_asm
HN026 Jan 22, 2024
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25 changes: 13 additions & 12 deletions librz/asm/arch/pic/pic_baseline.c
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Original file line number Diff line number Diff line change
Expand Up @@ -215,40 +215,41 @@ int pic_baseline_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l) {
#undef EMIT_INVALID

op->size = 2;

const char *buf_asm = "invalid";
switch (op_info->args) {
case PIC_BASELINE_OP_ARGS_NONE:
buf_asm = op_info->mnemonic;
rz_asm_op_set_asm(op, op_info->mnemonic);
break;
case PIC_BASELINE_OP_ARGS_2F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_2F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_2F_MASK_F);
break;
case PIC_BASELINE_OP_ARGS_3F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3F_MASK_F);
break;
case PIC_BASELINE_OP_ARGS_3K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3K_MASK_K);
break;
case PIC_BASELINE_OP_ARGS_1D_5F:
buf_asm = sdb_fmt("%s 0x%x, %c", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_1D_5F_MASK_F,
rz_asm_op_setf_asm(op, "%s 0x%x, %c", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_1D_5F_MASK_F,
(instr & PIC_BASELINE_OP_ARGS_1D_5F_MASK_D) >> 5 ? 'f' : 'w');
break;
case PIC_BASELINE_OP_ARGS_5F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_5F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_5F_MASK_F);
break;
case PIC_BASELINE_OP_ARGS_3B_5F:
buf_asm = sdb_fmt("%s 0x%x, 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3B_5F_MASK_F,
rz_asm_op_setf_asm(op, "%s 0x%x, 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3B_5F_MASK_F,
(instr & PIC_BASELINE_OP_ARGS_3B_5F_MASK_B) >> 5);
break;
case PIC_BASELINE_OP_ARGS_8K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_8K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_8K_MASK_K);
break;
case PIC_BASELINE_OP_ARGS_9K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_9K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_9K_MASK_K);
break;
default:
rz_asm_op_set_asm(op, "invalid");
break;
}
strcpy(opbuf, buf_asm);
strcpy(opbuf, rz_asm_op_get_asm(op));
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return op->size;
}
32 changes: 17 additions & 15 deletions librz/asm/arch/pic/pic_midrange.c
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Original file line number Diff line number Diff line change
Expand Up @@ -185,65 +185,67 @@ int pic_midrange_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l) {

op->size = 2;

const char *buf_asm = NULL;
switch (op_info->args) {
case PIC_MIDRANGE_OP_ARGS_NONE:
buf_asm = op_info->mnemonic;
rz_asm_op_set_asm(op, op_info->mnemonic);
break;
case PIC_MIDRANGE_OP_ARGS_2F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_2F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_2F_MASK_F);
break;
case PIC_MIDRANGE_OP_ARGS_7F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_7F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_7F_MASK_F);
break;
case PIC_MIDRANGE_OP_ARGS_1D_7F:
buf_asm = sdb_fmt("%s 0x%x, %c", op_info->mnemonic,
rz_asm_op_setf_asm(op, "%s 0x%x, %c", op_info->mnemonic,
instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_F,
(instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_D) >> 7 ? 'f' : 'w');
break;
case PIC_MIDRANGE_OP_ARGS_1N_6K:
if (opcode == PIC_MIDRANGE_OPCODE_ADDFSR) {
buf_asm = sdb_fmt("%s FSR%d, 0x%x", op_info->mnemonic,
rz_asm_op_setf_asm(op, "%s FSR%d, 0x%x", op_info->mnemonic,
(instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >>
6,
instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K);
} else {
buf_asm = sdb_fmt("%s 0x%x[FSR%d]", op_info->mnemonic,
rz_asm_op_setf_asm(op, "%s 0x%x[FSR%d]", op_info->mnemonic,
instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K,
(instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >> 6);
}
break;
case PIC_MIDRANGE_OP_ARGS_3B_7F:
buf_asm = sdb_fmt("%s 0x%x, %d", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F,
rz_asm_op_setf_asm(op, "%s 0x%x, %d", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F,
(instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_B) >> 7);
break;
case PIC_MIDRANGE_OP_ARGS_4K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_4K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_4K_MASK_K);
break;
case PIC_MIDRANGE_OP_ARGS_8K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_8K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_8K_MASK_K);
break;
case PIC_MIDRANGE_OP_ARGS_9K:
branch = (instr & PIC_MIDRANGE_OP_ARGS_9K_MASK_K);
branch |= ((branch & 0x100) ? 0xfe00 : 0);
buf_asm = sdb_fmt("%s %s0x%x",
rz_asm_op_setf_asm(op, "%s %s0x%x",
op_info->mnemonic, branch < 0 ? "-" : "",
branch < 0 ? -branch : branch);
break;
case PIC_MIDRANGE_OP_ARGS_11K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_11K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_11K_MASK_K);
break;
case PIC_MIDRANGE_OP_ARGS_1N_2M:
snprintf(
fsr_op, sizeof(fsr_op),
PicMidrangeFsrOps[instr &
PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_M],
(instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_N) >> 2);
buf_asm = sdb_fmt("%s %s", op_info->mnemonic, fsr_op);
rz_asm_op_setf_asm(op, "%s %s", op_info->mnemonic, fsr_op);
break;
default:
rz_asm_op_set_asm(op, "invalid");
break;
}
if (buf_asm) {
strcpy(opbuf, buf_asm);
if (rz_asm_op_get_asm(op)) {
strcpy(opbuf, rz_asm_op_get_asm(op));
}
return op->size;
}
33 changes: 16 additions & 17 deletions librz/asm/arch/pic/pic_pic18.c
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Original file line number Diff line number Diff line change
Expand Up @@ -119,9 +119,8 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
return -1;
}
ut16 instr = rz_read_le16(b); // instruction
// if still redundan code is reported think of this of instr=0x2
const char *buf_asm = "invalid";
strcpy(opbuf, buf_asm);
// if still redundan code is reported think of this of instr=0x
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strcpy(opbuf, "invalid");

for (i = 0; ops[i].opmin != (ops[i].opmin & instr) || ops[i].opmax != (ops[i].opmax | instr); i++) {
;
Expand All @@ -134,23 +133,23 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
op->size = 2;
switch (ops[i].optype) {
case NO_ARG:
buf_asm = ops[i].name;
rz_asm_op_set_asm(op, ops[i].name);
break;
case N_T:
case K_T:
buf_asm = sdb_fmt("%s 0x%x", ops[i].name, instr & 0xff);
rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0xff);
break;
case DAF_T:
buf_asm = sdb_fmt("%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 1, (instr >> 8) & 1);
rz_asm_op_setf_asm(op, "%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 1, (instr >> 8) & 1);
break;
case AF_T:
buf_asm = sdb_fmt("%s 0x%x, %d", ops[i].name, instr & 0xff, (instr >> 8) & 1);
rz_asm_op_setf_asm(op, "%s 0x%x, %d", ops[i].name, instr & 0xff, (instr >> 8) & 1);
break;
case BAF_T:
buf_asm = sdb_fmt("%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 0x7, (instr >> 8) & 0x1);
rz_asm_op_setf_asm(op, "%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 0x7, (instr >> 8) & 0x1);
break;
case NEX_T:
buf_asm = sdb_fmt("%s 0x%x", ops[i].name, instr & 0x7ff);
rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0x7ff);
break;
case CALL_T:
if (blen < 4) {
Expand All @@ -164,7 +163,7 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
if (dword_instr >> 28 != 0xf) {
return -1;
}
buf_asm = sdb_fmt("%s 0x%x, %d", ops[i].name,
rz_asm_op_setf_asm(op, "%s 0x%x, %d", ops[i].name,
(dword_instr & 0xff) | (dword_instr >> 8 & 0xfff00), (dword_instr >> 8) & 0x1);
}
break;
Expand All @@ -178,7 +177,7 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
if (dword_instr >> 28 != 0xf) {
return -1;
}
buf_asm = sdb_fmt("%s 0x%x", ops[i].name,
rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name,
((dword_instr & 0xff) | ((dword_instr & 0xfff0000) >> 8)) * 2);
}
break;
Expand All @@ -192,15 +191,15 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
if (dword_instr >> 28 != 0xf) {
return -1;
}
buf_asm = sdb_fmt("%s 0x%x, 0x%x", ops[i].name,
rz_asm_op_setf_asm(op, "%s 0x%x, 0x%x", ops[i].name,
dword_instr & 0xfff, (dword_instr >> 16) & 0xfff);
}
break;
case SHK_T:
buf_asm = sdb_fmt("%s 0x%x", ops[i].name, instr & 0xf);
rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0xf);
break;
case S_T:
buf_asm = sdb_fmt("%s %d", ops[i].name, instr & 0x1);
rz_asm_op_setf_asm(op, "%s %d", ops[i].name, instr & 0x1);
break;
case LFSR_T: {
if (blen < 4) {
Expand All @@ -212,13 +211,13 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
return -1;
}
ut8 reg_n = (dword_instr >> 4) & 0x3;
buf_asm = sdb_fmt("%s %s, %d", ops[i].name, fsr[reg_n],
rz_asm_op_setf_asm(op, "%s %s, %d", ops[i].name, fsr[reg_n],
(dword_instr & 0xf) << 8 | ((dword_instr >> 16) & 0xff));
break;
}
default:
buf_asm = "unknown args";
rz_asm_op_set_asm(op, "unknown args");
};
strcpy(opbuf, buf_asm);
strcpy(opbuf, rz_asm_op_get_asm(op));
return op->size;
}
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