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Remove Capstone 3 (fix CS 4 & 5) #3934

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Oct 25, 2023
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16 changes: 8 additions & 8 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -62,8 +62,8 @@ jobs:
linux-gcc-tests-asan,
linux-clang-tests-asan,
linux-gcc-tests-codecov,
capstone-v3,
capstone-v4,
capstone-v5,
]
include:
- name: linux-meson-clang-tests
Expand Down Expand Up @@ -129,31 +129,31 @@ jobs:
timeout: 60
cflags: "-Wno-cpp"
allow_failure: false
- name: capstone-v3
- name: capstone-sys
os: ubuntu-22.04
build_system: meson
compiler: gcc
meson_options: -Dbuildtype=release -Duse_capstone_version=v3 --werror
meson_options: -Dbuildtype=release -Duse_sys_capstone=enabled --werror
run_tests: false
enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }}
timeout: 45
cflags: "-Wno-cpp"
allow_failure: false
- name: capstone-sys
- name: capstone-v4
os: ubuntu-22.04
build_system: meson
compiler: gcc
meson_options: -Dbuildtype=release -Duse_sys_capstone=enabled --werror
meson_options: -Dbuildtype=release -Duse_capstone_version=v4 --werror
run_tests: false
enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }}
timeout: 45
cflags: "-Wno-cpp"
allow_failure: false
- name: capstone-v4
allow_failure: true
- name: capstone-v5
os: ubuntu-22.04
build_system: meson
compiler: gcc
meson_options: -Dbuildtype=release -Duse_capstone_version=v4 --werror
meson_options: -Dbuildtype=release -Duse_capstone_version=v5 --werror
run_tests: false
enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }}
timeout: 45
Expand Down
28 changes: 15 additions & 13 deletions librz/analysis/arch/arm/arm_accessors32.h
Original file line number Diff line number Diff line change
Expand Up @@ -21,17 +21,14 @@
#define MEMDISP_BV(x) (HASMEMINDEX(x) ? REG_VAL(insn->detail->arm.operands[x].mem.index) : U32(MEMDISP(x)))
#define ISIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_IMM || insn->detail->arm.operands[x].type == ARM_OP_FP)
#define ISREG(x) (insn->detail->arm.operands[x].type == ARM_OP_REG)
#define ISPSRFLAGS(x) (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR)
#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM)
#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP)

#if CS_API_MAJOR > 3
#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
#else
#define LSHIFT(x) 0
#define LSHIFT2(x) 0
#if CS_NEXT_VERSION >= 6
#define ISPSRFLAGS(x) (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR)
#endif
#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM)
#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP)

#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
#define OPCOUNT() insn->detail->arm.op_count
#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0)
#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type
Expand All @@ -40,7 +37,12 @@
SHIFTTYPE(x) == ARM_SFT_RRX_REG)
#define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value

#define ISPOSTINDEX() insn->detail->arm.post_index
#if CS_NEXT_VERSION >= 6
#define CS_ARMCC(CC) ARMCC_##CC
#define ISWRITEBACK32() insn->detail->writeback
#define ISPREINDEX32() (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32()) && (!ISPOSTINDEX())) || \
((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32()) && (!ISPOSTINDEX())))
#define ISPOSTINDEX32() insn->detail->arm.post_index
#else
#define CS_ARMCC(CC) ARM_CC_##CC
#define ISWRITEBACK32() insn->detail->arm.writeback
#define ISPOSTINDEX32() (((OPCOUNT() == 3) && (ISIMM(2) || ISREG(2)) && (ISWRITEBACK32())) || ((OPCOUNT() == 4) && (ISIMM(3) || ISREG(3)) && (ISWRITEBACK32())))
#endif
6 changes: 1 addition & 5 deletions librz/analysis/arch/arm/arm_accessors64.h
Original file line number Diff line number Diff line change
Expand Up @@ -21,12 +21,8 @@
#define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
#define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)

#if CS_API_MAJOR > 3
#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
#else
#define LSHIFT2_64(x) 0
#endif
#define OPCOUNT64() insn->detail->arm64.op_count
#define OPCOUNT64() insn->detail->arm64.op_count

#define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
#define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
Expand Down
5 changes: 5 additions & 0 deletions librz/analysis/arch/arm/arm_cs.h
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,12 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a

RZ_IPI bool rz_arm_cs_is_group_member(RZ_NONNULL const cs_insn *insn, arm_insn_group feature);

#if CS_NEXT_VERSION >= 6
RZ_IPI bool rz_arm_cs_is_float_insn(const cs_insn *insn);
RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCodes cond_type);
#else
RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type);
#endif
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);

RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
Expand Down
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