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Remove Capstone 3 (fix CS 4 & 5) #3933

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Remove Capstone 3 (fix CS 4 & 5) #3933

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1f5402f
Remove macros checking for CS_API_VERSION 3
Rot127 Oct 20, 2023
c396779
Remove CS 3 from meson_options and subprojects.
Rot127 Oct 20, 2023
f62ba77
Remove Capstone v3 from CI
Rot127 Oct 20, 2023
6d549bc
Run clang-format
Rot127 Oct 20, 2023
cf170e7
Remove CS_API_VERSION >= 4 checks since always true from now on.
Rot127 Oct 20, 2023
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11 changes: 0 additions & 11 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,6 @@ jobs:
linux-gcc-tests-asan,
linux-clang-tests-asan,
linux-gcc-tests-codecov,
capstone-v3,
capstone-v4,
]
include:
Expand Down Expand Up @@ -129,16 +128,6 @@ jobs:
timeout: 60
cflags: "-Wno-cpp"
allow_failure: false
- name: capstone-v3
os: ubuntu-22.04
build_system: meson
compiler: gcc
meson_options: -Dbuildtype=release -Duse_capstone_version=v3 --werror
run_tests: false
enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }}
timeout: 45
cflags: "-Wno-cpp"
allow_failure: false
- name: capstone-sys
os: ubuntu-22.04
build_system: meson
Expand Down
9 changes: 2 additions & 7 deletions librz/analysis/arch/arm/arm_accessors32.h
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Expand Up @@ -25,13 +25,8 @@
#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM)
#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP)

#if CS_API_MAJOR > 3
#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
#else
#define LSHIFT(x) 0
#define LSHIFT2(x) 0
#endif
#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
#define OPCOUNT() insn->detail->arm.op_count
#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0)
#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type
Expand Down
6 changes: 1 addition & 5 deletions librz/analysis/arch/arm/arm_accessors64.h
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Expand Up @@ -21,12 +21,8 @@
#define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
#define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)

#if CS_API_MAJOR > 3
#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
#else
#define LSHIFT2_64(x) 0
#endif
#define OPCOUNT64() insn->detail->arm64.op_count
#define OPCOUNT64() insn->detail->arm64.op_count

#define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
#define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
Expand Down
2 changes: 0 additions & 2 deletions librz/analysis/arch/arm/arm_esil64.c
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Expand Up @@ -1127,9 +1127,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
}
break;
case ARM64_INS_NEG:
#if CS_API_MAJOR > 3
case ARM64_INS_NEGS:
#endif
if (LSHIFT2_64(1)) {
SHIFTED_REG64_APPEND(&op->esil, 1);
} else {
Expand Down
26 changes: 0 additions & 26 deletions librz/analysis/arch/arm/arm_il32.c
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Expand Up @@ -264,11 +264,7 @@ static inline RzFloatFormat cvtdt2fmt(arm_vectordata_type type, bool choose_src)
#define VVEC_DT(insn) insn->detail->arm.vector_data
#define FROM_FMT(dt) cvtdt2fmt(dt, true)
#define TO_FMT(dt) cvtdt2fmt(dt, false)
#if CS_API_MAJOR > 3
// clang-format off
#define NEON_LANE(n) insn->detail->arm.operands[n].neon_lane
// clang-format on
#endif

/**
* IL to write the given capstone reg
Expand Down Expand Up @@ -1371,8 +1367,6 @@ static void label_svc(RzILVM *vm, RzILOpEffect *op) {
// stub, nothing to do here
}

#if CS_API_MAJOR > 3

/**
* Capstone: ARM_INS_HVC
* ARM: hvc
Expand All @@ -1381,8 +1375,6 @@ static RzILOpEffect *hvc(cs_insn *insn, bool is_thumb) {
return GOTO("hvc");
}

#endif

static void label_hvc(RzILVM *vm, RzILOpEffect *op) {
// stub, nothing to do here
}
Expand Down Expand Up @@ -2591,7 +2583,6 @@ static RzILOpEffect *write_reg_lane(arm_reg reg, ut32 lane, ut32 vec_size, RzILO
* VFP and NEON
*/

#if CS_API_MAJOR > 3
/**
* Capstone: ARM_INS_VMOV
* ARM: vmov
Expand Down Expand Up @@ -2708,7 +2699,6 @@ static RzILOpEffect *vmov(cs_insn *insn, bool is_thumb) {

return write_reg(REGID(0), val);
}
#endif

/**
* Capstone: ARM_INS_VMRS
Expand Down Expand Up @@ -3088,7 +3078,6 @@ static RzILOpEffect *vldn_multiple_elem(cs_insn *insn, bool is_thumb) {
return SEQ2(eff, wback_eff);
}

#if CS_API_MAJOR > 3
static RzILOpEffect *vldn_single_lane(cs_insn *insn, bool is_thumb) {
ut32 mem_idx;
bool use_rm_as_wback_offset = false;
Expand Down Expand Up @@ -3170,7 +3159,6 @@ static RzILOpEffect *vldn_single_lane(cs_insn *insn, bool is_thumb) {

return SEQ2(eff, wback_eff);
}
#endif

static RzILOpEffect *vldn_all_lane(cs_insn *insn, bool is_thumb) {
ut32 mem_idx;
Expand Down Expand Up @@ -3261,12 +3249,10 @@ static RzILOpEffect *vldn(cs_insn *insn, bool is_thumb) {
return NULL;
}

#if CS_API_MAJOR > 3
// to single lane
if (NEON_LANE(0) != -1) {
return vldn_single_lane(insn, is_thumb);
}
#endif

// TODO: capstone cannot distinguish details of the following instructions
// vld3.8 {d0, d1, d2}, [r0] (f420040f)
Expand Down Expand Up @@ -3365,7 +3351,6 @@ static RzILOpEffect *vstn_multiple_elem(cs_insn *insn, bool is_thumb) {
return SEQ2(eff, wback_eff);
}

#if CS_API_MAJOR > 3
static RzILOpEffect *vstn_from_single_lane(cs_insn *insn, bool is_thumb) {
ut32 mem_idx;
bool use_rm_as_wback_offset = false;
Expand Down Expand Up @@ -3446,18 +3431,15 @@ static RzILOpEffect *vstn_from_single_lane(cs_insn *insn, bool is_thumb) {

return SEQ2(eff, wback_eff);
}
#endif

static RzILOpEffect *vstn(cs_insn *insn, bool is_thumb) {
if (OPCOUNT() < 2 || !ISREG(0)) {
return NULL;
}

#if CS_API_MAJOR > 3
if (NEON_LANE(0) != -1) {
return vstn_from_single_lane(insn, is_thumb);
}
#endif

return vstn_multiple_elem(insn, is_thumb);
}
Expand Down Expand Up @@ -3622,7 +3604,6 @@ static RzILOpEffect *vcvt(cs_insn *insn, bool is_thumb) {
return NULL;
}

#if CS_API_MAJOR > 3
static RzILOpEffect *vdup(cs_insn *insn, bool is_thumb) {
if (OPCOUNT() < 2) {
return NULL;
Expand All @@ -3643,7 +3624,6 @@ static RzILOpEffect *vdup(cs_insn *insn, bool is_thumb) {

return eff;
}
#endif

static RzILOpEffect *vext(cs_insn *insn, bool is_thumb) {
if (OPCOUNT() < 2) {
Expand Down Expand Up @@ -4144,10 +4124,8 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb)
return clz(insn, is_thumb);
case ARM_INS_SVC:
return svc(insn, is_thumb);
#if CS_API_MAJOR > 3
case ARM_INS_HVC:
return hvc(insn, is_thumb);
#endif
case ARM_INS_BFC:
return bfc(insn, is_thumb);
case ARM_INS_BFI:
Expand Down Expand Up @@ -4302,11 +4280,9 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb)
case ARM_INS_VMOVN:
case ARM_INS_VMOVX:
#endif
#if CS_API_MAJOR > 3
case ARM_INS_VMOV:
case ARM_INS_VMVN:
return vmov(insn, is_thumb);
#endif
case ARM_INS_VMSR:
return vmsr(insn, is_thumb);
case ARM_INS_VMRS:
Expand Down Expand Up @@ -4353,10 +4329,8 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb)
case ARM_INS_VCVTT:
#endif
return vcvt(insn, is_thumb);
#if CS_API_MAJOR > 3
case ARM_INS_VDUP:
return vdup(insn, is_thumb);
#endif
case ARM_INS_VEXT:
return vext(insn, is_thumb);
case ARM_INS_VZIP:
Expand Down
6 changes: 0 additions & 6 deletions librz/analysis/arch/arm/arm_il64.c
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Expand Up @@ -1838,15 +1838,11 @@ static RzILOpEffect *mvn(cs_insn *insn) {
RzILOpBitVector *res;
switch (insn->id) {
case ARM64_INS_NEG:
#if CS_API_MAJOR > 3
case ARM64_INS_NEGS:
#endif
res = NEG(val);
break;
case ARM64_INS_NGC:
#if CS_API_MAJOR > 3
case ARM64_INS_NGCS:
#endif
res = NEG(ADD(val, ITE(VARG("cf"), UN(bits, 0), UN(bits, 1))));
break;
default: // ARM64_INS_MVN
Expand Down Expand Up @@ -2652,10 +2648,8 @@ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) {
case ARM64_INS_MVN:
case ARM64_INS_NEG:
case ARM64_INS_NGC:
#if CS_API_MAJOR > 3
case ARM64_INS_NEGS:
case ARM64_INS_NGCS:
#endif
return mvn(insn);
case ARM64_INS_RBIT:
return rbit(insn);
Expand Down
10 changes: 0 additions & 10 deletions librz/analysis/arch/ppc/ppc_il.c
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Expand Up @@ -60,7 +60,6 @@ RZ_IPI bool ppc_is_x_form(ut32 insn_id) {
case PPC_INS_STDX:
case PPC_INS_STDCX:
case PPC_INS_STWCX:
#if CS_API_MAJOR > 3
case PPC_INS_LBZCIX:
case PPC_INS_LDCIX:
case PPC_INS_LHZCIX:
Expand All @@ -69,7 +68,6 @@ RZ_IPI bool ppc_is_x_form(ut32 insn_id) {
case PPC_INS_STHCIX:
case PPC_INS_STWCIX:
case PPC_INS_STDCIX:
#endif
return true;
}
}
Expand Down Expand Up @@ -101,10 +99,8 @@ RZ_IPI st32 ppc_get_mem_acc_size(ut32 insn_id) {
case PPC_INS_STBU:
case PPC_INS_STBUX:
case PPC_INS_STBX:
#if CS_API_MAJOR > 3
case PPC_INS_STBCIX:
case PPC_INS_LBZCIX:
#endif
return PPC_BYTE;
case PPC_INS_LHA:
case PPC_INS_LHAU:
Expand All @@ -120,10 +116,8 @@ RZ_IPI st32 ppc_get_mem_acc_size(ut32 insn_id) {
case PPC_INS_STHU:
case PPC_INS_STHUX:
case PPC_INS_STHX:
#if CS_API_MAJOR > 3
case PPC_INS_LHZCIX:
case PPC_INS_STHCIX:
#endif
return PPC_HWORD;
case PPC_INS_LWA:
case PPC_INS_LWARX:
Expand All @@ -142,10 +136,8 @@ RZ_IPI st32 ppc_get_mem_acc_size(ut32 insn_id) {
case PPC_INS_STWUX:
case PPC_INS_STWX:
case PPC_INS_STMW:
#if CS_API_MAJOR > 3
case PPC_INS_LWZCIX:
case PPC_INS_STWCIX:
#endif
return PPC_WORD;
case PPC_INS_LD:
case PPC_INS_LDARX:
Expand All @@ -159,10 +151,8 @@ RZ_IPI st32 ppc_get_mem_acc_size(ut32 insn_id) {
case PPC_INS_STDU:
case PPC_INS_STDUX:
case PPC_INS_STDX:
#if CS_API_MAJOR > 3
case PPC_INS_LDCIX:
case PPC_INS_STDCIX:
#endif
return PPC_DWORD;
}
}
Expand Down
12 changes: 0 additions & 12 deletions librz/analysis/arch/ppc/ppc_il_ops.c
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Expand Up @@ -84,12 +84,10 @@ static RzILOpEffect *load_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, cons
case PPC_INS_LWA:
case PPC_INS_LWAX:
case PPC_INS_LWAUX:
#if CS_API_MAJOR > 3
case PPC_INS_LBZCIX:
case PPC_INS_LHZCIX:
case PPC_INS_LWZCIX:
case PPC_INS_LDCIX:
#endif
#if CS_NEXT_VERSION >= 6
base = VARG(rA);
#else
Expand Down Expand Up @@ -275,12 +273,10 @@ static RzILOpEffect *store_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, con
case PPC_INS_STHUX:
case PPC_INS_STWUX:
case PPC_INS_STDUX:
#if CS_API_MAJOR > 3
case PPC_INS_STBCIX:
case PPC_INS_STHCIX:
case PPC_INS_STWCIX:
case PPC_INS_STDCIX:
#endif
#if CS_NEXT_VERSION >= 6
base = VARG(rA);
#else
Expand Down Expand Up @@ -667,7 +663,6 @@ static RzILOpEffect *bitwise_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, c
res = LOGNOT(
(id == PPC_INS_NAND) ? LOGAND(op0, op1) : LOGOR(op0, op1));
break;
#if CS_API_MAJOR > 3
// Compare bytes
case PPC_INS_CMPB: {
// do n = 0 to (64BIT_CPU ? 7 : 3)
Expand Down Expand Up @@ -700,7 +695,6 @@ static RzILOpEffect *bitwise_op(RZ_BORROW csh handle, RZ_BORROW cs_insn *insn, c

return SEQ5(SETL("res", UA(0)), init_n, init_bitmask, loop, SETG(rA, VARL("res")));
}
#endif
case PPC_INS_EQV:
op0 = VARG(rS);
op1 = VARG(rB);
Expand Down Expand Up @@ -1504,12 +1498,10 @@ RZ_IPI RzILOpEffect *rz_ppc_cs_get_il_op(RZ_BORROW csh handle, RZ_BORROW cs_insn
case PPC_INS_LWZU:
case PPC_INS_LWZUX:
case PPC_INS_LWZX:
#if CS_API_MAJOR > 3
case PPC_INS_LBZCIX:
case PPC_INS_LHZCIX:
case PPC_INS_LWZCIX:
case PPC_INS_LDCIX:
#endif
lop = load_op(handle, insn, mode);
break;
case PPC_INS_STB:
Expand Down Expand Up @@ -1553,12 +1545,10 @@ RZ_IPI RzILOpEffect *rz_ppc_cs_get_il_op(RZ_BORROW csh handle, RZ_BORROW cs_insn
case PPC_INS_STXVD2X:
case PPC_INS_STXVW4X:
case PPC_INS_DCBZ:
#if CS_API_MAJOR > 3
case PPC_INS_STHCIX:
case PPC_INS_STWCIX:
case PPC_INS_STBCIX:
case PPC_INS_STDCIX:
#endif
lop = store_op(handle, insn, mode);
break;
#if CS_NEXT_VERSION < 6
Expand Down Expand Up @@ -1593,9 +1583,7 @@ RZ_IPI RzILOpEffect *rz_ppc_cs_get_il_op(RZ_BORROW csh handle, RZ_BORROW cs_insn
case PPC_INS_CNTLZW:
case PPC_INS_POPCNTD:
case PPC_INS_POPCNTW:
#if CS_API_MAJOR > 3
case PPC_INS_CMPB:
#endif
#if CS_API_MAJOR == 5
case PPC_INS_CMPRB:
case PPC_INS_CMPEQB:
Expand Down
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