From f1a14c50748b531f166f1aea95e7b9a51a4b9ff7 Mon Sep 17 00:00:00 2001 From: Siddharth Mishra Date: Wed, 26 Jul 2023 00:20:55 +0530 Subject: [PATCH] Add ASM Tests For MIPS32 BE --- librz/analysis/arch/mips/README.md | 1254 ++++++++++----------- librz/analysis/arch/mips/mips_il.c | 228 ++-- librz/analysis/arch/mips/status_update.py | 27 +- librz/analysis/p/alignment_checker.py | 143 --- librz/analysis/p/analysis_mips_cs.c | 176 +-- test/db/asm/mips_32 | 221 ++++ 6 files changed, 1098 insertions(+), 951 deletions(-) delete mode 100644 librz/analysis/p/alignment_checker.py create mode 100644 test/db/asm/mips_32 diff --git a/librz/analysis/arch/mips/README.md b/librz/analysis/arch/mips/README.md index 8b43e3a7f20..0bd62f010d6 100644 --- a/librz/analysis/arch/mips/README.md +++ b/librz/analysis/arch/mips/README.md @@ -1,629 +1,629 @@ # MIPS UPLIFTING STATUS -| Instruction Name | MIPS32 | MIPS64 | mMIPS32 | mMIPS64 | -|--------------------------------|------------|------------|------------|------------| -| MIPS_INS_ABSQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADD | [x] | [x] | [x] | [ ] | -| MIPS_INS_ADDIUPC | [x] | [x] | [x] | [ ] | -| MIPS_INS_ADDIUR1SP | [ ] | [ ] | [x] | [x] | -| MIPS_INS_ADDIUR2 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_ADDIUS5 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_ADDIUSP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDQH | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDQH_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDSC | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDS_A | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDS_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDS_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDU16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_ADDUH | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDUH_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDU | [x] | [x] | [x] | [ ] | -| MIPS_INS_ADDU_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDVI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDWC | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADD_A | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ADDI | [x] | [x] | [x] | [ ] | -| MIPS_INS_ADDIU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_ALIGN | [x] | [x] | [x] | [ ] | -| MIPS_INS_ALUIPC | [x] | [x] | [x] | [ ] | -| MIPS_INS_AND | [x] | [x] | [x] | [ ] | -| MIPS_INS_AND16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_ANDI16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_ANDI | [x] | [x] | [x] | [ ] | -| MIPS_INS_APPEND | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ASUB_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ASUB_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_AUI | [x] | [x] | [x] | [ ] | -| MIPS_INS_AUIPC | [x] | [x] | [x] | [ ] | -| MIPS_INS_AVER_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_AVER_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_AVE_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_AVE_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_B16 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BADDU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BAL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BALC | [x] | [x] | [x] | [ ] | -| MIPS_INS_BALIGN | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BBIT0 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BBIT032 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BBIT1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BBIT132 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC0F | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BC0FL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BC0T | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BC0TL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BC1EQZ | [x] | [x] | [x] | [ ] | -| MIPS_INS_BC1F | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC1FL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC1NEZ | [x] | [x] | [x] | [ ] | -| MIPS_INS_BC1T | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC1TL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC2EQZ | [x] | [x] | [x] | [ ] | -| MIPS_INS_BC2F | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC2FL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC2NEZ | [x] | [x] | [x] | [ ] | -| MIPS_INS_BC2T | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC2TL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BC3F | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BC3FL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BC3T | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BC3TL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BCLRI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BCLR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BEQ | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BEQC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BEQL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BEQZ16 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BEQZALC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BEQZC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGEC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGEUC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGEZ | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGEZAL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BGEZALC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGEZALL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGEZALS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BGEZC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGEZL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGTZ | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGTZALC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGTZC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BGTZL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BINSLI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BINSL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BINSRI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BINSR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BITREV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BITSWAP | [x] | [ ] | [ ] | [ ] | -| MIPS_INS_BLEZ | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLEZALC | [x] | [x] | [x] | [ ] | -| MIPS_INS_BLEZC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLEZL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLTC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLTUC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLTZ | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLTZAL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLTZALC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLTZALL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLTZALS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BLTZC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BLTZL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BMNZI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BMNZ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BMZI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BMZ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BNE | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BNEC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BNEGI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BNEG | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BNEL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BNEZ16 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BNEZALC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BNEZC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BNVC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BNZ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BOVC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BPOSGE32 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BREAK | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BREAK16 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BSELI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BSEL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BSETI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BSET | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BZ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BEQZ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_B | [x] | [x] | [ ] | [ ] | -| MIPS_INS_BNEZ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BTEQZ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_BTNEZ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CACHE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CEIL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CEQI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CEQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CFC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CFCMSA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CINS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CINS32 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLASS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLEI_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLEI_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLE_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLE_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLO | [x] | [ ] | [ ] | [ ] | -| MIPS_INS_CLTI_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLTI_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLT_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLT_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CLZ | [x] | [ ] | [ ] | [ ] | -| MIPS_INS_CMPGDU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CMPGU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CMPU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CMP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_COPY_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_COPY_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CTC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CTCMSA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CVT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_C | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_CMPI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DADD | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DADDI | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DADDIU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DADDU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DAHI | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DALIGN | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DATI | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DAUI | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DBITSWAP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DCLO | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DCLZ | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DDIV | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DDIVU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DERET | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DEXT | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DEXTM | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DEXTU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DINS | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DINSM | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DINSU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DIV | [x] | [x] | [ ] | [ ] | -| MIPS_INS_DIVU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_DIV_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DIV_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DLSA | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DMFC0 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DMFC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DMFC2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DMOD | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DMODU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DMTC0 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DMTC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DMTC2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DMUH | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DMUHU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DMUL | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DMULT | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DMULTU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DMULU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DOTP_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DOTP_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPADD_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPADD_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPAQX_SA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPAQX_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPAQ_SA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPAQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPAU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPAX | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPOP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPSQX_SA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPSQX_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPSQ_SA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPSQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPSUB_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPSUB_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPSU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPSX | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DPS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_DROTR | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DROTR32 | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DROTRV | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSBH | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSHD | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSLL | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSLL32 | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSLLV | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSRA | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSRA32 | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSRAV | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSRL | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSRL32 | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSRLV | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSUB | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_DSUBU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_EHB | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ERET | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXT | [x] | [x] | [ ] | [ ] | -| MIPS_INS_EXTP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTPDP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTPDPV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTPV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTRV_RS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTRV_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTRV_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTRV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTR_RS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTR_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTR_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_EXTS32 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ABS | [x] | [x] | [x] | [ ] | -| MIPS_INS_FADD | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCAF | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCEQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCLASS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCLE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCLT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCNE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCOR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCUEQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCULE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCULT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCUNE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FCUN | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FDIV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FEXDO | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FEXP2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FEXUPL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FEXUPR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FFINT_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FFINT_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FFQL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FFQR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FILL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FLOG2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FLOOR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FMADD | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FMAX_A | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FMAX | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FMIN_A | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FMIN | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MOV | [x] | [x] | [ ] | [ ] | -| MIPS_INS_FMSUB | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FMUL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MUL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_NEG | [x] | [x] | [ ] | [ ] | -| MIPS_INS_FRCP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FRINT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FRSQRT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSAF | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSEQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSLE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSLT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSNE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSOR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSQRT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SQRT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSUB | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUB | [x] | [x] | [ ] | [ ] | -| MIPS_INS_FSUEQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSULE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSULT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSUNE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FSUN | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FTINT_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FTINT_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FTQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FTRUNC_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_FTRUNC_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_HADD_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_HADD_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_HSUB_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_HSUB_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ILVEV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ILVL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ILVOD | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_ILVR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_INS | [x] | [x] | [ ] | [ ] | -| MIPS_INS_INSERT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_INSV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_INSVE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_J | [x] | [x] | [ ] | [ ] | -| MIPS_INS_JAL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_JALR | [x] | [x] | [ ] | [ ] | -| MIPS_INS_JALRS16 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_JALRS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_JALS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_JALX | [x] | [x] | [ ] | [ ] | -| MIPS_INS_JIALC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_JIC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_JR | [x] | [x] | [ ] | [ ] | -| MIPS_INS_JR16 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_JRADDIUSP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_JRC | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_JALRC | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LB | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LBU16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_LBUX | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LBU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LD | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_LDC1 | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LDC2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LDC3 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LDI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LDL | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_LDPC | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_LDR | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_LDXC1 | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LH | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LHU16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_LHX | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LHU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LI16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_LL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LLD | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_LSA | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LUXC1 | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LUI | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LW | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LW16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_LWC1 | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LWC2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LWC3 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LWL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LWM16 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LWM32 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LWPC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LWP | [ ] | [ ] | [x] | [x] | -| MIPS_INS_LWR | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LWUPC | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_LWU | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_LWX | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LWXC1 | [x] | [x] | [ ] | [ ] | -| MIPS_INS_LWXS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_LI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MADD | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MADDF | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MADDR_Q | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MADDU | [x] | [ ] | [ ] | [ ] | -| MIPS_INS_MADDV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MADD_Q | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAQ_SA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAXA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAXI_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAXI_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAX_A | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAX | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAX_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MAX_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MFC0 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MFC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MFC2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MFHC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MFHI | [x] | [ ] | [ ] | [ ] | -| MIPS_INS_MFLO | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MINA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MINI_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MINI_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MIN_A | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MIN | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MIN_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MIN_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MOD | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MODSUB | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MODU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MOD_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MOD_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MOVE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MOVEP | [ ] | [ ] | [x] | [x] | -| MIPS_INS_MOVF | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MOVN | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MOVT | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MOVZ | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MSUB | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MSUBF | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MSUBR_Q | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MSUBU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MSUBV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MSUB_Q | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTC0 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTC2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTHC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTHI | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MTHLIP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTLO | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MTM0 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTM1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTM2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTP0 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTP1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MTP2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MUH | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MUHU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MULEQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MULEU_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MULQ_RS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MULQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MULR_Q | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MULSAQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MULSA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MULT | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MULTU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_MULU | [x] | [ ] | [ ] | [ ] | -| MIPS_INS_MULV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MUL_Q | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_MUL_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_NLOC | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_NLZC | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_NMADD | [x] | [x] | [ ] | [ ] | -| MIPS_INS_NMSUB | [x] | [x] | [ ] | [ ] | -| MIPS_INS_NOR | [x] | [x] | [ ] | [ ] | -| MIPS_INS_NORI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_NOT16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_NOT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_OR | [x] | [x] | [ ] | [ ] | -| MIPS_INS_OR16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_ORI | [x] | [x] | [ ] | [ ] | -| MIPS_INS_PACKRL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PAUSE | [x] | [x] | [ ] | [ ] | -| MIPS_INS_PCKEV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PCKOD | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PCNT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PICK | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_POP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECEQU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECEQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECEU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECRQU_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECRQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECRQ_RS | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECR_SRA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PRECR_SRA_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_PREF | [x] | [x] | [ ] | [ ] | -| MIPS_INS_PREPEND | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_RADDU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_RDDSP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_RDHWR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_REPLV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_REPL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_RINT | [x] | [x] | [ ] | [ ] | -| MIPS_INS_ROTR | [x] | [x] | [ ] | [ ] | -| MIPS_INS_ROTRV | [x] | [ ] | [ ] | [ ] | -| MIPS_INS_ROUND | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SAT_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SAT_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SB | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SB16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_SC | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SCD | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_SD | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_SDBBP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SDBBP16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_SDC1 | [ ] | [x] | [ ] | [ ] | -| MIPS_INS_SDC2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SDC3 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SDL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SDR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SDXC1 | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SEB | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SEH | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SELEQZ | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SELNEZ | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SEL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SEQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SEQI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SH | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SH16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_SHF | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHILO | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHILOV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHLLV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHLLV_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHLL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHLL_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHRAV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHRAV_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHRA | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHRA_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHRLV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SHRL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SLDI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SLD | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SLL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SLL16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_SLLI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SLLV | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SLT | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SLTI | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SLTIU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SLTU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SNE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SNEI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SPLATI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SPLAT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SRA | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SRAI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SRARI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SRAR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SRAV | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SRL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SRL16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_SRLI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SRLRI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SRLR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SRLV | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SSNOP | [x] | [x] | [ ] | [ ] | -| MIPS_INS_ST | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBQH | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBQH_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBQ_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBSUS_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBSUU_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBS_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBS_U | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBU16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_SUBUH | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBUH_R | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBU | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SUBU_S | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBVI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUBV | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SUXC1 | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SW | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SW16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_SWC1 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SWC2 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SWC3 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SWL | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SWM16 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SWM32 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SWP | [ ] | [ ] | [x] | [x] | -| MIPS_INS_SWR | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SWXC1 | [x] | [x] | [ ] | [ ] | -| MIPS_INS_SYNC | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SYNCI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_SYSCALL | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TEQ | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TEQI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TGE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TGEI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TGEIU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TGEU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TLBP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TLBR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TLBWI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TLBWR | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TLT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TLTI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TLTIU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TLTU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TNE | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TNEI | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_TRUNC | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_V3MULU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_VMM0 | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_VMULU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_VSHF | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_WAIT | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_WRDSP | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_WSBH | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_XOR | [x] | [x] | [ ] | [ ] | -| MIPS_INS_XOR16 | [ ] | [ ] | [x] | [x] | -| MIPS_INS_XORI | [x] | [x] | [ ] | [ ] | -| MIPS_INS_NOP | [x] | [x] | [ ] | [ ] | -| MIPS_INS_NEGU | [ ] | [ ] | [ ] | [ ] | -| MIPS_INS_JALR_HB | [x] | [x] | [ ] | [ ] | -| MIPS_INS_JR_HB | [x] | [x] | [ ] | [ ] | +| Instruction Name | MIPS32 | MIPS64 | mMIPS32 | mMIPS64 | HAS TEST | +|--------------------------------|------------|------------|------------|------------|------------| +| MIPS_INS_ABSQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADD | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_ADDIUPC | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_ADDIUR1SP | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_ADDIUR2 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_ADDIUS5 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_ADDIUSP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDQH | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDQH_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDSC | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDS_A | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDS_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDS_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDU16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_ADDUH | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDUH_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDU | [ ] | [ ] | [ ] | [ ] | 1 | +| MIPS_INS_ADDU_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDVI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDWC | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADD_A | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ADDI | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_ADDIU | [ ] | [ ] | [ ] | [ ] | 3 | +| MIPS_INS_ALIGN | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_ALUIPC | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_AND | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_AND16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_ANDI16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_ANDI | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_APPEND | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ASUB_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ASUB_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_AUI | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_AUIPC | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_AVER_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_AVER_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_AVE_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_AVE_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_B16 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BADDU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BAL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BALC | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_BALIGN | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BBIT0 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BBIT032 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BBIT1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BBIT132 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC0F | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BC0FL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BC0T | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BC0TL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BC1EQZ | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_BC1F | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC1FL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC1NEZ | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_BC1T | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC1TL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC2EQZ | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_BC2F | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC2FL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC2NEZ | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_BC2T | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC2TL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BC3F | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BC3FL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BC3T | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BC3TL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BCLRI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BCLR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BEQ | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BEQC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BEQL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BEQZ16 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BEQZALC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BEQZC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGEC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGEUC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGEZ | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGEZAL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BGEZALC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGEZALL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGEZALS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BGEZC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGEZL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGTZ | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGTZALC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGTZC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BGTZL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BINSLI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BINSL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BINSRI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BINSR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BITREV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BITSWAP | [x] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BLEZ | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLEZALC | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_BLEZC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLEZL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLTC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLTUC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLTZ | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLTZAL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLTZALC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLTZALL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLTZALS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BLTZC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BLTZL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BMNZI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BMNZ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BMZI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BMZ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BNE | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BNEC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BNEGI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BNEG | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BNEL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BNEZ16 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BNEZALC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BNEZC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BNVC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BNZ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BOVC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BPOSGE32 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BREAK | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BREAK16 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BSELI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BSEL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BSETI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BSET | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BZ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BEQZ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_B | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_BNEZ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BTEQZ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_BTNEZ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CACHE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CEIL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CEQI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CEQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CFC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CFCMSA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CINS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CINS32 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLASS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLEI_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLEI_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLE_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLE_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLO | [x] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLTI_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLTI_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLT_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLT_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CLZ | [x] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CMPGDU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CMPGU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CMPU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CMP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_COPY_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_COPY_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CTC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CTCMSA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CVT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_C | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_CMPI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DADD | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DADDI | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DADDIU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DADDU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DAHI | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DALIGN | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DATI | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DAUI | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DBITSWAP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DCLO | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DCLZ | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DDIV | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DDIVU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DERET | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DEXT | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DEXTM | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DEXTU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DINS | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DINSM | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DINSU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DIV | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DIVU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DIV_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DIV_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DLSA | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DMFC0 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DMFC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DMFC2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DMOD | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DMODU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DMTC0 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DMTC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DMTC2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DMUH | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DMUHU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DMUL | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DMULT | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DMULTU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DMULU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DOTP_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DOTP_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPADD_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPADD_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPAQX_SA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPAQX_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPAQ_SA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPAQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPAU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPAX | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPOP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPSQX_SA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPSQX_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPSQ_SA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPSQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPSUB_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPSUB_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPSU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPSX | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DPS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_DROTR | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DROTR32 | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DROTRV | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSBH | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSHD | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSLL | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSLL32 | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSLLV | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSRA | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSRA32 | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSRAV | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSRL | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSRL32 | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSRLV | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSUB | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_DSUBU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_EHB | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ERET | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXT | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_EXTP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTPDP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTPDPV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTPV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTRV_RS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTRV_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTRV_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTRV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTR_RS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTR_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTR_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_EXTS32 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ABS | [x] | [x] | [x] | [ ] | 0 | +| MIPS_INS_FADD | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCAF | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCEQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCLASS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCLE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCLT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCNE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCOR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCUEQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCULE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCULT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCUNE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FCUN | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FDIV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FEXDO | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FEXP2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FEXUPL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FEXUPR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FFINT_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FFINT_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FFQL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FFQR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FILL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FLOG2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FLOOR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FMADD | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FMAX_A | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FMAX | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FMIN_A | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FMIN | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MOV | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_FMSUB | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FMUL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MUL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_NEG | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_FRCP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FRINT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FRSQRT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSAF | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSEQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSLE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSLT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSNE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSOR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSQRT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SQRT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSUB | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUB | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_FSUEQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSULE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSULT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSUNE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FSUN | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FTINT_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FTINT_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FTQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FTRUNC_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_FTRUNC_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_HADD_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_HADD_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_HSUB_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_HSUB_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ILVEV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ILVL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ILVOD | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ILVR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_INS | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_INSERT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_INSV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_INSVE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_J | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_JAL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_JALR | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_JALRS16 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_JALRS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_JALS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_JALX | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_JIALC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_JIC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_JR | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_JR16 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_JRADDIUSP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_JRC | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_JALRC | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LB | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LBU16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_LBUX | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LBU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LD | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LDC1 | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LDC2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LDC3 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LDI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LDL | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LDPC | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LDR | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LDXC1 | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LH | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LHU16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_LHX | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LHU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LI16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_LL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LLD | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LSA | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LUXC1 | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LUI | [ ] | [ ] | [ ] | [ ] | 1 | +| MIPS_INS_LW | [ ] | [ ] | [ ] | [ ] | 1 | +| MIPS_INS_LW16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_LWC1 | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LWC2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LWC3 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LWL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LWM16 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LWM32 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LWPC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LWP | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_LWR | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LWUPC | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LWU | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LWX | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LWXC1 | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_LWXS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_LI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MADD | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MADDF | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MADDR_Q | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MADDU | [x] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MADDV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MADD_Q | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAQ_SA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAXA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAXI_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAXI_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAX_A | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAX | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAX_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MAX_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MFC0 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MFC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MFC2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MFHC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MFHI | [x] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MFLO | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MINA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MINI_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MINI_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MIN_A | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MIN | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MIN_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MIN_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MOD | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MODSUB | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MODU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MOD_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MOD_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MOVE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MOVEP | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_MOVF | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MOVN | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MOVT | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MOVZ | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MSUB | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MSUBF | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MSUBR_Q | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MSUBU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MSUBV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MSUB_Q | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTC0 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTC2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTHC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTHI | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MTHLIP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTLO | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MTM0 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTM1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTM2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTP0 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTP1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MTP2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MUH | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MUHU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MULEQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MULEU_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MULQ_RS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MULQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MULR_Q | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MULSAQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MULSA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MULT | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MULTU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_MULU | [x] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MULV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MUL_Q | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_MUL_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_NLOC | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_NLZC | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_NMADD | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_NMSUB | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_NOR | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_NORI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_NOT16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_NOT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_OR | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_OR16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_ORI | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_PACKRL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PAUSE | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_PCKEV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PCKOD | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PCNT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PICK | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_POP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECEQU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECEQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECEU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECRQU_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECRQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECRQ_RS | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECR_SRA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PRECR_SRA_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_PREF | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_PREPEND | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_RADDU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_RDDSP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_RDHWR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_REPLV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_REPL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_RINT | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_ROTR | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_ROTRV | [x] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_ROUND | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SAT_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SAT_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SB | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SB16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_SC | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SCD | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SD | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SDBBP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SDBBP16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_SDC1 | [ ] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SDC2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SDC3 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SDL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SDR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SDXC1 | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SEB | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SEH | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SELEQZ | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SELNEZ | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SEL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SEQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SEQI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SH | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SH16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_SHF | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHILO | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHILOV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHLLV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHLLV_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHLL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHLL_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHRAV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHRAV_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHRA | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHRA_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHRLV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SHRL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SLDI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SLD | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SLL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SLL16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_SLLI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SLLV | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SLT | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SLTI | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SLTIU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SLTU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SNE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SNEI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SPLATI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SPLAT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SRA | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SRAI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SRARI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SRAR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SRAV | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SRL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SRL16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_SRLI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SRLRI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SRLR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SRLV | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SSNOP | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_ST | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBQH | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBQH_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBQ_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBSUS_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBSUU_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBS_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBS_U | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBU16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_SUBUH | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBUH_R | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBU | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SUBU_S | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBVI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUBV | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SUXC1 | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SW | [ ] | [ ] | [ ] | [ ] | 2 | +| MIPS_INS_SW16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_SWC1 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SWC2 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SWC3 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SWL | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SWM16 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SWM32 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SWP | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_SWR | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SWXC1 | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_SYNC | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SYNCI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_SYSCALL | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TEQ | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TEQI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TGE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TGEI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TGEIU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TGEU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TLBP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TLBR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TLBWI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TLBWR | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TLT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TLTI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TLTIU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TLTU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TNE | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TNEI | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_TRUNC | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_V3MULU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_VMM0 | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_VMULU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_VSHF | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_WAIT | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_WRDSP | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_WSBH | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_XOR | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_XOR16 | [ ] | [ ] | [x] | [x] | 0 | +| MIPS_INS_XORI | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_NOP | [ ] | [ ] | [ ] | [ ] | 1 | +| MIPS_INS_NEGU | [ ] | [ ] | [ ] | [ ] | 0 | +| MIPS_INS_JALR_HB | [x] | [x] | [ ] | [ ] | 0 | +| MIPS_INS_JR_HB | [x] | [x] | [ ] | [ ] | 0 | diff --git a/librz/analysis/arch/mips/mips_il.c b/librz/analysis/arch/mips/mips_il.c index 9e4f08954f7..3e74cbc6a53 100644 --- a/librz/analysis/arch/mips/mips_il.c +++ b/librz/analysis/arch/mips/mips_il.c @@ -50,8 +50,7 @@ typedef Effect *(*MipsILLifterFunction)(RzAnalysis *, cs_insn *, ut32, bool, boo #define IL_LIFTER_NAME(name) MipsLifter_##name // size of Registers -#define GPRLEN (analysis->bits) -#define FPRLEN() (fp64 ? 64 : 32) +#define GPRLEN (analysis->bits) // v : value to be sign extended // vn : bitsize of v @@ -120,7 +119,6 @@ static const char *cpu_reg_enum_to_name_map[] = { [MIPS_REG_30] = "fp", [MIPS_REG_31] = "ra", - // AFPR128 [MIPS_REG_W0] = "w0", [MIPS_REG_W1] = "w1", @@ -254,7 +252,10 @@ static const char *cpu_reg_enum_to_name_map[] = { #define IL_MEM_OPND_OFFSET(opndidx) SN(GPRLEN, SIGN_EXTEND(MEM_OPND_OFFSET(opndidx), 16, GPRLEN)) // TODO: FIGURE OUT ROUNDING MODE -#define RMODE RZ_FLOAT_RMODE_RNE +#define RMODE RZ_FLOAT_RMODE_RNE +#define FMT32 RZ_FLOAT_IEEE754_BIN_32 +#define FMT64 RZ_FLOAT_IEEE754_BIN_64 +#define TO_FLOAT(bv) BV2F(fp64 ? FMT64 : FMT32, bv) // CAUSE REGISTER HANDLER MACROS // only the exception bits present here are used in whole code @@ -290,22 +291,22 @@ static const char *cpu_reg_enum_to_name_map[] = { * \param offset Offset for base register in memory operand * \return Effect for loading multiple words to consecutive registers * */ -static inline Effect* load_multiple(int size, int beg, int end, char* base, st64 offset, int gprlen) { - const char* rt = REG_NAME(beg); - BitVector* addr = ADD(VARG(base), SN(gprlen, offset)); - Effect *lm = SETG(rt, LOADW(size, addr)); +/* static inline Effect* load_multiple(int size, int beg, int end, char* base, st64 offset, int gprlen) { */ +/* const char* rt = REG_NAME(beg); */ +/* BitVector* addr = ADD(VARG(base), SN(gprlen, offset)); */ +/* Effect *lm = SETG(rt, LOADW(size, addr)); */ - for(int i = beg + 1; i <= end; i++) { - rt = REG_NAME(i); - addr = ADD(VARG(base), SN(gprlen, offset + (i-beg)*4)); - lm = SEQ2(lm, SETG(rt, LOADW(size, addr))); - } +/* for(int i = beg + 1; i <= end; i++) { */ +/* rt = REG_NAME(i); */ +/* addr = ADD(VARG(base), SN(gprlen, offset + (i-beg)*4)); */ +/* lm = SEQ2(lm, SETG(rt, LOADW(size, addr))); */ +/* } */ - return lm; -} +/* return lm; */ +/* } */ -/// idx is mem opnd index to use -#define LOAD_MULTIPLE(size, beg, end, idx) load_multiple(size, beg, end, MEM_OPND_BASE(idx), MEM_OPND_OFFSET(idx), GPRLEN) +/* /// idx is mem opnd index to use */ +/* #define LOAD_MULTIPLE(size, beg, end, idx) load_multiple(size, beg, end, MEM_OPND_BASE(idx), MEM_OPND_OFFSET(idx), GPRLEN) */ IL_LIFTER(ABSQ_S) { return NOP(); @@ -322,11 +323,10 @@ IL_LIFTER(ABSQ_S) { * */ IL_LIFTER(ADD) { // return NOP if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } - // destination reg const char *rd = REG_OPND(0); Pure *rs = IL_REG_OPND(1); Pure *rt = IL_REG_OPND(2); @@ -335,7 +335,7 @@ IL_LIFTER(ADD) { // TODO: Verify if 32 bits or 64 bits FPRLEN makes any difference // do we need to explicitly cast floats to 32 bit? if (float_op) { - return SETG(rd, FADD(RMODE, rs, rt)); + return SETG(rd, F2BV(FADD(RMODE, TO_FLOAT(rs), TO_FLOAT(rt)))); } else { BitVector *sum = SIGNED(GPRLEN, ADD(rs, rt)); Bool *overflow = IL_CHECK_OVERFLOW(DUP(sum), 32); @@ -351,7 +351,7 @@ IL_LIFTER(ADD) { * */ IL_LIFTER(ADDIUPC) { // return NOP if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -383,7 +383,7 @@ IL_LIFTER(ADDIUR1SP) { * */ IL_LIFTER(ADDIUR2) { const char *rd = REG_OPND(0); - Pure* rs = IL_REG_OPND(1); + Pure *rs = IL_REG_OPND(1); st64 imm = SIGN_EXTEND(IMM_OPND(2) << 2, 8, GPRLEN); return SETG(rd, ADD(rs, SN(GPRLEN, imm))); } @@ -466,7 +466,7 @@ IL_LIFTER(ADDUH_R) { * */ IL_LIFTER(ADDU) { // return NOP if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -501,7 +501,7 @@ IL_LIFTER(ADD_A) { * */ IL_LIFTER(ADDI) { // return NOP if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -530,7 +530,7 @@ IL_LIFTER(ADDI) { * */ IL_LIFTER(ADDIU) { // return NOP if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -555,7 +555,7 @@ IL_LIFTER(ADDIU) { * */ IL_LIFTER(ALIGN) { // return NOP if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -583,7 +583,7 @@ IL_LIFTER(ALIGN) { * */ IL_LIFTER(ALUIPC) { // return NOP if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -602,7 +602,7 @@ IL_LIFTER(ALUIPC) { * */ IL_LIFTER(AND) { // return NOP if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -620,8 +620,8 @@ IL_LIFTER(AND) { * Exceptions: None * */ IL_LIFTER(AND16) { - const char* rt = REG_OPND(0); - Pure* rs = IL_REG_OPND(1); + const char *rt = REG_OPND(0); + Pure *rs = IL_REG_OPND(1); return SETG(rt, LOGAND(VARG(rt), rs)); } @@ -633,8 +633,8 @@ IL_LIFTER(AND16) { * Exceptions: None * */ IL_LIFTER(ANDI16) { - const char* rd = REG_OPND(0); - Pure* rs = IL_REG_OPND(1); + const char *rd = REG_OPND(0); + Pure *rs = IL_REG_OPND(1); ut64 imm = IMM_OPND(2); return SETG(rd, LOGAND(rs, UN(GPRLEN, imm))); } @@ -647,7 +647,7 @@ IL_LIFTER(ANDI16) { * */ IL_LIFTER(ANDI) { // return nop if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -679,7 +679,7 @@ IL_LIFTER(ASUB_U) { * */ IL_LIFTER(AUI) { // return nop if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -701,7 +701,7 @@ IL_LIFTER(AUI) { * */ IL_LIFTER(AUIPC) { // return nop if target register is $zero - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } @@ -1163,8 +1163,7 @@ IL_LIFTER(BGEZ) { // signed-greater-than-equal-to Bool *cond = SGE(rs, SN(GPRLEN, 0)); - Effect *branch_op = BRANCH(cond, JMP(jump_target), NOP()); - return branch_op; + return BRANCH(cond, JMP(jump_target), NOP()); } /** @@ -1652,7 +1651,7 @@ IL_LIFTER(BMZ) { * Exceptions: ReservedInstruction * */ IL_LIFTER(BNE) { - if(REG_OPND(0) != REG_OPND(1)) { + if (REG_OPND(0) != REG_OPND(1)) { Pure *rs = IL_REG_OPND(0); Pure *rt = IL_REG_OPND(1); @@ -1844,8 +1843,24 @@ IL_LIFTER(BSET) { IL_LIFTER(BZ) { return NOP(); } + +/** + * Branch on Equal to Zero + * Format: BEQZ rs, offset + * Description: if GPR[rs] >= 0 then branch + * Exceptions: ReservedInstruction + * TODO: Check for delay slot in BEQZ and BNEZ + * */ IL_LIFTER(BEQZ) { - return NOP(); + Pure *rs = IL_REG_OPND(0); + + st64 offset = (st64)IMM_OPND(1) << 2; + offset = SIGN_EXTEND(offset, 18, GPRLEN); + BitVector *jump_target = UN(GPRLEN, pc + offset); + + // signed-greater-than-equal-to + Bool *cond = EQ(rs, SN(GPRLEN, 0)); + return BRANCH(cond, JMP(jump_target), NOP()); } /** @@ -1863,9 +1878,24 @@ IL_LIFTER(B) { return jump_op; } +/** + * Branch on Not Equal to Zero + * Format: BNEZ rs, offset + * Description: if GPR[rs] != 0 then branch + * Exceptions: ReservedInstruction + * */ IL_LIFTER(BNEZ) { - return NOP(); + Pure *rs = IL_REG_OPND(0); + + st64 offset = (st64)IMM_OPND(1) << 2; + offset = SIGN_EXTEND(offset, 18, GPRLEN); + BitVector *jump_target = UN(GPRLEN, pc + offset); + + // signed-greater-than-equal-to + Bool *cond = EQ(rs, SN(GPRLEN, 0)); + return BRANCH(cond, JMP(jump_target), NOP()); } + IL_LIFTER(BTEQZ) { return NOP(); } @@ -2243,6 +2273,10 @@ IL_LIFTER(DDIV) { * Exceptions: None * */ IL_LIFTER(DDIVU) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { + return NOP(); + } + // NOTE: ISA divide operations are suspicuous if (OPND_COUNT() == 2) { Pure *rs = IL_REG_OPND(0); @@ -2418,6 +2452,11 @@ IL_LIFTER(DINSU) { * Exceptions: None * */ IL_LIFTER(DIV) { + // return NOP if target register is $zero + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { + return NOP(); + } + if (OPND_COUNT() == 2) { Pure *rs = IL_REG_OPND(0); Pure *rt = IL_REG_OPND(1); @@ -2433,7 +2472,7 @@ IL_LIFTER(DIV) { Pure *rs = IL_REG_OPND(1); Pure *rt = IL_REG_OPND(2); if (float_op) { - return SETG(rd, FDIV(RMODE, rs, rt)); + return SETG(rd, F2BV(FDIV(RMODE, TO_FLOAT(rs), TO_FLOAT(rt)))); } else { return SETG(rd, SDIV(rs, rt)); } @@ -2449,6 +2488,10 @@ IL_LIFTER(DIV) { * Exceptions: None * */ IL_LIFTER(DIVU) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { + return NOP(); + } + // NOTE: ISA divide operations are suspicuous if (OPND_COUNT() == 2) { Pure *rs = IL_REG_OPND(0); @@ -2519,7 +2562,7 @@ IL_LIFTER(DMOD) { Pure *rt = IL_REG_OPND(2); BitVector *remainder = SMOD(rs, rt); - return SETG(rd, remainder); + return SETG(rd, remainder); } /** @@ -2564,7 +2607,7 @@ IL_LIFTER(DMUH) { BitVector *prod_hi = CAST(64, IL_FALSE, SHIFTR0(prod, U8(64))); - return SETG(rd, prod_hi); + return SETG(rd, prod_hi); } /** @@ -3235,12 +3278,16 @@ IL_LIFTER(FMUL) { * Exceptions: None * */ IL_LIFTER(MUL) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { + return NOP(); + } + const char *rd = REG_OPND(0); Pure *rs = IL_REG_OPND(1); Pure *rt = IL_REG_OPND(2); if (float_op) { - return SETG(rd, FMUL(RMODE, rs, rt)); + return SETG(rd, F2BV(FMUL(RMODE, TO_FLOAT(rs), TO_FLOAT(rt)))); } else { BitVector *rs64 = SIGNED(64, rs); BitVector *rt64 = SIGNED(64, rt); @@ -3309,15 +3356,25 @@ IL_LIFTER(FSUB) { * Exceptions: IntegerOverflow * */ IL_LIFTER(SUB) { + // return NOP if target register is $zero + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { + return NOP(); + } + const char *rd = REG_OPND(0); Pure *rs = IL_REG_OPND(1); Pure *rt = IL_REG_OPND(2); - BitVector *diff = SUB(rs, rt); - Effect *set_rd = SETG(rd, diff); - Bool *overflow = IL_CHECK_OVERFLOW(DUP(diff), 32); - - return BRANCH(overflow, IL_CAUSE_OVERFLOW(), set_rd); + // add.fmt + // TODO: Verify if 32 bits or 64 bits FPRLEN makes any difference + // do we need to explicitly cast floats to 32 bit? + if (float_op) { + return SETG(rd, F2BV(FADD(RMODE, TO_FLOAT(rs), TO_FLOAT(rt)))); + } else { + BitVector *sum = SIGNED(GPRLEN, SUB(rs, rt)); + Bool *overflow = IL_CHECK_OVERFLOW(DUP(sum), 32); // TODO: Verify this, also in ADD + return BRANCH(overflow, IL_CAUSE_OVERFLOW(), SETG(rd, sum)); + } } IL_LIFTER(FSUEQ) { @@ -3605,9 +3662,9 @@ IL_LIFTER(LB) { * Exceptions: TLB Refill, TLB Invalid, Address Error, Watch * */ IL_LIFTER(LBU16) { - const char* rt = REG_OPND(0); - Pure* base = IL_MEM_OPND_BASE(1); - BitVector* offset = IL_MEM_OPND_OFFSET(1); + const char *rt = REG_OPND(0); + Pure *base = IL_MEM_OPND_BASE(1); + BitVector *offset = IL_MEM_OPND_OFFSET(1); return SETG(rt, LOADW(8, ADD(base, offset))); } @@ -3767,7 +3824,6 @@ IL_LIFTER(LDPC) { BitVector *memaddr = ADD(base, S64(offset)); BitVector *dword = LOADW(64, memaddr); - return SETG(rs, dword); } @@ -3886,9 +3942,9 @@ IL_LIFTER(LH) { * Exceptions: TLB Refill, TLB Invalid, Address Error, Watch * */ IL_LIFTER(LHU16) { - const char* rt = REG_OPND(0); - Pure* base = IL_MEM_OPND_BASE(1); - BitVector* offset = IL_MEM_OPND_OFFSET(1); + const char *rt = REG_OPND(0); + Pure *base = IL_MEM_OPND_BASE(1); + BitVector *offset = IL_MEM_OPND_OFFSET(1); return SETG(rt, LOADW(16, ADD(base, offset))); } @@ -3923,7 +3979,7 @@ IL_LIFTER(LHU) { * Exceptions: None * */ IL_LIFTER(LI16) { - const char* rd = REG_OPND(0); + const char *rd = REG_OPND(0); st64 imm = SIGN_EXTEND(IMM_OPND(1), 8, GPRLEN); return SETG(rd, SN(GPRLEN, imm)); } @@ -4060,7 +4116,7 @@ IL_LIFTER(LW) { * Exceptions: TLB Refill, TLB Invalid, Address Error, Reserved Instruction, Coprocessor Unusable, Watch * */ IL_LIFTER(LW16) { - const char* rt = REG_OPND(0); + const char *rt = REG_OPND(0); Pure *base = IL_MEM_OPND_BASE(1); BitVector *offset = SN(GPRLEN, MEM_OPND_OFFSET(1) << 2); @@ -4170,14 +4226,14 @@ IL_LIFTER(LWPC) { * Exceptions; TLB Refill, TLB Invalid, Bus Error, Address Error, Watch * */ IL_LIFTER(LWP) { - const char* rd = REG_OPND(0); - const char* rd_next = REG_NAME(REG_OPND_ID(0) + 1); + const char *rd = REG_OPND(0); + const char *rd_next = REG_NAME(REG_OPND_ID(0) + 1); - Pure* base = IL_MEM_OPND_BASE(1); + Pure *base = IL_MEM_OPND_BASE(1); st64 offset = SIGN_EXTEND(MEM_OPND_OFFSET(1), 12, GPRLEN); - Effect* load1 = SETG(rd, LOADW(32, ADD(base, SN(GPRLEN, offset)))); - Effect* load2 = SETG(rd_next, LOADW(32, ADD(base, SN(GPRLEN, offset + 4)))); + Effect *load1 = SETG(rd, LOADW(32, ADD(base, SN(GPRLEN, offset)))); + Effect *load2 = SETG(rd_next, LOADW(32, ADD(base, SN(GPRLEN, offset + 4)))); return SEQ2(load1, load2); } @@ -4214,7 +4270,7 @@ IL_LIFTER(LWR) { b3 = SETG(rt, LOGOR(LOGAND(word, UN(GPRLEN, 0x000000FF)), LOGAND(VARG(rt), UN(GPRLEN, 0xFFFFFF00)))); Bool *b2cond = EQ(DUP(memaddr_low2bit), UN(2, 2)); - b2 = BRANCH(b2cond, SETG(rt, LOGAND(LOGOR(DUP(word), UN(GPRLEN, 0x0000FFFF)), LOGAND(VARG(rt), UN(GPRLEN, 0xFFFF0000)))), b3); + b2 = BRANCH(b2cond, SETG(rt, LOGAND(LOGOR(DUP(word), UN(GPRLEN, 0x0000FFFF)), LOGAND(VARG(rt), UN(GPRLEN, 0xFFFF0000)))), b3); Bool *b1cond = EQ(DUP(memaddr_low2bit), UN(2, 1)); b1 = BRANCH(b1cond, SETG(rt, LOGOR(LOGAND(DUP(word), UN(GPRLEN, 0x00FFFFFF)), LOGAND(VARG(rt), UN(GPRLEN, 0xFF000000)))), b2); @@ -4502,7 +4558,7 @@ IL_LIFTER(MOD) { Pure *rt = IL_REG_OPND(2); BitVector *remainder = SMOD(rs, rt); - return SETG(rd, remainder); + return SETG(rd, remainder); } IL_LIFTER(MODSUB) { @@ -4538,14 +4594,14 @@ IL_LIFTER(MOD_U) { * Exceptions: * */ IL_LIFTER(MOVE) { - if(REG_OPND_ID(0) == MIPS_REG_ZERO) { + if (REG_OPND_ID(0) == MIPS_REG_ZERO) { return NOP(); } const char *rd = REG_OPND(0); Pure *rs = IL_REG_OPND(1); - return SETG(rd, rs); + return SETG(rd, rs); } // MISSING: MOVE16 @@ -4558,17 +4614,19 @@ IL_LIFTER(MOVE) { * */ IL_LIFTER(MOVEP) { Effect *mov1 = NULL, *mov2 = NULL; - if(REG_OPND_ID(0) != MIPS_REG_ZERO) { - const char* rd = REG_OPND(0); - Pure* re = IL_REG_OPND(1); + if (REG_OPND_ID(0) != MIPS_REG_ZERO) { + const char *rd = REG_OPND(0); + Pure *re = IL_REG_OPND(1); mov1 = SETG(rd, re); - } else mov1 = NOP(); + } else + mov1 = NOP(); - if(REG_OPND_ID(2) == MIPS_REG_ZERO) { - const char* rs = REG_OPND(2); - Pure* rt = IL_REG_OPND(3); + if (REG_OPND_ID(2) == MIPS_REG_ZERO) { + const char *rs = REG_OPND(2); + Pure *rt = IL_REG_OPND(3); mov2 = SETG(rs, rt); - } else mov2 = NOP(); + } else + mov2 = NOP(); return SEQ2(mov1, mov2); } @@ -5042,8 +5100,8 @@ IL_LIFTER(NORI) { * Exceptions: None * */ IL_LIFTER(NOT16) { - const char* rt = REG_OPND(0); - Pure* rs = IL_REG_OPND(1); + const char *rt = REG_OPND(0); + Pure *rs = IL_REG_OPND(1); return SETG(rt, XOR(rs, UN(GPRLEN, -1))); } @@ -5055,8 +5113,8 @@ IL_LIFTER(NOT16) { * Exceptions: None * */ IL_LIFTER(NOT) { - const char* rt = REG_OPND(0); - Pure* rs = IL_REG_OPND(1); + const char *rt = REG_OPND(0); + Pure *rs = IL_REG_OPND(1); return SETG(rt, XOR(rs, UN(GPRLEN, -1))); } @@ -5082,8 +5140,8 @@ IL_LIFTER(OR) { * Exceptions: None * */ IL_LIFTER(OR16) { - const char* rt = REG_OPND(0); - Pure* rs = IL_REG_OPND(1); + const char *rt = REG_OPND(0); + Pure *rs = IL_REG_OPND(1); return SETG(rt, LOGOR(VARG(rt), rs)); } @@ -6054,11 +6112,11 @@ IL_LIFTER(SWM32) { * Exceptions: TLB Refill, TLB Invalid, TLB Modified, Bus Error, Address Error, Watch * */ IL_LIFTER(SWP) { - Pure* rs = IL_REG_OPND(0); - Pure* rs_next = VARG(REG_NAME(REG_OPND_ID(0) + 1)); + Pure *rs = IL_REG_OPND(0); + Pure *rs_next = VARG(REG_NAME(REG_OPND_ID(0) + 1)); - Pure* base = IL_MEM_OPND_BASE(1); - BitVector* offset = IL_MEM_OPND_OFFSET(1); + Pure *base = IL_MEM_OPND_BASE(1); + BitVector *offset = IL_MEM_OPND_OFFSET(1); return SEQ2(STOREW(ADD(base, offset), rs), STOREW(ADD(base, offset), rs_next)); } diff --git a/librz/analysis/arch/mips/status_update.py b/librz/analysis/arch/mips/status_update.py index e053c07a91f..87b2273f249 100644 --- a/librz/analysis/arch/mips/status_update.py +++ b/librz/analysis/arch/mips/status_update.py @@ -656,7 +656,7 @@ def load_status(): """ Reads current README.md file and loads current uplifting status @return status dictionary - {insn_name : [mips32_status, mips64_status, mmips32_status, mmips64_status]} + {insn_name : [mips32_status, mips64_status, mmips32_status, mmips64_status, test_status]} """ f = open("README.md", mode="r") @@ -684,6 +684,7 @@ def load_status(): mips64_status = cols[2].strip() != "[ ]" mmips32_status = cols[3].strip() != "[ ]" mmips64_status = cols[4].strip() != "[ ]" + test_status = int(cols[5].strip()) # fill status hash table status[insn_name] = [ @@ -691,6 +692,7 @@ def load_status(): mips64_status, mmips32_status, mmips64_status, + test_status ] return status @@ -702,8 +704,8 @@ def write_status(status): # generate columns f.write( - "| Instruction Name | MIPS32 | MIPS64 | mMIPS32 | mMIPS64 |\n" - "|--------------------------------|------------|------------|------------|------------|\n" + "| Instruction Name | MIPS32 | MIPS64 | mMIPS32 | mMIPS64 | HAS TEST |\n" + "|--------------------------------|------------|------------|------------|------------|------------|\n" ) # print empty data @@ -712,9 +714,10 @@ def write_status(status): mips64_status = "[x]" if status[insn_list[i]][1] == True else "[ ]" mmips32_status = "[x]" if status[insn_list[i]][2] == True else "[ ]" mmips64_status = "[x]" if status[insn_list[i]][3] == True else "[ ]" + test_status = str(status[insn_list[i]][4]) f.write( - f"| {insn_list[i]:>30} | {mips32_status:>10} | {mips64_status:>10} | {mmips32_status:>10} | {mmips64_status:>10} |\n" + f"| {insn_list[i]:>30} | {mips32_status:>10} | {mips64_status:>10} | {mmips32_status:>10} | {mmips64_status:>10} | {test_status:>10} |\n" ) f.close() @@ -725,6 +728,8 @@ def update_status(args): Update current status Architecture names that are not present will be marked as false @param args Contains arguments for update command + First argument contains name of instruction + Second argument contains architectures list """ status = load_status() @@ -734,7 +739,7 @@ def update_status(args): arch_list = args[1:] # generate new status - new_insn_status = [False, False, False, False] + new_insn_status = [False, False, False, False, status[insn_name][-1]] for arch in arch_list: if arch == "mips32": new_insn_status[0] = True @@ -744,6 +749,8 @@ def update_status(args): new_insn_status[2] = True if arch == "mmips64": new_insn_status[3] = True + if arch == "test": + new_insn_status[4] += 1 # update instruction status status[insn_name] = new_insn_status @@ -752,11 +759,12 @@ def update_status(args): def show_status(): status = load_status() - # count total number of uplifted instructions + # count total number of uplifted instructions or have tests mips32 = 0 mips64 = 0 mmips32 = 0 mmips64 = 0 + test = 0 for i in range(len(insn_list)): s = status[insn_list[i]] @@ -769,8 +777,10 @@ def show_status(): mmips32 += 1 if s[3] == True: mmips64 += 1 + if s[4] != 0: + test += 1 - print(f"STATUS : MIPS32 = {mips32} | MIPS64 = {mips64} | mMIPS32 = {mmips32} | mMIPS64 = {mmips64}") + print(f"STATUS : MIPS32 = {mips32} | MIPS64 = {mips64} | mMIPS32 = {mmips32} | mMIPS64 = {mmips64} | HAS TEST = {test}") # process cmd line args def show_help(): @@ -778,11 +788,12 @@ def show_help(): print( "COMMANDS : help # display this help\n" " : new # generate new status file\n" - " : update ... # update status for current arch\n" + " : update [] ... # update status for current arch or test\n" " : show # display total number of \n" " # uplifted instructions per arch\n" "EXAMPLES :\n" " : eg: update ADDI mips32 mmips64 # mips32 and mmps64 will be marked, others will be unmarked\n" + " : eg: update ADDIUR1SP test # marks +1 for test of ADDIUR1SP everytime this is called\n" " : eg: coverage mipsbins/bin/ls mips32 little # Will load bin/ls elf file and calculate uplifting status" ) diff --git a/librz/analysis/p/alignment_checker.py b/librz/analysis/p/alignment_checker.py deleted file mode 100644 index 79c1b86c7fa..00000000000 --- a/librz/analysis/p/alignment_checker.py +++ /dev/null @@ -1,143 +0,0 @@ -#!/usr/bin/env python3 - -import re - -data = """ -gpr zero .64 0 0\n -gpr at .64 8 0\n -gpr v0 .64 16 0\n -gpr v1 .64 24 0\n -gpr a0 .64 32 0\n -gpr a1 .64 40 0\n -gpr a2 .64 48 0\n -gpr a3 .64 56 0\n -gpr t0 .64 64 0\n -gpr t1 .64 72 0\n -gpr t2 .64 80 0\n -gpr t3 .64 88 0\n -gpr t4 .64 96 0\n -gpr t5 .64 104 0\n -gpr t6 .64 112 0\n -gpr t7 .64 120 0\n -gpr s0 .64 128 0\n -gpr s1 .64 136 0\n -gpr s2 .64 144 0\n -gpr s3 .64 152 0\n -gpr s4 .64 160 0\n -gpr s5 .64 168 0\n -gpr s6 .64 176 0\n -gpr s7 .64 184 0\n -gpr t8 .64 192 0\n -gpr t9 .64 200 0\n -gpr k0 .64 208 0\n -gpr k1 .64 216 0\n -gpr gp .64 224 0\n -gpr sp .64 232 0\n -gpr fp .64 240 0\n -gpr ra .64 248 0\n -gpr pc .64 256 0\n -gpr hi .64 264 0\n -gpr lo .64 272 0\n -gpr t .64 280 0\n -fpu f0 .64 288 0\n -fpu f1 .64 296 0\n -fpu f2 .64 304 0\n -fpu f3 .64 312 0\n -fpu f4 .64 320 0\n -fpu f5 .64 328 0\n -fpu f6 .64 336 0\n -fpu f7 .64 344 0\n -fpu f8 .64 352 0\n -fpu f9 .64 360 0\n -fpu f10 .64 368 0\n -fpu f11 .64 376 0\n -fpu f12 .64 384 0\n -fpu f13 .64 392 0\n -fpu f14 .64 400 0\n -fpu f15 .64 408 0\n -fpu f16 .64 416 0\n -fpu f17 .64 424 0\n -fpu f18 .64 432 0\n -fpu f19 .64 440 0\n -fpu f20 .64 448 0\n -fpu f21 .64 456 0\n -fpu f22 .64 464 0\n -fpu f23 .64 472 0\n -fpu f24 .64 480 0\n -fpu f25 .64 488 0\n -fpu f26 .64 496 0\n -fpu f27 .64 504 0\n -fpu f28 .64 512 0\n -fpu f29 .64 520 0\n -fpu f30 .64 528 0\n -fpu f31 .64 536 0\n -flg FCC0 .1 537 0\n -flg FCC1 .1 538 0\n -flg FCC2 .1 539 0\n -flg FCC3 .1 540 0\n -flg FCC4 .1 541 0\n -flg FCC5 .1 542 0\n -flg FCC6 .1 543 0\n -flg FCC7 .1 544 0\n -flg CC0 .1 545 0\n -flg CC1 .1 545 0\n -flg CC2 .1 547 0\n -flg CC3 .1 548 0\n -flg CC4 .1 549 0\n -flg CC5 .1 550 0\n -flg CC6 .1 551 0\n -flg CC7 .1 552 0\n -flg CAUSE_EXC .8 553 0\n -flg LLbit .1 554 0\n -gpr w0 .128 555 0\n -gpr w1 .128 571 0\n -gpr w2 .128 587 0\n -gpr w3 .128 603 0\n -gpr w4 .128 619 0\n -gpr w5 .128 635 0\n -gpr w6 .128 651 0\n -gpr w7 .128 667 0\n -gpr w8 .128 683 0\n -gpr w9 .128 699 0\n -gpr w10 .128 715 0\n -gpr w11 .128 731 0\n -gpr w12 .128 747 0\n -gpr w13 .128 763 0\n -gpr w14 .128 779 0\n -gpr w15 .128 795 0\n -gpr w16 .128 811 0\n -gpr w17 .128 827 0\n -gpr w18 .128 843 0\n -gpr w19 .128 859 0\n -gpr w20 .128 875 0\n -gpr w21 .128 891 0\n -gpr w22 .128 907 0\n -gpr w23 .128 923 0\n -gpr w24 .128 939 0\n -gpr w25 .128 955 0\n -gpr w26 .128 971 0\n -gpr w27 .128 987 0\n -gpr w28 .128 1003 0\n -gpr w29 .128 1019 0\n -gpr w30 .128 1035 0\n -gpr w31 .128 1051 0\n -gpr ac0 .64 1067 0\n -gpr ac1 .64 1075 0\n -gpr ac2 .64 1083 0\n -gpr ac3 .64 1091 0\n -""" - -lines = data.strip().split("\n") # Split the dataset into line -fixed = "" -address = 0 -for line in lines: - columns = re.split(r"\s+", line.strip()) - if len(columns) <= 4: - fixed += line - fixed += "\n" - continue - size = int(columns[2].strip(".")) - fixed += f"{columns[0]}\t{columns[1]}\t{columns[2]}\t{address}\t0" - address += (size + 7)//8 - -print(fixed) diff --git a/librz/analysis/p/analysis_mips_cs.c b/librz/analysis/p/analysis_mips_cs.c index 7d333d5a5a9..b43e824f9f6 100644 --- a/librz/analysis/p/analysis_mips_cs.c +++ b/librz/analysis/p/analysis_mips_cs.c @@ -1154,97 +1154,98 @@ static char *get_reg_profile(RzAnalysis *analysis) { "gpr hi .32 132 0\n" "gpr lo .32 136 0\n" "gpr t .32 140 0\n" - "fpu f0 .32 144 0\n" - "fpu f1 .32 148 0\n" - "fpu f2 .32 152 0\n" - "fpu f3 .32 156 0\n" - "fpu f4 .32 160 0\n" - "fpu f5 .32 164 0\n" - "fpu f6 .32 168 0\n" - "fpu f7 .32 172 0\n" - "fpu f8 .32 176 0\n" - "fpu f9 .32 180 0\n" - "fpu f10 .32 184 0\n" - "fpu f11 .32 188 0\n" - "fpu f12 .32 192 0\n" - "fpu f13 .32 196 0\n" - "fpu f14 .32 200 0\n" - "fpu f15 .32 204 0\n" - "fpu f16 .32 208 0\n" - "fpu f17 .32 212 0\n" - "fpu f18 .32 216 0\n" - "fpu f19 .32 220 0\n" - "fpu f20 .32 224 0\n" - "fpu f21 .32 228 0\n" - "fpu f22 .32 232 0\n" - "fpu f23 .32 236 0\n" - "fpu f24 .32 240 0\n" - "fpu f25 .32 244 0\n" - "fpu f26 .32 248 0\n" - "fpu f27 .32 252 0\n" - "fpu f28 .32 256 0\n" - "fpu f29 .32 260 0\n" - "fpu f30 .32 264 0\n" - "fpu f31 .32 268 0\n" - "flg FCC0 .1 269 0\n" - "flg FCC1 .1 270 0\n" - "flg FCC2 .1 271 0\n" - "flg FCC3 .1 272 0\n" - "flg FCC4 .1 273 0\n" - "flg FCC5 .1 274 0\n" - "flg FCC6 .1 275 0\n" - "flg FCC7 .1 276 0\n" + "fpu f0 .32 0 0\n" + "fpu f1 .32 4 0\n" + "fpu f2 .32 8 0\n" + "fpu f3 .32 12 0\n" + "fpu f4 .32 16 0\n" + "fpu f5 .32 20 0\n" + "fpu f6 .32 24 0\n" + "fpu f7 .32 28 0\n" + "fpu f8 .32 32 0\n" + "fpu f9 .32 36 0\n" + "fpu f10 .32 40 0\n" + "fpu f11 .32 44 0\n" + "fpu f12 .32 48 0\n" + "fpu f13 .32 52 0\n" + "fpu f14 .32 56 0\n" + "fpu f15 .32 60 0\n" + "fpu f16 .32 64 0\n" + "fpu f17 .32 68 0\n" + "fpu f18 .32 72 0\n" + "fpu f19 .32 76 0\n" + "fpu f20 .32 80 0\n" + "fpu f21 .32 84 0\n" + "fpu f22 .32 88 0\n" + "fpu f23 .32 92 0\n" + "fpu f24 .32 96 0\n" + "fpu f25 .32 100 0\n" + "fpu f26 .32 104 0\n" + "fpu f27 .32 108 0\n" + "fpu f28 .32 112 0\n" + "fpu f29 .32 116 0\n" + "fpu f30 .32 120 0\n" + "fpu f31 .32 124 0\n" - "flg CC0 .1 277 0\n" - "flg CC1 .1 278 0\n" - "flg CC2 .1 279 0\n" - "flg CC3 .1 280 0\n" - "flg CC4 .1 281 0\n" - "flg CC5 .1 282 0\n" - "flg CC6 .1 283 0\n" - "flg CC7 .1 284 0\n" + "flg FCC0 .1 144 0\n" + "flg FCC1 .1 145 0\n" + "flg FCC2 .1 146 0\n" + "flg FCC3 .1 147 0\n" + "flg FCC4 .1 148 0\n" + "flg FCC5 .1 149 0\n" + "flg FCC6 .1 150 0\n" + "flg FCC7 .1 151 0\n" - "flg CAUSE_EXC .8 285 0\n" - "flg LLbit .1 286 0\n" + "flg CC0 .1 152 0\n" + "flg CC1 .1 153 0\n" + "flg CC2 .1 154 0\n" + "flg CC3 .1 155 0\n" + "flg CC4 .1 156 0\n" + "flg CC5 .1 157 0\n" + "flg CC6 .1 158 0\n" + "flg CC7 .1 159 0\n" - "gpr w0 .128 287 0\n" - "gpr w1 .128 303 0\n" - "gpr w2 .128 319 0\n" - "gpr w3 .128 335 0\n" - "gpr w4 .128 351 0\n" - "gpr w5 .128 367 0\n" - "gpr w6 .128 383 0\n" - "gpr w7 .128 399 0\n" - "gpr w8 .128 415 0\n" - "gpr w9 .128 431 0\n" - "gpr w10 .128 447 0\n" - "gpr w11 .128 463 0\n" - "gpr w12 .128 479 0\n" - "gpr w13 .128 495 0\n" - "gpr w14 .128 511 0\n" - "gpr w15 .128 527 0\n" - "gpr w16 .128 543 0\n" - "gpr w17 .128 559 0\n" - "gpr w18 .128 575 0\n" - "gpr w19 .128 591 0\n" - "gpr w20 .128 607 0\n" - "gpr w21 .128 623 0\n" - "gpr w22 .128 639 0\n" - "gpr w23 .128 655 0\n" - "gpr w24 .128 671 0\n" - "gpr w25 .128 687 0\n" - "gpr w26 .128 703 0\n" - "gpr w27 .128 719 0\n" - "gpr w28 .128 735 0\n" - "gpr w29 .128 751 0\n" - "gpr w30 .128 767 0\n" - "gpr w31 .128 783 0\n" + "flg CAUSE_EXC .8 160 0\n" + "flg LLbit .1 161 0\n" - "gpr ac0 .32 799 0\n" - "gpr ac1 .32 803 0\n" - "gpr ac2 .32 807 0\n" - "gpr ac3 .32 811 0\n"; + "gpr w0 .128 162 0\n" + "gpr w1 .128 178 0\n" + "gpr w2 .128 194 0\n" + "gpr w3 .128 210 0\n" + "gpr w4 .128 226 0\n" + "gpr w5 .128 242 0\n" + "gpr w6 .128 258 0\n" + "gpr w7 .128 274 0\n" + "gpr w8 .128 290 0\n" + "gpr w9 .128 306 0\n" + "gpr w10 .128 322 0\n" + "gpr w11 .128 338 0\n" + "gpr w12 .128 354 0\n" + "gpr w13 .128 370 0\n" + "gpr w14 .128 386 0\n" + "gpr w15 .128 402 0\n" + "gpr w16 .128 418 0\n" + "gpr w17 .128 434 0\n" + "gpr w18 .128 450 0\n" + "gpr w19 .128 466 0\n" + "gpr w20 .128 482 0\n" + "gpr w21 .128 498 0\n" + "gpr w22 .128 514 0\n" + "gpr w23 .128 530 0\n" + "gpr w24 .128 546 0\n" + "gpr w25 .128 562 0\n" + "gpr w26 .128 578 0\n" + "gpr w27 .128 594 0\n" + "gpr w28 .128 610 0\n" + "gpr w29 .128 626 0\n" + "gpr w30 .128 642 0\n" + "gpr w31 .128 658 0\n" + + "gpr ac0 .32 674 0\n" + "gpr ac1 .32 678 0\n" + "gpr ac2 .32 682 0\n" + "gpr ac3 .32 686 0\n"; break; case 64: p = @@ -1379,8 +1380,7 @@ static char *get_reg_profile(RzAnalysis *analysis) { "gpr ac0 .64 1074 0\n" "gpr ac1 .64 1082 0\n" "gpr ac2 .64 1090 0\n" - "gpr ac3 .64 1098 0\n" - ; + "gpr ac3 .64 1098 0\n"; break; } return p ? strdup(p) : NULL; diff --git a/test/db/asm/mips_32 b/test/db/asm/mips_32 new file mode 100644 index 00000000000..091687e4ade --- /dev/null +++ b/test/db/asm/mips_32 @@ -0,0 +1,221 @@ +dE "lui gp, 0xa" 3c1c000a 0x400238 (set gp (bv 32 0xa0000)) +dE "addiu gp, gp, 0x2f68" 279c2f68 0x40023c (set gp (+ (var gp) (bv 32 0x2f68))) +dE "addu gp, gp, t9" 0399e021 0x400240 (set gp (+ (var gp) (var t9))) +dE "addiu sp, sp, -0x20" 27bdffe0 0x400244 (set sp (+ (var sp) (bv 32 0xffffffe0))) +dE "sw gp, 0x10(sp)" afbc0010 0x400248 (storew 0 (+ (var sp) (bv 32 0x10)) (var gp)) +dE "sw ra, 0x1c(sp)" afbf001c 0x40024c (storew 0 (+ (var sp) (bv 32 0x1c)) (var ra)) +dE "lw v0, -0x75a8(gp)" 8f828a58 0x400250 (set v0 (cast 32 (msb (loadw 0 32 (+ (var gp) (bv 32 0xffff8a58)))) (loadw 0 32 (+ (var gp) (bv 32 0xffff8a58))))) +dE "nop " 00000000 0x400254 nop +dE "lw t9, -0x75a8(gp)" 8f998a58 0x400260 (set t9 (cast 32 (msb (loadw 0 32 (+ (var gp) (bv 32 0xffff8a58)))) (loadw 0 32 (+ (var gp) (bv 32 0xffff8a58))))) +dE "jalr t9" 0320f809 0x400268 (seq (set ra (bv 32 0x400270)) (jmp (var t9))) +dE "lw ra, 0x1c(sp)" 8fbf001c 0x400270 (set ra (cast 32 (msb (loadw 0 32 (+ (var sp) (bv 32 0x1c)))) (loadw 0 32 (+ (var sp) (bv 32 0x1c))))) +dE "jr ra" 03e00008 0x400278 (jmp (var ra)) +dE "addiu sp, sp, 0x20" 27bd0020 0x40027c (set sp (+ (var sp) (bv 32 0x20))) +dE "lui t9, 0x47" 3c190047 0x400280 (set t9 (bv 32 0x470000)) +dE "sw ra, 0xbc(sp)" afbf00bc 0x4002d8 (storew 0 (+ (var sp) (bv 32 0xbc)) (var ra)) +dEB "lwc0 3, -7100(s1)" c223e444 0x40030c nop +dEB "lwc0 3, -7100(s1)" c223e444 0x40030c nop +dEB "li at, 1" 24010001 0x400318 nop +dEB "swc0 c0_random, -7100(s1)" e221e444 0x40031c nop +dEB "li v0, 1" 24020001 0x400324 nop +dEB "li v0, 1" 24020001 0x400324 nop +dE "move a2, zero" 00003025 0x400388 (set a2 (var zero)) +dE "syscall " 0000000c 0x400394 nop +dE "move a2, zero" 00003025 0x400388 (set a2 (var zero)) +dE "slti v0, v0, 2" 28420002 0x4003d8 (set v0 (ite (&& (sle (var v0) (bv 32 0x2)) (! (== (var v0) (bv 32 0x2)))) (bv 32 0x1) (bv 32 0x0))) +dE "move a1, zero" 00002825 0x400490 (set a1 (var zero)) +dE "break 0xff" 00ff000d 0x40050c (set CAUSE_EXC (bv 8 0x9)) +dE "sltu v0, s1, v0" 0222102b 0x400598 (set v0 (ite (&& (ule (var s1) (var v0)) (! (== (var s1) (var v0)))) (bv 32 0x1) (bv 32 0x0))) +dE "jr t9" 03200008 0x4005c4 (jmp (var t9)) +dEB "lwc0 c0_context, -5764(s0)" c204e97c 0x40060c nop +dE "sc at, -0x1684(s0)" e201e97c 0x400614 (branch (! (is_zero (cast 2 false (+ (var s0) (bv 32 0xffffe97c))))) (seq (storew 0 (+ (var s0) (bv 32 0xffffe97c)) (cast 32 false (var at))) (set LLbit false) (set at (bv 32 0x1))) (set CAUSE_EXC (bv 8 0x5))) +dE "sb v1, -0x1688(v0)" a043e978 0x400668 (storew 0 (+ (var v0) (bv 32 0xffffe978)) (cast 8 false (var v1))) +dE "addu gp, gp, ra" 039fe021 0x4006a4 (set gp (+ (var gp) (var ra))) +dE "and sp, sp, at" 03a1e824 0x4006bc (set sp (& (var sp) (var at))) +dE "lui a0, 0x4a" 3c04004a 0x4006f0 (set a0 (bv 32 0x4a0000)) +dE "subu a1, a1, a0" 00a42823 0x400734 (set a1 (- (var a1) (var a0))) +dE "sra v0, a1, 2" 00051083 0x400738 (set v0 (>> (var a1) (bv 5 0x2) (msb (var a1)))) +dE "srl a1, a1, 0x1f" 00052fc2 0x40073c (set a1 (>> (var a1) (bv 5 0x1f) false)) +dE "addu a1, a1, v0" 00a22821 0x400740 (set a1 (+ (var a1) (var v0))) +dE "sra a1, a1, 1" 00052843 0x400744 (set a1 (>> (var a1) (bv 5 0x1) (msb (var a1)))) +dE "lbu v0, -0x4370(s0)" 9202bc90 0x400778 (set v0 (cast 32 false (loadw 0 8 (+ (var s0) (bv 32 0xffffbc90))))) +dE "sb v0, -0x4370(s0)" a202bc90 0x4007b0 (storew 0 (+ (var s0) (bv 32 0xffffbc90)) (cast 8 false (var v0))) +dE "lb v0, (v0)" 80420000 0x40082c (set v0 (cast 32 (msb (loadw 0 8 (+ (var v0) (bv 32 0x0)))) (loadw 0 8 (+ (var v0) (bv 32 0x0))))) +dE "subu v0, v0, s0" 00501023 0x400970 (set v0 (- (var v0) (var s0))) +dE "sra s1, v0, 2" 00028883 0x400978 (set s1 (>> (var v0) (bv 5 0x2) (msb (var v0)))) +dEB "swc0 c0_random, 0(v0)" e0410000 0x400a80 nop +dE "sll v0, v0, 2" 00021080 0x400ad4 (set v0 (cast 32 (msb (<< (var v0) (bv 5 0x2) false)) (<< (var v0) (bv 5 0x2) false))) +dE "lwl v0, (v1)" 88620000 0x400b80 (branch (== (cast 2 false (+ (var v1) (bv 32 0x0))) (bv 2 0x0)) (set v0 (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x0)) (bv 32 0xfffffffc))))) (branch (== (cast 2 false (+ (var v1) (bv 32 0x0))) (bv 2 0x1)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (bv 32 0xffffff00)) (& (var v0) (bv 32 0xff)))) (branch (== (cast 2 false (+ (var v1) (bv 32 0x0))) (bv 2 0x2)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (bv 32 0xffff0000)) (& (var v0) (bv 32 0xffff)))) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (bv 32 0xff000000)) (& (var v0) (bv 32 0xffffff))))))) +dE "lwr v0, 3(v1)" 98620003 0x400b88 (branch (== (cast 2 false (+ (var v1) (bv 32 0x3))) (bv 2 0x0)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (bv 32 0xff)) (& (var v0) (bv 32 0xffffff00)))) (branch (== (cast 2 false (+ (var v1) (bv 32 0x3))) (bv 2 0x1)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (bv 32 0xffff)) (& (var v0) (bv 32 0xffff0000)))) (branch (== (cast 2 false (+ (var v1) (bv 32 0x3))) (bv 2 0x2)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (bv 32 0xffffff)) (& (var v0) (bv 32 0xff000000)))) (set v0 (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x3)) (bv 32 0xfffffffc)))))))) +dE "ori v1, v1, 0xffff" 3463ffff 0x400b90 (set v1 (| (var v1) (bv 32 0xffff))) +dE "and v0, v0, v1" 00431024 0x400b94 (set v0 (& (var v0) (var v1))) +dE "lwl v0, 4(v1)" 88620004 0x400bc0 (branch (== (cast 2 false (+ (var v1) (bv 32 0x4))) (bv 2 0x0)) (set v0 (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x4)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x4)) (bv 32 0xfffffffc))))) (branch (== (cast 2 false (+ (var v1) (bv 32 0x4))) (bv 2 0x1)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x4)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x4)) (bv 32 0xfffffffc)))) (bv 32 0xffffff00)) (& (var v0) (bv 32 0xff)))) (branch (== (cast 2 false (+ (var v1) (bv 32 0x4))) (bv 2 0x2)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x4)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x4)) (bv 32 0xfffffffc)))) (bv 32 0xffff0000)) (& (var v0) (bv 32 0xffff)))) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x4)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x4)) (bv 32 0xfffffffc)))) (bv 32 0xff000000)) (& (var v0) (bv 32 0xffffff))))))) +dE "lwr v0, 7(v1)" 98620007 0x400bc8 (branch (== (cast 2 false (+ (var v1) (bv 32 0x7))) (bv 2 0x0)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x7)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x7)) (bv 32 0xfffffffc)))) (bv 32 0xff)) (& (var v0) (bv 32 0xffffff00)))) (branch (== (cast 2 false (+ (var v1) (bv 32 0x7))) (bv 2 0x1)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x7)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x7)) (bv 32 0xfffffffc)))) (bv 32 0xffff)) (& (var v0) (bv 32 0xffff0000)))) (branch (== (cast 2 false (+ (var v1) (bv 32 0x7))) (bv 2 0x2)) (set v0 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x7)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x7)) (bv 32 0xfffffffc)))) (bv 32 0xffffff)) (& (var v0) (bv 32 0xff000000)))) (set v0 (cast 32 (msb (loadw 0 32 (& (+ (var v1) (bv 32 0x7)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var v1) (bv 32 0x7)) (bv 32 0xfffffffc)))))))) +dE "subu s6, v0, s0" 0050b023 0x400c68 (set s6 (- (var v0) (var s0))) +dE "sltu v0, s3, s6" 0276102b 0x400c90 (set v0 (ite (&& (ule (var s3) (var s6)) (! (== (var s3) (var s6)))) (bv 32 0x1) (bv 32 0x0))) +dE "andi v0, v0, 0xf000" 3042f000 0x400e2c (set v0 (& (var v0) (bv 32 0xf000))) +dE "sll a0, a0, 5" 00042140 0x400f48 (set a0 (cast 32 (msb (<< (var a0) (bv 5 0x5) false)) (<< (var a0) (bv 5 0x5) false))) +dE "sltu v1, v0, a0" 0044182b 0x400f58 (set v1 (ite (&& (ule (var v0) (var a0)) (! (== (var v0) (var a0)))) (bv 32 0x1) (bv 32 0x0))) +dE "sltiu v1, s2, 0x20" 2e430020 0x400fa0 (set v1 (ite (&& (ule (var s2) (bv 32 0x20)) (! (== (var s2) (bv 32 0x20)))) (bv 32 0x1) (bv 32 0x0))) +dE "negu v0, s5" 00151023 0x400fc8 nop +dE "divu zero, s0, s2" 0212001b 0x400fec (seq (set lo (div (var s0) (var s2))) (set hi (mod (var s0) (var s2)))) +dE "break 7" 0007000d 0x400ff0 (set CAUSE_EXC (bv 8 0x9)) +dE "mflo v0" 00001012 0x400ff8 (set v0 (var lo)) +dE "mult v0, s3" 00530018 0x401004 (seq (set hi (cast 32 (msb (cast 32 false (>> (* (cast 64 (msb (var v0)) (var v0)) (cast 64 (msb (var s3)) (var s3))) (bv 8 0x20) false))) (cast 32 false (>> (* (cast 64 (msb (var v0)) (var v0)) (cast 64 (msb (var s3)) (var s3))) (bv 8 0x20) false)))) (set lo (cast 32 (msb (cast 32 false (* (cast 64 (msb (var v0)) (var v0)) (cast 64 (msb (var s3)) (var s3))))) (cast 32 false (* (cast 64 (msb (var v0)) (var v0)) (cast 64 (msb (var s3)) (var s3))))))) +dE "mflo s4" 0000a012 0x401008 (set s4 (var lo)) +dE "and v1, v1, v0" 00621824 0x401054 (set v1 (& (var v1) (var v0))) +dE "negu v0, v0" 00021023 0x4010b4 nop +dE "sltiu v0, v0, -0xfff" 2c42f001 0x4010b8 (set v0 (ite (&& (ule (var v0) (bv 32 0xfffff001)) (! (== (var v0) (bv 32 0xfffff001)))) (bv 32 0x1) (bv 32 0x0))) +dE "divu zero, s0, s3" 0213001b 0x4010d8 (seq (set lo (div (var s0) (var s3))) (set hi (mod (var s0) (var s3)))) +dE "mfhi s3" 00009810 0x40115c (set s3 (var hi)) +dE "lbu v0, (v0)" 90420000 0x4012d4 (set v0 (cast 32 false (loadw 0 8 (+ (var v0) (bv 32 0x0))))) +dE "sll v1, a1, 4" 00051900 0x401310 (set v1 (cast 32 (msb (<< (var a1) (bv 5 0x4) false)) (<< (var a1) (bv 5 0x4) false))) +dE "sb v1, (v0)" a0430000 0x4016d4 (storew 0 (+ (var v0) (bv 32 0x0)) (cast 8 false (var v1))) +dE "sltiu v1, v0, -0xfff" 2c43f001 0x401a10 (set v1 (ite (&& (ule (var v0) (bv 32 0xfffff001)) (! (== (var v0) (bv 32 0xfffff001)))) (bv 32 0x1) (bv 32 0x0))) +dE "xori a1, s0, 0x80" 3a050080 0x401aa4 (set a1 (^ (var s0) (bv 32 0x80))) +dE "xori a1, a1, 0x81" 38a50081 0x401b20 (set a1 (^ (var a1) (bv 32 0x81))) +dE "lbu v0, -0x72d8(v1)" 90628d28 0x401b50 (set v0 (cast 32 false (loadw 0 8 (+ (var v1) (bv 32 0xffff8d28))))) +dE "srl v0, v0, 3" 000210c2 0x401e20 (set v0 (>> (var v0) (bv 5 0x3) false)) +dE "andi v0, v0, 0xf8" 304200f8 0x401ed0 (set v0 (& (var v0) (bv 32 0xf8))) +dE "andi v1, v0, 7" 30430007 0x401f38 (set v1 (& (var v0) (bv 32 0x7))) +dE "srl v1, v1, 0xc" 00031b02 0x401f4c (set v1 (>> (var v1) (bv 5 0xc) false)) +dE "xor v0, v1, a3" 00671026 0x401f60 (set v0 (^ (var v1) (var a3))) +dE "xori a1, v0, 0xff" 384500ff 0x4020b0 (set a1 (^ (var v0) (bv 32 0xff))) +dE "or v0, a0, a1" 00851025 0x402100 (set v0 (| (var a0) (var a1))) +dE "or v0, v0, v1" 00431025 0x402110 (set v0 (| (var v0) (var v1))) +dE "negu v1, a1" 00051823 0x402144 nop +dE "mult v1, a2" 00660018 0x4023cc (seq (set hi (cast 32 (msb (cast 32 false (>> (* (cast 64 (msb (var v1)) (var v1)) (cast 64 (msb (var a2)) (var a2))) (bv 8 0x20) false))) (cast 32 false (>> (* (cast 64 (msb (var v1)) (var v1)) (cast 64 (msb (var a2)) (var a2))) (bv 8 0x20) false)))) (set lo (cast 32 (msb (cast 32 false (* (cast 64 (msb (var v1)) (var v1)) (cast 64 (msb (var a2)) (var a2))))) (cast 32 false (* (cast 64 (msb (var v1)) (var v1)) (cast 64 (msb (var a2)) (var a2))))))) +dE "mflo v1" 00001812 0x4023d4 (set v1 (var lo)) +dE "xor a0, v1, a1" 00652026 0x40261c (set a0 (^ (var v1) (var a1))) +dE "mult a2, v1" 00c30018 0x402650 (seq (set hi (cast 32 (msb (cast 32 false (>> (* (cast 64 (msb (var a2)) (var a2)) (cast 64 (msb (var v1)) (var v1))) (bv 8 0x20) false))) (cast 32 false (>> (* (cast 64 (msb (var a2)) (var a2)) (cast 64 (msb (var v1)) (var v1))) (bv 8 0x20) false)))) (set lo (cast 32 (msb (cast 32 false (* (cast 64 (msb (var a2)) (var a2)) (cast 64 (msb (var v1)) (var v1))))) (cast 32 false (* (cast 64 (msb (var a2)) (var a2)) (cast 64 (msb (var v1)) (var v1))))))) +dE "ori a0, s1, 1" 36240001 0x402b00 (set a0 (| (var s1) (bv 32 0x1))) +dE "xor t1, s4, t0" 02884826 0x402b64 (set t1 (^ (var s4) (var t0))) +dE "ori s1, s1, 1" 36310001 0x402bcc (set s1 (| (var s1) (bv 32 0x1))) +dE "or v1, v1, a0" 00641825 0x402cd0 (set v1 (| (var v1) (var a0))) +dE "slti v1, v1, 2" 28630002 0x4032d8 (set v1 (ite (&& (sle (var v1) (bv 32 0x2)) (! (== (var v1) (bv 32 0x2)))) (bv 32 0x1) (bv 32 0x0))) +dE "slti v1, a1, 2" 28a30002 0x4039f8 (set v1 (ite (&& (sle (var a1) (bv 32 0x2)) (! (== (var a1) (bv 32 0x2)))) (bv 32 0x1) (bv 32 0x0))) +dE "slt a3, a1, a2" 00a6382a 0x403d54 (set a3 (ite (&& (sle (var a1) (var a2)) (! (== (var a1) (var a2)))) (bv 32 0x1) (bv 32 0x0))) +dE "lhu a3, (a0)" 94870000 0x4040f0 (set a3 (cast 32 false (loadw 0 16 (+ (var a0) (bv 32 0x0))))) +dE "sh a3, (a0)" a4870000 0x4045f8 (storew 0 (+ (var a0) (bv 32 0x0)) (cast 16 false (var a3))) +dE "lb s5, 0x20(sp)" 83b50020 0x404b7c (set s5 (cast 32 (msb (loadw 0 8 (+ (var sp) (bv 32 0x20)))) (loadw 0 8 (+ (var sp) (bv 32 0x20))))) +dE "slt v0, v0, v1" 0043102a 0x404e4c (set v0 (ite (&& (sle (var v0) (var v1)) (! (== (var v0) (var v1)))) (bv 32 0x1) (bv 32 0x0))) +dE "lhu a0, (v1)" 94640000 0x40574c (set a0 (cast 32 false (loadw 0 16 (+ (var v1) (bv 32 0x0))))) +dE "lhu v1, (a0)" 94830000 0x4057a4 (set v1 (cast 32 false (loadw 0 16 (+ (var a0) (bv 32 0x0))))) +dE "sh v1, (a0)" a4830000 0x4057bc (storew 0 (+ (var a0) (bv 32 0x0)) (cast 16 false (var v1))) +dE "sh a3, (v0)" a4470000 0x405d64 (storew 0 (+ (var v0) (bv 32 0x0)) (cast 16 false (var a3))) +dE "sllv a3, t4, a3" 00ec3804 0x405d98 (set a3 (cast 32 (msb (<< (var t4) (& (var a3) (bv 32 0x1f)) false)) (<< (var t4) (& (var a3) (bv 32 0x1f)) false))) +dE "sllv v1, a3, v1" 00671804 0x405e88 (set v1 (cast 32 (msb (<< (var a3) (& (var v1) (bv 32 0x1f)) false)) (<< (var a3) (& (var v1) (bv 32 0x1f)) false))) +dE "nor t1, zero, v1" 00034827 0x405ed4 (set t1 (~ (| (var zero) (var v1)))) +dE "divu zero, v0, s1" 0051001b 0x406d80 (seq (set lo (div (var v0) (var s1))) (set hi (mod (var v0) (var s1)))) +dE "mfhi v1" 00001810 0x406d88 (set v1 (var hi)) +dE "mfhi s1" 00008810 0x406e4c (set s1 (var hi)) +dE "multu a0, a1" 00850019 0x40883c (seq (set hi (cast 32 (msb (cast 32 false (>> (* (cast 64 false (var a0)) (cast 64 false (var a1))) (bv 8 0x20) false))) (cast 32 false (>> (* (cast 64 false (var a0)) (cast 64 false (var a1))) (bv 8 0x20) false)))) (set lo (cast 32 (msb (cast 32 false (* (cast 64 false (var a0)) (cast 64 false (var a1))))) (cast 32 false (* (cast 64 false (var a0)) (cast 64 false (var a1))))))) +dE "slt v0, s3, s1" 0271102a 0x408efc (set v0 (ite (&& (sle (var s3) (var s1)) (! (== (var s3) (var s1)))) (bv 32 0x1) (bv 32 0x0))) +dE "jr v0" 00400008 0x409748 (jmp (var v0)) +dE "lwl t8, (a1)" 88b80000 0x409ac8 (branch (== (cast 2 false (+ (var a1) (bv 32 0x0))) (bv 2 0x0)) (set t8 (cast 32 (msb (loadw 0 32 (& (+ (var a1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var a1) (bv 32 0x0)) (bv 32 0xfffffffc))))) (branch (== (cast 2 false (+ (var a1) (bv 32 0x0))) (bv 2 0x1)) (set t8 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var a1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var a1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (bv 32 0xffffff00)) (& (var t8) (bv 32 0xff)))) (branch (== (cast 2 false (+ (var a1) (bv 32 0x0))) (bv 2 0x2)) (set t8 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var a1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var a1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (bv 32 0xffff0000)) (& (var t8) (bv 32 0xffff)))) (set t8 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var a1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var a1) (bv 32 0x0)) (bv 32 0xfffffffc)))) (bv 32 0xff000000)) (& (var t8) (bv 32 0xffffff))))))) +dE "swl t8, (a0)" a8980000 0x409ad0 (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x0)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (var t8)) (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x1)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 24 false (>> (var t8) (bv 8 0x8) false))) (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x2)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 16 false (>> (var t8) (bv 8 0x10) false))) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 8 false (>> (var t8) (bv 8 0x18) false)))))) +dE "lb v1, (a1)" 80a30000 0x409bf8 (set v1 (cast 32 (msb (loadw 0 8 (+ (var a1) (bv 32 0x0)))) (loadw 0 8 (+ (var a1) (bv 32 0x0))))) +dE "lwr v1, 3(a1)" 98a30003 0x409c60 (branch (== (cast 2 false (+ (var a1) (bv 32 0x3))) (bv 2 0x0)) (set v1 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (bv 32 0xff)) (& (var v1) (bv 32 0xffffff00)))) (branch (== (cast 2 false (+ (var a1) (bv 32 0x3))) (bv 2 0x1)) (set v1 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (bv 32 0xffff)) (& (var v1) (bv 32 0xffff0000)))) (branch (== (cast 2 false (+ (var a1) (bv 32 0x3))) (bv 2 0x2)) (set v1 (| (& (cast 32 (msb (loadw 0 32 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (bv 32 0xffffff)) (& (var v1) (bv 32 0xff000000)))) (set v1 (cast 32 (msb (loadw 0 32 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)))) (loadw 0 32 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)))))))) +dE "swl v1, (a0)" a8830000 0x409c68 (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x0)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (var v1)) (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x1)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 24 false (>> (var v1) (bv 8 0x8) false))) (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x2)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 16 false (>> (var v1) (bv 8 0x10) false))) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 8 false (>> (var v1) (bv 8 0x18) false)))))) +dE "swl a1, (a0)" a8850000 0x409e48 (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x0)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (var a1)) (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x1)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 24 false (>> (var a1) (bv 8 0x8) false))) (branch (== (& (+ (var a0) (bv 32 0x0)) (bv 32 0x3)) (bv 32 0x2)) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (storew 0 (& (+ (var a0) (bv 32 0x0)) (bv 32 0xfffffffc)) (cast 8 false (>> (var a1) (bv 8 0x18) false)))))) +dE "swc1 f21, 0x38(a0)" e4950038 0x40e92c (storew 0 (+ (var a0) (bv 32 0x38)) (var f21)) +dE "swc1 f20, 0x3c(a0)" e494003c 0x40e930 (storew 0 (+ (var a0) (bv 32 0x3c)) (var f20)) +dE "swc1 f23, 0x40(a0)" e4970040 0x40e934 (storew 0 (+ (var a0) (bv 32 0x40)) (var f23)) +dE "multu v1, s3" 00730019 0x40fe6c (seq (set hi (cast 32 (msb (cast 32 false (>> (* (cast 64 false (var v1)) (cast 64 false (var s3))) (bv 8 0x20) false))) (cast 32 false (>> (* (cast 64 false (var v1)) (cast 64 false (var s3))) (bv 8 0x20) false)))) (set lo (cast 32 (msb (cast 32 false (* (cast 64 false (var v1)) (cast 64 false (var s3))))) (cast 32 false (* (cast 64 false (var v1)) (cast 64 false (var s3))))))) +dE "srlv v1, a2, a3" 00e61806 0x40fe7c (set v1 (>> (var a2) (cast 5 false (var a3)) false)) +dE "sllv v1, v1, a2" 00c31804 0x40ffec (set v1 (cast 32 (msb (<< (var v1) (& (var a2) (bv 32 0x1f)) false)) (<< (var v1) (& (var a2) (bv 32 0x1f)) false))) +dE "nor t2, zero, t7" 000f5027 0x410010 (set t2 (~ (| (var zero) (var t7)))) +dE "srlv a0, a0, t7" 01e42006 0x410014 (set a0 (>> (var a0) (cast 5 false (var t7)) false)) +dE "multu a3, t1" 00e90019 0x410018 (seq (set hi (cast 32 (msb (cast 32 false (>> (* (cast 64 false (var a3)) (cast 64 false (var t1))) (bv 8 0x20) false))) (cast 32 false (>> (* (cast 64 false (var a3)) (cast 64 false (var t1))) (bv 8 0x20) false)))) (set lo (cast 32 (msb (cast 32 false (* (cast 64 false (var a3)) (cast 64 false (var t1))))) (cast 32 false (* (cast 64 false (var a3)) (cast 64 false (var t1))))))) +dE "srlv t3, t3, a2" 00cb5806 0x4100d4 (set t3 (>> (var t3) (cast 5 false (var a2)) false)) +dE "nor t2, zero, a2" 00065027 0x410288 (set t2 (~ (| (var zero) (var a2)))) +dE "lwc1 f0, 4(v0)" c4400004 0x410f84 (set f0 (loadw 0 32 (+ (var v0) (bv 32 0x4)))) +dE "lwc1 f1, -8(v0)" c441fff8 0x410f8c (set f1 (loadw 0 32 (+ (var v0) (bv 32 0xfffffff8)))) +dE "lwc1 f1, (v0)" c4410000 0x41104c (set f1 (loadw 0 32 (+ (var v0) (bv 32 0x0)))) +dE "lh v0, 2(v0)" 84420002 0x412720 (set v0 (cast 32 (msb (loadw 0 16 (+ (var v0) (bv 32 0x2)))) (loadw 0 16 (+ (var v0) (bv 32 0x2))))) +dE "lh v1, 0xc(s0)" 8603000c 0x414f44 (set v1 (cast 32 (msb (loadw 0 16 (+ (var s0) (bv 32 0xc)))) (loadw 0 16 (+ (var s0) (bv 32 0xc))))) +dE "lh v0, 0xc(s0)" 8602000c 0x414f7c (set v0 (cast 32 (msb (loadw 0 16 (+ (var s0) (bv 32 0xc)))) (loadw 0 16 (+ (var s0) (bv 32 0xc))))) +dE "swr a2, 3(a1)" b8a60003 0x419fd4 (branch (== (& (+ (var a1) (bv 32 0x3)) (bv 32 0x3)) (bv 32 0x0)) (storew 0 (+ (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)) (bv 32 0x3)) (cast 8 false (var a2))) (branch (== (& (+ (var a1) (bv 32 0x3)) (bv 32 0x3)) (bv 32 0x1)) (storew 0 (+ (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)) (bv 32 0x2)) (cast 16 false (var a2))) (branch (== (& (+ (var a1) (bv 32 0x3)) (bv 32 0x3)) (bv 32 0x2)) (storew 0 (+ (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)) (bv 32 0x1)) (cast 24 false (var a2))) (storew 0 (& (+ (var a1) (bv 32 0x3)) (bv 32 0xfffffffc)) (var a2))))) +dE "swr v1, 7(a1)" b8a30007 0x419fdc (branch (== (& (+ (var a1) (bv 32 0x7)) (bv 32 0x3)) (bv 32 0x0)) (storew 0 (+ (& (+ (var a1) (bv 32 0x7)) (bv 32 0xfffffffc)) (bv 32 0x3)) (cast 8 false (var v1))) (branch (== (& (+ (var a1) (bv 32 0x7)) (bv 32 0x3)) (bv 32 0x1)) (storew 0 (+ (& (+ (var a1) (bv 32 0x7)) (bv 32 0xfffffffc)) (bv 32 0x2)) (cast 16 false (var v1))) (branch (== (& (+ (var a1) (bv 32 0x7)) (bv 32 0x3)) (bv 32 0x2)) (storew 0 (+ (& (+ (var a1) (bv 32 0x7)) (bv 32 0xfffffffc)) (bv 32 0x1)) (cast 24 false (var v1))) (storew 0 (& (+ (var a1) (bv 32 0x7)) (bv 32 0xfffffffc)) (var v1))))) +dE "srav a1, a2, a1" 00a62807 0x41ef84 (set a1 (>> (var a2) (cast 5 false (var a1)) (msb (var a2)))) +dE "srav v0, v0, v1" 00621007 0x421744 (set v0 (>> (var v0) (cast 5 false (var v1)) (msb (var v0)))) +dE "swr v0, 3(s5)" baa20003 0x425964 (branch (== (& (+ (var s5) (bv 32 0x3)) (bv 32 0x3)) (bv 32 0x0)) (storew 0 (+ (& (+ (var s5) (bv 32 0x3)) (bv 32 0xfffffffc)) (bv 32 0x3)) (cast 8 false (var v0))) (branch (== (& (+ (var s5) (bv 32 0x3)) (bv 32 0x3)) (bv 32 0x1)) (storew 0 (+ (& (+ (var s5) (bv 32 0x3)) (bv 32 0xfffffffc)) (bv 32 0x2)) (cast 16 false (var v0))) (branch (== (& (+ (var s5) (bv 32 0x3)) (bv 32 0x3)) (bv 32 0x2)) (storew 0 (+ (& (+ (var s5) (bv 32 0x3)) (bv 32 0xfffffffc)) (bv 32 0x1)) (cast 24 false (var v0))) (storew 0 (& (+ (var s5) (bv 32 0x3)) (bv 32 0xfffffffc)) (var v0))))) +dE "srav a2, a2, a1" 00a63007 0x42ef54 (set a2 (>> (var a2) (cast 5 false (var a1)) (msb (var a2)))) +dE "mtc1 t3, f0" 448b0000 0x440278 nop +dE "mtc1 t2, f1" 448a0800 0x44027c nop +dE "c.un.d f0, f0" 46200031 0x440284 nop +dE "mtc1 t3, f2" 448b1000 0x4402a4 nop +dE "c.ule.d f2, f0" 46201037 0x4402b4 nop +dEB "cfc1 v1, c1_fcsr" 4443f800 0x440878 nop +dE "div zero, v0, a2" 0046001a 0x440a1c (seq (set lo (sdiv (var v0) (var a2))) (set hi (smod (var v0) (var a2)))) +dE "div zero, v1, v0" 0062001a 0x440a3c (seq (set lo (sdiv (var v1) (var v0))) (set hi (smod (var v1) (var v0)))) +dEB "cfc1 v0, c1_fcsr" 4442f800 0x442da8 nop +dE "div zero, a0, v0" 0082001a 0x445acc (seq (set lo (sdiv (var a0) (var v0))) (set hi (smod (var a0) (var v0)))) +dE "break" 0000000d 0x4583cc (set CAUSE_EXC (bv 8 0x9)) +dEB "ctc1 at, c1_fcsr" 44c1f800 0x400d28 nop +dE "cvt.w.d f0, f0" 46200024 0x400d30 nop +dEB "ctc1 v0, c1_fcsr" 44c2f800 0x400d34 nop +dE "mfc1 a0, f0" 44040000 0x400d3c nop +dE "cvt.d.w f0, f0" 46800021 0x400e04 nop +dE "sub.d f0, f2, f0" 46201001 0x400e18 (set f0 (fbits (+. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "mul.d f0, f2, f0" 46201002 0x400e4c (set f0 (fbits (*. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "mfc1 a3, f2" 44071000 0x4014e8 nop +dE "mfc1 a2, f3" 44061800 0x4014ec nop +dE "mul.s f0, f2, f0" 46001002 0x4006fc (set f0 (fbits (*. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "mul.s f4, f4, f0" 46002102 0x40071c (set f4 (fbits (*. rne (float 0 (var f4) ) (float 0 (var f0) )))) +dE "mul.s f0, f4, f0" 46002002 0x400730 (set f0 (fbits (*. rne (float 0 (var f4) ) (float 0 (var f0) )))) +dE "add.s f0, f2, f0" 46001000 0x400734 (set f0 (fbits (+. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "c.eq.s f0, f2" 46020032 0x400750 nop +dE "sub.s f2, f2, f0" 46001081 0x400774 (set f2 (fbits (+. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "div.s f2, f2, f0" 46001083 0x400780 (set f2 (fbits (/. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "add.s f2, f2, f0" 46001080 0x4007d0 (set f2 (fbits (+. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "cvt.d.s f4, f0" 46000121 0x400870 nop +dE "cvt.d.s f0, f0" 46000021 0x40087c nop +dE "cvt.d.s f2, f2" 460010a1 0x400888 nop +dE "cvt.s.w f0, f0" 46800020 0x4009fc nop +dE "sub.s f0, f2, f0" 46001001 0x400aa0 (set f0 (fbits (+. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "mov.d f12, f0" 46200306 0x40141c (set f12 (var f0)) +dE "c.le.d f2, f0" 4620103e 0x40143c nop +dEB "cfc1 a0, c1_fcsr" 4444f800 0x40144c nop +dEB "ctc1 a0, c1_fcsr" 44c4f800 0x40146c nop +dE "sub.d f0, f0, f2" 46220001 0x401480 (set f0 (fbits (+. rne (float 0 (var f0) ) (float 0 (var f2) )))) +dE "cvt.d.w f2, f0" 468000a1 0x400748 nop +dE "div.d f0, f2, f0" 46201003 0x400760 (set f0 (fbits (/. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "mov.s f12, f0" 46000306 0x400834 (set f12 (var f0)) +dE "add.s f6, f0, f0" 46000180 0x400b14 (set f6 (fbits (+. rne (float 0 (var f0) ) (float 0 (var f0) )))) +dE "mov.s f14, f0" 46000386 0x400b70 (set f14 (var f0)) +dE "mov.s f12, f6" 46003306 0x400b74 (set f12 (var f6)) +dE "c.lt.d f2, f0" 4620103c 0x401128 nop +dE "c.eq.s f2, f0" 46001032 0x400c18 nop +dE "div.s f0, f2, f0" 46001003 0x400c3c (set f0 (fbits (/. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "div.s f0, f4, f0" 46002003 0x400e94 (set f0 (fbits (/. rne (float 0 (var f4) ) (float 0 (var f0) )))) +dE "cvt.s.d f0, f0" 46200020 0x4012cc nop +dE "add.d f2, f0, f0" 46200080 0x400880 (set f2 (fbits (+. rne (float 0 (var f0) ) (float 0 (var f0) )))) +dE "mul.d f2, f2, f0" 46201082 0x400898 (set f2 (fbits (*. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "add.d f0, f0, f4" 46240000 0x4008d4 (set f0 (fbits (+. rne (float 0 (var f0) ) (float 0 (var f4) )))) +dE "mov.d f2, f0" 46200086 0x400954 (set f2 (var f0)) +dE "mul.d f20, f2, f0" 46201502 0x400968 (set f20 (fbits (*. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "add.d f2, f20, f0" 4620a080 0x4009d0 (set f2 (fbits (+. rne (float 0 (var f20) ) (float 0 (var f0) )))) +dE "sub.d f2, f20, f0" 4620a081 0x400a98 (set f2 (fbits (+. rne (float 0 (var f20) ) (float 0 (var f0) )))) +dE "mov.d f20, f0" 46200506 0x400750 (set f20 (var f0)) +dE "cvt.d.w f2, f2" 468010a1 0x400bcc nop +dE "div.d f2, f2, f0" 46201083 0x4006fc (set f2 (fbits (/. rne (float 0 (var f2) ) (float 0 (var f0) )))) +dE "c.eq.d f2, f0" 46201032 0x4007f0 nop +dE "c.lt.d f20, f0" 4620a03c 0x4007d0 nop +dE "div.d f0, f0, f2" 46220003 0x400d10 (set f0 (fbits (/. rne (float 0 (var f0) ) (float 0 (var f2) )))) +dE "c.lt.d f0, f2" 4622003c 0x4018dc nop +dE "c.le.d f0, f2" 4622003e 0x40090c nop +dE "cvt.s.w f2, f0" 468000a0 0x4016c8 nop +dE "c.lt.s f0, f2" 4602003c 0x4008d0 nop +dE "sub.s f4, f4, f0" 46002101 0x4007d8 (set f4 (fbits (+. rne (float 0 (var f4) ) (float 0 (var f0) )))) +dE "c.eq.d f0, f2" 46220032 0x400f74 nop +dE "c.un.d f2, f2" 46221031 0x401b9c nop +dE "c.ule.d f6, f4" 46243037 0x401bdc nop +dE "c.un.d f4, f4" 46242031 0x401d08 nop +dE "c.eq.d f4, f6" 46262032 0x402524 nop +dE "c.ule.d f8, f4" 46244037 0x4029d4 nop +dE "c.ult.d f4, f8" 46282035 0x402a08 nop +dE "cvt.s.w f20, f0" 46800520 0x400960 nop +dE "mtlo v0" 00400013 0x400690 (set lo (var v0)) +dE "cvt.w.s f0, f0" 46000024 0x400834 nop +dE "c.lt.s f2, f0" 4600103c 0x4008b0 nop