diff --git a/librz/analysis/arch/pic/pic16f_memmaps/pic16f882.h b/librz/analysis/arch/pic/pic16f_memmaps/pic16f882.h deleted file mode 100644 index b10ed4d63b1..00000000000 --- a/librz/analysis/arch/pic/pic16f_memmaps/pic16f882.h +++ /dev/null @@ -1,540 +0,0 @@ -// SPDX-FileCopyrightText: 2023 Siddharth Mishra -// SPDX-License-Identifier: LGPL-3.0-only - -/** - * This file describes the memory map of PICF16882 device in PIC16F family. - * */ - -#ifndef RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F882_H -#define RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F882_H - -#include "regtypes.h" - -// clang-format off -PicMidrangeRegType pic16f882_reg_map[] = { - /* BANK 0 */ - REG_INDF, /* 0x00 */ - REG_TMR0, /* 0x01 */ - REG_PCL, /* 0x02 */ - REG_STATUS, /* 0x03 */ - REG_FSR, /* 0x04 */ - REG_PORTA, /* 0x05 */ - REG_PORTB, /* 0x06 */ - REG_PORTC, /* 0x07 */ - REG_UNIMPLEMENTED, /* 0x08 */ - REG_PORTE, /* 0x09 */ - REG_PCLATH, /* 0x0a */ - REG_INTCON, /* 0x0b */ - REG_PIR1, /* 0x0c */ - REG_PIR2, /* 0x0d */ - REG_TMR1L, /* 0x0e */ - REG_TMR1H, /* 0x0f */ - REG_T1CON, /* 0x10 */ - REG_TMR2, /* 0x11 */ - REG_T2CON, /* 0x12 */ - REG_SSPBUF, /* 0x13 */ - REG_SSPCON, /* 0x14 */ - REG_CCPR1L, /* 0x15 */ - REG_CCPR1H, /* 0x16 */ - REG_CCP1CON, /* 0x17 */ - REG_RCSTA, /* 0x18 */ - REG_TXREG, /* 0x19 */ - REG_RCREG, /* 0x1a */ - REG_CCPR2L, /* 0x1b */ - REG_CCPR2H, /* 0x1c */ - REG_CCP2CON, /* 0x1d */ - REG_ADRESH, /* 0x1e */ - REG_ADCON0, /* 0x1f */ - REG_FREG, /* 0x20 */ - REG_FREG, /* 0x21 */ - REG_FREG, /* 0x22 */ - REG_FREG, /* 0x23 */ - REG_FREG, /* 0x24 */ - REG_FREG, /* 0x25 */ - REG_FREG, /* 0x26 */ - REG_FREG, /* 0x27 */ - REG_FREG, /* 0x28 */ - REG_FREG, /* 0x29 */ - REG_FREG, /* 0x2a */ - REG_FREG, /* 0x2b */ - REG_FREG, /* 0x2c */ - REG_FREG, /* 0x2d */ - REG_FREG, /* 0x2e */ - REG_FREG, /* 0x2f */ - REG_FREG, /* 0x30 */ - REG_FREG, /* 0x31 */ - REG_FREG, /* 0x32 */ - REG_FREG, /* 0x33 */ - REG_FREG, /* 0x34 */ - REG_FREG, /* 0x35 */ - REG_FREG, /* 0x36 */ - REG_FREG, /* 0x37 */ - REG_FREG, /* 0x38 */ - REG_FREG, /* 0x39 */ - REG_FREG, /* 0x3a */ - REG_FREG, /* 0x3b */ - REG_FREG, /* 0x3c */ - REG_FREG, /* 0x3d */ - REG_FREG, /* 0x3e */ - REG_FREG, /* 0x3f */ - REG_FREG, /* 0x40 */ - REG_FREG, /* 0x41 */ - REG_FREG, /* 0x42 */ - REG_FREG, /* 0x43 */ - REG_FREG, /* 0x44 */ - REG_FREG, /* 0x45 */ - REG_FREG, /* 0x46 */ - REG_FREG, /* 0x47 */ - REG_FREG, /* 0x48 */ - REG_FREG, /* 0x49 */ - REG_FREG, /* 0x4a */ - REG_FREG, /* 0x4b */ - REG_FREG, /* 0x4c */ - REG_FREG, /* 0x4d */ - REG_FREG, /* 0x4e */ - REG_FREG, /* 0x4f */ - REG_FREG, /* 0x50 */ - REG_FREG, /* 0x51 */ - REG_FREG, /* 0x52 */ - REG_FREG, /* 0x53 */ - REG_FREG, /* 0x54 */ - REG_FREG, /* 0x55 */ - REG_FREG, /* 0x56 */ - REG_FREG, /* 0x57 */ - REG_FREG, /* 0x58 */ - REG_FREG, /* 0x59 */ - REG_FREG, /* 0x5a */ - REG_FREG, /* 0x5b */ - REG_FREG, /* 0x5c */ - REG_FREG, /* 0x5d */ - REG_FREG, /* 0x5e */ - REG_FREG, /* 0x5f */ - REG_FREG, /* 0x60 */ - REG_FREG, /* 0x61 */ - REG_FREG, /* 0x62 */ - REG_FREG, /* 0x63 */ - REG_FREG, /* 0x64 */ - REG_FREG, /* 0x65 */ - REG_FREG, /* 0x66 */ - REG_FREG, /* 0x67 */ - REG_FREG, /* 0x68 */ - REG_FREG, /* 0x69 */ - REG_FREG, /* 0x6a */ - REG_FREG, /* 0x6b */ - REG_FREG, /* 0x6c */ - REG_FREG, /* 0x6d */ - REG_FREG, /* 0x6e */ - REG_FREG, /* 0x6f */ - REG_FREG, /* 0x70 */ - REG_FREG, /* 0x71 */ - REG_FREG, /* 0x72 */ - REG_FREG, /* 0x73 */ - REG_FREG, /* 0x74 */ - REG_FREG, /* 0x75 */ - REG_FREG, /* 0x76 */ - REG_FREG, /* 0x77 */ - REG_FREG, /* 0x78 */ - REG_FREG, /* 0x79 */ - REG_FREG, /* 0x7a */ - REG_FREG, /* 0x7b */ - REG_FREG, /* 0x7c */ - REG_FREG, /* 0x7d */ - REG_FREG, /* 0x7e */ - REG_FREG, /* 0x7f */ - - /* BANK1 */ - - REG_INDF, /* 0x80 */ - REG_OPTION_REG, /* 0x81 */ - REG_PCL, /* 0x82 */ - REG_STATUS, /* 0x83 */ - REG_FSR, /* 0x84 */ - REG_TRISA, /* 0x85 */ - REG_TRISB, /* 0x86 */ - REG_TRISC, /* 0x87 */ - REG_UNIMPLEMENTED, /* 0x88 */ - REG_TRISE, /* 0x89 */ - REG_PCLATH, /* 0x8a */ - REG_INTCON, /* 0x8b */ - REG_PIE1, /* 0x8c */ - REG_PIE2, /* 0x8d */ - REG_PCON, /* 0x8e */ - REG_OSCCON, /* 0x8f */ - REG_OSCTUNE, /* 0x90 */ - REG_SSPCON2, /* 0x91 */ - REG_PR2, /* 0x92 */ - REG_SSPADD, /* 0x93 */ - REG_SSPSTAT, /* 0x94 */ - REG_WPUB, /* 0x95 */ - REG_IOCB, /* 0x96 */ - REG_VRCON, /* 0x97 */ - REG_RCSTA, /* 0x98 */ - REG_TXSTA, /* 0x99 */ - REG_SPBRG, /* 0x9a */ - REG_SPBRGH, /* 0x9b */ - REG_PWM1CON, /* 0x9c */ - REG_ECCPAS, /* 0x9d */ - REG_ADRESL, /* 0x9e */ - REG_ADCON1, /* 0x9f */ - REG_FREG, /* 0xa0 */ - REG_FREG, /* 0xa1 */ - REG_FREG, /* 0xa2 */ - REG_FREG, /* 0xa3 */ - REG_FREG, /* 0xa4 */ - REG_FREG, /* 0xa5 */ - REG_FREG, /* 0xa6 */ - REG_FREG, /* 0xa7 */ - REG_FREG, /* 0xa8 */ - REG_FREG, /* 0xa9 */ - REG_FREG, /* 0xaa */ - REG_FREG, /* 0xab */ - REG_FREG, /* 0xac */ - REG_FREG, /* 0xad */ - REG_FREG, /* 0xae */ - REG_FREG, /* 0xaf */ - REG_FREG, /* 0xb0 */ - REG_FREG, /* 0xb1 */ - REG_FREG, /* 0xb2 */ - REG_FREG, /* 0xb3 */ - REG_FREG, /* 0xb4 */ - REG_FREG, /* 0xb5 */ - REG_FREG, /* 0xb6 */ - REG_FREG, /* 0xb7 */ - REG_FREG, /* 0xb8 */ - REG_FREG, /* 0xb9 */ - REG_FREG, /* 0xba */ - REG_FREG, /* 0xbb */ - REG_FREG, /* 0xbc */ - REG_FREG, /* 0xbd */ - REG_FREG, /* 0xbe */ - REG_FREG, /* 0xbf */ - REG_UNIMPLEMENTED, /* 0xc0 */ - REG_UNIMPLEMENTED, /* 0xc1 */ - REG_UNIMPLEMENTED, /* 0xc2 */ - REG_UNIMPLEMENTED, /* 0xc3 */ - REG_UNIMPLEMENTED, /* 0xc4 */ - REG_UNIMPLEMENTED, /* 0xc5 */ - REG_UNIMPLEMENTED, /* 0xc6 */ - REG_UNIMPLEMENTED, /* 0xc7 */ - REG_UNIMPLEMENTED, /* 0xc8 */ - REG_UNIMPLEMENTED, /* 0xc9 */ - REG_UNIMPLEMENTED, /* 0xca */ - REG_UNIMPLEMENTED, /* 0xcb */ - REG_UNIMPLEMENTED, /* 0xcc */ - REG_UNIMPLEMENTED, /* 0xcd */ - REG_UNIMPLEMENTED, /* 0xce */ - REG_UNIMPLEMENTED, /* 0xcf */ - REG_UNIMPLEMENTED, /* 0xd0 */ - REG_UNIMPLEMENTED, /* 0xd1 */ - REG_UNIMPLEMENTED, /* 0xd2 */ - REG_UNIMPLEMENTED, /* 0xd3 */ - REG_UNIMPLEMENTED, /* 0xd4 */ - REG_UNIMPLEMENTED, /* 0xd5 */ - REG_UNIMPLEMENTED, /* 0xd6 */ - REG_UNIMPLEMENTED, /* 0xd7 */ - REG_UNIMPLEMENTED, /* 0xd8 */ - REG_UNIMPLEMENTED, /* 0xd9 */ - REG_UNIMPLEMENTED, /* 0xda */ - REG_UNIMPLEMENTED, /* 0xdb */ - REG_UNIMPLEMENTED, /* 0xdc */ - REG_UNIMPLEMENTED, /* 0xdd */ - REG_UNIMPLEMENTED, /* 0xde */ - REG_UNIMPLEMENTED, /* 0xdf */ - REG_UNIMPLEMENTED, /* 0xe0 */ - REG_UNIMPLEMENTED, /* 0xe1 */ - REG_UNIMPLEMENTED, /* 0xe2 */ - REG_UNIMPLEMENTED, /* 0xe3 */ - REG_UNIMPLEMENTED, /* 0xe4 */ - REG_UNIMPLEMENTED, /* 0xe5 */ - REG_UNIMPLEMENTED, /* 0xe6 */ - REG_UNIMPLEMENTED, /* 0xe7 */ - REG_UNIMPLEMENTED, /* 0xe8 */ - REG_UNIMPLEMENTED, /* 0xe9 */ - REG_UNIMPLEMENTED, /* 0xea */ - REG_UNIMPLEMENTED, /* 0xeb */ - REG_UNIMPLEMENTED, /* 0xec */ - REG_UNIMPLEMENTED, /* 0xed */ - REG_UNIMPLEMENTED, /* 0xee */ - REG_UNIMPLEMENTED, /* 0xef */ - REG_FREG, /* 0xf0 */ - REG_FREG, /* 0xf1 */ - REG_FREG, /* 0xf2 */ - REG_FREG, /* 0xf3 */ - REG_FREG, /* 0xf4 */ - REG_FREG, /* 0xf5 */ - REG_FREG, /* 0xf6 */ - REG_FREG, /* 0xf7 */ - REG_FREG, /* 0xf8 */ - REG_FREG, /* 0xf9 */ - REG_FREG, /* 0xfa */ - REG_FREG, /* 0xfb */ - REG_FREG, /* 0xfc */ - REG_FREG, /* 0xfd */ - REG_FREG, /* 0xfe */ - REG_FREG, /* 0xff */ - - /* BANK 2 */ - - REG_INDF, /* 0x100 */ - REG_TMR0, /* 0x101 */ - REG_PCL, /* 0x102 */ - REG_STATUS, /* 0x103 */ - REG_FSR, /* 0x104 */ - REG_WDTCON, /* 0x105 */ - REG_PORTB, /* 0x106 */ - REG_CM1CON0, /* 0x107 */ - REG_CM2CON0, /* 0x108 */ - REG_CM2CON1, /* 0x109 */ - REG_PCLATH, /* 0x10a */ - REG_INTCON, /* 0x10b */ - REG_EEDAT, /* 0x10c */ - REG_EEADR, /* 0x10d */ - REG_EEDATH, /* 0x10e */ - REG_EEADRH, /* 0x10f */ - REG_UNIMPLEMENTED, /* 0x110 */ - REG_UNIMPLEMENTED, /* 0x111 */ - REG_UNIMPLEMENTED, /* 0x112 */ - REG_UNIMPLEMENTED, /* 0x113 */ - REG_UNIMPLEMENTED, /* 0x114 */ - REG_UNIMPLEMENTED, /* 0x115 */ - REG_UNIMPLEMENTED, /* 0x116 */ - REG_UNIMPLEMENTED, /* 0x117 */ - REG_UNIMPLEMENTED, /* 0x118 */ - REG_UNIMPLEMENTED, /* 0x119 */ - REG_UNIMPLEMENTED, /* 0x11a */ - REG_UNIMPLEMENTED, /* 0x11b */ - REG_UNIMPLEMENTED, /* 0x11c */ - REG_UNIMPLEMENTED, /* 0x11d */ - REG_UNIMPLEMENTED, /* 0x11e */ - REG_UNIMPLEMENTED, /* 0x11f */ - REG_UNIMPLEMENTED, /* 0x120 */ - REG_UNIMPLEMENTED, /* 0x121 */ - REG_UNIMPLEMENTED, /* 0x122 */ - REG_UNIMPLEMENTED, /* 0x123 */ - REG_UNIMPLEMENTED, /* 0x124 */ - REG_UNIMPLEMENTED, /* 0x125 */ - REG_UNIMPLEMENTED, /* 0x126 */ - REG_UNIMPLEMENTED, /* 0x127 */ - REG_UNIMPLEMENTED, /* 0x128 */ - REG_UNIMPLEMENTED, /* 0x129 */ - REG_UNIMPLEMENTED, /* 0x12a */ - REG_UNIMPLEMENTED, /* 0x12b */ - REG_UNIMPLEMENTED, /* 0x12c */ - REG_UNIMPLEMENTED, /* 0x12d */ - REG_UNIMPLEMENTED, /* 0x12e */ - REG_UNIMPLEMENTED, /* 0x12f */ - REG_UNIMPLEMENTED, /* 0x130 */ - REG_UNIMPLEMENTED, /* 0x131 */ - REG_UNIMPLEMENTED, /* 0x132 */ - REG_UNIMPLEMENTED, /* 0x133 */ - REG_UNIMPLEMENTED, /* 0x134 */ - REG_UNIMPLEMENTED, /* 0x135 */ - REG_UNIMPLEMENTED, /* 0x136 */ - REG_UNIMPLEMENTED, /* 0x137 */ - REG_UNIMPLEMENTED, /* 0x138 */ - REG_UNIMPLEMENTED, /* 0x139 */ - REG_UNIMPLEMENTED, /* 0x13a */ - REG_UNIMPLEMENTED, /* 0x13b */ - REG_UNIMPLEMENTED, /* 0x13c */ - REG_UNIMPLEMENTED, /* 0x13d */ - REG_UNIMPLEMENTED, /* 0x13e */ - REG_UNIMPLEMENTED, /* 0x13f */ - REG_UNIMPLEMENTED, /* 0x140 */ - REG_UNIMPLEMENTED, /* 0x141 */ - REG_UNIMPLEMENTED, /* 0x142 */ - REG_UNIMPLEMENTED, /* 0x143 */ - REG_UNIMPLEMENTED, /* 0x144 */ - REG_UNIMPLEMENTED, /* 0x145 */ - REG_UNIMPLEMENTED, /* 0x146 */ - REG_UNIMPLEMENTED, /* 0x147 */ - REG_UNIMPLEMENTED, /* 0x148 */ - REG_UNIMPLEMENTED, /* 0x149 */ - REG_UNIMPLEMENTED, /* 0x14a */ - REG_UNIMPLEMENTED, /* 0x14b */ - REG_UNIMPLEMENTED, /* 0x14c */ - REG_UNIMPLEMENTED, /* 0x14d */ - REG_UNIMPLEMENTED, /* 0x14e */ - REG_UNIMPLEMENTED, /* 0x14f */ - REG_UNIMPLEMENTED, /* 0x150 */ - REG_UNIMPLEMENTED, /* 0x151 */ - REG_UNIMPLEMENTED, /* 0x152 */ - REG_UNIMPLEMENTED, /* 0x153 */ - REG_UNIMPLEMENTED, /* 0x154 */ - REG_UNIMPLEMENTED, /* 0x155 */ - REG_UNIMPLEMENTED, /* 0x156 */ - REG_UNIMPLEMENTED, /* 0x157 */ - REG_UNIMPLEMENTED, /* 0x158 */ - REG_UNIMPLEMENTED, /* 0x159 */ - REG_UNIMPLEMENTED, /* 0x15a */ - REG_UNIMPLEMENTED, /* 0x15b */ - REG_UNIMPLEMENTED, /* 0x15c */ - REG_UNIMPLEMENTED, /* 0x15d */ - REG_UNIMPLEMENTED, /* 0x15e */ - REG_UNIMPLEMENTED, /* 0x15f */ - REG_UNIMPLEMENTED, /* 0x160 */ - REG_UNIMPLEMENTED, /* 0x161 */ - REG_UNIMPLEMENTED, /* 0x162 */ - REG_UNIMPLEMENTED, /* 0x163 */ - REG_UNIMPLEMENTED, /* 0x164 */ - REG_UNIMPLEMENTED, /* 0x165 */ - REG_UNIMPLEMENTED, /* 0x166 */ - REG_UNIMPLEMENTED, /* 0x167 */ - REG_UNIMPLEMENTED, /* 0x168 */ - REG_UNIMPLEMENTED, /* 0x169 */ - REG_UNIMPLEMENTED, /* 0x16a */ - REG_UNIMPLEMENTED, /* 0x16b */ - REG_UNIMPLEMENTED, /* 0x16c */ - REG_UNIMPLEMENTED, /* 0x16d */ - REG_UNIMPLEMENTED, /* 0x16e */ - REG_UNIMPLEMENTED, /* 0x16f */ - REG_FREG, /* 0x170 */ - REG_FREG, /* 0x171 */ - REG_FREG, /* 0x172 */ - REG_FREG, /* 0x173 */ - REG_FREG, /* 0x174 */ - REG_FREG, /* 0x175 */ - REG_FREG, /* 0x176 */ - REG_FREG, /* 0x177 */ - REG_FREG, /* 0x178 */ - REG_FREG, /* 0x179 */ - REG_FREG, /* 0x17a */ - REG_FREG, /* 0x17b */ - REG_FREG, /* 0x17c */ - REG_FREG, /* 0x17d */ - REG_FREG, /* 0x17e */ - REG_FREG, /* 0x17f */ - - /* BANK 3 */ - - REG_INDF, /* 0x180 */ - REG_OPTION_REG, /* 0x181 */ - REG_PCL, /* 0x182 */ - REG_STATUS, /* 0x183 */ - REG_FSR, /* 0x184 */ - REG_SRCON, /* 0x185 */ - REG_TRISB, /* 0x186 */ - REG_BAUDCTL, /* 0x187 */ - REG_ANSEL, /* 0x188 */ - REG_ANSELH, /* 0x189 */ - REG_PCLATH, /* 0x18a */ - REG_INTCON, /* 0x18b */ - REG_EECON1, /* 0x18c */ - REG_EECON2, /* 0x18d */ - REG_RESERVED, /* 0x18e */ - REG_RESERVED, /* 0x18f */ - REG_UNIMPLEMENTED, /* 0x190 */ - REG_UNIMPLEMENTED, /* 0x191 */ - REG_UNIMPLEMENTED, /* 0x192 */ - REG_UNIMPLEMENTED, /* 0x193 */ - REG_UNIMPLEMENTED, /* 0x194 */ - REG_UNIMPLEMENTED, /* 0x195 */ - REG_UNIMPLEMENTED, /* 0x196 */ - REG_UNIMPLEMENTED, /* 0x197 */ - REG_UNIMPLEMENTED, /* 0x198 */ - REG_UNIMPLEMENTED, /* 0x199 */ - REG_UNIMPLEMENTED, /* 0x19a */ - REG_UNIMPLEMENTED, /* 0x19b */ - REG_UNIMPLEMENTED, /* 0x19c */ - REG_UNIMPLEMENTED, /* 0x19d */ - REG_UNIMPLEMENTED, /* 0x19e */ - REG_UNIMPLEMENTED, /* 0x19f */ - REG_UNIMPLEMENTED, /* 0x1a0 */ - REG_UNIMPLEMENTED, /* 0x1a1 */ - REG_UNIMPLEMENTED, /* 0x1a2 */ - REG_UNIMPLEMENTED, /* 0x1a3 */ - REG_UNIMPLEMENTED, /* 0x1a4 */ - REG_UNIMPLEMENTED, /* 0x1a5 */ - REG_UNIMPLEMENTED, /* 0x1a6 */ - REG_UNIMPLEMENTED, /* 0x1a7 */ - REG_UNIMPLEMENTED, /* 0x1a8 */ - REG_UNIMPLEMENTED, /* 0x1a9 */ - REG_UNIMPLEMENTED, /* 0x1aa */ - REG_UNIMPLEMENTED, /* 0x1ab */ - REG_UNIMPLEMENTED, /* 0x1ac */ - REG_UNIMPLEMENTED, /* 0x1ad */ - REG_UNIMPLEMENTED, /* 0x1ae */ - REG_UNIMPLEMENTED, /* 0x1af */ - REG_UNIMPLEMENTED, /* 0x1b0 */ - REG_UNIMPLEMENTED, /* 0x1b1 */ - REG_UNIMPLEMENTED, /* 0x1b2 */ - REG_UNIMPLEMENTED, /* 0x1b3 */ - REG_UNIMPLEMENTED, /* 0x1b4 */ - REG_UNIMPLEMENTED, /* 0x1b5 */ - REG_UNIMPLEMENTED, /* 0x1b6 */ - REG_UNIMPLEMENTED, /* 0x1b7 */ - REG_UNIMPLEMENTED, /* 0x1b8 */ - REG_UNIMPLEMENTED, /* 0x1b9 */ - REG_UNIMPLEMENTED, /* 0x1ba */ - REG_UNIMPLEMENTED, /* 0x1bb */ - REG_UNIMPLEMENTED, /* 0x1bc */ - REG_UNIMPLEMENTED, /* 0x1bd */ - REG_UNIMPLEMENTED, /* 0x1be */ - REG_UNIMPLEMENTED, /* 0x1bf */ - REG_UNIMPLEMENTED, /* 0x1c0 */ - REG_UNIMPLEMENTED, /* 0x1c1 */ - REG_UNIMPLEMENTED, /* 0x1c2 */ - REG_UNIMPLEMENTED, /* 0x1c3 */ - REG_UNIMPLEMENTED, /* 0x1c4 */ - REG_UNIMPLEMENTED, /* 0x1c5 */ - REG_UNIMPLEMENTED, /* 0x1c6 */ - REG_UNIMPLEMENTED, /* 0x1c7 */ - REG_UNIMPLEMENTED, /* 0x1c8 */ - REG_UNIMPLEMENTED, /* 0x1c9 */ - REG_UNIMPLEMENTED, /* 0x1ca */ - REG_UNIMPLEMENTED, /* 0x1cb */ - REG_UNIMPLEMENTED, /* 0x1cc */ - REG_UNIMPLEMENTED, /* 0x1cd */ - REG_UNIMPLEMENTED, /* 0x1ce */ - REG_UNIMPLEMENTED, /* 0x1cf */ - REG_UNIMPLEMENTED, /* 0x1d0 */ - REG_UNIMPLEMENTED, /* 0x1d1 */ - REG_UNIMPLEMENTED, /* 0x1d2 */ - REG_UNIMPLEMENTED, /* 0x1d3 */ - REG_UNIMPLEMENTED, /* 0x1d4 */ - REG_UNIMPLEMENTED, /* 0x1d5 */ - REG_UNIMPLEMENTED, /* 0x1d6 */ - REG_UNIMPLEMENTED, /* 0x1d7 */ - REG_UNIMPLEMENTED, /* 0x1d8 */ - REG_UNIMPLEMENTED, /* 0x1d9 */ - REG_UNIMPLEMENTED, /* 0x1da */ - REG_UNIMPLEMENTED, /* 0x1db */ - REG_UNIMPLEMENTED, /* 0x1dc */ - REG_UNIMPLEMENTED, /* 0x1dd */ - REG_UNIMPLEMENTED, /* 0x1de */ - REG_UNIMPLEMENTED, /* 0x1df */ - REG_UNIMPLEMENTED, /* 0x1e0 */ - REG_UNIMPLEMENTED, /* 0x1e1 */ - REG_UNIMPLEMENTED, /* 0x1e2 */ - REG_UNIMPLEMENTED, /* 0x1e3 */ - REG_UNIMPLEMENTED, /* 0x1e4 */ - REG_UNIMPLEMENTED, /* 0x1e5 */ - REG_UNIMPLEMENTED, /* 0x1e6 */ - REG_UNIMPLEMENTED, /* 0x1e7 */ - REG_UNIMPLEMENTED, /* 0x1e8 */ - REG_UNIMPLEMENTED, /* 0x1e9 */ - REG_UNIMPLEMENTED, /* 0x1ea */ - REG_UNIMPLEMENTED, /* 0x1eb */ - REG_UNIMPLEMENTED, /* 0x1ec */ - REG_UNIMPLEMENTED, /* 0x1ed */ - REG_UNIMPLEMENTED, /* 0x1ee */ - REG_UNIMPLEMENTED, /* 0x1ef */ - REG_FREG, /* 0x1f0 */ - REG_FREG, /* 0x1f1 */ - REG_FREG, /* 0x1f2 */ - REG_FREG, /* 0x1f3 */ - REG_FREG, /* 0x1f4 */ - REG_FREG, /* 0x1f5 */ - REG_FREG, /* 0x1f6 */ - REG_FREG, /* 0x1f7 */ - REG_FREG, /* 0x1f8 */ - REG_FREG, /* 0x1f9 */ - REG_FREG, /* 0x1fa */ - REG_FREG, /* 0x1fb */ - REG_FREG, /* 0x1fc */ - REG_FREG, /* 0x1fd */ - REG_FREG, /* 0x1fe */ - REG_FREG, /* 0x1ff */ -}; -// clang-format on - -#endif // RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F882_H diff --git a/librz/analysis/arch/pic/pic16f_memmaps/pic16f883_4.h b/librz/analysis/arch/pic/pic16f_memmaps/pic16f883_4.h deleted file mode 100644 index d38285ecd3d..00000000000 --- a/librz/analysis/arch/pic/pic16f_memmaps/pic16f883_4.h +++ /dev/null @@ -1,543 +0,0 @@ -// SPDX-FileCopyrightText: 2023 Siddharth Mishra -// SPDX-License-Identifier: LGPL-3.0-only - -/** - * This file describes the memory map of PICF16883/4 device in PIC16F family. - * */ - -#ifndef RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F883_H -#define RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F883_H - -#include "regtypes.h" - -// clang-format off -PicMidrangeRegType pic16f883_reg_map[] = { - /* BANK 0 */ - REG_INDF, /* 0x00 */ - REG_TMR0, /* 0x01 */ - REG_PCL, /* 0x02 */ - REG_STATUS, /* 0x03 */ - REG_FSR, /* 0x04 */ - REG_PORTA, /* 0x05 */ - REG_PORTB, /* 0x06 */ - REG_PORTC, /* 0x07 */ - REG_PORTD, /* 0x08 */ - REG_PORTE, /* 0x09 */ - REG_PCLATH, /* 0x0a */ - REG_INTCON, /* 0x0b */ - REG_PIR1, /* 0x0c */ - REG_PIR2, /* 0x0d */ - REG_TMR1L, /* 0x0e */ - REG_TMR1H, /* 0x0f */ - REG_T1CON, /* 0x10 */ - REG_TMR2, /* 0x11 */ - REG_T2CON, /* 0x12 */ - REG_SSPBUF, /* 0x13 */ - REG_SSPCON, /* 0x14 */ - REG_CCPR1L, /* 0x15 */ - REG_CCPR1H, /* 0x16 */ - REG_CCP1CON, /* 0x17 */ - REG_RCSTA, /* 0x18 */ - REG_TXREG, /* 0x19 */ - REG_RCREG, /* 0x1a */ - REG_CCPR2L, /* 0x1b */ - REG_CCPR2H, /* 0x1c */ - REG_CCP2CON, /* 0x1d */ - REG_ADRESH, /* 0x1e */ - REG_ADCON0, /* 0x1f */ - REG_FREG, /* 0x20 */ - REG_FREG, /* 0x21 */ - REG_FREG, /* 0x22 */ - REG_FREG, /* 0x23 */ - REG_FREG, /* 0x24 */ - REG_FREG, /* 0x25 */ - REG_FREG, /* 0x26 */ - REG_FREG, /* 0x27 */ - REG_FREG, /* 0x28 */ - REG_FREG, /* 0x29 */ - REG_FREG, /* 0x2a */ - REG_FREG, /* 0x2b */ - REG_FREG, /* 0x2c */ - REG_FREG, /* 0x2d */ - REG_FREG, /* 0x2e */ - REG_FREG, /* 0x2f */ - REG_FREG, /* 0x30 */ - REG_FREG, /* 0x31 */ - REG_FREG, /* 0x32 */ - REG_FREG, /* 0x33 */ - REG_FREG, /* 0x34 */ - REG_FREG, /* 0x35 */ - REG_FREG, /* 0x36 */ - REG_FREG, /* 0x37 */ - REG_FREG, /* 0x38 */ - REG_FREG, /* 0x39 */ - REG_FREG, /* 0x3a */ - REG_FREG, /* 0x3b */ - REG_FREG, /* 0x3c */ - REG_FREG, /* 0x3d */ - REG_FREG, /* 0x3e */ - REG_FREG, /* 0x3f */ - REG_FREG, /* 0x40 */ - REG_FREG, /* 0x41 */ - REG_FREG, /* 0x42 */ - REG_FREG, /* 0x43 */ - REG_FREG, /* 0x44 */ - REG_FREG, /* 0x45 */ - REG_FREG, /* 0x46 */ - REG_FREG, /* 0x47 */ - REG_FREG, /* 0x48 */ - REG_FREG, /* 0x49 */ - REG_FREG, /* 0x4a */ - REG_FREG, /* 0x4b */ - REG_FREG, /* 0x4c */ - REG_FREG, /* 0x4d */ - REG_FREG, /* 0x4e */ - REG_FREG, /* 0x4f */ - REG_FREG, /* 0x50 */ - REG_FREG, /* 0x51 */ - REG_FREG, /* 0x52 */ - REG_FREG, /* 0x53 */ - REG_FREG, /* 0x54 */ - REG_FREG, /* 0x55 */ - REG_FREG, /* 0x56 */ - REG_FREG, /* 0x57 */ - REG_FREG, /* 0x58 */ - REG_FREG, /* 0x59 */ - REG_FREG, /* 0x5a */ - REG_FREG, /* 0x5b */ - REG_FREG, /* 0x5c */ - REG_FREG, /* 0x5d */ - REG_FREG, /* 0x5e */ - REG_FREG, /* 0x5f */ - REG_FREG, /* 0x60 */ - REG_FREG, /* 0x61 */ - REG_FREG, /* 0x62 */ - REG_FREG, /* 0x63 */ - REG_FREG, /* 0x64 */ - REG_FREG, /* 0x65 */ - REG_FREG, /* 0x66 */ - REG_FREG, /* 0x67 */ - REG_FREG, /* 0x68 */ - REG_FREG, /* 0x69 */ - REG_FREG, /* 0x6a */ - REG_FREG, /* 0x6b */ - REG_FREG, /* 0x6c */ - REG_FREG, /* 0x6d */ - REG_FREG, /* 0x6e */ - REG_FREG, /* 0x6f */ - REG_FREG, /* 0x70 */ - REG_FREG, /* 0x71 */ - REG_FREG, /* 0x72 */ - REG_FREG, /* 0x73 */ - REG_FREG, /* 0x74 */ - REG_FREG, /* 0x75 */ - REG_FREG, /* 0x76 */ - REG_FREG, /* 0x77 */ - REG_FREG, /* 0x78 */ - REG_FREG, /* 0x79 */ - REG_FREG, /* 0x7a */ - REG_FREG, /* 0x7b */ - REG_FREG, /* 0x7c */ - REG_FREG, /* 0x7d */ - REG_FREG, /* 0x7e */ - REG_FREG, /* 0x7f */ - - /* BANK1 */ - - REG_INDF, /* 0x80 */ - REG_OPTION_REG, /* 0x81 */ - REG_PCL, /* 0x82 */ - REG_STATUS, /* 0x83 */ - REG_FSR, /* 0x84 */ - REG_TRISA, /* 0x85 */ - REG_TRISB, /* 0x86 */ - REG_TRISC, /* 0x87 */ - REG_TRISD, /* 0x88 */ - REG_TRISE, /* 0x89 */ - REG_PCLATH, /* 0x8a */ - REG_INTCON, /* 0x8b */ - REG_PIE1, /* 0x8c */ - REG_PIE2, /* 0x8d */ - REG_PCON, /* 0x8e */ - REG_OSCCON, /* 0x8f */ - REG_OSCTUNE, /* 0x90 */ - REG_SSPCON2, /* 0x91 */ - REG_PR2, /* 0x92 */ - REG_SSPADD, /* 0x93 */ - REG_SSPSTAT, /* 0x94 */ - REG_WPUB, /* 0x95 */ - REG_IOCB, /* 0x96 */ - REG_VRCON, /* 0x97 */ - REG_TXSTA, /* 0x98 */ - REG_SPBRG, /* 0x99 */ - REG_SPBRGH, /* 0x9a */ - REG_PWM1CON, /* 0x9b */ - REG_ECCPAS, /* 0x9c */ - REG_PSTRCON, /* 0x9d */ - REG_ADRESL, /* 0x9e */ - REG_ADCON1, /* 0x9f */ - REG_FREG, /* 0xa0 */ - REG_FREG, /* 0xa1 */ - REG_FREG, /* 0xa2 */ - REG_FREG, /* 0xa3 */ - REG_FREG, /* 0xa4 */ - REG_FREG, /* 0xa5 */ - REG_FREG, /* 0xa6 */ - REG_FREG, /* 0xa7 */ - REG_FREG, /* 0xa8 */ - REG_FREG, /* 0xa9 */ - REG_FREG, /* 0xaa */ - REG_FREG, /* 0xab */ - REG_FREG, /* 0xac */ - REG_FREG, /* 0xad */ - REG_FREG, /* 0xae */ - REG_FREG, /* 0xaf */ - REG_FREG, /* 0xb0 */ - REG_FREG, /* 0xb1 */ - REG_FREG, /* 0xb2 */ - REG_FREG, /* 0xb3 */ - REG_FREG, /* 0xb4 */ - REG_FREG, /* 0xb5 */ - REG_FREG, /* 0xb6 */ - REG_FREG, /* 0xb7 */ - REG_FREG, /* 0xb8 */ - REG_FREG, /* 0xb9 */ - REG_FREG, /* 0xba */ - REG_FREG, /* 0xbb */ - REG_FREG, /* 0xbc */ - REG_FREG, /* 0xbd */ - REG_FREG, /* 0xbe */ - REG_FREG, /* 0xbf */ - REG_FREG, /* 0xc0 */ - REG_FREG, /* 0xc1 */ - REG_FREG, /* 0xc2 */ - REG_FREG, /* 0xc3 */ - REG_FREG, /* 0xc4 */ - REG_FREG, /* 0xc5 */ - REG_FREG, /* 0xc6 */ - REG_FREG, /* 0xc7 */ - REG_FREG, /* 0xc8 */ - REG_FREG, /* 0xc9 */ - REG_FREG, /* 0xca */ - REG_FREG, /* 0xcb */ - REG_FREG, /* 0xcc */ - REG_FREG, /* 0xcd */ - REG_FREG, /* 0xce */ - REG_FREG, /* 0xcf */ - REG_FREG, /* 0xd0 */ - REG_FREG, /* 0xd1 */ - REG_FREG, /* 0xd2 */ - REG_FREG, /* 0xd3 */ - REG_FREG, /* 0xd4 */ - REG_FREG, /* 0xd5 */ - REG_FREG, /* 0xd6 */ - REG_FREG, /* 0xd7 */ - REG_FREG, /* 0xd8 */ - REG_FREG, /* 0xd9 */ - REG_FREG, /* 0xda */ - REG_FREG, /* 0xdb */ - REG_FREG, /* 0xdc */ - REG_FREG, /* 0xdd */ - REG_FREG, /* 0xde */ - REG_FREG, /* 0xdf */ - REG_FREG, /* 0xe0 */ - REG_FREG, /* 0xe1 */ - REG_FREG, /* 0xe2 */ - REG_FREG, /* 0xe3 */ - REG_FREG, /* 0xe4 */ - REG_FREG, /* 0xe5 */ - REG_FREG, /* 0xe6 */ - REG_FREG, /* 0xe7 */ - REG_FREG, /* 0xe8 */ - REG_FREG, /* 0xe9 */ - REG_FREG, /* 0xea */ - REG_FREG, /* 0xeb */ - REG_FREG, /* 0xec */ - REG_FREG, /* 0xed */ - REG_FREG, /* 0xee */ - REG_FREG, /* 0xef */ - REG_FREG, /* 0xf0 */ - REG_FREG, /* 0xf1 */ - REG_FREG, /* 0xf2 */ - REG_FREG, /* 0xf3 */ - REG_FREG, /* 0xf4 */ - REG_FREG, /* 0xf5 */ - REG_FREG, /* 0xf6 */ - REG_FREG, /* 0xf7 */ - REG_FREG, /* 0xf8 */ - REG_FREG, /* 0xf9 */ - REG_FREG, /* 0xfa */ - REG_FREG, /* 0xfb */ - REG_FREG, /* 0xfc */ - REG_FREG, /* 0xfd */ - REG_FREG, /* 0xfe */ - REG_FREG, /* 0xff */ - - /* BANK 2 */ - - REG_INDF, /* 0x100 */ - REG_TMR0, /* 0x101 */ - REG_PCL, /* 0x102 */ - REG_STATUS, /* 0x103 */ - REG_FSR, /* 0x104 */ - REG_WDTCON, /* 0x105 */ - REG_PORTB, /* 0x106 */ - REG_CM1CON0, /* 0x107 */ - REG_CM2CON0, /* 0x108 */ - REG_CM2CON1, /* 0x109 */ - REG_PCLATH, /* 0x10a */ - REG_INTCON, /* 0x10b */ - REG_EEDAT, /* 0x10c */ - REG_EEADR, /* 0x10d */ - REG_EEDATH, /* 0x10e */ - REG_EEADRH, /* 0x10f */ - REG_UNIMPLEMENTED, /* 0x110 */ - REG_UNIMPLEMENTED, /* 0x111 */ - REG_UNIMPLEMENTED, /* 0x112 */ - REG_UNIMPLEMENTED, /* 0x113 */ - REG_UNIMPLEMENTED, /* 0x114 */ - REG_UNIMPLEMENTED, /* 0x115 */ - REG_UNIMPLEMENTED, /* 0x116 */ - REG_UNIMPLEMENTED, /* 0x117 */ - REG_UNIMPLEMENTED, /* 0x118 */ - REG_UNIMPLEMENTED, /* 0x119 */ - REG_UNIMPLEMENTED, /* 0x11a */ - REG_UNIMPLEMENTED, /* 0x11b */ - REG_UNIMPLEMENTED, /* 0x11c */ - REG_UNIMPLEMENTED, /* 0x11d */ - REG_UNIMPLEMENTED, /* 0x11e */ - REG_UNIMPLEMENTED, /* 0x11f */ - REG_FREG, /* 0x120 */ - REG_FREG, /* 0x121 */ - REG_FREG, /* 0x122 */ - REG_FREG, /* 0x123 */ - REG_FREG, /* 0x124 */ - REG_FREG, /* 0x125 */ - REG_FREG, /* 0x126 */ - REG_FREG, /* 0x127 */ - REG_FREG, /* 0x128 */ - REG_FREG, /* 0x129 */ - REG_FREG, /* 0x12a */ - REG_FREG, /* 0x12b */ - REG_FREG, /* 0x12c */ - REG_FREG, /* 0x12d */ - REG_FREG, /* 0x12e */ - REG_FREG, /* 0x12f */ - REG_FREG, /* 0x130 */ - REG_FREG, /* 0x131 */ - REG_FREG, /* 0x132 */ - REG_FREG, /* 0x133 */ - REG_FREG, /* 0x134 */ - REG_FREG, /* 0x135 */ - REG_FREG, /* 0x136 */ - REG_FREG, /* 0x137 */ - REG_FREG, /* 0x138 */ - REG_FREG, /* 0x139 */ - REG_FREG, /* 0x13a */ - REG_FREG, /* 0x13b */ - REG_FREG, /* 0x13c */ - REG_FREG, /* 0x13d */ - REG_FREG, /* 0x13e */ - REG_FREG, /* 0x13f */ - REG_FREG, /* 0x140 */ - REG_FREG, /* 0x141 */ - REG_FREG, /* 0x142 */ - REG_FREG, /* 0x143 */ - REG_FREG, /* 0x144 */ - REG_FREG, /* 0x145 */ - REG_FREG, /* 0x146 */ - REG_FREG, /* 0x147 */ - REG_FREG, /* 0x148 */ - REG_FREG, /* 0x149 */ - REG_FREG, /* 0x14a */ - REG_FREG, /* 0x14b */ - REG_FREG, /* 0x14c */ - REG_FREG, /* 0x14d */ - REG_FREG, /* 0x14e */ - REG_FREG, /* 0x14f */ - REG_FREG, /* 0x150 */ - REG_FREG, /* 0x151 */ - REG_FREG, /* 0x152 */ - REG_FREG, /* 0x153 */ - REG_FREG, /* 0x154 */ - REG_FREG, /* 0x155 */ - REG_FREG, /* 0x156 */ - REG_FREG, /* 0x157 */ - REG_FREG, /* 0x158 */ - REG_FREG, /* 0x159 */ - REG_FREG, /* 0x15a */ - REG_FREG, /* 0x15b */ - REG_FREG, /* 0x15c */ - REG_FREG, /* 0x15d */ - REG_FREG, /* 0x15e */ - REG_FREG, /* 0x15f */ - REG_FREG, /* 0x160 */ - REG_FREG, /* 0x161 */ - REG_FREG, /* 0x162 */ - REG_FREG, /* 0x163 */ - REG_FREG, /* 0x164 */ - REG_FREG, /* 0x165 */ - REG_FREG, /* 0x166 */ - REG_FREG, /* 0x167 */ - REG_FREG, /* 0x168 */ - REG_FREG, /* 0x169 */ - REG_FREG, /* 0x16a */ - REG_FREG, /* 0x16b */ - REG_FREG, /* 0x16c */ - REG_FREG, /* 0x16d */ - REG_FREG, /* 0x16e */ - REG_FREG, /* 0x16f */ - REG_FREG, /* 0x170 */ - REG_FREG, /* 0x171 */ - REG_FREG, /* 0x172 */ - REG_FREG, /* 0x173 */ - REG_FREG, /* 0x174 */ - REG_FREG, /* 0x175 */ - REG_FREG, /* 0x176 */ - REG_FREG, /* 0x177 */ - REG_FREG, /* 0x178 */ - REG_FREG, /* 0x179 */ - REG_FREG, /* 0x17a */ - REG_FREG, /* 0x17b */ - REG_FREG, /* 0x17c */ - REG_FREG, /* 0x17d */ - REG_FREG, /* 0x17e */ - REG_FREG, /* 0x17f */ - - /* BANK 3 */ - - REG_INDF, /* 0x180 */ - REG_OPTION_REG, /* 0x181 */ - REG_PCL, /* 0x182 */ - REG_STATUS, /* 0x183 */ - REG_FSR, /* 0x184 */ - REG_SRCON, /* 0x185 */ - REG_TRISB, /* 0x186 */ - REG_BAUDCTL, /* 0x187 */ - REG_ANSEL, /* 0x188 */ - REG_ANSELH, /* 0x189 */ - REG_PCLATH, /* 0x18a */ - REG_INTCON, /* 0x18b */ - REG_EECON1, /* 0x18c */ - REG_EECON2, /* 0x18d */ - REG_RESERVED, /* 0x18e */ - REG_RESERVED, /* 0x18f */ - REG_UNIMPLEMENTED, /* 0x190 */ - REG_UNIMPLEMENTED, /* 0x191 */ - REG_UNIMPLEMENTED, /* 0x192 */ - REG_UNIMPLEMENTED, /* 0x193 */ - REG_UNIMPLEMENTED, /* 0x194 */ - REG_UNIMPLEMENTED, /* 0x195 */ - REG_UNIMPLEMENTED, /* 0x196 */ - REG_UNIMPLEMENTED, /* 0x197 */ - REG_UNIMPLEMENTED, /* 0x198 */ - REG_UNIMPLEMENTED, /* 0x199 */ - REG_UNIMPLEMENTED, /* 0x19a */ - REG_UNIMPLEMENTED, /* 0x19b */ - REG_UNIMPLEMENTED, /* 0x19c */ - REG_UNIMPLEMENTED, /* 0x19d */ - REG_UNIMPLEMENTED, /* 0x19e */ - REG_UNIMPLEMENTED, /* 0x19f */ - REG_UNIMPLEMENTED, /* 0x1a0 */ - REG_UNIMPLEMENTED, /* 0x1a1 */ - REG_UNIMPLEMENTED, /* 0x1a2 */ - REG_UNIMPLEMENTED, /* 0x1a3 */ - REG_UNIMPLEMENTED, /* 0x1a4 */ - REG_UNIMPLEMENTED, /* 0x1a5 */ - REG_UNIMPLEMENTED, /* 0x1a6 */ - REG_UNIMPLEMENTED, /* 0x1a7 */ - REG_UNIMPLEMENTED, /* 0x1a8 */ - REG_UNIMPLEMENTED, /* 0x1a9 */ - REG_UNIMPLEMENTED, /* 0x1aa */ - REG_UNIMPLEMENTED, /* 0x1ab */ - REG_UNIMPLEMENTED, /* 0x1ac */ - REG_UNIMPLEMENTED, /* 0x1ad */ - REG_UNIMPLEMENTED, /* 0x1ae */ - REG_UNIMPLEMENTED, /* 0x1af */ - REG_UNIMPLEMENTED, /* 0x1b0 */ - REG_UNIMPLEMENTED, /* 0x1b1 */ - REG_UNIMPLEMENTED, /* 0x1b2 */ - REG_UNIMPLEMENTED, /* 0x1b3 */ - REG_UNIMPLEMENTED, /* 0x1b4 */ - REG_UNIMPLEMENTED, /* 0x1b5 */ - REG_UNIMPLEMENTED, /* 0x1b6 */ - REG_UNIMPLEMENTED, /* 0x1b7 */ - REG_UNIMPLEMENTED, /* 0x1b8 */ - REG_UNIMPLEMENTED, /* 0x1b9 */ - REG_UNIMPLEMENTED, /* 0x1ba */ - REG_UNIMPLEMENTED, /* 0x1bb */ - REG_UNIMPLEMENTED, /* 0x1bc */ - REG_UNIMPLEMENTED, /* 0x1bd */ - REG_UNIMPLEMENTED, /* 0x1be */ - REG_UNIMPLEMENTED, /* 0x1bf */ - REG_UNIMPLEMENTED, /* 0x1c0 */ - REG_UNIMPLEMENTED, /* 0x1c1 */ - REG_UNIMPLEMENTED, /* 0x1c2 */ - REG_UNIMPLEMENTED, /* 0x1c3 */ - REG_UNIMPLEMENTED, /* 0x1c4 */ - REG_UNIMPLEMENTED, /* 0x1c5 */ - REG_UNIMPLEMENTED, /* 0x1c6 */ - REG_UNIMPLEMENTED, /* 0x1c7 */ - REG_UNIMPLEMENTED, /* 0x1c8 */ - REG_UNIMPLEMENTED, /* 0x1c9 */ - REG_UNIMPLEMENTED, /* 0x1ca */ - REG_UNIMPLEMENTED, /* 0x1cb */ - REG_UNIMPLEMENTED, /* 0x1cc */ - REG_UNIMPLEMENTED, /* 0x1cd */ - REG_UNIMPLEMENTED, /* 0x1ce */ - REG_UNIMPLEMENTED, /* 0x1cf */ - REG_UNIMPLEMENTED, /* 0x1d0 */ - REG_UNIMPLEMENTED, /* 0x1d1 */ - REG_UNIMPLEMENTED, /* 0x1d2 */ - REG_UNIMPLEMENTED, /* 0x1d3 */ - REG_UNIMPLEMENTED, /* 0x1d4 */ - REG_UNIMPLEMENTED, /* 0x1d5 */ - REG_UNIMPLEMENTED, /* 0x1d6 */ - REG_UNIMPLEMENTED, /* 0x1d7 */ - REG_UNIMPLEMENTED, /* 0x1d8 */ - REG_UNIMPLEMENTED, /* 0x1d9 */ - REG_UNIMPLEMENTED, /* 0x1da */ - REG_UNIMPLEMENTED, /* 0x1db */ - REG_UNIMPLEMENTED, /* 0x1dc */ - REG_UNIMPLEMENTED, /* 0x1dd */ - REG_UNIMPLEMENTED, /* 0x1de */ - REG_UNIMPLEMENTED, /* 0x1df */ - REG_UNIMPLEMENTED, /* 0x1e0 */ - REG_UNIMPLEMENTED, /* 0x1e1 */ - REG_UNIMPLEMENTED, /* 0x1e2 */ - REG_UNIMPLEMENTED, /* 0x1e3 */ - REG_UNIMPLEMENTED, /* 0x1e4 */ - REG_UNIMPLEMENTED, /* 0x1e5 */ - REG_UNIMPLEMENTED, /* 0x1e6 */ - REG_UNIMPLEMENTED, /* 0x1e7 */ - REG_UNIMPLEMENTED, /* 0x1e8 */ - REG_UNIMPLEMENTED, /* 0x1e9 */ - REG_UNIMPLEMENTED, /* 0x1ea */ - REG_UNIMPLEMENTED, /* 0x1eb */ - REG_UNIMPLEMENTED, /* 0x1ec */ - REG_UNIMPLEMENTED, /* 0x1ed */ - REG_UNIMPLEMENTED, /* 0x1ee */ - REG_UNIMPLEMENTED, /* 0x1ef */ - REG_FREG, /* 0x1f0 */ - REG_FREG, /* 0x1f1 */ - REG_FREG, /* 0x1f2 */ - REG_FREG, /* 0x1f3 */ - REG_FREG, /* 0x1f4 */ - REG_FREG, /* 0x1f5 */ - REG_FREG, /* 0x1f6 */ - REG_FREG, /* 0x1f7 */ - REG_FREG, /* 0x1f8 */ - REG_FREG, /* 0x1f9 */ - REG_FREG, /* 0x1fa */ - REG_FREG, /* 0x1fb */ - REG_FREG, /* 0x1fc */ - REG_FREG, /* 0x1fd */ - REG_FREG, /* 0x1fe */ - REG_FREG, /* 0x1ff */ -}; -// clang-format on - -// memory map for PIC16F883 and PIC16F884 are same -PicMidrangeRegType *pic16f884_reg_map = pic16f883_reg_map; - -#endif // RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F882_H diff --git a/librz/analysis/arch/pic/pic16f_memmaps/pic16f886_7.h b/librz/analysis/arch/pic/pic16f_memmaps/pic16f886_7.h deleted file mode 100644 index 6581385ece0..00000000000 --- a/librz/analysis/arch/pic/pic16f_memmaps/pic16f886_7.h +++ /dev/null @@ -1,543 +0,0 @@ -// SPDX-FileCopyrightText: 2023 Siddharth Mishra -// SPDX-License-Identifier: LGPL-3.0-only - -/** - * This file describes the memory map of PICF16886/7 device in PIC16F family. - * */ - -#ifndef RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F886_H -#define RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F886_H - -#include "regtypes.h" - -// clang-format off -PicMidrangeRegType pic16f886_reg_map[] = { - /* BANK 0 */ - REG_INDF, /* 0x00 */ - REG_TMR0, /* 0x01 */ - REG_PCL, /* 0x02 */ - REG_STATUS, /* 0x03 */ - REG_FSR, /* 0x04 */ - REG_PORTA, /* 0x05 */ - REG_PORTB, /* 0x06 */ - REG_PORTC, /* 0x07 */ - REG_PORTD, /* 0x08 */ - REG_PORTE, /* 0x09 */ - REG_PCLATH, /* 0x0a */ - REG_INTCON, /* 0x0b */ - REG_PIR1, /* 0x0c */ - REG_PIR2, /* 0x0d */ - REG_TMR1L, /* 0x0e */ - REG_TMR1H, /* 0x0f */ - REG_T1CON, /* 0x10 */ - REG_TMR2, /* 0x11 */ - REG_T2CON, /* 0x12 */ - REG_SSPBUF, /* 0x13 */ - REG_SSPCON, /* 0x14 */ - REG_CCPR1L, /* 0x15 */ - REG_CCPR1H, /* 0x16 */ - REG_CCP1CON, /* 0x17 */ - REG_RCSTA, /* 0x18 */ - REG_TXREG, /* 0x19 */ - REG_RCREG, /* 0x1a */ - REG_CCPR2L, /* 0x1b */ - REG_CCPR2H, /* 0x1c */ - REG_CCP2CON, /* 0x1d */ - REG_ADRESH, /* 0x1e */ - REG_ADCON0, /* 0x1f */ - REG_FREG, /* 0x20 */ - REG_FREG, /* 0x21 */ - REG_FREG, /* 0x22 */ - REG_FREG, /* 0x23 */ - REG_FREG, /* 0x24 */ - REG_FREG, /* 0x25 */ - REG_FREG, /* 0x26 */ - REG_FREG, /* 0x27 */ - REG_FREG, /* 0x28 */ - REG_FREG, /* 0x29 */ - REG_FREG, /* 0x2a */ - REG_FREG, /* 0x2b */ - REG_FREG, /* 0x2c */ - REG_FREG, /* 0x2d */ - REG_FREG, /* 0x2e */ - REG_FREG, /* 0x2f */ - REG_FREG, /* 0x30 */ - REG_FREG, /* 0x31 */ - REG_FREG, /* 0x32 */ - REG_FREG, /* 0x33 */ - REG_FREG, /* 0x34 */ - REG_FREG, /* 0x35 */ - REG_FREG, /* 0x36 */ - REG_FREG, /* 0x37 */ - REG_FREG, /* 0x38 */ - REG_FREG, /* 0x39 */ - REG_FREG, /* 0x3a */ - REG_FREG, /* 0x3b */ - REG_FREG, /* 0x3c */ - REG_FREG, /* 0x3d */ - REG_FREG, /* 0x3e */ - REG_FREG, /* 0x3f */ - REG_FREG, /* 0x40 */ - REG_FREG, /* 0x41 */ - REG_FREG, /* 0x42 */ - REG_FREG, /* 0x43 */ - REG_FREG, /* 0x44 */ - REG_FREG, /* 0x45 */ - REG_FREG, /* 0x46 */ - REG_FREG, /* 0x47 */ - REG_FREG, /* 0x48 */ - REG_FREG, /* 0x49 */ - REG_FREG, /* 0x4a */ - REG_FREG, /* 0x4b */ - REG_FREG, /* 0x4c */ - REG_FREG, /* 0x4d */ - REG_FREG, /* 0x4e */ - REG_FREG, /* 0x4f */ - REG_FREG, /* 0x50 */ - REG_FREG, /* 0x51 */ - REG_FREG, /* 0x52 */ - REG_FREG, /* 0x53 */ - REG_FREG, /* 0x54 */ - REG_FREG, /* 0x55 */ - REG_FREG, /* 0x56 */ - REG_FREG, /* 0x57 */ - REG_FREG, /* 0x58 */ - REG_FREG, /* 0x59 */ - REG_FREG, /* 0x5a */ - REG_FREG, /* 0x5b */ - REG_FREG, /* 0x5c */ - REG_FREG, /* 0x5d */ - REG_FREG, /* 0x5e */ - REG_FREG, /* 0x5f */ - REG_FREG, /* 0x60 */ - REG_FREG, /* 0x61 */ - REG_FREG, /* 0x62 */ - REG_FREG, /* 0x63 */ - REG_FREG, /* 0x64 */ - REG_FREG, /* 0x65 */ - REG_FREG, /* 0x66 */ - REG_FREG, /* 0x67 */ - REG_FREG, /* 0x68 */ - REG_FREG, /* 0x69 */ - REG_FREG, /* 0x6a */ - REG_FREG, /* 0x6b */ - REG_FREG, /* 0x6c */ - REG_FREG, /* 0x6d */ - REG_FREG, /* 0x6e */ - REG_FREG, /* 0x6f */ - REG_FREG, /* 0x70 */ - REG_FREG, /* 0x71 */ - REG_FREG, /* 0x72 */ - REG_FREG, /* 0x73 */ - REG_FREG, /* 0x74 */ - REG_FREG, /* 0x75 */ - REG_FREG, /* 0x76 */ - REG_FREG, /* 0x77 */ - REG_FREG, /* 0x78 */ - REG_FREG, /* 0x79 */ - REG_FREG, /* 0x7a */ - REG_FREG, /* 0x7b */ - REG_FREG, /* 0x7c */ - REG_FREG, /* 0x7d */ - REG_FREG, /* 0x7e */ - REG_FREG, /* 0x7f */ - - /* BANK1 */ - - REG_INDF, /* 0x80 */ - REG_OPTION_REG, /* 0x81 */ - REG_PCL, /* 0x82 */ - REG_STATUS, /* 0x83 */ - REG_FSR, /* 0x84 */ - REG_TRISA, /* 0x85 */ - REG_TRISB, /* 0x86 */ - REG_TRISC, /* 0x87 */ - REG_TRISD, /* 0x88 */ - REG_TRISE, /* 0x89 */ - REG_PCLATH, /* 0x8a */ - REG_INTCON, /* 0x8b */ - REG_PIE1, /* 0x8c */ - REG_PIE2, /* 0x8d */ - REG_PCON, /* 0x8e */ - REG_OSCCON, /* 0x8f */ - REG_OSCTUNE, /* 0x90 */ - REG_SSPCON2, /* 0x91 */ - REG_PR2, /* 0x92 */ - REG_SSPADD, /* 0x93 */ - REG_SSPSTAT, /* 0x94 */ - REG_WPUB, /* 0x95 */ - REG_IOCB, /* 0x96 */ - REG_VRCON, /* 0x97 */ - REG_TXSTA, /* 0x98 */ - REG_SPBRG, /* 0x99 */ - REG_SPBRGH, /* 0x9a */ - REG_PWM1CON, /* 0x9b */ - REG_ECCPAS, /* 0x9c */ - REG_PSTRCON, /* 0x9d */ - REG_ADRESL, /* 0x9e */ - REG_ADCON1, /* 0x9f */ - REG_FREG, /* 0xa0 */ - REG_FREG, /* 0xa1 */ - REG_FREG, /* 0xa2 */ - REG_FREG, /* 0xa3 */ - REG_FREG, /* 0xa4 */ - REG_FREG, /* 0xa5 */ - REG_FREG, /* 0xa6 */ - REG_FREG, /* 0xa7 */ - REG_FREG, /* 0xa8 */ - REG_FREG, /* 0xa9 */ - REG_FREG, /* 0xaa */ - REG_FREG, /* 0xab */ - REG_FREG, /* 0xac */ - REG_FREG, /* 0xad */ - REG_FREG, /* 0xae */ - REG_FREG, /* 0xaf */ - REG_FREG, /* 0xb0 */ - REG_FREG, /* 0xb1 */ - REG_FREG, /* 0xb2 */ - REG_FREG, /* 0xb3 */ - REG_FREG, /* 0xb4 */ - REG_FREG, /* 0xb5 */ - REG_FREG, /* 0xb6 */ - REG_FREG, /* 0xb7 */ - REG_FREG, /* 0xb8 */ - REG_FREG, /* 0xb9 */ - REG_FREG, /* 0xba */ - REG_FREG, /* 0xbb */ - REG_FREG, /* 0xbc */ - REG_FREG, /* 0xbd */ - REG_FREG, /* 0xbe */ - REG_FREG, /* 0xbf */ - REG_FREG, /* 0xc0 */ - REG_FREG, /* 0xc1 */ - REG_FREG, /* 0xc2 */ - REG_FREG, /* 0xc3 */ - REG_FREG, /* 0xc4 */ - REG_FREG, /* 0xc5 */ - REG_FREG, /* 0xc6 */ - REG_FREG, /* 0xc7 */ - REG_FREG, /* 0xc8 */ - REG_FREG, /* 0xc9 */ - REG_FREG, /* 0xca */ - REG_FREG, /* 0xcb */ - REG_FREG, /* 0xcc */ - REG_FREG, /* 0xcd */ - REG_FREG, /* 0xce */ - REG_FREG, /* 0xcf */ - REG_FREG, /* 0xd0 */ - REG_FREG, /* 0xd1 */ - REG_FREG, /* 0xd2 */ - REG_FREG, /* 0xd3 */ - REG_FREG, /* 0xd4 */ - REG_FREG, /* 0xd5 */ - REG_FREG, /* 0xd6 */ - REG_FREG, /* 0xd7 */ - REG_FREG, /* 0xd8 */ - REG_FREG, /* 0xd9 */ - REG_FREG, /* 0xda */ - REG_FREG, /* 0xdb */ - REG_FREG, /* 0xdc */ - REG_FREG, /* 0xdd */ - REG_FREG, /* 0xde */ - REG_FREG, /* 0xdf */ - REG_FREG, /* 0xe0 */ - REG_FREG, /* 0xe1 */ - REG_FREG, /* 0xe2 */ - REG_FREG, /* 0xe3 */ - REG_FREG, /* 0xe4 */ - REG_FREG, /* 0xe5 */ - REG_FREG, /* 0xe6 */ - REG_FREG, /* 0xe7 */ - REG_FREG, /* 0xe8 */ - REG_FREG, /* 0xe9 */ - REG_FREG, /* 0xea */ - REG_FREG, /* 0xeb */ - REG_FREG, /* 0xec */ - REG_FREG, /* 0xed */ - REG_FREG, /* 0xee */ - REG_FREG, /* 0xef */ - REG_FREG, /* 0xf0 */ - REG_FREG, /* 0xf1 */ - REG_FREG, /* 0xf2 */ - REG_FREG, /* 0xf3 */ - REG_FREG, /* 0xf4 */ - REG_FREG, /* 0xf5 */ - REG_FREG, /* 0xf6 */ - REG_FREG, /* 0xf7 */ - REG_FREG, /* 0xf8 */ - REG_FREG, /* 0xf9 */ - REG_FREG, /* 0xfa */ - REG_FREG, /* 0xfb */ - REG_FREG, /* 0xfc */ - REG_FREG, /* 0xfd */ - REG_FREG, /* 0xfe */ - REG_FREG, /* 0xff */ - - /* BANK 2 */ - - REG_INDF, /* 0x100 */ - REG_TMR0, /* 0x101 */ - REG_PCL, /* 0x102 */ - REG_STATUS, /* 0x103 */ - REG_FSR, /* 0x104 */ - REG_WDTCON, /* 0x105 */ - REG_PORTB, /* 0x106 */ - REG_CM1CON0, /* 0x107 */ - REG_CM2CON0, /* 0x108 */ - REG_CM2CON1, /* 0x109 */ - REG_PCLATH, /* 0x10a */ - REG_INTCON, /* 0x10b */ - REG_EEDAT, /* 0x10c */ - REG_EEADR, /* 0x10d */ - REG_EEDATH, /* 0x10e */ - REG_EEADRH, /* 0x10f */ - REG_FREG, /* 0x110 */ - REG_FREG, /* 0x111 */ - REG_FREG, /* 0x112 */ - REG_FREG, /* 0x113 */ - REG_FREG, /* 0x114 */ - REG_FREG, /* 0x115 */ - REG_FREG, /* 0x116 */ - REG_FREG, /* 0x117 */ - REG_FREG, /* 0x118 */ - REG_FREG, /* 0x119 */ - REG_FREG, /* 0x11a */ - REG_FREG, /* 0x11b */ - REG_FREG, /* 0x11c */ - REG_FREG, /* 0x11d */ - REG_FREG, /* 0x11e */ - REG_FREG, /* 0x11f */ - REG_FREG, /* 0x120 */ - REG_FREG, /* 0x121 */ - REG_FREG, /* 0x122 */ - REG_FREG, /* 0x123 */ - REG_FREG, /* 0x124 */ - REG_FREG, /* 0x125 */ - REG_FREG, /* 0x126 */ - REG_FREG, /* 0x127 */ - REG_FREG, /* 0x128 */ - REG_FREG, /* 0x129 */ - REG_FREG, /* 0x12a */ - REG_FREG, /* 0x12b */ - REG_FREG, /* 0x12c */ - REG_FREG, /* 0x12d */ - REG_FREG, /* 0x12e */ - REG_FREG, /* 0x12f */ - REG_FREG, /* 0x130 */ - REG_FREG, /* 0x131 */ - REG_FREG, /* 0x132 */ - REG_FREG, /* 0x133 */ - REG_FREG, /* 0x134 */ - REG_FREG, /* 0x135 */ - REG_FREG, /* 0x136 */ - REG_FREG, /* 0x137 */ - REG_FREG, /* 0x138 */ - REG_FREG, /* 0x139 */ - REG_FREG, /* 0x13a */ - REG_FREG, /* 0x13b */ - REG_FREG, /* 0x13c */ - REG_FREG, /* 0x13d */ - REG_FREG, /* 0x13e */ - REG_FREG, /* 0x13f */ - REG_FREG, /* 0x140 */ - REG_FREG, /* 0x141 */ - REG_FREG, /* 0x142 */ - REG_FREG, /* 0x143 */ - REG_FREG, /* 0x144 */ - REG_FREG, /* 0x145 */ - REG_FREG, /* 0x146 */ - REG_FREG, /* 0x147 */ - REG_FREG, /* 0x148 */ - REG_FREG, /* 0x149 */ - REG_FREG, /* 0x14a */ - REG_FREG, /* 0x14b */ - REG_FREG, /* 0x14c */ - REG_FREG, /* 0x14d */ - REG_FREG, /* 0x14e */ - REG_FREG, /* 0x14f */ - REG_FREG, /* 0x150 */ - REG_FREG, /* 0x151 */ - REG_FREG, /* 0x152 */ - REG_FREG, /* 0x153 */ - REG_FREG, /* 0x154 */ - REG_FREG, /* 0x155 */ - REG_FREG, /* 0x156 */ - REG_FREG, /* 0x157 */ - REG_FREG, /* 0x158 */ - REG_FREG, /* 0x159 */ - REG_FREG, /* 0x15a */ - REG_FREG, /* 0x15b */ - REG_FREG, /* 0x15c */ - REG_FREG, /* 0x15d */ - REG_FREG, /* 0x15e */ - REG_FREG, /* 0x15f */ - REG_FREG, /* 0x160 */ - REG_FREG, /* 0x161 */ - REG_FREG, /* 0x162 */ - REG_FREG, /* 0x163 */ - REG_FREG, /* 0x164 */ - REG_FREG, /* 0x165 */ - REG_FREG, /* 0x166 */ - REG_FREG, /* 0x167 */ - REG_FREG, /* 0x168 */ - REG_FREG, /* 0x169 */ - REG_FREG, /* 0x16a */ - REG_FREG, /* 0x16b */ - REG_FREG, /* 0x16c */ - REG_FREG, /* 0x16d */ - REG_FREG, /* 0x16e */ - REG_FREG, /* 0x16f */ - REG_FREG, /* 0x170 */ - REG_FREG, /* 0x171 */ - REG_FREG, /* 0x172 */ - REG_FREG, /* 0x173 */ - REG_FREG, /* 0x174 */ - REG_FREG, /* 0x175 */ - REG_FREG, /* 0x176 */ - REG_FREG, /* 0x177 */ - REG_FREG, /* 0x178 */ - REG_FREG, /* 0x179 */ - REG_FREG, /* 0x17a */ - REG_FREG, /* 0x17b */ - REG_FREG, /* 0x17c */ - REG_FREG, /* 0x17d */ - REG_FREG, /* 0x17e */ - REG_FREG, /* 0x17f */ - - /* BANK 3 */ - - REG_INDF, /* 0x180 */ - REG_OPTION_REG, /* 0x181 */ - REG_PCL, /* 0x182 */ - REG_STATUS, /* 0x183 */ - REG_FSR, /* 0x184 */ - REG_SRCON, /* 0x185 */ - REG_TRISB, /* 0x186 */ - REG_BAUDCTL, /* 0x187 */ - REG_ANSEL, /* 0x188 */ - REG_ANSELH, /* 0x189 */ - REG_PCLATH, /* 0x18a */ - REG_INTCON, /* 0x18b */ - REG_EECON1, /* 0x18c */ - REG_EECON2, /* 0x18d */ - REG_RESERVED, /* 0x18e */ - REG_RESERVED, /* 0x18f */ - REG_FREG, /* 0x190 */ - REG_FREG, /* 0x191 */ - REG_FREG, /* 0x192 */ - REG_FREG, /* 0x193 */ - REG_FREG, /* 0x194 */ - REG_FREG, /* 0x195 */ - REG_FREG, /* 0x196 */ - REG_FREG, /* 0x197 */ - REG_FREG, /* 0x198 */ - REG_FREG, /* 0x199 */ - REG_FREG, /* 0x19a */ - REG_FREG, /* 0x19b */ - REG_FREG, /* 0x19c */ - REG_FREG, /* 0x19d */ - REG_FREG, /* 0x19e */ - REG_FREG, /* 0x19f */ - REG_FREG, /* 0x1a0 */ - REG_FREG, /* 0x1a1 */ - REG_FREG, /* 0x1a2 */ - REG_FREG, /* 0x1a3 */ - REG_FREG, /* 0x1a4 */ - REG_FREG, /* 0x1a5 */ - REG_FREG, /* 0x1a6 */ - REG_FREG, /* 0x1a7 */ - REG_FREG, /* 0x1a8 */ - REG_FREG, /* 0x1a9 */ - REG_FREG, /* 0x1aa */ - REG_FREG, /* 0x1ab */ - REG_FREG, /* 0x1ac */ - REG_FREG, /* 0x1ad */ - REG_FREG, /* 0x1ae */ - REG_FREG, /* 0x1af */ - REG_FREG, /* 0x1b0 */ - REG_FREG, /* 0x1b1 */ - REG_FREG, /* 0x1b2 */ - REG_FREG, /* 0x1b3 */ - REG_FREG, /* 0x1b4 */ - REG_FREG, /* 0x1b5 */ - REG_FREG, /* 0x1b6 */ - REG_FREG, /* 0x1b7 */ - REG_FREG, /* 0x1b8 */ - REG_FREG, /* 0x1b9 */ - REG_FREG, /* 0x1ba */ - REG_FREG, /* 0x1bb */ - REG_FREG, /* 0x1bc */ - REG_FREG, /* 0x1bd */ - REG_FREG, /* 0x1be */ - REG_FREG, /* 0x1bf */ - REG_FREG, /* 0x1c0 */ - REG_FREG, /* 0x1c1 */ - REG_FREG, /* 0x1c2 */ - REG_FREG, /* 0x1c3 */ - REG_FREG, /* 0x1c4 */ - REG_FREG, /* 0x1c5 */ - REG_FREG, /* 0x1c6 */ - REG_FREG, /* 0x1c7 */ - REG_FREG, /* 0x1c8 */ - REG_FREG, /* 0x1c9 */ - REG_FREG, /* 0x1ca */ - REG_FREG, /* 0x1cb */ - REG_FREG, /* 0x1cc */ - REG_FREG, /* 0x1cd */ - REG_FREG, /* 0x1ce */ - REG_FREG, /* 0x1cf */ - REG_FREG, /* 0x1d0 */ - REG_FREG, /* 0x1d1 */ - REG_FREG, /* 0x1d2 */ - REG_FREG, /* 0x1d3 */ - REG_FREG, /* 0x1d4 */ - REG_FREG, /* 0x1d5 */ - REG_FREG, /* 0x1d6 */ - REG_FREG, /* 0x1d7 */ - REG_FREG, /* 0x1d8 */ - REG_FREG, /* 0x1d9 */ - REG_FREG, /* 0x1da */ - REG_FREG, /* 0x1db */ - REG_FREG, /* 0x1dc */ - REG_FREG, /* 0x1dd */ - REG_FREG, /* 0x1de */ - REG_FREG, /* 0x1df */ - REG_FREG, /* 0x1e0 */ - REG_FREG, /* 0x1e1 */ - REG_FREG, /* 0x1e2 */ - REG_FREG, /* 0x1e3 */ - REG_FREG, /* 0x1e4 */ - REG_FREG, /* 0x1e5 */ - REG_FREG, /* 0x1e6 */ - REG_FREG, /* 0x1e7 */ - REG_FREG, /* 0x1e8 */ - REG_FREG, /* 0x1e9 */ - REG_FREG, /* 0x1ea */ - REG_FREG, /* 0x1eb */ - REG_FREG, /* 0x1ec */ - REG_FREG, /* 0x1ed */ - REG_FREG, /* 0x1ee */ - REG_FREG, /* 0x1ef */ - REG_FREG, /* 0x1f0 */ - REG_FREG, /* 0x1f1 */ - REG_FREG, /* 0x1f2 */ - REG_FREG, /* 0x1f3 */ - REG_FREG, /* 0x1f4 */ - REG_FREG, /* 0x1f5 */ - REG_FREG, /* 0x1f6 */ - REG_FREG, /* 0x1f7 */ - REG_FREG, /* 0x1f8 */ - REG_FREG, /* 0x1f9 */ - REG_FREG, /* 0x1fa */ - REG_FREG, /* 0x1fb */ - REG_FREG, /* 0x1fc */ - REG_FREG, /* 0x1fd */ - REG_FREG, /* 0x1fe */ - REG_FREG, /* 0x1ff */ -}; -// clang-format on - -// memory map for PIC16F883 and PIC16F884 are same -PicMidrangeRegType *pic16f887_reg_map = pic16f886_reg_map; - -#endif // RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F886_H diff --git a/librz/analysis/arch/pic/pic16f_memmaps/regtypes.h b/librz/analysis/arch/pic/pic16f_memmaps/regtypes.h deleted file mode 100644 index f4774911e04..00000000000 --- a/librz/analysis/arch/pic/pic16f_memmaps/regtypes.h +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-FileCopyrightText: 2023 Siddharth Mishra -// SPDX-License-Identifier: LGPL-3.0-only - -/** - * Defines the various reigster types supported by the PIC16F family - * and a lookup table to map from these register types to their string names. - * */ - -#ifndef RZ_PIC_MIDRANGE_PIC_REGTYPES_H -#define RZ_PIC_MIDRANGE_PIC_REGTYPES_H - -// clang-format off - -/** - * Instead of storing strings in file register map, - * it's better to store enums in order to save memory. - * */ -typedef enum pic_midrange_reg_type_t { - REG_INDF, - REG_TMR0, - REG_PCL, /* lower byte of PC register */ - REG_STATUS, /* status register */ - REG_FSR, - REG_PORTA, - REG_PORTB, - REG_PORTC, - REG_PORTD, - REG_PORTE, - REG_PORTF, - REG_PORTG, - REG_PCLATH, /* PCLATH is used to control PCH (higher part of PC reg)*/ - REG_INTCON, - REG_PIR1, - REG_PIR2, - REG_TMR1L, - REG_TMR1H, - REG_T1CON, - REG_TMR2, - REG_T2CON, - REG_SSPBUF, - REG_SSPCON, - REG_SSPCON2, - REG_CCPR1L, - REG_CCPR1H, - REG_CCP1CON, - REG_RCSTA, - REG_TXREG, - REG_RCREG, - REG_CCPR2L, - REG_CCPR2H, - REG_CCP2CON, - REG_ADRESH, - REG_ADRESL, - REG_ADCON0, - REG_ADCON, - REG_OPTION_REG, - REG_TRISA, - REG_TRISB, - REG_TRISC, - REG_TRISD, - REG_TRISE, - REG_TRISF, - REG_TRISG, - REG_PIE1, - REG_PIE2, - REG_PCON, - REG_OSCCON, - REG_OSCCAL, - REG_PR2, - REG_SSPADD, - REG_SSPSTAT, - REG_TXSTA, - REG_SPBRG, - REG_SPBRGH, - REG_ADDCON1, - REG_OSCTUNE, - REG_WPUB, - REG_IOCB, - REG_VRCON, - REG_PWM1CON, - REG_ECCPAS, - REG_PSTRCON, - REG_ADCON1, - REG_WDTCON, - REG_CM1CON0, - REG_CM2CON0, - REG_CM2CON1, - REG_EEDAT, - REG_EEADR, - REG_EEDATH, - REG_EEADRH, - REG_SRCON, - REG_BAUDCTL, - REG_ANSEL, - REG_ANSELH, - REG_EECON1, - REG_EECON2, - REG_RESERVED, - REG_FREG, /* normal indexed file register */ - REG_UNIMPLEMENTED, /* unimplemented registers are read as 0 */ - REG_NUM /* can be used when a function fails and want to return an invalid value */ -} PicMidrangeRegType; - -/** - * Map from reg enums to reg names - * */ -const char* pic_midrange_il_regnames[REG_UNIMPLEMENTED + 1] = { - [REG_INDF] = "REG_INDF", - [REG_TMR0] = "REG_TMR0", - [REG_PCL] = "REG_PCL", - [REG_STATUS] = "REG_STATUS", - [REG_FSR] = "REG_FSR", - [REG_PORTA] = "REG_PORTA", - [REG_PORTB] = "REG_PORTB", - [REG_PORTC] = "REG_PORTC", - [REG_PORTD] = "REG_PORTD", - [REG_PORTE] = "REG_PORTE", - [REG_PORTF] = "REG_PORTF", - [REG_PORTG] = "REG_PORTG", - [REG_PCLATH] = "REG_PCLATH", - [REG_INTCON] = "REG_INTCON", - [REG_PIR1] = "REG_PIR1", - [REG_PIR2] = "REG_PIR2", - [REG_TMR1L] = "REG_TMR1L", - [REG_TMR1H] = "REG_TMR1H", - [REG_T1CON] = "REG_T1CON", - [REG_TMR2] = "REG_TMR2", - [REG_T2CON] = "REG_T2CON", - [REG_SSPBUF] = "REG_SSPBUF", - [REG_SSPCON] = "REG_SSPCON", - [REG_SSPCON2] = "REG_SSPCON2", - [REG_CCPR1L] = "REG_CCPR1L", - [REG_CCPR1H] = "REG_CCPR1H", - [REG_CCP1CON] = "REG_CCP1CON", - [REG_RCSTA] = "REG_RCSTA", - [REG_TXREG] = "REG_TXREG", - [REG_RCREG] = "REG_RCREG", - [REG_CCPR2L] = "REG_CCPR2L", - [REG_CCPR2H] = "REG_CCPR2H", - [REG_CCP2CON] = "REG_CCP2CON", - [REG_ADRESH] = "REG_ADRESH", - [REG_ADRESL] = "REG_ADRESL", - [REG_ADCON0] = "REG_ADCON0", - [REG_ADCON] = "REG_ADCON", - [REG_OPTION_REG] = "REG_OPTION_REG", - [REG_TRISA] = "REG_TRISA", - [REG_TRISB] = "REG_TRISB", - [REG_TRISC] = "REG_TRISC", - [REG_TRISD] = "REG_TRISD", - [REG_TRISE] = "REG_TRISE", - [REG_TRISF] = "REG_TRISF", - [REG_TRISG] = "REG_TRISG", - [REG_PIE1] = "REG_PIE1", - [REG_PIE2] = "REG_PIE2", - [REG_PCON] = "REG_PCON", - [REG_OSCCON] = "REG_OSCCON", - [REG_OSCCAL] = "REG_OSCCAL", - [REG_PR2] = "REG_PR2", - [REG_SSPADD] = "REG_SSPADD", - [REG_SSPSTAT] = "REG_SSPSTAT", - [REG_TXSTA] = "REG_TXSTA", - [REG_SPBRG] = "REG_SPBRG", - [REG_SPBRGH] = "REG_SPBRGH", - [REG_ADDCON1] = "REG_ADDCON1", - [REG_OSCTUNE] = "REG_OSCTUNE", - [REG_WPUB] = "REG_WPUB", - [REG_IOCB] = "REG_IOCB", - [REG_VRCON] = "REG_VRCON", - [REG_PWM1CON] = "REG_PWM1CON", - [REG_ECCPAS] = "REG_ECCPAS", - [REG_PSTRCON] = "REG_PSTRCON", - [REG_ADCON1] = "REG_ADCON1", - [REG_WDTCON] = "REG_WDTCON", - [REG_CM1CON0] = "REG_CM1CON0", - [REG_CM2CON0] = "REG_CM2CON0", - [REG_CM2CON1] = "REG_CM2CON1", - [REG_EEDAT] = "REG_EEDAT", - [REG_EEADR] = "REG_EEADR", - [REG_EEDATH] = "REG_EEDATH", - [REG_EEADRH] = "REG_EEADRH", - [REG_SRCON] = "REG_SRCON", - [REG_BAUDCTL] = "REG_BAUDCTL", - [REG_ANSEL] = "REG_ANSEL", - [REG_ANSELH] = "REG_ANSELH", - [REG_EECON1] = "REG_EECON1", - [REG_EECON2] = "REG_EECON2", - [REG_RESERVED] = "REG_RESERVED", - [REG_FREG] = "REG_FREG", - [REG_UNIMPLEMENTED] = "REG_UNIMPLEMENTED", -}; - -// clang-format on - -#endif // RZ_PIC_MIDRANGE_PIC_REGTYPES_H diff --git a/librz/analysis/arch/pic/pic_il.h b/librz/analysis/arch/pic/pic_il.h deleted file mode 100644 index 45043f6b8fb..00000000000 --- a/librz/analysis/arch/pic/pic_il.h +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-FileCopyrightText: 2023 Siddharth Mishra -// SPDX-License-Identifier: LGPL-3.0-only - -#ifndef PIC_IL_H_ -#define PIC_IL_H_ - -#include - -/** - * PIC Mid-Range Device Type. - * Since each device has it's own set of supported instructions - * and memory map (# of banks, register arrangement etc...), - * we'll support analysis of each of these devices differently! - * */ -typedef enum pic16f_device_type_t { - PIC16F882, - PIC16F883, - PIC16F884, - PIC16F886, - PIC16F887, - PIC_MIDRANGE_SUPPORTED_DEVICE_NUM -} PicMidrangeDeviceType; - -/** - * This struct will store the CPU state of a PIC Mid-Range - * device while being uplifted. - * - * Register are indexed using a value between 0x00-0x7f and a selected bank. - * Instructions are indexed using a page selector (PCLATH) - * Hence we need to maintain a state of CPU while being analyzed. - * - * This opens possibilities of storing more useful data to improve the process. - * */ -typedef struct pic_midrange_cpu_state_t { - PicMidrangeDeviceType device_type; - ut8 selected_bank; ///< for register indexing. - ut8 selected_page; ///< for instruction indexing. -} PicMidrangeCPUState; - -RZ_IPI RZ_OWN PicMidrangeCPUState *rz_pic_midrange_new_cpu_state(PicMidrangeDeviceType device_type); -RZ_IPI RzAnalysisILConfig *rz_midrange_il_vm_config(RZ_NONNULL RzAnalysis *analysis, PicMidrangeDeviceType device_type); -RZ_IPI RzILOpEffect *rz_midrange_il_op(RZ_NONNULL RzAnalysis *analysis, - RZ_NONNULL RZ_BORROW RzAnalysisOp *op, - RZ_NONNULL PicMidrangeCPUState *cpu_state, - ut16 instr); - -// baseline -/* RZ_IPI RzAnalysisILConfig *rz_pic_baseline_il_vm_config(RZ_NONNULL RzAnalysis *analysis); */ -/* RZ_IPI RzILOpEffect *rz_pic_baseline_il_op(RZ_NONNULL RzAnalysis *analysis, RZ_NONNULL RZ_BORROW RzAnalysisOp *op, ut16 instr ; */ - -// TODO: Add support for PIC18F & other device families - -#endif // PIC_IL_H_ diff --git a/librz/analysis/arch/pic/pic_midrange_il.c b/librz/analysis/arch/pic/pic_midrange_il.c deleted file mode 100644 index a7b07196d95..00000000000 --- a/librz/analysis/arch/pic/pic_midrange_il.c +++ /dev/null @@ -1,480 +0,0 @@ -// SPDX-FileCopyrightText: 2023 Siddharth Mishra -// SPDX-License-Identifier: LGPL-3.0-only - -#include -#include - -#include "pic_il.h" -#include "../../../arm/arch/pic/pic_midrange.h" - -#include - -// HELPER DEFINES & TYPEDEFS - -typedef RzILOpEffect *(PicILUplifter)(ut16 instr); -#define IL_LIFTER(op) pic_midrange_##op_il_lifter(RZ_NONNULL PicMidrangeCPUState *cpu_state, ut16 instr) - -// REGISTER DECLARATIONS & DEFINITIONS -#include "pic16f_memmaps/memmaps.h" -#define GET_REG_NAME(reg_type) GET_REG_NAME(reg_type) -#define GET_WREG() VARG("WREG") -#define GET_FREG(idx) VARG("FREG" #idx) -// idx is kept with name in order to differentiate between same registers of different banks -#define GET_SPREG(name, bank) VARG(name) -#define BANK_SIZE ((ut32)0x80) -#define BANK_COMMON_MAP_LOW cpu_state->selected_bank *BANK_SIZE + 0X70 -#define BANK_COMMON_MAP_HIGH cpu_state->selected_bank *BANK_SIZE + 0X7F - -// fields inside status register -const char *pic_midrange_status_flags[] = { - "IRP", "RP1", "RP0", "TO", "PD", "Z", "DC", "C" -}; - -#define IRP 7 -#define RP1 6 -#define RP0 5 -#define TO 4 -#define PD 3 -#define Z 2 -#define DC 1 -#define C 0 -#define STATUS(x) pic_midrange_status_flags[x] - -// device to register schema map -const char **pic_midrange_device_reg_map[] = { - [PIC16F882] = pic16f882_reg_map, - [PIC16F883] = pic16f883_reg_map, - [PIC16F884] = pic16f884_reg_map, - [PIC16F886] = pic16f886_reg_map, - [PIC16F887] = pic16f887_reg_map, -}; - -/** - * Get PicMidrangeRegType corresponding to give register index - * - * \param cpu_state Device CPU state. - * \param regidx Register index inside given bank of given device type. - * - * \return PicMidrangeRegType - * */ -PicMidrangeRegType pic_midrange_il_get_reg_type(RZ_NONNULL PicMidrangeCPUState *cpu_state, ut8 regidx) { - rz_return_val_if_fail(cpu_state, REG_INVALID); - - // compute linear register address - ut32 addr = cpu_state->selected_bank * BANK_SIZE + regidx; - return pic_midrange_device_reg_map[cpu_state->device_type][addr]; -} - -/** - * Get RzILOpPure corresponding to given register index of given device type. - * - * \param cpu_state Device CPU state. - * \paramm regidx Register index in given memory bank of given device type. - * - * \return valid RzILOpPure on success, NULL otherwise. - * */ -RzILOpPure *pic_midrange_il_get_reg(RZ_NONNULL PicMidrangeCPUState *cpu_state, ut8 regidx) { - rz_return_val_if_fail(cpu_state, NULL); - - // compute linear address - ut32 addr = cpu_state->selected_bank * BANK_SIZE + regidx; - PicMidrangeRegType reg_type = pic_midrange_device_reg_map[device_type][addr]; - - // return register for given type - if (reg_type == REG_FREG) { - // last 16 registers in higher banks are mapped to bank 0 - if (addr >= BANK_COMMON_MAP_LOW && addr <= BANK_COMMON_MAP_HIGH) { - addr = regidx; - } - return GET_FREG(addr); - } else if (reg_type == REG_UNIMPLEMENTED || reg_type == REG_RESERVED) { - return GET_SPREG(GET_REG_NAME(reg_type)) - } else { - // for other special registers we need to append their bank index at the end - // in order to avoid confusions - // IDK any better way to do this atm. - // allocating 4 extra bytes at the end to make sure devices with 128 and more - // # of banks will also be supported. - size_t regnamesz = strlen(GET_REG_NAME(reg_type)) + 4; - const char *regname = malloc(regnamesz); - memset(regname, 0, regnamesz) - strcpy(regname, GET_REG_NAME(reg_type)); - char *bankstr = rz_num_as_string(NULL, cpu_state->selected_bank, true); - if (!bankstr) { - RZ_LOG_ERROR("RzIL : FAILED TO CONVERT NUMBER TO STRING"); - return NULL; - } - strcat(regname, bankstr); - free(bankstr); - } -} - -// use only in IL_LIFTER functions -#define GET_REG_TYPE(idx) pic_midrange_il_get_reg_type(cpu_state, idx) -#define GET_REG(idx) pic_midrange_il_get_reg(cpu_state, idx); - -#define GET_REG_7F(varname) \ - RzILOpPure *varname = NULL; \ - do { \ - ut8 regidx = PIC_MIDRANGE_OP_ARGS_7F_GET_F(instr); \ - ut8 addr = cpu_state->selected_bank * BANK_SIZE + regidx; \ - PicMidrangeRegType reg_type = GET_REG_TYPE(addr); \ - if (reg_type == REG_UNIMPLEMENTED || reg_type == REG_RESERVED) { \ - freg = U8(0); \ - } else { \ - freg = GET_REG(regidx); \ - } \ - } while (0) - -// overflow is not used in status register but just keeping this for future "maybe" use -#define CHECK_OVERFLOW(x, y, res) AND(XOR(MSB(x), MSB(res)), XOR(MSB(y), MSB(res))) -#define CHECK_CARRY(x, y, res) OR(AND(MSB(x), MSB(y)), AND(OR(MSB(x), MSB(y)), INV(MSB(res)))) -#define CHECK_BORROW(x, y, res) OR(OR(AND(INV(MSB(x)), MSB(y)), AND(INV(MSB(x)), MSB(res))), AND(MSB(x), AND(MSB(y), MSB(res)))) -#define CHECK_DIGIT_CARRY(x, y, res) OR(AND(BITN(x, 3), BITN(y, 3)), AND(OR(BITN(x, 3), BITN(y, 3)), INV(BITN(res, 3)))) -#define CHECK_DIGIT_BORROW(x, y, res) OR(OR(AND(INV(BITN(x, 3)), BITN(y, 3)), AND(INV(BITN(x, 3)), BITN(res, 3))), AND(BITN(x, 3), AND(BITN(y, 3), BITN(res, 3)))) - -/** - * Handle C, DC & Z flags for the previous operation. - * To be used after an arithmetic operation. - * Order of operands must be preserved for subtraction - * operations, i.e `add = false` - * - * \param x First operand - * \param y Second operand - * \param res Result of last performed operation that affected the flag. - * \param add Was this an add operation? - * - * \return \c RzILOpEffect containing set of steps to set status flags. - * */ -RzILOpEffect *pic_midrange_il_set_arithmetic_flags(RZ_BORROW RzILOpPure *x, RZ_BORROW RzILOpPure *y, RZ_BORROW RzILOpPure *res, bool add) { - // get carry flag - RzILOpBool *cf = NULL; - RzILOpBool *dcf = NULL; - if (add) { - cf = CHECK_CARRY(x, y, res); - dcf = CHECK_DIGIT_CARRY(x, y, res); - } else { // sub - cf = CHECK_BORROW(x, y, res); - dcf = CHECK_DIGIT_BORROW(x, y, res); - } - - // get zero flag - RzILOpBool *zf = IS_ZERO(res); - - return SEQ3(SETG(STATUS(C), cf), - SETG(STATUS(DC), dcf), - SETG(STATUS(Z), zf)); -} - -#define SET_STATUS_ADD(x, y, r) pic_midrange_il_set_arithmetic_flags(x, y, r, true) -#define SET_STATUS_SUB(x, y, r) pic_midrange_il_set_arithmetic_flags(x, y, r, false) - -// INSTRUCTIONS LOOKUP-TABLE -// clang-format off -PicILUplifter pic_midrange_il_uplifters[] = { - [PIC_MIDRANGE_OPCODE_NOP] = IL_LIFTER(NOP), - [PIC_MIDRANGE_OPCODE_RETURN] = IL_LIFTER(RETURN), - [PIC_MIDRANGE_OPCODE_RETFIE] = IL_LIFTER(RETFIE), - [PIC_MIDRANGE_OPCODE_OPTION] = IL_LIFTER(OPTION), - [PIC_MIDRANGE_OPCODE_SLEEP] = IL_LIFTER(SLEEP), - [PIC_MIDRANGE_OPCODE_CLRWDT] = IL_LIFTER(CLRWDT), - [PIC_MIDRANGE_OPCODE_TRIS] = IL_LIFTER(TRIS), - [PIC_MIDRANGE_OPCODE_MOVWF] = IL_LIFTER(MOVWF), - [PIC_MIDRANGE_OPCODE_CLR] = IL_LIFTER(CLR), - [PIC_MIDRANGE_OPCODE_SUBWF] = IL_LIFTER(SUBWF), - [PIC_MIDRANGE_OPCODE_DECF] = IL_LIFTER(DECF), - [PIC_MIDRANGE_OPCODE_IORWF] = IL_LIFTER(IORWF), - [PIC_MIDRANGE_OPCODE_ANDWF] = IL_LIFTER(ANDWF), - [PIC_MIDRANGE_OPCODE_XORWF] = IL_LIFTER(XORWF), - [PIC_MIDRANGE_OPCODE_ADDWF] = IL_LIFTER(ADDWF), - [PIC_MIDRANGE_OPCODE_MOVF] = IL_LIFTER(MOVF), - [PIC_MIDRANGE_OPCODE_COMF] = IL_LIFTER(COMF), - [PIC_MIDRANGE_OPCODE_INCF] = IL_LIFTER(INCF), - [PIC_MIDRANGE_OPCODE_DECFSZ] = IL_LIFTER(DECFSZ), - [PIC_MIDRANGE_OPCODE_RRF] = IL_LIFTER(RRF), - [PIC_MIDRANGE_OPCODE_RLF] = IL_LIFTER(RLF), - [PIC_MIDRANGE_OPCODE_SWAPF] = IL_LIFTER(SWAPF), - [PIC_MIDRANGE_OPCODE_INCFSZ] = IL_LIFTER(INCFSZ), - [PIC_MIDRANGE_OPCODE_BCF] = IL_LIFTER(BCF), - [PIC_MIDRANGE_OPCODE_BSF] = IL_LIFTER(BSF), - [PIC_MIDRANGE_OPCODE_BTFSC] = IL_LIFTER(BTFSC), - [PIC_MIDRANGE_OPCODE_BTFSS] = IL_LIFTER(BTFSS), - [PIC_MIDRANGE_OPCODE_CALL] = IL_LIFTER(CALL), - [PIC_MIDRANGE_OPCODE_GOTO] = IL_LIFTER(GOTO), - [PIC_MIDRANGE_OPCODE_MOVLW] = IL_LIFTER(MOVLW), - [PIC_MIDRANGE_OPCODE_RETLW] = IL_LIFTER(RETLW), - [PIC_MIDRANGE_OPCODE_IORLW] = IL_LIFTER(IORLW), - [PIC_MIDRANGE_OPCODE_ANDLW] = IL_LIFTER(ANDLW), - [PIC_MIDRANGE_OPCODE_XORLW] = IL_LIFTER(XORLW), - [PIC_MIDRANGE_OPCODE_SUBLW] = IL_LIFTER(SUBLW), - [PIC_MIDRANGE_OPCODE_ADDLW] = IL_LIFTER(ADDLW), - [PIC_MIDRANGE_OPCODE_RESET] = IL_LIFTER(RESET), - [PIC_MIDRANGE_OPCODE_CALLW] = IL_LIFTER(CALLW), - [PIC_MIDRANGE_OPCODE_BRW] = IL_LIFTER(BRW), - [PIC_MIDRANGE_OPCODE_MOVIW_1] = IL_LIFTER(MOVIW_1), - [PIC_MIDRANGE_OPCODE_MOVWI_1] = IL_LIFTER(MOVWI_1), - [PIC_MIDRANGE_OPCODE_MOVLB] = IL_LIFTER(MOVLB), - [PIC_MIDRANGE_OPCODE_LSLF] = IL_LIFTER(LSLF), - [PIC_MIDRANGE_OPCODE_LSRF] = IL_LIFTER(LSRF), - [PIC_MIDRANGE_OPCODE_ASRF] = IL_LIFTER(ASRF), - [PIC_MIDRANGE_OPCODE_SUBWFB] = IL_LIFTER(SUBWFB), - [PIC_MIDRANGE_OPCODE_ADDWFC] = IL_LIFTER(ADDWFC), - [PIC_MIDRANGE_OPCODE_ADDFSR] = IL_LIFTER(ADDFSR), - [PIC_MIDRANGE_OPCODE_MOVLP] = IL_LIFTER(MOVLP), - [PIC_MIDRANGE_OPCODE_BRA] = IL_LIFTER(BRA), - [PIC_MIDRANGE_OPCODE_MOVIW_2] = IL_LIFTER(MOVIW_2), - [PIC_MIDRANGE_OPCODE_MOVWI_2] = IL_LIFTER(MOVWI_2), - [PIC_MIDRANGE_OPCODE_INVALID] = NULL -}; -// clang-format on - -/** - * NOP - * Operation: No Operation. - * Operands: NONE - * Status affected : NONE - * */ -IL_LIFTER(NOP) { - NOP(); -} - -IL_LIFTER(RETURN) {} -IL_LIFTER(RETFIE) {} -IL_LIFTER(OPTION) {} -IL_LIFTER(SLEEP) {} -IL_LIFTER(CLRWDT) {} -IL_LIFTER(TRIS) {} -IL_LIFTER(MOVWF) {} -IL_LIFTER(CLR) {} - -/** - * SUBWF - * Operation: Subtract FREG from WREG. - * Operands: f, d - * Status affected : C, DC, Z - * */ -IL_LIFTER(SUBWF) { - GET_REG_7F(freg); - RzILOpPure *wreg = GET_WREG(); - - // if d bit is enabled then result will go in freg else wreg - bool reg_dest = PIC_MIDRANGE_OP_PARGS_7F_GET_D(instr); - RzILOpPure *dest = reg_dest : freg ? wreg; - - // create a copy of current value of wreg because it's going to change - RzILOpEffect *wreg_old = SETL("wreg_old", wreg); - RzILOpEffect *sub_op = SETG(dest, SUB(wreg, freg)); - RzILOpEffect *set_status_op = SET_STATUS_SUB(VARL("wreg_old"), freg, wreg); - return SEQ3(wreg_old, sub_op, set_status_op); -} - -IL_LIFTER(DECF) {} -IL_LIFTER(IORWF) {} - -/** - * ANDWF - * Operation: Take logical AND of FREG and WREG. - * Operands: f, d - * Status affected : Z - * */ -IL_LIFTER(ANDWF) { - GET_REG_7F(freg); - - // if d bit is enabled then result will go in freg else wreg - bool reg_dest = PIC_MIDRANGE_OP_PARGS_7F_GET_D(instr); - RzILOpPure *dest = reg_dest : freg ? GET_WREG(); - - // create a copy of current value of wreg because it's going to change - RzILOpEffect *and_op = SETG(dest, LOGAND(GET_WREG(), freg)); - RzILOpEffect *set_status_op = IS_ZERO(GET_WREG()); - return SEQ2(and_op, set_status_op); -} - -/** - * ANDWF - * Operation: Take logical AND of FREG and WREG. - * Operands: f, d - * Status affected : Z - * */ -IL_LIFTER(XORWF) { - GET_REG_7F(freg); - RzILOpPure *wreg = GET_WREG(); - - // if d bit is enabled then result will go in freg else wreg - bool reg_dest = PIC_MIDRANGE_OP_PARGS_7F_GET_D(instr); - RzILOpPure *dest = reg_dest : freg ? wreg; - - // create a copy of current value of wreg because it's going to change - RzILOpEffect *and_op = SETG(dest, LOGAND(wreg, freg)); - RzILOpEffect *set_status_op = IS_ZERO(wreg); - return SEQ2(and_op, set_status_op); -} - -/** - * ADDWF - * Operation: Add FREG to WREG. - * Operands: f, d - * Status affected : C, DC, Z - * */ -IL_LIFTER(ADDWF) { - GET_REG_7F(freg); - RzILOpPure *wreg = GET_WREG(); - - // if d bit is enabled then result will go in freg else wreg - bool reg_dest = PIC_MIDRANGE_OP_PARGS_7F_GET_D(instr); - RzILOpPure *dest = reg_dest : freg ? wreg; - - // create a copy of current value of wreg because it's going to change - RzILOpEffect *wreg_old = SETL("wreg_old", wreg); - RzILOpEffect *add_op = SETG(dest, ADD(wreg, freg)); - RzILOpEffect *set_status_op = SET_STATUS_ADD(VARL("wreg_old"), freg, wreg); - return SEQ3(wreg_old, add_op, set_status_op); -} - -IL_LIFTER(MOVF) {} -IL_LIFTER(COMF) {} -IL_LIFTER(INCF) {} -IL_LIFTER(DECFSZ) {} -IL_LIFTER(RRF) {} -IL_LIFTER(RLF) {} -IL_LIFTER(SWAPF) {} -IL_LIFTER(INCFSZ) {} -IL_LIFTER(BCF) {} -IL_LIFTER(BSF) {} -IL_LIFTER(BTFSC) {} -IL_LIFTER(BTFSS) {} -IL_LIFTER(CALL) {} -IL_LIFTER(GOTO) {} -IL_LIFTER(MOVLW) {} -IL_LIFTER(RETLW) {} - -IL_LIFTER(IORLW) {} - -/** - * ANDLW. - * Operation: Take logical AND between literal and WREG - * Operands: Literal (k) - * Status affected : Z - * */ -IL_LIFTER(ANDLW) { - ut8 literal = PIC_MIDRANGE_OP_ARGS_8K_GET_K(instr); - RzILOpPure *wreg = GET_WREG(); - RzILOpEffect *and_op = SETG(wreg, LOGAND(wreg, U8(literal))); - RzILOpEffect *set_status_op = SET(STATUS(Z), IS_ZERO(wreg)); - return SEQ2(and_op, set_status_op); -} - -/** - * XORLW. - * Operation: Take logical XOR between literal and WREG - * Operands: Literal (k) - * Status affected : Z - * */ -IL_LIFTER(XORLW) { - ut8 literal = PIC_MIDRANGE_OP_ARGS_8K_GET_K(instr); - RzILOpPure *wreg = GET_WREG(); - RzILOpEffect *xor_op = SETG(wreg, LOGXOR(wreg, U8(literal))); - RzILOpEffect *set_status_op = SET(STATUS(Z), IS_ZERO(wreg)); - return SEQ2(xor_op, set_status_op); -} - -/** - * SUBLW. - * Operation: Subtract Literal From WREG - * Operands: Literal (k) - * Status affected : C, DC, Z - * */ -IL_LIFTER(SUBLW) { - ut8 literal = PIC_MIDRANGE_OP_ARGS_8K_GET_K(instr); - RzILOpPure *wreg = GET_WREG(); - RzILOpEffect *wreg_old = SETL("wreg_old", wreg); - RzILOpEffect *sub_op = SETG(wreg, SUB(wreg, U8(literal))); - RzILOpEffect *set_status_op = SET_STATUS_SUB(VARL("wreg_old"), U8(literal), wreg); - return SEQ3(wreg_old, sub_op, set_status_op); -} - -/** - * ADDLW. - * Operation: Add Literal To WREG - * Operands: Literal (k) - * Status affected : C, DC, Z - * */ -IL_LIFTER(ADDLW) { - ut8 literal = PIC_MIDRANGE_OP_ARGS_8K_GET_K(instr); - RzILOpPure *wreg = GET_WREG(); - RzILOpEffect *wreg_old = SETL("wreg_old", wreg); - RzILOpEffect *add_op = SETG(wreg, ADD(wreg, U8(literal))); - RzILOpEffect *set_status_op = SET_STATUS_ADD(VARL("wreg_old"), U8(literal), wreg); - return SEQ3(wreg_old, add_op, set_status_op); -} - -IL_LIFTER(RESET) {} -IL_LIFTER(CALLW) {} -IL_LIFTER(BRW) {} -IL_LIFTER(MOVIW_1) {} -IL_LIFTER(MOVWI_1) {} -IL_LIFTER(MOVLB) {} -IL_LIFTER(LSLF) {} -IL_LIFTER(LSRF) {} -IL_LIFTER(ASRF) {} -IL_LIFTER(SUBWFB) {} -IL_LIFTER(ADDWFC) {} -IL_LIFTER(ADDFSR) {} -IL_LIFTER(MOVLP) {} -IL_LIFTER(BRA) {} -IL_LIFTER(MOVIW_2) {} -IL_LIFTER(MOVWI_2) {} -IL_LIFTER(INVALID) {} - -/** - * Create new Mid-Range device CPU state. - * - * \param device_type Device to to initialize CPU state for. - * - * \return Valid ptr to PicMidrangeCPUState on success, NULL otherwise. - * */ -RZ_IPI RZ_OWN PicMidrangeCPUState *rz_pic_midrange_new_cpu_state(PicMidrangeDeviceType device_type) { - if (device_type >= PIC_MIDRANGE_SUPPORTED_DEVICE_NUM) { - RZ_LOG_ERROR("RzIL : Invalid PIC Mid-Range device type provided"); - } - - PicMidrangeCPUState *cpu_state = malloc(sizeof(PicMidrangeCPUState)); - if (!cpu_state) { - return NULL; - } - - cpu_state->device_type = device_type; - cpu_state->selected_bank = 0; // initially bank is 0 - cpu_state->selected_page = 0; // initially page is 0 -} - -RZ_IPI RzILOpEffect *rz_midrange_il_op(RZ_NONNULL RzAnalysis *analysis, RZ_NONNULL RZ_BORROW RzAnalysisOp *op, RZ_NONNULL RZ_BORROW PicMidrangeCPUState *cpu_state, ut16 instr) { - // get opcode - PicMidrangeOpcode opcode = pic_midrange_get_opcode(instr); - if (opcode == PIC_MIDRANGE_OPCODE_INVALID) { - return NULL; - } - - // get opargs - PicMidrangeOpArgs opargs = pic_midrange_get_opargs(instr); - - // uplift - PicILUplifter uplifter = pic_midrange_il_uplifters[opcode]; - if (uplifter) { - return uplifter(opargs, instr); - } - - // return NULL on failure - return NULL; -} - -/** - * \brief Returns IL VM config for given PIC Mid-Range device type. - * - * \param analysis \c RzAnalysis instance. - * \param device_type Device type in PIC16F family. - * - * \return valid ptr to RzAnalysisILConfig on success, NULL otherwise. - * */ -RZ_IPI RzAnalysisILConfig *rz_midrange_il_vm_config(RZ_NONNULL RzAnalysis *analysis, PicMidrangeDeviceType device_type) { -} diff --git a/librz/analysis/arch/pic/pic16f_memmaps/memmaps.h b/librz/arch/isa/pic/pic16f_memmaps/memmaps.h similarity index 100% rename from librz/analysis/arch/pic/pic16f_memmaps/memmaps.h rename to librz/arch/isa/pic/pic16f_memmaps/memmaps.h diff --git a/librz/arch/isa/pic/pic16f_memmaps/pic16f882.h b/librz/arch/isa/pic/pic16f_memmaps/pic16f882.h new file mode 100644 index 00000000000..a9a56a1c534 --- /dev/null +++ b/librz/arch/isa/pic/pic16f_memmaps/pic16f882.h @@ -0,0 +1,540 @@ +// SPDX-FileCopyrightText: 2023 Siddharth Mishra +// SPDX-License-Identifier: LGPL-3.0-only + +/** + * This file describes the memory map of PICF16882 device in PIC16F family. + * */ + +#ifndef RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F882_H +#define RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F882_H + +#include "regtypes.h" + +// clang-format off +PicMidrangeRegType pic16f882_reg_map[] = { + /* BANK 0 */ + INDF, /* 0x00 */ + TMR0, /* 0x01 */ + PCL, /* 0x02 */ + STATUS, /* 0x03 */ + FSR, /* 0x04 */ + PORTA, /* 0x05 */ + PORTB, /* 0x06 */ + PORTC, /* 0x07 */ + UNIMPLEMENTED, /* 0x08 */ + PORTE, /* 0x09 */ + PCLATH, /* 0x0a */ + INTCON, /* 0x0b */ + PIR1, /* 0x0c */ + PIR2, /* 0x0d */ + TMR1L, /* 0x0e */ + TMR1H, /* 0x0f */ + T1CON, /* 0x10 */ + TMR2, /* 0x11 */ + T2CON, /* 0x12 */ + SSPBUF, /* 0x13 */ + SSPCON, /* 0x14 */ + CCPR1L, /* 0x15 */ + CCPR1H, /* 0x16 */ + CCP1CON, /* 0x17 */ + RCSTA, /* 0x18 */ + TXREG, /* 0x19 */ + RCREG, /* 0x1a */ + CCPR2L, /* 0x1b */ + CCPR2H, /* 0x1c */ + CCP2CON, /* 0x1d */ + ADRESH, /* 0x1e */ + ADCON0, /* 0x1f */ + FREG, /* 0x20 */ + FREG, /* 0x21 */ + FREG, /* 0x22 */ + FREG, /* 0x23 */ + FREG, /* 0x24 */ + FREG, /* 0x25 */ + FREG, /* 0x26 */ + FREG, /* 0x27 */ + FREG, /* 0x28 */ + FREG, /* 0x29 */ + FREG, /* 0x2a */ + FREG, /* 0x2b */ + FREG, /* 0x2c */ + FREG, /* 0x2d */ + FREG, /* 0x2e */ + FREG, /* 0x2f */ + FREG, /* 0x30 */ + FREG, /* 0x31 */ + FREG, /* 0x32 */ + FREG, /* 0x33 */ + FREG, /* 0x34 */ + FREG, /* 0x35 */ + FREG, /* 0x36 */ + FREG, /* 0x37 */ + FREG, /* 0x38 */ + FREG, /* 0x39 */ + FREG, /* 0x3a */ + FREG, /* 0x3b */ + FREG, /* 0x3c */ + FREG, /* 0x3d */ + FREG, /* 0x3e */ + FREG, /* 0x3f */ + FREG, /* 0x40 */ + FREG, /* 0x41 */ + FREG, /* 0x42 */ + FREG, /* 0x43 */ + FREG, /* 0x44 */ + FREG, /* 0x45 */ + FREG, /* 0x46 */ + FREG, /* 0x47 */ + FREG, /* 0x48 */ + FREG, /* 0x49 */ + FREG, /* 0x4a */ + FREG, /* 0x4b */ + FREG, /* 0x4c */ + FREG, /* 0x4d */ + FREG, /* 0x4e */ + FREG, /* 0x4f */ + FREG, /* 0x50 */ + FREG, /* 0x51 */ + FREG, /* 0x52 */ + FREG, /* 0x53 */ + FREG, /* 0x54 */ + FREG, /* 0x55 */ + FREG, /* 0x56 */ + FREG, /* 0x57 */ + FREG, /* 0x58 */ + FREG, /* 0x59 */ + FREG, /* 0x5a */ + FREG, /* 0x5b */ + FREG, /* 0x5c */ + FREG, /* 0x5d */ + FREG, /* 0x5e */ + FREG, /* 0x5f */ + FREG, /* 0x60 */ + FREG, /* 0x61 */ + FREG, /* 0x62 */ + FREG, /* 0x63 */ + FREG, /* 0x64 */ + FREG, /* 0x65 */ + FREG, /* 0x66 */ + FREG, /* 0x67 */ + FREG, /* 0x68 */ + FREG, /* 0x69 */ + FREG, /* 0x6a */ + FREG, /* 0x6b */ + FREG, /* 0x6c */ + FREG, /* 0x6d */ + FREG, /* 0x6e */ + FREG, /* 0x6f */ + FREG, /* 0x70 */ + FREG, /* 0x71 */ + FREG, /* 0x72 */ + FREG, /* 0x73 */ + FREG, /* 0x74 */ + FREG, /* 0x75 */ + FREG, /* 0x76 */ + FREG, /* 0x77 */ + FREG, /* 0x78 */ + FREG, /* 0x79 */ + FREG, /* 0x7a */ + FREG, /* 0x7b */ + FREG, /* 0x7c */ + FREG, /* 0x7d */ + FREG, /* 0x7e */ + FREG, /* 0x7f */ + + /* BANK1 */ + + INDF, /* 0x80 */ + OPTION_REG, /* 0x81 */ + PCL, /* 0x82 */ + STATUS, /* 0x83 */ + FSR, /* 0x84 */ + TRISA, /* 0x85 */ + TRISB, /* 0x86 */ + TRISC, /* 0x87 */ + UNIMPLEMENTED, /* 0x88 */ + TRISE, /* 0x89 */ + PCLATH, /* 0x8a */ + INTCON, /* 0x8b */ + PIE1, /* 0x8c */ + PIE2, /* 0x8d */ + PCON, /* 0x8e */ + OSCCON, /* 0x8f */ + OSCTUNE, /* 0x90 */ + SSPCON2, /* 0x91 */ + PR2, /* 0x92 */ + SSPADD, /* 0x93 */ + SSPSTAT, /* 0x94 */ + WPUB, /* 0x95 */ + IOCB, /* 0x96 */ + VRCON, /* 0x97 */ + RCSTA, /* 0x98 */ + TXSTA, /* 0x99 */ + SPBRG, /* 0x9a */ + SPBRGH, /* 0x9b */ + PWM1CON, /* 0x9c */ + ECCPAS, /* 0x9d */ + ADRESL, /* 0x9e */ + ADCON1, /* 0x9f */ + FREG, /* 0xa0 */ + FREG, /* 0xa1 */ + FREG, /* 0xa2 */ + FREG, /* 0xa3 */ + FREG, /* 0xa4 */ + FREG, /* 0xa5 */ + FREG, /* 0xa6 */ + FREG, /* 0xa7 */ + FREG, /* 0xa8 */ + FREG, /* 0xa9 */ + FREG, /* 0xaa */ + FREG, /* 0xab */ + FREG, /* 0xac */ + FREG, /* 0xad */ + FREG, /* 0xae */ + FREG, /* 0xaf */ + FREG, /* 0xb0 */ + FREG, /* 0xb1 */ + FREG, /* 0xb2 */ + FREG, /* 0xb3 */ + FREG, /* 0xb4 */ + FREG, /* 0xb5 */ + FREG, /* 0xb6 */ + FREG, /* 0xb7 */ + FREG, /* 0xb8 */ + FREG, /* 0xb9 */ + FREG, /* 0xba */ + FREG, /* 0xbb */ + FREG, /* 0xbc */ + FREG, /* 0xbd */ + FREG, /* 0xbe */ + FREG, /* 0xbf */ + UNIMPLEMENTED, /* 0xc0 */ + UNIMPLEMENTED, /* 0xc1 */ + UNIMPLEMENTED, /* 0xc2 */ + UNIMPLEMENTED, /* 0xc3 */ + UNIMPLEMENTED, /* 0xc4 */ + UNIMPLEMENTED, /* 0xc5 */ + UNIMPLEMENTED, /* 0xc6 */ + UNIMPLEMENTED, /* 0xc7 */ + UNIMPLEMENTED, /* 0xc8 */ + UNIMPLEMENTED, /* 0xc9 */ + UNIMPLEMENTED, /* 0xca */ + UNIMPLEMENTED, /* 0xcb */ + UNIMPLEMENTED, /* 0xcc */ + UNIMPLEMENTED, /* 0xcd */ + UNIMPLEMENTED, /* 0xce */ + UNIMPLEMENTED, /* 0xcf */ + UNIMPLEMENTED, /* 0xd0 */ + UNIMPLEMENTED, /* 0xd1 */ + UNIMPLEMENTED, /* 0xd2 */ + UNIMPLEMENTED, /* 0xd3 */ + UNIMPLEMENTED, /* 0xd4 */ + UNIMPLEMENTED, /* 0xd5 */ + UNIMPLEMENTED, /* 0xd6 */ + UNIMPLEMENTED, /* 0xd7 */ + UNIMPLEMENTED, /* 0xd8 */ + UNIMPLEMENTED, /* 0xd9 */ + UNIMPLEMENTED, /* 0xda */ + UNIMPLEMENTED, /* 0xdb */ + UNIMPLEMENTED, /* 0xdc */ + UNIMPLEMENTED, /* 0xdd */ + UNIMPLEMENTED, /* 0xde */ + UNIMPLEMENTED, /* 0xdf */ + UNIMPLEMENTED, /* 0xe0 */ + UNIMPLEMENTED, /* 0xe1 */ + UNIMPLEMENTED, /* 0xe2 */ + UNIMPLEMENTED, /* 0xe3 */ + UNIMPLEMENTED, /* 0xe4 */ + UNIMPLEMENTED, /* 0xe5 */ + UNIMPLEMENTED, /* 0xe6 */ + UNIMPLEMENTED, /* 0xe7 */ + UNIMPLEMENTED, /* 0xe8 */ + UNIMPLEMENTED, /* 0xe9 */ + UNIMPLEMENTED, /* 0xea */ + UNIMPLEMENTED, /* 0xeb */ + UNIMPLEMENTED, /* 0xec */ + UNIMPLEMENTED, /* 0xed */ + UNIMPLEMENTED, /* 0xee */ + UNIMPLEMENTED, /* 0xef */ + FREG, /* 0xf0 */ + FREG, /* 0xf1 */ + FREG, /* 0xf2 */ + FREG, /* 0xf3 */ + FREG, /* 0xf4 */ + FREG, /* 0xf5 */ + FREG, /* 0xf6 */ + FREG, /* 0xf7 */ + FREG, /* 0xf8 */ + FREG, /* 0xf9 */ + FREG, /* 0xfa */ + FREG, /* 0xfb */ + FREG, /* 0xfc */ + FREG, /* 0xfd */ + FREG, /* 0xfe */ + FREG, /* 0xff */ + + /* BANK 2 */ + + INDF, /* 0x100 */ + TMR0, /* 0x101 */ + PCL, /* 0x102 */ + STATUS, /* 0x103 */ + FSR, /* 0x104 */ + WDTCON, /* 0x105 */ + PORTB, /* 0x106 */ + CM1CON0, /* 0x107 */ + CM2CON0, /* 0x108 */ + CM2CON1, /* 0x109 */ + PCLATH, /* 0x10a */ + INTCON, /* 0x10b */ + EEDAT, /* 0x10c */ + EEADR, /* 0x10d */ + EEDATH, /* 0x10e */ + EEADRH, /* 0x10f */ + UNIMPLEMENTED, /* 0x110 */ + UNIMPLEMENTED, /* 0x111 */ + UNIMPLEMENTED, /* 0x112 */ + UNIMPLEMENTED, /* 0x113 */ + UNIMPLEMENTED, /* 0x114 */ + UNIMPLEMENTED, /* 0x115 */ + UNIMPLEMENTED, /* 0x116 */ + UNIMPLEMENTED, /* 0x117 */ + UNIMPLEMENTED, /* 0x118 */ + UNIMPLEMENTED, /* 0x119 */ + UNIMPLEMENTED, /* 0x11a */ + UNIMPLEMENTED, /* 0x11b */ + UNIMPLEMENTED, /* 0x11c */ + UNIMPLEMENTED, /* 0x11d */ + UNIMPLEMENTED, /* 0x11e */ + UNIMPLEMENTED, /* 0x11f */ + UNIMPLEMENTED, /* 0x120 */ + UNIMPLEMENTED, /* 0x121 */ + UNIMPLEMENTED, /* 0x122 */ + UNIMPLEMENTED, /* 0x123 */ + UNIMPLEMENTED, /* 0x124 */ + UNIMPLEMENTED, /* 0x125 */ + UNIMPLEMENTED, /* 0x126 */ + UNIMPLEMENTED, /* 0x127 */ + UNIMPLEMENTED, /* 0x128 */ + UNIMPLEMENTED, /* 0x129 */ + UNIMPLEMENTED, /* 0x12a */ + UNIMPLEMENTED, /* 0x12b */ + UNIMPLEMENTED, /* 0x12c */ + UNIMPLEMENTED, /* 0x12d */ + UNIMPLEMENTED, /* 0x12e */ + UNIMPLEMENTED, /* 0x12f */ + UNIMPLEMENTED, /* 0x130 */ + UNIMPLEMENTED, /* 0x131 */ + UNIMPLEMENTED, /* 0x132 */ + UNIMPLEMENTED, /* 0x133 */ + UNIMPLEMENTED, /* 0x134 */ + UNIMPLEMENTED, /* 0x135 */ + UNIMPLEMENTED, /* 0x136 */ + UNIMPLEMENTED, /* 0x137 */ + UNIMPLEMENTED, /* 0x138 */ + UNIMPLEMENTED, /* 0x139 */ + UNIMPLEMENTED, /* 0x13a */ + UNIMPLEMENTED, /* 0x13b */ + UNIMPLEMENTED, /* 0x13c */ + UNIMPLEMENTED, /* 0x13d */ + UNIMPLEMENTED, /* 0x13e */ + UNIMPLEMENTED, /* 0x13f */ + UNIMPLEMENTED, /* 0x140 */ + UNIMPLEMENTED, /* 0x141 */ + UNIMPLEMENTED, /* 0x142 */ + UNIMPLEMENTED, /* 0x143 */ + UNIMPLEMENTED, /* 0x144 */ + UNIMPLEMENTED, /* 0x145 */ + UNIMPLEMENTED, /* 0x146 */ + UNIMPLEMENTED, /* 0x147 */ + UNIMPLEMENTED, /* 0x148 */ + UNIMPLEMENTED, /* 0x149 */ + UNIMPLEMENTED, /* 0x14a */ + UNIMPLEMENTED, /* 0x14b */ + UNIMPLEMENTED, /* 0x14c */ + UNIMPLEMENTED, /* 0x14d */ + UNIMPLEMENTED, /* 0x14e */ + UNIMPLEMENTED, /* 0x14f */ + UNIMPLEMENTED, /* 0x150 */ + UNIMPLEMENTED, /* 0x151 */ + UNIMPLEMENTED, /* 0x152 */ + UNIMPLEMENTED, /* 0x153 */ + UNIMPLEMENTED, /* 0x154 */ + UNIMPLEMENTED, /* 0x155 */ + UNIMPLEMENTED, /* 0x156 */ + UNIMPLEMENTED, /* 0x157 */ + UNIMPLEMENTED, /* 0x158 */ + UNIMPLEMENTED, /* 0x159 */ + UNIMPLEMENTED, /* 0x15a */ + UNIMPLEMENTED, /* 0x15b */ + UNIMPLEMENTED, /* 0x15c */ + UNIMPLEMENTED, /* 0x15d */ + UNIMPLEMENTED, /* 0x15e */ + UNIMPLEMENTED, /* 0x15f */ + UNIMPLEMENTED, /* 0x160 */ + UNIMPLEMENTED, /* 0x161 */ + UNIMPLEMENTED, /* 0x162 */ + UNIMPLEMENTED, /* 0x163 */ + UNIMPLEMENTED, /* 0x164 */ + UNIMPLEMENTED, /* 0x165 */ + UNIMPLEMENTED, /* 0x166 */ + UNIMPLEMENTED, /* 0x167 */ + UNIMPLEMENTED, /* 0x168 */ + UNIMPLEMENTED, /* 0x169 */ + UNIMPLEMENTED, /* 0x16a */ + UNIMPLEMENTED, /* 0x16b */ + UNIMPLEMENTED, /* 0x16c */ + UNIMPLEMENTED, /* 0x16d */ + UNIMPLEMENTED, /* 0x16e */ + UNIMPLEMENTED, /* 0x16f */ + FREG, /* 0x170 */ + FREG, /* 0x171 */ + FREG, /* 0x172 */ + FREG, /* 0x173 */ + FREG, /* 0x174 */ + FREG, /* 0x175 */ + FREG, /* 0x176 */ + FREG, /* 0x177 */ + FREG, /* 0x178 */ + FREG, /* 0x179 */ + FREG, /* 0x17a */ + FREG, /* 0x17b */ + FREG, /* 0x17c */ + FREG, /* 0x17d */ + FREG, /* 0x17e */ + FREG, /* 0x17f */ + + /* BANK 3 */ + + INDF, /* 0x180 */ + OPTION_REG, /* 0x181 */ + PCL, /* 0x182 */ + STATUS, /* 0x183 */ + FSR, /* 0x184 */ + SRCON, /* 0x185 */ + TRISB, /* 0x186 */ + BAUDCTL, /* 0x187 */ + ANSEL, /* 0x188 */ + ANSELH, /* 0x189 */ + PCLATH, /* 0x18a */ + INTCON, /* 0x18b */ + EECON1, /* 0x18c */ + EECON2, /* 0x18d */ + _RESERVED, /* 0x18e */ + _RESERVED, /* 0x18f */ + UNIMPLEMENTED, /* 0x190 */ + UNIMPLEMENTED, /* 0x191 */ + UNIMPLEMENTED, /* 0x192 */ + UNIMPLEMENTED, /* 0x193 */ + UNIMPLEMENTED, /* 0x194 */ + UNIMPLEMENTED, /* 0x195 */ + UNIMPLEMENTED, /* 0x196 */ + UNIMPLEMENTED, /* 0x197 */ + UNIMPLEMENTED, /* 0x198 */ + UNIMPLEMENTED, /* 0x199 */ + UNIMPLEMENTED, /* 0x19a */ + UNIMPLEMENTED, /* 0x19b */ + UNIMPLEMENTED, /* 0x19c */ + UNIMPLEMENTED, /* 0x19d */ + UNIMPLEMENTED, /* 0x19e */ + UNIMPLEMENTED, /* 0x19f */ + UNIMPLEMENTED, /* 0x1a0 */ + UNIMPLEMENTED, /* 0x1a1 */ + UNIMPLEMENTED, /* 0x1a2 */ + UNIMPLEMENTED, /* 0x1a3 */ + UNIMPLEMENTED, /* 0x1a4 */ + UNIMPLEMENTED, /* 0x1a5 */ + UNIMPLEMENTED, /* 0x1a6 */ + UNIMPLEMENTED, /* 0x1a7 */ + UNIMPLEMENTED, /* 0x1a8 */ + UNIMPLEMENTED, /* 0x1a9 */ + UNIMPLEMENTED, /* 0x1aa */ + UNIMPLEMENTED, /* 0x1ab */ + UNIMPLEMENTED, /* 0x1ac */ + UNIMPLEMENTED, /* 0x1ad */ + UNIMPLEMENTED, /* 0x1ae */ + UNIMPLEMENTED, /* 0x1af */ + UNIMPLEMENTED, /* 0x1b0 */ + UNIMPLEMENTED, /* 0x1b1 */ + UNIMPLEMENTED, /* 0x1b2 */ + UNIMPLEMENTED, /* 0x1b3 */ + UNIMPLEMENTED, /* 0x1b4 */ + UNIMPLEMENTED, /* 0x1b5 */ + UNIMPLEMENTED, /* 0x1b6 */ + UNIMPLEMENTED, /* 0x1b7 */ + UNIMPLEMENTED, /* 0x1b8 */ + UNIMPLEMENTED, /* 0x1b9 */ + UNIMPLEMENTED, /* 0x1ba */ + UNIMPLEMENTED, /* 0x1bb */ + UNIMPLEMENTED, /* 0x1bc */ + UNIMPLEMENTED, /* 0x1bd */ + UNIMPLEMENTED, /* 0x1be */ + UNIMPLEMENTED, /* 0x1bf */ + UNIMPLEMENTED, /* 0x1c0 */ + UNIMPLEMENTED, /* 0x1c1 */ + UNIMPLEMENTED, /* 0x1c2 */ + UNIMPLEMENTED, /* 0x1c3 */ + UNIMPLEMENTED, /* 0x1c4 */ + UNIMPLEMENTED, /* 0x1c5 */ + UNIMPLEMENTED, /* 0x1c6 */ + UNIMPLEMENTED, /* 0x1c7 */ + UNIMPLEMENTED, /* 0x1c8 */ + UNIMPLEMENTED, /* 0x1c9 */ + UNIMPLEMENTED, /* 0x1ca */ + UNIMPLEMENTED, /* 0x1cb */ + UNIMPLEMENTED, /* 0x1cc */ + UNIMPLEMENTED, /* 0x1cd */ + UNIMPLEMENTED, /* 0x1ce */ + UNIMPLEMENTED, /* 0x1cf */ + UNIMPLEMENTED, /* 0x1d0 */ + UNIMPLEMENTED, /* 0x1d1 */ + UNIMPLEMENTED, /* 0x1d2 */ + UNIMPLEMENTED, /* 0x1d3 */ + UNIMPLEMENTED, /* 0x1d4 */ + UNIMPLEMENTED, /* 0x1d5 */ + UNIMPLEMENTED, /* 0x1d6 */ + UNIMPLEMENTED, /* 0x1d7 */ + UNIMPLEMENTED, /* 0x1d8 */ + UNIMPLEMENTED, /* 0x1d9 */ + UNIMPLEMENTED, /* 0x1da */ + UNIMPLEMENTED, /* 0x1db */ + UNIMPLEMENTED, /* 0x1dc */ + UNIMPLEMENTED, /* 0x1dd */ + UNIMPLEMENTED, /* 0x1de */ + UNIMPLEMENTED, /* 0x1df */ + UNIMPLEMENTED, /* 0x1e0 */ + UNIMPLEMENTED, /* 0x1e1 */ + UNIMPLEMENTED, /* 0x1e2 */ + UNIMPLEMENTED, /* 0x1e3 */ + UNIMPLEMENTED, /* 0x1e4 */ + UNIMPLEMENTED, /* 0x1e5 */ + UNIMPLEMENTED, /* 0x1e6 */ + UNIMPLEMENTED, /* 0x1e7 */ + UNIMPLEMENTED, /* 0x1e8 */ + UNIMPLEMENTED, /* 0x1e9 */ + UNIMPLEMENTED, /* 0x1ea */ + UNIMPLEMENTED, /* 0x1eb */ + UNIMPLEMENTED, /* 0x1ec */ + UNIMPLEMENTED, /* 0x1ed */ + UNIMPLEMENTED, /* 0x1ee */ + UNIMPLEMENTED, /* 0x1ef */ + FREG, /* 0x1f0 */ + FREG, /* 0x1f1 */ + FREG, /* 0x1f2 */ + FREG, /* 0x1f3 */ + FREG, /* 0x1f4 */ + FREG, /* 0x1f5 */ + FREG, /* 0x1f6 */ + FREG, /* 0x1f7 */ + FREG, /* 0x1f8 */ + FREG, /* 0x1f9 */ + FREG, /* 0x1fa */ + FREG, /* 0x1fb */ + FREG, /* 0x1fc */ + FREG, /* 0x1fd */ + FREG, /* 0x1fe */ + FREG, /* 0x1ff */ +}; +// clang-format on + +#endif // RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F882_H diff --git a/librz/arch/isa/pic/pic16f_memmaps/pic16f883_4.h b/librz/arch/isa/pic/pic16f_memmaps/pic16f883_4.h new file mode 100644 index 00000000000..97841336dd6 --- /dev/null +++ b/librz/arch/isa/pic/pic16f_memmaps/pic16f883_4.h @@ -0,0 +1,543 @@ +// SPDX-FileCopyrightText: 2023 Siddharth Mishra +// SPDX-License-Identifier: LGPL-3.0-only + +/** + * This file describes the memory map of PICF16883/4 device in PIC16F family. + * */ + +#ifndef RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F883_H +#define RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F883_H + +#include "regtypes.h" + +// clang-format off +PicMidrangeRegType pic16f883_reg_map[] = { + /* BANK 0 */ + INDF, /* 0x00 */ + TMR0, /* 0x01 */ + PCL, /* 0x02 */ + STATUS, /* 0x03 */ + FSR, /* 0x04 */ + PORTA, /* 0x05 */ + PORTB, /* 0x06 */ + PORTC, /* 0x07 */ + PORTD, /* 0x08 */ + PORTE, /* 0x09 */ + PCLATH, /* 0x0a */ + INTCON, /* 0x0b */ + PIR1, /* 0x0c */ + PIR2, /* 0x0d */ + TMR1L, /* 0x0e */ + TMR1H, /* 0x0f */ + T1CON, /* 0x10 */ + TMR2, /* 0x11 */ + T2CON, /* 0x12 */ + SSPBUF, /* 0x13 */ + SSPCON, /* 0x14 */ + CCPR1L, /* 0x15 */ + CCPR1H, /* 0x16 */ + CCP1CON, /* 0x17 */ + RCSTA, /* 0x18 */ + TXREG, /* 0x19 */ + RCREG, /* 0x1a */ + CCPR2L, /* 0x1b */ + CCPR2H, /* 0x1c */ + CCP2CON, /* 0x1d */ + ADRESH, /* 0x1e */ + ADCON0, /* 0x1f */ + FREG, /* 0x20 */ + FREG, /* 0x21 */ + FREG, /* 0x22 */ + FREG, /* 0x23 */ + FREG, /* 0x24 */ + FREG, /* 0x25 */ + FREG, /* 0x26 */ + FREG, /* 0x27 */ + FREG, /* 0x28 */ + FREG, /* 0x29 */ + FREG, /* 0x2a */ + FREG, /* 0x2b */ + FREG, /* 0x2c */ + FREG, /* 0x2d */ + FREG, /* 0x2e */ + FREG, /* 0x2f */ + FREG, /* 0x30 */ + FREG, /* 0x31 */ + FREG, /* 0x32 */ + FREG, /* 0x33 */ + FREG, /* 0x34 */ + FREG, /* 0x35 */ + FREG, /* 0x36 */ + FREG, /* 0x37 */ + FREG, /* 0x38 */ + FREG, /* 0x39 */ + FREG, /* 0x3a */ + FREG, /* 0x3b */ + FREG, /* 0x3c */ + FREG, /* 0x3d */ + FREG, /* 0x3e */ + FREG, /* 0x3f */ + FREG, /* 0x40 */ + FREG, /* 0x41 */ + FREG, /* 0x42 */ + FREG, /* 0x43 */ + FREG, /* 0x44 */ + FREG, /* 0x45 */ + FREG, /* 0x46 */ + FREG, /* 0x47 */ + FREG, /* 0x48 */ + FREG, /* 0x49 */ + FREG, /* 0x4a */ + FREG, /* 0x4b */ + FREG, /* 0x4c */ + FREG, /* 0x4d */ + FREG, /* 0x4e */ + FREG, /* 0x4f */ + FREG, /* 0x50 */ + FREG, /* 0x51 */ + FREG, /* 0x52 */ + FREG, /* 0x53 */ + FREG, /* 0x54 */ + FREG, /* 0x55 */ + FREG, /* 0x56 */ + FREG, /* 0x57 */ + FREG, /* 0x58 */ + FREG, /* 0x59 */ + FREG, /* 0x5a */ + FREG, /* 0x5b */ + FREG, /* 0x5c */ + FREG, /* 0x5d */ + FREG, /* 0x5e */ + FREG, /* 0x5f */ + FREG, /* 0x60 */ + FREG, /* 0x61 */ + FREG, /* 0x62 */ + FREG, /* 0x63 */ + FREG, /* 0x64 */ + FREG, /* 0x65 */ + FREG, /* 0x66 */ + FREG, /* 0x67 */ + FREG, /* 0x68 */ + FREG, /* 0x69 */ + FREG, /* 0x6a */ + FREG, /* 0x6b */ + FREG, /* 0x6c */ + FREG, /* 0x6d */ + FREG, /* 0x6e */ + FREG, /* 0x6f */ + FREG, /* 0x70 */ + FREG, /* 0x71 */ + FREG, /* 0x72 */ + FREG, /* 0x73 */ + FREG, /* 0x74 */ + FREG, /* 0x75 */ + FREG, /* 0x76 */ + FREG, /* 0x77 */ + FREG, /* 0x78 */ + FREG, /* 0x79 */ + FREG, /* 0x7a */ + FREG, /* 0x7b */ + FREG, /* 0x7c */ + FREG, /* 0x7d */ + FREG, /* 0x7e */ + FREG, /* 0x7f */ + + /* BANK1 */ + + INDF, /* 0x80 */ + OPTION_REG, /* 0x81 */ + PCL, /* 0x82 */ + STATUS, /* 0x83 */ + FSR, /* 0x84 */ + TRISA, /* 0x85 */ + TRISB, /* 0x86 */ + TRISC, /* 0x87 */ + TRISD, /* 0x88 */ + TRISE, /* 0x89 */ + PCLATH, /* 0x8a */ + INTCON, /* 0x8b */ + PIE1, /* 0x8c */ + PIE2, /* 0x8d */ + PCON, /* 0x8e */ + OSCCON, /* 0x8f */ + OSCTUNE, /* 0x90 */ + SSPCON2, /* 0x91 */ + PR2, /* 0x92 */ + SSPADD, /* 0x93 */ + SSPSTAT, /* 0x94 */ + WPUB, /* 0x95 */ + IOCB, /* 0x96 */ + VRCON, /* 0x97 */ + TXSTA, /* 0x98 */ + SPBRG, /* 0x99 */ + SPBRGH, /* 0x9a */ + PWM1CON, /* 0x9b */ + ECCPAS, /* 0x9c */ + PSTRCON, /* 0x9d */ + ADRESL, /* 0x9e */ + ADCON1, /* 0x9f */ + FREG, /* 0xa0 */ + FREG, /* 0xa1 */ + FREG, /* 0xa2 */ + FREG, /* 0xa3 */ + FREG, /* 0xa4 */ + FREG, /* 0xa5 */ + FREG, /* 0xa6 */ + FREG, /* 0xa7 */ + FREG, /* 0xa8 */ + FREG, /* 0xa9 */ + FREG, /* 0xaa */ + FREG, /* 0xab */ + FREG, /* 0xac */ + FREG, /* 0xad */ + FREG, /* 0xae */ + FREG, /* 0xaf */ + FREG, /* 0xb0 */ + FREG, /* 0xb1 */ + FREG, /* 0xb2 */ + FREG, /* 0xb3 */ + FREG, /* 0xb4 */ + FREG, /* 0xb5 */ + FREG, /* 0xb6 */ + FREG, /* 0xb7 */ + FREG, /* 0xb8 */ + FREG, /* 0xb9 */ + FREG, /* 0xba */ + FREG, /* 0xbb */ + FREG, /* 0xbc */ + FREG, /* 0xbd */ + FREG, /* 0xbe */ + FREG, /* 0xbf */ + FREG, /* 0xc0 */ + FREG, /* 0xc1 */ + FREG, /* 0xc2 */ + FREG, /* 0xc3 */ + FREG, /* 0xc4 */ + FREG, /* 0xc5 */ + FREG, /* 0xc6 */ + FREG, /* 0xc7 */ + FREG, /* 0xc8 */ + FREG, /* 0xc9 */ + FREG, /* 0xca */ + FREG, /* 0xcb */ + FREG, /* 0xcc */ + FREG, /* 0xcd */ + FREG, /* 0xce */ + FREG, /* 0xcf */ + FREG, /* 0xd0 */ + FREG, /* 0xd1 */ + FREG, /* 0xd2 */ + FREG, /* 0xd3 */ + FREG, /* 0xd4 */ + FREG, /* 0xd5 */ + FREG, /* 0xd6 */ + FREG, /* 0xd7 */ + FREG, /* 0xd8 */ + FREG, /* 0xd9 */ + FREG, /* 0xda */ + FREG, /* 0xdb */ + FREG, /* 0xdc */ + FREG, /* 0xdd */ + FREG, /* 0xde */ + FREG, /* 0xdf */ + FREG, /* 0xe0 */ + FREG, /* 0xe1 */ + FREG, /* 0xe2 */ + FREG, /* 0xe3 */ + FREG, /* 0xe4 */ + FREG, /* 0xe5 */ + FREG, /* 0xe6 */ + FREG, /* 0xe7 */ + FREG, /* 0xe8 */ + FREG, /* 0xe9 */ + FREG, /* 0xea */ + FREG, /* 0xeb */ + FREG, /* 0xec */ + FREG, /* 0xed */ + FREG, /* 0xee */ + FREG, /* 0xef */ + FREG, /* 0xf0 */ + FREG, /* 0xf1 */ + FREG, /* 0xf2 */ + FREG, /* 0xf3 */ + FREG, /* 0xf4 */ + FREG, /* 0xf5 */ + FREG, /* 0xf6 */ + FREG, /* 0xf7 */ + FREG, /* 0xf8 */ + FREG, /* 0xf9 */ + FREG, /* 0xfa */ + FREG, /* 0xfb */ + FREG, /* 0xfc */ + FREG, /* 0xfd */ + FREG, /* 0xfe */ + FREG, /* 0xff */ + + /* BANK 2 */ + + INDF, /* 0x100 */ + TMR0, /* 0x101 */ + PCL, /* 0x102 */ + STATUS, /* 0x103 */ + FSR, /* 0x104 */ + WDTCON, /* 0x105 */ + PORTB, /* 0x106 */ + CM1CON0, /* 0x107 */ + CM2CON0, /* 0x108 */ + CM2CON1, /* 0x109 */ + PCLATH, /* 0x10a */ + INTCON, /* 0x10b */ + EEDAT, /* 0x10c */ + EEADR, /* 0x10d */ + EEDATH, /* 0x10e */ + EEADRH, /* 0x10f */ + UNIMPLEMENTED, /* 0x110 */ + UNIMPLEMENTED, /* 0x111 */ + UNIMPLEMENTED, /* 0x112 */ + UNIMPLEMENTED, /* 0x113 */ + UNIMPLEMENTED, /* 0x114 */ + UNIMPLEMENTED, /* 0x115 */ + UNIMPLEMENTED, /* 0x116 */ + UNIMPLEMENTED, /* 0x117 */ + UNIMPLEMENTED, /* 0x118 */ + UNIMPLEMENTED, /* 0x119 */ + UNIMPLEMENTED, /* 0x11a */ + UNIMPLEMENTED, /* 0x11b */ + UNIMPLEMENTED, /* 0x11c */ + UNIMPLEMENTED, /* 0x11d */ + UNIMPLEMENTED, /* 0x11e */ + UNIMPLEMENTED, /* 0x11f */ + FREG, /* 0x120 */ + FREG, /* 0x121 */ + FREG, /* 0x122 */ + FREG, /* 0x123 */ + FREG, /* 0x124 */ + FREG, /* 0x125 */ + FREG, /* 0x126 */ + FREG, /* 0x127 */ + FREG, /* 0x128 */ + FREG, /* 0x129 */ + FREG, /* 0x12a */ + FREG, /* 0x12b */ + FREG, /* 0x12c */ + FREG, /* 0x12d */ + FREG, /* 0x12e */ + FREG, /* 0x12f */ + FREG, /* 0x130 */ + FREG, /* 0x131 */ + FREG, /* 0x132 */ + FREG, /* 0x133 */ + FREG, /* 0x134 */ + FREG, /* 0x135 */ + FREG, /* 0x136 */ + FREG, /* 0x137 */ + FREG, /* 0x138 */ + FREG, /* 0x139 */ + FREG, /* 0x13a */ + FREG, /* 0x13b */ + FREG, /* 0x13c */ + FREG, /* 0x13d */ + FREG, /* 0x13e */ + FREG, /* 0x13f */ + FREG, /* 0x140 */ + FREG, /* 0x141 */ + FREG, /* 0x142 */ + FREG, /* 0x143 */ + FREG, /* 0x144 */ + FREG, /* 0x145 */ + FREG, /* 0x146 */ + FREG, /* 0x147 */ + FREG, /* 0x148 */ + FREG, /* 0x149 */ + FREG, /* 0x14a */ + FREG, /* 0x14b */ + FREG, /* 0x14c */ + FREG, /* 0x14d */ + FREG, /* 0x14e */ + FREG, /* 0x14f */ + FREG, /* 0x150 */ + FREG, /* 0x151 */ + FREG, /* 0x152 */ + FREG, /* 0x153 */ + FREG, /* 0x154 */ + FREG, /* 0x155 */ + FREG, /* 0x156 */ + FREG, /* 0x157 */ + FREG, /* 0x158 */ + FREG, /* 0x159 */ + FREG, /* 0x15a */ + FREG, /* 0x15b */ + FREG, /* 0x15c */ + FREG, /* 0x15d */ + FREG, /* 0x15e */ + FREG, /* 0x15f */ + FREG, /* 0x160 */ + FREG, /* 0x161 */ + FREG, /* 0x162 */ + FREG, /* 0x163 */ + FREG, /* 0x164 */ + FREG, /* 0x165 */ + FREG, /* 0x166 */ + FREG, /* 0x167 */ + FREG, /* 0x168 */ + FREG, /* 0x169 */ + FREG, /* 0x16a */ + FREG, /* 0x16b */ + FREG, /* 0x16c */ + FREG, /* 0x16d */ + FREG, /* 0x16e */ + FREG, /* 0x16f */ + FREG, /* 0x170 */ + FREG, /* 0x171 */ + FREG, /* 0x172 */ + FREG, /* 0x173 */ + FREG, /* 0x174 */ + FREG, /* 0x175 */ + FREG, /* 0x176 */ + FREG, /* 0x177 */ + FREG, /* 0x178 */ + FREG, /* 0x179 */ + FREG, /* 0x17a */ + FREG, /* 0x17b */ + FREG, /* 0x17c */ + FREG, /* 0x17d */ + FREG, /* 0x17e */ + FREG, /* 0x17f */ + + /* BANK 3 */ + + INDF, /* 0x180 */ + OPTION_REG, /* 0x181 */ + PCL, /* 0x182 */ + STATUS, /* 0x183 */ + FSR, /* 0x184 */ + SRCON, /* 0x185 */ + TRISB, /* 0x186 */ + BAUDCTL, /* 0x187 */ + ANSEL, /* 0x188 */ + ANSELH, /* 0x189 */ + PCLATH, /* 0x18a */ + INTCON, /* 0x18b */ + EECON1, /* 0x18c */ + EECON2, /* 0x18d */ + _RESERVED, /* 0x18e */ + _RESERVED, /* 0x18f */ + UNIMPLEMENTED, /* 0x190 */ + UNIMPLEMENTED, /* 0x191 */ + UNIMPLEMENTED, /* 0x192 */ + UNIMPLEMENTED, /* 0x193 */ + UNIMPLEMENTED, /* 0x194 */ + UNIMPLEMENTED, /* 0x195 */ + UNIMPLEMENTED, /* 0x196 */ + UNIMPLEMENTED, /* 0x197 */ + UNIMPLEMENTED, /* 0x198 */ + UNIMPLEMENTED, /* 0x199 */ + UNIMPLEMENTED, /* 0x19a */ + UNIMPLEMENTED, /* 0x19b */ + UNIMPLEMENTED, /* 0x19c */ + UNIMPLEMENTED, /* 0x19d */ + UNIMPLEMENTED, /* 0x19e */ + UNIMPLEMENTED, /* 0x19f */ + UNIMPLEMENTED, /* 0x1a0 */ + UNIMPLEMENTED, /* 0x1a1 */ + UNIMPLEMENTED, /* 0x1a2 */ + UNIMPLEMENTED, /* 0x1a3 */ + UNIMPLEMENTED, /* 0x1a4 */ + UNIMPLEMENTED, /* 0x1a5 */ + UNIMPLEMENTED, /* 0x1a6 */ + UNIMPLEMENTED, /* 0x1a7 */ + UNIMPLEMENTED, /* 0x1a8 */ + UNIMPLEMENTED, /* 0x1a9 */ + UNIMPLEMENTED, /* 0x1aa */ + UNIMPLEMENTED, /* 0x1ab */ + UNIMPLEMENTED, /* 0x1ac */ + UNIMPLEMENTED, /* 0x1ad */ + UNIMPLEMENTED, /* 0x1ae */ + UNIMPLEMENTED, /* 0x1af */ + UNIMPLEMENTED, /* 0x1b0 */ + UNIMPLEMENTED, /* 0x1b1 */ + UNIMPLEMENTED, /* 0x1b2 */ + UNIMPLEMENTED, /* 0x1b3 */ + UNIMPLEMENTED, /* 0x1b4 */ + UNIMPLEMENTED, /* 0x1b5 */ + UNIMPLEMENTED, /* 0x1b6 */ + UNIMPLEMENTED, /* 0x1b7 */ + UNIMPLEMENTED, /* 0x1b8 */ + UNIMPLEMENTED, /* 0x1b9 */ + UNIMPLEMENTED, /* 0x1ba */ + UNIMPLEMENTED, /* 0x1bb */ + UNIMPLEMENTED, /* 0x1bc */ + UNIMPLEMENTED, /* 0x1bd */ + UNIMPLEMENTED, /* 0x1be */ + UNIMPLEMENTED, /* 0x1bf */ + UNIMPLEMENTED, /* 0x1c0 */ + UNIMPLEMENTED, /* 0x1c1 */ + UNIMPLEMENTED, /* 0x1c2 */ + UNIMPLEMENTED, /* 0x1c3 */ + UNIMPLEMENTED, /* 0x1c4 */ + UNIMPLEMENTED, /* 0x1c5 */ + UNIMPLEMENTED, /* 0x1c6 */ + UNIMPLEMENTED, /* 0x1c7 */ + UNIMPLEMENTED, /* 0x1c8 */ + UNIMPLEMENTED, /* 0x1c9 */ + UNIMPLEMENTED, /* 0x1ca */ + UNIMPLEMENTED, /* 0x1cb */ + UNIMPLEMENTED, /* 0x1cc */ + UNIMPLEMENTED, /* 0x1cd */ + UNIMPLEMENTED, /* 0x1ce */ + UNIMPLEMENTED, /* 0x1cf */ + UNIMPLEMENTED, /* 0x1d0 */ + UNIMPLEMENTED, /* 0x1d1 */ + UNIMPLEMENTED, /* 0x1d2 */ + UNIMPLEMENTED, /* 0x1d3 */ + UNIMPLEMENTED, /* 0x1d4 */ + UNIMPLEMENTED, /* 0x1d5 */ + UNIMPLEMENTED, /* 0x1d6 */ + UNIMPLEMENTED, /* 0x1d7 */ + UNIMPLEMENTED, /* 0x1d8 */ + UNIMPLEMENTED, /* 0x1d9 */ + UNIMPLEMENTED, /* 0x1da */ + UNIMPLEMENTED, /* 0x1db */ + UNIMPLEMENTED, /* 0x1dc */ + UNIMPLEMENTED, /* 0x1dd */ + UNIMPLEMENTED, /* 0x1de */ + UNIMPLEMENTED, /* 0x1df */ + UNIMPLEMENTED, /* 0x1e0 */ + UNIMPLEMENTED, /* 0x1e1 */ + UNIMPLEMENTED, /* 0x1e2 */ + UNIMPLEMENTED, /* 0x1e3 */ + UNIMPLEMENTED, /* 0x1e4 */ + UNIMPLEMENTED, /* 0x1e5 */ + UNIMPLEMENTED, /* 0x1e6 */ + UNIMPLEMENTED, /* 0x1e7 */ + UNIMPLEMENTED, /* 0x1e8 */ + UNIMPLEMENTED, /* 0x1e9 */ + UNIMPLEMENTED, /* 0x1ea */ + UNIMPLEMENTED, /* 0x1eb */ + UNIMPLEMENTED, /* 0x1ec */ + UNIMPLEMENTED, /* 0x1ed */ + UNIMPLEMENTED, /* 0x1ee */ + UNIMPLEMENTED, /* 0x1ef */ + FREG, /* 0x1f0 */ + FREG, /* 0x1f1 */ + FREG, /* 0x1f2 */ + FREG, /* 0x1f3 */ + FREG, /* 0x1f4 */ + FREG, /* 0x1f5 */ + FREG, /* 0x1f6 */ + FREG, /* 0x1f7 */ + FREG, /* 0x1f8 */ + FREG, /* 0x1f9 */ + FREG, /* 0x1fa */ + FREG, /* 0x1fb */ + FREG, /* 0x1fc */ + FREG, /* 0x1fd */ + FREG, /* 0x1fe */ + FREG, /* 0x1ff */ +}; +// clang-format on + +// memory map for PIC16F883 and PIC16F884 are same +PicMidrangeRegType *pic16f884_reg_map = pic16f883_reg_map; + +#endif // RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F882_H diff --git a/librz/arch/isa/pic/pic16f_memmaps/pic16f886_7.h b/librz/arch/isa/pic/pic16f_memmaps/pic16f886_7.h new file mode 100644 index 00000000000..e9c77efce5f --- /dev/null +++ b/librz/arch/isa/pic/pic16f_memmaps/pic16f886_7.h @@ -0,0 +1,543 @@ +// SPDX-FileCopyrightText: 2023 Siddharth Mishra +// SPDX-License-Identifier: LGPL-3.0-only + +/** + * This file describes the memory map of PICF16886/7 device in PIC16F family. + * */ + +#ifndef RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F886_H +#define RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F886_H + +#include "regtypes.h" + +// clang-format off +PicMidrangeRegType pic16f886_reg_map[] = { + /* BANK 0 */ + INDF, /* 0x00 */ + TMR0, /* 0x01 */ + PCL, /* 0x02 */ + STATUS, /* 0x03 */ + FSR, /* 0x04 */ + PORTA, /* 0x05 */ + PORTB, /* 0x06 */ + PORTC, /* 0x07 */ + PORTD, /* 0x08 */ + PORTE, /* 0x09 */ + PCLATH, /* 0x0a */ + INTCON, /* 0x0b */ + PIR1, /* 0x0c */ + PIR2, /* 0x0d */ + TMR1L, /* 0x0e */ + TMR1H, /* 0x0f */ + T1CON, /* 0x10 */ + TMR2, /* 0x11 */ + T2CON, /* 0x12 */ + SSPBUF, /* 0x13 */ + SSPCON, /* 0x14 */ + CCPR1L, /* 0x15 */ + CCPR1H, /* 0x16 */ + CCP1CON, /* 0x17 */ + RCSTA, /* 0x18 */ + TXREG, /* 0x19 */ + RCREG, /* 0x1a */ + CCPR2L, /* 0x1b */ + CCPR2H, /* 0x1c */ + CCP2CON, /* 0x1d */ + ADRESH, /* 0x1e */ + ADCON0, /* 0x1f */ + FREG, /* 0x20 */ + FREG, /* 0x21 */ + FREG, /* 0x22 */ + FREG, /* 0x23 */ + FREG, /* 0x24 */ + FREG, /* 0x25 */ + FREG, /* 0x26 */ + FREG, /* 0x27 */ + FREG, /* 0x28 */ + FREG, /* 0x29 */ + FREG, /* 0x2a */ + FREG, /* 0x2b */ + FREG, /* 0x2c */ + FREG, /* 0x2d */ + FREG, /* 0x2e */ + FREG, /* 0x2f */ + FREG, /* 0x30 */ + FREG, /* 0x31 */ + FREG, /* 0x32 */ + FREG, /* 0x33 */ + FREG, /* 0x34 */ + FREG, /* 0x35 */ + FREG, /* 0x36 */ + FREG, /* 0x37 */ + FREG, /* 0x38 */ + FREG, /* 0x39 */ + FREG, /* 0x3a */ + FREG, /* 0x3b */ + FREG, /* 0x3c */ + FREG, /* 0x3d */ + FREG, /* 0x3e */ + FREG, /* 0x3f */ + FREG, /* 0x40 */ + FREG, /* 0x41 */ + FREG, /* 0x42 */ + FREG, /* 0x43 */ + FREG, /* 0x44 */ + FREG, /* 0x45 */ + FREG, /* 0x46 */ + FREG, /* 0x47 */ + FREG, /* 0x48 */ + FREG, /* 0x49 */ + FREG, /* 0x4a */ + FREG, /* 0x4b */ + FREG, /* 0x4c */ + FREG, /* 0x4d */ + FREG, /* 0x4e */ + FREG, /* 0x4f */ + FREG, /* 0x50 */ + FREG, /* 0x51 */ + FREG, /* 0x52 */ + FREG, /* 0x53 */ + FREG, /* 0x54 */ + FREG, /* 0x55 */ + FREG, /* 0x56 */ + FREG, /* 0x57 */ + FREG, /* 0x58 */ + FREG, /* 0x59 */ + FREG, /* 0x5a */ + FREG, /* 0x5b */ + FREG, /* 0x5c */ + FREG, /* 0x5d */ + FREG, /* 0x5e */ + FREG, /* 0x5f */ + FREG, /* 0x60 */ + FREG, /* 0x61 */ + FREG, /* 0x62 */ + FREG, /* 0x63 */ + FREG, /* 0x64 */ + FREG, /* 0x65 */ + FREG, /* 0x66 */ + FREG, /* 0x67 */ + FREG, /* 0x68 */ + FREG, /* 0x69 */ + FREG, /* 0x6a */ + FREG, /* 0x6b */ + FREG, /* 0x6c */ + FREG, /* 0x6d */ + FREG, /* 0x6e */ + FREG, /* 0x6f */ + FREG, /* 0x70 */ + FREG, /* 0x71 */ + FREG, /* 0x72 */ + FREG, /* 0x73 */ + FREG, /* 0x74 */ + FREG, /* 0x75 */ + FREG, /* 0x76 */ + FREG, /* 0x77 */ + FREG, /* 0x78 */ + FREG, /* 0x79 */ + FREG, /* 0x7a */ + FREG, /* 0x7b */ + FREG, /* 0x7c */ + FREG, /* 0x7d */ + FREG, /* 0x7e */ + FREG, /* 0x7f */ + + /* BANK1 */ + + INDF, /* 0x80 */ + OPTION_REG, /* 0x81 */ + PCL, /* 0x82 */ + STATUS, /* 0x83 */ + FSR, /* 0x84 */ + TRISA, /* 0x85 */ + TRISB, /* 0x86 */ + TRISC, /* 0x87 */ + TRISD, /* 0x88 */ + TRISE, /* 0x89 */ + PCLATH, /* 0x8a */ + INTCON, /* 0x8b */ + PIE1, /* 0x8c */ + PIE2, /* 0x8d */ + PCON, /* 0x8e */ + OSCCON, /* 0x8f */ + OSCTUNE, /* 0x90 */ + SSPCON2, /* 0x91 */ + PR2, /* 0x92 */ + SSPADD, /* 0x93 */ + SSPSTAT, /* 0x94 */ + WPUB, /* 0x95 */ + IOCB, /* 0x96 */ + VRCON, /* 0x97 */ + TXSTA, /* 0x98 */ + SPBRG, /* 0x99 */ + SPBRGH, /* 0x9a */ + PWM1CON, /* 0x9b */ + ECCPAS, /* 0x9c */ + PSTRCON, /* 0x9d */ + ADRESL, /* 0x9e */ + ADCON1, /* 0x9f */ + FREG, /* 0xa0 */ + FREG, /* 0xa1 */ + FREG, /* 0xa2 */ + FREG, /* 0xa3 */ + FREG, /* 0xa4 */ + FREG, /* 0xa5 */ + FREG, /* 0xa6 */ + FREG, /* 0xa7 */ + FREG, /* 0xa8 */ + FREG, /* 0xa9 */ + FREG, /* 0xaa */ + FREG, /* 0xab */ + FREG, /* 0xac */ + FREG, /* 0xad */ + FREG, /* 0xae */ + FREG, /* 0xaf */ + FREG, /* 0xb0 */ + FREG, /* 0xb1 */ + FREG, /* 0xb2 */ + FREG, /* 0xb3 */ + FREG, /* 0xb4 */ + FREG, /* 0xb5 */ + FREG, /* 0xb6 */ + FREG, /* 0xb7 */ + FREG, /* 0xb8 */ + FREG, /* 0xb9 */ + FREG, /* 0xba */ + FREG, /* 0xbb */ + FREG, /* 0xbc */ + FREG, /* 0xbd */ + FREG, /* 0xbe */ + FREG, /* 0xbf */ + FREG, /* 0xc0 */ + FREG, /* 0xc1 */ + FREG, /* 0xc2 */ + FREG, /* 0xc3 */ + FREG, /* 0xc4 */ + FREG, /* 0xc5 */ + FREG, /* 0xc6 */ + FREG, /* 0xc7 */ + FREG, /* 0xc8 */ + FREG, /* 0xc9 */ + FREG, /* 0xca */ + FREG, /* 0xcb */ + FREG, /* 0xcc */ + FREG, /* 0xcd */ + FREG, /* 0xce */ + FREG, /* 0xcf */ + FREG, /* 0xd0 */ + FREG, /* 0xd1 */ + FREG, /* 0xd2 */ + FREG, /* 0xd3 */ + FREG, /* 0xd4 */ + FREG, /* 0xd5 */ + FREG, /* 0xd6 */ + FREG, /* 0xd7 */ + FREG, /* 0xd8 */ + FREG, /* 0xd9 */ + FREG, /* 0xda */ + FREG, /* 0xdb */ + FREG, /* 0xdc */ + FREG, /* 0xdd */ + FREG, /* 0xde */ + FREG, /* 0xdf */ + FREG, /* 0xe0 */ + FREG, /* 0xe1 */ + FREG, /* 0xe2 */ + FREG, /* 0xe3 */ + FREG, /* 0xe4 */ + FREG, /* 0xe5 */ + FREG, /* 0xe6 */ + FREG, /* 0xe7 */ + FREG, /* 0xe8 */ + FREG, /* 0xe9 */ + FREG, /* 0xea */ + FREG, /* 0xeb */ + FREG, /* 0xec */ + FREG, /* 0xed */ + FREG, /* 0xee */ + FREG, /* 0xef */ + FREG, /* 0xf0 */ + FREG, /* 0xf1 */ + FREG, /* 0xf2 */ + FREG, /* 0xf3 */ + FREG, /* 0xf4 */ + FREG, /* 0xf5 */ + FREG, /* 0xf6 */ + FREG, /* 0xf7 */ + FREG, /* 0xf8 */ + FREG, /* 0xf9 */ + FREG, /* 0xfa */ + FREG, /* 0xfb */ + FREG, /* 0xfc */ + FREG, /* 0xfd */ + FREG, /* 0xfe */ + FREG, /* 0xff */ + + /* BANK 2 */ + + INDF, /* 0x100 */ + TMR0, /* 0x101 */ + PCL, /* 0x102 */ + STATUS, /* 0x103 */ + FSR, /* 0x104 */ + WDTCON, /* 0x105 */ + PORTB, /* 0x106 */ + CM1CON0, /* 0x107 */ + CM2CON0, /* 0x108 */ + CM2CON1, /* 0x109 */ + PCLATH, /* 0x10a */ + INTCON, /* 0x10b */ + EEDAT, /* 0x10c */ + EEADR, /* 0x10d */ + EEDATH, /* 0x10e */ + EEADRH, /* 0x10f */ + FREG, /* 0x110 */ + FREG, /* 0x111 */ + FREG, /* 0x112 */ + FREG, /* 0x113 */ + FREG, /* 0x114 */ + FREG, /* 0x115 */ + FREG, /* 0x116 */ + FREG, /* 0x117 */ + FREG, /* 0x118 */ + FREG, /* 0x119 */ + FREG, /* 0x11a */ + FREG, /* 0x11b */ + FREG, /* 0x11c */ + FREG, /* 0x11d */ + FREG, /* 0x11e */ + FREG, /* 0x11f */ + FREG, /* 0x120 */ + FREG, /* 0x121 */ + FREG, /* 0x122 */ + FREG, /* 0x123 */ + FREG, /* 0x124 */ + FREG, /* 0x125 */ + FREG, /* 0x126 */ + FREG, /* 0x127 */ + FREG, /* 0x128 */ + FREG, /* 0x129 */ + FREG, /* 0x12a */ + FREG, /* 0x12b */ + FREG, /* 0x12c */ + FREG, /* 0x12d */ + FREG, /* 0x12e */ + FREG, /* 0x12f */ + FREG, /* 0x130 */ + FREG, /* 0x131 */ + FREG, /* 0x132 */ + FREG, /* 0x133 */ + FREG, /* 0x134 */ + FREG, /* 0x135 */ + FREG, /* 0x136 */ + FREG, /* 0x137 */ + FREG, /* 0x138 */ + FREG, /* 0x139 */ + FREG, /* 0x13a */ + FREG, /* 0x13b */ + FREG, /* 0x13c */ + FREG, /* 0x13d */ + FREG, /* 0x13e */ + FREG, /* 0x13f */ + FREG, /* 0x140 */ + FREG, /* 0x141 */ + FREG, /* 0x142 */ + FREG, /* 0x143 */ + FREG, /* 0x144 */ + FREG, /* 0x145 */ + FREG, /* 0x146 */ + FREG, /* 0x147 */ + FREG, /* 0x148 */ + FREG, /* 0x149 */ + FREG, /* 0x14a */ + FREG, /* 0x14b */ + FREG, /* 0x14c */ + FREG, /* 0x14d */ + FREG, /* 0x14e */ + FREG, /* 0x14f */ + FREG, /* 0x150 */ + FREG, /* 0x151 */ + FREG, /* 0x152 */ + FREG, /* 0x153 */ + FREG, /* 0x154 */ + FREG, /* 0x155 */ + FREG, /* 0x156 */ + FREG, /* 0x157 */ + FREG, /* 0x158 */ + FREG, /* 0x159 */ + FREG, /* 0x15a */ + FREG, /* 0x15b */ + FREG, /* 0x15c */ + FREG, /* 0x15d */ + FREG, /* 0x15e */ + FREG, /* 0x15f */ + FREG, /* 0x160 */ + FREG, /* 0x161 */ + FREG, /* 0x162 */ + FREG, /* 0x163 */ + FREG, /* 0x164 */ + FREG, /* 0x165 */ + FREG, /* 0x166 */ + FREG, /* 0x167 */ + FREG, /* 0x168 */ + FREG, /* 0x169 */ + FREG, /* 0x16a */ + FREG, /* 0x16b */ + FREG, /* 0x16c */ + FREG, /* 0x16d */ + FREG, /* 0x16e */ + FREG, /* 0x16f */ + FREG, /* 0x170 */ + FREG, /* 0x171 */ + FREG, /* 0x172 */ + FREG, /* 0x173 */ + FREG, /* 0x174 */ + FREG, /* 0x175 */ + FREG, /* 0x176 */ + FREG, /* 0x177 */ + FREG, /* 0x178 */ + FREG, /* 0x179 */ + FREG, /* 0x17a */ + FREG, /* 0x17b */ + FREG, /* 0x17c */ + FREG, /* 0x17d */ + FREG, /* 0x17e */ + FREG, /* 0x17f */ + + /* BANK 3 */ + + INDF, /* 0x180 */ + OPTION_REG, /* 0x181 */ + PCL, /* 0x182 */ + STATUS, /* 0x183 */ + FSR, /* 0x184 */ + SRCON, /* 0x185 */ + TRISB, /* 0x186 */ + BAUDCTL, /* 0x187 */ + ANSEL, /* 0x188 */ + ANSELH, /* 0x189 */ + PCLATH, /* 0x18a */ + INTCON, /* 0x18b */ + EECON1, /* 0x18c */ + EECON2, /* 0x18d */ + _RESERVED, /* 0x18e */ + _RESERVED, /* 0x18f */ + FREG, /* 0x190 */ + FREG, /* 0x191 */ + FREG, /* 0x192 */ + FREG, /* 0x193 */ + FREG, /* 0x194 */ + FREG, /* 0x195 */ + FREG, /* 0x196 */ + FREG, /* 0x197 */ + FREG, /* 0x198 */ + FREG, /* 0x199 */ + FREG, /* 0x19a */ + FREG, /* 0x19b */ + FREG, /* 0x19c */ + FREG, /* 0x19d */ + FREG, /* 0x19e */ + FREG, /* 0x19f */ + FREG, /* 0x1a0 */ + FREG, /* 0x1a1 */ + FREG, /* 0x1a2 */ + FREG, /* 0x1a3 */ + FREG, /* 0x1a4 */ + FREG, /* 0x1a5 */ + FREG, /* 0x1a6 */ + FREG, /* 0x1a7 */ + FREG, /* 0x1a8 */ + FREG, /* 0x1a9 */ + FREG, /* 0x1aa */ + FREG, /* 0x1ab */ + FREG, /* 0x1ac */ + FREG, /* 0x1ad */ + FREG, /* 0x1ae */ + FREG, /* 0x1af */ + FREG, /* 0x1b0 */ + FREG, /* 0x1b1 */ + FREG, /* 0x1b2 */ + FREG, /* 0x1b3 */ + FREG, /* 0x1b4 */ + FREG, /* 0x1b5 */ + FREG, /* 0x1b6 */ + FREG, /* 0x1b7 */ + FREG, /* 0x1b8 */ + FREG, /* 0x1b9 */ + FREG, /* 0x1ba */ + FREG, /* 0x1bb */ + FREG, /* 0x1bc */ + FREG, /* 0x1bd */ + FREG, /* 0x1be */ + FREG, /* 0x1bf */ + FREG, /* 0x1c0 */ + FREG, /* 0x1c1 */ + FREG, /* 0x1c2 */ + FREG, /* 0x1c3 */ + FREG, /* 0x1c4 */ + FREG, /* 0x1c5 */ + FREG, /* 0x1c6 */ + FREG, /* 0x1c7 */ + FREG, /* 0x1c8 */ + FREG, /* 0x1c9 */ + FREG, /* 0x1ca */ + FREG, /* 0x1cb */ + FREG, /* 0x1cc */ + FREG, /* 0x1cd */ + FREG, /* 0x1ce */ + FREG, /* 0x1cf */ + FREG, /* 0x1d0 */ + FREG, /* 0x1d1 */ + FREG, /* 0x1d2 */ + FREG, /* 0x1d3 */ + FREG, /* 0x1d4 */ + FREG, /* 0x1d5 */ + FREG, /* 0x1d6 */ + FREG, /* 0x1d7 */ + FREG, /* 0x1d8 */ + FREG, /* 0x1d9 */ + FREG, /* 0x1da */ + FREG, /* 0x1db */ + FREG, /* 0x1dc */ + FREG, /* 0x1dd */ + FREG, /* 0x1de */ + FREG, /* 0x1df */ + FREG, /* 0x1e0 */ + FREG, /* 0x1e1 */ + FREG, /* 0x1e2 */ + FREG, /* 0x1e3 */ + FREG, /* 0x1e4 */ + FREG, /* 0x1e5 */ + FREG, /* 0x1e6 */ + FREG, /* 0x1e7 */ + FREG, /* 0x1e8 */ + FREG, /* 0x1e9 */ + FREG, /* 0x1ea */ + FREG, /* 0x1eb */ + FREG, /* 0x1ec */ + FREG, /* 0x1ed */ + FREG, /* 0x1ee */ + FREG, /* 0x1ef */ + FREG, /* 0x1f0 */ + FREG, /* 0x1f1 */ + FREG, /* 0x1f2 */ + FREG, /* 0x1f3 */ + FREG, /* 0x1f4 */ + FREG, /* 0x1f5 */ + FREG, /* 0x1f6 */ + FREG, /* 0x1f7 */ + FREG, /* 0x1f8 */ + FREG, /* 0x1f9 */ + FREG, /* 0x1fa */ + FREG, /* 0x1fb */ + FREG, /* 0x1fc */ + FREG, /* 0x1fd */ + FREG, /* 0x1fe */ + FREG, /* 0x1ff */ +}; +// clang-format on + +// memory map for PIC16F883 and PIC16F884 are same +PicMidrangeRegType *pic16f887_reg_map = pic16f886_reg_map; + +#endif // RZ_PIC_MIDRANGE_PIC_MEMMAP_PIC16F886_H diff --git a/librz/arch/isa/pic/pic16f_memmaps/regtypes.h b/librz/arch/isa/pic/pic16f_memmaps/regtypes.h new file mode 100644 index 00000000000..adde505f9dc --- /dev/null +++ b/librz/arch/isa/pic/pic16f_memmaps/regtypes.h @@ -0,0 +1,203 @@ +// SPDX-FileCopyrightText: 2023 Siddharth Mishra +// SPDX-License-Identifier: LGPL-3.0-only + +/** + * Defines the various reigster types supported by the PIC16F family + * and a lookup table to map from these register types to their string names. + * */ + +#ifndef RZ_PIC_MIDRANGE_PIC_REGTYPES_H +#define RZ_PIC_MIDRANGE_PIC_REGTYPES_H + +// clang-format off + +/** + * Instead of storing strings in file register map, + * it's better to store enums in order to save memory. + * */ +typedef enum pic_midrange_reg_type_t { + INDF, + TMR0, + PCL, /* lower byte of PC register */ + STATUS, /* status register */ + FSR, + PORTA, + PORTB, + PORTC, + PORTD, + PORTE, + PORTF, + PORTG, + PCLATH, /* PCLATH is used to control PCH (higher part of PC reg)*/ + INTCON, + PIR1, + PIR2, + TMR1L, + TMR1H, + T1CON, + TMR2, + T2CON, + SSPBUF, + SSPCON, + SSPCON2, + CCPR1L, + CCPR1H, + CCP1CON, + RCSTA, + TXREG, + RCREG, + CCPR2L, + CCPR2H, + CCP2CON, + ADRESH, + ADRESL, + ADCON0, + + ADCON, + OPTION_REG, + TRISA, + TRISB, + TRISC, + TRISD, + TRISE, + TRISF, + TRISG, + PIE1, + PIE2, + PCON, + OSCCON, + OSCCAL, + PR2, + SSPADD, + SSPSTAT, + TXSTA, + SPBRG, + SPBRGH, + ADDCON1, + + OSCTUNE, + WPUB, + IOCB, + VRCON, + PWM1CON, + ECCPAS, + PSTRCON, + ADCON1, + WDTCON, + CM1CON0, + CM2CON0, + CM2CON1, + EEDAT, + EEADR, + EEDATH, + EEADRH, + SRCON, + BAUDCTL, + ANSEL, + ANSELH, + EECON1, + EECON2, + _RESERVED, + FREG, /* normal indexed file register */ + UNIMPLEMENTED, /* unimplemented registers are read as 0 */ + INVALID /* can be used when a function fails and want to return an invalid value */ +} PicMidrangeRegType; + +/** + * Map from reg enums to reg names + * */ +const char* pic_midrange_regnames[] = { + [INDF] = "indf", + [TMR0] = "tmr0", + [PCL] = "pcl", + [STATUS] = "status", + [FSR] = "fsr", + [PORTA] = "porta", + [PORTB] = "portb", + [PORTC] = "portc", + [PORTD] = "portd", + [PORTE] = "porte", + [PORTF] = "portf", + [PORTG] = "portg", + [PCLATH] = "pclath", + [INTCON] = "intcon", + [PIR1] = "pir1", + [PIR2] = "pir2", + [TMR1L] = "tmr1l", + [TMR1H] = "tmr1h", + [T1CON] = "t1con", + [TMR2] = "tmr2", + [T2CON] = "t2con", + [SSPBUF] = "sspbuf", + [SSPCON] = "sspcon", + [SSPCON2] = "sspcon2", + [CCPR1L] = "ccpr1l", + [CCPR1H] = "ccpr1h", + [CCP1CON] = "ccp1con", + [RCSTA] = "rcsta", + [TXREG] = "txreg", + [RCREG] = "rcreg", + [CCPR2L] = "ccpr2l", + [CCPR2H] = "ccpr2h", + [CCP2CON] = "ccp2con", + [ADRESH] = "adresh", + [ADRESL] = "adresl", + [ADCON0] = "adcon0", + [ADCON] = "adcon", + [OPTION_REG] = "option_reg", + [TRISA] = "trisa", + [TRISB] = "trisb", + [TRISC] = "trisc", + [TRISD] = "trisd", + [TRISE] = "trise", + [TRISF] = "trisf", + [TRISG] = "trisg", + [PIE1] = "pie1", + [PIE2] = "pie2", + [PCON] = "pcon", + [OSCCON] = "osccon", + [OSCCAL] = "osccal", + [PR2] = "pr2", + [SSPADD] = "sspadd", + [SSPSTAT] = "sspstat", + [TXSTA] = "txsta", + [SPBRG] = "spbrg", + [SPBRGH] = "spbrgh", + [ADDCON1] = "addcon1", + [OSCTUNE] = "osctune", + [WPUB] = "wpub", + [IOCB] = "iocb", + [VRCON] = "vrcon", + [PWM1CON] = "pwm1con", + [ECCPAS] = "eccpas", + [PSTRCON] = "pstrcon", + [ADCON1] = "adcon1", + [WDTCON] = "wdtcon", + [CM1CON0] = "cm1con0", + [CM2CON0] = "cm2con0", + [CM2CON1] = "cm2con1", + [EEDAT] = "eedat", + [EEADR] = "eeadr", + [EEDATH] = "eedath", + [EEADRH] = "eeadrh", + [SRCON] = "srcon", + [BAUDCTL] = "baudctl", + [ANSEL] = "ansel", + [ANSELH] = "anselh", + [EECON1] = "eecon1", + [EECON2] = "eecon2", + [_RESERVED] = "reserved", + [FREG] = "freg", + [UNIMPLEMENTED] = "unimplemented", +}; +// clang-format on + +static inline const char *pic_midrange_regname(ut32 reg) { + if (reg >= RZ_ARRAY_SIZE(pic_midrange_regnames)) { + rz_warn_if_reached(); + return NULL; + } + return pic_midrange_regnames[reg]; +} + +#endif // RZ_PIC_MIDRANGE_PIC_REGTYPES_H diff --git a/librz/arch/isa/pic/pic18_analysis.inc b/librz/arch/isa/pic/pic18_analysis.inc new file mode 100644 index 00000000000..5b5cadbce7d --- /dev/null +++ b/librz/arch/isa/pic/pic18_analysis.inc @@ -0,0 +1,361 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-FileCopyrightText: 2015-2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +#include "pic_pic18.h" +#include "pic18_esil.inc" + +typedef struct { + const Pic18Op *op; + const HtSU *mm; +} Pic18ILContext; + +#include "pic18_il.inc" + +static void pic18_cond_branch(RzAnalysisOp *aop, ut64 addr, const ut8 *buf) { + aop->type = RZ_ANALYSIS_OP_TYPE_CJMP; + aop->jump = addr + 2 + 2 * (*(ut16 *)buf & 0xff); + aop->fail = addr + aop->size; + aop->cycles = 2; +} + +static int analysis_pic18_op( + RzAnalysis *analysis, RzAnalysisOp *aop, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask) { + + aop->size = 2; + Pic18Op op = { 0 }; + if (!pic18_disasm_op(&op, addr, buf, len)) { + goto err; + } + aop->size = op.size; + switch (op.code) { + case PIC18_OPCODE_CALL: + case PIC18_OPCODE_RCALL: + aop->type = RZ_ANALYSIS_OP_TYPE_CALL; + break; + case PIC18_OPCODE_BRA: // bra + aop->type = RZ_ANALYSIS_OP_TYPE_JMP; + aop->cycles = 2; + aop->jump = addr + 2 + 2 * (*(ut16 *)buf & 0x7ff); + break; + case PIC18_OPCODE_MOVFF: // movff + aop->type = RZ_ANALYSIS_OP_TYPE_MOV; + break; + case PIC18_OPCODE_BTFSC: // btfsc + case PIC18_OPCODE_BTFSS: // btfss + aop->type = RZ_ANALYSIS_OP_TYPE_CJMP; + break; + case PIC18_OPCODE_BCF: // bcf + case PIC18_OPCODE_BSF: // bsf + case PIC18_OPCODE_BTG: // btg + aop->type = RZ_ANALYSIS_OP_TYPE_UNK; + break; + case PIC18_OPCODE_BZ: // bz + pic18_cond_branch(aop, addr, buf); + break; + case PIC18_OPCODE_BNZ: // bnz + pic18_cond_branch(aop, addr, buf); + break; + case PIC18_OPCODE_BNC: // bnc + pic18_cond_branch(aop, addr, buf); + break; + case PIC18_OPCODE_BOV: // bov + pic18_cond_branch(aop, addr, buf); + break; + case PIC18_OPCODE_BNOV: // bnov + pic18_cond_branch(aop, addr, buf); + break; + case PIC18_OPCODE_BN: // bn + pic18_cond_branch(aop, addr, buf); + break; + case PIC18_OPCODE_BNN: // bnn + pic18_cond_branch(aop, addr, buf); + break; + case PIC18_OPCODE_BC: // bc + pic18_cond_branch(aop, addr, buf); + break; + case PIC18_OPCODE_GOTO: // goto + aop->cycles = 2; + aop->jump = op.k; + aop->type = RZ_ANALYSIS_OP_TYPE_JMP; + break; + case PIC18_OPCODE_ADDLW: // addlw + aop->type = RZ_ANALYSIS_OP_TYPE_ADD; + aop->cycles = 1; + break; + case PIC18_OPCODE_MOVLW: // movlw + aop->type = RZ_ANALYSIS_OP_TYPE_LOAD; + aop->cycles = 1; + break; + case PIC18_OPCODE_MULLW: // mullw + aop->type = RZ_ANALYSIS_OP_TYPE_MUL; + aop->cycles = 1; + break; + case PIC18_OPCODE_RETLW: // retlw + aop->type = RZ_ANALYSIS_OP_TYPE_RET; + aop->cycles = 2; + break; + case PIC18_OPCODE_ANDLW: // andlw + aop->type = RZ_ANALYSIS_OP_TYPE_AND; + aop->cycles = 1; + break; + case PIC18_OPCODE_XORLW: // xorlw + aop->type = RZ_ANALYSIS_OP_TYPE_XOR; + aop->cycles = 1; + break; + case PIC18_OPCODE_IORLW: // iorlw + aop->type = RZ_ANALYSIS_OP_TYPE_OR; + aop->cycles = 1; + break; + case PIC18_OPCODE_SUBLW: // sublw + aop->type = RZ_ANALYSIS_OP_TYPE_SUB; + aop->cycles = 1; + break; + case PIC18_OPCODE_LFSR: // lfsr + aop->type = RZ_ANALYSIS_OP_TYPE_LOAD; + break; + case PIC18_OPCODE_SUBWF: // subwf + case PIC18_OPCODE_SUBFWB: // subwfb + case PIC18_OPCODE_SUBWFB: // subfwb + case PIC18_OPCODE_DCFSNZ: // dcfsnz + case PIC18_OPCODE_DECFSZ: // decfsz + case PIC18_OPCODE_DECF: // decf + aop->type = RZ_ANALYSIS_OP_TYPE_SUB; + break; + case PIC18_OPCODE_MOVF: // movf + aop->type = RZ_ANALYSIS_OP_TYPE_MOV; + break; + case PIC18_OPCODE_INFSNZ: // infsnz + case PIC18_OPCODE_INCFSZ: // incfsz + case PIC18_OPCODE_INCF: // incf + case PIC18_OPCODE_ADDWFC: // addwfc + aop->type = RZ_ANALYSIS_OP_TYPE_ADD; + break; + case PIC18_OPCODE_ADDWF: // addwf + aop->cycles = 1; + aop->type = RZ_ANALYSIS_OP_TYPE_ADD; + break; + case PIC18_OPCODE_RLNCF: // rlncf + case PIC18_OPCODE_RLCF: // rlcf + aop->type = RZ_ANALYSIS_OP_TYPE_ROL; + break; + case PIC18_OPCODE_RRNCF: // rrncf + case PIC18_OPCODE_RRCF: // rrcf + aop->type = RZ_ANALYSIS_OP_TYPE_ROR; + break; + case PIC18_OPCODE_SWAPF: // swapf + aop->type = RZ_ANALYSIS_OP_TYPE_UNK; + break; + case PIC18_OPCODE_COMF: // comf + aop->type = RZ_ANALYSIS_OP_TYPE_CPL; + break; + case PIC18_OPCODE_XORWF: // xorwf + aop->type = RZ_ANALYSIS_OP_TYPE_XOR; + break; + case PIC18_OPCODE_ANDWF: // andwf + aop->type = RZ_ANALYSIS_OP_TYPE_AND; + break; + case PIC18_OPCODE_IORWF: // iorwf + aop->type = RZ_ANALYSIS_OP_TYPE_OR; + break; + case PIC18_OPCODE_MOVWF: // movwf + aop->type = RZ_ANALYSIS_OP_TYPE_STORE; + break; + case PIC18_OPCODE_NEGF: // negf + case PIC18_OPCODE_CLRF: // clrf + case PIC18_OPCODE_SETF: // setf + aop->type = RZ_ANALYSIS_OP_TYPE_UNK; + break; + case PIC18_OPCODE_TSTFSZ: // tstfsz + aop->type = RZ_ANALYSIS_OP_TYPE_CJMP; + break; + case PIC18_OPCODE_CPFSGT: // cpfsgt + case PIC18_OPCODE_CPFSEQ: // cpfseq + case PIC18_OPCODE_CPFSLT: // cpfslt + aop->type = RZ_ANALYSIS_OP_TYPE_CMP; + break; + case PIC18_OPCODE_MULWF: // mulwf + aop->type = RZ_ANALYSIS_OP_TYPE_MUL; + break; + case PIC18_OPCODE_MOVLB: // movlb + aop->type = RZ_ANALYSIS_OP_TYPE_LOAD; + aop->cycles = 1; + break; + case PIC18_OPCODE_RESET: // reset + case PIC18_OPCODE_DAW: // daw + // case CLWDT // clwdt + case PIC18_OPCODE_SLEEP: // sleep + aop->type = RZ_ANALYSIS_OP_TYPE_UNK; + break; + case PIC18_OPCODE_RETURN: // return + aop->type = RZ_ANALYSIS_OP_TYPE_RET; + aop->cycles = 2; + break; + case PIC18_OPCODE_RETFIE: // retfie + aop->type = RZ_ANALYSIS_OP_TYPE_RET; + break; + case PIC18_OPCODE_TBLWTMs: // tblwt + case PIC18_OPCODE_TBLWTMsi: // tblwt + case PIC18_OPCODE_TBLWTis: // tblwt + case PIC18_OPCODE_TBLWTMsd: // tblwt + aop->type = RZ_ANALYSIS_OP_TYPE_LOAD; + break; + case PIC18_OPCODE_TBLRDis: // tblrd + case PIC18_OPCODE_TBLRDs: // tblrd + case PIC18_OPCODE_TBLRDsi: // tblrd + case PIC18_OPCODE_TBLRDsd: // tblrd + aop->type = RZ_ANALYSIS_OP_TYPE_STORE; + break; + case PIC18_OPCODE_POP: // pop + aop->type = RZ_ANALYSIS_OP_TYPE_POP; + break; + case PIC18_OPCODE_PUSH: // push + aop->type = RZ_ANALYSIS_OP_TYPE_PUSH; + break; + case PIC18_OPCODE_NOP: // nop + aop->type = RZ_ANALYSIS_OP_TYPE_NOP; + aop->cycles = 1; + break; + default: + goto err; + } + + if (mask & RZ_ANALYSIS_OP_MASK_ESIL) { + pic18_esil(aop, &op, addr, buf); + } + + if (mask & RZ_ANALYSIS_OP_MASK_IL) { + Pic18ILContext ctx = { + .op = &op, + .mm = ((PicContext *)analysis->plugin_data)->pic18_mm, + }; + aop->il_op = pic18_il(&ctx); + } + + return aop->size; +err: + aop->type = RZ_ANALYSIS_OP_TYPE_ILL; + return aop->size; +} + +static char *analysis_pic_pic18_get_reg_profile(RzAnalysis *esil) { + const char *p = + "#pc lives in nowhere actually" + "=PC pc\n" + "=SP tos\n" + "=A0 porta\n" + "=A1 portb\n" + "gpr pc .32 0 0\n" + "gpr pcl .8 0 0\n" + "gpr pclath .8 1 0\n" + "gpr pclatu .8 2 0\n" + "#bsr max is 0b111\n" + "gpr bsr .8 4 0\n" + "#tos doesn't exist\n" + "#general rule of thumb any register of size >8 bits has no existence\n" + "gpr tos .32 5 0\n" + "gpr tosl .8 5 0\n" + "gpr tosh .8 6 0\n" + "gpr tosu .8 7 0\n" + + "gpr indf0 .16 9 0\n" + "gpr fsr0 .12 9 0\n" + "gpr fsr0l .8 9 0\n" + "gpr fsr0h .8 10 0\n" + "gpr indf1 .16 11 0\n" + "gpr fsr1 .12 11 0\n" + "gpr fsr1l .8 11 0\n" + "gpr fsr1h .8 12 0\n" + "gpr indf2 .16 13 0\n" + "gpr fsr2 .12 13 0\n" + "gpr frs2l .8 13 0\n" + "gpr fsr2h .8 14 0\n" + "gpr tblptr .22 15 0\n" + "gpr tblptrl .8 15 0\n" + "gpr tblptrh .8 16 0\n" + "gpr tblptru .8 17 0\n" + "gpr rcon .8 18 0\n" + "gpr memcon .8 19 0\n" + "gpr intcon .8 20 0\n" + "gpr intcon2 .8 21 0\n" + "gpr intcon3 .8 22 0\n" + "gpr pie1 .8 23 0\n" + "gpr porta .7 29 0\n" + "gpr trisa .8 30 0\n" + "gpr portb .8 33 0\n" + "gpr tisb .8 34 0\n" + "gpr latb .8 35 0\n" + "gpr portc .8 36 0\n" + "gpr trisc .8 37 0\n" + "gpr latc .8 38 0\n" + "gpr portd .8 39 0\n" + "gpr trisd .8 40 0\n" + "gpr latd .8 41 0\n" + "gpr pspcon .8 42 0\n" + "gpr porte .8 43 0\n" + "gpr trise .8 44 0\n" + "gpr late .8 45 0\n" + "gpr t0con .8 46 0\n" + "gpr t1con .8 47 0\n" + "gpr t2con .8 48 0\n" + "gpr tmr1h .8 50 0\n" + "gpr tmr0h .8 51 0\n" + "gpr tmr1l .8 52 0\n" + "gpr tmr2 .8 53 0\n" + "gpr pr2 .8 54 0\n" + "gpr ccpr1h .8 55 0\n" + "gpr postinc2 .8 56 0\n" + "gpr ccpr1l .8 57 0\n" + "gpr postdec2 .8 58 0\n" + "gpr ccp1con .8 59 0\n" + "gpr preinc2 .8 60 0\n" + "gpr ccpr2h .8 61 0\n" + "gpr plusw2 .8 62 0\n" + "gpr ccpr2l .8 63 0\n" + "gpr ccp2con .8 64 0\n" + "gpr status .8 65 0\n" + "flg c .1 .520 0\n" + "flg dc .1 .521 0\n" + "flg z .1 .522 0\n" + "flg ov .1 .523 0\n" + "flg n .1 .524 0\n" + "gpr prod .16 66 0\n" + "gpr prodl .8 66 0\n" + "gpr prodh .8 67 0\n" + "gpr osccon .8 68 0\n" + "gpr tmr3h .8 69 0\n" + "gpr lvdcon .8 70 0\n" + "gpr tmr3l .8 71 0\n" + "gpr wdtcon .8 72 0\n" + "gpr t3con .8 73 0\n" + "gpr spbrg .8 74 0\n" + "gpr postinc0 .8 75 0\n" + "gpr rcreg .8 76 0\n" + "gpr postdec0 .8 77 0\n" + "gpr txreg .8 78 0\n" + "gpr preinc0 .8 79 0\n" + "gpr txsta .8 80 0\n" + "gpr plusw0 .8 81 0\n" + "gpr rcsta .8 82 0\n" + "gpr sspbuf .8 83 0\n" + "gpr wreg .8 84 0\n" + "gpr sspadd .8 85 0\n" + "gpr sspstat .8 86 0\n" + "gpr postinc1 .8 87 0\n" + "gpr sspcon1 .8 88 0\n" + "gpr postdec1 .8 89 0\n" + "gpr sspcon2 .8 90 0\n" + "gpr preinc1 .8 91 0\n" + "gpr adresh .8 92 0\n" + "gpr plusw1 .8 93 0\n" + "gpr adresl .8 94 0\n" + "gpr adcon0 .8 95 0\n" + "#stkprt max is 0b11111\n" + "gpr stkptr .8 96 0\n" + "gpr tblat .8 14 0\n" + "gpr _sram .8 98 0\n" + "gpr _stack .8 99 0\n"; + return strdup(p); +} diff --git a/librz/arch/isa/pic/pic18_esil.inc b/librz/arch/isa/pic/pic18_esil.inc new file mode 100644 index 00000000000..63c198f8399 --- /dev/null +++ b/librz/arch/isa/pic/pic18_esil.inc @@ -0,0 +1,80 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-FileCopyrightText: 2015-2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +static void pic18_cond_branch_esil(RzAnalysisOp *aop, ut64 addr, const ut8 *buf, char *flag) { + rz_strbuf_setf(&aop->esil, "%s,?,{,0x%" PFMT64x ",pc,=,}", flag, aop->jump); +} + +static void pic18_esil( + RzAnalysisOp *aop, Pic18Op *op, ut64 addr, const ut8 *buf) { + switch (op->code) { + case PIC18_OPCODE_BRA: // bra + rz_strbuf_setf(&aop->esil, "0x%" PFMT64x ",pc,=", aop->jump); + break; + case PIC18_OPCODE_BZ: // bz + pic18_cond_branch_esil(aop, addr, buf, "z"); + break; + case PIC18_OPCODE_BNZ: // bnz + pic18_cond_branch_esil(aop, addr, buf, "z,!"); + break; + case PIC18_OPCODE_BNC: // bnc + pic18_cond_branch_esil(aop, addr, buf, "c,!"); + break; + case PIC18_OPCODE_BOV: // bov + pic18_cond_branch_esil(aop, addr, buf, "ov"); + break; + case PIC18_OPCODE_BNOV: // bnov + pic18_cond_branch_esil(aop, addr, buf, "ov,!"); + break; + case PIC18_OPCODE_BN: // bn + pic18_cond_branch_esil(aop, addr, buf, "n"); + break; + case PIC18_OPCODE_BNN: // bnn + pic18_cond_branch_esil(aop, addr, buf, "n,!"); + break; + case PIC18_OPCODE_BC: // bc + pic18_cond_branch_esil(aop, addr, buf, "c"); + break; + case PIC18_OPCODE_GOTO: // goto + rz_strbuf_setf(&aop->esil, "0x%" PFMT64x ",pc,=", aop->jump); + break; + case PIC18_OPCODE_ADDLW: // addlw + // TODO add support for dc flag + rz_strbuf_setf(&aop->esil, "0x%x,wreg,+=,$z,z,:=,7,$s,n,:=,7,$c,c,:=,7,$o,ov,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_MOVLW: // movlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_MULLW: // mullw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,*,prod,=", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_RETLW: // retlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,=,tos,pc,=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_ANDLW: // andlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,&=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_XORLW: // xorlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,^=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_IORLW: // iorlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,^=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_SUBLW: // sublw + // TODO add support for dc flag + rz_strbuf_setf(&aop->esil, "wreg,0x%x,-,wreg,=,$z,z,:=,7,$s,n,:=,7,$c,c,:=,7,$o,ov,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_MOVLB: // movlb + rz_strbuf_setf(&aop->esil, "0x%x,bsr,=,", *(ut16 *)buf & 0xf); + break; + case PIC18_OPCODE_RETURN: // return + rz_strbuf_setf(&aop->esil, "tos,pc,=,"); + break; + case PIC18_OPCODE_NOP: // nop + rz_strbuf_setf(&aop->esil, ","); + break; + default: break; + } +} \ No newline at end of file diff --git a/librz/arch/isa/pic/pic18_il.inc b/librz/arch/isa/pic/pic18_il.inc new file mode 100644 index 00000000000..dbce1ed3794 --- /dev/null +++ b/librz/arch/isa/pic/pic18_il.inc @@ -0,0 +1,461 @@ +// SPDX-FileCopyrightText: 2024 billow +// SPDX-License-Identifier: LGPL-3.0-only + +#include + +static ut64 pic18_regadr(const HtSU *mm, const char *v) { + bool f = false; + ut64 adr = ht_su_find((HtSU *)mm, v, &f); + if (f) { + return adr; + } + rz_warn_if_reached(); + return UT64_MAX; +} + +static RzILOpPure *varg_mm(const HtSU *mm, const char *v) { + bool f = false; + ut64 adr = ht_su_find((HtSU *)mm, v, &f); + if (f) { + return LOAD(U16(adr)); + } + ut8 b = pic18_status(v); + if (b != 0xff) { + return BITN(varg_mm(mm, "status"), b); + } + if (RZ_STR_EQ(v, "tblptr")) { + return APPEND(varg_mm(mm, "tblptru"), APPEND(varg_mm(mm, "tblptrh"), varg_mm(mm, "tblptrl"))); + } + rz_warn_if_reached(); + return NULL; +} + +static RzILOpEffect *setg_mm(const HtSU *mm, const char *v, RzILOpPure *x) { + bool f = false; + ut64 adr = ht_su_find((HtSU *)mm, v, &f); + if (f) { + return STORE(U16(adr), x); + } + ut8 b = pic18_status(v); + if (b != 0xff) { + return setg_mm(mm, "status", bit_set(varg_mm(mm, "status"), b, x)); + } + if (RZ_STR_EQ(v, "tblptr")) { + return SEQ4( + SETL("__tblptr", x), + setg_mm(mm, "tblptrl", UNSIGNED(8, VARL("__tblptr"))), + setg_mm(mm, "tblptrh", UNSIGNED(8, SHIFTR0(VARL("__tblptr"), U8(8)))), + setg_mm(mm, "tblptru", UNSIGNED(8, SHIFTR0(VARL("__tblptr"), U8(16))))); + } + rz_warn_if_reached(); + return NULL; +} + +#undef VARG +#undef SETG +#define VARG(x) varg_mm(ctx->mm, x) +#define SETG(v, x) setg_mm(ctx->mm, v, x) + +#define K (ctx->op->k) +#define D (ctx->op->d) +#define F (ctx->op->f) +#define B (ctx->op->b) +#define N (ctx->op->n) +#define PC (ctx->op->addr) + +#define RW "wreg" +#define VRW (VARG(RW)) +#define RF pic18_regname(F) +#define VRF (VARG(pic18_regname(F))) +#define RWF (D ? pic18_regname(F) : RW) +#define VRWF (VARG(RWF)) + +#define VPC (U16(PC)) +#define RC "c" +#define VRC VARG(RC) +#define RN "n" +#define VRN VARG(RN) +#define ROV "ov" +#define VROV VARG(ROV) +#define RZ "z" +#define VRZ VARG(RZ) +#define RS "s" +#define VRS VARG(RS) + +/** + * The `d` bit selects the destination for the operation. + * If `d` is 1; the result is stored back in the File Register `f`. + * If `d` is 0; the result is stored in the WREG Register. + * + * The `a` bit selects which bank is accessed for the operation. + * If `a` is 1; the bank specified by the BSR Register is used. + * If `a` is 0; the access bank is used. + */ +static RzILOpEffect *set_dest(const Pic18ILContext *ctx, RzILOpPure *x) { + const char *regname = ctx->op->d ? pic18_regname(F) : RW; + if (ctx->op->a) { + ut64 adr = pic18_regadr(ctx->mm, regname); + if (adr != UT64_MAX) { + return STORE(ADD(MUL(UNSIGNED(16, LOGAND(VARG("bsr"), U8(0x0f))), U16(0x100)), U16(adr)), + x); + } + return NULL; + } + return SETG(regname, x); +} + +static RzILOpEffect *status_add(RzILOpPure *a, RzILOpPure *b, RzILOpPure *res, RzILOpPure *curry) { + return NOP(); +} + +static RzILOpEffect *status_sub(RzILOpPure *a, RzILOpPure *b, RzILOpPure *res, RzILOpPure *curry) { + return NOP(); +} + +static RzILOpEffect *status_res(const Pic18ILContext *ctx, RzILOpPure *res) { + return NOP(); +} + +static RzILOpEffect *set_dest_status(const Pic18ILContext *ctx, RzILOpPure *x) { + return SEQ3( + SETL("__res", x), + status_res(ctx, VARL("__res")), + set_dest(ctx, VARL("__res"))); +} + +static RzILOpPure *complement_1(RzILOpPure *x) { + return NEG(x); +} + +static RzILOpPure *complement_2(RzILOpPure *x) { + return ADD(U8(1), NEG(x)); +} + +static RzILOpPure *decimal_adjust(const Pic18ILContext *ctx, RzILOpPure *x) { + return LET( + "_x03", UNSIGNED(4, x), + LET( + "_x47", UNSIGNED(4, SHIFTR0(DUP(x), U8(4))), + APPEND( + ITE(OR(UGT(VARL("_x47"), UN(4, 9)), VARG("c")), + ADD(VARL("_x47"), UN(4, 6)), + VARL("_x47")), + ITE(OR(UGT(VARL("_x03"), UN(4, 9)), VARG("dc")), + ADD(VARL("_x03"), UN(4, 6)), + VARL("_x03"))))); +} + +static RzILOpEffect *op_add(const Pic18ILContext *ctx, const char *dst, + RzILOpPure *a, RzILOpPure *b, RzILOpPure *curry) { + if (dst) { + return SEQ3( + SETL("_res", ADD(a, curry ? ADD(b, curry) : b)), + status_add(DUP(a), DUP(b), VARL("_res"), curry ? DUP(curry) : NULL), + SETG(dst, VARL("_res"))); + } + return SEQ3( + SETL("_res", ADD(a, curry ? ADD(b, curry) : b)), + status_add(DUP(a), DUP(b), VARL("_res"), curry ? DUP(curry) : NULL), + set_dest(ctx, VARL("_res"))); +} + +static RzILOpEffect *op_sub(const Pic18ILContext *ctx, const char *dst, + RzILOpPure *a, RzILOpPure *b, RzILOpPure *curry) { + if (dst) { + return SEQ3( + SETL("_res", SUB(a, curry ? ADD(b, curry) : b)), + status_sub(DUP(a), DUP(b), VARL("_res"), curry ? DUP(curry) : NULL), + SETG(dst, VARL("_res"))); + } + return SEQ3( + SETL("_res", SUB(a, curry ? ADD(b, curry) : b)), + status_sub(DUP(a), DUP(b), VARL("_res"), curry ? DUP(curry) : NULL), + set_dest(ctx, VARL("_res"))); +} + +static RzILOpEffect *op_branch(const Pic18ILContext *ctx, RzILOpPure *condition) { + return condition ? BRANCH(condition, JMP(U16(PC + 2 + 2 * ctx->op->n)), NOP()) + : JMP(U16(PC + 2 + 2 * ctx->op->n)); +} + +static RzILOpEffect *load_shadows_opt(const Pic18ILContext *ctx) { + return BRANCH(NON_ZERO(VARG("s")), + SEQ3( + SETG("ws", VRW), + SETG("ss", VRS), + SETG("bsrs", VARG("bsr"))), + NOP()); +} + +static RzILOpEffect *op_call(const Pic18ILContext *ctx) { + return SEQ3( + SETG("tos", U16(PC + 4)), + JMP(U32(K << 1)), + load_shadows_opt(ctx)); +} + +static RzILOpEffect *op_and(const Pic18ILContext *ctx, const char *dst, + RzILOpPure *a, RzILOpPure *b) { + return SEQ3( + SETL("_res", LOGAND(a, b)), + status_res(ctx, VARL("_res")), + SETG(dst, VARL("_res"))); +} + +static RzILOpEffect *op_skip_if(const Pic18ILContext *ctx, RzILOpPure *condition) { + return BRANCH(condition, JMP(U16(PC + INS_LEN * 2)), NOP()); +} + +static RzILOpEffect *set_prod16(const Pic18ILContext *ctx, RzILOpPure *res) { + return SEQ3( + SETL("_res", res), + SETG("prodh", UNSIGNED(8, SHIFTR0(VARL("_res"), U8(8)))), + SETG("prodl", UNSIGNED(8, VARL("_res")))); +} + +static RzILOpEffect *op_pop(const Pic18ILContext *ctx) { + return SEQ2( + SETG("stkptr", SUB(VARG("stkptr"), U16(4))), + SETG("tos", LOADW(32, ADD(VARG("_stack"), VARG("stkptr"))))); +} + +static RzILOpEffect *op_pop_jmp(const Pic18ILContext *ctx) { + return SEQ3( + SETL("_pc", VARG("tos")), + op_pop(ctx), + JMP(VARL("_pc"))); +} + +static RzILOpEffect *op_push(const Pic18ILContext *ctx, RzILOpPure *x) { + return SEQ3( + SETG("stkptr", ADD(VARG("stkptr"), U16(4))), + STOREW(ADD(VARG("_stack"), VARG("stkptr")), x), + SETG("tos", DUP(x))); +} + +static RzILOpEffect *pic18_il(Pic18ILContext *ctx) { + switch (ctx->op->code) { + case PIC18_OPCODE_ADDLW: return op_add(ctx, RW, VRW, U16(K), NULL); + case PIC18_OPCODE_ADDWF: return op_add(ctx, NULL, VRW, VRF, NULL); + case PIC18_OPCODE_ADDWFC: return op_add(ctx, NULL, VRW, VRF, VRC); + case PIC18_OPCODE_ANDLW: return op_and(ctx, RW, VRW, U16(K)); + case PIC18_OPCODE_ANDWF: return op_and(ctx, NULL, VRW, VRF); + case PIC18_OPCODE_BC: return op_branch(ctx, VRC); + case PIC18_OPCODE_BN: return op_branch(ctx, VRN); + case PIC18_OPCODE_BOV: return op_branch(ctx, VROV); + case PIC18_OPCODE_BZ: return op_branch(ctx, VRZ); + case PIC18_OPCODE_BNC: return op_branch(ctx, INV(VRC)); + case PIC18_OPCODE_BNN: return op_branch(ctx, INV(VRN)); + case PIC18_OPCODE_BNOV: return op_branch(ctx, INV(VROV)); + case PIC18_OPCODE_BNZ: return op_branch(ctx, INV(VRZ)); + case PIC18_OPCODE_BRA: return op_branch(ctx, NULL); + + case PIC18_OPCODE_BCF: return regbit_set(RF, B, 0); + case PIC18_OPCODE_BSF: return regbit_set(RF, B, 1); + case PIC18_OPCODE_BTG: return regbit_set1(RF, B, INV(bit_get(VRF, B))); + case PIC18_OPCODE_BTFSC: return op_skip_if(ctx, INV(bit_get(VRF, B))); + case PIC18_OPCODE_BTFSS: return op_skip_if(ctx, bit_get(VRF, B)); + + case PIC18_OPCODE_CALL: return op_call(ctx); + case PIC18_OPCODE_CLRF: return SEQ2(SETG(RF, U8(0)), SETG("z", IL_TRUE)); + case PIC18_OPCODE_CLRWDT: + return SEQ4( + SETG("wdt", U8(0)), + SETG("wdt_prescaler_count", IL_FALSE), + SETG("to", IL_TRUE), + SETG("pd", IL_TRUE)); + case PIC18_OPCODE_COMF: return set_dest_status(ctx, complement_1(VRF)); + case PIC18_OPCODE_CPFSEQ: return op_skip_if(ctx, EQ(VRW, VRF)); + case PIC18_OPCODE_CPFSGT: return op_skip_if(ctx, SGT(VRW, VRF)); + case PIC18_OPCODE_CPFSLT: return op_skip_if(ctx, SLT(VRW, VRF)); + case PIC18_OPCODE_DAW: + return SEQ3( + SETL("_res", decimal_adjust(ctx, VRW)), + SETG("c", IL_FALSE), // TODO: status C + SETG(RW, VARL("_res"))); + case PIC18_OPCODE_DECF: + return SEQ3( + SETL("_res", SUB(VRF, U8(1))), + status_sub(VRF, U8(1), VARL("_res"), NULL), + set_dest(ctx, VARL("_res"))); + case PIC18_OPCODE_DECFSZ: + return SEQ3( + SETL("_res", SUB(VRF, U8(1))), + set_dest(ctx, VARL("_res")), + op_skip_if(ctx, IS_ZERO(VARL("_res")))); + case PIC18_OPCODE_DCFSNZ: + return SEQ3( + SETL("_res", SUB(VRF, U8(1))), + set_dest(ctx, VARL("_res")), + op_skip_if(ctx, NON_ZERO(VARL("_res")))); + case PIC18_OPCODE_GOTO: return JMP(U32((ut32)K << 1)); + case PIC18_OPCODE_INCF: + return SEQ3( + SETL("_res", ADD(VRF, U8(1))), + status_add(VRF, U8(1), VARL("_res"), NULL), + set_dest(ctx, VARL("_res"))); + case PIC18_OPCODE_INCFSZ: + return SEQ3( + SETL("_res", ADD(VRF, U8(1))), + set_dest(ctx, VARL("_res")), + op_skip_if(ctx, IS_ZERO(VARL("_res")))); + case PIC18_OPCODE_INFSNZ: + return SEQ3( + SETL("_res", ADD(VRF, U8(1))), + set_dest(ctx, VARL("_res")), + op_skip_if(ctx, NON_ZERO(VARL("_res")))); + case PIC18_OPCODE_IORWF: + return set_dest_status(ctx, LOGOR(VRW, VRF)); + case PIC18_OPCODE_IORLW: + return SEQ2( + SETG(RW, LOGOR(VRW, U16(K))), + status_res(ctx, VRW)); + case PIC18_OPCODE_LFSR: return SETG(RFSR(F), U16(K)); + case PIC18_OPCODE_MOVF: + return set_dest_status(ctx, VRF); + case PIC18_OPCODE_MOVFF: + return SETG(pic18_regname(ctx->op->d), VARG(pic18_regname(ctx->op->s))); + case PIC18_OPCODE_MOVLB: + return SETG("bsr", LOGOR(U8(K), LOGAND(VARG("bsr"), U8(0xf0)))); + case PIC18_OPCODE_MOVLW: + return SETG(RW, U8(K)); + case PIC18_OPCODE_MOVWF: + return SETG(RF, VRW); + case PIC18_OPCODE_MULLW: + return set_prod16(ctx, MUL(UNSIGNED(16, VRW), U16(K))); + case PIC18_OPCODE_MULWF: + return set_prod16(ctx, MUL(UNSIGNED(16, VRW), UNSIGNED(16, VRF))); + case PIC18_OPCODE_NOP: return NOP(); + case PIC18_OPCODE_NEGF: return SETG(RF, complement_2(VRF)); + case PIC18_OPCODE_POP: return op_pop(ctx); + case PIC18_OPCODE_PUSH: return op_push(ctx, U32(PC)); + case PIC18_OPCODE_RCALL: + return SEQ2( + op_push(ctx, U32(PC + 2)), + JMP(U32(PC + 2 + 2 * N))); + case PIC18_OPCODE_RESET: return NOP(); + case PIC18_OPCODE_RETFIE: + return SEQ3( + BRANCH( + IS_ZERO(VARG("ipen")), + SETG("gie", IL_TRUE), + SEQ2( + SETL("_g", APPEND(VARG("gieh"), VARG("geil"))), + BRANCH( + EQ(VARG("_g"), UN(2, 0b11)), + SETG("invalid", IL_TRUE), + BRANCH( + EQ(VARG("_g"), UN(2, 0b10)), + SEQ2(SETG("giel", IL_TRUE), + SETG("gieh", IL_TRUE)), + NOP())))), + load_shadows_opt(ctx), + op_pop_jmp(ctx)); + case PIC18_OPCODE_RETLW: + return SEQ2( + SETG(RW, U8(K)), + op_pop_jmp(ctx)); + case PIC18_OPCODE_RETURN: + return SEQ2( + load_shadows_opt(ctx), + op_pop_jmp(ctx)); + case PIC18_OPCODE_RLNCF: + return set_dest_status(ctx, LET("_x", VRF, LOGOR(SHIFTL0(VARLP("_x"), U8(7)), BOOL_TO_BV(MSB(VARLP("_x")), 8)))); + case PIC18_OPCODE_RRNCF: + return set_dest_status(ctx, LET("_x", VRF, LOGOR(SHIFTR0(VARLP("_x"), U8(7)), BOOL_TO_BV(LSB(VARLP("_x")), 8)))); + case PIC18_OPCODE_RLCF: + return SEQ3( + SETL("_x", VRF), + SETG("c", MSB(VARG("_x"))), + set_dest_status(ctx, LOGOR(SHIFTL0(VARLP("_x"), U8(7)), BOOL_TO_BV(VRC, 8)))); + case PIC18_OPCODE_RRCF: + return SEQ3( + SETL("_x", VRF), + SETG("c", LSB(VARG("_x"))), + set_dest_status(ctx, LOGOR(SHIFTR0(VARLP("_x"), U8(7)), BOOL_TO_BV(VRC, 8)))); + case PIC18_OPCODE_SETF: + return SETG(RF, U8(0xff)); + case PIC18_OPCODE_SLEEP: + return SEQ4( + SETG("wdt", U8(0)), + SETG("wdt_prescaler_count", IL_FALSE), + SETG("to", IL_TRUE), + SETG("pd", IL_FALSE)); + case PIC18_OPCODE_SUBFWB: return op_sub(ctx, NULL, VRW, VRF, VRC); + case PIC18_OPCODE_SUBLW: return op_sub(ctx, RW, U8(K), VRW, NULL); + case PIC18_OPCODE_SUBWF: return op_sub(ctx, NULL, VRF, VRW, NULL); + case PIC18_OPCODE_SUBWFB: return op_sub(ctx, NULL, VRF, VRW, VRC); + case PIC18_OPCODE_SWAPF: + return set_dest(ctx, APPEND(UNSIGNED(4, VRF), UNSIGNED(4, SHIFTR0(VRF, U8(4))))); + + case PIC18_OPCODE_TBLRDs: + return SETG("tablat", LOAD(VARG("tblptr"))); + case PIC18_OPCODE_TBLRDis: + return SEQ2( + SETG("tblptr", ADD(VARG("tblptr"), U32(1))), + SETG("tablat", LOAD(VARG("tblptr")))); + case PIC18_OPCODE_TBLRDsd: + return SEQ2( + SETG("tablat", LOAD(VARG("tblptr"))), + SETG("tblptr", SUB(VARG("tblptr"), U32(1)))); + case PIC18_OPCODE_TBLRDsi: + return SEQ2( + SETG("tablat", LOAD(VARG("tblptr"))), + SETG("tblptr", ADD(VARG("tblptr"), U32(1)))); + case PIC18_OPCODE_TBLWTMs: + return STORE(VARG("tblptr"), VARG("tablat")); + case PIC18_OPCODE_TBLWTis: + return SEQ2( + SETG("tblptr", ADD(VARG("tblptr"), U32(1))), + STORE(VARG("tblptr"), VARG("tablat"))); + case PIC18_OPCODE_TBLWTMsd: + return SEQ2( + STORE(VARG("tblptr"), VARG("tablat")), + SETG("tblptr", SUB(VARG("tblptr"), U32(1)))); + case PIC18_OPCODE_TBLWTMsi: + return SEQ2( + STORE(VARG("tblptr"), VARG("tablat")), + SETG("tblptr", ADD(VARG("tblptr"), U32(1)))); + case PIC18_OPCODE_TSTFSZ: + return op_skip_if(ctx, IS_ZERO(VRF)); + case PIC18_OPCODE_XORWF: + return set_dest_status(ctx, XOR(VRW, VRF)); + case PIC18_OPCODE_XORLW: + return SEQ2( + SETG(RW, XOR(VRW, VRF)), + status_res(ctx, VRW)); + case PIC18_OPCODE_INVALID: break; + } + return NULL; +} + +#undef K +#undef D +#undef F +#undef B +#undef N +#undef PC + +#undef RW +#undef VRW +#undef RF +#undef VRF +#undef RWF +#undef VRWF +#undef VPC +#undef RC +#undef VRC +#undef RN +#undef VRN +#undef ROV +#undef VROV +#undef RZ +#undef VRZ +#undef RS +#undef VRS + +static RzAnalysisILConfig *pic18_il_config( + RZ_NONNULL RzAnalysis *analysis) { + RzAnalysisILConfig *cfg = rz_analysis_il_config_new(32, false, 16); + return cfg; +} diff --git a/librz/arch/isa/pic/pic_baseline.c b/librz/arch/isa/pic/pic_baseline.c index 49bb05bb502..b57751bb6b1 100644 --- a/librz/arch/isa/pic/pic_baseline.c +++ b/librz/arch/isa/pic/pic_baseline.c @@ -197,7 +197,7 @@ const PicBaselineOpInfo *pic_baseline_get_op_info(PicBaselineOpcode opcode) { return &pic_baseline_op_info[opcode]; } -int pic_baseline_disassemble(RzAsmOp *op, const ut8 *b, int l) { +int pic_baseline_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) { #define EMIT_INVALID \ { \ op->size = 1; \ diff --git a/librz/arch/isa/pic/pic_baseline.h b/librz/arch/isa/pic/pic_baseline.h index af5abc5783f..4d7d4fc4900 100644 --- a/librz/arch/isa/pic/pic_baseline.h +++ b/librz/arch/isa/pic/pic_baseline.h @@ -78,6 +78,6 @@ typedef enum { PicBaselineOpcode pic_baseline_get_opcode(ut16 instr); PicBaselineOpArgs pic_baseline_get_opargs(PicBaselineOpcode opcode); const PicBaselineOpInfo *pic_baseline_get_op_info(PicBaselineOpcode opcode); -int pic_baseline_disassemble(RzAsmOp *op, const ut8 *b, int l); +int pic_baseline_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l); #endif // PIC_BASELINE_H diff --git a/librz/arch/isa/pic/pic_midrange.c b/librz/arch/isa/pic/pic_midrange.c index 429c318cca9..4b3050e2f20 100644 --- a/librz/arch/isa/pic/pic_midrange.c +++ b/librz/arch/isa/pic/pic_midrange.c @@ -3,7 +3,7 @@ #include "pic_midrange.h" -static const PicMidrangeOpInfo +static const PicMidrangeOpAsmInfo pic_midrange_op_info[PIC_MIDRANGE_OPCODE_INVALID] = { { "nop", PIC_MIDRANGE_OP_ARGS_NONE }, { "return", PIC_MIDRANGE_OP_ARGS_NONE }, @@ -11,6 +11,8 @@ static const PicMidrangeOpInfo { "option", PIC_MIDRANGE_OP_ARGS_NONE }, { "sleep", PIC_MIDRANGE_OP_ARGS_NONE }, { "clrwdt", PIC_MIDRANGE_OP_ARGS_NONE }, + { "clrf", PIC_MIDRANGE_OP_ARGS_7F }, + { "clrw", PIC_MIDRANGE_OP_ARGS_NONE }, { "tris", PIC_MIDRANGE_OP_ARGS_2F }, { "movwf", PIC_MIDRANGE_OP_ARGS_7F }, { "clr", PIC_MIDRANGE_OP_ARGS_1D_7F }, @@ -118,6 +120,8 @@ PicMidrangeOpcode pic_midrange_get_opcode(ut16 instr) { switch (instr >> 7) { // 7 first MSB bits case 0x1: return PIC_MIDRANGE_OPCODE_MOVWF; + case 0x2: return PIC_MIDRANGE_OPCODE_CLRW; + case 0x3: return PIC_MIDRANGE_OPCODE_CLRF; case 0x62: return PIC_MIDRANGE_OPCODE_ADDFSR; case 0x63: return PIC_MIDRANGE_OPCODE_MOVLP; case 0x7e: return PIC_MIDRANGE_OPCODE_MOVIW_2; @@ -152,19 +156,6 @@ PicMidrangeOpcode pic_midrange_get_opcode(ut16 instr) { return PIC_MIDRANGE_OPCODE_INVALID; } -/** - * \brief Get \c PicMidrangeOpArgs corresponding to given \c PicMidrangeOpcode. - * - * \param opcode - * \return Corresponding \c OpArgs enum, -1 on failure. - * */ -PicMidrangeOpArgs pic_midrange_get_opargs(PicMidrangeOpcode opcode) { - if (opcode >= PIC_MIDRANGE_OPCODE_INVALID) { - return -1; - } - return pic_midrange_op_info[opcode].args; -} - /** * \brief Get opcode information (mnemonic and arguments) corresponding * to a given \c PicMidrangeOpcode. @@ -172,7 +163,7 @@ PicMidrangeOpArgs pic_midrange_get_opargs(PicMidrangeOpcode opcode) { * \param opcode * \return \c PicMidrangeOpInfo pointer. * */ -const PicMidrangeOpInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode) { +const PicMidrangeOpAsmInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode) { if (opcode >= PIC_MIDRANGE_OPCODE_INVALID) { return NULL; } @@ -189,7 +180,7 @@ const PicMidrangeOpInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode) { * * \return Number of decoded bytes (2 on success, 1 on failure). * */ -int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l) { +int pic_midrange_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) { char fsr_op[6]; st16 branch; @@ -209,7 +200,7 @@ int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l) { EMIT_INVALID } - const PicMidrangeOpInfo *op_info = pic_midrange_get_op_info(opcode); + const PicMidrangeOpAsmInfo *op_info = pic_midrange_get_op_info(opcode); if (!op_info) { EMIT_INVALID } @@ -223,16 +214,20 @@ int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l) { rz_asm_op_set_asm(op, op_info->mnemonic); break; case PIC_MIDRANGE_OP_ARGS_2F: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, + rz_asm_op_setf_asm(op, "%s 0x%x", + op_info->mnemonic, PIC_MIDRANGE_OP_ARGS_2F_GET_F(instr)); break; case PIC_MIDRANGE_OP_ARGS_7F: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, + rz_asm_op_setf_asm(op, "%s 0x%x", + op_info->mnemonic, PIC_MIDRANGE_OP_ARGS_7F_GET_F(instr)); break; case PIC_MIDRANGE_OP_ARGS_1D_7F: - rz_asm_op_setf_asm(op, "%s 0x%x, %c", op_info->mnemonic, - PIC_MIDRANGE_OP_ARGS_7F_GET_F(instr)); + rz_asm_op_setf_asm(op, "%s 0x%x, %c", + op_info->mnemonic, + PIC_MIDRANGE_OP_ARGS_7F_GET_F(instr), + PIC_MIDRANGE_OP_ARGS_7F_GET_F(instr) >> 7 ? 'f' : 'w'); break; case PIC_MIDRANGE_OP_ARGS_1N_6K: if (opcode == PIC_MIDRANGE_OPCODE_ADDFSR) { diff --git a/librz/arch/isa/pic/pic_midrange.h b/librz/arch/isa/pic/pic_midrange.h index 3e1285a6fbe..09f588b2ac2 100644 --- a/librz/arch/isa/pic/pic_midrange.h +++ b/librz/arch/isa/pic/pic_midrange.h @@ -55,7 +55,7 @@ typedef enum { typedef struct _pic_midrange_op { const char *mnemonic; PicMidrangeOpArgs args; -} PicMidrangeOpInfo; +} PicMidrangeOpAsmInfo; typedef enum { PIC_MIDRANGE_OPCODE_NOP = 0, @@ -64,6 +64,8 @@ typedef enum { PIC_MIDRANGE_OPCODE_OPTION, PIC_MIDRANGE_OPCODE_SLEEP, PIC_MIDRANGE_OPCODE_CLRWDT, + PIC_MIDRANGE_OPCODE_CLRF, + PIC_MIDRANGE_OPCODE_CLRW, PIC_MIDRANGE_OPCODE_TRIS, PIC_MIDRANGE_OPCODE_MOVWF, PIC_MIDRANGE_OPCODE_CLR, @@ -115,7 +117,7 @@ typedef enum { PicMidrangeOpcode pic_midrange_get_opcode(ut16 instr); PicMidrangeOpArgs pic_midrange_get_opargs(PicMidrangeOpcode opcode); -const PicMidrangeOpInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode); -int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l); +const PicMidrangeOpAsmInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode); +int pic_midrange_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l); #endif // PIC_MIDRANGE_H diff --git a/librz/arch/isa/pic/pic_midrange_analysis.inc b/librz/arch/isa/pic/pic_midrange_analysis.inc new file mode 100644 index 00000000000..e6e2399edf6 --- /dev/null +++ b/librz/arch/isa/pic/pic_midrange_analysis.inc @@ -0,0 +1,259 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-FileCopyrightText: 2015-2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +#include "pic_midrange.h" +#include "pic_midrange_il.inc" + +typedef void (*pic_midrange_inst_handler_t)(RzAnalysis *analysis, RzAnalysisOp *op, + ut64 addr, + PicMidrangeOpArgsVal *args); + +typedef struct { + PicMidrangeOpcode opcode; + PicMidrangeOpArgs args; + pic_midrange_inst_handler_t handler; + pic_midrange_il_handler il_handler; +} PicMidrangeOpAnalysisInfo; + +#define INST_HANDLER(OPCODE_NAME) \ + static void _inst__##OPCODE_NAME(RzAnalysis *analysis, RzAnalysisOp *op, \ + ut64 addr, \ + PicMidrangeOpArgsVal *args) +#define INST_DECL(NAME, ARGS) \ + [PIC_MIDRANGE_OPCODE_##NAME] = { \ + PIC_MIDRANGE_OPCODE_##NAME, PIC_MIDRANGE_OP_ARGS_##ARGS, \ + _inst__##NAME, IL_LIFTER(NAME) \ + } + +#include "pic_midrange_esil.inc" + +static const PicMidrangeOpAnalysisInfo pic_midrange_op_analysis_info[] = { + INST_DECL(NOP, NONE), + INST_DECL(RETURN, NONE), + INST_DECL(RETFIE, NONE), + INST_DECL(OPTION, NONE), + INST_DECL(SLEEP, NONE), + INST_DECL(CLRWDT, NONE), + INST_DECL(TRIS, 2F), + INST_DECL(MOVWF, 7F), + INST_DECL(CLR, 1D_7F), + INST_DECL(SUBWF, 1D_7F), + INST_DECL(DECF, 1D_7F), + INST_DECL(IORWF, 1D_7F), + INST_DECL(ANDWF, 1D_7F), + INST_DECL(XORWF, 1D_7F), + INST_DECL(ADDWF, 1D_7F), + INST_DECL(MOVF, 1D_7F), + INST_DECL(COMF, 1D_7F), + INST_DECL(INCF, 1D_7F), + INST_DECL(DECFSZ, 1D_7F), + INST_DECL(RRF, 1D_7F), + INST_DECL(RLF, 1D_7F), + INST_DECL(SWAPF, 1D_7F), + INST_DECL(INCFSZ, 1D_7F), + INST_DECL(BCF, 3B_7F), + INST_DECL(BSF, 3B_7F), + INST_DECL(BTFSC, 3B_7F), + INST_DECL(BTFSS, 3B_7F), + INST_DECL(CALL, 11K), + INST_DECL(GOTO, 11K), + INST_DECL(MOVLW, 8K), + INST_DECL(RETLW, 8K), + INST_DECL(IORLW, 8K), + INST_DECL(ANDLW, 8K), + INST_DECL(XORLW, 8K), + INST_DECL(SUBLW, 8K), + INST_DECL(ADDLW, 8K), + INST_DECL(RESET, NONE), + INST_DECL(CALLW, NONE), + INST_DECL(BRW, NONE), + INST_DECL(MOVIW_1, 1N_2M), + INST_DECL(MOVWI_1, 1N_2M), + INST_DECL(MOVLB, 4K), + INST_DECL(LSLF, 1D_7F), + INST_DECL(LSRF, 1D_7F), + INST_DECL(ASRF, 1D_7F), + INST_DECL(SUBWFB, 1D_7F), + INST_DECL(ADDWFC, 1D_7F), + INST_DECL(ADDFSR, 1N_6K), + INST_DECL(MOVLP, 7F), + INST_DECL(BRA, 9K), + INST_DECL(MOVIW_2, 1N_6K), + INST_DECL(MOVWI_2, 1N_6K), + INST_DECL(CLRF, 7F), +}; + +static void analysis_pic_midrange_extract_args( + ut16 instr, + PicMidrangeOpArgs args, + PicMidrangeOpArgsVal *args_val) { + + memset(args_val, 0, sizeof(PicMidrangeOpArgsVal)); + + switch (args) { + case PIC_MIDRANGE_OP_ARGS_NONE: return; + case PIC_MIDRANGE_OP_ARGS_2F: + args_val->f = instr & PIC_MIDRANGE_OP_ARGS_2F_MASK_F; + return; + case PIC_MIDRANGE_OP_ARGS_7F: + args_val->f = instr & PIC_MIDRANGE_OP_ARGS_7F_MASK_F; + return; + case PIC_MIDRANGE_OP_ARGS_1D_7F: + args_val->f = instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_F; + args_val->d = + (instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_D) >> 7; + return; + case PIC_MIDRANGE_OP_ARGS_1N_6K: + args_val->n = + (instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >> 6; + args_val->k = instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K; + return; + case PIC_MIDRANGE_OP_ARGS_3B_7F: + args_val->b = + (instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_B) >> 7; + args_val->f = instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F; + return; + case PIC_MIDRANGE_OP_ARGS_4K: + args_val->k = instr & PIC_MIDRANGE_OP_ARGS_4K_MASK_K; + return; + case PIC_MIDRANGE_OP_ARGS_8K: + args_val->k = instr & PIC_MIDRANGE_OP_ARGS_8K_MASK_K; + return; + case PIC_MIDRANGE_OP_ARGS_9K: + args_val->k = instr & PIC_MIDRANGE_OP_ARGS_9K_MASK_K; + return; + case PIC_MIDRANGE_OP_ARGS_11K: + args_val->k = instr & PIC_MIDRANGE_OP_ARGS_11K_MASK_K; + return; + case PIC_MIDRANGE_OP_ARGS_1N_2M: + args_val->n = + (instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_N) >> 2; + args_val->m = instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_M; + return; + } +} + +static RzIODesc *cpu_memory_map( + RzIOBind *iob, RzIODesc *desc, ut32 addr, ut32 size) { + char mstr[16]; + rz_strf(mstr, "malloc://%d", size); + if (desc && iob->fd_get_name(iob->io, desc->fd)) { + iob->fd_remap(iob->io, desc->fd, addr); + } else { + desc = iob->open_at(iob->io, mstr, RZ_PERM_RW, 0, addr, NULL); + } + return desc; +} + +static bool pic_midrange_reg_write(RzReg *reg, const char *regname, ut32 num) { + if (reg) { + RzRegItem *item = rz_reg_get(reg, regname, RZ_REG_TYPE_GPR); + if (item) { + rz_reg_set_value(reg, item, num); + return true; + } + } + return false; +} + +static void analysis_pic_midrange_setup(RzAnalysis *analysis, bool force) { + PicContext *ctx = (PicContext *)analysis->plugin_data; + + if (!ctx->init_done || force) { + // Allocate memory as needed. + // We assume that code is already allocated with firmware + // image + ctx->mem_sram = + cpu_memory_map(&analysis->iob, ctx->mem_sram, + PIC_MIDRANGE_ESIL_SRAM_START, 0x1000); + ctx->mem_stack = + cpu_memory_map(&analysis->iob, ctx->mem_sram, + PIC_MIDRANGE_ESIL_CSTACK_TOP, 0x20); + + pic_midrange_reg_write(analysis->reg, "_sram", + PIC_MIDRANGE_ESIL_SRAM_START); + pic_midrange_reg_write(analysis->reg, "_stack", + PIC_MIDRANGE_ESIL_CSTACK_TOP); + pic_midrange_reg_write(analysis->reg, "stkptr", 0x1f); + + ctx->init_done = true; + } +} + +static int analysis_pic_midrange_op( + RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask) { + + if (!buf || len < 2) { + op->type = RZ_ANALYSIS_OP_TYPE_ILL; + return op->size; + } + + analysis_pic_midrange_setup(analysis, false); + ut16 instr = rz_read_le16(buf); + // Default op params + op->size = 2; + op->cycles = 1; + op->type = RZ_ANALYSIS_OP_TYPE_NOP; + + PicMidrangeOpcode opcode = pic_midrange_get_opcode(instr); + PicMidrangeOpArgsVal args_val; + + if (opcode < RZ_ARRAY_SIZE(pic_midrange_op_analysis_info)) { + const PicMidrangeOpAnalysisInfo *info = pic_midrange_op_analysis_info + opcode; + if (!info) { + return -1; + } + analysis_pic_midrange_extract_args( + instr, info->args, + &args_val); + if (mask & RZ_ANALYSIS_OP_MASK_ESIL) { + info->handler(analysis, op, addr, &args_val); + } + if (mask & RZ_ANALYSIS_OP_MASK_IL) { + PicMidrangeILContext il_ctx = { + .analysis = analysis, + .op = op, + .args = args_val, + .addr = addr, + .d = instr, + }; + rz_pic_midrange_cpu_state_setup(&il_ctx.cpu, PIC16F886); + op->il_op = info->il_handler(&il_ctx, opcode); + } + } + + return op->size; +} + +static char *analysis_pic_midrange_get_reg_profile(RzAnalysis *a) { + const char *p = + "=PC pc\n" + "=SP stkptr\n" + "=A0 porta\n" + "=A1 portb\n" + "gpr indf0 .8 0 0\n" + "gpr indf1 .8 1 0\n" + "gpr pcl .8 2 0\n" + "gpr status .8 3 0\n" + "flg c .1 3.0 0\n" + "flg dc .1 3.1 0\n" + "flg z .1 3.2 0\n" + "flg pd .1 3.3 0\n" + "flg to .1 3.4 0\n" + "gpr fsr0l .8 4 0\n" + "gpr fsr0h .8 5 0\n" + "gpr fsr1l .8 6 0\n" + "gpr fsr1h .8 7 0\n" + "gpr bsr .8 8 0\n" + "gpr wreg .8 9 0\n" + "gpr pclath .8 10 0\n" + "gpr intcon .8 11 0\n" + "gpr pc .16 12 0\n" + "gpr stkptr .8 14 0\n" + "gpr _sram .32 15 0\n" + "gpr _stack .32 19 0\n"; + return strdup(p); +} diff --git a/librz/arch/isa/pic/pic_midrange_esil.inc b/librz/arch/isa/pic/pic_midrange_esil.inc new file mode 100644 index 00000000000..eefffc4a178 --- /dev/null +++ b/librz/arch/isa/pic/pic_midrange_esil.inc @@ -0,0 +1,522 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-FileCopyrightText: 2015-2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +#define e(frag) rz_strbuf_append(&op->esil, frag) +#define ef(frag, ...) rz_strbuf_appendf(&op->esil, frag, __VA_ARGS__) + +#define PIC_MIDRANGE_ESIL_SRAM_START (1 << 16) +#define PIC_MIDRANGE_ESIL_CSTACK_TOP ((1 << 16) + (1 << 12)) + +#define PIC_MIDRANGE_ESIL_BSR_ADDR "bsr,0x80,*,0x%x,+,_sram,+" + +#define PIC_MIDRANGE_ESIL_OPTION_ADDR "0x95,_sram,+" + +#define PIC_MIDRANGE_ESIL_UPDATE_FLAGS \ + "$z,z,:=," \ + "7,$c,c,:=," \ + "4,$c,dc,:=," + +#define PIC_MIDRANGE_ESIL_LW_OP(O) \ + "0x%x,wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS + +#define PIC_MIDRANGE_ESIL_FWF_OP(O) \ + "wreg," PIC_MIDRANGE_ESIL_BSR_ADDR "," #O \ + "=[1]," PIC_MIDRANGE_ESIL_UPDATE_FLAGS + +#define PIC_MIDRANGE_ESIL_WWF_OP(O) \ + PIC_MIDRANGE_ESIL_BSR_ADDR \ + ",[1]," \ + "wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS + +#define PIC_MIDRANGE_ESIL_FWF_OP_C(O) \ + "c,wreg," \ + "+," PIC_MIDRANGE_ESIL_BSR_ADDR "," #O \ + "=[1]," PIC_MIDRANGE_ESIL_UPDATE_FLAGS + +#define PIC_MIDRANGE_ESIL_WWF_OP_C(O) \ + "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1]," #O "," \ + "wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS + +INST_HANDLER(NOP) {} + +INST_HANDLER(RETFIE) { + op->type = RZ_ANALYSIS_OP_TYPE_RET; +} + +INST_HANDLER(OPTION) { + op->type = RZ_ANALYSIS_OP_TYPE_STORE; +} + +INST_HANDLER(TRIS) { + op->type = RZ_ANALYSIS_OP_TYPE_STORE; +} + +INST_HANDLER(RETURN) { + op->type = RZ_ANALYSIS_OP_TYPE_RET; + e("0x1f,stkptr,==,$z,?{,BREAK,},"); + e("_stack,stkptr,2,*,+,[2],2,*,pc,=,"); + e("0x01,stkptr,-=,"); + e("0xff,stkptr,==,$z,?{,0x1f,stkptr,=,},"); +} + +INST_HANDLER(CALL) { + ut64 pclath; + op->type = RZ_ANALYSIS_OP_TYPE_CALL; + rz_analysis_esil_reg_read(analysis->esil, "pclath", &pclath, NULL); + op->jump = 2 * (((pclath & 0x78) << 8) + args->k); + ef("8,pclath,0x78,&,<<,0x%x,+,2,*,pc,=,", args->k); + e("0x1f,stkptr,==,$z,?{,0xff,stkptr,=,},"); + e("0x0f,stkptr,==,$z,?{,0xff,stkptr,=,},"); + e("0x01,stkptr,+=,"); + ef("0x%" PFMT64x ",_stack,stkptr,2,*,+,=[2],", (addr + 2) / 2); +} + +INST_HANDLER(GOTO) { + ut64 pclath; + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + rz_analysis_esil_reg_read(analysis->esil, "pclath", &pclath, NULL); + op->jump = 2 * (((pclath & 0x78) << 8) + args->k); + ef("8,pclath,0x78,&,<<,0x%x,+,2,*,pc,=,", args->k); +} + +INST_HANDLER(BCF) { + ut8 mask = ~(1 << args->b); + ef(PIC_MIDRANGE_ESIL_BSR_ADDR + ",[1],0x%x,&," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", + args->f, mask, args->f); +} + +INST_HANDLER(BSF) { + ut8 mask = (1 << args->b); + ef(PIC_MIDRANGE_ESIL_BSR_ADDR + ",[1],0x%x,|," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", + args->f, mask, args->f); +} + +INST_HANDLER(BTFSC) { + ut8 mask = (1 << args->b); + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = addr + 4; + op->fail = addr + 2; + ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],0x%x,&,!,?{,0x%" PFMT64x ",pc,=,},", + args->f, mask, op->jump); +} + +INST_HANDLER(BTFSS) { + ut8 mask = (1 << args->b); + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = addr + 4; + op->fail = addr + 2; + ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],0x%x,&,?{,0x%" PFMT64x ",pc,=,},", args->f, + mask, op->jump); +} + +INST_HANDLER(BRA) { + st16 branch = args->k; + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + branch |= ((branch & 0x100) ? 0xfe00 : 0); + op->jump = addr + 2 * (branch + 1); + ef("%s0x%x,1,+,2,*,pc,+=,", branch < 0 ? "-" : "", + branch < 0 ? -branch : branch); +} + +INST_HANDLER(BRW) { + ut64 wreg; + op->type = RZ_ANALYSIS_OP_TYPE_UJMP; + rz_analysis_esil_reg_read(analysis->esil, "wreg", &wreg, NULL); + op->jump = addr + 2 * (wreg + 1); + e("wreg,1,+,2,*,pc,+=,"); +} + +INST_HANDLER(CLR) { + if (args->d) { + ef("0x00," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); + } else { + e("0x00,wreg,=,"); + } + e("1,z,=,"); +} + +INST_HANDLER(SUBWF) { + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + if (args->d) { + ef(PIC_MIDRANGE_ESIL_FWF_OP(-), args->f); + } else { + ef(PIC_MIDRANGE_ESIL_WWF_OP(-), args->f); + e("wreg,0x00,-,wreg,=,c,!=,dc,!=,"); + } +} + +INST_HANDLER(DECFSZ) { + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = addr + 4; + op->fail = addr + 2; + if (args->d) { + ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",-=[1],", args->f); + } else { + ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],-,wreg,=,", + args->f); + } + ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],!,?{,0x%" PFMT64x ",pc,=,},", args->f, + op->jump); +} + +INST_HANDLER(INCFSZ) { + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = addr + 4; + op->fail = addr + 2; + if (args->d) { + ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",+=[1],", args->f); + } else { + ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],+,wreg,=,", + args->f); + } + ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],!,?{,0x%" PFMT64x ",pc,=,},", args->f, + op->jump); +} + +INST_HANDLER(INCF) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + if (args->d) { + ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",+=[1],", args->f); + } else { + ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],+,wreg,=,", + args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(DECF) { + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + if (args->d) { + ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",-=[1],", args->f); + } else { + ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],-,wreg,=,", + args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(IORWF) { + op->type = RZ_ANALYSIS_OP_TYPE_OR; + if (args->d) { + ef(PIC_MIDRANGE_ESIL_FWF_OP(|), args->f); + } else { + ef(PIC_MIDRANGE_ESIL_WWF_OP(|), args->f); + } +} + +INST_HANDLER(ANDWF) { + op->type = RZ_ANALYSIS_OP_TYPE_AND; + if (args->d) { + ef(PIC_MIDRANGE_ESIL_FWF_OP(&), args->f); + } else { + ef(PIC_MIDRANGE_ESIL_WWF_OP(&), args->f); + } +} + +INST_HANDLER(XORWF) { + op->type = RZ_ANALYSIS_OP_TYPE_XOR; + if (args->d) { + ef(PIC_MIDRANGE_ESIL_FWF_OP(^), args->f); + } else { + ef(PIC_MIDRANGE_ESIL_WWF_OP(^), args->f); + } +} + +INST_HANDLER(ADDWF) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + if (args->d) { + ef(PIC_MIDRANGE_ESIL_FWF_OP(+), args->f); + } else { + ef(PIC_MIDRANGE_ESIL_WWF_OP(+), args->f); + } +} + +INST_HANDLER(SUBLW) { + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + ef(PIC_MIDRANGE_ESIL_LW_OP(-), args->k); +} + +INST_HANDLER(ADDLW) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + ef(PIC_MIDRANGE_ESIL_LW_OP(+), args->k); +} + +INST_HANDLER(IORLW) { + op->type = RZ_ANALYSIS_OP_TYPE_OR; + ef(PIC_MIDRANGE_ESIL_LW_OP(|), args->k); +} + +INST_HANDLER(ANDLW) { + op->type = RZ_ANALYSIS_OP_TYPE_AND; + ef(PIC_MIDRANGE_ESIL_LW_OP(&), args->k); +} + +INST_HANDLER(XORLW) { + op->type = RZ_ANALYSIS_OP_TYPE_XOR; + ef(PIC_MIDRANGE_ESIL_LW_OP(^), args->k); +} + +INST_HANDLER(MOVLW) { + op->type = RZ_ANALYSIS_OP_TYPE_LOAD; + ef("0x%x,wreg,=,", args->k); +} + +INST_HANDLER(RETLW) { + op->type = RZ_ANALYSIS_OP_TYPE_RET; + ef("0x%x,wreg,=,", args->k); + e("0x1f,stkptr,==,$z,?{,BREAK,},"); + e("_stack,stkptr,2,*,+,[2],2,*,pc,=,"); + e("0x01,stkptr,-=,"); + e("0xff,stkptr,==,$z,?{,0x1f,stkptr,=,},"); +} + +INST_HANDLER(MOVLP) { + op->type = RZ_ANALYSIS_OP_TYPE_LOAD; + ef("0x%x,pclath,=,", args->f); +} + +INST_HANDLER(MOVLB) { + op->type = RZ_ANALYSIS_OP_TYPE_LOAD; + ef("0x%x,bsr,=,", args->k); +} + +INST_HANDLER(CALLW) { + op->type = RZ_ANALYSIS_OP_TYPE_UCALL; + e("8,pclath,<<,0x%x,+,wreg,2,*,pc,=,"); + e("0x1f,stkptr,==,$z,?{,0xff,stkptr,=,},"); + e("0x0f,stkptr,==,$z,?{,0xff,stkptr,=,},"); + e("0x01,stkptr,+=,"); + ef("0x%" PFMT64x ",_stack,stkptr,2,*,+,=[2],", (addr + 2) / 2); +} + +INST_HANDLER(MOVWF) { + op->type = RZ_ANALYSIS_OP_TYPE_STORE; + ef("wreg," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); +} + +INST_HANDLER(MOVF) { + op->type = RZ_ANALYSIS_OP_TYPE_LOAD; + if (args->d) { + ef(PIC_MIDRANGE_ESIL_BSR_ADDR + ",[1]," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", + args->f, args->f); + } else { + ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],wreg,=,", args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(SWAPF) { + ef("4," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,0x0f,&,", args->f); + ef("4," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,0xf0,&,", args->f); + e("|,"); + ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); +} + +INST_HANDLER(LSLF) { + op->type = RZ_ANALYSIS_OP_TYPE_SHL; + ef("7," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,c,=,", args->f); + if (args->d) { + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",<<=[1],", args->f); + } else { + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,wreg,=,", + args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(LSRF) { + op->type = RZ_ANALYSIS_OP_TYPE_SHR; + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,c,=,", args->f); + if (args->d) { + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",>>=[1],", args->f); + } else { + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,wreg,=,", + args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(ASRF) { + op->type = RZ_ANALYSIS_OP_TYPE_SHR; + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,c,=,", args->f); + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,", args->f); + ef("0x80," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,", args->f); + if (args->d) { + ef("|," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); + } else { + e("|,wreg,=,"); + } + e("$z,z,:=,"); +} + +INST_HANDLER(RRF) { + op->type = RZ_ANALYSIS_OP_TYPE_ROR; + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,", args->f); + if (args->d) { + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",>>=[1]," + "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",|=[1],", + args->f, args->f); + } else { + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,wreg,=," + "c,wreg,|=[1],", + args->f); + } + e("c,=,"); +} + +INST_HANDLER(RLF) { + op->type = RZ_ANALYSIS_OP_TYPE_ROL; + ef("7," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,", args->f); + if (args->d) { + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",<<=[1]," + "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",|=[1],", + args->f, args->f); + } else { + ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,wreg,=," + "c,wreg,|=[1],", + args->f); + } + e("c,=,"); +} + +INST_HANDLER(COMF) { + if (args->d) { + ef("0xff," PIC_MIDRANGE_ESIL_BSR_ADDR ",^=[1],", args->f); + } else { + ef("0xff," PIC_MIDRANGE_ESIL_BSR_ADDR ",^,wreg,=,", args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(RESET) { + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = 0; + e("0x0,pc,=,"); + e("0x1f,stkptr,=,"); +} + +INST_HANDLER(ADDFSR) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + if (args->n == 0) { + ef("0x%x,fsr0l,+=,", args->k); + e("7,$c,?{,0x01,fsr0h,+=,},"); + } else { + ef("0x%x,fsr1l,+=,", args->k); + e("7,$c,?{,0x01,fsr1h,+=,},"); + } +} + +INST_HANDLER(CLRWDT) { + e("1,to,=,"); + e("1,pd,=,"); +} + +INST_HANDLER(SLEEP) { + e("1,to,=,"); + e("0,pd,=,"); +} + +INST_HANDLER(SUBWFB) { + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + e("c,!=,"); + if (args->d) { + ef(PIC_MIDRANGE_ESIL_FWF_OP_C(-), args->f); + } else { + ef(PIC_MIDRANGE_ESIL_WWF_OP_C(-), args->f); + e("wreg,0x00,-,wreg,=,c,!=,dc,!=,"); + } +} + +INST_HANDLER(ADDWFC) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + if (args->d) { + ef(PIC_MIDRANGE_ESIL_FWF_OP_C(+), args->f); + } else { + ef(PIC_MIDRANGE_ESIL_WWF_OP_C(+), args->f); + } +} + +INST_HANDLER(MOVIW_1) { + if (args->n == 0) { + if (!(args->m & 2)) { + ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); + ef("7,$c%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + e("indf0,wreg,=,"); + e("$z,z,:=,"); + if (args->m & 2) { + ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); + ef("7,$c%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + } else { + if (!(args->m & 2)) { + ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); + ef("7,$c%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + e("indf1,wreg,=,"); + e("$z,z,:=,"); + if (args->m & 2) { + ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); + ef("7,$c%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + } +} + +INST_HANDLER(MOVWI_1) { + if (args->n == 0) { + if (!(args->m & 2)) { + ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); + ef("$c7%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + e("wreg,indf0=,"); + e("$z,z,:=,"); + if (args->m & 2) { + ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); + ef("$c7%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + } else { + if (!(args->m & 2)) { + ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); + ef("$c7,fsr1h,%s,", (args->m & 1) ? ",!" : ""); + } + e("wreg,indf1=,"); + e("$z,z,:=,"); + if (args->m & 2) { + ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); + ef("$c7%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + } +} + +INST_HANDLER(MOVIW_2) { + if (args->n == 0) { + e("fsr0l,8,fsr0h,<<,+,"); + } else { + e("fsr1l,8,fsr1h,<<,+,"); + } + ef("0x%x,+,[1],wreg,=,", args->k); +} + +INST_HANDLER(MOVWI_2) { + e("wreg,"); + if (args->n == 0) { + e("fsr0l,8,fsr0h,<<,+,"); + } else { + e("fsr1l,8,fsr1h,<<,+,"); + } + e("=[1],"); +} + +INST_HANDLER(CLRF) {} diff --git a/librz/arch/isa/pic/pic_midrange_il.inc b/librz/arch/isa/pic/pic_midrange_il.inc new file mode 100644 index 00000000000..822c9259b9d --- /dev/null +++ b/librz/arch/isa/pic/pic_midrange_il.inc @@ -0,0 +1,594 @@ +// SPDX-FileCopyrightText: 2023 Siddharth Mishra +// SPDX-FileCopyrightText: 2024 Billow +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include + +#include "pic_midrange.h" + +#include + +#include +#include + +/** + * PIC Mid-Range Device Type. + * Since each device has it's own set of supported instructions + * and memory map (# of banks, register arrangement etc...), + * we'll support analysis of each of these devices differently! + * */ +typedef enum pic16f_device_type_t { + PIC16F882, + PIC16F883, + PIC16F884, + PIC16F886, + PIC16F887, + PIC_MIDRANGE_SUPPORTED_DEVICE_NUM +} PicMidrangeDeviceType; + +/** + * This struct will store the CPU state of a PIC Mid-Range + * device while being uplifted. + * + * Register are indexed using a value between 0x00-0x7f and a selected bank. + * Instructions are indexed using a page selector (PCLATH) + * Hence we need to maintain a state of CPU while being analyzed. + * + * This opens possibilities of storing more useful data to improve the process. + * */ +typedef struct pic_midrange_cpu_state_t { + PicMidrangeDeviceType device_type; + ut8 selected_bank; ///< for register indexing. + ut8 selected_page; ///< for instruction indexing. + bool skip; +} PicMidrangeCPUState; + +typedef struct _pic_midrange_op_args_val { + ut16 f; + ut16 k; + ut8 d; + ut8 m; + ut8 n; + ut8 b; +} PicMidrangeOpArgsVal; + +typedef struct pic_midrange_il_context_t { + RzAnalysis *analysis; + RzAnalysisOp *op; + PicMidrangeCPUState cpu; + PicMidrangeOpArgsVal args; + ut64 addr; + ut16 d; +} PicMidrangeILContext; + +typedef RzILOpEffect *(*pic_midrange_il_handler)(PicMidrangeILContext *, ut16); + +// HELPER DEFINES & TYPEDEFS + +#define IL_LIFTER(op) pic_midrange_##op##_il_lifter +#define IL_LIFTER_IMPL(op) static RzILOpEffect *pic_midrange_##op##_il_lifter( \ + RZ_NONNULL PicMidrangeILContext *ctx, ut16 instr) + +// REGISTER DECLARATIONS & DEFINITIONS +#include "pic16f_memmaps/memmaps.h" + +#define BANK_SIZE ((ut32)0x80) +#define BANK_COMMON_MAP_LOW cpu_state->selected_bank *BANK_SIZE + 0X70 +#define BANK_COMMON_MAP_HIGH cpu_state->selected_bank *BANK_SIZE + 0X7F + +#define K (ctx->args.k) +#define D (ctx->args.d) +#define F (ctx->args.f) +#define B (ctx->args.b) +#define N (ctx->args.n) +#define PC (ctx->addr) +#define VPC (U16(PC)) + +#define RW "w" +#define VRW (VARG(RW)) +#define RF pic_midrange_regname(F) +#define VRF (VARG(pic_midrange_regname(F))) +#define RWF (D ? pic_midrange_regname(F) : "w") +#define VRWF (VARG(RWF)) + +#define INS_LEN 2 + +// device to register schema map +PicMidrangeRegType *pic_midrange_device_reg_map[] = { + [PIC16F882] = pic16f882_reg_map, + [PIC16F883] = pic16f883_reg_map, + // [PIC16F884] = pic16f884_reg_map, + [PIC16F886] = pic16f886_reg_map, + // [PIC16F887] = pic16f887_reg_map, +}; + +static RzILOpPure *SLICE(RzILOpPure *x, ut8 l, ut8 r) { + return LOGAND(SHIFTR0(x, U16(l)), U16(~(-1 << (r - l + 1)))); +} + +#define SEXT(B, x, b) ((st##B)(x << (B - b)) >> (B - b)) + +static const char *RFSR(ut8 n) { + static const char *FSR_names[] = { + "FSR0", "FSR1" + }; + if (n >= RZ_ARRAY_SIZE(FSR_names)) { + return NULL; + } + return FSR_names[n]; +} + +#define VRFSR(n) VARG(RFSR(n)) + +#define BITN(x, n) IS_ZERO(LOGAND(SHIFTR0(x, U32(n)), U32(1))) +// overflow is not used in status register but just keeping this for future "maybe" use +#define CHECK_OVERFLOW(x, y, res) AND(XOR(MSB(x), MSB(res)), XOR(MSB(y), MSB(res))) +#define CHECK_CARRY(x, y, res) OR(AND(MSB(x), MSB(y)), AND(OR(MSB(x), MSB(y)), INV(MSB(res)))) +#define CHECK_BORROW(x, y, res) OR(OR(AND(INV(MSB(x)), MSB(y)), AND(INV(MSB(x)), MSB(res))), AND(MSB(x), AND(MSB(y), MSB(res)))) +#define CHECK_DIGIT_CARRY(x, y, res) OR(AND(BITN(x, 3), BITN(y, 3)), AND(OR(BITN(x, 3), BITN(y, 3)), INV(BITN(res, 3)))) +#define CHECK_DIGIT_BORROW(x, y, res) OR( \ + OR(AND(INV(BITN(x, 3)), BITN(y, 3)), AND(INV(BITN(x, 3)), BITN(res, 3))), \ + AND(BITN(x, 3), AND(BITN(y, 3), BITN(res, 3)))) + +/** + * Handle C, DC & Z flags for the previous operation. + * To be used after an arithmetic operation. + * Order of operands must be preserved for subtraction + * operations, i.e `add = false` + * + * \param x First operand + * \param y Second operand + * \param res Result of last performed operation that affected the flag. + * \param add Was this an add operation? + * + * \return \c RzILOpEffect containing set of steps to set status flags. + * */ +RzILOpEffect *pic_midrange_il_set_arithmetic_flags( + RZ_BORROW RzILOpPure *x, RZ_BORROW RzILOpPure *y, RZ_BORROW RzILOpPure *res, bool add) { + // get carry flag + RzILOpBool *cf = NULL; + RzILOpBool *dcf = NULL; + if (add) { + cf = CHECK_CARRY(x, y, res); + dcf = CHECK_DIGIT_CARRY(x, y, res); + } else { // sub + cf = CHECK_BORROW(x, y, res); + dcf = CHECK_DIGIT_BORROW(x, y, res); + } + + // get zero flag + RzILOpBool *zf = IS_ZERO(res); + + return SEQ3(SETG("c", cf), + SETG("dc", dcf), + SETG("z", zf)); +} + +#define SET_STATUS_ADD(x, y, r) pic_midrange_il_set_arithmetic_flags(x, y, r, true) +#define SET_STATUS_SUB(x, y, r) pic_midrange_il_set_arithmetic_flags(x, y, r, false) + +/** + * NOP + * Operation: No Operation. + * Operands: NONE + * Status affected : NONE + * */ +IL_LIFTER_IMPL(NOP) { + return NOP(); +} + +/** + * ADDLW. + * Operation: Add Literal To wreg + * Operands: Literal (k) + * Status affected : C, DC, Z + * */ +IL_LIFTER_IMPL(ADDLW) { + RzILOpEffect *add_op = SETG("w", ADD(VARG("w"), U16(K))); + RzILOpEffect *set_status_op = + SET_STATUS_ADD(VARL("_1"), U16(K), VARG("w")); + return SEQ3(SETL("_1", VARG("w")), + add_op, + set_status_op); +} + +/** + * ADDWF + * Operation: Add freg to wreg. + * Operands: f, d + * Status affected : C, DC, Z + * */ +IL_LIFTER_IMPL(ADDWF) { + RzILOpEffect *add_op = SETG(RWF, ADD(VARG(RW), U16(K))); + RzILOpEffect *set_status_op = + SET_STATUS_ADD(VARL("_1"), U16(K), VARG(RWF)); + return SEQ3(SETL("_1", VARG(RW)), + add_op, + set_status_op); +} + +IL_LIFTER_IMPL(ANDLW) { + // TODO: set status Z + return SETG(RW, LOGAND(VARG(RW), U16(K))); +} + +/** + * ANDWF + * Operation: Take logical AND of freg and wreg. + * Operands: f, d + * Status affected : Z + * */ +IL_LIFTER_IMPL(ANDWF) { + // TODO: set status Z + return SETG(RWF, LOGAND(VARG(RW), U16(K))); +} + +static RzILOpPure *bit_set(RzILOpPure *v, ut32 b, bool x) { + if (x) { + return LOGOR(v, U8(1 << b)); + } + return LOGAND(v, U8(~(1 << b))); +} + +static RzILOpPure *bit_set1(RzILOpPure *v, ut32 b, RzILOpBool *x) { + return ITE(x, LOGOR(v, U8(1 << b)), LOGAND(v, U8(~(1 << b)))); +} + +static RzILOpPure *bit_get(RzILOpPure *v, ut32 b) { + return NON_ZERO(LOGAND(v, U8(1 << b))); +} + +static RzILOpEffect *regbit_set(const char *reg, ut32 b, bool x) { + return SETG(reg, bit_set(VARG(reg), b, x)); +} +static RzILOpEffect *regbit_set1(const char *reg, ut32 b, RzILOpBool *x) { + return SETG(reg, bit_set1(VARG(reg), b, x)); +} + +IL_LIFTER_IMPL(BCF) { + return regbit_set(pic_midrange_regname(F), B, 0); +} + +IL_LIFTER_IMPL(BSF) { + return regbit_set(pic_midrange_regname(F), B, 1); +} + +IL_LIFTER_IMPL(BTFSC) { + return BRANCH(bit_get(VARG(pic_midrange_regname(F)), B), NOP(), JMP(U32(PC + INS_LEN * 2))); +} + +IL_LIFTER_IMPL(BTFSS) { + return BRANCH(bit_get(VARG(pic_midrange_regname(F)), B), JMP(U32(PC + INS_LEN * 2)), NOP()); +} + +IL_LIFTER_IMPL(CALL) { + return SEQ2( + SETG("tos", U16(PC + INS_LEN)), + JMP(LOGOR(U16(K), SHIFTL0(SLICE(VARG("pclath"), 3, 4), U16(11))))); +} + +IL_LIFTER_IMPL(CLRF) { + return SEQ2( + SETG(pic_midrange_regname(F), U16(0)), + SETG("z", U16(1))); +} + +IL_LIFTER_IMPL(CLR) { + return SEQ2( + SETG(RW, U16(0)), + SETG("z", U16(1))); +} + +IL_LIFTER_IMPL(CLRWDT) { + return SEQ4( + SETG("wdt", U16(0)), + SETG("wdt_prescaler_count", U16(0)), + SETG("to", U16(1)), + SETG("pd", U16(1))); +} + +IL_LIFTER_IMPL(COMF) { + return SEQ2( + SETG(RWF, NEG(VRF)), + SETG("z", IS_ZERO(VARG(RWF)))); +} + +IL_LIFTER_IMPL(DECF) { + return SEQ2( + SETG(RWF, SUB(VRF, U16(1))), + SETG("z", IS_ZERO(VARG(RWF)))); +} + +IL_LIFTER_IMPL(DECFSZ) { + return SEQ2( + SETG(RWF, SUB(VRF, U16(1))), + BRANCH(IS_ZERO(VARG(RWF)), + JMP(U16(PC + INS_LEN * 2)), + NOP())); +} + +IL_LIFTER_IMPL(GOTO) { + return JMP(LOGOR(U16(K), SHIFTL0(SLICE(VARG("pclath"), 3, 4), U16(11)))); +} + +IL_LIFTER_IMPL(INCF) { + return SEQ2( + SETG(RWF, ADD(VRF, U16(1))), + SETG("z", IS_ZERO(VARG(RWF)))); +} + +IL_LIFTER_IMPL(INCFSZ) { + return SEQ2( + SETG(RWF, ADD(VRF, U16(1))), + BRANCH(IS_ZERO(VARG(RWF)), + JMP(U16(PC + INS_LEN * 2)), + NOP())); +} + +IL_LIFTER_IMPL(IORLW) { + return SEQ2( + SETG(RW, LOGOR(VRW, U16(K))), + SETG("z", IS_ZERO(VRW))); +} + +IL_LIFTER_IMPL(IORWF) { + return SEQ2( + SETG(RWF, LOGOR(VRW, VRF)), + SETG("z", IS_ZERO(VRWF))); +} + +IL_LIFTER_IMPL(MOVLW) { + return SETG(RW, U16(K)); +} + +IL_LIFTER_IMPL(MOVF) { + return SEQ2(SETG(RWF, VRF), + SETG("z", IS_ZERO(VRWF))); +} + +IL_LIFTER_IMPL(MOVWF) { + return SETG(RF, VRW); +} + +IL_LIFTER_IMPL(OPTION) { + return SETG("option", VRW); +} + +IL_LIFTER_IMPL(RETFIE) { + return SEQ2( + SETG("tos", VPC), + SETG("gie", U16(1))); +} + +IL_LIFTER_IMPL(RETLW) { + return SEQ2( + SETG(RW, U16(K)), + JMP(VARG("tos"))); +} + +IL_LIFTER_IMPL(RETURN) { + return JMP(VARG("tos")); +} + +IL_LIFTER_IMPL(RLF) { + return SEQ3( + SETG("_c", LOGAND(SHIFTR0(VRF, U8(7)), U8(1))), + SETG(RWF, LOGOR(SHIFTL0(VRF, U8(1)), VARG("c"))), + SETG("c", VARL("_v"))); +} + +IL_LIFTER_IMPL(RRF) { + return SEQ3( + SETG("_c", LOGAND(VRF, U8(1))), + SETG(RWF, LOGOR(SHIFTR0(VRF, U8(1)), SHIFTL0(VARG("c"), U8(7)))), + SETG("c", VARL("_v"))); +} + +IL_LIFTER_IMPL(SLEEP) { + return SEQ4( + SETG("wdt", U8(0)), + SETG("wdt_prescaler_count", U8(0)), + SETG("to", U8(1)), + SETG("pd", U8(0))); +} + +IL_LIFTER_IMPL(SUBLW) { + return SEQ3( + SETL("_w", VRW), + SETG(RW, SUB(U8(K), VARL("_w"))), + SET_STATUS_SUB(VARL("_w"), U8(K), VRW)); +} + +IL_LIFTER_IMPL(SUBWF) { + return SEQ3( + SETL("_res", SUB(VRF, VRW)), + SET_STATUS_SUB(VRF, VRW, VARL("_res")), + SETG(RWF, VARL("_res"))); +} + +IL_LIFTER_IMPL(SWAPF) { + return SETG(RWF, APPEND(UNSIGNED(4, VRF), UNSIGNED(4, SHIFTR0(VRF, U8(4))))); +} + +IL_LIFTER_IMPL(TRIS) { + // TODO: TRIS register f; + return SETG("tris", VRW); +} + +/** + * XORLW. + * Operation: Take logical XOR between literal and wreg + * Operands: Literal (k) + * Status affected : Z + * */ +IL_LIFTER_IMPL(XORLW) { + return SEQ2( + SETG(RW, LOGXOR(VRW, U8(K))), + SETG("z", IS_ZERO(VRW))); +} + +/** + * ANDWF + * Operation: Take logical AND of freg and wreg. + * Operands: f, d + * Status affected : Z + * */ +IL_LIFTER_IMPL(XORWF) { + return SEQ2( + SETG(RWF, LOGXOR(VRW, VRF)), + SETG("z", IS_ZERO(VRWF))); +} + +// 14-bit enhanced PIC additional instructions + +RzILOpEffect *reset() { + return NOP(); +} + +RzILOpEffect *setZ(RzILOpPure *x) { + return SETG("z", IS_ZERO(x)); +} + +IL_LIFTER_IMPL(RESET) { + return SEQ2( + reset(), + JMP(U16(0))); +} +IL_LIFTER_IMPL(CALLW) { + return SEQ2( + SETG("tos", U16(PC + INS_LEN)), + JMP(LOGOR(U16(K), UNSIGNED(16, VRW)))); +} +IL_LIFTER_IMPL(BRW) { + return JMP(ADD(UNSIGNED(16, VRW), SHIFTR0(U16(PC + INS_LEN), U16(1)))); +} +IL_LIFTER_IMPL(MOVIW_1) { + switch (ctx->d & 0b11) { + case 0x0: return SEQ3( + SETG(RFSR(N), ADD(VRFSR(N), U8(1))), + SETG(RW, VRFSR(N)), + setZ(VRW)); + case 0x1: return SEQ3( + SETG(RFSR(N), SUB(VRFSR(N), U8(1))), + SETG(RW, VRFSR(N)), + setZ(VRW)); + case 0x2: return SEQ3( + SETG(RW, VRFSR(N)), + SETG(RFSR(N), ADD(VRFSR(N), U8(1))), + setZ(VRW)); + case 0x3: return SEQ3( + SETG(RW, VRFSR(N)), + SETG(RFSR(N), SUB(VRFSR(N), U8(1))), + setZ(VRW)); + default: break; + } + return NULL; +} +IL_LIFTER_IMPL(MOVIW_2) { + return SEQ2( + SETG(RW, LOAD(ADD(VRFSR(N), S8(SEXT(8, K, 6))))), + setZ(VRW)); +} + +IL_LIFTER_IMPL(MOVWI_1) { + return SETG(RFSR(N), VRW); +} +IL_LIFTER_IMPL(MOVWI_2) { + return STORE(ADD(VRFSR(N), S8(SEXT(8, K, 6))), VRW); +} + +IL_LIFTER_IMPL(MOVLB) { + // imm5? + return SETG("bsr", U8(K)); +} +IL_LIFTER_IMPL(MOVLP) { + // imm7? + return SETG("pclath", U8(K)); +} + +IL_LIFTER_IMPL(LSLF) { + return SEQ3( + SETG("c", MSB(VRF)), + SETG(RWF, SHIFTL0(VRF, U8(1))), + setZ(VRWF)); +} +IL_LIFTER_IMPL(LSRF) { + return SEQ3( + SETG("c", LSB(VRF)), + SETG(RWF, SHIFTR0(VRF, U8(1))), + setZ(VRWF)); +} +IL_LIFTER_IMPL(ASRF) { + return SEQ3( + SETG("c", LSB(VRF)), + SETG(RWF, SHIFTRA(VRF, U8(1))), + setZ(VRWF)); +} +IL_LIFTER_IMPL(SUBWFB) { + return SEQ3( + SETG("_res", ADD(SUB(VRF, VRW), VARG("c"))), + SET_STATUS_SUB(VRF, VRW, VARL("_res")), + SETG(RWF, VARL("_res"))); +} +IL_LIFTER_IMPL(ADDWFC) { + return SEQ3( + SETG("_res", ADD(ADD(VRF, VRW), VARG("c"))), + SET_STATUS_ADD(VRF, VRW, VARL("_res")), + SETG(RWF, VARL("_res"))); +} +IL_LIFTER_IMPL(ADDFSR) { + return SETG(RFSR(N), ADD(VRFSR(N), S8(SEXT(8, K, 6)))); +} +IL_LIFTER_IMPL(BRA) { + return JMP(U16(PC + SEXT(16, K, 9))); +} + +#undef K +#undef D +#undef F +#undef B +#undef N +#undef PC +#undef VPC + +#undef RW +#undef VRW +#undef RF +#undef VRF +#undef RWF +#undef VRWF + +/** + * Create new Mid-Range device CPU state. + * + * */ +static bool rz_pic_midrange_cpu_state_setup( + PicMidrangeCPUState *state, + PicMidrangeDeviceType device_type) { + rz_return_val_if_fail(state, NULL); + if (device_type >= PIC_MIDRANGE_SUPPORTED_DEVICE_NUM) { + RZ_LOG_ERROR("RzIL : Invalid PIC Mid-Range device type provided"); + return false; + } + + state->device_type = device_type; + state->selected_bank = 0; // initially bank is 0 + state->selected_page = 0; // initially page is 0 + return true; +} + +/** + * \brief Returns IL VM config for given PIC Mid-Range device type. + * + * \param analysis \c RzAnalysis instance. + * \param device_type Device type in PIC16F family. + * + * \return valid ptr to RzAnalysisILConfig on success, NULL otherwise. + * */ +static RzAnalysisILConfig *pic_midrange_il_config( + RZ_NONNULL RzAnalysis *analysis) { + RzAnalysisILConfig *cfg = rz_analysis_il_config_new(16, false, 16); + cfg->reg_bindings = pic_midrange_regnames; + return cfg; +} \ No newline at end of file diff --git a/librz/arch/isa/pic/pic_pic18.c b/librz/arch/isa/pic/pic_pic18.c index 7c19fe4872d..d4927c886cd 100644 --- a/librz/arch/isa/pic/pic_pic18.c +++ b/librz/arch/isa/pic/pic_pic18.c @@ -9,213 +9,531 @@ // PIC18CXXX instruction set // instruction classification according to the argument types -#define NO_ARG 0 -#define DAF_T 1 -#define F32_T 2 -#define BAF_T 3 -#define K_T 4 -#define N_T 5 -#define CALL_T 6 -#define NEX_T 7 -#define AF_T 8 -#define GOTO_T 9 -#define SHK_T 10 -#define S_T 11 -#define LFSR_T 12 static char *fsr[] = { "fsr0", "fsr1", "fsr2", "reserved" }; -static struct { +typedef struct { + Pic18Opcode code; ut16 opmin; ut16 opmax; char *name; - ut8 optype; + Pic18ArgsKind optype; // and some magical hocus pocus ;) -} ops[] = { - { 0xf000, 0xffff, "nop", NO_ARG }, - { 0xef00, 0xefff, "goto", GOTO_T }, - { 0xee00, 0xee3f, "lfsr", LFSR_T }, - { 0xec00, 0xedff, "call", CALL_T }, - { 0xe700, 0xe7ff, "bnn", N_T }, - { 0xe600, 0xe6ff, "bn", N_T }, - { 0xe500, 0xe5ff, "bnov", N_T }, - { 0xe400, 0xe4ff, "bov", N_T }, - { 0xe300, 0xe3ff, "bnc", N_T }, - { 0xe200, 0xe2ff, "bc", N_T }, - { 0xe100, 0xe1ff, "bnz", N_T }, - { 0xe000, 0xe0ff, "bz", N_T }, - { 0xd800, 0xdfff, "rcall", NEX_T }, - { 0xd000, 0xd7ff, "bra", NEX_T }, - { 0xc000, 0xcfff, "movff", F32_T }, - { 0xb000, 0xbfff, "btfsc", BAF_T }, - { 0xa000, 0xafff, "btfss", BAF_T }, - { 0x9000, 0x9fff, "bcf", BAF_T }, - { 0x8000, 0x8fff, "bsf", BAF_T }, - { 0x7000, 0x7fff, "btg", BAF_T }, - { 0x6e00, 0x6fff, "movwf", AF_T }, - { 0x6c00, 0x6dff, "negf", AF_T }, - { 0x6a00, 0x6bff, "clrf", AF_T }, - { 0x6800, 0x69ff, "setf", AF_T }, - { 0x6600, 0x67ff, "tstfsz", AF_T }, - { 0x6400, 0x65ff, "cpfsgt", AF_T }, - { 0x6200, 0x63ff, "cpfseq", AF_T }, - { 0x6000, 0x61ff, "cpfslt", AF_T }, - { 0x5c00, 0x5fff, "subwf", DAF_T }, - { 0x5800, 0x5bff, "subwfb", DAF_T }, - { 0x5400, 0x57ff, "subfwb", DAF_T }, - { 0x5000, 0x53ff, "movf", DAF_T }, - { 0x4c00, 0x4fff, "dcfsnz", DAF_T }, - { 0x4800, 0x4bff, "infsnz", DAF_T }, - { 0x4400, 0x47ff, "rlncf", DAF_T }, - { 0x4000, 0x43ff, "rrncf", DAF_T }, - { 0x3c00, 0x3fff, "incfsz", DAF_T }, - { 0x3800, 0x3bff, "swapf", DAF_T }, - { 0x3400, 0x37ff, "rlcf", DAF_T }, - { 0x3000, 0x33ff, "rrcf", DAF_T }, - { 0x2c00, 0x2fff, "decfsz", DAF_T }, - { 0x2800, 0x2bff, "incf", DAF_T }, - { 0x2400, 0x27ff, "addwf", DAF_T }, - { 0x2000, 0x23ff, "addwfc", DAF_T }, - { 0x1c00, 0x1fff, "comf", DAF_T }, - { 0x1800, 0x1bff, "xorwf", DAF_T }, - { 0x1400, 0x17ff, "andwf", DAF_T }, - { 0x1000, 0x13ff, "iorwf", DAF_T }, - { 0xf00, 0xfff, "addlw", K_T }, - { 0xe00, 0xeff, "movlw", K_T }, - { 0xd00, 0xdff, "mullw", K_T }, - { 0xc00, 0xcff, "retlw", K_T }, - { 0xb00, 0xbff, "andlw", K_T }, - { 0xa00, 0xaff, "xorlw", K_T }, - { 0x900, 0x9ff, "iorlw", K_T }, - { 0x800, 0x8ff, "sublw", K_T }, - { 0x400, 0x7ff, "decf", DAF_T }, - { 0x200, 0x3ff, "mulwf", AF_T }, - { 0x100, 0x10f, "movlb", SHK_T }, - { 0xff, 0xff, "reset", NO_ARG }, - { 0x12, 0x13, "return", S_T }, - { 0x10, 0x11, "retfie", S_T }, - { 0xf, 0xf, "tblwt+*", NO_ARG }, - { 0xe, 0xe, "tblwt*-", NO_ARG }, - { 0xd, 0xd, "tblwt*+", NO_ARG }, - { 0xc, 0xc, "tblwt*", NO_ARG }, - { 0xb, 0xb, "tblrd+*", NO_ARG }, - { 0xa, 0xa, "tblrd*-", NO_ARG }, - { 0x9, 0x9, "tblrd*+", NO_ARG }, - { 0x8, 0x8, "tblrd*", NO_ARG }, - { 0x7, 0x7, "daw", NO_ARG }, - { 0x6, 0x6, "pop", NO_ARG }, - { 0x5, 0x5, "push", NO_ARG }, - { 0x4, 0x4, "clrwdt", NO_ARG }, - { 0x3, 0x3, "sleep", NO_ARG }, - { 0x0, 0x0, "nop", NO_ARG }, - { 0x0, 0xffff, "invalid", NO_ARG }, +} Pic18OpDesc; + +static const Pic18OpDesc ops[] = { + { PIC18_OPCODE_NOP, 0xf000, 0xffff, "nop", NO_ARG }, + { PIC18_OPCODE_GOTO, 0xef00, 0xefff, "goto", K20_T }, + { PIC18_OPCODE_LFSR, 0xee00, 0xee3f, "lfsr", FK_T }, + { PIC18_OPCODE_CALL, 0xec00, 0xedff, "call", K20S_T }, + { PIC18_OPCODE_BNN, 0xe700, 0xe7ff, "bnn", N8_T }, + { PIC18_OPCODE_BN, 0xe600, 0xe6ff, "bn", N8_T }, + { PIC18_OPCODE_BNOV, 0xe500, 0xe5ff, "bnov", N8_T }, + { PIC18_OPCODE_BOV, 0xe400, 0xe4ff, "bov", N8_T }, + { PIC18_OPCODE_BNC, 0xe300, 0xe3ff, "bnc", N8_T }, + { PIC18_OPCODE_BC, 0xe200, 0xe2ff, "bc", N8_T }, + { PIC18_OPCODE_BNZ, 0xe100, 0xe1ff, "bnz", N8_T }, + { PIC18_OPCODE_BZ, 0xe000, 0xe0ff, "bz", N8_T }, + { PIC18_OPCODE_RCALL, 0xd800, 0xdfff, "rcall", N11_T }, + { PIC18_OPCODE_BRA, 0xd000, 0xd7ff, "bra", N11_T }, + { PIC18_OPCODE_MOVFF, 0xc000, 0xcfff, "movff", SD_T }, + { PIC18_OPCODE_BTFSC, 0xb000, 0xbfff, "btfsc", FBA_T }, + { PIC18_OPCODE_BTFSS, 0xa000, 0xafff, "btfss", FBA_T }, + { PIC18_OPCODE_BCF, 0x9000, 0x9fff, "bcf", FBA_T }, + { PIC18_OPCODE_BSF, 0x8000, 0x8fff, "bsf", FBA_T }, + { PIC18_OPCODE_BTG, 0x7000, 0x7fff, "btg", FBA_T }, + { PIC18_OPCODE_MOVWF, 0x6e00, 0x6fff, "movwf", FA_T }, + { PIC18_OPCODE_NEGF, 0x6c00, 0x6dff, "negf", FA_T }, + { PIC18_OPCODE_CLRF, 0x6a00, 0x6bff, "clrf", FA_T }, + { PIC18_OPCODE_SETF, 0x6800, 0x69ff, "setf", FA_T }, + { PIC18_OPCODE_TSTFSZ, 0x6600, 0x67ff, "tstfsz", FA_T }, + { PIC18_OPCODE_CPFSGT, 0x6400, 0x65ff, "cpfsgt", FA_T }, + { PIC18_OPCODE_CPFSEQ, 0x6200, 0x63ff, "cpfseq", FA_T }, + { PIC18_OPCODE_CPFSLT, 0x6000, 0x61ff, "cpfslt", FA_T }, + { PIC18_OPCODE_SUBWF, 0x5c00, 0x5fff, "subwf", FDA_T }, + { PIC18_OPCODE_SUBWFB, 0x5800, 0x5bff, "subwfb", FDA_T }, + { PIC18_OPCODE_SUBFWB, 0x5400, 0x57ff, "subfwb", FDA_T }, + { PIC18_OPCODE_MOVF, 0x5000, 0x53ff, "movf", FDA_T }, + { PIC18_OPCODE_DCFSNZ, 0x4c00, 0x4fff, "dcfsnz", FDA_T }, + { PIC18_OPCODE_INFSNZ, 0x4800, 0x4bff, "infsnz", FDA_T }, + { PIC18_OPCODE_RLNCF, 0x4400, 0x47ff, "rlncf", FDA_T }, + { PIC18_OPCODE_RRNCF, 0x4000, 0x43ff, "rrncf", FDA_T }, + { PIC18_OPCODE_INCFSZ, 0x3c00, 0x3fff, "incfsz", FDA_T }, + { PIC18_OPCODE_SWAPF, 0x3800, 0x3bff, "swapf", FDA_T }, + { PIC18_OPCODE_RLCF, 0x3400, 0x37ff, "rlcf", FDA_T }, + { PIC18_OPCODE_RRCF, 0x3000, 0x33ff, "rrcf", FDA_T }, + { PIC18_OPCODE_DECFSZ, 0x2c00, 0x2fff, "decfsz", FDA_T }, + { PIC18_OPCODE_INCF, 0x2800, 0x2bff, "incf", FDA_T }, + { PIC18_OPCODE_ADDWF, 0x2400, 0x27ff, "addwf", FDA_T }, + { PIC18_OPCODE_ADDWFC, 0x2000, 0x23ff, "addwfc", FDA_T }, + { PIC18_OPCODE_COMF, 0x1c00, 0x1fff, "comf", FDA_T }, + { PIC18_OPCODE_XORWF, 0x1800, 0x1bff, "xorwf", FDA_T }, + { PIC18_OPCODE_ANDWF, 0x1400, 0x17ff, "andwf", FDA_T }, + { PIC18_OPCODE_IORWF, 0x1000, 0x13ff, "iorwf", FDA_T }, + { PIC18_OPCODE_ADDLW, 0xf00, 0xfff, "addlw", K8_T }, + { PIC18_OPCODE_MOVLW, 0xe00, 0xeff, "movlw", K8_T }, + { PIC18_OPCODE_MULLW, 0xd00, 0xdff, "mullw", K8_T }, + { PIC18_OPCODE_RETLW, 0xc00, 0xcff, "retlw", K8_T }, + { PIC18_OPCODE_ANDLW, 0xb00, 0xbff, "andlw", K8_T }, + { PIC18_OPCODE_XORLW, 0xa00, 0xaff, "xorlw", K8_T }, + { PIC18_OPCODE_IORLW, 0x900, 0x9ff, "iorlw", K8_T }, + { PIC18_OPCODE_SUBLW, 0x800, 0x8ff, "sublw", K8_T }, + { PIC18_OPCODE_DECF, 0x400, 0x7ff, "decf", FDA_T }, + { PIC18_OPCODE_MULWF, 0x200, 0x3ff, "mulwf", FA_T }, + { PIC18_OPCODE_MOVLB, 0x100, 0x10f, "movlb", K4_T }, + { PIC18_OPCODE_RESET, 0xff, 0xff, "reset", NO_ARG }, + { PIC18_OPCODE_RETURN, 0x12, 0x13, "return", S_T }, + { PIC18_OPCODE_RETFIE, 0x10, 0x11, "retfie", S_T }, + { PIC18_OPCODE_TBLWTis, 0xf, 0xf, "tblwt+*", NO_ARG }, + { PIC18_OPCODE_TBLWTMsd, 0xe, 0xe, "tblwt*-", NO_ARG }, + { PIC18_OPCODE_TBLWTMsi, 0xd, 0xd, "tblwt*+", NO_ARG }, + { PIC18_OPCODE_TBLWTMs, 0xc, 0xc, "tblwt*", NO_ARG }, + { PIC18_OPCODE_TBLRDis, 0xb, 0xb, "tblrd+*", NO_ARG }, + { PIC18_OPCODE_TBLRDsd, 0xa, 0xa, "tblrd*-", NO_ARG }, + { PIC18_OPCODE_TBLRDsi, 0x9, 0x9, "tblrd*+", NO_ARG }, + { PIC18_OPCODE_TBLRDs, 0x8, 0x8, "tblrd*", NO_ARG }, + { PIC18_OPCODE_DAW, 0x7, 0x7, "daw", NO_ARG }, + { PIC18_OPCODE_POP, 0x6, 0x6, "pop", NO_ARG }, + { PIC18_OPCODE_PUSH, 0x5, 0x5, "push", NO_ARG }, + { PIC18_OPCODE_CLRWDT, 0x4, 0x4, "clrwdt", NO_ARG }, + { PIC18_OPCODE_SLEEP, 0x3, 0x3, "sleep", NO_ARG }, + { PIC18_OPCODE_NOP, 0x0, 0x0, "nop", NO_ARG }, }; -int pic_pic18_disassemble(RzAsmOp *op, const ut8 *b, int blen) { - int i; - if (blen < 2) { // well noone loves reading bitstream of size zero or 1 !! - rz_asm_op_set_asm(op, "invalid"); - op->size = blen; - return -1; +static const char *pic18_SFRs[] = { + [0xFFF - 0xF80] = "tosu", + [0xFFE - 0xF80] = "tosh", + [0xFFD - 0xF80] = "tosl", + [0xFFC - 0xF80] = "stkptr", + [0xFFB - 0xF80] = "pclatu", + [0xFFA - 0xF80] = "pclath", + [0xFF9 - 0xF80] = "pcl", + [0xFF8 - 0xF80] = "tblptru", + [0xFF7 - 0xF80] = "tblptrh", + [0xFF6 - 0xF80] = "tblptrl", + [0xFF5 - 0xF80] = "tablat", + [0xFF4 - 0xF80] = "prodh", + [0xFF3 - 0xF80] = "prodl", + [0xFF2 - 0xF80] = "intcon", + [0xFF1 - 0xF80] = "intcon2", + [0xFF0 - 0xF80] = "intcon3", + [0xFEF - 0xF80] = "indf0", + [0xFEE - 0xF80] = "postinc0", + [0xFED - 0xF80] = "postdec0", + [0xFEC - 0xF80] = "preinc0", + [0xFEB - 0xF80] = "plusw0", + [0xFEA - 0xF80] = "fsr0h", + [0xFE9 - 0xF80] = "fsr0l", + [0xFE8 - 0xF80] = "wreg", + [0xFE7 - 0xF80] = "indf1", + [0xFE6 - 0xF80] = "postinc1", + [0xFE5 - 0xF80] = "postdec1", + [0xFE4 - 0xF80] = "preinc1", + [0xFE3 - 0xF80] = "plusw1", + [0xFE2 - 0xF80] = "fsr1h", + [0xFE1 - 0xF80] = "fsr1l", + [0xFE0 - 0xF80] = "bsr", + [0xFDF - 0xF80] = "indf2", + [0xFDE - 0xF80] = "postinc2", + [0xFDD - 0xF80] = "postdec2", + [0xFDC - 0xF80] = "preinc2", + [0xFDB - 0xF80] = "plusw2", + [0xFDA - 0xF80] = "fsr2h", + [0xFD9 - 0xF80] = "fsr2l", + [0xFD8 - 0xF80] = "status", + [0xFD7 - 0xF80] = "tmr0h", + [0xFD6 - 0xF80] = "tmr0l", + [0xFD5 - 0xF80] = "t0con", + [0xFD4 - 0xF80] = "—", + [0xFD3 - 0xF80] = "osccon", + [0xFD2 - 0xF80] = "lvdcon", + [0xFD1 - 0xF80] = "wdtcon", + [0xFD0 - 0xF80] = "rcon", + [0xFCF - 0xF80] = "tmr1h", + [0xFCE - 0xF80] = "tmr1l", + [0xFCD - 0xF80] = "t1con", + [0xFCC - 0xF80] = "tmr2", + [0xFCB - 0xF80] = "pr2", + [0xFCA - 0xF80] = "t2con", + [0xFC9 - 0xF80] = "sspbuf", + [0xFC8 - 0xF80] = "sspadd", + [0xFC7 - 0xF80] = "sspstat", + [0xFC6 - 0xF80] = "sspcon1", + [0xFC5 - 0xF80] = "sspcon2", + [0xFC4 - 0xF80] = "adresh", + [0xFC3 - 0xF80] = "adresl", + [0xFC2 - 0xF80] = "adcon0", + [0xFC1 - 0xF80] = "adcon1", + [0xFC0 - 0xF80] = "—", + [0xFBF - 0xF80] = "ccpr1h", + [0xFBE - 0xF80] = "ccpr1l", + [0xFBD - 0xF80] = "ccp1con", + [0xFBC - 0xF80] = "ccpr2h", + [0xFBB - 0xF80] = "ccpr2l", + [0xFBA - 0xF80] = "ccp2con", + [0xFB9 - 0xF80] = "—", + [0xFB8 - 0xF80] = "—", + [0xFB7 - 0xF80] = "—", + [0xFB6 - 0xF80] = "—", + [0xFB5 - 0xF80] = "—", + [0xFB4 - 0xF80] = "—", + [0xFB3 - 0xF80] = "tmr3h", + [0xFB2 - 0xF80] = "tmr3l", + [0xFB1 - 0xF80] = "t3con", + [0xFB0 - 0xF80] = "—", + [0xFAF - 0xF80] = "spbrg", + [0xFAE - 0xF80] = "rcreg", + [0xFAD - 0xF80] = "txreg", + [0xFAC - 0xF80] = "txsta", + [0xFAB - 0xF80] = "rcsta", + [0xFAA - 0xF80] = "—", + [0xFA9 - 0xF80] = "—", + [0xFA8 - 0xF80] = "—", + [0xFA7 - 0xF80] = "—", + [0xFA6 - 0xF80] = "—", + [0xFA5 - 0xF80] = "—", + [0xFA4 - 0xF80] = "—", + [0xFA3 - 0xF80] = "—", + [0xFA2 - 0xF80] = "ipr2", + [0xFA1 - 0xF80] = "pir2", + [0xFA0 - 0xF80] = "pie2", + [0xF9F - 0xF80] = "ipr1", + [0xF9E - 0xF80] = "pir1", + [0xF9D - 0xF80] = "pie1", + [0xF9C - 0xF80] = "—", + [0xF9B - 0xF80] = "—", + [0xF9A - 0xF80] = "—", + [0xF99 - 0xF80] = "—", + [0xF98 - 0xF80] = "—", + [0xF97 - 0xF80] = "—", + [0xF96 - 0xF80] = "trise", + [0xF95 - 0xF80] = "trisd", + [0xF94 - 0xF80] = "trisc", + [0xF93 - 0xF80] = "trisb", + [0xF92 - 0xF80] = "trisa", + [0xF91 - 0xF80] = "—", + [0xF90 - 0xF80] = "—", + [0xF8F - 0xF80] = "—", + [0xF8E - 0xF80] = "—", + [0xF8D - 0xF80] = "late", + [0xF8C - 0xF80] = "latd", + [0xF8B - 0xF80] = "latc", + [0xF8A - 0xF80] = "latb", + [0xF89 - 0xF80] = "lata", + [0xF88 - 0xF80] = "—", + [0xF87 - 0xF80] = "—", + [0xF86 - 0xF80] = "—", + [0xF85 - 0xF80] = "—", + [0xF84 - 0xF80] = "porte", + [0xF83 - 0xF80] = "portd", + [0xF82 - 0xF80] = "portc", + [0xF81 - 0xF80] = "portb", + [0xF80 - 0xF80] = "porta", + "_sram", + "_stack" +}; + +static const char *pic18_GPRs[] = { + "0x00", + "0x01", + "0x02", + "0x03", + "0x04", + "0x05", + "0x06", + "0x07", + "0x08", + "0x09", + "0x0a", + "0x0b", + "0x0c", + "0x0d", + "0x0e", + "0x0f", + "0x10", + "0x11", + "0x12", + "0x13", + "0x14", + "0x15", + "0x16", + "0x17", + "0x18", + "0x19", + "0x1a", + "0x1b", + "0x1c", + "0x1d", + "0x1e", + "0x1f", + "0x20", + "0x21", + "0x22", + "0x23", + "0x24", + "0x25", + "0x26", + "0x27", + "0x28", + "0x29", + "0x2a", + "0x2b", + "0x2c", + "0x2d", + "0x2e", + "0x2f", + "0x30", + "0x31", + "0x32", + "0x33", + "0x34", + "0x35", + "0x36", + "0x37", + "0x38", + "0x39", + "0x3a", + "0x3b", + "0x3c", + "0x3d", + "0x3e", + "0x3f", + "0x40", + "0x41", + "0x42", + "0x43", + "0x44", + "0x45", + "0x46", + "0x47", + "0x48", + "0x49", + "0x4a", + "0x4b", + "0x4c", + "0x4d", + "0x4e", + "0x4f", + "0x50", + "0x51", + "0x52", + "0x53", + "0x54", + "0x55", + "0x56", + "0x57", + "0x58", + "0x59", + "0x5a", + "0x5b", + "0x5c", + "0x5d", + "0x5e", + "0x5f", + "0x60", + "0x61", + "0x62", + "0x63", + "0x64", + "0x65", + "0x66", + "0x67", + "0x68", + "0x69", + "0x6a", + "0x6b", + "0x6c", + "0x6d", + "0x6e", + "0x6f", + "0x70", + "0x71", + "0x72", + "0x73", + "0x74", + "0x75", + "0x76", + "0x77", + "0x78", + "0x79", + "0x7a", + "0x7b", + "0x7c", + "0x7d", + "0x7e", + "0x7f" +}; + +const char *pic18_regname(size_t index) { + if (index > 0xf00 && index <= 0xfff) { + return pic18_regname(index % 0x100); + } + if (index <= 0xff && index >= 0x80) { + return pic18_SFRs[index - 0x80]; + } + if (index < 0x80) { + return pic18_GPRs[index]; } - ut16 instr = rz_read_le16(b); // instruction - // if still redundant code is reported think of this of instr=0x + rz_warn_if_reached(); + return NULL; +} + +static const char *status_bits[] = { + "c", + "dc", + "z", + "ov", + "n" +}; - for (i = 0; ops[i].opmin != (ops[i].opmin & instr) || ops[i].opmax != (ops[i].opmax | instr); i++) { - ; +ut8 pic18_status(const char *name) { + for (int i = 0; i < RZ_ARRAY_SIZE(status_bits); ++i) { + if (RZ_STR_EQ(name, status_bits[i])) { + return i; + } } - if (ops[i].opmin == 0 && ops[i].opmax == 0xffff) { - rz_asm_op_set_asm(op, ops[i].name); - op->size = 2; - return -1; + return 0xff; +} + +bool pic18_disasm_op(Pic18Op *op, ut64 addr, const ut8 *buff, ut64 len) { +#define check_len(x) \ + if (len < x) { \ + op->code = PIC18_OPCODE_INVALID; \ + return false; \ + } \ + op->size = x; + + op->addr = addr; + check_len(2); + ut16 word = rz_read_le16(buff); + Pic18OpDesc *desc = (Pic18OpDesc *)ops; + for (; desc->opmin != (desc->opmin & word) || + desc->opmax != (desc->opmax | word); + desc++) { } - op->size = 2; - switch (ops[i].optype) { - case NO_ARG: - rz_asm_op_set_asm(op, ops[i].name); + op->code = desc->code; + op->mnemonic = desc->name; + op->args_kind = desc->optype; + + switch (op->args_kind) { + case N8_T: + op->n = word & 0xff; break; - case N_T: - case K_T: - rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0xff); + case K8_T: + op->k = word & 0xff; break; - case DAF_T: - rz_asm_op_setf_asm(op, "%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 1, (instr >> 8) & 1); + case FDA_T: + op->f = word & 0xff; + op->d = (word >> 9) & 1; + op->a = (word >> 8) & 1; break; - case AF_T: - rz_asm_op_setf_asm(op, "%s 0x%x, %d", ops[i].name, instr & 0xff, (instr >> 8) & 1); + case FA_T: + op->f = word & 0xff; + op->a = (word >> 8) & 1; break; - case BAF_T: - rz_asm_op_setf_asm(op, "%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 0x7, (instr >> 8) & 0x1); + case FBA_T: + op->f = word & 0xff; + op->a = (word >> 8) & 1; + op->b = (word >> 9) & 0x7; break; - case NEX_T: - rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0x7ff); + case N11_T: + op->n = word & 0x7ff; break; - case CALL_T: - if (blen < 4) { - return -1; - } - op->size = 4; - { - ut32 dword_instr = rz_read_le32(b); - // I dont even know how the bits are arranged but it works !!! - //`the wierdness of little endianess` - if (dword_instr >> 28 != 0xf) { - return -1; - } - rz_asm_op_setf_asm(op, "%s 0x%x, %d", ops[i].name, - (dword_instr & 0xff) | (dword_instr >> 8 & 0xfff00), (dword_instr >> 8) & 0x1); - } + case K4_T: + op->k = word & 0xf; break; - case GOTO_T: - if (blen < 4) { - return -1; - } - { - op->size = 4; - ut32 dword_instr = rz_read_le32(b); - if (dword_instr >> 28 != 0xf) { - return -1; - } - rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, - ((dword_instr & 0xff) | ((dword_instr & 0xfff0000) >> 8)) * 2); - } + case S_T: + op->s = word & 0x1; break; - case F32_T: - if (blen < 4) { - return -1; - } - op->size = 4; - { - ut32 dword_instr = rz_read_le32(b); - if (dword_instr >> 28 != 0xf) { - return -1; - } - rz_asm_op_setf_asm(op, "%s 0x%x, 0x%x", ops[i].name, - dword_instr & 0xfff, (dword_instr >> 16) & 0xfff); - } +#define check_dword_inst \ + check_len(4); \ + ut32 dword = rz_read_le32(buff); \ + if (dword >> 28 != 0xf) { \ + return false; \ + } + + case K20S_T: { + check_dword_inst; + op->k = (dword & 0xff) | ((dword >> 16 & 0xfff) << 8); + op->s = (dword >> 8) & 0x1; break; - case SHK_T: - rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0xf); + } + case K20_T: { + check_dword_inst; + op->k = (dword & 0xff) | ((dword >> 16 & 0xfff) << 8); break; - case S_T: - rz_asm_op_setf_asm(op, "%s %d", ops[i].name, instr & 0x1); + } + case SD_T: { + check_dword_inst; + op->s = dword & 0xfff; + op->d = (dword >> 16) & 0xfff; break; - case LFSR_T: { - if (blen < 4) { - return -1; - } - op->size = 4; - ut32 dword_instr = rz_read_le32(b); - if (dword_instr >> 28 != 0xf) { - return -1; - } - ut8 reg_n = (dword_instr >> 4) & 0x3; - rz_asm_op_setf_asm(op, "%s %s, %d", ops[i].name, fsr[reg_n], - (dword_instr & 0xf) << 8 | ((dword_instr >> 16) & 0xff)); + } + case FK_T: { + check_dword_inst; + op->f = (dword >> 4) & 0x3; + op->k = (dword & 0xf) << 8 | ((dword >> 16) & 0xff); break; } default: - rz_asm_op_set_asm(op, "unknown args"); - }; - return op->size; + break; + } + + switch (op->args_kind) { + case NO_ARG: + default: + break; + case N8_T: + case N11_T: + rz_strf(op->operands, "0x%x", op->n); + break; + case K4_T: + case K8_T: + rz_strf(op->operands, "0x%x", op->k); + break; + case K20_T: + rz_strf(op->operands, "0x%x", op->k << 1); + break; + case FDA_T: + rz_strf(op->operands, "%s, %d, %d", pic18_regname(op->f), op->d, op->a); + break; + case FA_T: + rz_strf(op->operands, "%s, %d", pic18_regname(op->f), op->a); + break; + case FBA_T: + rz_strf(op->operands, "%s, %d, %d", pic18_regname(op->f), op->b, op->a); + break; + case K20S_T: + rz_strf(op->operands, "0x%x, %d", op->k << 1, op->s); + break; + case SD_T: + rz_strf(op->operands, "%s, %s", pic18_regname(op->s), pic18_regname(op->d)); + break; + case S_T: + rz_strf(op->operands, "%d", op->s); + break; + case FK_T: { + rz_strf(op->operands, "%s, %d", fsr[op->f], op->k); + break; + } + } + + return true; +} + +int pic_pic18_disassemble(RzAsm *a, RzAsmOp *asm_op, const ut8 *b, int blen) { + asm_op->size = 2; + Pic18Op op = { 0 }; + if (!pic18_disasm_op(&op, a->pc, b, blen) || + op.code == PIC18_OPCODE_INVALID) { + rz_asm_op_set_asm(asm_op, "invalid"); + return -1; + } + asm_op->size = op.size; + if (RZ_STR_ISEMPTY(op.operands)) { + rz_asm_op_set_asm(asm_op, op.mnemonic); + } else { + rz_asm_op_setf_asm(asm_op, "%s %s", op.mnemonic, op.operands); + } + return asm_op->size; } diff --git a/librz/arch/isa/pic/pic_pic18.h b/librz/arch/isa/pic/pic_pic18.h index ca17c8402b3..455339c61b6 100644 --- a/librz/arch/isa/pic/pic_pic18.h +++ b/librz/arch/isa/pic/pic_pic18.h @@ -7,6 +7,136 @@ #include -int pic_pic18_disassemble(RzAsmOp *op, const ut8 *b, int l); +typedef enum { + PIC18_OPCODE_ADDLW, + PIC18_OPCODE_ADDWF, + PIC18_OPCODE_ADDWFC, + PIC18_OPCODE_ANDWF, + PIC18_OPCODE_ANDLW, + + PIC18_OPCODE_BCF, + PIC18_OPCODE_BSF, + PIC18_OPCODE_BTG, + PIC18_OPCODE_BTFSC, + PIC18_OPCODE_BTFSS, + PIC18_OPCODE_BNN, + PIC18_OPCODE_BN, + PIC18_OPCODE_BNOV, + PIC18_OPCODE_BOV, + PIC18_OPCODE_BNC, + PIC18_OPCODE_BC, + PIC18_OPCODE_BNZ, + PIC18_OPCODE_BZ, + PIC18_OPCODE_BRA, + + PIC18_OPCODE_COMF, + PIC18_OPCODE_CALL, + PIC18_OPCODE_CLRWDT, + PIC18_OPCODE_CLRF, + PIC18_OPCODE_CPFSGT, + PIC18_OPCODE_CPFSEQ, + PIC18_OPCODE_CPFSLT, + + PIC18_OPCODE_DAW, + PIC18_OPCODE_DECF, + PIC18_OPCODE_DECFSZ, + PIC18_OPCODE_DCFSNZ, + + PIC18_OPCODE_GOTO, + + PIC18_OPCODE_IORWF, + PIC18_OPCODE_INFSNZ, + PIC18_OPCODE_INCF, + PIC18_OPCODE_INCFSZ, + PIC18_OPCODE_IORLW, + + PIC18_OPCODE_LFSR, + + PIC18_OPCODE_MOVF, + PIC18_OPCODE_MOVWF, + PIC18_OPCODE_MULWF, + PIC18_OPCODE_MOVLB, + PIC18_OPCODE_MOVFF, + PIC18_OPCODE_MOVLW, + PIC18_OPCODE_MULLW, + + PIC18_OPCODE_NOP, + PIC18_OPCODE_NEGF, + + PIC18_OPCODE_POP, + PIC18_OPCODE_PUSH, + + PIC18_OPCODE_RETURN, + PIC18_OPCODE_RETFIE, + PIC18_OPCODE_RLNCF, + PIC18_OPCODE_RRNCF, + PIC18_OPCODE_RLCF, + PIC18_OPCODE_RRCF, + PIC18_OPCODE_RCALL, + PIC18_OPCODE_RESET, + PIC18_OPCODE_RETLW, + + PIC18_OPCODE_SLEEP, + PIC18_OPCODE_SETF, + PIC18_OPCODE_SUBWF, + PIC18_OPCODE_SUBWFB, + PIC18_OPCODE_SUBFWB, + PIC18_OPCODE_SWAPF, + PIC18_OPCODE_SUBLW, + + PIC18_OPCODE_TBLRDs, + PIC18_OPCODE_TBLRDis, + PIC18_OPCODE_TBLRDsd, + PIC18_OPCODE_TBLRDsi, + PIC18_OPCODE_TBLWTMs, + PIC18_OPCODE_TBLWTis, + PIC18_OPCODE_TBLWTMsd, + PIC18_OPCODE_TBLWTMsi, + PIC18_OPCODE_TSTFSZ, + + PIC18_OPCODE_XORWF, + PIC18_OPCODE_XORLW, + + PIC18_OPCODE_INVALID +} Pic18Opcode; + +typedef enum { + NO_ARG, + FDA_T, + SD_T, + FBA_T, + K4_T, + K8_T, + K20_T, + K20S_T, + S_T, + N8_T, + N11_T, + FA_T, + FK_T, +} Pic18ArgsKind; + +typedef struct { + ut64 addr; + Pic18Opcode code; + const char *mnemonic; + char operands[32]; + ut8 size; + Pic18ArgsKind args_kind; + struct { + ut32 k : 20; + ut16 n : 11; + ut16 d; + ut16 s; + ut8 f; + ut8 a : 1; + ut8 b : 3; + }; +} Pic18Op; + +const char *pic18_regname(size_t index); +ut8 pic18_status(const char *name); +bool pic18_disasm_op(Pic18Op *op, ut64 addr, const ut8 *buff, ut64 len); +int pic_pic18_disassemble(RzAsm *a, RzAsmOp *asm_op, const ut8 *b, int l); #endif // PIC_PIC18_H diff --git a/librz/arch/p/analysis/analysis_pic.c b/librz/arch/p/analysis/analysis_pic.c index d27497ef10c..29cb314337a 100644 --- a/librz/arch/p/analysis/analysis_pic.c +++ b/librz/arch/p/analysis/analysis_pic.c @@ -5,662 +5,13 @@ #include #include -#include - -#include "pic/pic_midrange.h" - -typedef struct _pic_midrange_op_args_val { - ut16 f; - ut16 k; - ut8 d; - ut8 m; - ut8 n; - ut8 b; -} PicMidrangeOpArgsVal; - -typedef void (*pic_midrange_inst_handler_t)(RzAnalysis *analysis, RzAnalysisOp *op, - ut64 addr, - PicMidrangeOpArgsVal *args); - -typedef struct _pic_midrange_op_analysis_info { - PicMidrangeOpcode opcode; - PicMidrangeOpArgs args; - pic_midrange_inst_handler_t handler; -} PicMidrangeOpAnalInfo; - -#define INST_HANDLER(OPCODE_NAME) \ - void _inst__##OPCODE_NAME(RzAnalysis *analysis, RzAnalysisOp *op, \ - ut64 addr, \ - PicMidrangeOpArgsVal *args) -#define INST_DECL(NAME, ARGS) \ - { \ - PIC_MIDRANGE_OPCODE_##NAME, PIC_MIDRANGE_OP_ARGS_##ARGS, \ - _inst__##NAME \ - } - -#define e(frag) rz_strbuf_append(&op->esil, frag) -#define ef(frag, ...) rz_strbuf_appendf(&op->esil, frag, __VA_ARGS__) - -#define PIC_MIDRANGE_ESIL_SRAM_START (1 << 16) -#define PIC_MIDRANGE_ESIL_CSTACK_TOP ((1 << 16) + (1 << 12)) - -#define PIC_MIDRANGE_ESIL_BSR_ADDR "bsr,0x80,*,0x%x,+,_sram,+" - -#define PIC_MIDRANGE_ESIL_OPTION_ADDR "0x95,_sram,+" - -#define PIC_MIDRANGE_ESIL_UPDATE_FLAGS \ - "$z,z,:=," \ - "7,$c,c,:=," \ - "4,$c,dc,:=," - -#define PIC_MIDRANGE_ESIL_LW_OP(O) \ - "0x%x,wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -#define PIC_MIDRANGE_ESIL_FWF_OP(O) \ - "wreg," PIC_MIDRANGE_ESIL_BSR_ADDR "," #O \ - "=[1]," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -#define PIC_MIDRANGE_ESIL_WWF_OP(O) \ - PIC_MIDRANGE_ESIL_BSR_ADDR \ - ",[1]," \ - "wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -#define PIC_MIDRANGE_ESIL_FWF_OP_C(O) \ - "c,wreg," \ - "+," PIC_MIDRANGE_ESIL_BSR_ADDR "," #O \ - "=[1]," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -#define PIC_MIDRANGE_ESIL_WWF_OP_C(O) \ - "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1]," #O "," \ - "wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -INST_HANDLER(NOP) {} - -INST_HANDLER(RETFIE) { - op->type = RZ_ANALYSIS_OP_TYPE_RET; -} - -INST_HANDLER(OPTION) { - op->type = RZ_ANALYSIS_OP_TYPE_STORE; -} - -INST_HANDLER(TRIS) { - op->type = RZ_ANALYSIS_OP_TYPE_STORE; -} - -INST_HANDLER(RETURN) { - op->type = RZ_ANALYSIS_OP_TYPE_RET; - e("0x1f,stkptr,==,$z,?{,BREAK,},"); - e("_stack,stkptr,2,*,+,[2],2,*,pc,=,"); - e("0x01,stkptr,-=,"); - e("0xff,stkptr,==,$z,?{,0x1f,stkptr,=,},"); -} - -INST_HANDLER(CALL) { - ut64 pclath; - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - rz_analysis_esil_reg_read(analysis->esil, "pclath", &pclath, NULL); - op->jump = 2 * (((pclath & 0x78) << 8) + args->k); - ef("8,pclath,0x78,&,<<,0x%x,+,2,*,pc,=,", args->k); - e("0x1f,stkptr,==,$z,?{,0xff,stkptr,=,},"); - e("0x0f,stkptr,==,$z,?{,0xff,stkptr,=,},"); - e("0x01,stkptr,+=,"); - ef("0x%" PFMT64x ",_stack,stkptr,2,*,+,=[2],", (addr + 2) / 2); -} - -INST_HANDLER(GOTO) { - ut64 pclath; - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - rz_analysis_esil_reg_read(analysis->esil, "pclath", &pclath, NULL); - op->jump = 2 * (((pclath & 0x78) << 8) + args->k); - ef("8,pclath,0x78,&,<<,0x%x,+,2,*,pc,=,", args->k); -} - -INST_HANDLER(BCF) { - ut8 mask = ~(1 << args->b); - ef(PIC_MIDRANGE_ESIL_BSR_ADDR - ",[1],0x%x,&," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", - args->f, mask, args->f); -} - -INST_HANDLER(BSF) { - ut8 mask = (1 << args->b); - ef(PIC_MIDRANGE_ESIL_BSR_ADDR - ",[1],0x%x,|," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", - args->f, mask, args->f); -} - -INST_HANDLER(BTFSC) { - ut8 mask = (1 << args->b); - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 4; - op->fail = addr + 2; - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],0x%x,&,!,?{,0x%" PFMT64x ",pc,=,},", - args->f, mask, op->jump); -} - -INST_HANDLER(BTFSS) { - ut8 mask = (1 << args->b); - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 4; - op->fail = addr + 2; - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],0x%x,&,?{,0x%" PFMT64x ",pc,=,},", args->f, - mask, op->jump); -} - -INST_HANDLER(BRA) { - st16 branch = args->k; - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - branch |= ((branch & 0x100) ? 0xfe00 : 0); - op->jump = addr + 2 * (branch + 1); - ef("%s0x%x,1,+,2,*,pc,+=,", branch < 0 ? "-" : "", - branch < 0 ? -branch : branch); -} - -INST_HANDLER(BRW) { - ut64 wreg; - op->type = RZ_ANALYSIS_OP_TYPE_UJMP; - rz_analysis_esil_reg_read(analysis->esil, "wreg", &wreg, NULL); - op->jump = addr + 2 * (wreg + 1); - e("wreg,1,+,2,*,pc,+=,"); -} - -INST_HANDLER(CLR) { - if (args->d) { - ef("0x00," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); - } else { - e("0x00,wreg,=,"); - } - e("1,z,=,"); -} - -INST_HANDLER(SUBWF) { - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(-), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(-), args->f); - e("wreg,0x00,-,wreg,=,c,!=,dc,!=,"); - } -} - -INST_HANDLER(DECFSZ) { - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 4; - op->fail = addr + 2; - if (args->d) { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",-=[1],", args->f); - } else { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],-,wreg,=,", - args->f); - } - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],!,?{,0x%" PFMT64x ",pc,=,},", args->f, - op->jump); -} - -INST_HANDLER(INCFSZ) { - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 4; - op->fail = addr + 2; - if (args->d) { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",+=[1],", args->f); - } else { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],+,wreg,=,", - args->f); - } - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],!,?{,0x%" PFMT64x ",pc,=,},", args->f, - op->jump); -} - -INST_HANDLER(INCF) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - if (args->d) { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",+=[1],", args->f); - } else { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],+,wreg,=,", - args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(DECF) { - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - if (args->d) { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",-=[1],", args->f); - } else { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],-,wreg,=,", - args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(IORWF) { - op->type = RZ_ANALYSIS_OP_TYPE_OR; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(|), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(|), args->f); - } -} - -INST_HANDLER(ANDWF) { - op->type = RZ_ANALYSIS_OP_TYPE_AND; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(&), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(&), args->f); - } -} - -INST_HANDLER(XORWF) { - op->type = RZ_ANALYSIS_OP_TYPE_XOR; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(^), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(^), args->f); - } -} - -INST_HANDLER(ADDWF) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(+), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(+), args->f); - } -} - -INST_HANDLER(SUBLW) { - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - ef(PIC_MIDRANGE_ESIL_LW_OP(-), args->k); -} - -INST_HANDLER(ADDLW) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - ef(PIC_MIDRANGE_ESIL_LW_OP(+), args->k); -} - -INST_HANDLER(IORLW) { - op->type = RZ_ANALYSIS_OP_TYPE_OR; - ef(PIC_MIDRANGE_ESIL_LW_OP(|), args->k); -} - -INST_HANDLER(ANDLW) { - op->type = RZ_ANALYSIS_OP_TYPE_AND; - ef(PIC_MIDRANGE_ESIL_LW_OP(&), args->k); -} - -INST_HANDLER(XORLW) { - op->type = RZ_ANALYSIS_OP_TYPE_XOR; - ef(PIC_MIDRANGE_ESIL_LW_OP(^), args->k); -} - -INST_HANDLER(MOVLW) { - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - ef("0x%x,wreg,=,", args->k); -} - -INST_HANDLER(RETLW) { - op->type = RZ_ANALYSIS_OP_TYPE_RET; - ef("0x%x,wreg,=,", args->k); - e("0x1f,stkptr,==,$z,?{,BREAK,},"); - e("_stack,stkptr,2,*,+,[2],2,*,pc,=,"); - e("0x01,stkptr,-=,"); - e("0xff,stkptr,==,$z,?{,0x1f,stkptr,=,},"); -} - -INST_HANDLER(MOVLP) { - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - ef("0x%x,pclath,=,", args->f); -} - -INST_HANDLER(MOVLB) { - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - ef("0x%x,bsr,=,", args->k); -} - -INST_HANDLER(CALLW) { - op->type = RZ_ANALYSIS_OP_TYPE_UCALL; - e("8,pclath,<<,0x%x,+,wreg,2,*,pc,=,"); - e("0x1f,stkptr,==,$z,?{,0xff,stkptr,=,},"); - e("0x0f,stkptr,==,$z,?{,0xff,stkptr,=,},"); - e("0x01,stkptr,+=,"); - ef("0x%" PFMT64x ",_stack,stkptr,2,*,+,=[2],", (addr + 2) / 2); -} - -INST_HANDLER(MOVWF) { - op->type = RZ_ANALYSIS_OP_TYPE_STORE; - ef("wreg," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); -} - -INST_HANDLER(MOVF) { - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_BSR_ADDR - ",[1]," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", - args->f, args->f); - } else { - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],wreg,=,", args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(SWAPF) { - ef("4," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,0x0f,&,", args->f); - ef("4," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,0xf0,&,", args->f); - e("|,"); - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); -} - -INST_HANDLER(LSLF) { - op->type = RZ_ANALYSIS_OP_TYPE_SHL; - ef("7," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,c,=,", args->f); - if (args->d) { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",<<=[1],", args->f); - } else { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,wreg,=,", - args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(LSRF) { - op->type = RZ_ANALYSIS_OP_TYPE_SHR; - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,c,=,", args->f); - if (args->d) { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",>>=[1],", args->f); - } else { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,wreg,=,", - args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(ASRF) { - op->type = RZ_ANALYSIS_OP_TYPE_SHR; - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,c,=,", args->f); - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,", args->f); - ef("0x80," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,", args->f); - if (args->d) { - ef("|," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); - } else { - e("|,wreg,=,"); - } - e("$z,z,:=,"); -} - -INST_HANDLER(RRF) { - op->type = RZ_ANALYSIS_OP_TYPE_ROR; - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,", args->f); - if (args->d) { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",>>=[1]," - "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",|=[1],", - args->f, args->f); - } else { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,wreg,=," - "c,wreg,|=[1],", - args->f); - } - e("c,=,"); -} - -INST_HANDLER(RLF) { - op->type = RZ_ANALYSIS_OP_TYPE_ROL; - ef("7," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,", args->f); - if (args->d) { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",<<=[1]," - "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",|=[1],", - args->f, args->f); - } else { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,wreg,=," - "c,wreg,|=[1],", - args->f); - } - e("c,=,"); -} - -INST_HANDLER(COMF) { - if (args->d) { - ef("0xff," PIC_MIDRANGE_ESIL_BSR_ADDR ",^=[1],", args->f); - } else { - ef("0xff," PIC_MIDRANGE_ESIL_BSR_ADDR ",^,wreg,=,", args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(RESET) { - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->jump = 0; - e("0x0,pc,=,"); - e("0x1f,stkptr,=,"); -} - -INST_HANDLER(ADDFSR) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - if (args->n == 0) { - ef("0x%x,fsr0l,+=,", args->k); - e("7,$c,?{,0x01,fsr0h,+=,},"); - } else { - ef("0x%x,fsr1l,+=,", args->k); - e("7,$c,?{,0x01,fsr1h,+=,},"); - } -} - -INST_HANDLER(CLRWDT) { - e("1,to,=,"); - e("1,pd,=,"); -} - -INST_HANDLER(SLEEP) { - e("1,to,=,"); - e("0,pd,=,"); -} - -INST_HANDLER(SUBWFB) { - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - e("c,!=,"); - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP_C(-), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP_C(-), args->f); - e("wreg,0x00,-,wreg,=,c,!=,dc,!=,"); - } -} - -INST_HANDLER(ADDWFC) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP_C(+), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP_C(+), args->f); - } -} - -INST_HANDLER(MOVIW_1) { - if (args->n == 0) { - if (!(args->m & 2)) { - ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); - ef("7,$c%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - e("indf0,wreg,=,"); - e("$z,z,:=,"); - if (args->m & 2) { - ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); - ef("7,$c%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - } else { - if (!(args->m & 2)) { - ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); - ef("7,$c%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - e("indf1,wreg,=,"); - e("$z,z,:=,"); - if (args->m & 2) { - ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); - ef("7,$c%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - } -} - -INST_HANDLER(MOVWI_1) { - if (args->n == 0) { - if (!(args->m & 2)) { - ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); - ef("$c7%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - e("wreg,indf0=,"); - e("$z,z,:=,"); - if (args->m & 2) { - ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); - ef("$c7%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - } else { - if (!(args->m & 2)) { - ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); - ef("$c7,fsr1h,%s,", (args->m & 1) ? ",!" : ""); - } - e("wreg,indf1=,"); - e("$z,z,:=,"); - if (args->m & 2) { - ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); - ef("$c7%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - } -} - -INST_HANDLER(MOVIW_2) { - if (args->n == 0) { - e("fsr0l,8,fsr0h,<<,+,"); - } else { - e("fsr1l,8,fsr1h,<<,+,"); - } - ef("0x%x,+,[1],wreg,=,", args->k); -} - -INST_HANDLER(MOVWI_2) { - e("wreg,"); - if (args->n == 0) { - e("fsr0l,8,fsr0h,<<,+,"); - } else { - e("fsr1l,8,fsr1h,<<,+,"); - } - e("=[1],"); -} - -#define PIC_MIDRANGE_OPINFO_LEN 52 -static const PicMidrangeOpAnalInfo pic_midrange_op_analysis_info[PIC_MIDRANGE_OPINFO_LEN] = { - INST_DECL(NOP, NONE), INST_DECL(RETURN, NONE), - INST_DECL(RETFIE, NONE), INST_DECL(OPTION, NONE), - INST_DECL(SLEEP, NONE), INST_DECL(CLRWDT, NONE), - INST_DECL(TRIS, 2F), INST_DECL(MOVWF, 7F), - INST_DECL(CLR, 1D_7F), INST_DECL(SUBWF, 1D_7F), - INST_DECL(DECF, 1D_7F), INST_DECL(IORWF, 1D_7F), - INST_DECL(ANDWF, 1D_7F), INST_DECL(XORWF, 1D_7F), - INST_DECL(ADDWF, 1D_7F), INST_DECL(MOVF, 1D_7F), - INST_DECL(COMF, 1D_7F), INST_DECL(INCF, 1D_7F), - INST_DECL(DECFSZ, 1D_7F), INST_DECL(RRF, 1D_7F), - INST_DECL(RLF, 1D_7F), INST_DECL(SWAPF, 1D_7F), - INST_DECL(INCFSZ, 1D_7F), INST_DECL(BCF, 3B_7F), - INST_DECL(BSF, 3B_7F), INST_DECL(BTFSC, 3B_7F), - INST_DECL(BTFSS, 3B_7F), INST_DECL(CALL, 11K), - INST_DECL(GOTO, 11K), INST_DECL(MOVLW, 8K), - INST_DECL(RETLW, 8K), INST_DECL(IORLW, 8K), - INST_DECL(ANDLW, 8K), INST_DECL(XORLW, 8K), - INST_DECL(SUBLW, 8K), INST_DECL(ADDLW, 8K), - INST_DECL(RESET, NONE), INST_DECL(CALLW, NONE), - INST_DECL(BRW, NONE), INST_DECL(MOVIW_1, 1N_2M), - INST_DECL(MOVWI_1, 1N_2M), INST_DECL(MOVLB, 4K), - INST_DECL(LSLF, 1D_7F), INST_DECL(LSRF, 1D_7F), - INST_DECL(ASRF, 1D_7F), INST_DECL(SUBWFB, 1D_7F), - INST_DECL(ADDWFC, 1D_7F), INST_DECL(ADDFSR, 1N_6K), - INST_DECL(MOVLP, 7F), INST_DECL(BRA, 9K), - INST_DECL(MOVIW_2, 1N_6K), INST_DECL(MOVWI_2, 1N_6K) -}; - -static void analysis_pic_midrange_extract_args(ut16 instr, - PicMidrangeOpArgs args, - PicMidrangeOpArgsVal *args_val) { - - memset(args_val, 0, sizeof(PicMidrangeOpArgsVal)); - - switch (args) { - case PIC_MIDRANGE_OP_ARGS_NONE: return; - case PIC_MIDRANGE_OP_ARGS_2F: - args_val->f = instr & PIC_MIDRANGE_OP_ARGS_2F_MASK_F; - return; - case PIC_MIDRANGE_OP_ARGS_7F: - args_val->f = instr & PIC_MIDRANGE_OP_ARGS_7F_MASK_F; - return; - case PIC_MIDRANGE_OP_ARGS_1D_7F: - args_val->f = instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_F; - args_val->d = - (instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_D) >> 7; - return; - case PIC_MIDRANGE_OP_ARGS_1N_6K: - args_val->n = - (instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >> 6; - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_3B_7F: - args_val->b = - (instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_B) >> 7; - args_val->f = instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F; - return; - case PIC_MIDRANGE_OP_ARGS_4K: - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_4K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_8K: - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_8K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_9K: - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_9K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_11K: - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_11K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_1N_2M: - args_val->n = - (instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_N) >> 2; - args_val->m = instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_M; - return; - } -} - -static RzIODesc *mem_sram = 0; -static RzIODesc *mem_stack = 0; - -static RzIODesc *cpu_memory_map(RzIOBind *iob, RzIODesc *desc, ut32 addr, - ut32 size) { - char *mstr = rz_str_newf("malloc://%d", size); - if (desc && iob->fd_get_name(iob->io, desc->fd)) { - iob->fd_remap(iob->io, desc->fd, addr); - } else { - desc = iob->open_at(iob->io, mstr, RZ_PERM_RW, 0, addr, NULL); - } - free(mstr); - return desc; -} - -static bool pic_midrange_reg_write(RzReg *reg, const char *regname, ut32 num) { - if (reg) { - RzRegItem *item = rz_reg_get(reg, regname, RZ_REG_TYPE_GPR); - if (item) { - rz_reg_set_value(reg, item, num); - return true; - } - } - return false; -} +#include "../isa/pic/pic_pic18.h" typedef struct { + RzIODesc *mem_sram; + RzIODesc *mem_stack; bool init_done; + HtSU *pic18_mm; } PicContext; static bool pic_init(void **user) { @@ -669,541 +20,102 @@ static bool pic_init(void **user) { return false; } ctx->init_done = false; + ctx->pic18_mm = ht_su_new(HT_STR_CONST); + char k[32]; + for (int i = 0; i < 0x100; ++i) { + const char *regname = pic18_regname(i); + ht_su_insert(ctx->pic18_mm, regname, i); + for (int bank = 1; bank < 0x10; ++bank) { + rz_strf(k, "%s_%02x", regname, bank); + ht_su_insert(ctx->pic18_mm, k, bank * 0x100 + i); + } + } *user = ctx; return true; } -static void analysis_pic_midrange_malloc(RzAnalysis *analysis, bool force) { - PicContext *ctx = (PicContext *)analysis->plugin_data; - - if (!ctx->init_done || force) { - // Allocate memory as needed. - // We assume that code is already allocated with firmware - // image - mem_sram = - cpu_memory_map(&analysis->iob, mem_sram, - PIC_MIDRANGE_ESIL_SRAM_START, 0x1000); - mem_stack = - cpu_memory_map(&analysis->iob, mem_stack, - PIC_MIDRANGE_ESIL_CSTACK_TOP, 0x20); - - pic_midrange_reg_write(analysis->reg, "_sram", - PIC_MIDRANGE_ESIL_SRAM_START); - pic_midrange_reg_write(analysis->reg, "_stack", - PIC_MIDRANGE_ESIL_CSTACK_TOP); - pic_midrange_reg_write(analysis->reg, "stkptr", 0x1f); - - ctx->init_done = true; +static bool pic_fini(void *user) { + PicContext *ctx = (PicContext *)user; + if (ctx) { + ht_su_free(ctx->pic18_mm); + RZ_FREE(ctx); } + return true; } -static int analysis_pic_midrange_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, - const ut8 *buf, int len) { +#include "pic/pic_midrange_analysis.inc" +#include "pic/pic18_analysis.inc" - ut16 instr; - int i; - - analysis_pic_midrange_malloc(analysis, false); - - if (!buf || len < 2) { - op->type = RZ_ANALYSIS_OP_TYPE_ILL; - return op->size; +static int analysis_pic_op( + RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask) { + if (RZ_STR_ISEMPTY(analysis->cpu) || + RZ_STR_EQ(analysis->cpu, "pic") || + RZ_STR_EQ(analysis->cpu, "pic18")) { + return analysis_pic18_op(analysis, op, addr, buf, len, mask); } - instr = rz_read_le16(buf); - - // Default op params - op->size = 2; - op->cycles = 1; - op->type = RZ_ANALYSIS_OP_TYPE_NOP; - - PicMidrangeOpcode opcode = pic_midrange_get_opcode(instr); - PicMidrangeOpArgsVal args_val; - - for (i = 0; i < PIC_MIDRANGE_OPINFO_LEN; i++) { - if (pic_midrange_op_analysis_info[i].opcode == opcode) { - analysis_pic_midrange_extract_args( - instr, pic_midrange_op_analysis_info[i].args, - &args_val); - pic_midrange_op_analysis_info[i].handler(analysis, op, addr, - &args_val); - break; - } + if (RZ_STR_EQ(analysis->cpu, "baseline") || + RZ_STR_EQ(analysis->cpu, "midrange")) { + return analysis_pic_midrange_op(analysis, op, addr, buf, len, mask); } - - return op->size; -} - -static void pic18_cond_branch(RzAnalysisOp *op, ut64 addr, const ut8 *buf, char *flag) { - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 2 + 2 * (*(ut16 *)buf & 0xff); - op->fail = addr + op->size; - op->cycles = 2; - rz_strbuf_setf(&op->esil, "%s,?,{,0x%" PFMT64x ",pc,=,}", flag, op->jump); + return -1; } -static int analysis_pic_pic18_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len) { - // TODO code should be refactored and broken into smaller chunks!! - // TODO complete the esil emitter - if (len < 2) { - op->size = len; - goto beach; // pancake style :P - } - op->size = 2; - ut16 b = *(ut16 *)buf; - ut32 dword_instr = 0; - memcpy(&dword_instr, buf, RZ_MIN(sizeof(dword_instr), len)); - switch (b >> 9) { - case 0x76: // call - if (len < 4) { - goto beach; - } - if (dword_instr >> 28 != 0xf) { - goto beach; - } - op->size = 4; - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - return op->size; - }; - switch (b >> 11) { // NEX_T - case 0x1b: // rcall - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - return op->size; - case 0x1a: // bra - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->cycles = 2; - op->jump = addr + 2 + 2 * (*(ut16 *)buf & 0x7ff); - rz_strbuf_setf(&op->esil, "0x%" PFMT64x ",pc,=", op->jump); - return op->size; +static char *analysis_pic_get_reg_profile(RzAnalysis *analysis) { + if (RZ_STR_ISEMPTY(analysis->cpu) || + RZ_STR_EQ(analysis->cpu, "pic") || + RZ_STR_EQ(analysis->cpu, "pic18")) { + return analysis_pic_pic18_get_reg_profile(analysis); } - switch (b >> 12) { // NOP,movff,BAF_T - case 0xf: // nop - op->type = RZ_ANALYSIS_OP_TYPE_NOP; - op->cycles = 1; - rz_strbuf_setf(&op->esil, ","); - return op->size; - case 0xc: // movff - if (len < 4) { - goto beach; - } - if (dword_instr >> 28 != 0xf) { - goto beach; - } - op->size = 4; - op->type = RZ_ANALYSIS_OP_TYPE_MOV; - return op->size; - case 0xb: // btfsc - case 0xa: // btfss - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - return op->size; - case 0x9: // bcf - case 0x8: // bsf - case 0x7: // btg - op->type = RZ_ANALYSIS_OP_TYPE_UNK; - return op->size; - }; - - switch (b >> 8) { // GOTO_T,N_T,K_T - case 0xe0: // bz - pic18_cond_branch(op, addr, buf, "z"); - return op->size; - case 0xe1: // bnz - pic18_cond_branch(op, addr, buf, "z,!"); - return op->size; - case 0xe3: // bnc - pic18_cond_branch(op, addr, buf, "c,!"); - return op->size; - case 0xe4: // bov - pic18_cond_branch(op, addr, buf, "ov"); - return op->size; - case 0xe5: // bnov - pic18_cond_branch(op, addr, buf, "ov,!"); - return op->size; - case 0xe6: // bn - pic18_cond_branch(op, addr, buf, "n"); - return op->size; - case 0xe7: // bnn - pic18_cond_branch(op, addr, buf, "n,!"); - return op->size; - case 0xe2: // bc - pic18_cond_branch(op, addr, buf, "c"); - return op->size; - case 0xef: // goto - if (len < 4) { - goto beach; - } - if (dword_instr >> 28 != 0xf) { - goto beach; - } - op->size = 4; - op->cycles = 2; - op->jump = ((dword_instr & 0xff) | ((dword_instr & 0xfff0000) >> 8)) * 2; - rz_strbuf_setf(&op->esil, "0x%" PFMT64x ",pc,=", op->jump); - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - return op->size; - case 0xf: // addlw - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - op->cycles = 1; - // TODO add support for dc flag - rz_strbuf_setf(&op->esil, "0x%x,wreg,+=,$z,z,:=,7,$s,n,:=,7,$c,c,:=,7,$o,ov,:=,", *(ut16 *)buf & 0xff); - return op->size; - case 0xe: // movlw - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,=,", *(ut16 *)buf & 0xff); - return op->size; - case 0xd: // mullw - op->type = RZ_ANALYSIS_OP_TYPE_MUL; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,*,prod,=", *(ut16 *)buf & 0xff); - return op->size; - case 0xc: // retlw - op->type = RZ_ANALYSIS_OP_TYPE_RET; - op->cycles = 2; - rz_strbuf_setf(&op->esil, "0x%x,wreg,=,tos,pc,=,", *(ut16 *)buf & 0xff); - return op->size; - case 0xb: // andlw - op->type = RZ_ANALYSIS_OP_TYPE_AND; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,&=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); - return op->size; - case 0xa: // xorlw - op->type = RZ_ANALYSIS_OP_TYPE_XOR; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,^=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); - return op->size; - case 0x9: // iorlw - op->type = RZ_ANALYSIS_OP_TYPE_OR; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,^=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); - return op->size; - case 0x8: // sublw - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - op->cycles = 1; - // TODO add support for dc flag - rz_strbuf_setf(&op->esil, "wreg,0x%x,-,wreg,=,$z,z,:=,7,$s,n,:=,7,$c,c,:=,7,$o,ov,:=,", *(ut16 *)buf & 0xff); - return op->size; - }; - - switch (b >> 6) { // LFSR - case 0x3b8: // lfsr - if (len < 4) { - goto beach; - } - if (dword_instr >> 28 != 0xf) { - goto beach; - } - op->size = 4; - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - return op->size; - }; - switch (b >> 10) { // DAF_T - case 0x17: // subwf - case 0x16: // subwfb - case 0x15: // subfwb - case 0x13: // dcfsnz - case 0xb: // decfsz - case 0x1: // decf - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - return op->size; - case 0x14: // movf - op->type = RZ_ANALYSIS_OP_TYPE_MOV; - return op->size; - case 0x12: // infsnz - case 0xf: // incfsz - case 0xa: // incf - case 0x8: // addwfc - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - return op->size; - case 0x9: // addwf - op->cycles = 1; - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - return op->size; - case 0x11: // rlncf - case 0xd: // rlcf - op->type = RZ_ANALYSIS_OP_TYPE_ROL; - return op->size; - case 0x10: // rrncf - case 0xc: // rrcf - op->type = RZ_ANALYSIS_OP_TYPE_ROR; - return op->size; - case 0xe: // swapf - op->type = RZ_ANALYSIS_OP_TYPE_UNK; - return op->size; - case 0x7: // comf - op->type = RZ_ANALYSIS_OP_TYPE_CPL; - return op->size; - case 0x6: // xorwf - op->type = RZ_ANALYSIS_OP_TYPE_XOR; - return op->size; - case 0x5: // andwf - op->type = RZ_ANALYSIS_OP_TYPE_AND; - return op->size; - case 0x4: // iorwf - op->type = RZ_ANALYSIS_OP_TYPE_OR; - return op->size; - }; - switch (b >> 9) { // AF_T - case 0x37: // movwf - op->type = RZ_ANALYSIS_OP_TYPE_STORE; - return op->size; - case 0x36: // negf - case 0x35: // clrf - case 0x34: // setf - op->type = RZ_ANALYSIS_OP_TYPE_UNK; - return op->size; - case 0x33: // tstfsz - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - return op->size; - case 0x32: // cpfsgt - case 0x31: // cpfseq - case 0x30: // cpfslt - op->type = RZ_ANALYSIS_OP_TYPE_CMP; - return op->size; - case 0x1: // mulwf - op->type = RZ_ANALYSIS_OP_TYPE_MUL; - return op->size; - }; - switch (b >> 4) { - case 0x10: // movlb - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,bsr,=,", *(ut16 *)buf & 0xf); - return op->size; - }; - switch (b) { - case 0xff: // reset - case 0x7: // daw - case 0x4: // clwdt - case 0x3: // sleep - op->type = RZ_ANALYSIS_OP_TYPE_UNK; - return op->size; - case 0x13: // return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - op->cycles = 2; - rz_strbuf_setf(&op->esil, "tos,pc,=,"); - return op->size; - case 0x12: // return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - op->cycles = 2; - rz_strbuf_setf(&op->esil, "tos,pc,="); - return op->size; - case 0x11: // retfie - case 0x10: // retfie - op->type = RZ_ANALYSIS_OP_TYPE_RET; - return op->size; - case 0xf: // tblwt - case 0xe: // tblwt - case 0xd: // tblwt - case 0xc: // tblwt - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - return op->size; - case 0xb: // tblrd - case 0xa: // tblrd - case 0x9: // tblrd - case 0x8: // tblrd - op->type = RZ_ANALYSIS_OP_TYPE_STORE; - return op->size; - case 0x6: // pop - op->type = RZ_ANALYSIS_OP_TYPE_POP; - return op->size; - case 0x5: // push - op->type = RZ_ANALYSIS_OP_TYPE_PUSH; - return op->size; - case 0x0: // nop - op->type = RZ_ANALYSIS_OP_TYPE_NOP; - op->cycles = 1; - rz_strbuf_setf(&op->esil, ","); - return op->size; - }; -beach: - op->type = RZ_ANALYSIS_OP_TYPE_ILL; - return op->size; -} - -static char *analysis_pic_midrange_get_reg_profile(RzAnalysis *esil) { - const char *p = - "=PC pc\n" - "=SP stkptr\n" - "=A0 porta\n" - "=A1 portb\n" - "gpr indf0 .8 0 0\n" - "gpr indf1 .8 1 0\n" - "gpr pcl .8 2 0\n" - "gpr status .8 3 0\n" - "flg c .1 3.0 0\n" - "flg dc .1 3.1 0\n" - "flg z .1 3.2 0\n" - "flg pd .1 3.3 0\n" - "flg to .1 3.4 0\n" - "gpr fsr0l .8 4 0\n" - "gpr fsr0h .8 5 0\n" - "gpr fsr1l .8 6 0\n" - "gpr fsr1h .8 7 0\n" - "gpr bsr .8 8 0\n" - "gpr wreg .8 9 0\n" - "gpr pclath .8 10 0\n" - "gpr intcon .8 11 0\n" - "gpr pc .16 12 0\n" - "gpr stkptr .8 14 0\n" - "gpr _sram .32 15 0\n" - "gpr _stack .32 19 0\n"; - return strdup(p); -} - -static char *analysis_pic_pic18_get_reg_profile(RzAnalysis *esil) { - const char *p = - "#pc lives in nowhere actually" - "=PC pc\n" - "=SP tos\n" - "=A0 porta\n" - "=A1 portb\n" - "gpr pc .32 0 0\n" - "gpr pcl .8 0 0\n" - "gpr pclath .8 1 0\n" - "gpr pclatu .8 2 0\n" - "#bsr max is 0b111\n" - "gpr bsr .8 4 0\n" - "#tos doesn't exist\n" - "#general rule of thumb any register of size >8 bits has no existence\n" - "gpr tos .32 5 0\n" - "gpr tosl .8 5 0\n" - "gpr tosh .8 6 0\n" - "gpr tosu .8 7 0\n" - - "gpr indf0 .16 9 0\n" - "gpr fsr0 .12 9 0\n" - "gpr fsr0l .8 9 0\n" - "gpr fsr0h .8 10 0\n" - "gpr indf1 .16 11 0\n" - "gpr fsr1 .12 11 0\n" - "gpr fsr1l .8 11 0\n" - "gpr fsr1h .8 12 0\n" - "gpr indf2 .16 13 0\n" - "gpr fsr2 .12 13 0\n" - "gpr frs2l .8 13 0\n" - "gpr fsr2h .8 14 0\n" - "gpr tblptr .22 15 0\n" - "gpr tblptrl .8 15 0\n" - "gpr tblptrh .8 16 0\n" - "gpr tblptru .8 17 0\n" - "gpr rcon .8 18 0\n" - "gpr memcon .8 19 0\n" - "gpr intcon .8 20 0\n" - "gpr intcon2 .8 21 0\n" - "gpr intcon3 .8 22 0\n" - "gpr pie1 .8 23 0\n" - "gpr porta .7 29 0\n" - "gpr trisa .8 30 0\n" - "gpr portb .8 33 0\n" - "gpr tisb .8 34 0\n" - "gpr latb .8 35 0\n" - "gpr portc .8 36 0\n" - "gpr trisc .8 37 0\n" - "gpr latc .8 38 0\n" - "gpr portd .8 39 0\n" - "gpr trisd .8 40 0\n" - "gpr latd .8 41 0\n" - "gpr pspcon .8 42 0\n" - "gpr porte .8 43 0\n" - "gpr trise .8 44 0\n" - "gpr late .8 45 0\n" - "gpr t0con .8 46 0\n" - "gpr t1con .8 47 0\n" - "gpr t2con .8 48 0\n" - "gpr tmr1h .8 50 0\n" - "gpr tmr0h .8 51 0\n" - "gpr tmr1l .8 52 0\n" - "gpr tmr2 .8 53 0\n" - "gpr pr2 .8 54 0\n" - "gpr ccpr1h .8 55 0\n" - "gpr postinc2 .8 56 0\n" - "gpr ccpr1l .8 57 0\n" - "gpr postdec2 .8 58 0\n" - "gpr ccp1con .8 59 0\n" - "gpr preinc2 .8 60 0\n" - "gpr ccpr2h .8 61 0\n" - "gpr plusw2 .8 62 0\n" - "gpr ccpr2l .8 63 0\n" - "gpr ccp2con .8 64 0\n" - "gpr status .8 65 0\n" - "flg c .1 .520 0\n" - "flg dc .1 .521 0\n" - "flg z .1 .522 0\n" - "flg ov .1 .523 0\n" - "flg n .1 .524 0\n" - "gpr prod .16 66 0\n" - "gpr prodl .8 66 0\n" - "gpr prodh .8 67 0\n" - "gpr osccon .8 68 0\n" - "gpr tmr3h .8 69 0\n" - "gpr lvdcon .8 70 0\n" - "gpr tmr3l .8 71 0\n" - "gpr wdtcon .8 72 0\n" - "gpr t3con .8 73 0\n" - "gpr spbrg .8 74 0\n" - "gpr postinc0 .8 75 0\n" - "gpr rcreg .8 76 0\n" - "gpr postdec0 .8 77 0\n" - "gpr txreg .8 78 0\n" - "gpr preinc0 .8 79 0\n" - "gpr txsta .8 80 0\n" - "gpr plusw0 .8 81 0\n" - "gpr rcsta .8 82 0\n" - "gpr sspbuf .8 83 0\n" - "gpr wreg .8 84 0\n" - "gpr sspadd .8 85 0\n" - "gpr sspstat .8 86 0\n" - "gpr postinc1 .8 87 0\n" - "gpr sspcon1 .8 88 0\n" - "gpr postdec1 .8 89 0\n" - "gpr sspcon2 .8 90 0\n" - "gpr preinc1 .8 91 0\n" - "gpr adresh .8 92 0\n" - "gpr plusw1 .8 93 0\n" - "gpr adresl .8 94 0\n" - "gpr adcon0 .8 95 0\n" - "#stkprt max is 0b11111\n" - "gpr stkptr .8 96 0\n" - "gpr tablat .8 14 0\n"; - return strdup(p); -} - -static int analysis_pic_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { - if (analysis->cpu && strcasecmp(analysis->cpu, "baseline") == 0) { - // TODO: implement - return -1; - } - if (analysis->cpu && strcasecmp(analysis->cpu, "midrange") == 0) { - return analysis_pic_midrange_op(analysis, op, addr, buf, len); - } - if (analysis->cpu && strcasecmp(analysis->cpu, "pic18") == 0) { - return analysis_pic_pic18_op(analysis, op, addr, buf, len); + if (RZ_STR_EQ(analysis->cpu, "baseline") || + RZ_STR_EQ(analysis->cpu, "midrange")) { + return analysis_pic_midrange_get_reg_profile(analysis); } - return -1; + return NULL; } -static char *analysis_pic_get_reg_profile(RzAnalysis *analysis) { - if (analysis->cpu && strcasecmp(analysis->cpu, "baseline") == 0) { - // TODO: We are using the midrange profile as the baseline - return analysis_pic_midrange_get_reg_profile(analysis); +static RzAnalysisILConfig *pic_il_config(RzAnalysis *a) { + if (a->cpu && strcasecmp(a->cpu, "baseline") == 0) { + // TODO: We are using the midrange il config as the baseline + return pic_midrange_il_config(a); } - if (analysis->cpu && strcasecmp(analysis->cpu, "midrange") == 0) { - return analysis_pic_midrange_get_reg_profile(analysis); + if (a->cpu && strcasecmp(a->cpu, "midrange") == 0) { + return pic_midrange_il_config(a); } - if (analysis->cpu && strcasecmp(analysis->cpu, "pic18") == 0) { - return analysis_pic_pic18_get_reg_profile(analysis); + if (a->cpu && strcasecmp(a->cpu, "pic18") == 0) { + return pic18_il_config(a); } return NULL; } -static bool pic_fini(void *user) { - PicContext *ctx = (PicContext *)user; - if (ctx) { - RZ_FREE(ctx); +static int pic_archinfo(RzAnalysis *a, RzAnalysisInfoType query) { + if (RZ_STR_ISEMPTY(a->cpu) || + RZ_STR_EQ(a->cpu, "pic") || + RZ_STR_EQ(a->cpu, "pic18")) { + switch (query) { + case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: return 2; + case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: return 4; + case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN: return 2; + case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN: return 4; + case RZ_ANALYSIS_ARCHINFO_CAN_USE_POINTERS: return 1; + default: return -1; + } } - return true; + + if (RZ_STR_EQ(a->cpu, "baseline") || + RZ_STR_EQ(a->cpu, "midrange")) { + switch (query) { + case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: return 2; + case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: return 2; + case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN: return 2; + case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN: return 2; + case RZ_ANALYSIS_ARCHINFO_CAN_USE_POINTERS: return 1; + default: return -1; + } + } + return -1; } RzAnalysisPlugin rz_analysis_plugin_pic = { @@ -1215,6 +127,8 @@ RzAnalysisPlugin rz_analysis_plugin_pic = { .op = &analysis_pic_op, .init = pic_init, .fini = pic_fini, + .il_config = pic_il_config, .get_reg_profile = &analysis_pic_get_reg_profile, - .esil = true + .esil = true, + .archinfo = pic_archinfo }; diff --git a/librz/arch/p/asm/asm_pic.c b/librz/arch/p/asm/asm_pic.c index ffe38be12d1..e57e3ed22c0 100644 --- a/librz/arch/p/asm/asm_pic.c +++ b/librz/arch/p/asm/asm_pic.c @@ -12,11 +12,11 @@ static int asm_pic_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) { int res = -1; if (a->cpu && strcasecmp(a->cpu, "baseline") == 0) { - res = pic_baseline_disassemble(op, b, l); + res = pic_baseline_disassemble(a, op, b, l); } else if (a->cpu && strcasecmp(a->cpu, "midrange") == 0) { - res = pic_midrange_disassemble(op, b, l); - } else if (a->cpu && strcasecmp(a->cpu, "pic18") == 0) { - res = pic_pic18_disassemble(op, b, l); + res = pic_midrange_disassemble(a, op, b, l); + } else if (a->cpu && (strcasecmp(a->cpu, "pic18") == 0 || RZ_STR_EQ(a->cpu, "pic"))) { + res = pic_pic18_disassemble(a, op, b, l); } return op->size = res; } @@ -24,7 +24,7 @@ static int asm_pic_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) { RzAsmPlugin rz_asm_plugin_pic = { .name = "pic", .arch = "pic", - .cpus = "baseline,midrange,pic18", + .cpus = "pic18,baseline,midrange", .bits = 8, .license = "LGPL3", .desc = "PIC disassembler", diff --git a/librz/bin/format/elf/elf_info.c b/librz/bin/format/elf/elf_info.c index 906e2132771..a25ce6d5c63 100644 --- a/librz/bin/format/elf/elf_info.c +++ b/librz/bin/format/elf/elf_info.c @@ -264,6 +264,7 @@ static const struct arch_translation arch_translation_table[] = { { EM_SPARCV9, "sparc" }, { EM_PPC, "ppc" }, { EM_PPC64, "ppc" }, + { EM_MCHP_PIC, "pic" }, { EM_PARISC, "hppa" }, { EM_PROPELLER, "propeller" }, { EM_MICROBLAZE, "microblaze.gnu" }, diff --git a/librz/include/rz_il/rz_il_opbuilder_begin.h b/librz/include/rz_il/rz_il_opbuilder_begin.h index 3c289a657bc..c0bbc39c259 100644 --- a/librz/include/rz_il/rz_il_opbuilder_begin.h +++ b/librz/include/rz_il/rz_il_opbuilder_begin.h @@ -130,7 +130,6 @@ #define NON_ZERO(x) rz_il_op_new_non_zero(x) #define IS_ZERO(x) rz_il_op_new_is_zero(x) -#define BITN(x, n) IZ_ZERO(AND(SHIFTR0(x, n)), U8(1)) #define MSB(x) rz_il_op_new_msb(x) #define LSB(x) rz_il_op_new_lsb(x) #define EQ(x, y) rz_il_op_new_eq(x, y) diff --git a/librz/include/rz_il/rz_il_opbuilder_end.h b/librz/include/rz_il/rz_il_opbuilder_end.h index ef954a21331..1241793e8d8 100644 --- a/librz/include/rz_il/rz_il_opbuilder_end.h +++ b/librz/include/rz_il/rz_il_opbuilder_end.h @@ -92,7 +92,6 @@ #undef NON_ZERO #undef IS_ZERO -#undef BITN #undef MSB #undef LSB #undef EQ diff --git a/test/db/analysis/pic b/test/db/analysis/pic index f932eab38d0..a81f815af72 100644 --- a/test/db/analysis/pic +++ b/test/db/analysis/pic @@ -106,5 +106,7 @@ plusw1 = 0x00 adresl = 0x00 adcon0 = 0x00 stkptr = 0x00 +_sram = 0x00 +_stack = 0x00 EOF RUN diff --git a/test/db/asm/pic_pic18_8 b/test/db/asm/pic_pic18_8 index 3ea12004117..a6c3c5f7448 100644 --- a/test/db/asm/pic_pic18_8 +++ b/test/db/asm/pic_pic18_8 @@ -5,7 +5,7 @@ d "andwf 0x85, 1, 1" 8517 d "bcf 0x42, 7, 1" 429f d "bnn 0xfa" fae7 d "bra 0x51e" 1ed5 -d "call 0x612a1, 1" a1ed12f6 +d "call 0xc2542, 1" a1ed12f6 d "clrf 0x15, 0" 156a d "comf 0x48, 0, 0" 481c d "cpfseq 0x71, 1" 7163 diff --git a/test/db/cmd/cmd_list b/test/db/cmd/cmd_list index 66436970289..9adfd8d9db9 100644 --- a/test/db/cmd/cmd_list +++ b/test/db/cmd/cmd_list @@ -412,7 +412,7 @@ adAe_ 16 32 64 mips BSD Capstone MIPS disassembler _dA__ 16 msp430 LGPL3 msp430 disassembly plugin adA__ 16 32 64 null MIT no disassemble (by pancake) v1.0.0 _dA__ 32 or1k LGPL3 OpenRISC 1000 -_dAe_ 8 pic LGPL3 PIC disassembler +_dAeI 8 pic LGPL3 PIC disassembler a____ 32 64 ppc.as LGPL3 as PPC Assembler (use RZ_PPC_AS environment) (by eagleoflqj) _dAeI 32 64 ppc BSD Capstone PowerPC disassembler (by pancake) _dA__ 32 propeller LGPL3 propeller disassembly plugin