From 8ea03a8e552f9d3c5abc4106056e1bb3d464de89 Mon Sep 17 00:00:00 2001
From: billow <billow.fun@gmail.com>
Date: Thu, 16 May 2024 09:30:49 +0800
Subject: [PATCH] fix

---
 librz/arch/isa/pic/pic18.c             | 4 +++-
 librz/arch/isa/pic/pic_midrange.c      | 6 +-----
 librz/arch/isa/pic/pic_midrange_il.inc | 7 -------
 librz/arch/p/analysis/analysis_pic.c   | 4 ++--
 test/db/analysis/pic                   | 4 ++++
 5 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/librz/arch/isa/pic/pic18.c b/librz/arch/isa/pic/pic18.c
index 318ed41be06..7af38fbca09 100644
--- a/librz/arch/isa/pic/pic18.c
+++ b/librz/arch/isa/pic/pic18.c
@@ -6,7 +6,9 @@
 
 #include "pic18.h"
 
-// PIC18CXXX instruction set
+/**
+ * \file PIC18CXXX instruction set
+ */
 
 // instruction classification according to the argument types
 
diff --git a/librz/arch/isa/pic/pic_midrange.c b/librz/arch/isa/pic/pic_midrange.c
index c293157f6df..7c86cd475fc 100644
--- a/librz/arch/isa/pic/pic_midrange.c
+++ b/librz/arch/isa/pic/pic_midrange.c
@@ -179,10 +179,6 @@ static const char *PicMidrangeFsrOps[] = { "++FSR%d", "--FSR%d", "FSR%d++",
  * \brief Decode a Pic Midrange instruction to it's corresponding opcode enum.
  * */
 PicMidrangeOpcode pic_midrange_get_opcode(ut16 instr) {
-	if (instr & (1 << 14)) {
-		return PIC_MIDRANGE_OPCODE_INVALID;
-	}
-
 	switch (instr >> 11) { // 3 first MSB bits
 	case 0x4: return PIC_MIDRANGE_OPCODE_CALL;
 	case 0x5: return PIC_MIDRANGE_OPCODE_GOTO;
@@ -336,7 +332,7 @@ bool pic16_disasm_op(Pic16Op *op, ut64 addr, const ut8 *b, ut64 l) {
 		return false;
 	}
 
-	op->instr = rz_read_le16(b);
+	op->instr = rz_read_le16(b) & 0x3fff;
 	PicMidrangeOpcode opcode = pic_midrange_get_opcode(op->instr);
 	if (opcode == PIC_MIDRANGE_OPCODE_INVALID) {
 		return false;
diff --git a/librz/arch/isa/pic/pic_midrange_il.inc b/librz/arch/isa/pic/pic_midrange_il.inc
index 7194e608bba..b21505c7761 100644
--- a/librz/arch/isa/pic/pic_midrange_il.inc
+++ b/librz/arch/isa/pic/pic_midrange_il.inc
@@ -67,13 +67,6 @@ static RzILOpEffect *set_register_i(ut16 i, RzILOpPure *x);
 #define PC  (ctx->x->addr)
 #define VPC (U16(PC))
 
-static const char *PIC16_FSR[] = {
-	"fsr0l",
-	"fsr0h",
-	"fsr1l",
-	"fsr1h",
-};
-
 static RzILOpPure *val_fsrn(ut8 n) {
 	rz_return_val_if_fail(n <= 1, NULL);
 	return APPEND(register_i(2 * n + FSR0L + 1), register_i(2 * n + FSR0L));
diff --git a/librz/arch/p/analysis/analysis_pic.c b/librz/arch/p/analysis/analysis_pic.c
index 594d2cc2782..d55a13660fb 100644
--- a/librz/arch/p/analysis/analysis_pic.c
+++ b/librz/arch/p/analysis/analysis_pic.c
@@ -86,8 +86,8 @@ static int pic_archinfo(RzAnalysis *analysis, RzAnalysisInfoType query) {
 		switch (query) {
 		case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: return 2;
 		case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: return 2;
-		case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN: return 2;
-		case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN: return 2;
+		case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN: return 1;
+		case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN: return 1;
 		case RZ_ANALYSIS_ARCHINFO_CAN_USE_POINTERS: return 1;
 		default: return -1;
 		}
diff --git a/test/db/analysis/pic b/test/db/analysis/pic
index 8516bf629f8..2f9108c0df1 100644
--- a/test/db/analysis/pic
+++ b/test/db/analysis/pic
@@ -27,6 +27,10 @@ pc = 0x0000
 stkptr = 0x00
 _sram = 0x00000000
 _stack = 0x00000000
+tosl = 0x00
+tosh = 0x00
+tris = 0x00
+_bank = 0x00
 =============== pic18
 pc = 0x00000000
 bsr = 0x00