diff --git a/librz/arch/isa/pic/pic18_il.inc b/librz/arch/isa/pic/pic18_il.inc index 02fed42fb4f..a6f4542af1d 100644 --- a/librz/arch/isa/pic/pic18_il.inc +++ b/librz/arch/isa/pic/pic18_il.inc @@ -3,194 +3,149 @@ #include -static ut64 pic18_regadr(Pic18ILContext *ctx, const char *v) { - bool f = false; - ut64 adr = ht_su_find((HtSU *)ctx->mm, v, &f); - if (f) { - return adr; - } - rz_warn_if_reached(); - return UT64_MAX; -} - -static RzILOpPure *varg_mm(Pic18ILContext *ctx, const char *v); -static RzILOpEffect *setg_mm(Pic18ILContext *ctx, const char *v, RzILOpPure *x); +#define U24(x) UN(24, x) +static RzILOpPure *varg_mm(Pic18ILContext *ctx, const char *v, ut8 bank); +static RzILOpEffect *setg_mm(Pic18ILContext *ctx, const char *v, RzILOpPure *x, ut8 bank); -static RzILOpPure *varg_mm_uhl(Pic18ILContext *ctx, const char *u, const char *h, const char *l) { - return APPEND(varg_mm(ctx, u), APPEND(varg_mm(ctx, h), varg_mm(ctx, l))); -} -static RzILOpEffect *setg_mm_uhl(Pic18ILContext *ctx, const char *u, const char *h, const char *l, RzILOpPure *x) { - return SEQ4( - SETL("__x", x), - setg_mm(ctx, u, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(16)))), - setg_mm(ctx, h, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(8)))), - setg_mm(ctx, l, UNSIGNED(8, VARL("__x")))); -} -static RzILOpPure *varg_mm_hl(Pic18ILContext *ctx, const char *v) { - char h[8]; - char l[8]; - rz_strf(h, "%sh", v); - rz_strf(l, "%sl", v); - return APPEND(varg_mm(ctx, h), varg_mm(ctx, l)); -} -static RzILOpEffect *setg_mm_hl(Pic18ILContext *ctx, const char *v, RzILOpPure *x) { - char h[8]; - char l[8]; - rz_strf(h, "%sh", v); - rz_strf(l, "%sl", v); - return SEQ3( - SETL("__x", x), - setg_mm(ctx, h, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(8)))), - setg_mm(ctx, l, UNSIGNED(8, VARL("__x")))); -} - -/** - * \see https://ww1.microchip.com/downloads/en/DeviceDoc/39500a.pdf - * 7.7.6 Indirect Addressing, INDF, and FSR Registers - * Each FSR register has an INDF register plus four addresses associated with it. The same INDFn, - * and FSRnH:FSRnL registers are used, but depending on the INDFn address selected, the - * FSRnH:FSRnL registers may be modified. - * When a data access is done to the one of the five INDFn locations, the address selected will configure the FSRn register to: - * • Do nothing to FSRn after an indirect access (no change) - INDFn - * • Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn - * • Auto-increment FSRn after an indirect access (post-increment) - POSTINCn - * • Auto-increment FSRn before an indirect access (pre-increment) - PREINCn - * • Use the value in the WREG register as an offset to FSRn. Do not modify the value of the - * WREG or the FSRn register after an indirect access (no change) - PLUSWn - */ -static RzILOpPure *varg_mm(Pic18ILContext *ctx, const char *v) { +static RzILOpPure *pic18_regadr(Pic18ILContext *ctx, const char *v, ut8 bank) { if (RZ_STR_ISEMPTY(v)) { return NULL; } + char fsr[8] = { 0 }; if (rz_str_startswith(v, "indf")) { - char fsr[8]; long n = strtol(v + 4, NULL, 0); rz_strf(fsr, "fsr%ld", n); - return LOAD(UNSIGNED(24, varg_mm(ctx, fsr))); } if (rz_str_startswith(v, "postdec")) { - char fsr[8]; long n = strtol(v + 7, NULL, 0); rz_strf(fsr, "fsr%ld", n); rz_warn_if_fail(ctx->eff.tag == ILOpEff_None); ctx->eff.tag = ILOpEff_PostDec; strcat(ctx->eff.fsr, fsr); - return LOAD(UNSIGNED(24, varg_mm(ctx, fsr))); } if (rz_str_startswith(v, "postinc")) { - char fsr[8]; long n = strtol(v + 7, NULL, 0); rz_strf(fsr, "fsr%ld", n); rz_warn_if_fail(ctx->eff.tag == ILOpEff_None); ctx->eff.tag = ILOpEff_PostInc; strcat(ctx->eff.fsr, fsr); - return LOAD(UNSIGNED(24, varg_mm(ctx, fsr))); } if (rz_str_startswith(v, "predec")) { - char fsr[8]; long n = strtol(v + 6, NULL, 0); rz_strf(fsr, "fsr%ld", n); rz_warn_if_fail(ctx->eff.tag == ILOpEff_None); ctx->eff.tag = ILOpEff_PreInc; strcat(ctx->eff.fsr, fsr); - return LOAD(UNSIGNED(24, varg_mm(ctx, fsr))); } if (rz_str_startswith(v, "plusw")) { - char fsr[8]; long n = strtol(v + 5, NULL, 0); rz_strf(fsr, "fsr%ld", n); - return LOAD(UNSIGNED(24, ADD(varg_mm(ctx, fsr), UNSIGNED(16, varg_mm(ctx, "wreg"))))); + return UNSIGNED(24, ADD(varg_mm(ctx, fsr, bank), UNSIGNED(16, varg_mm(ctx, "wreg", bank)))); + } + if (fsr[0]) { + return UNSIGNED(24, varg_mm(ctx, fsr, bank)); } bool f = false; ut64 adr = ht_su_find((HtSU *)ctx->mm, v, &f); if (f) { - return LOAD(UN(24, adr)); + return U24(adr + bank * 0x100); } + return NULL; +} + +static RzILOpPure *varg_hl(Pic18ILContext *ctx, const char *v, ut8 bank) { + char h[8]; + char l[8]; + rz_strf(h, "%sh", v); + rz_strf(l, "%sl", v); + return APPEND(varg_mm(ctx, h, bank), varg_mm(ctx, l, bank)); +} +static RzILOpEffect *setg_hl(Pic18ILContext *ctx, const char *v, RzILOpPure *x, ut8 bank) { + char h[8]; + char l[8]; + rz_strf(h, "%sh", v); + rz_strf(l, "%sl", v); + return SEQ3( + SETL("__x", x), + setg_mm(ctx, h, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(8))), bank), + setg_mm(ctx, l, UNSIGNED(8, VARL("__x")), bank)); +} +static RzILOpPure *varg_uhl(Pic18ILContext *ctx, const char *v, ut8 bank) { + char u[8]; + rz_strf(u, "%su", v); + return APPEND(varg_mm(ctx, u, bank), varg_hl(ctx, v, bank)); +} +static RzILOpEffect *setg_uhl(Pic18ILContext *ctx, const char *v, RzILOpPure *x, ut8 bank) { + char u[8]; + rz_strf(u, "%su", v); + return SEQ3( + SETL("__x", x), + setg_mm(ctx, u, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(16))), bank), + setg_hl(ctx, v, VARL("__x"), bank)); +} + +/** + * \see https://ww1.microchip.com/downloads/en/DeviceDoc/39500a.pdf + * 7.7.6 Indirect Addressing, INDF, and FSR Registers + * Each FSR register has an INDF register plus four addresses associated with it. The same INDFn, + * and FSRnH:FSRnL registers are used, but depending on the INDFn address selected, the + * FSRnH:FSRnL registers may be modified. + * When a data access is done to the one of the five INDFn locations, the address selected will configure the FSRn register to: + * • Do nothing to FSRn after an indirect access (no change) - INDFn + * • Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn + * • Auto-increment FSRn after an indirect access (post-increment) - POSTINCn + * • Auto-increment FSRn before an indirect access (pre-increment) - PREINCn + * • Use the value in the WREG register as an offset to FSRn. Do not modify the value of the + * WREG or the FSRn register after an indirect access (no change) - PLUSWn + */ +static RzILOpPure *varg_mm(Pic18ILContext *ctx, const char *v, ut8 bank) { + if (RZ_STR_ISEMPTY(v)) { + return NULL; + } + RzILOpPure *adr = pic18_regadr(ctx, v, bank); + if (adr) { + return LOAD(adr); + } + ut8 b = pic18_status(v); if (b != 0xff) { - return bit_get(varg_mm(ctx, "status"), b); - } - if (RZ_STR_EQ(v, "tblptr")) { - return varg_mm_uhl(ctx, "tblptru", "tblptrh", "tblptrl"); + return bit_get(varg_mm(ctx, "status", bank), b); } - if (RZ_STR_EQ(v, "tos")) { - return varg_mm_uhl(ctx, "tosu", "tosh", "tosl"); + if (RZ_STR_EQ(v, "tblptr") || RZ_STR_EQ(v, "tos")) { + return varg_uhl(ctx, v, bank); } if (rz_str_startswith(v, "fsr")) { - return varg_mm_hl(ctx, v); + return varg_hl(ctx, v, bank); } return VARG(v); } - -static RzILOpEffect *setg_mm(Pic18ILContext *ctx, const char *v, RzILOpPure *x) { +static RzILOpEffect *setg_mm(Pic18ILContext *ctx, const char *v, RzILOpPure *x, ut8 bank) { if (RZ_STR_ISEMPTY(v)) { return NULL; } - if (rz_str_startswith(v, "indf")) { - char fsr[8]; - long n = strtol(v + 4, NULL, 0); - rz_strf(fsr, "fsr%ld", n); - return STORE(UNSIGNED(24, varg_mm(ctx, fsr)), x); - } - if (rz_str_startswith(v, "postdec")) { - char fsr[8]; - long n = strtol(v + 7, NULL, 0); - rz_strf(fsr, "fsr%ld", n); - rz_warn_if_fail(ctx->eff.tag == ILOpEff_None); - ctx->eff.tag = ILOpEff_PostDec; - strcat(ctx->eff.fsr, fsr); - return STORE(UNSIGNED(24, varg_mm(ctx, fsr)), x); - } - if (rz_str_startswith(v, "postinc")) { - char fsr[8]; - long n = strtol(v + 7, NULL, 0); - rz_strf(fsr, "fsr%ld", n); - rz_warn_if_fail(ctx->eff.tag == ILOpEff_None); - ctx->eff.tag = ILOpEff_PostInc; - strcat(ctx->eff.fsr, fsr); - return STORE(UNSIGNED(24, varg_mm(ctx, fsr)), x); - } - if (rz_str_startswith(v, "predec")) { - char fsr[8]; - long n = strtol(v + 6, NULL, 0); - rz_strf(fsr, "fsr%ld", n); - rz_warn_if_fail(ctx->eff.tag == ILOpEff_None); - ctx->eff.tag = ILOpEff_PreInc; - strcat(ctx->eff.fsr, fsr); - return STORE(UNSIGNED(24, varg_mm(ctx, fsr)), x); - } - if (rz_str_startswith(v, "plusw")) { - char fsr[8]; - long n = strtol(v + 5, NULL, 0); - rz_strf(fsr, "fsr%ld", n); - return STORE(UNSIGNED(24, ADD(varg_mm(ctx, fsr), UNSIGNED(16, varg_mm(ctx, "wreg")))), x); - } - bool f = false; - ut64 adr = ht_su_find((HtSU *)ctx->mm, v, &f); - if (f) { - return STORE(UN(24, adr), x); + RzILOpPure *adr = pic18_regadr(ctx, v, bank); + if (adr) { + return STORE(adr, x); } + ut8 b = pic18_status(v); if (b != 0xff) { - return setg_mm(ctx, "status", bit_set1(varg_mm(ctx, "status"), b, x)); - } - if (RZ_STR_EQ(v, "tblptr")) { - return setg_mm_uhl(ctx, "tblptru", "tblptrh", "tblptrl", x); + return setg_mm(ctx, "status", bit_set1(varg_mm(ctx, "status", bank), b, x), bank); } - if (RZ_STR_EQ(v, "tos")) { - return setg_mm_uhl(ctx, "tosu", "tosh", "tosl", x); + if (RZ_STR_EQ(v, "tblptr") || RZ_STR_EQ(v, "tos")) { + return setg_uhl(ctx, v, x, bank); } if (rz_str_startswith(v, "fsr")) { - return setg_mm_hl(ctx, v, x); + return setg_hl(ctx, v, x, bank); } return SETG(v, x); } #undef VARG #undef SETG -#define VARG(x) varg_mm(ctx, x) -#define SETG(v, x) setg_mm(ctx, v, x) +#define VARG(x) varg_mm(ctx, x, 0) +#define SETG(v, x) setg_mm(ctx, v, x, 0) #define K (ctx->op->k) #define D (ctx->op->d) @@ -230,10 +185,10 @@ static RzILOpEffect *setg_mm(Pic18ILContext *ctx, const char *v, RzILOpPure *x) static RzILOpEffect *set_dest(Pic18ILContext *ctx, RzILOpPure *x) { const char *fsr = ctx->op->d ? pic18_regname(F) : RW; if (ctx->op->a) { - ut64 adr = pic18_regadr(ctx, fsr); - if (adr != UT64_MAX) { + RzILOpPure *adr = pic18_regadr(ctx, fsr, 0); + if (adr != NULL) { return STORE( - ADD(MUL(UNSIGNED(24, LOGAND(VARG("bsr"), U8(0x0f))), UN(24, 0x100)), UN(24, adr)), + ADD(MUL(UNSIGNED(24, LOGAND(VARG("bsr"), U8(0x0f))), UN(24, 0x100)), adr), x); } return NULL; @@ -513,8 +468,14 @@ static RzILOpEffect *pic18_il_op(Pic18ILContext *ctx) { case PIC18_OPCODE_LFSR: return op_lfsr(ctx); case PIC18_OPCODE_MOVF: return set_dest_status(ctx, VRF); - case PIC18_OPCODE_MOVFF: - return SETG(pic18_regname(ctx->op->d), VARG(pic18_regname(ctx->op->s))); + case PIC18_OPCODE_MOVFF: { + char s[16], d[16]; + const char *rs = pic18_regname_extra(ctx->op->s, s); + const char *rd = pic18_regname_extra(ctx->op->d, d); + return setg_mm(ctx, rd, + varg_mm(ctx, rs, 0), + 0); + } case PIC18_OPCODE_MOVLB: return SETG("bsr", LOGOR(U8(K), LOGAND(VARG("bsr"), U8(0xf0)))); case PIC18_OPCODE_MOVLW: diff --git a/librz/arch/isa/pic/pic_midrange_il.inc b/librz/arch/isa/pic/pic_midrange_il.inc index fbfa0508fd1..e8b137feca6 100644 --- a/librz/arch/isa/pic/pic_midrange_il.inc +++ b/librz/arch/isa/pic/pic_midrange_il.inc @@ -123,9 +123,9 @@ static const char *RFSR(ut8 n) { #define BITN(x, n) IS_ZERO(UNSIGNED(1, SHIFTR0(x, U32(n)))) // overflow is not used in status register but just keeping this for future "maybe" use -#define CHECK_OVERFLOW(x, y, res) AND(XOR(MSB(x), MSB(res)), XOR(MSB(y), MSB(DUP(res)))) -#define CHECK_CARRY(x, y, res) OR(AND(MSB(x), MSB(y)), AND(OR(MSB(DUP(x)), MSB(DUP(y))), INV(MSB(res)))) -#define CHECK_BORROW(x, y, res) OR(OR(AND(INV(MSB(x)), MSB(y)), AND(INV(MSB(DUP(x))), MSB(res))), AND(MSB(DUP(x)), AND(MSB(DUP(y)), MSB(DUP(res))))) +#define CHECK_OVERFLOW(x, y, res) AND(XOR(MSB(x), MSB(res)), XOR(MSB(y), MSB(DUP(res)))) +#define CHECK_CARRY(x, y, res) OR(AND(MSB(x), MSB(y)), AND(OR(MSB(DUP(x)), MSB(DUP(y))), INV(MSB(res)))) +#define CHECK_BORROW(x, y, res) OR(OR(AND(INV(MSB(x)), MSB(y)), AND(INV(MSB(DUP(x))), MSB(res))), AND(MSB(DUP(x)), AND(MSB(DUP(y)), MSB(DUP(res))))) #define CHECK_DIGIT_CARRY(x, y, res) OR(AND(BITN(x, 3), BITN(y, 3)), AND(OR(BITN(DUP(x), 3), BITN(DUP(y), 3)), INV(BITN(res, 3)))) #define CHECK_DIGIT_BORROW(x, y, res) OR( \ OR(AND(INV(BITN(x, 3)), BITN(y, 3)), AND(INV(BITN(DUP(x), 3)), BITN(res, 3))), \ diff --git a/librz/arch/isa/pic/pic_pic18.c b/librz/arch/isa/pic/pic_pic18.c index b481a421290..fdb5cc4da4e 100644 --- a/librz/arch/isa/pic/pic_pic18.c +++ b/librz/arch/isa/pic/pic_pic18.c @@ -144,7 +144,7 @@ static const char *pic18_SFRs[] = { [0xFD7 - 0xF80] = "tmr0h", [0xFD6 - 0xF80] = "tmr0l", [0xFD5 - 0xF80] = "t0con", - [0xFD4 - 0xF80] = "—", + [0xFD4 - 0xF80] = "0xd4", [0xFD3 - 0xF80] = "osccon", [0xFD2 - 0xF80] = "lvdcon", [0xFD1 - 0xF80] = "wdtcon", @@ -164,66 +164,66 @@ static const char *pic18_SFRs[] = { [0xFC3 - 0xF80] = "adresl", [0xFC2 - 0xF80] = "adcon0", [0xFC1 - 0xF80] = "adcon1", - [0xFC0 - 0xF80] = "—", + [0xFC0 - 0xF80] = "0xc0", [0xFBF - 0xF80] = "ccpr1h", [0xFBE - 0xF80] = "ccpr1l", [0xFBD - 0xF80] = "ccp1con", [0xFBC - 0xF80] = "ccpr2h", [0xFBB - 0xF80] = "ccpr2l", [0xFBA - 0xF80] = "ccp2con", - [0xFB9 - 0xF80] = "—", - [0xFB8 - 0xF80] = "—", - [0xFB7 - 0xF80] = "—", - [0xFB6 - 0xF80] = "—", - [0xFB5 - 0xF80] = "—", - [0xFB4 - 0xF80] = "—", + [0xFB9 - 0xF80] = "0xb9", + [0xFB8 - 0xF80] = "0xb8", + [0xFB7 - 0xF80] = "0xb7", + [0xFB6 - 0xF80] = "0xb6", + [0xFB5 - 0xF80] = "0xb5", + [0xFB4 - 0xF80] = "0xb4", [0xFB3 - 0xF80] = "tmr3h", [0xFB2 - 0xF80] = "tmr3l", [0xFB1 - 0xF80] = "t3con", - [0xFB0 - 0xF80] = "—", + [0xFB0 - 0xF80] = "0xb0", [0xFAF - 0xF80] = "spbrg", [0xFAE - 0xF80] = "rcreg", [0xFAD - 0xF80] = "txreg", [0xFAC - 0xF80] = "txsta", [0xFAB - 0xF80] = "rcsta", - [0xFAA - 0xF80] = "—", - [0xFA9 - 0xF80] = "—", - [0xFA8 - 0xF80] = "—", - [0xFA7 - 0xF80] = "—", - [0xFA6 - 0xF80] = "—", - [0xFA5 - 0xF80] = "—", - [0xFA4 - 0xF80] = "—", - [0xFA3 - 0xF80] = "—", + [0xFAA - 0xF80] = "0xaa", + [0xFA9 - 0xF80] = "0xa9", + [0xFA8 - 0xF80] = "0xa8", + [0xFA7 - 0xF80] = "0xa7", + [0xFA6 - 0xF80] = "0xa6", + [0xFA5 - 0xF80] = "0xa5", + [0xFA4 - 0xF80] = "0xa4", + [0xFA3 - 0xF80] = "0xa3", [0xFA2 - 0xF80] = "ipr2", [0xFA1 - 0xF80] = "pir2", [0xFA0 - 0xF80] = "pie2", [0xF9F - 0xF80] = "ipr1", [0xF9E - 0xF80] = "pir1", [0xF9D - 0xF80] = "pie1", - [0xF9C - 0xF80] = "—", - [0xF9B - 0xF80] = "—", - [0xF9A - 0xF80] = "—", - [0xF99 - 0xF80] = "—", - [0xF98 - 0xF80] = "—", - [0xF97 - 0xF80] = "—", + [0xF9C - 0xF80] = "0x9c", + [0xF9B - 0xF80] = "0x9b", + [0xF9A - 0xF80] = "0x9a", + [0xF99 - 0xF80] = "0x99", + [0xF98 - 0xF80] = "0x98", + [0xF97 - 0xF80] = "0x97", [0xF96 - 0xF80] = "trise", [0xF95 - 0xF80] = "trisd", [0xF94 - 0xF80] = "trisc", [0xF93 - 0xF80] = "trisb", [0xF92 - 0xF80] = "trisa", - [0xF91 - 0xF80] = "—", - [0xF90 - 0xF80] = "—", - [0xF8F - 0xF80] = "—", - [0xF8E - 0xF80] = "—", + [0xF91 - 0xF80] = "0x91", + [0xF90 - 0xF80] = "0x90", + [0xF8F - 0xF80] = "0x8f", + [0xF8E - 0xF80] = "0x8e", [0xF8D - 0xF80] = "late", [0xF8C - 0xF80] = "latd", [0xF8B - 0xF80] = "latc", [0xF8A - 0xF80] = "latb", [0xF89 - 0xF80] = "lata", - [0xF88 - 0xF80] = "—", - [0xF87 - 0xF80] = "—", - [0xF86 - 0xF80] = "—", - [0xF85 - 0xF80] = "—", + [0xF88 - 0xF80] = "0x88", + [0xF87 - 0xF80] = "0x87", + [0xF86 - 0xF80] = "0x86", + [0xF85 - 0xF80] = "0x85", [0xF84 - 0xF80] = "porte", [0xF83 - 0xF80] = "portd", [0xF82 - 0xF80] = "portc", @@ -363,9 +363,6 @@ static const char *pic18_GPRs[] = { }; const char *pic18_regname(size_t index) { - if (index > 0xf00 && index <= 0xfff) { - return pic18_regname(index % 0x100); - } if (index <= 0xff && index >= 0x80) { return pic18_SFRs[index - 0x80]; } @@ -376,6 +373,17 @@ const char *pic18_regname(size_t index) { return NULL; } +const char *pic18_regname_extra(size_t index, char *regname) { + if (index <= 0xff) { + return pic18_regname(index); + } + if (index >= 0xf80 && index <= 0xfff) { + return pic18_regname(index % 0x100); + } + sprintf(regname, "0x%zx", index); + return regname; +} + static const char *status_bits[] = { "c", "dc", @@ -505,9 +513,14 @@ bool pic18_disasm_op(Pic18Op *op, ut64 addr, const ut8 *buff, ut64 len) { case K20S_T: rz_strf(op->operands, "0x%x, %d", op->k << 1, op->s); break; - case SD_T: - rz_strf(op->operands, "%s, %s", pic18_regname(op->s), pic18_regname(op->d)); + case SD_T: { + char s[16]; + char d[16]; + rz_strf(op->operands, "%s, %s", + pic18_regname_extra(op->s, s), + pic18_regname_extra(op->d, d)); break; + } case S_T: rz_strf(op->operands, "%d", op->s); break; diff --git a/librz/arch/isa/pic/pic_pic18.h b/librz/arch/isa/pic/pic_pic18.h index 455339c61b6..16cfc4f15f1 100644 --- a/librz/arch/isa/pic/pic_pic18.h +++ b/librz/arch/isa/pic/pic_pic18.h @@ -135,6 +135,7 @@ typedef struct { } Pic18Op; const char *pic18_regname(size_t index); +const char *pic18_regname_extra(size_t index, char *regname); ut8 pic18_status(const char *name); bool pic18_disasm_op(Pic18Op *op, ut64 addr, const ut8 *buff, ut64 len); int pic_pic18_disassemble(RzAsm *a, RzAsmOp *asm_op, const ut8 *b, int l); diff --git a/librz/arch/p/analysis/analysis_pic.c b/librz/arch/p/analysis/analysis_pic.c index e1594955c7e..cdfa3fb262d 100644 --- a/librz/arch/p/analysis/analysis_pic.c +++ b/librz/arch/p/analysis/analysis_pic.c @@ -21,14 +21,13 @@ static bool pic_init(void **user) { } ctx->init_done = false; ctx->pic18_mm = ht_su_new(HT_STR_CONST); - char k[32]; - for (int i = 0; i < 0x100; ++i) { + for (int i = 0; i < 0x80; ++i) { const char *regname = pic18_regname(i); ht_su_insert(ctx->pic18_mm, regname, i); - for (int bank = 1; bank < 0x10; ++bank) { - rz_strf(k, "%s_%02x", regname, bank); - ht_su_insert(ctx->pic18_mm, k, bank * 0x100 + i); - } + } + for (int i = 0x80; i < 0x100; ++i) { + const char *regname = pic18_regname(i); + ht_su_insert(ctx->pic18_mm, regname, i + 0xf00); } *user = ctx; return true; diff --git a/test/db/analysis/pic b/test/db/analysis/pic index a81f815af72..5b8cd3f2c44 100644 --- a/test/db/analysis/pic +++ b/test/db/analysis/pic @@ -108,5 +108,6 @@ adcon0 = 0x00 stkptr = 0x00 _sram = 0x00 _stack = 0x00 +_skip = 0x00 EOF RUN diff --git a/test/db/asm/pic_pic18_8 b/test/db/asm/pic_pic18_8 index a6c3c5f7448..3035ef412eb 100644 --- a/test/db/asm/pic_pic18_8 +++ b/test/db/asm/pic_pic18_8 @@ -1,5 +1,5 @@ d "addlw 0x12" 120f -d "addwf 0xd1, 0, 1" d125 +d "addwf wdtcon, 0, 1" d125 d "addwfc 0x35, 1, 0" 3522 d "andwf 0x85, 1, 1" 8517 d "bcf 0x42, 7, 1" 429f @@ -10,7 +10,7 @@ d "clrf 0x15, 0" 156a d "comf 0x48, 0, 0" 481c d "cpfseq 0x71, 1" 7163 d "cpfsgt 0x62, 0" 6264 -d "cpfslt 0xc4, 0" c460 +d "cpfslt adresh, 0" c460 d "goto 0x274e" a7ef13f0 d "invalid" 02 dB "invalid" 0200