From 7d6f23bd026522905d32524e3bbb8c4dcce53e4e Mon Sep 17 00:00:00 2001 From: billow Date: Thu, 16 May 2024 06:01:25 +0800 Subject: [PATCH] Add pic16 tests --- librz/arch/isa/pic/pic_il.inc | 3 +- librz/arch/isa/pic/pic_midrange_analysis.c | 23 +- librz/arch/isa/pic/pic_midrange_il.inc | 193 ++++++----- test/db/asm/pic_pic16_8 | 384 +++++++++++++++++++++ 4 files changed, 506 insertions(+), 97 deletions(-) diff --git a/librz/arch/isa/pic/pic_il.inc b/librz/arch/isa/pic/pic_il.inc index 077fbec5d1b..1088acdab27 100644 --- a/librz/arch/isa/pic/pic_il.inc +++ b/librz/arch/isa/pic/pic_il.inc @@ -3,7 +3,8 @@ // SPDX-License-Identifier: LGPL-3.0-only static inline RzILOpPure *pure_slice(RzILOpPure *x, ut8 l, ut8 r) { - return LOGAND(SHIFTR0(x, U16(l)), U16(~(-1 << (r - l + 1)))); + rz_return_val_if_fail(l < r, NULL); + return UNSIGNED(r - l, SHIFTR0(x, U16(l))); } #define SEXT(B, x, b) ((st##B)(x << (B - b)) >> (B - b)) diff --git a/librz/arch/isa/pic/pic_midrange_analysis.c b/librz/arch/isa/pic/pic_midrange_analysis.c index 511a85a6f43..9a08a0fe3a3 100644 --- a/librz/arch/isa/pic/pic_midrange_analysis.c +++ b/librz/arch/isa/pic/pic_midrange_analysis.c @@ -185,27 +185,28 @@ char *pic_midrange_get_reg_profile(RzAnalysis *a) { "=A1 portb\n" "gpr indf0 .8 0 0\n" "gpr indf1 .8 1 0\n" - "gpr pcl .8 2 0\n" + "gpr pcl .8 2 0\n" "gpr status .8 3 0\n" - "flg c .1 3.0 0\n" - "flg dc .1 3.1 0\n" - "flg z .1 3.2 0\n" - "flg pd .1 3.3 0\n" - "flg to .1 3.4 0\n" + "flg c .1 3.0 0\n" + "flg dc .1 3.1 0\n" + "flg z .1 3.2 0\n" + "flg pd .1 3.3 0\n" + "flg to .1 3.4 0\n" "gpr fsr0l .8 4 0\n" "gpr fsr0h .8 5 0\n" "gpr fsr1l .8 6 0\n" "gpr fsr1h .8 7 0\n" - "gpr bsr .8 8 0\n" + "gpr bsr .8 8 0\n" "gpr wreg .8 9 0\n" "gpr pclath .8 10 0\n" "gpr intcon .8 11 0\n" - "gpr pc .16 12 0\n" + "gpr pc .16 12 0\n" "gpr stkptr .8 14 0\n" "gpr _sram .32 15 0\n" "gpr _stack .32 19 0\n" - "gpr tos .8 21 0\n" - "gpr tris .8 22 0\n" - "gpr _bank .8 23 0\n"; + "gpr tosl .8 24 0\n" + "gpr tosh .8 25 0\n" + "gpr tris .8 26 0\n" + "gpr _bank .8 27 0\n"; return strdup(p); } diff --git a/librz/arch/isa/pic/pic_midrange_il.inc b/librz/arch/isa/pic/pic_midrange_il.inc index 8ff00e66ee3..7194e608bba 100644 --- a/librz/arch/isa/pic/pic_midrange_il.inc +++ b/librz/arch/isa/pic/pic_midrange_il.inc @@ -8,19 +8,19 @@ #include "pic_il.inc" enum { - INDF, - TMR0, + INDF0, + INDF1, PCL, STATUS, - FSR, - PORTA, - PORTB, - PORTC, - PORTD, - PORTE, + FSR0L, + FSR0H, + FSR1L, + FSR1H, + BSR, + WREG, PCLATH, INTCON, -}; +} GPRs; static ut16 OPTION_REG = 1; @@ -46,12 +46,19 @@ enum { IRP } STAUTS_Register; +static const ut16 STKPTR = 0xfed; +static const ut16 TOSL = 0xfee; +static const ut16 TOSH = 0xfef; + typedef struct pic_midrange_il_context_t { RzAnalysis *analysis; RzAnalysisOp *op; const Pic16Op *x; } PicMidrangeILContext; +static RzILOpPure *register_i(ut16 i); +static RzILOpEffect *set_register_i(ut16 i, RzILOpPure *x); + #define K (ctx->x->args.k) #define D (ctx->x->args.d) #define F (ctx->x->args.f) @@ -59,27 +66,50 @@ typedef struct pic_midrange_il_context_t { #define N (ctx->x->args.n) #define PC (ctx->x->addr) #define VPC (U16(PC)) -#define RW "wreg" -#define VRW (VARG(RW)) -static RzILOpPure *register_i(ut8 i) { +static const char *PIC16_FSR[] = { + "fsr0l", + "fsr0h", + "fsr1l", + "fsr1h", +}; + +static RzILOpPure *val_fsrn(ut8 n) { + rz_return_val_if_fail(n <= 1, NULL); + return APPEND(register_i(2 * n + FSR0L + 1), register_i(2 * n + FSR0L)); +} +static RzILOpEffect *set_fsrn(ut8 n, RzILOpPure *x) { + rz_return_val_if_fail(n <= 1, NULL); + return SEQ3( + SETL("__x", x), + set_register_i(2 * n + FSR0L + 1, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(8)))), + set_register_i(2 * n + FSR0L, UNSIGNED(8, VARL("__x")))); +} + +static RzILOpPure *val_bank() { + return VARG("_bank"); +} +static RzILOpEffect *set_bank() { + return SETG("_bank", LOGAND(register_i(BSR), U8(0x1f))); +} + +static RzILOpPure *register_i(ut16 i) { rz_warn_if_fail(i < 0x80); - if (i == INDF) { - return LOAD(register_i(FSR)); + if (i == INDF0 || i == INDF1) { + return LOAD(val_fsrn(i - INDF0)); } - return LOAD(ADD(U16(i), MUL(VARG("_bank"), U8(0x80)))); + return LOAD(ADD(U16(i), UNSIGNED(16, MUL(val_bank(), U8(0x80))))); } -static RzILOpEffect *set_register_i(ut8 i, RzILOpPure *x) { +static RzILOpEffect *set_register_i(ut16 i, RzILOpPure *x) { rz_warn_if_fail(i < 0x80); - if (i == INDF) { - return STORE(register_i(FSR), x); + if (i == INDF0 || i == INDF1) { + return STORE(val_fsrn(i - INDF0), x); } - RzILOpEffect *eff = STORE(ADD(U16(i), MUL(VARG("_bank"), U8(0x80))), x); - if (i == STATUS) { - return SEQ2(eff, - SETG("_bank", pure_slice(register_i(STATUS), RP0, RP1 + 1))); + RzILOpEffect *eff = STORE(ADD(U16(i), UNSIGNED(16, MUL(val_bank(), U8(0x80)))), x); + if (i == BSR) { + return SEQ2(eff, set_bank()); } return eff; } @@ -88,8 +118,15 @@ static RzILOpEffect *set_register_i(ut8 i, RzILOpPure *x) { #define VARGb(i, b) bit_get(register_i(i), b) #define SETGb(i, b, x) set_register_i(i, bit_set1(register_i(i), b, x)) +#define VRW register_i(WREG) +#define SET_W(x) set_register_i(WREG, x) #define VRF register_i(F) -#define SET_F(x) (set_register_i(F, x)) +#define SET_F(x) set_register_i(F, x) + +#define VTOS APPEND(LOAD(U16(TOSH)), LOAD(U16(TOSL))) +#define SET_TOS(x) SEQ3(SETL("__tos", x), \ + STORE(U16(TOSH), UNSIGNED(8, SHIFTR0(VARL("__tos"), U8(8)))), \ + STORE(U16(TOSL), UNSIGNED(8, VARL("__tos")))) static RzILOpPure *register_WF(PicMidrangeILContext *ctx) { rz_warn_if_fail(F < 0x80); @@ -97,7 +134,7 @@ static RzILOpPure *register_WF(PicMidrangeILContext *ctx) { } static RzILOpEffect *set_register_WF(PicMidrangeILContext *ctx, RzILOpPure *x) { rz_warn_if_fail(F < 0x80); - return D ? SET_F(x) : SETG(RW, x); + return D ? SET_F(x) : SET_W(x); } #define VRWF register_WF(ctx) #define SET_WF(x) (set_register_WF(ctx, x)) @@ -112,18 +149,6 @@ typedef RzILOpEffect *(*pic_midrange_il_handler)(PicMidrangeILContext *, ut16); #define INS_LEN 2 -static const char *RFSR(ut8 n) { - static const char *FSR_names[] = { - "fsr0", "fsr1" - }; - if (n >= RZ_ARRAY_SIZE(FSR_names)) { - return NULL; - } - return FSR_names[n]; -} - -#define VRFSR(n) VARG(RFSR(n)) - /** * Handle C, DC & Z flags for the previous operation. * To be used after an arithmetic operation. @@ -144,14 +169,14 @@ RzILOpEffect *pic_midrange_il_set_arithmetic_flags(PicMidrangeILContext *ctx, RzILOpBool *dcf = NULL; if (add) { cf = CHECK_CARRY(x, y, res); - dcf = CHECK_DIGIT_CARRY(x, y, res); + dcf = CHECK_DIGIT_CARRY(DUP(x), DUP(y), DUP(res)); } else { // sub cf = CHECK_BORROW(x, y, res); - dcf = CHECK_DIGIT_BORROW(x, y, res); + dcf = CHECK_DIGIT_BORROW(DUP(x), DUP(y), DUP(res)); } // get zero flag - RzILOpBool *zf = IS_ZERO(res); + RzILOpBool *zf = IS_ZERO(DUP(res)); return SEQ3( SETGb(STATUS, C, cf), @@ -179,9 +204,9 @@ IL_LIFTER_IMPL(NOP) { * Status affected : C, DC, Z * */ IL_LIFTER_IMPL(ADDLW) { - RzILOpEffect *add_op = SETG(RW, ADD(VRW, U16(K))); + RzILOpEffect *add_op = SET_W(ADD(VRW, U8(K))); RzILOpEffect *set_status_op = - SET_STATUS_ADD(ctx, VARL("_1"), U16(K), VRW); + SET_STATUS_ADD(ctx, VARL("_1"), U8(K), VRW); return SEQ3(SETL("_1", VRW), add_op, set_status_op); @@ -194,17 +219,17 @@ IL_LIFTER_IMPL(ADDLW) { * Status affected : C, DC, Z * */ IL_LIFTER_IMPL(ADDWF) { - RzILOpEffect *add_op = SET_WF(ADD(VRW, U16(K))); + RzILOpEffect *add_op = SET_WF(ADD(VRW, U8(K))); RzILOpEffect *set_status_op = - SET_STATUS_ADD(ctx, VARL("_1"), U16(K), VRWF); - return SEQ3(SETL("_1", VARG(RW)), + SET_STATUS_ADD(ctx, VARL("_1"), U8(K), VRWF); + return SEQ3(SETL("_1", VRW), add_op, set_status_op); } IL_LIFTER_IMPL(ANDLW) { // TODO: set status Z - return SETG(RW, LOGAND(VARG(RW), U16(K))); + return SET_W(LOGAND(VRW, U8(K))); } /** @@ -215,7 +240,7 @@ IL_LIFTER_IMPL(ANDLW) { * */ IL_LIFTER_IMPL(ANDWF) { // TODO: set status Z - return SET_WF(LOGAND(VARG(RW), U16(K))); + return SET_WF(LOGAND(VRW, U8(K))); } IL_LIFTER_IMPL(BCF) { @@ -227,17 +252,17 @@ IL_LIFTER_IMPL(BSF) { } IL_LIFTER_IMPL(BTFSC) { - return BRANCH(bit_get(VRF, B), NOP(), JMP(U32(PC + INS_LEN * 2))); + return BRANCH(bit_get(VRF, B), NOP(), JMP(U16(PC + INS_LEN * 2))); } IL_LIFTER_IMPL(BTFSS) { - return BRANCH(bit_get(VRF, B), JMP(U32(PC + INS_LEN * 2)), NOP()); + return BRANCH(bit_get(VRF, B), JMP(U16(PC + INS_LEN * 2)), NOP()); } IL_LIFTER_IMPL(CALL) { return SEQ2( - SETG("tos", U16(PC + INS_LEN)), - JMP(LOGOR(U16(K), SHIFTL0(pure_slice(register_i(PCLATH), 3, 4), U16(11))))); + SET_TOS(U16(PC + INS_LEN)), + JMP(LOGOR(U16(K), SHIFTL0(UNSIGNED(16, pure_slice(register_i(PCLATH), 3, 4)), U16(11))))); } IL_LIFTER_IMPL(CLRF) { @@ -248,7 +273,7 @@ IL_LIFTER_IMPL(CLRF) { IL_LIFTER_IMPL(CLR) { return SEQ2( - SETG(RW, U8(0)), + SET_W(U8(0)), SETGb(STATUS, Z, IL_TRUE)); } @@ -264,31 +289,31 @@ IL_LIFTER_IMPL(COMF) { IL_LIFTER_IMPL(DECF) { return SEQ2( - SET_WF(SUB(VRF, U16(1))), + SET_WF(SUB(VRF, U8(1))), SETGb(STATUS, Z, IS_ZERO(VRWF))); } IL_LIFTER_IMPL(DECFSZ) { return SEQ2( - SET_WF(SUB(VRF, U16(1))), + SET_WF(SUB(VRF, U8(1))), BRANCH(IS_ZERO(VRWF), JMP(U16(PC + INS_LEN * 2)), NOP())); } IL_LIFTER_IMPL(GOTO) { - return JMP(LOGOR(U16(K), SHIFTL0(pure_slice(register_i(PCLATH), 3, 4), U16(11)))); + return JMP(LOGOR(U16(K), SHIFTL0(UNSIGNED(16, pure_slice(register_i(PCLATH), 3, 4)), U16(11)))); } IL_LIFTER_IMPL(INCF) { return SEQ2( - SET_WF(ADD(VRF, U16(1))), + SET_WF(ADD(VRF, U8(1))), SETGb(STATUS, Z, IS_ZERO(VRWF))); } IL_LIFTER_IMPL(INCFSZ) { return SEQ2( - SET_WF(ADD(VRF, U16(1))), + SET_WF(ADD(VRF, U8(1))), BRANCH(IS_ZERO(VRWF), JMP(U16(PC + INS_LEN * 2)), NOP())); @@ -296,7 +321,7 @@ IL_LIFTER_IMPL(INCFSZ) { IL_LIFTER_IMPL(IORLW) { return SEQ2( - SETG(RW, LOGOR(VRW, U16(K))), + SET_W(LOGOR(VRW, U8(K))), SETGb(STATUS, Z, IS_ZERO(VRW))); } @@ -307,7 +332,7 @@ IL_LIFTER_IMPL(IORWF) { } IL_LIFTER_IMPL(MOVLW) { - return SETG(RW, U16(K)); + return SET_W(U8(K)); } IL_LIFTER_IMPL(MOVF) { @@ -325,32 +350,32 @@ IL_LIFTER_IMPL(OPTION) { IL_LIFTER_IMPL(RETFIE) { return SEQ2( - SETG("tos", VPC), + SET_TOS(VPC), SETGb(INTCON, GIE, IL_TRUE)); } IL_LIFTER_IMPL(RETLW) { return SEQ2( - SETG(RW, U16(K)), - JMP(VARG("tos"))); + SET_W(U8(K)), + JMP(VTOS)); } IL_LIFTER_IMPL(RETURN) { - return JMP(VARG("tos")); + return JMP(VTOS); } IL_LIFTER_IMPL(RLF) { return SEQ3( SETL("_c", LOGAND(SHIFTR0(VRF, U8(7)), U8(1))), SET_WF(LOGOR(SHIFTL0(VRF, U8(1)), VARL("_c"))), - SETGb(STATUS, C, VARL("_v"))); + SETGb(STATUS, C, NON_ZERO(VARL("_c")))); } IL_LIFTER_IMPL(RRF) { return SEQ3( SETL("_c", LOGAND(VRF, U8(1))), SET_WF(LOGOR(SHIFTR0(VRF, U8(1)), SHIFTL0(VARL("_c"), U8(7)))), - SETGb(STATUS, C, VARL("_v"))); + SETGb(STATUS, C, NON_ZERO(VARL("_c")))); } IL_LIFTER_IMPL(SLEEP) { @@ -360,7 +385,7 @@ IL_LIFTER_IMPL(SLEEP) { IL_LIFTER_IMPL(SUBLW) { return SEQ3( SETL("_w", VRW), - SETG(RW, SUB(U8(K), VARL("_w"))), + SET_W(SUB(U8(K), VARL("_w"))), SET_STATUS_SUB(ctx, VARL("_w"), U8(K), VRW)); } @@ -388,7 +413,7 @@ IL_LIFTER_IMPL(TRIS) { * */ IL_LIFTER_IMPL(XORLW) { return SEQ2( - SETG(RW, LOGXOR(VRW, U8(K))), + SET_W(LOGXOR(VRW, U8(K))), SETGb(STATUS, Z, IS_ZERO(VRW))); } @@ -423,7 +448,7 @@ IL_LIFTER_IMPL(RESET) { } IL_LIFTER_IMPL(CALLW) { return SEQ2( - SETG("tos", U16(PC + INS_LEN)), + SET_TOS(U16(PC + INS_LEN)), JMP(LOGOR(U16(K), UNSIGNED(16, VRW)))); } IL_LIFTER_IMPL(BRW) { @@ -432,20 +457,20 @@ IL_LIFTER_IMPL(BRW) { IL_LIFTER_IMPL(MOVIW_1) { switch (ctx->x->instr & 0b11) { case 0x0: return SEQ3( - SETG(RFSR(N), ADD(VRFSR(N), U8(1))), - SETG(RW, VRFSR(N)), + set_fsrn(N, ADD(val_fsrn(N), U16(1))), + SET_W(LOAD(val_fsrn(N))), SETZ(VRW)); case 0x1: return SEQ3( - SETG(RFSR(N), SUB(VRFSR(N), U8(1))), - SETG(RW, VRFSR(N)), + set_fsrn(N, SUB(val_fsrn(N), U16(1))), + SET_W(LOAD(val_fsrn(N))), SETZ(VRW)); case 0x2: return SEQ3( - SETG(RW, VRFSR(N)), - SETG(RFSR(N), ADD(VRFSR(N), U8(1))), + SET_W(LOAD(val_fsrn(N))), + set_fsrn(N, ADD(val_fsrn(N), U16(1))), SETZ(VRW)); case 0x3: return SEQ3( - SETG(RW, VRFSR(N)), - SETG(RFSR(N), SUB(VRFSR(N), U8(1))), + SET_W(LOAD(val_fsrn(N))), + set_fsrn(N, SUB(val_fsrn(N), U16(1))), SETZ(VRW)); default: break; } @@ -453,20 +478,20 @@ IL_LIFTER_IMPL(MOVIW_1) { } IL_LIFTER_IMPL(MOVIW_2) { return SEQ2( - SETG(RW, LOAD(ADD(VRFSR(N), S8(SEXT(8, K, 6))))), + SET_W(LOAD(ADD(val_fsrn(N), S16(SEXT(16, K, 6))))), SETZ(VRW)); } IL_LIFTER_IMPL(MOVWI_1) { - return SETG(RFSR(N), VRW); + return STORE(val_fsrn(N), VRW); } IL_LIFTER_IMPL(MOVWI_2) { - return STORE(ADD(VRFSR(N), S8(SEXT(8, K, 6))), VRW); + return STORE(ADD(val_fsrn(N), S16(SEXT(16, K, 6))), VRW); } IL_LIFTER_IMPL(MOVLB) { // imm5? - return SETG("bsr", U8(K)); + return SETGi(BSR, U8(K)); } IL_LIFTER_IMPL(MOVLP) { // imm7? @@ -493,18 +518,18 @@ IL_LIFTER_IMPL(ASRF) { } IL_LIFTER_IMPL(SUBWFB) { return SEQ3( - SETL("_res", ADD(SUB(VRF, VRW), VARGb(STATUS, C))), + SETL("_res", ADD(SUB(VRF, VRW), BOOL_TO_BV(VARGb(STATUS, C), 8))), SET_STATUS_SUB(ctx, VRF, VRW, VARL("_res")), SET_WF(VARL("_res"))); } IL_LIFTER_IMPL(ADDWFC) { return SEQ3( - SETL("_res", ADD(ADD(VRF, VRW), VARGb(STATUS, C))), + SETL("_res", ADD(ADD(VRF, VRW), BOOL_TO_BV(VARGb(STATUS, C), 8))), SET_STATUS_ADD(ctx, VRF, VRW, VARL("_res")), SET_WF(VARL("_res"))); } IL_LIFTER_IMPL(ADDFSR) { - return SETG(RFSR(N), ADD(VRFSR(N), S8(SEXT(8, K, 6)))); + return set_fsrn(N, ADD(val_fsrn(N), S16(SEXT(8, K, 6)))); } IL_LIFTER_IMPL(BRA) { return JMP(U16(PC + SEXT(16, K, 9))); @@ -526,11 +551,9 @@ IL_LIFTER_IMPL(BRA) { #undef VRWF const char *pic16_reg_bindings[] = { - "wreg", - "tos", "tris", - "bsr", "_bank", + NULL, }; /** diff --git a/test/db/asm/pic_pic16_8 b/test/db/asm/pic_pic16_8 index e69de29bb2d..dc79487d5bc 100644 --- a/test/db/asm/pic_pic16_8 +++ b/test/db/asm/pic_pic16_8 @@ -0,0 +1,384 @@ +d "bsf 0x55, 256" 5515 0x000000 (store 0 (+ (bv 16 0x55) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x55) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "movwi 0x3f[FSR1]" ff3f 0x000000 (store 0 (+ (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0xffff)) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "nop" 0000 0x000000 nop +d "nop" 0000 0x00ff00 nop +d "reset" 0100 0x000000 (seq nop (jmp (bv 16 0x0))) +d "goto 0x2aa" aa2a 0x000000 (jmp (| (bv 16 0x2aa) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "bsf 0x55, 256" 5515 0x00ff00 (store 0 (+ (bv 16 0x55) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x55) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "movwi 0x3f[FSR1]" ff3f 0x00ff00 (store 0 (+ (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0xffff)) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "reset" 0100 0x00ff00 (seq nop (jmp (bv 16 0x0))) +d "goto 0x2aa" aa2a 0x00ff00 (jmp (| (bv 16 0x2aa) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "bsf 0x56, 256" 5615 0x000000 (store 0 (+ (bv 16 0x56) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x56) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "goto 0x2ab" ab2a 0x000000 (jmp (| (bv 16 0x2ab) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "bsf 0x56, 256" 5615 0x00ff00 (store 0 (+ (bv 16 0x56) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x56) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "goto 0x2ab" ab2a 0x00ff00 (jmp (| (bv 16 0x2ab) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x2ac" ac2a 0x000000 (jmp (| (bv 16 0x2ac) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "bsf 0x57, 256" 5715 0x000000 (store 0 (+ (bv 16 0x57) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x57) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "goto 0x2ac" ac2a 0x00ff00 (jmp (| (bv 16 0x2ac) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "bsf 0x57, 256" 5715 0x00ff00 (store 0 (+ (bv 16 0x57) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x57) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "goto 0x2ad" ad2a 0x000000 (jmp (| (bv 16 0x2ad) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x2ad" ad2a 0x00ff00 (jmp (| (bv 16 0x2ad) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "bsf 0x58, 256" 5815 0x000000 (store 0 (+ (bv 16 0x58) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x58) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "goto 0x2ae" ae2a 0x000000 (jmp (| (bv 16 0x2ae) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "bsf 0x58, 256" 5815 0x00ff00 (store 0 (+ (bv 16 0x58) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x58) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "bsf 0x59, 256" 5915 0x000000 (store 0 (+ (bv 16 0x59) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x59) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) +d "return" 0800 0x000000 (jmp (append (load 0 (bv 16 0xfef)) (load 0 (bv 16 0xfee)))) +d "return" 0800 0x00ff00 (jmp (append (load 0 (bv 16 0xfef)) (load 0 (bv 16 0xfee)))) +d "retfie" 0900 0x000000 (seq (set __tos (bv 16 0x0)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retfie" 0900 0x00ff00 (seq (set __tos (bv 16 0xff00)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "callw" 0a00 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "callw" 0a00 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "brw" 0b00 0x000000 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0x2) (bv 16 0x1) false))) +d "brw" 0b00 0x00ff00 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0xff02) (bv 16 0x1) false))) +d "moviw ++FSR0" 1000 0x0 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw ++FSR0" 1000 0xff00 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw --FSR1" 1100 0x0 (seq (set __x (- (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw --FSR1" 1100 0xff00 (seq (set __x (- (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw FSR0++" 1200 0x0 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw FSR0++" 1200 0xff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw FSR1--" 1300 0x0 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set __x (- (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw FSR1--" 1300 0xff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set __x (- (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw ++FSR0" 1400 0x0 (seq (set __x (+ (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "movwi ++FSR0" 1800 0x0 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi ++FSR0" 1800 0xff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi --FSR1" 1900 0x0 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi --FSR1" 1900 0xff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi FSR0++" 1a00 0x0 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi FSR0++" 1a00 0xff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi FSR1--" 1b00 0x0 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movlb 0x0" 2000 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x0" 2000 0x00ff00 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x1" 2100 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x1)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x1" 2100 0x00ff00 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x1)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x2" 2200 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x2)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x2" 2200 0x00ff00 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x2)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x3" 2300 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x3)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x3" 2300 0x00ff00 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x3)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x4" 2400 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x4)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "option" 6200 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "option" 6200 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "sleep" 6300 0x000000 nop +d "sleep" 6300 0x00ff00 nop +d "tris 0x0" 6400 0x000000 (set tris (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "tris 0x0" 6400 0x00ff00 (set tris (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "tris 0x1" 6500 0x000000 (set tris (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "tris 0x1" 6500 0x00ff00 (set tris (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "tris 0x2" 6600 0x000000 (set tris (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "tris 0x2" 6600 0x00ff00 (set tris (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "tris 0x3" 6700 0x000000 (set tris (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "tris 0x3" 6700 0x00ff00 (set tris (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf 0x0" 8000 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(load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "decf 0x1, w" 0103 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (- (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 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(cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x0))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "iorlw 0x1" 0138 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "iorlw 0x1" 0138 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "iorlw 0x2" 0238 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x2))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d 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