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rzil: switch event list to pvector (#3928)
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* switch from RzList to RzPvector

* Removed the commented line of code

* Removed tab to support clang format

* Added space after foreach statement to support clang format
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@wungfuh
wungfuh committed Oct 18, 2023
1 parent 1018286 commit 6b0fbb6
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Showing 5 changed files with 32 additions and 31 deletions.
5 changes: 3 additions & 2 deletions librz/core/cil.c
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Original file line number Diff line number Diff line change
Expand Up @@ -744,7 +744,7 @@ RZ_IPI bool rz_core_analysis_il_step_with_events(RzCore *core, PJ *pj) {
RzILVM *vm = core->analysis->il_vm->vm;

RzStrBuf *sb = NULL;
RzListIter *it;
void **it;
RzILEvent *evt;

bool evt_read = rz_config_get_b(core->config, "rzil.step.events.read");
Expand All @@ -759,7 +759,8 @@ RZ_IPI bool rz_core_analysis_il_step_with_events(RzCore *core, PJ *pj) {
if (!pj) {
sb = rz_strbuf_new("");
}
rz_list_foreach (vm->events, it, evt) {
rz_pvector_foreach (vm->events, it) {
evt = *it;
if (!evt_read && (evt->type == RZ_IL_EVENT_MEM_READ || evt->type == RZ_IL_EVENT_VAR_READ)) {
continue;
} else if (!evt_write && (evt->type != RZ_IL_EVENT_MEM_READ && evt->type != RZ_IL_EVENT_VAR_READ)) {
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4 changes: 2 additions & 2 deletions librz/il/il_vm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ RZ_API bool rz_il_vm_init(RzILVM *vm, ut64 start_addr, ut32 addr_size, bool big_
vm->addr_size = addr_size;
vm->big_endian = big_endian;

vm->events = rz_list_newf((RzListFree)rz_il_event_free);
vm->events = rz_pvector_new((RzPVectorFree)rz_il_event_free);
if (!vm->events) {
RZ_LOG_ERROR("RzIL: cannot allocate VM event list\n");
rz_il_vm_fini(vm);
Expand Down Expand Up @@ -108,7 +108,7 @@ RZ_API void rz_il_vm_fini(RzILVM *vm) {
rz_bv_free(vm->pc);
vm->pc = NULL;

rz_list_free(vm->events);
rz_pvector_free(vm->events);
vm->events = NULL;
}

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4 changes: 2 additions & 2 deletions librz/il/il_vm_eval.c
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Original file line number Diff line number Diff line change
Expand Up @@ -273,7 +273,7 @@ RZ_API void rz_il_vm_mem_storew(RzILVM *vm, RzILMemIndex index, RzBitVector *key
*/
RZ_API void rz_il_vm_event_add(RzILVM *vm, RzILEvent *evt) {
rz_return_if_fail(vm && vm->events && evt);
if (!rz_list_append(vm->events, evt)) {
if (!rz_pvector_push(vm->events, evt)) {
rz_warn_if_reached();
rz_il_event_free(evt);
}
Expand All @@ -283,7 +283,7 @@ RZ_API void rz_il_vm_event_add(RzILVM *vm, RzILEvent *evt) {
* Remove any recorded events from `vm->events`
*/
RZ_API void rz_il_vm_clear_events(RzILVM *vm) {
rz_list_purge(vm->events);
rz_pvector_clear(vm->events);
}

/**
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2 changes: 1 addition & 1 deletion librz/include/rz_il/rz_il_vm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ struct rz_il_vm_t {
RzBitVector *pc; ///< Program Counter of VM
RzILOpPureHandler *op_handler_pure_table; ///< Array of Handler, handler can be indexed by opcode
RzILOpEffectHandler *op_handler_effect_table; ///< Array of Handler, handler can be indexed by opcode
RzList /*<RzILEvent *>*/ *events; ///< List of events that has happened in the last step
RzPVector /*<RzILEvent *>*/ *events; ///< List of events that has happened in the last step
bool big_endian; ///< Sets the endianness of the memory reads/writes operations
};

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48 changes: 24 additions & 24 deletions test/unit/test_il_vm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -207,7 +207,7 @@ static bool test_rzil_vm_op_let() {
rz_pvector_free(vars);

// var and set for local pure vars should not emit events because everything is local
mu_assert_eq(rz_list_length(vm->events), 0, "no events");
mu_assert_eq(rz_pvector_len(vm->events), 0, "no events");

rz_il_vm_free(vm);
mu_end;
Expand Down Expand Up @@ -252,7 +252,7 @@ static bool test_rzil_vm_op_cast() {
mu_assert_eq(rz_bv_to_ut64(r), 0x1f42, "eval val");
rz_bv_free(r);

mu_assert_eq(rz_list_length(vm->events), 0, "no events");
mu_assert_eq(rz_pvector_len(vm->events), 0, "no events");

rz_il_vm_free(vm);
mu_end;
Expand All @@ -279,7 +279,7 @@ static bool test_rzil_vm_op_unsigned() {
mu_assert_eq(rz_bv_to_ut64(r), 0xf2, "eval val");
rz_bv_free(r);

mu_assert_eq(rz_list_length(vm->events), 0, "no events");
mu_assert_eq(rz_pvector_len(vm->events), 0, "no events");

rz_il_vm_free(vm);
mu_end;
Expand All @@ -306,7 +306,7 @@ static bool test_rzil_vm_op_signed() {
mu_assert_eq(rz_bv_to_ut64(r), 0x1ff2, "eval val");
rz_bv_free(r);

mu_assert_eq(rz_list_length(vm->events), 0, "no events");
mu_assert_eq(rz_pvector_len(vm->events), 0, "no events");

rz_il_vm_free(vm);
mu_end;
Expand All @@ -333,8 +333,8 @@ static bool test_rzil_vm_op_set() {
mu_assert_eq(rz_pvector_len(vars), 0, "cleanup");
rz_pvector_free(vars);

mu_assert_eq(rz_list_length(vm->events), 1, "events count");
RzILEvent *ev = rz_list_get_n(vm->events, 0);
mu_assert_eq(rz_pvector_len(vm->events), 1, "events count");
RzILEvent *ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_VAR_WRITE, "event type");
mu_assert_streq(ev->data.var_write.variable, "r1", "event var");
RzBitVector *ref = rz_bv_new_from_ut64(32, 0);
Expand Down Expand Up @@ -365,9 +365,9 @@ static bool test_rzil_vm_op_set() {
mu_assert_eq(rz_pvector_len(vars), 0, "cleanup");
rz_pvector_free(vars);

mu_assert_eq(rz_list_length(vm->events), 3, "events count");
mu_assert_eq(rz_pvector_len(vm->events), 3, "events count");

ev = rz_list_get_n(vm->events, 0);
ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_PC_WRITE, "event type"); // pc write done by the step
ref = rz_bv_new_from_ut64(8, 0);
mu_assert_true(rz_bv_eq(ev->data.pc_write.old_pc, ref), "old pc");
Expand All @@ -376,15 +376,15 @@ static bool test_rzil_vm_op_set() {
mu_assert_true(rz_bv_eq(ev->data.pc_write.new_pc, ref), "new pc");
rz_bv_free(ref);

ev = rz_list_get_n(vm->events, 1);
ev = rz_pvector_at(vm->events, 1);
mu_assert_eq(ev->type, RZ_IL_EVENT_VAR_READ, "event type");
mu_assert_streq(ev->data.var_write.variable, "r1", "event var");
ref = rz_bv_new_from_ut64(32, 42);
mu_assert_eq(ev->data.var_read.value->type, RZ_IL_TYPE_PURE_BITVECTOR, "event old value type");
mu_assert_true(rz_bv_eq(ev->data.var_read.value->data.bv, ref), "event value");
rz_bv_free(ref);

ev = rz_list_get_n(vm->events, 2);
ev = rz_pvector_at(vm->events, 2);
mu_assert_eq(ev->type, RZ_IL_EVENT_VAR_WRITE, "event type");
mu_assert_streq(ev->data.var_write.variable, "r1", "event var");
ref = rz_bv_new_from_ut64(32, 42);
Expand Down Expand Up @@ -555,8 +555,8 @@ static bool test_rzil_vm_op_load() {
mu_assert_eq(rz_bv_to_ut64(res), 0x42, "res value");
rz_bv_free(res);

mu_assert_eq(rz_list_length(vm->events), 1, "events count");
RzILEvent *ev = rz_list_get_n(vm->events, 0);
mu_assert_eq(rz_pvector_len(vm->events), 1, "events count");
RzILEvent *ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_MEM_READ, "event type");
RzBitVector *ref = rz_bv_new_from_ut64(16, 3);
mu_assert_true(rz_bv_eq(ev->data.mem_read.address, ref), "event addr");
Expand All @@ -574,8 +574,8 @@ static bool test_rzil_vm_op_load() {
mu_assert_eq(rz_bv_to_ut64(res), 0xaa, "res value (overflow)");
rz_bv_free(res);

mu_assert_eq(rz_list_length(vm->events), 1, "events count");
ev = rz_list_get_n(vm->events, 0);
mu_assert_eq(rz_pvector_len(vm->events), 1, "events count");
ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_MEM_READ, "event type");
ref = rz_bv_new_from_ut64(16, 100);
mu_assert_true(rz_bv_eq(ev->data.mem_read.address, ref), "event addr");
Expand Down Expand Up @@ -603,8 +603,8 @@ static bool test_rzil_vm_op_store() {
ut8 expect[] = { 0x10, 0x11, 0xab, 0x42, 0x14, 0x15 };
mu_assert_memeq(data, expect, sizeof(expect), "stored");

mu_assert_eq(rz_list_length(vm->events), 1, "events count");
RzILEvent *ev = rz_list_get_n(vm->events, 0);
mu_assert_eq(rz_pvector_len(vm->events), 1, "events count");
RzILEvent *ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_MEM_WRITE, "event type");
RzBitVector *ref = rz_bv_new_from_ut64(16, 2);
mu_assert_true(rz_bv_eq(ev->data.mem_write.address, ref), "event addr");
Expand Down Expand Up @@ -636,8 +636,8 @@ static bool test_rzil_vm_op_loadw_le() {
mu_assert_eq(rz_bv_to_ut64(res), 0x442, "res value");
rz_bv_free(res);

mu_assert_eq(rz_list_length(vm->events), 1, "events count");
RzILEvent *ev = rz_list_get_n(vm->events, 0);
mu_assert_eq(rz_pvector_len(vm->events), 1, "events count");
RzILEvent *ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_MEM_READ, "event type");
RzBitVector *ref = rz_bv_new_from_ut64(16, 3);
mu_assert_true(rz_bv_eq(ev->data.mem_read.address, ref), "event addr");
Expand Down Expand Up @@ -665,8 +665,8 @@ static bool test_rzil_vm_op_storew_le() {
ut8 expect[] = { 0x0, 0x1, 0xcd, 0xab, 0x4, 0x5 };
mu_assert_memeq(data, expect, sizeof(expect), "stored");

mu_assert_eq(rz_list_length(vm->events), 1, "events count");
RzILEvent *ev = rz_list_get_n(vm->events, 0);
mu_assert_eq(rz_pvector_len(vm->events), 1, "events count");
RzILEvent *ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_MEM_WRITE, "event type");
RzBitVector *ref = rz_bv_new_from_ut64(16, 2);
mu_assert_true(rz_bv_eq(ev->data.mem_write.address, ref), "event addr");
Expand Down Expand Up @@ -697,8 +697,8 @@ static bool test_rzil_vm_op_loadw_be() {
mu_assert_eq(rz_bv_len(res), 16, "res byte size");
mu_assert_eq(rz_bv_to_ut64(res), 0x4204, "res value");

mu_assert_eq(rz_list_length(vm->events), 1, "events count");
RzILEvent *ev = rz_list_get_n(vm->events, 0);
mu_assert_eq(rz_pvector_len(vm->events), 1, "events count");
RzILEvent *ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_MEM_READ, "event type");
RzBitVector *ref = rz_bv_new_from_ut64(16, 3);
mu_assert_true(rz_bv_eq(ev->data.mem_read.address, ref), "event addr");
Expand Down Expand Up @@ -727,8 +727,8 @@ static bool test_rzil_vm_op_storew_be() {
ut8 expect[] = { 0x0, 0x1, 0xab, 0xcd, 0x4, 0x5 };
mu_assert_memeq(data, expect, sizeof(expect), "stored");

mu_assert_eq(rz_list_length(vm->events), 1, "events count");
RzILEvent *ev = rz_list_get_n(vm->events, 0);
mu_assert_eq(rz_pvector_len(vm->events), 1, "events count");
RzILEvent *ev = rz_pvector_at(vm->events, 0);
mu_assert_eq(ev->type, RZ_IL_EVENT_MEM_WRITE, "event type");
RzBitVector *ref = rz_bv_new_from_ut64(16, 2);
mu_assert_true(rz_bv_eq(ev->data.mem_write.address, ref), "event addr");
Expand Down

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