diff --git a/librz/analysis/arch/arm/arm_accessors32.h b/librz/analysis/arch/arm/arm_accessors32.h
index b44ebfefa25..5ded7f07e28 100644
--- a/librz/analysis/arch/arm/arm_accessors32.h
+++ b/librz/analysis/arch/arm/arm_accessors32.h
@@ -22,10 +22,10 @@
 #define ISIMM(x)         (insn->detail->arm.operands[x].type == ARM_OP_IMM || insn->detail->arm.operands[x].type == ARM_OP_FP)
 #define ISREG(x)         (insn->detail->arm.operands[x].type == ARM_OP_REG)
 #if CS_NEXT_VERSION >= 6
-#define ISPSRFLAGS(x)    (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR)
+#define ISPSRFLAGS(x) (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR)
 #endif
-#define ISMEM(x)         (insn->detail->arm.operands[x].type == ARM_OP_MEM)
-#define ISFPIMM(x)       (insn->detail->arm.operands[x].type == ARM_OP_FP)
+#define ISMEM(x)   (insn->detail->arm.operands[x].type == ARM_OP_MEM)
+#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP)
 
 #define LSHIFT(x)       insn->detail->arm.operands[x].mem.lshift
 #define LSHIFT2(x)      insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
@@ -38,11 +38,11 @@
 #define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value
 
 #if CS_NEXT_VERSION >= 6
-#define CS_ARMCC(CC) ARMCC_##CC
+#define CS_ARMCC(CC)    ARMCC_##CC
 #define ISWRITEBACK32() insn->detail->writeback
 #define ISPOSTINDEX32() insn->detail->arm.post_index
 #else
-#define CS_ARMCC(CC) ARM_CC_##CC
+#define CS_ARMCC(CC)    ARM_CC_##CC
 #define ISWRITEBACK32() insn->detail->arm.writeback
 #define ISPOSTINDEX32() (((OPCOUNT() == 3) && (ISIMM(2) || ISREG(2)) && (ISWRITEBACK32())) || ((OPCOUNT() == 4) && (ISIMM(3) || ISREG(3)) && (ISWRITEBACK32())))
 #endif
diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c
index b361d9e4837..5d2dbc5cad9 100644
--- a/librz/analysis/p/analysis_arm_cs.c
+++ b/librz/analysis/p/analysis_arm_cs.c
@@ -15,42 +15,41 @@
 #include "../../asm/arch/arm/arm_it.h"
 
 #if CS_NEXT_VERSION < 6
-inline static const char *ARMCondCodeToString(arm_cc cc)
-{
-  switch (cc) {
-  default:
-    assert(0 && "Unknown condition code");
-  case ARM_CC_EQ:
-    return "eq";
-  case ARM_CC_NE:
-    return "ne";
-  case ARM_CC_HS:
-    return "hs";
-  case ARM_CC_LO:
-    return "lo";
-  case ARM_CC_MI:
-    return "mi";
-  case ARM_CC_PL:
-    return "pl";
-  case ARM_CC_VS:
-    return "vs";
-  case ARM_CC_VC:
-    return "vc";
-  case ARM_CC_HI:
-    return "hi";
-  case ARM_CC_LS:
-    return "ls";
-  case ARM_CC_GE:
-    return "ge";
-  case ARM_CC_LT:
-    return "lt";
-  case ARM_CC_GT:
-    return "gt";
-  case ARM_CC_LE:
-    return "le";
-  case ARM_CC_AL:
-    return "al";
-  }
+inline static const char *ARMCondCodeToString(arm_cc cc) {
+	switch (cc) {
+	default:
+		assert(0 && "Unknown condition code");
+	case ARM_CC_EQ:
+		return "eq";
+	case ARM_CC_NE:
+		return "ne";
+	case ARM_CC_HS:
+		return "hs";
+	case ARM_CC_LO:
+		return "lo";
+	case ARM_CC_MI:
+		return "mi";
+	case ARM_CC_PL:
+		return "pl";
+	case ARM_CC_VS:
+		return "vs";
+	case ARM_CC_VC:
+		return "vc";
+	case ARM_CC_HI:
+		return "hi";
+	case ARM_CC_LS:
+		return "ls";
+	case ARM_CC_GE:
+		return "ge";
+	case ARM_CC_LT:
+		return "lt";
+	case ARM_CC_GT:
+		return "gt";
+	case ARM_CC_LE:
+		return "le";
+	case ARM_CC_AL:
+		return "al";
+	}
 }
 #endif
 
diff --git a/librz/asm/arch/arm/arm_it.c b/librz/asm/arch/arm/arm_it.c
index 15951d0361b..126e71236d4 100644
--- a/librz/asm/arch/arm/arm_it.c
+++ b/librz/asm/arch/arm/arm_it.c
@@ -29,41 +29,40 @@ RZ_API void rz_arm_it_context_fini(RzArmITContext *ctx) {
 }
 
 #if CS_NEXT_VERSION < 6
-inline static arm_cc ARMCC_getOppositeCondition(arm_cc cc)
-{
-  switch (cc) {
-  default:
-    // llvm_unreachable("Unknown condition code");
-    assert(0);
-  case ARM_CC_EQ:
-    return ARM_CC_NE;
-  case ARM_CC_NE:
-    return ARM_CC_EQ;
-  case ARM_CC_HS:
-    return ARM_CC_LO;
-  case ARM_CC_LO:
-    return ARM_CC_HS;
-  case ARM_CC_MI:
-    return ARM_CC_PL;
-  case ARM_CC_PL:
-    return ARM_CC_MI;
-  case ARM_CC_VS:
-    return ARM_CC_VC;
-  case ARM_CC_VC:
-    return ARM_CC_VS;
-  case ARM_CC_HI:
-    return ARM_CC_LS;
-  case ARM_CC_LS:
-    return ARM_CC_HI;
-  case ARM_CC_GE:
-    return ARM_CC_LT;
-  case ARM_CC_LT:
-    return ARM_CC_GE;
-  case ARM_CC_GT:
-    return ARM_CC_LE;
-  case ARM_CC_LE:
-    return ARM_CC_GT;
-  }
+inline static arm_cc ARMCC_getOppositeCondition(arm_cc cc) {
+	switch (cc) {
+	default:
+		// llvm_unreachable("Unknown condition code");
+		assert(0);
+	case ARM_CC_EQ:
+		return ARM_CC_NE;
+	case ARM_CC_NE:
+		return ARM_CC_EQ;
+	case ARM_CC_HS:
+		return ARM_CC_LO;
+	case ARM_CC_LO:
+		return ARM_CC_HS;
+	case ARM_CC_MI:
+		return ARM_CC_PL;
+	case ARM_CC_PL:
+		return ARM_CC_MI;
+	case ARM_CC_VS:
+		return ARM_CC_VC;
+	case ARM_CC_VC:
+		return ARM_CC_VS;
+	case ARM_CC_HI:
+		return ARM_CC_LS;
+	case ARM_CC_LS:
+		return ARM_CC_HI;
+	case ARM_CC_GE:
+		return ARM_CC_LT;
+	case ARM_CC_LT:
+		return ARM_CC_GE;
+	case ARM_CC_GT:
+		return ARM_CC_LE;
+	case ARM_CC_LE:
+		return ARM_CC_GT;
+	}
 }
 #endif
 
diff --git a/librz/asm/arch/arm/armass.c b/librz/asm/arch/arm/armass.c
index 76540ea9d7b..29c78ebed23 100644
--- a/librz/asm/arch/arm/armass.c
+++ b/librz/asm/arch/arm/armass.c
@@ -5813,7 +5813,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) {
 						}
 						ao->o |= ((ret >> 16) & 0xff) << 8;
 						ao->o |= ((ret >> 8) & 0xff) << 16;
-						ao->o |= ((ret)&0xff) << 24;
+						ao->o |= ((ret) & 0xff) << 24;
 					} else {
 						RZ_LOG_ERROR("assembler: arm: %s: instruction does not accept a register as argument\n", ops[i].name);
 						return 0;
@@ -5839,7 +5839,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) {
 						dst /= 4;
 						ao->o |= ((dst >> 16) & 0xff) << 8;
 						ao->o |= ((dst >> 8) & 0xff) << 16;
-						ao->o |= ((dst)&0xff) << 24;
+						ao->o |= ((dst) & 0xff) << 24;
 						return 4;
 					} else {
 						ao->o |= (getreg(ao->a[0]) << 24);
@@ -5850,7 +5850,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) {
 					o |= ((n >> 12) & 0xf) << 8;
 					o |= ((n >> 8) & 0xf) << 20;
 					o |= ((n >> 4) & 0xf) << 16;
-					o |= ((n)&0xf) << 24;
+					o |= ((n) & 0xf) << 24;
 					ao->o |= o;
 				} break;
 				case TYPE_SWI:
diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c
index fe9a4fd40b3..c98802602b2 100644
--- a/librz/asm/p/asm_arm_cs.c
+++ b/librz/asm/p/asm_arm_cs.c
@@ -17,42 +17,41 @@ typedef struct arm_cs_context_t {
 } ArmCSContext;
 
 #if CS_NEXT_VERSION < 6
-inline static const char *ARMCondCodeToString(arm_cc cc)
-{
-  switch (cc) {
-  default:
-    assert(0 && "Unknown condition code");
-  case ARM_CC_EQ:
-    return "eq";
-  case ARM_CC_NE:
-    return "ne";
-  case ARM_CC_HS:
-    return "hs";
-  case ARM_CC_LO:
-    return "lo";
-  case ARM_CC_MI:
-    return "mi";
-  case ARM_CC_PL:
-    return "pl";
-  case ARM_CC_VS:
-    return "vs";
-  case ARM_CC_VC:
-    return "vc";
-  case ARM_CC_HI:
-    return "hi";
-  case ARM_CC_LS:
-    return "ls";
-  case ARM_CC_GE:
-    return "ge";
-  case ARM_CC_LT:
-    return "lt";
-  case ARM_CC_GT:
-    return "gt";
-  case ARM_CC_LE:
-    return "le";
-  case ARM_CC_AL:
-    return "al";
-  }
+inline static const char *ARMCondCodeToString(arm_cc cc) {
+	switch (cc) {
+	default:
+		assert(0 && "Unknown condition code");
+	case ARM_CC_EQ:
+		return "eq";
+	case ARM_CC_NE:
+		return "ne";
+	case ARM_CC_HS:
+		return "hs";
+	case ARM_CC_LO:
+		return "lo";
+	case ARM_CC_MI:
+		return "mi";
+	case ARM_CC_PL:
+		return "pl";
+	case ARM_CC_VS:
+		return "vs";
+	case ARM_CC_VC:
+		return "vc";
+	case ARM_CC_HI:
+		return "hi";
+	case ARM_CC_LS:
+		return "ls";
+	case ARM_CC_GE:
+		return "ge";
+	case ARM_CC_LT:
+		return "lt";
+	case ARM_CC_GT:
+		return "gt";
+	case ARM_CC_LE:
+		return "le";
+	case ARM_CC_AL:
+		return "al";
+	}
 }
 #endif