Controlling access to floating point and vector state from machine mode

[dramforever]

As mentioned in the issue I've posted about the privileged manual: riscv/riscv-isa-manual#832, mstatus.FS and mstatus.VS cannot actually be used to disable supervisor-mode access to floating point and vector state, because the two fields are aliases of sstatus.FS and sstatus.VS, and thus supervisor mode can turn these state on even if they are turned off in mstatus.

This differs from the requirements of mstateenN, which actually disables access in supervisor mode. This presents a problem with emulating the hypervisor extension in machine mode. As mentioned in the Smstateen spec, supporting emulation of the hypervisor extension is a goal of Smstateen:

Recall that the main reason the mstateen CSRs must exist is so machine level can emulate the hypervisor extension. When machine level isn’t emulating the hypervisor extension, it is likely there will be no need to keep any implemented mstateen bits zero.

But since neither mstatus nor mstateen controls supervisor mode FS and VS, in case the hypervisor extension emulated, all states except FS and VS in emulated-VS-mode can be controlled by an emulated-HS-mode hypervisor. The hypervisor extension does however mandate such control with HS-level sstatus.{FS,VS}. Please see linked privileged spec issue for why I think it is not possible to completely emulate the behavior of (HS-level) sstatus.FS and vsstatus.FS, even if machine mode software is aware of FS and VS.

Since that issue had not received any replies at time of writing this issue, I'm not sure if my analysis is correct, but I am pretty confident about it. Is it possible to fix it with Smstateen so at least future implementations allow full emulation of the hypervisor extension?