diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail
index 6478919ca..f0fdc7a38 100644
--- a/model/riscv_csr_map.sail
+++ b/model/riscv_csr_map.sail
@@ -176,6 +176,9 @@ mapping clause csr_name_map = 0x00F  <-> "vcsr"
 mapping clause csr_name_map = 0xC20  <-> "vl"
 mapping clause csr_name_map = 0xC21  <-> "vtype"
 mapping clause csr_name_map = 0xC22  <-> "vlenb"
+/* Smstateen csrs */
+mapping clause csr_name_map = 0x30C  <-> "mstateen0"
+mapping clause csr_name_map = 0x31C  <-> "mstateen0h"
 
 val csr_name : csreg -> string
 overload to_str = {csr_name}
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index f2980fb9e..e37310709 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -38,8 +38,10 @@ function readCSR csr : csreg -> xlenbits = {
     (0x305,  _) => get_mtvec(),
     (0x306,  _) => zero_extend(mcounteren.bits),
     (0x30A,  _) => menvcfg.bits[sizeof(xlen) - 1 .. 0],
+    (0x30C,  _) => mstateen0.bits()[sizeof(xlen) - 1 .. 0],
     (0x310, 32) => mstatush.bits,
     (0x31A, 32) => menvcfg.bits[63 .. 32],
+    (0x31C, 32) => mstateen0.bits()[63 .. 32],
     (0x320,  _) => zero_extend(mcountinhibit.bits),
 
     (0x340,  _) => mscratch,
@@ -125,8 +127,11 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
     (0x306,  _) => { mcounteren = legalize_mcounteren(mcounteren, value); Some(zero_extend(mcounteren.bits)) },
     (0x30A, 32) => { menvcfg = legalize_menvcfg(menvcfg, menvcfg.bits[63 .. 32] @ value); Some(menvcfg.bits[31 .. 0]) },
     (0x30A, 64) => { menvcfg = legalize_menvcfg(menvcfg, value); Some(menvcfg.bits) },
+    (0x30C, 32) => { mstateen0 = legalize_mstateen0(mstateen0, mstateen0.bits()[63 .. 32] @ value); Some(mstateen0.bits()[31 .. 0]) },
+    (0x30C, 64) => { mstateen0 = legalize_mstateen0(mstateen0, value); Some(mstateen0.bits()) },
     (0x310, 32) => { Some(mstatush.bits) }, // ignore writes for now
     (0x31A, 32) => { menvcfg = legalize_menvcfg(menvcfg, value @ menvcfg.bits[31 .. 0]); Some(menvcfg.bits[63 .. 32]) },
+    (0x31C, 32) => { mstateen0 = legalize_mstateen0(mstateen0, value @ mstateen0.bits()[31 .. 0]); Some(mstateen0.bits()[63 .. 32]) },
     (0x320,  _) => { mcountinhibit = legalize_mcountinhibit(mcountinhibit, value); Some(zero_extend(mcountinhibit.bits)) },
     (0x340,  _) => { mscratch = value; Some(mscratch) },
     (0x341,  _) => { Some(set_xret_target(Machine, value)) },
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 5bf2ce90d..eac9e57cd 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -31,8 +31,10 @@ function is_CSR_defined (csr : csreg) -> bool =
     0x305 => true, // mtvec
     0x306 => haveUsrMode(), // mcounteren
     0x30A => haveUsrMode(), // menvcfg
+    0x30C => haveSupMode() & haveSmstateen(), // mstateen0
     0x310 => sizeof(xlen) == 32, // mstatush
     0x31A => haveUsrMode() & (sizeof(xlen) == 32), // menvcfgh
+    0x31C => haveSupMode() & (sizeof(xlen) == 32) & haveSmstateen(), // mstateen0h
     0x320 => true, // mcountinhibit
     /* machine mode: trap handling */
     0x340 => true, // mscratch
@@ -117,7 +119,6 @@ function check_Counteren(csr : csreg, p : Privilege) -> bool =
               else true
   }
 
-
 /* Seed may only be accessed if we are doing a write, and access has been
  * allowed in the current priv mode
  */
@@ -525,6 +526,8 @@ function init_sys() -> unit = {
 
   menvcfg.bits = zero_extend(0b0);
   senvcfg.bits = zero_extend(0b0);
+  mstateen0->bits() = zero_extend(0b0);
+
   /* initialize vector csrs */
   elen               = 0b1; /* ELEN=64 as the common case */
   vlen               = 0b0100; /* VLEN=512 as a default value */
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 6eb174189..1cff633d5 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -175,6 +175,12 @@ function haveZicond() -> bool = true
 /* Zabha extension support */
 function haveZabha() -> bool = true
 
+/* Smstateen extension support */
+function haveSmstateen() -> bool = true
+
+/* Ssqosid extension support */
+function haveSsqosid() -> bool = true
+
 /*
  * Illegal values legalized to least privileged mode supported.
  * Note: the only valid combinations of supported modes are M, M+U, M+S+U.
@@ -865,6 +871,24 @@ function is_fiom_active() -> bool = {
     User => (menvcfg[FIOM] | senvcfg[FIOM]) == 0b1,
   }
 }
+
+bitfield Mstateen0 : bits(64) = {
+  // controls to new state introduced by the following small extensions of Priv-1.14-era:
+  PRIV114  : 55
+}
+register mstateen0 : Mstateen0
+// If any extension controlled by PRIV114 bit in mstateen0 is present
+// then PRIV114 bit is present
+function havePriv114Extensions() -> bool = {
+  haveSsqosid()
+}
+function legalize_mstateen0(o : Mstateen0, v : bits(64)) -> Mstateen0 = {
+  let v = Mk_Mstateen0(v);
+  let o = update_PRIV114(o, if havePriv114Extensions() then v.PRIV114() else 0b0);
+  // Other extensions are not implemented yet so all other fields are read only zero.
+  o
+}
+
 /* vector csrs */
 register vstart : bits(16) /* use the largest possible length of vstart */
 register vxsat  : bits(1)