From 057890ddd13bcb43a006cb34bb4cda48cd817f0a Mon Sep 17 00:00:00 2001 From: XinlaiWan Date: Tue, 19 Sep 2023 18:32:34 +0800 Subject: [PATCH] Add mstatus.VS setting code for vector extension --- c_emulator/riscv_platform.c | 4 +- c_emulator/riscv_platform.h | 2 +- c_emulator/riscv_platform_impl.c | 2 +- c_emulator/riscv_platform_impl.h | 2 +- c_emulator/riscv_sim.c | 2 +- model/riscv_insts_vext_arith.sail | 136 +++++++++++++++--------------- model/riscv_insts_vext_fp.sail | 72 ++++++++-------- model/riscv_insts_vext_mask.sail | 32 +++---- model/riscv_insts_vext_mem.sail | 48 +++++------ model/riscv_insts_vext_red.sail | 12 +-- model/riscv_insts_vext_vm.sail | 56 ++++++------ model/riscv_insts_vext_vset.sail | 8 +- model/riscv_sys_control.sail | 14 +-- model/riscv_sys_regs.sail | 18 ++-- model/riscv_vext_regs.sail | 13 +++ ocaml_emulator/platform.ml | 4 +- ocaml_emulator/riscv_ocaml_sim.ml | 4 +- 17 files changed, 225 insertions(+), 204 deletions(-) diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c index 676d8d965..35d5e4f46 100644 --- a/c_emulator/riscv_platform.c +++ b/c_emulator/riscv_platform.c @@ -37,9 +37,9 @@ bool sys_enable_zfinx(unit u) return rv_enable_zfinx; } -bool sys_enable_rvv(unit u) +bool sys_enable_vext(unit u) { - return rv_enable_rvv; + return rv_enable_vext; } bool sys_enable_writable_misa(unit u) diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h index a9b2d363c..2a4e8ba9d 100644 --- a/c_emulator/riscv_platform.h +++ b/c_emulator/riscv_platform.h @@ -6,7 +6,7 @@ bool sys_enable_next(unit); bool sys_enable_fdext(unit); bool sys_enable_zfinx(unit); bool sys_enable_writable_misa(unit); -bool sys_enable_rvv(unit); +bool sys_enable_vext(unit); bool plat_enable_dirty_update(unit); bool plat_enable_misaligned_access(unit); diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c index 2cc5cb3ac..e49b5caae 100644 --- a/c_emulator/riscv_platform_impl.c +++ b/c_emulator/riscv_platform_impl.c @@ -9,7 +9,7 @@ bool rv_enable_rvc = true; bool rv_enable_next = false; bool rv_enable_writable_misa = true; bool rv_enable_fdext = true; -bool rv_enable_rvv = true; +bool rv_enable_vext = true; bool rv_enable_dirty_update = false; bool rv_enable_misaligned = false; diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h index de9e0bfee..660bb015a 100644 --- a/c_emulator/riscv_platform_impl.h +++ b/c_emulator/riscv_platform_impl.h @@ -12,7 +12,7 @@ extern bool rv_enable_zfinx; extern bool rv_enable_rvc; extern bool rv_enable_next; extern bool rv_enable_fdext; -extern bool rv_enable_rvv; +extern bool rv_enable_vext; extern bool rv_enable_writable_misa; extern bool rv_enable_dirty_update; extern bool rv_enable_misaligned; diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index b08553dde..b806402e9 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -288,7 +288,7 @@ char *process_args(int argc, char **argv) break; case 'W': fprintf(stderr, "disabling RVV vector instructions.\n"); - rv_enable_rvv = false; + rv_enable_vext = false; break; case 'i': fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n"); diff --git a/model/riscv_insts_vext_arith.sail b/model/riscv_insts_vext_arith.sail index f5e73b25a..3183bb0a4 100644 --- a/model/riscv_insts_vext_arith.sail +++ b/model/riscv_insts_vext_arith.sail @@ -70,8 +70,8 @@ mapping encdec_vvfunct6 : vvfunct6 <-> bits(6) = { VV_VSSRA <-> 0b101011 } -mapping clause encdec = VVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_vvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_vvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(VVTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW_pow = get_sew_pow(); @@ -204,8 +204,8 @@ mapping encdec_nvsfunct6 : nvsfunct6 <-> bits(6) = { NVS_VNSRA <-> 0b101101 } -mapping clause encdec = NVSTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_nvsfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = NVSTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_nvsfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(NVSTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -271,8 +271,8 @@ mapping encdec_nvfunct6 : nvfunct6 <-> bits(6) = { NV_VNCLIP <-> 0b101111 } -mapping clause encdec = NVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_nvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = NVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_nvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(NVTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -333,8 +333,8 @@ mapping clause assembly = NVTYPE(funct6, vm, vs2, vs1, vd) /* ********************** OPIVV (Integer Merge Instruction) ********************** */ union clause ast = MASKTYPEV : (regidx, regidx, regidx) -mapping clause encdec = MASKTYPEV (vs2, vs1, vd) if haveRVV() - <-> 0b010111 @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MASKTYPEV (vs2, vs1, vd) if haveVExt() + <-> 0b010111 @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(MASKTYPEV(vs2, vs1, vd)) = { let start_element = get_start_element(); @@ -381,8 +381,8 @@ mapping clause assembly = MASKTYPEV(vs2, vs1, vd) /* ********************** OPIVV (Integer Move Instruction) *********************** */ union clause ast = MOVETYPEV : (regidx, regidx) -mapping clause encdec = MOVETYPEV (vs1, vd) if haveRVV() - <-> 0b010111 @ 0b1 @ 0b00000 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MOVETYPEV (vs1, vd) if haveVExt() + <-> 0b010111 @ 0b1 @ 0b00000 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(MOVETYPEV(vs1, vd)) = { let SEW = get_sew(); @@ -440,8 +440,8 @@ mapping encdec_vxfunct6 : vxfunct6 <-> bits(6) = { VX_VSSRA <-> 0b101011 } -mapping clause encdec = VXTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_vxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_vxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(VXTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -556,8 +556,8 @@ mapping encdec_nxsfunct6 : nxsfunct6 <-> bits(6) = { NXS_VNSRA <-> 0b101101 } -mapping clause encdec = NXSTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_nxsfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = NXSTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_nxsfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(NXSTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -623,8 +623,8 @@ mapping encdec_nxfunct6 : nxfunct6 <-> bits(6) = { NX_VNCLIP <-> 0b101111 } -mapping clause encdec = NXTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_nxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = NXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_nxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(NXTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -692,8 +692,8 @@ mapping encdec_vxsgfunct6 : vxsgfunct6 <-> bits(6) = { VX_VRGATHER <-> 0b001100 } -mapping clause encdec = VXSG(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_vxsgfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VXSG(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_vxsgfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(VXSG(funct6, vm, vs2, rs1, vd)) = { let SEW_pow = get_sew_pow(); @@ -755,8 +755,8 @@ mapping clause assembly = VXSG(funct6, vm, vs2, rs1, vd) /* ********************** OPIVX (Integer Merge Instruction) ********************** */ union clause ast = MASKTYPEX : (regidx, regidx, regidx) -mapping clause encdec = MASKTYPEX(vs2, rs1, vd) if haveRVV() - <-> 0b010111 @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MASKTYPEX(vs2, rs1, vd) if haveVExt() + <-> 0b010111 @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(MASKTYPEX(vs2, rs1, vd)) = { let start_element = get_start_element(); @@ -803,8 +803,8 @@ mapping clause assembly = MASKTYPEX(vs2, rs1, vd) /* ********************** OPIVX (Integer Move Instruction) *********************** */ union clause ast = MOVETYPEX : (regidx, regidx) -mapping clause encdec = MOVETYPEX (rs1, vd) if haveRVV() - <-> 0b010111 @ 0b1 @ 0b00000 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MOVETYPEX (rs1, vd) if haveVExt() + <-> 0b010111 @ 0b1 @ 0b00000 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(MOVETYPEX(rs1, vd)) = { let SEW = get_sew(); @@ -854,8 +854,8 @@ mapping encdec_vifunct6 : vifunct6 <-> bits(6) = { VI_VSSRA <-> 0b101011 } -mapping clause encdec = VITYPE(funct6, vm, vs2, simm, vd) if haveRVV() - <-> encdec_vifunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VITYPE(funct6, vm, vs2, simm, vd) if haveVExt() + <-> encdec_vifunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(VITYPE(funct6, vm, vs2, simm, vd)) = { let SEW = get_sew(); @@ -946,8 +946,8 @@ mapping encdec_nisfunct6 : nisfunct6 <-> bits(6) = { NIS_VNSRA <-> 0b101101 } -mapping clause encdec = NISTYPE(funct6, vm, vs2, simm, vd) if haveRVV() - <-> encdec_nisfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = NISTYPE(funct6, vm, vs2, simm, vd) if haveVExt() + <-> encdec_nisfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(NISTYPE(funct6, vm, vs2, simm, vd)) = { let SEW = get_sew(); @@ -1013,8 +1013,8 @@ mapping encdec_nifunct6 : nifunct6 <-> bits(6) = { NI_VNCLIP <-> 0b101111 } -mapping clause encdec = NITYPE(funct6, vm, vs2, simm, vd) if haveRVV() - <-> encdec_nifunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = NITYPE(funct6, vm, vs2, simm, vd) if haveVExt() + <-> encdec_nifunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(NITYPE(funct6, vm, vs2, simm, vd)) = { let SEW = get_sew(); @@ -1082,8 +1082,8 @@ mapping encdec_visgfunct6 : visgfunct6 <-> bits(6) = { VI_VRGATHER <-> 0b001100 } -mapping clause encdec = VISG(funct6, vm, vs2, simm, vd) if haveRVV() - <-> encdec_visgfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VISG(funct6, vm, vs2, simm, vd) if haveVExt() + <-> encdec_visgfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(VISG(funct6, vm, vs2, simm, vd)) = { let SEW_pow = get_sew_pow(); @@ -1145,8 +1145,8 @@ mapping clause assembly = VISG(funct6, vm, vs2, simm, vd) /* ********************** OPIVI (Integer Merge Instruction) ********************** */ union clause ast = MASKTYPEI : (regidx, bits(5), regidx) -mapping clause encdec = MASKTYPEI(vs2, simm, vd) if haveRVV() - <-> 0b010111 @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MASKTYPEI(vs2, simm, vd) if haveVExt() + <-> 0b010111 @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(MASKTYPEI(vs2, simm, vd)) = { let start_element = get_start_element(); @@ -1193,8 +1193,8 @@ mapping clause assembly = MASKTYPEI(vs2, simm, vd) /* ********************** OPIVI (Integer Move Instruction) *********************** */ union clause ast = MOVETYPEI : (regidx, bits(5)) -mapping clause encdec = MOVETYPEI (vd, simm) if haveRVV() - <-> 0b010111 @ 0b1 @ 0b00000 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MOVETYPEI (vd, simm) if haveVExt() + <-> 0b010111 @ 0b1 @ 0b00000 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(MOVETYPEI(vd, simm)) = { let SEW = get_sew(); @@ -1229,8 +1229,8 @@ mapping clause assembly = MOVETYPEI(vd, simm) /* ********************* OPIVI (Whole Vector Register Move) ********************** */ union clause ast = VMVRTYPE : (regidx, bits(5), regidx) -mapping clause encdec = VMVRTYPE(vs2, simm, vd) if haveRVV() - <-> 0b100111 @ 0b1 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VMVRTYPE(vs2, simm, vd) if haveVExt() + <-> 0b100111 @ 0b1 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(VMVRTYPE(vs2, simm, vd)) = { let start_element = get_start_element(); @@ -1287,8 +1287,8 @@ mapping encdec_mvvfunct6 : mvvfunct6 <-> bits(6) = { MVV_VREM <-> 0b100011 } -mapping clause encdec = MVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_mvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_mvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(MVVTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -1396,8 +1396,8 @@ mapping encdec_mvvmafunct6 : mvvmafunct6 <-> bits(6) = { MVV_VNMSUB <-> 0b101011 } -mapping clause encdec = MVVMATYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_mvvmafunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MVVMATYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_mvvmafunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(MVVMATYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -1456,8 +1456,8 @@ mapping encdec_wvvfunct6 : wvvfunct6 <-> bits(6) = { WVV_VWMULSU <-> 0b111010 } -mapping clause encdec = WVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_wvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = WVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_wvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(WVVTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -1526,8 +1526,8 @@ mapping encdec_wvfunct6 : wvfunct6 <-> bits(6) = { WV_VSUBU <-> 0b110110 } -mapping clause encdec = WVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_wvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = WVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_wvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(WVTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -1589,8 +1589,8 @@ mapping encdec_wmvvfunct6 : wmvvfunct6 <-> bits(6) = { WMVV_VWMACCSU <-> 0b111111 } -mapping clause encdec = WMVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_wmvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = WMVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_wmvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(WMVVTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -1650,8 +1650,8 @@ mapping vext2_vs1 : vext2funct6 <-> bits(5) = { VEXT2_SVF2 <-> 0b00111 } -mapping clause encdec = VEXT2TYPE(funct6, vm, vs2, vd) if haveRVV() - <-> 0b010010 @ vm @ vs2 @ vext2_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VEXT2TYPE(funct6, vm, vs2, vd) if haveVExt() + <-> 0b010010 @ vm @ vs2 @ vext2_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(VEXT2TYPE(funct6, vm, vs2, vd)) = { let SEW = get_sew(); @@ -1708,8 +1708,8 @@ mapping vext4_vs1 : vext4funct6 <-> bits(5) = { VEXT4_SVF4 <-> 0b00101 } -mapping clause encdec = VEXT4TYPE(funct6, vm, vs2, vd) if haveRVV() - <-> 0b010010 @ vm @ vs2 @ vext4_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VEXT4TYPE(funct6, vm, vs2, vd) if haveVExt() + <-> 0b010010 @ vm @ vs2 @ vext4_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(VEXT4TYPE(funct6, vm, vs2, vd)) = { let SEW = get_sew(); @@ -1766,8 +1766,8 @@ mapping vext8_vs1 : vext8funct6 <-> bits(5) = { VEXT8_SVF8 <-> 0b00011 } -mapping clause encdec = VEXT8TYPE(funct6, vm, vs2, vd) if haveRVV() - <-> 0b010010 @ vm @ vs2 @ vext8_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VEXT8TYPE(funct6, vm, vs2, vd) if haveVExt() + <-> 0b010010 @ vm @ vs2 @ vext8_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(VEXT8TYPE(funct6, vm, vs2, vd)) = { let SEW = get_sew(); @@ -1818,8 +1818,8 @@ mapping clause assembly = VEXT8TYPE(funct6, vm, vs2, vd) /* ************************ OPMVV (vmv.x.s in VWXUNARY0) ************************* */ union clause ast = VMVXS : (regidx, regidx) -mapping clause encdec = VMVXS(vs2, rd) if haveRVV() - <-> 0b010000 @ 0b1 @ vs2 @ 0b00000 @ 0b010 @ rd @ 0b1010111 if haveRVV() +mapping clause encdec = VMVXS(vs2, rd) if haveVExt() + <-> 0b010000 @ 0b1 @ vs2 @ 0b00000 @ 0b010 @ rd @ 0b1010111 if haveVExt() function clause execute(VMVXS(vs2, rd)) = { let SEW = get_sew(); @@ -1846,8 +1846,8 @@ mapping clause assembly = VMVXS(vs2, rd) /* ********************* OPMVV (Vector Compress Instruction) ********************* */ union clause ast = MVVCOMPRESS : (regidx, regidx, regidx) -mapping clause encdec = MVVCOMPRESS(vs2, vs1, vd) if haveRVV() - <-> 0b010111 @ 0b1 @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MVVCOMPRESS(vs2, vs1, vd) if haveVExt() + <-> 0b010111 @ 0b1 @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(MVVCOMPRESS(vs2, vs1, vd)) = { let start_element = get_start_element(); @@ -1920,8 +1920,8 @@ mapping encdec_mvxfunct6 : mvxfunct6 <-> bits(6) = { MVX_VREM <-> 0b100011 } -mapping clause encdec = MVXTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_mvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MVXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_mvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt() function clause execute(MVXTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -2040,8 +2040,8 @@ mapping encdec_mvxmafunct6 : mvxmafunct6 <-> bits(6) = { MVX_VNMSUB <-> 0b101011 } -mapping clause encdec = MVXMATYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_mvxmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MVXMATYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_mvxmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt() function clause execute(MVXMATYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -2101,8 +2101,8 @@ mapping encdec_wvxfunct6 : wvxfunct6 <-> bits(6) = { WVX_VWMULSU <-> 0b111010 } -mapping clause encdec = WVXTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_wvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = WVXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_wvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt() function clause execute(WVXTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -2170,8 +2170,8 @@ mapping encdec_wxfunct6 : wxfunct6 <-> bits(6) = { WX_VSUBU <-> 0b110110 } -mapping clause encdec = WXTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_wxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = WXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_wxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt() function clause execute(WXTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -2233,8 +2233,8 @@ mapping encdec_wmvxfunct6 : wmvxfunct6 <-> bits(6) = { WMVX_VWMACCSU <-> 0b111111 } -mapping clause encdec = WMVXTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_wmvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = WMVXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_wmvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt() function clause execute(WMVXTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -2289,8 +2289,8 @@ mapping clause assembly = WMVXTYPE(funct6, vm, vs2, rs1, vd) /* ****************************** OPMVX (VRXUNARY0) ****************************** */ union clause ast = VMVSX : (regidx, regidx) -mapping clause encdec = VMVSX(rs1, vd) if haveRVV() - <-> 0b010000 @ 0b1 @ 0b00000 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VMVSX(rs1, vd) if haveVExt() + <-> 0b010000 @ 0b1 @ 0b00000 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt() function clause execute(VMVSX(rs1, vd)) = { let SEW = get_sew(); diff --git a/model/riscv_insts_vext_fp.sail b/model/riscv_insts_vext_fp.sail index fbf85afd4..bba7e5448 100755 --- a/model/riscv_insts_vext_fp.sail +++ b/model/riscv_insts_vext_fp.sail @@ -57,8 +57,8 @@ mapping encdec_fvvfunct6 : fvvfunct6 <-> bits(6) = { FVV_VMUL <-> 0b100100 } -mapping clause encdec = FVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_fvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_fvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(FVVTYPE(funct6, vm, vs2, vs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -132,8 +132,8 @@ mapping encdec_fvvmafunct6 : fvvmafunct6 <-> bits(6) = { FVV_VNMSAC <-> 0b101111 } -mapping clause encdec = FVVMATYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_fvvmafunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FVVMATYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_fvvmafunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(FVVMATYPE(funct6, vm, vs2, vs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -199,8 +199,8 @@ mapping encdec_fwvvfunct6 : fwvvfunct6 <-> bits(6) = { FWVV_VMUL <-> 0b111000 } -mapping clause encdec = FWVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_fwvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FWVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_fwvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(FWVVTYPE(funct6, vm, vs2, vs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -264,8 +264,8 @@ mapping encdec_fwvvmafunct6 : fwvvmafunct6 <-> bits(6) = { FWVV_VNMSAC <-> 0b111111 } -mapping clause encdec = FWVVMATYPE(funct6, vm, vs1, vs2, vd) if haveRVV() - <-> encdec_fwvvmafunct6(funct6) @ vm @ vs1 @ vs2 @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FWVVMATYPE(funct6, vm, vs1, vs2, vd) if haveVExt() + <-> encdec_fwvvmafunct6(funct6) @ vm @ vs1 @ vs2 @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(FWVVMATYPE(funct6, vm, vs1, vs2, vd)) = { let rm_3b = fcsr.FRM(); @@ -328,8 +328,8 @@ mapping encdec_fwvfunct6 : fwvfunct6 <-> bits(6) = { FWV_VSUB <-> 0b110110 } -mapping clause encdec = FWVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_fwvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FWVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_fwvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(FWVTYPE(funct6, vm, vs2, vs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -391,8 +391,8 @@ mapping encdec_vfunary0_vs1 : vfunary0 <-> bits(5) = { FV_CVT_RTZ_X_F <-> 0b00111 } -mapping clause encdec = VFUNARY0(vm, vs2, vfunary0, vd) if haveRVV() - <-> 0b010010 @ vm @ vs2 @ encdec_vfunary0_vs1(vfunary0) @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VFUNARY0(vm, vs2, vfunary0, vd) if haveVExt() + <-> 0b010010 @ vm @ vs2 @ encdec_vfunary0_vs1(vfunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = { let rm_3b = fcsr.FRM(); @@ -504,8 +504,8 @@ mapping encdec_vfwunary0_vs1 : vfwunary0 <-> bits(5) = { FWV_CVT_RTZ_X_F <-> 0b01111 } -mapping clause encdec = VFWUNARY0(vm, vs2, vfwunary0, vd) if haveRVV() - <-> 0b010010 @ vm @ vs2 @ encdec_vfwunary0_vs1(vfwunary0) @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VFWUNARY0(vm, vs2, vfwunary0, vd) if haveVExt() + <-> 0b010010 @ vm @ vs2 @ encdec_vfwunary0_vs1(vfwunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(VFWUNARY0(vm, vs2, vfwunary0, vd)) = { let rm_3b = fcsr.FRM(); @@ -634,8 +634,8 @@ mapping encdec_vfnunary0_vs1 : vfnunary0 <-> bits(5) = { FNV_CVT_RTZ_X_F <-> 0b10111 } -mapping clause encdec = VFNUNARY0(vm, vs2, vfnunary0, vd) if haveRVV() - <-> 0b010010 @ vm @ vs2 @ encdec_vfnunary0_vs1(vfnunary0) @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VFNUNARY0(vm, vs2, vfnunary0, vd) if haveVExt() + <-> 0b010010 @ vm @ vs2 @ encdec_vfnunary0_vs1(vfnunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(VFNUNARY0(vm, vs2, vfnunary0, vd)) = { let rm_3b = fcsr.FRM(); @@ -769,8 +769,8 @@ mapping encdec_vfunary1_vs1 : vfunary1 <-> bits(5) = { FVV_VCLASS <-> 0b10000 } -mapping clause encdec = VFUNARY1(vm, vs2, vfunary1, vd) if haveRVV() - <-> 0b010011 @ vm @ vs2 @ encdec_vfunary1_vs1(vfunary1) @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VFUNARY1(vm, vs2, vfunary1, vd) if haveVExt() + <-> 0b010011 @ vm @ vs2 @ encdec_vfunary1_vs1(vfunary1) @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(VFUNARY1(vm, vs2, vfunary1, vd)) = { let rm_3b = fcsr.FRM(); @@ -845,8 +845,8 @@ mapping clause assembly = VFUNARY1(vm, vs2, vfunary1, vd) /* ****************************** OPFVV (VWFUNARY0) ****************************** */ union clause ast = VFMVFS : (regidx, regidx) -mapping clause encdec = VFMVFS(vs2, rd) if haveRVV() - <-> 0b010000 @ 0b1 @ vs2 @ 0b00000 @ 0b001 @ rd @ 0b1010111 if haveRVV() +mapping clause encdec = VFMVFS(vs2, rd) if haveVExt() + <-> 0b010000 @ 0b1 @ vs2 @ 0b00000 @ 0b001 @ rd @ 0b1010111 if haveVExt() function clause execute(VFMVFS(vs2, rd)) = { let rm_3b = fcsr.FRM(); @@ -893,8 +893,8 @@ mapping encdec_fvffunct6 : fvffunct6 <-> bits(6) = { VF_VRSUB <-> 0b100111 } -mapping clause encdec = FVFTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_fvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FVFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_fvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(FVFTYPE(funct6, vm, vs2, rs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -983,8 +983,8 @@ mapping encdec_fvfmafunct6 : fvfmafunct6 <-> bits(6) = { VF_VNMSAC <-> 0b101111 } -mapping clause encdec = FVFMATYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_fvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FVFMATYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_fvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(FVFMATYPE(funct6, vm, vs2, rs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -1050,8 +1050,8 @@ mapping encdec_fwvffunct6 : fwvffunct6 <-> bits(6) = { FWVF_VMUL <-> 0b111000 } -mapping clause encdec = FWVFTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_fwvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FWVFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_fwvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(FWVFTYPE(funct6, vm, vs2, rs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -1114,8 +1114,8 @@ mapping encdec_fwvfmafunct6 : fwvfmafunct6 <-> bits(6) = { FWVF_VNMSAC <-> 0b111111 } -mapping clause encdec = FWVFMATYPE(funct6, vm, rs1, vs2, vd) if haveRVV() - <-> encdec_fwvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FWVFMATYPE(funct6, vm, rs1, vs2, vd) if haveVExt() + <-> encdec_fwvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(FWVFMATYPE(funct6, vm, rs1, vs2, vd)) = { let rm_3b = fcsr.FRM(); @@ -1177,8 +1177,8 @@ mapping encdec_fwffunct6 : fwffunct6 <-> bits(6) = { FWF_VSUB <-> 0b110110 } -mapping clause encdec = FWFTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_fwffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FWFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_fwffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(FWFTYPE(funct6, vm, vs2, rs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -1231,8 +1231,8 @@ mapping clause assembly = FWFTYPE(funct6, vm, vs2, rs1, vd) /* This instruction operates on all body elements regardless of mask value */ union clause ast = VFMERGE : (regidx, regidx, regidx) -mapping clause encdec = VFMERGE(vs2, rs1, vd) if haveRVV() - <-> 0b010111 @ 0b0 @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VFMERGE(vs2, rs1, vd) if haveVExt() + <-> 0b010111 @ 0b0 @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(VFMERGE(vs2, rs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -1282,8 +1282,8 @@ mapping clause assembly = VFMERGE(vs2, rs1, vd) /* This instruction shares the encoding with vfmerge.vfm, but with vm=1 and vs2=v0 */ union clause ast = VFMV : (regidx, regidx) -mapping clause encdec = VFMV(rs1, vd) if haveRVV() - <-> 0b010111 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VFMV(rs1, vd) if haveVExt() + <-> 0b010111 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(VFMV(rs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -1320,8 +1320,8 @@ mapping clause assembly = VFMV(rs1, vd) /* ****************************** OPFVF (VRFUNARY0) ****************************** */ union clause ast = VFMVSF : (regidx, regidx) -mapping clause encdec = VFMVSF(rs1, vd) if haveRVV() - <-> 0b010000 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VFMVSF(rs1, vd) if haveVExt() + <-> 0b010000 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(VFMVSF(rs1, vd)) = { let rm_3b = fcsr.FRM(); diff --git a/model/riscv_insts_vext_mask.sail b/model/riscv_insts_vext_mask.sail index 83e2c6dab..bb4594f7e 100755 --- a/model/riscv_insts_vext_mask.sail +++ b/model/riscv_insts_vext_mask.sail @@ -55,8 +55,8 @@ mapping encdec_mmfunct6 : mmfunct6 <-> bits(6) = { MM_VMXNOR <-> 0b011111 } -mapping clause encdec = MMTYPE(funct6, vs2, vs1, vd) if haveRVV() - <-> encdec_mmfunct6(funct6) @ 0b1 @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = MMTYPE(funct6, vs2, vs1, vd) if haveVExt() + <-> encdec_mmfunct6(funct6) @ 0b1 @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(MMTYPE(funct6, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -113,8 +113,8 @@ mapping clause assembly = MMTYPE(funct6, vs2, vs1, vd) /* ************************* OPMVV (vpopc in VWXUNARY0) ************************** */ union clause ast = VCPOP_M : (bits(1), regidx, regidx) -mapping clause encdec = VCPOP_M(vm, vs2, rd) if haveRVV() - <-> 0b010000 @ vm @ vs2 @ 0b10000 @ 0b010 @ rd @ 0b1010111 if haveRVV() +mapping clause encdec = VCPOP_M(vm, vs2, rd) if haveVExt() + <-> 0b010000 @ vm @ vs2 @ 0b10000 @ 0b010 @ rd @ 0b1010111 if haveVExt() function clause execute(VCPOP_M(vm, vs2, rd)) = { let SEW = get_sew(); @@ -149,8 +149,8 @@ mapping clause assembly = VCPOP_M(vm, vs2, rd) /* ************************* OPMVV (vfirst in VWXUNARY0) ************************* */ union clause ast = VFIRST_M : (bits(1), regidx, regidx) -mapping clause encdec = VFIRST_M(vm, vs2, rd) if haveRVV() - <-> 0b010000 @ vm @ vs2 @ 0b10001 @ 0b010 @ rd @ 0b1010111 if haveRVV() +mapping clause encdec = VFIRST_M(vm, vs2, rd) if haveVExt() + <-> 0b010000 @ vm @ vs2 @ 0b10001 @ 0b010 @ rd @ 0b1010111 if haveVExt() function clause execute(VFIRST_M(vm, vs2, rd)) = { let SEW = get_sew(); @@ -187,8 +187,8 @@ mapping clause assembly = VFIRST_M(vm, vs2, rd) /* ************************** OPMVV (vmsbf in VMUNARY0) ************************** */ union clause ast = VMSBF_M : (bits(1), regidx, regidx) -mapping clause encdec = VMSBF_M(vm, vs2, vd) if haveRVV() - <-> 0b010100 @ vm @ vs2 @ 0b00001 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VMSBF_M(vm, vs2, vd) if haveVExt() + <-> 0b010100 @ vm @ vs2 @ 0b00001 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(VMSBF_M(vm, vs2, vd)) = { let SEW = get_sew(); @@ -228,8 +228,8 @@ mapping clause assembly = VMSBF_M(vm, vs2, vd) /* ************************** OPMVV (vmsif in VMUNARY0) ************************** */ union clause ast = VMSIF_M : (bits(1), regidx, regidx) -mapping clause encdec = VMSIF_M(vm, vs2, vd) if haveRVV() - <-> 0b010100 @ vm @ vs2 @ 0b00011 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VMSIF_M(vm, vs2, vd) if haveVExt() + <-> 0b010100 @ vm @ vs2 @ 0b00011 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(VMSIF_M(vm, vs2, vd)) = { let SEW = get_sew(); @@ -269,8 +269,8 @@ mapping clause assembly = VMSIF_M(vm, vs2, vd) /* ************************** OPMVV (vmsof in VMUNARY0) ************************** */ union clause ast = VMSOF_M : (bits(1), regidx, regidx) -mapping clause encdec = VMSOF_M(vm, vs2, vd) if haveRVV() - <-> 0b010100 @ vm @ vs2 @ 0b00010 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VMSOF_M(vm, vs2, vd) if haveVExt() + <-> 0b010100 @ vm @ vs2 @ 0b00010 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(VMSOF_M(vm, vs2, vd)) = { let SEW = get_sew(); @@ -314,8 +314,8 @@ mapping clause assembly = VMSOF_M(vm, vs2, vd) /* ************************** OPMVV (viota in VMUNARY0) ************************** */ union clause ast = VIOTA_M : (bits(1), regidx, regidx) -mapping clause encdec = VIOTA_M(vm, vs2, vd) if haveRVV() - <-> 0b010100 @ vm @ vs2 @ 0b10000 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VIOTA_M(vm, vs2, vd) if haveVExt() + <-> 0b010100 @ vm @ vs2 @ 0b10000 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(VIOTA_M(vm, vs2, vd)) = { let SEW = get_sew(); @@ -355,8 +355,8 @@ mapping clause assembly = VIOTA_M(vm, vs2, vd) /* *************************** OPMVV (vid in VMUNARY0) *************************** */ union clause ast = VID_V : (bits(1), regidx) -mapping clause encdec = VID_V(vm, vd) if haveRVV() - <-> 0b010100 @ vm @ 0b00000 @ 0b10001 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VID_V(vm, vd) if haveVExt() + <-> 0b010100 @ vm @ 0b00000 @ 0b10001 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(VID_V(vm, vd)) = { let SEW = get_sew(); diff --git a/model/riscv_insts_vext_mem.sail b/model/riscv_insts_vext_mem.sail index 301ecad6d..292d98f02 100644 --- a/model/riscv_insts_vext_mem.sail +++ b/model/riscv_insts_vext_mem.sail @@ -101,8 +101,8 @@ mapping bytes_wordwidth : {|1, 2, 4, 8|} <-> word_width = { /* ******************** Vector Load Unit-Stride Normal & Segment (mop=0b00, lumop=0b00000) ********************* */ union clause ast = VLSEGTYPE : (bits(3), bits(1), regidx, vlewidth, regidx) -mapping clause encdec = VLSEGTYPE(nf, vm, rs1, width, vd) if haveRVV() - <-> nf @ 0b0 @ 0b00 @ vm @ 0b00000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() +mapping clause encdec = VLSEGTYPE(nf, vm, rs1, width, vd) if haveVExt() + <-> nf @ 0b0 @ 0b00 @ vm @ 0b00000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt() val process_vlseg : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired effect {escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vlseg (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = { @@ -167,8 +167,8 @@ mapping clause assembly = VLSEGTYPE(nf, vm, rs1, width, vd) /* ************ Vector Load Unit-Stride Normal & Segment Fault-Only-First (mop=0b00, lumop=0b10000) ************ */ union clause ast = VLSEGFFTYPE : (bits(3), bits(1), regidx, vlewidth, regidx) -mapping clause encdec = VLSEGFFTYPE(nf, vm, rs1, width, vd) if haveRVV() - <-> nf @ 0b0 @ 0b00 @ vm @ 0b10000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() +mapping clause encdec = VLSEGFFTYPE(nf, vm, rs1, width, vd) if haveVExt() + <-> nf @ 0b0 @ 0b00 @ vm @ 0b10000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt() val process_vlsegff : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired effect {escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = { @@ -272,8 +272,8 @@ mapping clause assembly = VLSEGFFTYPE(nf, vm, rs1, width, vd) /* ******************** Vector Store Unit-Stride Normal & Segment (mop=0b00, sumop=0b00000) ******************** */ union clause ast = VSSEGTYPE : (bits(3), bits(1), regidx, vlewidth, regidx) -mapping clause encdec = VSSEGTYPE(nf, vm, rs1, width, vs3) if haveRVV() - <-> nf @ 0b0 @ 0b00 @ vm @ 0b00000 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveRVV() +mapping clause encdec = VSSEGTYPE(nf, vm, rs1, width, vs3) if haveVExt() + <-> nf @ 0b0 @ 0b00 @ vm @ 0b00000 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveVExt() val process_vsseg : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vsseg (nf, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) = { @@ -341,8 +341,8 @@ mapping clause assembly = VSSEGTYPE(nf, vm, rs1, width, vs3) /* ****************************** Vector Load Strided Normal & Segment (mop=0b10) ****************************** */ union clause ast = VLSSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) -mapping clause encdec = VLSSEGTYPE(nf, vm, rs2, rs1, width, vd) if haveRVV() - <-> nf @ 0b0 @ 0b10 @ vm @ rs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() +mapping clause encdec = VLSSEGTYPE(nf, vm, rs2, rs1, width, vd) if haveVExt() + <-> nf @ 0b0 @ 0b10 @ vm @ rs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt() val process_vlsseg : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, regidx, int('p), int('n)) -> Retired effect {escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vlsseg (nf, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) = { @@ -408,8 +408,8 @@ mapping clause assembly = VLSSEGTYPE(nf, vm, rs2, rs1, width, vd) /* ***************************** Vector Store Strided Normal & Segment (mop=0b10) ****************************** */ union clause ast = VSSSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) -mapping clause encdec = VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3) if haveRVV() - <-> nf @ 0b0 @ 0b10 @ vm @ rs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveRVV() +mapping clause encdec = VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3) if haveVExt() + <-> nf @ 0b0 @ 0b10 @ vm @ rs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveVExt() val process_vssseg : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, regidx, int('p), int('n)) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vssseg (nf, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) = { @@ -478,8 +478,8 @@ mapping clause assembly = VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3) /* ************************* Vector Load Indexed Unordered Normal & Segment (mop=0b01) ************************* */ union clause ast = VLUXSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) -mapping clause encdec = VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd) if haveRVV() - <-> nf @ 0b0 @ 0b01 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() +mapping clause encdec = VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd) if haveVExt() + <-> nf @ 0b0 @ 0b01 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt() val process_vlxseg : forall 'f 'ib 'db 'ip 'dp 'n, (0 < 'f & 'f <= 8) & ('ib in {1, 2, 4, 8}) & ('db in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('ib), int('db), int('ip), int('dp), regidx, regidx, int('n), int) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vlxseg (nf, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, mop) = { @@ -546,8 +546,8 @@ mapping clause assembly = VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd) /* ************************** Vector Load Indexed Ordered Normal & Segment (mop=0b11) ************************** */ union clause ast = VLOXSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) -mapping clause encdec = VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd) if haveRVV() - <-> nf @ 0b0 @ 0b11 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() +mapping clause encdec = VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd) if haveVExt() + <-> nf @ 0b0 @ 0b11 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt() function clause execute(VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd)) = { let EEW_index_pow = vlewidth_pow(width); @@ -570,8 +570,8 @@ mapping clause assembly = VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd) /* ************************ Vector Store Indexed Unordered Normal & Segment (mop=0b01) ************************* */ union clause ast = VSUXSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) -mapping clause encdec = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) if haveRVV() - <-> nf @ 0b0 @ 0b01 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveRVV() +mapping clause encdec = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) if haveVExt() + <-> nf @ 0b0 @ 0b01 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveVExt() val process_vsxseg : forall 'f 'ib 'db 'ip 'dp 'n, (0 < 'f & 'f <= 8) & ('ib in {1, 2, 4, 8}) & ('db in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('ib), int('db), int('ip), int('dp), regidx, regidx, int('n), int) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vsxseg (nf, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, mop) = { @@ -641,8 +641,8 @@ mapping clause assembly = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) /* ************************* Vector Store Indexed Ordered Normal & Segment (mop=0b11) ************************** */ union clause ast = VSOXSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) -mapping clause encdec = VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3) if haveRVV() - <-> nf @ 0b0 @ 0b11 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveRVV() +mapping clause encdec = VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3) if haveVExt() + <-> nf @ 0b0 @ 0b11 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveVExt() function clause execute(VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3)) = { let EEW_index_pow = vlewidth_pow(width); @@ -665,8 +665,8 @@ mapping clause assembly = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) /* ***************** Vector Load Unit-Stride Whole Register (vm=0b1, mop=0b00, lumop=0b01000) ****************** */ union clause ast = VLRETYPE : (bits(3), regidx, vlewidth, regidx) -mapping clause encdec = VLRETYPE(nf, rs1, width, vd) if haveRVV() - <-> nf @ 0b0 @ 0b00 @ 0b1 @ 0b01000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() +mapping clause encdec = VLRETYPE(nf, rs1, width, vd) if haveVExt() + <-> nf @ 0b0 @ 0b00 @ 0b1 @ 0b01000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt() val process_vlre : forall 'f 'b 'n, ('f in {1, 2, 4, 8}) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), regidx, int('b), regidx, int('n)) -> Retired effect {escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = { @@ -747,8 +747,8 @@ mapping clause assembly = VLRETYPE(nf, rs1, width, vd) /* ***************** Vector Store Unit-Stride Whole Register (vm=0b1, mop=0b00, lumop=0b01000) ***************** */ union clause ast = VSRETYPE : (bits(3), regidx, regidx) -mapping clause encdec = VSRETYPE(nf, rs1, vs3) if haveRVV() - <-> nf @ 0b0 @ 0b00 @ 0b1 @ 0b01000 @ rs1 @ 0b000 @ vs3 @ 0b0100111 if haveRVV() +mapping clause encdec = VSRETYPE(nf, rs1, vs3) if haveVExt() + <-> nf @ 0b0 @ 0b00 @ 0b1 @ 0b01000 @ rs1 @ 0b000 @ vs3 @ 0b0100111 if haveVExt() val process_vsre : forall 'f 'b 'n, ('f in {1, 2, 4, 8}) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), int('b), regidx, regidx, int('n)) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vsre (nf, load_width_bytes, rs1, vs3, elem_per_reg) = { @@ -852,8 +852,8 @@ mapping encdec_lsop : vmlsop <-> bits(7) = { VSM <-> 0b0100111 } -mapping clause encdec = VMTYPE(rs1, vd_or_vs3, op) if haveRVV() - <-> 0b000 @ 0b0 @ 0b00 @ 0b1 @ 0b01011 @ rs1 @ 0b000 @ vd_or_vs3 @ encdec_lsop(op) if haveRVV() +mapping clause encdec = VMTYPE(rs1, vd_or_vs3, op) if haveVExt() + <-> 0b000 @ 0b0 @ 0b00 @ 0b1 @ 0b01011 @ rs1 @ 0b000 @ vd_or_vs3 @ encdec_lsop(op) if haveVExt() val process_vm : forall 'n 'l, ('n >= 0 & 'l >= 0). (regidx, regidx, int('n), int('l), vmlsop) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = { diff --git a/model/riscv_insts_vext_red.sail b/model/riscv_insts_vext_red.sail index 581953802..6b756f13a 100755 --- a/model/riscv_insts_vext_red.sail +++ b/model/riscv_insts_vext_red.sail @@ -49,8 +49,8 @@ mapping encdec_rivvfunct6 : rivvfunct6 <-> bits(6) = { IVV_VWREDSUM <-> 0b110001 } -mapping clause encdec = RIVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_rivvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = RIVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_rivvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(RIVVTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -114,8 +114,8 @@ mapping encdec_rmvvfunct6 : rmvvfunct6 <-> bits(6) = { MVV_VREDMAX <-> 0b000111 } -mapping clause encdec = RMVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_rmvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = RMVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_rmvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt() function clause execute(RMVVTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -185,8 +185,8 @@ mapping encdec_rfvvfunct6 : rfvvfunct6 <-> bits(6) = { FVV_VFWREDUSUM <-> 0b110001 } -mapping clause encdec = RFVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_rfvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = RFVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_rfvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt() val process_rfvv_single: forall 'n 'm 'p, 'n >= 0 & 'm in {8, 16, 32, 64}. (rfvvfunct6, bits(1), regidx, regidx, regidx, int('n), int('m), int('p)) -> Retired effect {escape, rreg, undef, wreg} function process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) = { diff --git a/model/riscv_insts_vext_vm.sail b/model/riscv_insts_vext_vm.sail index ff1eff994..b75b0799c 100755 --- a/model/riscv_insts_vext_vm.sail +++ b/model/riscv_insts_vext_vm.sail @@ -52,8 +52,8 @@ mapping encdec_vvmfunct6 : vvmfunct6 <-> bits(6) = { VVM_VMSBC <-> 0b010011 } -mapping clause encdec = VVMTYPE(funct6, vs2, vs1, vd) if haveRVV() - <-> encdec_vvmfunct6(funct6) @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VVMTYPE(funct6, vs2, vs1, vd) if haveVExt() + <-> encdec_vvmfunct6(funct6) @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(VVMTYPE(funct6, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -108,8 +108,8 @@ mapping encdec_vvmcfunct6 : vvmcfunct6 <-> bits(6) = { VVMC_VMSBC <-> 0b010011 } -mapping clause encdec = VVMCTYPE(funct6, vs2, vs1, vd) if haveRVV() - <-> encdec_vvmcfunct6(funct6) @ 0b1 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VVMCTYPE(funct6, vs2, vs1, vd) if haveVExt() + <-> encdec_vvmcfunct6(funct6) @ 0b1 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(VVMCTYPE(funct6, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -163,8 +163,8 @@ mapping encdec_vvmsfunct6 : vvmsfunct6 <-> bits(6) = { VVMS_VSBC <-> 0b010010 } -mapping clause encdec = VVMSTYPE(funct6, vs2, vs1, vd) if haveRVV() - <-> encdec_vvmsfunct6(funct6) @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VVMSTYPE(funct6, vs2, vs1, vd) if haveVExt() + <-> encdec_vvmsfunct6(funct6) @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(VVMSTYPE(funct6, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -226,8 +226,8 @@ mapping encdec_vvcmpfunct6 : vvcmpfunct6 <-> bits(6) = { VVCMP_VMSLE <-> 0b011101 } -mapping clause encdec = VVCMPTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_vvcmpfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VVCMPTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_vvcmpfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt() function clause execute(VVCMPTYPE(funct6, vm, vs2, vs1, vd)) = { let SEW = get_sew(); @@ -290,8 +290,8 @@ mapping encdec_vxmfunct6 : vxmfunct6 <-> bits(6) = { VXM_VMSBC <-> 0b010011 } -mapping clause encdec = VXMTYPE(funct6, vs2, rs1, vd) if haveRVV() - <-> encdec_vxmfunct6(funct6) @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VXMTYPE(funct6, vs2, rs1, vd) if haveVExt() + <-> encdec_vxmfunct6(funct6) @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(VXMTYPE(funct6, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -346,8 +346,8 @@ mapping encdec_vxmcfunct6 : vxmcfunct6 <-> bits(6) = { VXMC_VMSBC <-> 0b010011 } -mapping clause encdec = VXMCTYPE(funct6, vs2, rs1, vd) if haveRVV() - <-> encdec_vxmcfunct6(funct6) @ 0b1 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VXMCTYPE(funct6, vs2, rs1, vd) if haveVExt() + <-> encdec_vxmcfunct6(funct6) @ 0b1 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(VXMCTYPE(funct6, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -401,8 +401,8 @@ mapping encdec_vxmsfunct6 : vxmsfunct6 <-> bits(6) = { VXMS_VSBC <-> 0b010010 } -mapping clause encdec = VXMSTYPE(funct6, vs2, rs1, vd) if haveRVV() - <-> encdec_vxmsfunct6(funct6) @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VXMSTYPE(funct6, vs2, rs1, vd) if haveVExt() + <-> encdec_vxmsfunct6(funct6) @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(VXMSTYPE(funct6, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -466,8 +466,8 @@ mapping encdec_vxcmpfunct6 : vxcmpfunct6 <-> bits(6) = { VXCMP_VMSGT <-> 0b011111 } -mapping clause encdec = VXCMPTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_vxcmpfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VXCMPTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_vxcmpfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt() function clause execute(VXCMPTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -533,8 +533,8 @@ mapping encdec_vimfunct6 : vimfunct6 <-> bits(6) = { VIM_VMADC <-> 0b010001 /* carry in, carry out */ } -mapping clause encdec = VIMTYPE(funct6, vs2, simm, vd) if haveRVV() - <-> encdec_vimfunct6(funct6) @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VIMTYPE(funct6, vs2, simm, vd) if haveVExt() + <-> encdec_vimfunct6(funct6) @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(VIMTYPE(funct6, vs2, simm, vd)) = { let SEW = get_sew(); @@ -586,8 +586,8 @@ mapping encdec_vimcfunct6 : vimcfunct6 <-> bits(6) = { VIMC_VMADC <-> 0b010001 /* carry in, carry out */ } -mapping clause encdec = VIMCTYPE(funct6, vs2, simm, vd) if haveRVV() - <-> encdec_vimcfunct6(funct6) @ 0b1 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VIMCTYPE(funct6, vs2, simm, vd) if haveVExt() + <-> encdec_vimcfunct6(funct6) @ 0b1 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(VIMCTYPE(funct6, vs2, simm, vd)) = { let SEW = get_sew(); @@ -638,8 +638,8 @@ mapping encdec_vimsfunct6 : vimsfunct6 <-> bits(6) = { VIMS_VADC <-> 0b010000 /* Carry in, no carry out */ } -mapping clause encdec = VIMSTYPE(funct6, vs2, simm, vd) if haveRVV() - <-> encdec_vimsfunct6(funct6) @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VIMSTYPE(funct6, vs2, simm, vd) if haveVExt() + <-> encdec_vimsfunct6(funct6) @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(VIMSTYPE(funct6, vs2, simm, vd)) = { let SEW = get_sew(); @@ -699,8 +699,8 @@ mapping encdec_vicmpfunct6 : vicmpfunct6 <-> bits(6) = { VICMP_VMSGT <-> 0b011111 } -mapping clause encdec = VICMPTYPE(funct6, vm, vs2, simm, vd) if haveRVV() - <-> encdec_vicmpfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = VICMPTYPE(funct6, vm, vs2, simm, vd) if haveVExt() + <-> encdec_vicmpfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt() function clause execute(VICMPTYPE(funct6, vm, vs2, simm, vd)) = { let SEW = get_sew(); @@ -763,8 +763,8 @@ mapping encdec_fvvmfunct6 : fvvmfunct6 <-> bits(6) = { FVVM_VMFNE <-> 0b011100 } -mapping clause encdec = FVVMTYPE(funct6, vm, vs2, vs1, vd) if haveRVV() - <-> encdec_fvvmfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FVVMTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() + <-> encdec_fvvmfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt() function clause execute(FVVMTYPE(funct6, vm, vs2, vs1, vd)) = { let rm_3b = fcsr.FRM(); @@ -827,8 +827,8 @@ mapping encdec_fvfmfunct6 : fvfmfunct6 <-> bits(6) = { VFM_VMFGE <-> 0b011111 } -mapping clause encdec = FVFMTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_fvfmfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV() +mapping clause encdec = FVFMTYPE(funct6, vm, vs2, rs1, vd) if haveVExt() + <-> encdec_fvfmfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt() function clause execute(FVFMTYPE(funct6, vm, vs2, rs1, vd)) = { let rm_3b = fcsr.FRM(); diff --git a/model/riscv_insts_vext_vset.sail b/model/riscv_insts_vext_vset.sail index e869c6e90..960036237 100644 --- a/model/riscv_insts_vext_vset.sail +++ b/model/riscv_insts_vext_vset.sail @@ -79,8 +79,8 @@ mapping encdec_vsetop : vsetop <-> bits(4) ={ VSETVL <-> 0b1000 } -mapping clause encdec = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) if haveRVV() - <-> encdec_vsetop(op) @ ma @ ta @ sew @ lmul @ rs1 @ 0b111 @ rd @ 0b1010111 if haveRVV() +mapping clause encdec = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) if haveVExt() + <-> encdec_vsetop(op) @ ma @ ta @ sew @ lmul @ rs1 @ 0b111 @ rd @ 0b1010111 if haveVExt() function clause execute VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) = { let VLEN_pow = get_vlen_pow(); @@ -162,8 +162,8 @@ mapping clause assembly = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) /* ********************************* vsetivli ************************************ */ union clause ast = VSETI_TYPE : ( bits(1), bits(1), bits(3), bits(3), regidx, regidx) -mapping clause encdec = VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) if haveRVV() - <-> 0b1100 @ ma @ ta @ sew @ lmul @ uimm @ 0b111 @ rd @ 0b1010111 if haveRVV() +mapping clause encdec = VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) if haveVExt() + <-> 0b1100 @ ma @ ta @ sew @ lmul @ uimm @ 0b111 @ rd @ 0b1010111 if haveVExt() function clause execute VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) = { let VLEN_pow = get_vlen_pow(); diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index d8f378953..2f9d4ce21 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -554,13 +554,13 @@ function init_sys() -> unit = { mhartid = zero_extend(0b0); misa->MXL() = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64); - misa->A() = 0b1; /* atomics */ - misa->C() = bool_to_bits(sys_enable_rvc()); /* RVC */ - misa->I() = 0b1; /* base integer ISA */ - misa->M() = 0b1; /* integer multiply/divide */ - misa->U() = 0b1; /* user-mode */ - misa->S() = 0b1; /* supervisor-mode */ - misa->V() = bool_to_bits(sys_enable_rvv()); /* RVV */ + misa->A() = 0b1; /* atomics */ + misa->C() = bool_to_bits(sys_enable_rvc()); /* RVC */ + misa->I() = 0b1; /* base integer ISA */ + misa->M() = 0b1; /* integer multiply/divide */ + misa->U() = 0b1; /* user-mode */ + misa->S() = 0b1; /* supervisor-mode */ + misa->V() = bool_to_bits(sys_enable_vext()); /* vector extension */ if sys_enable_fdext() & sys_enable_zfinx() then internal_error(__FILE__, __LINE__, "F and Zfinx cannot both be enabled!"); diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 6307e727c..32a8efe7f 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -150,7 +150,8 @@ val sys_enable_fdext = {c: "sys_enable_fdext", ocaml: "Platform.enable_fdext", _ val sys_enable_zfinx = {c: "sys_enable_zfinx", ocaml: "Platform.enable_zfinx", _: "sys_enable_zfinx"} : unit -> bool /* whether the N extension was enabled at boot */ val sys_enable_next = {c: "sys_enable_next", ocaml: "Platform.enable_next", _: "sys_enable_next"} : unit -> bool -val sys_enable_rvv = {c: "sys_enable_rvv", ocaml: "Platform.enable_rvv", _: "sys_enable_rvv"} : unit -> bool +/* whether misa.v was enabled at boot */ +val sys_enable_vext = {c: "sys_enable_vext", ocaml: "Platform.enable_vext", _: "sys_enable_vext"} : unit -> bool /* This function allows an extension to veto a write to Misa if it would violate an alignment restriction on @@ -210,7 +211,6 @@ function haveZkne() -> bool = true function haveZknd() -> bool = true function haveZmmul() -> bool = true -function haveRVV() -> bool = misa.V() == 0b1 /* Zicond extension support */ function haveZicond() -> bool = true @@ -246,6 +246,7 @@ bitfield Mstatus : xlenbits = { FS : 14 .. 13, MPP : 12 .. 11, + VS : 10 .. 9, SPP : 8, MPIE : 7, @@ -299,7 +300,7 @@ function legalize_mstatus(o : Mstatus, v : xlenbits) -> Mstatus = { * that does not have a matching bitfield entry. All bits above 32 are handled * explicitly later. */ - let m : Mstatus = Mk_Mstatus(zero_extend(v[22 .. 11] @ 0b00 @ v[8 .. 7] @ 0b0 @ v[5 .. 3] @ 0b0 @ v[1 .. 0])); + let m : Mstatus = Mk_Mstatus(zero_extend(v[22 .. 7] @ 0b0 @ v[5 .. 3] @ 0b0 @ v[1 .. 0])); /* We don't have any extension context yet. */ let m = update_XS(m, extStatus_to_bits(Off)); @@ -310,7 +311,8 @@ function legalize_mstatus(o : Mstatus, v : xlenbits) -> Mstatus = { * FIXME: This should be made a platform parameter. */ let m = if sys_enable_zfinx() then update_FS(m, extStatus_to_bits(Off)) else m; - let dirty = extStatus_of_bits(m.FS()) == Dirty | extStatus_of_bits(m.XS()) == Dirty; + let dirty = extStatus_of_bits(m.FS()) == Dirty | extStatus_of_bits(m.XS()) == Dirty | + extStatus_of_bits(m.VS()) == Dirty; let m = update_SD(m, bool_to_bits(dirty)); /* We don't support dynamic changes to SXL and UXL. */ @@ -359,6 +361,8 @@ function haveFExt() -> bool = (misa.F() == 0b1) & (mstatus.FS() != 0b00) function haveDExt() -> bool = (misa.D() == 0b1) & (mstatus.FS() != 0b00) /* Zfh (half-precision) extension depends on misa.F and mstatus.FS */ function haveZfh() -> bool = (misa.F() == 0b1) & (mstatus.FS() != 0b00) +/* V extension has to enable both via misa.V as well as mstatus.VS */ +function haveVExt() -> bool = (misa.V() == 0b1) & (mstatus.VS() != 0b00) /* Zhinx, Zfinx and Zdinx extensions (TODO: gate FCSR access on [mhs]stateen0 bit 1 when implemented) */ function haveZhinx() -> bool = sys_enable_zfinx() @@ -594,6 +598,7 @@ bitfield Sstatus : xlenbits = { SUM : 18, XS : 16 .. 15, FS : 14 .. 13, + VS : 10 .. 9, SPP : 8, SPIE : 5, UPIE : 4, @@ -621,6 +626,7 @@ function lower_mstatus(m : Mstatus) -> Sstatus = { let s = update_SUM(s, m.SUM()); let s = update_XS(s, m.XS()); let s = update_FS(s, m.FS()); + let s = update_VS(s, m.VS()); let s = update_SPP(s, m.SPP()); let s = update_SPIE(s, m.SPIE()); let s = update_UPIE(s, m.UPIE()); @@ -636,7 +642,9 @@ function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = { let m = update_XS(m, s.XS()); // See comment for mstatus.FS. let m = update_FS(m, s.FS()); - let dirty = extStatus_of_bits(m.FS()) == Dirty | extStatus_of_bits(m.XS()) == Dirty; + let m = update_VS(m, s.VS()); + let dirty = extStatus_of_bits(m.FS()) == Dirty | extStatus_of_bits(m.XS()) == Dirty | + extStatus_of_bits(m.VS()) == Dirty; let m = update_SD(m, bool_to_bits(dirty)); let m = update_SPP(m, s.SPP()); diff --git a/model/riscv_vext_regs.sail b/model/riscv_vext_regs.sail index 522e76f70..9b5d6e9bf 100644 --- a/model/riscv_vext_regs.sail +++ b/model/riscv_vext_regs.sail @@ -106,6 +106,16 @@ mapping vreg_name = { 0b11111 <-> "v31" } +function dirty_v_context() -> unit = { + assert(sys_enable_vext()); + mstatus->VS() = extStatus_to_bits(Dirty); + mstatus->SD() = 0b1 +} + +function dirty_v_context_if_present() -> unit = { + if sys_enable_vext() then dirty_v_context() +} + val rV : forall 'n, 0 <= 'n < 32. regno('n) -> vregtype effect {rreg, escape} function rV r = { let zero_vreg : vregtype = zeros(); @@ -187,6 +197,8 @@ function wV (r, in_v) = { _ => assert(false, "invalid vector register number") }; + dirty_v_context(); + let VLEN = unsigned(vlenb) * 8; assert(0 < VLEN & VLEN <= sizeof(vlenmax)); if get_config_print_reg() @@ -249,6 +261,7 @@ val ext_write_vcsr : (bits(2), bits(1)) -> unit effect {rreg, wreg} function ext_write_vcsr (vxrm_val, vxsat_val) = { vcsr->vxrm() = vxrm_val; /* Note: frm can be an illegal value, 101, 110, 111 */ vcsr->vxsat() = vxsat_val; + dirty_v_context_if_present() } /* num_elem means max(VLMAX,VLEN/SEW)) according to Section 5.4 of RVV spec */ diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml index 4a72bceea..bfd072ef5 100644 --- a/ocaml_emulator/platform.ml +++ b/ocaml_emulator/platform.ml @@ -11,7 +11,7 @@ let config_enable_dirty_update = ref false let config_enable_misaligned_access = ref false let config_mtval_has_illegal_inst_bits = ref false let config_enable_pmp = ref false -let config_enable_rvv = ref true +let config_enable_vext = ref true let platform_arch = ref P.RV64 @@ -79,7 +79,7 @@ let enable_writable_misa () = !config_enable_writable_misa let enable_rvc () = !config_enable_rvc let enable_next () = !config_enable_next let enable_fdext () = false -let enable_rvv () = !config_enable_rvv +let enable_vext () = !config_enable_vext let enable_dirty_update () = !config_enable_dirty_update let enable_misaligned_access () = !config_enable_misaligned_access let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits diff --git a/ocaml_emulator/riscv_ocaml_sim.ml b/ocaml_emulator/riscv_ocaml_sim.ml index 7ea5d4113..9740eb58b 100644 --- a/ocaml_emulator/riscv_ocaml_sim.ml +++ b/ocaml_emulator/riscv_ocaml_sim.ml @@ -53,8 +53,8 @@ let options = Arg.align ([("-dump-dts", ("-disable-rvc", Arg.Clear P.config_enable_rvc, " disable the RVC extension on boot"); - ("-disable-rvv", - Arg.Clear P.config_enable_rvv, + ("-disable-vext", + Arg.Clear P.config_enable_vext, " disable the RVV extension on boot"); ("-disable-writable-misa-c", Arg.Clear P.config_enable_writable_misa,