From 05311922c74f262c7b044ea6adf1f47f83adf0b2 Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <ved@rivosinc.com>
Date: Fri, 29 Dec 2023 11:33:37 -0600
Subject: [PATCH] add srmcfg CSR introduced by Ssqosid

---
 model/riscv_csr_map.sail     |  2 ++
 model/riscv_insts_zicsr.sail |  2 ++
 model/riscv_sys_control.sail |  5 +++++
 model/riscv_sys_regs.sail    | 18 ++++++++++++++++++
 4 files changed, 27 insertions(+)

diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail
index 5850ef48b..1d6f1042d 100644
--- a/model/riscv_csr_map.sail
+++ b/model/riscv_csr_map.sail
@@ -173,6 +173,8 @@ mapping clause csr_name_map = 0x00F  <-> "vcsr"
 mapping clause csr_name_map = 0xC20  <-> "vl"
 mapping clause csr_name_map = 0xC21  <-> "vtype"
 mapping clause csr_name_map = 0xC22  <-> "vlenb"
+/* Sqosid csrs */
+mapping clause csr_name_map = 0x181  <-> "srmcfg"
 /* Smstateen csrs */
 mapping clause csr_name_map = 0x30C  <-> "mstateen0"
 mapping clause csr_name_map = 0x31C  <-> "mstateen0h"
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index b3716a149..b25f54831 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -165,6 +165,7 @@ function readCSR csr : csreg -> xlenbits = {
     (0x143,  _) => stval,
     (0x144,  _) => lower_mip(mip, mideleg).bits(),
     (0x180,  _) => satp,
+    (0x181,  _) => srmcfg.bits(),
 
     /* user mode counters */
     (0xC00,  _) => mcycle[(sizeof(xlen) - 1) .. 0],
@@ -261,6 +262,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
     (0x143,  _) => { stval = value; Some(stval) },
     (0x144,  _) => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits()) },
     (0x180,  _) => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) },
+    (0x181,  _) => { srmcfg = legalize_srmcfg(srmcfg, value); Some(srmcfg.bits()) },
 
     /* user mode: seed (entropy source). writes are ignored */
     (0x015,  _) => write_seed_csr(),
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 6353d253d..2b4aa33b3 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -155,6 +155,9 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
     /* supervisor mode: address translation */
     0x180 => haveSupMode() & (p == Machine | p == Supervisor), // satp
 
+    /* supervisor mode: resource management configurations */
+    0x181 => haveSsqosid() & (p == Machine | ((p == Supervisor) & (mstateen0.PRIV114() == 0b1))), // srmcfg
+
     /* user mode: counters */
     0xC00 => haveUsrMode(),    // cycle
     0xC01 => haveUsrMode(),    // time
@@ -627,6 +630,8 @@ function init_sys() -> unit = {
 
   init_pmp();
 
+  srmcfg->RCID()     = 0b000000000000;
+
   // log compatibility with spike
   if   get_config_print_reg()
   then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(zero_extend(0b0) : xlenbits) ^ ")")
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index f838a874e..8236b02f9 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -215,6 +215,9 @@ function haveZmmul()  -> bool = true
 /* Zicond extension support */
 function haveZicond() -> bool = true
 
+/* Ssqosid extension support */
+function haveSsqosid() -> bool = true
+
 bitfield Mstatush : bits(32) = {
   MBE  : 5,
   SBE  : 4
@@ -885,6 +888,7 @@ function is_fiom_active() -> bool = {
 
 bitfield Mstateen0 : bits(64) = {
   // controls to new state introduced by the following small extensions of Priv-1.14-era:
+  // - CSR srmcfg introduced by Ssqosid extension
   PRIV114  : 55
 }
 register mstateen0 : Mstateen0
@@ -982,3 +986,17 @@ function get_vtype_vma() = decode_agtype(vtype.vma())
 
 val get_vtype_vta : unit -> agtype
 function get_vtype_vta() = decode_agtype(vtype.vta())
+
+/* srmcfg CSR introduced by Ssqosid */
+bitfield Srmcfg : xlenbits = {
+  MCID : 27 .. 16,
+  RCID : 11 .. 0
+}
+
+register srmcfg : Srmcfg
+
+function legalize_srmcfg(s : Srmcfg, v : xlenbits) -> Srmcfg = {
+  let s = update_MCID(s, v[27 .. 16]);
+  let s = update_RCID(s, v[11 .. 0]);
+  s
+}