From fa025b623b5a71d7090640c0a1e198e6f0d35050 Mon Sep 17 00:00:00 2001 From: jb-brelot-nxp Date: Thu, 12 Sep 2024 09:34:14 +0200 Subject: [PATCH] Update src/clic.adoc Co-authored-by: Christian Herber Signed-off-by: jb-brelot-nxp --- src/clic.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/clic.adoc b/src/clic.adoc index 97ddf92..bdc1175 100644 --- a/src/clic.adoc +++ b/src/clic.adoc @@ -659,7 +659,7 @@ interrupt trigger when using accesses of {nxti} that include writes. A trigger The `interrupt_trap_enable` control bit is read-write to enable/disable this interrupt trigger. A trigger is signaled to the debug module if an interrupt trap is taken and the interrupt code matches a `clicinttrig[__i__]`.interrupt_number and the associated `clicinttrig[__i__]`.interrupt_trap_enable is set. -=== M-mode CLIC Register Access via Indirect CSR Access +=== Indirect Access M-mode CSRs Access to CLIC registers clicintctl[i], clicintattr[i], clicintip[i], clicintie[i], and clicinttrig[i] utilizes the Indirect CSR Access extension (Smcsrind/Sscsrind). Implementations may support