diff --git a/doc/vector-extra/riscv-crypto-spec-vector-extra.adoc b/doc/vector-extra/riscv-crypto-spec-vector-extra.adoc index 3dfd4ce5..53da28cc 100644 --- a/doc/vector-extra/riscv-crypto-spec-vector-extra.adoc +++ b/doc/vector-extra/riscv-crypto-spec-vector-extra.adoc @@ -113,7 +113,7 @@ defined in the link:https://github.com/riscv/riscv-crypto/releases/tag/v1.0.1-scalar[RISC-V Scalar Cryptography Extensions specification]. If `Zvkt` is implemented, all the instructions from `Zvbc32e` (`vclmul[h].[vv,vx]`) -shall be executed with data-independent execution latency as +shall be executed with data-independent execution latency. Whether `Zvkt` is implemented or not, all instructions from `Zvkgs` (`vgmul.vs`, `vghsh.vs`) shall be executed with data-independent execution latency. diff --git a/doc/vector-extra/riscv-crypto-vector-extra-inst-table.adoc b/doc/vector-extra/riscv-crypto-vector-extra-inst-table.adoc index ee5a09c6..8bd81a2d 100644 --- a/doc/vector-extra/riscv-crypto-vector-extra-inst-table.adoc +++ b/doc/vector-extra/riscv-crypto-vector-extra-inst-table.adoc @@ -3,7 +3,7 @@ === Additional Vector Cryptographic Instructions OP-P (0x77) -Additional Vector Crypto instructions, including Zvkgs, except Zvbb and Zvbc +Vector Crypto instructions, including `Zvkgs`, except `Zvbb` and `Zvbc`. The new/modified encoding are in bold and underlined. // [cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] diff --git a/doc/vector-extra/riscv-crypto-vector-extra-zvkgs.adoc b/doc/vector-extra/riscv-crypto-vector-extra-zvkgs.adoc index c8d83965..99155dc5 100644 --- a/doc/vector-extra/riscv-crypto-vector-extra-zvkgs.adoc +++ b/doc/vector-extra/riscv-crypto-vector-extra-zvkgs.adoc @@ -10,11 +10,11 @@ The instructions inherit the constraints defined in `Zvkg`: - element group size (EGS) is 4 - data independent execution timing -- `vl`/`vstart` must be multiples of EGS=4multiple constraints +- `vl`/`vstart` must be multiples of EGS=4 -All of these instructions work on 128-bit element groups comprised of four 32-bit elements. +All of these instructions work on 128-bit element groups comprised of four 32-bit elements, in element group parlance `EGS=4`, `EGW=128` and the instructions are only defined for `SEW=32`. -To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. +To help avoid side-channel timing attacks, these instructions shall always be implemented with data-independent timing. The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and @@ -29,8 +29,8 @@ Likewise, `vstart` must be a multiple of `EGS=4`. |EGW |Mnemonic |Instruction -| 32 | 128 | vghsh.vs | <> -| 32 | 128 | vgmul.vs | <> +| 32 | 128 | `vghsh.vs` | <> +| 32 | 128 | `vgmul.vs` | <> |===