From db6c2f1878381389966544d7844c7d10c557083e Mon Sep 17 00:00:00 2001 From: danbone Date: Wed, 31 Jan 2024 16:42:30 +0000 Subject: [PATCH] Use MemoryAccessInfo instead of Inst for passing requests between caches and MSS (#144) As part of #143 use MemoryAccessInfo as the standard transaction type for making memory requests outside of the core, instead of instructions. This paves way for adding an instruction cache, as well as prefetching and more complicated memory subsystems where requests do not always correspond to a particularly instruction. Changes are minor, mostly just renaming. Co-authored-by: Daniel Bone --- core/DCache.cpp | 14 +-- core/DCache.hpp | 8 +- core/MemoryAccessInfo.hpp | 11 +-- mss/BIU.cpp | 16 ++-- mss/BIU.hpp | 14 +-- mss/L2Cache.cpp | 89 +++++++++---------- mss/L2Cache.hpp | 74 ++++++++------- mss/MSS.cpp | 6 +- mss/MSS.hpp | 6 +- test/core/l2cache/BIUSinkUnit.hpp | 22 ++--- test/core/l2cache/L2SourceUnit.hpp | 21 +++-- .../expected_output/hit_case.out.EXPECTED | 28 +++--- .../single_access.out.EXPECTED | 20 ++--- 13 files changed, 166 insertions(+), 163 deletions(-) diff --git a/core/DCache.cpp b/core/DCache.cpp index 70761c22..af8f0e37 100644 --- a/core/DCache.cpp +++ b/core/DCache.cpp @@ -15,7 +15,7 @@ namespace olympia { (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getAckFromL2Cache_, uint32_t)); in_l2cache_resp_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, InstPtr)); + (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, MemoryAccessInfoPtr)); // DL1 cache config const uint32_t l1_line_size = p->l1_line_size; @@ -84,7 +84,7 @@ namespace olympia { if(!busy_) { busy_ = true; cache_pending_inst_ = memory_access_info_ptr; - out_l2cache_req_.send(cache_pending_inst_->getInstPtr()); + out_l2cache_req_.send(cache_pending_inst_); // Set the --dcache_l2cache_credits_ here. } @@ -92,19 +92,19 @@ namespace olympia { out_lsu_lookup_ack_.send(memory_access_info_ptr); } - void DCache::getRespFromL2Cache_(const InstPtr &inst_ptr) { + void DCache::getRespFromL2Cache_(const MemoryAccessInfoPtr &memory_access_info_ptr) { out_lsu_lookup_req_.send(cache_pending_inst_); - reloadCache_(inst_ptr->getRAdr()); + reloadCache_(memory_access_info_ptr->getPhyAddr()); cache_pending_inst_.reset(); busy_ = false; } void DCache::getAckFromL2Cache_(const uint32_t &ack) { // When DCache sends the request to L2Cache for a miss, - // This bool will be set to false, and Dcache should wait for ack from + // This bool will be set to false, and Dcache should wait for ack from // L2Cache notifying DCache that there is space in it's dcache request buffer - // - // Set it to true so that the following misses from DCache can be sent out to L2Cache. + // + // Set it to true so that the following misses from DCache can be sent out to L2Cache. dcache_l2cache_credits_ = ack; } diff --git a/core/DCache.hpp b/core/DCache.hpp index 202d91e9..e5982cbd 100644 --- a/core/DCache.hpp +++ b/core/DCache.hpp @@ -40,7 +40,7 @@ namespace olympia void getAckFromL2Cache_(const uint32_t & ack); - void getRespFromL2Cache_(const InstPtr & inst_ptr); + void getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr); using L1Handle = CacheFuncModel::Handle; L1Handle l1_cache_; @@ -61,7 +61,8 @@ namespace olympia sparta::DataInPort in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1}; - sparta::DataInPort in_l2cache_resp_{&unit_port_set_, "in_l2cache_resp", 1}; + sparta::DataInPort in_l2cache_resp_{&unit_port_set_, + "in_l2cache_resp", 1}; //////////////////////////////////////////////////////////////////////////////// // Output Ports @@ -74,7 +75,8 @@ namespace olympia sparta::DataOutPort out_lsu_lookup_req_{&unit_port_set_, "out_lsu_lookup_req", 1}; - sparta::DataOutPort out_l2cache_req_{&unit_port_set_, "out_l2cache_req", 0}; + sparta::DataOutPort out_l2cache_req_{&unit_port_set_, + "out_l2cache_req", 0}; //////////////////////////////////////////////////////////////////////////////// // Events diff --git a/core/MemoryAccessInfo.hpp b/core/MemoryAccessInfo.hpp index 294fea36..ceb6be9d 100644 --- a/core/MemoryAccessInfo.hpp +++ b/core/MemoryAccessInfo.hpp @@ -61,6 +61,8 @@ namespace olympia MemoryAccessInfo() = delete; + MemoryAccessInfo(const MemoryAccessInfo &rhs) = default; + MemoryAccessInfo(const InstPtr & inst_ptr) : ldst_inst_ptr_(inst_ptr), phy_addr_ready_(false), @@ -92,6 +94,10 @@ namespace olympia bool getPhyAddrStatus() const { return phy_addr_ready_; } + uint64_t getPhyAddr() const { return ldst_inst_ptr_->getRAdr(); } + + sparta::memory::addr_t getVAddr() const { return ldst_inst_ptr_->getTargetVAddr(); } + void setSrcUnit(const ArchUnit & src_unit) { src_ = src_unit; } const ArchUnit & getSrcUnit() const { return src_; } @@ -158,11 +164,6 @@ namespace olympia // Not for functional/performance purpose) MemoryAccessInfoPtr next_req_ = nullptr; - // Scoreboards - using ScoreboardViews = - std::array, core_types::N_REGFILES>; - ScoreboardViews scoreboard_views_; - LoadStoreInstIterator issue_queue_iterator_; LoadStoreInstIterator replay_queue_iterator_; }; diff --git a/mss/BIU.cpp b/mss/BIU.cpp index bc0b1933..82452e1f 100644 --- a/mss/BIU.cpp +++ b/mss/BIU.cpp @@ -19,7 +19,7 @@ namespace olympia_mss biu_latency_(p->biu_latency) { in_biu_req_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(BIU, receiveReqFromL2Cache_, olympia::InstPtr)); + (CREATE_SPARTA_HANDLER_WITH_DATA(BIU, receiveReqFromL2Cache_, olympia::MemoryAccessInfoPtr)); in_mss_ack_sync_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(BIU, getAckFromMSS_, bool)); @@ -41,9 +41,9 @@ namespace olympia_mss } // Receive new BIU request from L2Cache - void BIU::receiveReqFromL2Cache_(const olympia::InstPtr & inst_ptr) + void BIU::receiveReqFromL2Cache_(const olympia::MemoryAccessInfoPtr & memory_access_info_ptr) { - appendReqQueue_(inst_ptr); + appendReqQueue_(memory_access_info_ptr); // Schedule BIU request handling event only when: // (1)BIU is not busy, and (2)Request queue is not empty @@ -81,9 +81,9 @@ namespace olympia_mss void BIU::handle_MSS_Ack_() { out_biu_resp_.send(biu_req_queue_.front(), biu_latency_); - + biu_req_queue_.pop_front(); - + // Send out the ack to L2Cache through , we just created space in biu_req_queue_ ev_handle_biu_l2cache_ack_.schedule(sparta::Clock::Cycle(0)); biu_busy_ = false; @@ -113,7 +113,7 @@ namespace olympia_mss } // Handle ack backto L2Cache - void BIU::handle_BIU_L2Cache_Ack_() + void BIU::handle_BIU_L2Cache_Ack_() { uint32_t available_slots = biu_req_queue_size_ - biu_req_queue_.size(); out_biu_ack_.send(available_slots); @@ -126,12 +126,12 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Append BIU request queue - void BIU::appendReqQueue_(const olympia::InstPtr& inst_ptr) + void BIU::appendReqQueue_(const olympia::MemoryAccessInfoPtr& memory_access_info_ptr) { sparta_assert(biu_req_queue_.size() <= biu_req_queue_size_ ,"BIU request queue overflows!"); // Push new requests from back - biu_req_queue_.emplace_back(inst_ptr); + biu_req_queue_.emplace_back(memory_access_info_ptr); ILOG("Append BIU request queue!"); } diff --git a/mss/BIU.hpp b/mss/BIU.hpp index f494ff64..55a84acd 100644 --- a/mss/BIU.hpp +++ b/mss/BIU.hpp @@ -12,7 +12,7 @@ #include "sparta/collection/Collectable.hpp" #include "sparta/events/StartupEvent.hpp" -#include "Inst.hpp" +#include "MemoryAccessInfo.hpp" #include "CoreTypes.hpp" #include "FlushManager.hpp" @@ -56,7 +56,7 @@ namespace olympia_mss // Input Ports //////////////////////////////////////////////////////////////////////////////// - sparta::DataInPort in_biu_req_ + sparta::DataInPort in_biu_req_ {&unit_port_set_, "in_biu_req", 1}; sparta::SyncInPort in_mss_ack_sync_ @@ -70,10 +70,10 @@ namespace olympia_mss sparta::DataOutPort out_biu_ack_ {&unit_port_set_, "out_biu_ack"}; - sparta::DataOutPort out_biu_resp_ + sparta::DataOutPort out_biu_resp_ {&unit_port_set_, "out_biu_resp"}; - sparta::SyncOutPort out_mss_req_sync_ + sparta::SyncOutPort out_mss_req_sync_ {&unit_port_set_, "out_mss_req_sync", getClock()}; @@ -81,7 +81,7 @@ namespace olympia_mss // Internal States //////////////////////////////////////////////////////////////////////////////// - using BusRequestQueue = std::list; + using BusRequestQueue = std::list; BusRequestQueue biu_req_queue_; const uint32_t biu_req_queue_size_; @@ -112,7 +112,7 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Receive new BIU request from L2Cache - void receiveReqFromL2Cache_(const olympia::InstPtr &); + void receiveReqFromL2Cache_(const olympia::MemoryAccessInfoPtr &); // Handle BIU request void handle_BIU_Req_(); @@ -135,6 +135,6 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Append BIU request queue - void appendReqQueue_(const olympia::InstPtr &); + void appendReqQueue_(const olympia::MemoryAccessInfoPtr &); }; } diff --git a/mss/L2Cache.cpp b/mss/L2Cache.cpp index e70280af..55c877d6 100644 --- a/mss/L2Cache.cpp +++ b/mss/L2Cache.cpp @@ -88,13 +88,13 @@ namespace olympia_mss // In Port Handler registration in_dcache_l2cache_req_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getReqFromDCache_, olympia::InstPtr)); + (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getReqFromDCache_, olympia::MemoryAccessInfoPtr)); in_icache_l2cache_req_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getReqFromICache_, olympia::InstPtr)); + (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getReqFromICache_, olympia::MemoryAccessInfoPtr)); in_biu_resp_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getRespFromBIU_, olympia::InstPtr)); + (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getRespFromBIU_, olympia::MemoryAccessInfoPtr)); in_biu_ack_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getAckFromBIU_, uint32_t)); @@ -145,33 +145,33 @@ namespace olympia_mss } // Receive new L2Cache request from DCache - void L2Cache::getReqFromDCache_(const olympia::InstPtr & inst_ptr) { + void L2Cache::getReqFromDCache_(const olympia::MemoryAccessInfoPtr & memory_access_info_ptr) { ILOG("Request received from DCache on the port"); - appendDCacheReqQueue_(inst_ptr); + appendDCacheReqQueue_(memory_access_info_ptr); ev_handle_dcache_l2cache_req_.schedule(sparta::Clock::Cycle(0)); ++num_reqs_from_dcache_; } // Receive new L2Cache request from ICache - void L2Cache::getReqFromICache_(const olympia::InstPtr & inst_ptr) { + void L2Cache::getReqFromICache_(const olympia::MemoryAccessInfoPtr & memory_access_info_ptr) { ILOG("Request received from ICache on the port"); - appendICacheReqQueue_(inst_ptr); + appendICacheReqQueue_(memory_access_info_ptr); ev_handle_icache_l2cache_req_.schedule(sparta::Clock::Cycle(0)); ++num_reqs_from_icache_; } // Handle BIU resp - void L2Cache::getRespFromBIU_(const olympia::InstPtr & inst_ptr) { + void L2Cache::getRespFromBIU_(const olympia::MemoryAccessInfoPtr & memory_access_info_ptr) { ILOG("Response received from BIU on the port"); - appendBIURespQueue_(inst_ptr); + appendBIURespQueue_(memory_access_info_ptr); // Schedule BIU resp handling event only when: // Request queue is not empty @@ -281,14 +281,14 @@ namespace olympia_mss if (arbitration_winner == Channel::BIU) { - const olympia::InstPtr &instPtr = biu_resp_queue_.front(); + const olympia::MemoryAccessInfoPtr &memory_access_info_ptr = biu_resp_queue_.front(); // Function to check if the request to the given cacheline is present in the miss_pending_buffer_ - auto getCacheLine = [this] (auto inst_ptr) { return inst_ptr->getRAdr() >> shiftBy_; }; - auto const inst_cl = getCacheLine(instPtr); + auto getCacheLine = [this] (auto memory_access_info_ptr) { return memory_access_info_ptr->getPhyAddr() >> shiftBy_; }; + auto const inst_cl = getCacheLine(memory_access_info_ptr); - auto is_cl_present = [inst_cl, getCacheLine] (auto reqPtr) - { return getCacheLine(reqPtr->getInstPtr()) == inst_cl; }; + auto is_cl_present = [inst_cl, getCacheLine] (auto req) + { return getCacheLine(req) == inst_cl; }; auto req = std::find_if(miss_pending_buffer_.begin(), miss_pending_buffer_.end(), is_cl_present); @@ -326,7 +326,7 @@ namespace olympia_mss else if (arbitration_winner == Channel::ICACHE) { const auto &reqPtr = sparta::allocate_sparta_shared_pointer(memory_access_allocator_, - icache_req_queue_.front()); + *(icache_req_queue_.front())); reqPtr->setSrcUnit(L2ArchUnit::ICACHE); reqPtr->setDestUnit(L2ArchUnit::ICACHE); @@ -342,7 +342,7 @@ namespace olympia_mss else if (arbitration_winner == Channel::DCACHE) { const auto &reqPtr = sparta::allocate_sparta_shared_pointer(memory_access_allocator_, - dcache_req_queue_.front()); + *(dcache_req_queue_.front())); reqPtr->setSrcUnit(L2ArchUnit::DCACHE); reqPtr->setDestUnit(L2ArchUnit::DCACHE); @@ -397,7 +397,7 @@ namespace olympia_mss // Pipeline Stage CACHE_LOOKUP void L2Cache::handleCacheAccessRequest_() { const auto req = l2cache_pipeline_[stages_.CACHE_LOOKUP]; - ILOG("Pipeline stage CACHE_LOOKUP : " << req->getInstPtr()); + ILOG("Pipeline stage CACHE_LOOKUP : " << req); const L2CacheState cacheLookUpResult = cacheLookup_(req); @@ -407,9 +407,9 @@ namespace olympia_mss if (cacheLookUpResult == L2CacheState::MISS) { // Reload cache line - reloadCache_(req->getInstPtr()->getRAdr()); + reloadCache_(req->getPhyAddr()); - ILOG("Reload Complete: phyAddr=0x" << std::hex << req->getInstPtr()->getRAdr()); + ILOG("Reload Complete: phyAddr=0x" << std::hex << req->getPhyAddr()); } req->setCacheState(L2CacheState::HIT); @@ -424,7 +424,7 @@ namespace olympia_mss // Pipeline Stage HIT_MISS_HANDLING void L2Cache::handleCacheAccessResult_() { const auto req = l2cache_pipeline_[stages_.HIT_MISS_HANDLING]; - ILOG("Pipeline stage HIT_MISS_HANDLING : " << req->getInstPtr()); + ILOG("Pipeline stage HIT_MISS_HANDLING : " << req); --inFlight_reqs_; @@ -437,7 +437,7 @@ namespace olympia_mss // If it was a hit in L2Cache, return the request back to where it originally came from. // // Send out the resp to the original SrcUnit -- which is now the DestUnit. - sendOutResp_(req->getDestUnit(), req->getInstPtr()); + sendOutResp_(req->getDestUnit(), req); } else { // if (req->getCacheState() == L2CacheState::MISS) @@ -456,7 +456,7 @@ namespace olympia_mss } // Function to check if the request to the given cacheline is present in the miss_pending_buffer_ - auto getCacheLine = [this] (auto reqPtr) { return reqPtr->getInstPtr()->getRAdr() >> shiftBy_; }; + auto getCacheLine = [this] (auto reqPtr) { return reqPtr->getPhyAddr() >> shiftBy_; }; const auto req_cl = getCacheLine(req); auto is_cl_present = [&req, req_cl, getCacheLine] (auto reqPtr) @@ -466,7 +466,7 @@ namespace olympia_mss auto reqIter = std::find_if(miss_pending_buffer_.rbegin(), miss_pending_buffer_.rend(), is_cl_present); if (reqIter == miss_pending_buffer_.rend()) { - sendOutReq_(req->getDestUnit(), req->getInstPtr()); + sendOutReq_(req->getDestUnit(), req); } else { // Found a request to same cacheLine. @@ -481,75 +481,75 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Append L2Cache request queue for reqs from DCache - void L2Cache::appendDCacheReqQueue_(const olympia::InstPtr& inst_ptr) { + void L2Cache::appendDCacheReqQueue_(const olympia::MemoryAccessInfoPtr& memory_access_info_ptr) { sparta_assert(dcache_req_queue_.size() <= dcache_req_queue_size_ ,"DCache request queue overflows!"); // Push new requests from back - dcache_req_queue_.emplace_back(inst_ptr); + dcache_req_queue_.emplace_back(memory_access_info_ptr); ILOG("Append DCache->L2Cache request queue!"); } // Append L2Cache request queue for reqs from ICache - void L2Cache::appendICacheReqQueue_(const olympia::InstPtr& inst_ptr) { + void L2Cache::appendICacheReqQueue_(const olympia::MemoryAccessInfoPtr& memory_access_info_ptr) { sparta_assert(icache_req_queue_.size() <= icache_req_queue_size_ ,"ICache request queue overflows!"); // Push new requests from back - icache_req_queue_.emplace_back(inst_ptr); + icache_req_queue_.emplace_back(memory_access_info_ptr); ILOG("Append ICache->L2Cache request queue!"); } // Append BIU resp queue - void L2Cache::appendBIURespQueue_(const olympia::InstPtr& inst_ptr) { + void L2Cache::appendBIURespQueue_(const olympia::MemoryAccessInfoPtr& memory_access_info_ptr) { sparta_assert(biu_resp_queue_.size() <= biu_resp_queue_size_ ,"BIU resp queue overflows!"); // Push new requests from back - biu_resp_queue_.emplace_back(inst_ptr); + biu_resp_queue_.emplace_back(memory_access_info_ptr); ILOG("Append BIU->L2Cache resp queue!"); } // Append DCache resp queue - void L2Cache::appendDCacheRespQueue_(const olympia::InstPtr& inst_ptr) { + void L2Cache::appendDCacheRespQueue_(const olympia::MemoryAccessInfoPtr& memory_access_info_ptr) { sparta_assert(dcache_resp_queue_.size() <= dcache_resp_queue_size_ ,"DCache resp queue overflows!"); // Push new resp to the dcache_resp_queue_ - dcache_resp_queue_.emplace_back(inst_ptr); + dcache_resp_queue_.emplace_back(memory_access_info_ptr); ev_handle_l2cache_dcache_resp_.schedule(sparta::Clock::Cycle(0)); ILOG("Append L2Cache->DCache resp queue!"); } // Append ICache resp queue - void L2Cache::appendICacheRespQueue_(const olympia::InstPtr& inst_ptr) { + void L2Cache::appendICacheRespQueue_(const olympia::MemoryAccessInfoPtr& memory_access_info_ptr) { sparta_assert(icache_resp_queue_.size() <= icache_resp_queue_size_ ,"ICache resp queue overflows!"); // Push new resp to the icache_resp_queue_ - icache_resp_queue_.emplace_back(inst_ptr); + icache_resp_queue_.emplace_back(memory_access_info_ptr); ev_handle_l2cache_icache_resp_.schedule(sparta::Clock::Cycle(0)); ILOG("Append L2Cache->ICache resp queue!"); } // Append BIU req queue - void L2Cache::appendBIUReqQueue_(const olympia::InstPtr& inst_ptr) { + void L2Cache::appendBIUReqQueue_(const olympia::MemoryAccessInfoPtr& memory_access_info_ptr) { sparta_assert(biu_req_queue_.size() <= biu_req_queue_size_ ,"BIU req queue overflows!"); // Push new request to the biu_req_queue_ if biu credits are available with the L2Cache - biu_req_queue_.emplace_back(inst_ptr); + biu_req_queue_.emplace_back(memory_access_info_ptr); ev_handle_l2cache_biu_req_.schedule(sparta::Clock::Cycle(0)); ILOG("Append L2Cache->BIU req queue"); } // Return the resp to the master units - void L2Cache::sendOutResp_(const L2ArchUnit &unit, const olympia::InstPtr& instPtr) { - // if (instPtr is originally from DCache) + void L2Cache::sendOutResp_(const L2ArchUnit &unit, const olympia::MemoryAccessInfoPtr& MemoryAccessInfoPtr) { + // if (MemoryAccessInfoPtr is originally from DCache) if (unit == L2ArchUnit::DCACHE) { - appendDCacheRespQueue_(instPtr); + appendDCacheRespQueue_(MemoryAccessInfoPtr); } - // if (instPtr is originally from ICache) + // if (MemoryAccessInfoPtr is originally from ICache) else if (unit == L2ArchUnit::ICACHE) { - appendICacheRespQueue_(instPtr); + appendICacheRespQueue_(MemoryAccessInfoPtr); } else { sparta_assert(false, "Resp is being sent to a Unit that is not valid"); @@ -557,10 +557,10 @@ namespace olympia_mss } // Send the request to the slave units - void L2Cache::sendOutReq_(const L2ArchUnit &unit, const olympia::InstPtr& instPtr) { - // if (instPtr is destined for BIU on L2Cache miss) + void L2Cache::sendOutReq_(const L2ArchUnit &unit, const olympia::MemoryAccessInfoPtr& MemoryAccessInfoPtr) { + // if (MemoryAccessInfoPtr is destined for BIU on L2Cache miss) if (unit == L2ArchUnit::BIU) { - appendBIUReqQueue_(instPtr); + appendBIUReqQueue_(MemoryAccessInfoPtr); } else { sparta_assert(false, "Request is being sent to a Unit that is not valid"); @@ -622,8 +622,7 @@ namespace olympia_mss // Cache lookup for a HIT or MISS on a given request L2Cache::L2CacheState L2Cache::cacheLookup_(olympia::MemoryAccessInfoPtr mem_access_info_ptr) { - const olympia::InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr(); - uint64_t phyAddr = inst_ptr->getRAdr(); + uint64_t phyAddr = mem_access_info_ptr->getPhyAddr(); bool cache_hit = false; diff --git a/mss/L2Cache.hpp b/mss/L2Cache.hpp index 9a999ebb..a5fb1610 100644 --- a/mss/L2Cache.hpp +++ b/mss/L2Cache.hpp @@ -22,7 +22,6 @@ #include "sparta/resources/Pipe.hpp" #include "sparta/resources/Pipeline.hpp" -#include "Inst.hpp" #include "CoreTypes.hpp" #include "MemoryAccessInfo.hpp" @@ -50,7 +49,7 @@ namespace olympia_mss PARAMETER(uint32_t, biu_resp_queue_size, 4, "BIU resp queue size") PARAMETER(uint32_t, pipeline_req_queue_size, 64, "Pipeline request buffer size") PARAMETER(uint32_t, miss_pending_buffer_size, 64, "Pipeline request buffer size") - + // Parameters for the L2 cache PARAMETER(uint32_t, l2_line_size, 64, "L2 line size (power of 2)") PARAMETER(uint32_t, l2_size_kb, 512, "Size of L2 in KB (power of 2)") @@ -81,7 +80,6 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Statistics and Counters //////////////////////////////////////////////////////////////////////////////// - // sparta::StatisticDef cycles_per_instr_; // A simple expression to calculate IPC sparta::Counter num_reqs_from_dcache_; // Counter of number instructions received from DCache sparta::Counter num_reqs_from_icache_; // Counter of number instructions received from ICache sparta::Counter num_reqs_to_biu_; // Counter of number instructions forwarded to BIU -- Totals misses @@ -100,13 +98,13 @@ namespace olympia_mss // Input Ports //////////////////////////////////////////////////////////////////////////////// - sparta::DataInPort in_dcache_l2cache_req_ + sparta::DataInPort in_dcache_l2cache_req_ {&unit_port_set_, "in_dcache_l2cache_req", 1}; - sparta::DataInPort in_icache_l2cache_req_ + sparta::DataInPort in_icache_l2cache_req_ {&unit_port_set_, "in_icache_l2cache_req", 1}; - sparta::DataInPort in_biu_resp_ + sparta::DataInPort in_biu_resp_ {&unit_port_set_, "in_biu_l2cache_resp", 1}; sparta::DataInPort in_biu_ack_ @@ -117,13 +115,13 @@ namespace olympia_mss // Output Ports //////////////////////////////////////////////////////////////////////////////// - sparta::DataOutPort out_biu_req_ + sparta::DataOutPort out_biu_req_ {&unit_port_set_, "out_l2cache_biu_req"}; - sparta::DataOutPort out_l2cache_icache_resp_ + sparta::DataOutPort out_l2cache_icache_resp_ {&unit_port_set_, "out_l2cache_icache_resp"}; - sparta::DataOutPort out_l2cache_dcache_resp_ + sparta::DataOutPort out_l2cache_dcache_resp_ {&unit_port_set_, "out_l2cache_dcache_resp"}; sparta::DataOutPort out_l2cache_icache_ack_ @@ -137,8 +135,8 @@ namespace olympia_mss // Internal States //////////////////////////////////////////////////////////////////////////////// - - using CacheRequestQueue = std::vector; + + using CacheRequestQueue = std::vector; // Buffers for the incoming requests from DCache and ICache CacheRequestQueue dcache_req_queue_; @@ -175,7 +173,7 @@ namespace olympia_mss NUM_CHANNELS, __LAST = NUM_CHANNELS }; - + // Cache Pipeline class PipelineStages { @@ -189,25 +187,25 @@ namespace olympia_mss const uint32_t CACHE_LOOKUP; const uint32_t NO_ACCESS = 0; }; - + using L2ArchUnit = olympia::MemoryAccessInfo::ArchUnit; using L2CacheState = olympia::MemoryAccessInfo::CacheState; using L2CachePipeline = sparta::Pipeline; - + PipelineStages stages_; L2CachePipeline l2cache_pipeline_; - + sparta::Queue pipeline_req_queue_; uint32_t inFlight_reqs_ = 0; - + sparta::Buffer miss_pending_buffer_; const uint32_t miss_pending_buffer_size_; - + // L2 Cache using CacheHandle = olympia::CacheFuncModel::Handle; CacheHandle l2_cache_; - + const uint32_t l2_lineSize_; const uint32_t shiftBy_; const bool l2_always_hit_; @@ -257,11 +255,11 @@ namespace olympia_mss // Event to handle L2Cache ack for DCache sparta::UniqueEvent<> ev_handle_l2cache_dcache_ack_ {&unit_event_set_, "ev_handle_l2cache_dcache_ack", CREATE_SPARTA_HANDLER(L2Cache, handle_L2Cache_DCache_Ack_)}; - + // Event to create request for pipeline and feed it to the pipeline_req_queue_ sparta::UniqueEvent ev_create_req_ {&unit_event_set_, "create_req", CREATE_SPARTA_HANDLER(L2Cache, create_Req_)}; - + // Event to issue request to pipeline sparta::UniqueEvent ev_issue_req_ {&unit_event_set_, "issue_req", CREATE_SPARTA_HANDLER(L2Cache, issue_Req_)}; @@ -271,13 +269,13 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Receive new L2Cache request from DCache - void getReqFromDCache_(const olympia::InstPtr &); + void getReqFromDCache_(const olympia::MemoryAccessInfoPtr &); // Receive new L2Cache request from ICache - void getReqFromICache_(const olympia::InstPtr &); + void getReqFromICache_(const olympia::MemoryAccessInfoPtr &); // Receive BIU access Response - void getRespFromBIU_(const olympia::InstPtr &); + void getRespFromBIU_(const olympia::MemoryAccessInfoPtr &); // Receive BIU ack Response void getAckFromBIU_(const uint32_t &); @@ -309,10 +307,10 @@ namespace olympia_mss // Pipeline request create callback void create_Req_(); - + // Pipeline request issue callback void issue_Req_(); - + // Pipeline callbacks // Stage 1 @@ -329,43 +327,43 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Append L2Cache request queue for reqs from DCache - void appendDCacheReqQueue_(const olympia::InstPtr &); + void appendDCacheReqQueue_(const olympia::MemoryAccessInfoPtr &); // Append L2Cache request queue for reqs from ICache - void appendICacheReqQueue_(const olympia::InstPtr &); + void appendICacheReqQueue_(const olympia::MemoryAccessInfoPtr &); // Append L2Cache request queue for reqs to BIU - void appendBIUReqQueue_(const olympia::InstPtr &); + void appendBIUReqQueue_(const olympia::MemoryAccessInfoPtr &); // Append L2Cache resp queue for resps from BIU - void appendBIURespQueue_(const olympia::InstPtr &); + void appendBIURespQueue_(const olympia::MemoryAccessInfoPtr &); // Append L2Cache resp queue for resps to DCache BIU - void appendDCacheRespQueue_(const olympia::InstPtr &); + void appendDCacheRespQueue_(const olympia::MemoryAccessInfoPtr &); // Append L2Cache resp queue for resps to ICache - void appendICacheRespQueue_(const olympia::InstPtr &); + void appendICacheRespQueue_(const olympia::MemoryAccessInfoPtr &); + - // Select the channel to pick the request from - // Current options : + // Current options : // BIU - P0 // ICache - P1 - RoundRobin Candidate // DCache - P1 - RoundRobin Candidate Channel arbitrateL2CacheAccessReqs_(); - - // Cache lookup for a HIT or MISS on a given request + + // Cache lookup for a HIT or MISS on a given request L2CacheState cacheLookup_(sparta::SpartaSharedPointer); - + // Allocating the cacheline in the L2 bbased on return from BIU/L3 void reloadCache_(uint64_t); // Return the resp to the master units - void sendOutResp_(const L2ArchUnit&, const olympia::InstPtr&); + void sendOutResp_(const L2ArchUnit&, const olympia::MemoryAccessInfoPtr&); // Send the request to the slave units - void sendOutReq_(const L2ArchUnit&, const olympia::InstPtr&); + void sendOutReq_(const L2ArchUnit&, const olympia::MemoryAccessInfoPtr&); // Check if there are enough credits for the request to be issued to the l2cache_pipeline_ bool hasCreditsForPipelineIssue_(); diff --git a/mss/MSS.cpp b/mss/MSS.cpp index 9f21876b..99d5fe40 100644 --- a/mss/MSS.cpp +++ b/mss/MSS.cpp @@ -17,7 +17,7 @@ namespace olympia_mss mss_latency_(p->mss_latency) { in_mss_req_sync_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(MSS, getReqFromBIU_, olympia::InstPtr)); + (CREATE_SPARTA_HANDLER_WITH_DATA(MSS, getReqFromBIU_, olympia::MemoryAccessInfoPtr)); in_mss_req_sync_.setPortDelay(static_cast(1)); ILOG("MSS construct: #" << node->getGroupIdx()); @@ -29,9 +29,9 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Receive new MSS request from BIU - void MSS::getReqFromBIU_(const olympia::InstPtr & inst_ptr) + void MSS::getReqFromBIU_(const olympia::MemoryAccessInfoPtr & memory_access_info_ptr) { - sparta_assert((inst_ptr != nullptr), "MSS is not handling a valid request!"); + sparta_assert((memory_access_info_ptr != nullptr), "MSS is not handling a valid request!"); // Handle MSS request event can only be scheduled when MMS is not busy if (!mss_busy_) { diff --git a/mss/MSS.hpp b/mss/MSS.hpp index bdde3fac..db6c5b7f 100644 --- a/mss/MSS.hpp +++ b/mss/MSS.hpp @@ -14,7 +14,7 @@ #include "sparta/ports/SyncPort.hpp" #include "sparta/resources/Pipe.hpp" -#include "Inst.hpp" +#include "MemoryAccessInfo.hpp" #include "CoreTypes.hpp" #include "FlushManager.hpp" @@ -53,7 +53,7 @@ namespace olympia_mss // Input Ports //////////////////////////////////////////////////////////////////////////////// - sparta::SyncInPort in_mss_req_sync_ + sparta::SyncInPort in_mss_req_sync_ {&unit_port_set_, "in_mss_req_sync", getClock()}; @@ -86,7 +86,7 @@ namespace olympia_mss //////////////////////////////////////////////////////////////////////////////// // Receive new MSS request from BIU - void getReqFromBIU_(const olympia::InstPtr &); + void getReqFromBIU_(const olympia::MemoryAccessInfoPtr &); // Handle MSS request void handle_MSS_req_(); diff --git a/test/core/l2cache/BIUSinkUnit.hpp b/test/core/l2cache/BIUSinkUnit.hpp index ed72857f..47e2b044 100644 --- a/test/core/l2cache/BIUSinkUnit.hpp +++ b/test/core/l2cache/BIUSinkUnit.hpp @@ -17,7 +17,7 @@ namespace l2cache_test { public: static constexpr char name[] = "BIUSinkUnit"; - + class BIUSinkUnitParameters : public sparta::ParameterSet { public: @@ -29,12 +29,12 @@ namespace l2cache_test }; BIUSinkUnit(sparta::TreeNode * n, const BIUSinkUnitParameters * params) : sparta::Unit(n) { - + purpose_ = params->purpose; sink_latency_ = params->sink_latency; in_biu_req_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(BIUSinkUnit, sinkInst_, olympia::InstPtr)); + (CREATE_SPARTA_HANDLER_WITH_DATA(BIUSinkUnit, sinkInst_, olympia::MemoryAccessInfoPtr)); sparta::StartupEvent(n, CREATE_SPARTA_HANDLER(BIUSinkUnit, sendInitialCredits_)); } @@ -46,20 +46,20 @@ namespace l2cache_test out_biu_ack_.send(biu_req_queue_size_); ILOG("Sending initial credits to L2Cache : " << biu_req_queue_size_); } - - void sinkInst_(const olympia::InstPtr & instPtr) { - ILOG("Instruction: '" << instPtr << "' sinked"); + + void sinkInst_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) { + ILOG("Instruction: '" << mem_access_info_ptr->getInstPtr() << "' sinked"); uint32_t biu_req_queue_size_ = 32; out_biu_ack_.send(biu_req_queue_size_, sink_latency_); - out_biu_resp_.send(instPtr, 2*sink_latency_); + out_biu_resp_.send(mem_access_info_ptr, 2*sink_latency_); } - sparta::DataInPort in_biu_req_ {&unit_port_set_, "in_biu_req", - sparta::SchedulingPhase::Tick, 1}; - sparta::DataOutPort out_biu_resp_ {&unit_port_set_, "out_biu_resp"}; - sparta::DataOutPort out_biu_ack_ {&unit_port_set_, "out_biu_ack"}; + sparta::DataInPort in_biu_req_ {&unit_port_set_, "in_biu_req", + sparta::SchedulingPhase::Tick, 1}; + sparta::DataOutPort out_biu_resp_ {&unit_port_set_, "out_biu_resp"}; + sparta::DataOutPort out_biu_ack_ {&unit_port_set_, "out_biu_ack"}; std::string purpose_; sparta::Clock::Cycle sink_latency_; diff --git a/test/core/l2cache/L2SourceUnit.hpp b/test/core/l2cache/L2SourceUnit.hpp index 09194694..05aab52f 100644 --- a/test/core/l2cache/L2SourceUnit.hpp +++ b/test/core/l2cache/L2SourceUnit.hpp @@ -1,6 +1,7 @@ #pragma once +#include "core/MemoryAccessInfo.hpp" #include "core/InstGenerator.hpp" #include "core/MavisUnit.hpp" #include "mavis/ExtractorDirectInfo.h" @@ -41,7 +42,7 @@ namespace l2cache_test sparta_assert(mavis_facade_ != nullptr, "Could not find the Mavis Unit"); in_source_resp_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveInst_, olympia::InstPtr)); + (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveInst_, olympia::MemoryAccessInfoPtr)); in_source_ack_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveAck_, uint32_t)); @@ -72,7 +73,9 @@ namespace l2cache_test dinst = inst_generator_->getNextInst(getClock()); dinst->setUniqueID(unique_id_++); - req_inst_queue_.emplace_back(dinst); + olympia::MemoryAccessInfoPtr mem_info_ptr(new olympia::MemoryAccessInfo(dinst)); + + req_inst_queue_.emplace_back(mem_info_ptr); ev_req_inst_.schedule(schedule_time_); schedule_time_ += delay_btwn_insts_; @@ -82,7 +85,7 @@ namespace l2cache_test void req_inst_() { - ILOG("Instruction: '" << req_inst_queue_.front() << "' Requested"); + ILOG("Instruction: '" << req_inst_queue_.front()->getInstPtr() << "' Requested"); pending_reqs_++; pending_acks_++; @@ -91,9 +94,9 @@ namespace l2cache_test req_inst_queue_.erase(req_inst_queue_.begin()); } - void ReceiveInst_(const olympia::InstPtr & instPtr) { + void ReceiveInst_(const olympia::MemoryAccessInfoPtr & mem_info_ptr) { pending_reqs_--; - ILOG("Instruction: '" << instPtr << "' Received"); + ILOG("Instruction: '" << mem_info_ptr->getInstPtr() << "' Received"); } void ReceiveAck_(const uint32_t & ack) { @@ -101,11 +104,11 @@ namespace l2cache_test ILOG("Ack: '" << ack << "' Received"); } - sparta::DataInPort in_source_resp_ {&unit_port_set_, "in_source_resp", + sparta::DataInPort in_source_resp_ {&unit_port_set_, "in_source_resp", sparta::SchedulingPhase::Tick, 1}; - sparta::DataInPort in_source_ack_ {&unit_port_set_, "in_source_ack"}; + sparta::DataInPort in_source_ack_ {&unit_port_set_, "in_source_ack"}; - sparta::DataOutPort out_source_req_ {&unit_port_set_, "out_source_req"}; + sparta::DataOutPort out_source_req_ {&unit_port_set_, "out_source_req"}; uint32_t pending_acks_ = 1; uint32_t pending_reqs_ = 0; @@ -119,7 +122,7 @@ namespace l2cache_test sparta::UniqueEvent<> ev_req_inst_ {&unit_event_set_, "req_inst", CREATE_SPARTA_HANDLER(L2SourceUnit, req_inst_)}; - std::vector req_inst_queue_; + std::vector req_inst_queue_; sparta::Clock::Cycle schedule_time_ = 0; sparta::Clock::Cycle delay_btwn_insts_ = 0; bool unit_enable_; diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index abf6f485..abf3ec67 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Friday Fri Nov 17 11:05:39 2023 -#Elapsed: 0.074727s +#Start: Saturday Sat Jan 27 08:59:40 2024 +#Elapsed: 0.004092s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 {0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! {0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! {0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received @@ -77,15 +77,15 @@ {0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! {0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! {0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index 0a296dc2..bf6d8619 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Friday Fri Nov 17 11:01:07 2023 -#Elapsed: 0.082742s +#Start: Saturday Sat Jan 27 08:59:40 2024 +#Elapsed: 0.003294s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 {0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! {0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! {0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received