From 836dbbd24a4bbec9b223679559d8117ec8337cfb Mon Sep 17 00:00:00 2001 From: Knute Lingaard Date: Fri, 7 Jul 2023 11:09:16 -0500 Subject: [PATCH] Fixed another issue related to i2f; added pipe support/debug messages (#63) Couple more things: - Improved the performance of the simulator by reducing retire events - Added param support to enable/disable skipping of non-user mode instructions in an STF - Added more debug messages - Added Rename stall conditions/counters - Fixed instruction status; was not being updated --- CMakeLists.txt | 3 +- arches/isa_json/olympia_uarch_rv64b.json | 70 ++-- arches/isa_json/olympia_uarch_rv64c.json | 72 ++-- arches/isa_json/olympia_uarch_rv64g.json | 336 +++++++++--------- core/Decode.cpp | 6 +- core/Dispatch.cpp | 2 + core/ExecutePipe.cpp | 42 ++- core/Fetch.cpp | 5 +- core/Fetch.hpp | 7 +- core/Inst.hpp | 84 +++-- core/InstArchInfo.cpp | 25 ++ core/InstArchInfo.hpp | 23 ++ core/InstGenerator.cpp | 14 +- core/InstGenerator.hpp | 9 +- core/LSU.cpp | 42 ++- core/LSU.hpp | 49 ++- core/ROB.cpp | 35 +- core/ROB.hpp | 7 + core/Rename.cpp | 89 +++-- core/Rename.hpp | 61 +++- test/core/common/SourceUnit.hpp | 2 +- .../expected_output/big_core.out.EXPECTED | 64 ++-- .../expected_output/medium_core.out.EXPECTED | 64 ++-- .../expected_output/small_core.out.EXPECTED | 64 ++-- .../expected_output/big_core.out.EXPECTED | 134 +++---- .../big_core_small_rename.out.EXPECTED | 137 +++---- .../expected_output/medium_core.out.EXPECTED | 134 +++---- .../expected_output/small_core.out.EXPECTED | 134 +++---- 28 files changed, 986 insertions(+), 728 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index dde60b66..ce21aee3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -64,12 +64,13 @@ elseif (CMAKE_BUILD_TYPE MATCHES "^[Dd]ebug") elseif (CMAKE_BUILD_TYPE MATCHES "^[Pp]rofile") set(SPARTA_BUILD_TYPE "release") else() - message (FATAL_ERROR "Please provide a CMAKE_BUILD_TYPE: -DCMAKE_BUILD_TYPE=Release|Debug|Profile") + message (FATAL_ERROR "Please provide a CMAKE_BUILD_TYPE: -DCMAKE_BUILD_TYPE=Release|FastDebug|Debug|Profile") endif() # Profile build flags set(CMAKE_CXX_FLAGS_PROFILE "-O3 -pg -g -ftime-trace") set(CMAKE_CXX_FLAGS_FASTDEBUG "-O3 -g") +set(CMAKE_CXX_FLAGS_DEBUG "-O0 -g") # Include directories include_directories (core mss) diff --git a/arches/isa_json/olympia_uarch_rv64b.json b/arches/isa_json/olympia_uarch_rv64b.json index 8454307e..cfa7573d 100644 --- a/arches/isa_json/olympia_uarch_rv64b.json +++ b/arches/isa_json/olympia_uarch_rv64b.json @@ -2,211 +2,211 @@ { "mnemonic" : "rol", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sh2add", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "ror", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "clz", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "xnor", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sh3add", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "ctzw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sh1add.uw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "packuw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "orn", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "cpop", "dispatch" : ["alu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 3 }, { "mnemonic" : "rori", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "ctz", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sext.h", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "rorw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sext.b", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "slli.uw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "andn", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "add.uw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "packu", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "packw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "roriw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sh3add.uw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "pack", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sh2add.uw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "minu", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "rolw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "min", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "gorci", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "clzw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "maxu", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sh1add", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "max", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "grevi", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "cpopw", "dispatch" : ["alu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 3 } ] diff --git a/arches/isa_json/olympia_uarch_rv64c.json b/arches/isa_json/olympia_uarch_rv64c.json index 7033d0c0..ece7c4b6 100644 --- a/arches/isa_json/olympia_uarch_rv64c.json +++ b/arches/isa_json/olympia_uarch_rv64c.json @@ -2,217 +2,217 @@ { "mnemonic" : "c.addi4spn", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.fld", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.lw", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.ld", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.fsd", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.sw", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.sd", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.addi", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.addi16sp", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.jr", "dispatch" : ["alu"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "c.addiw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.jalr", "dispatch" : ["alu"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "c.li", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.lui", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.srli", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.srai", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.andi", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.sub", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.xor", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.or", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.and", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.subw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.addw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.j", "dispatch" : ["alu"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "c.beqz", "dispatch" : ["alu"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "c.bnez", "dispatch" : ["alu"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "c.slli", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.fldsp", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.lwsp", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.ldsp", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.mv", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.ebreak", "dispatch" : ["rob"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.add", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "c.fsdsp", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.swsp", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "c.sdsp", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 } ] diff --git a/arches/isa_json/olympia_uarch_rv64g.json b/arches/isa_json/olympia_uarch_rv64g.json index 9e7164ca..c5715da1 100644 --- a/arches/isa_json/olympia_uarch_rv64g.json +++ b/arches/isa_json/olympia_uarch_rv64g.json @@ -2,1037 +2,1037 @@ { "mnemonic" : "beq", "dispatch" : ["br"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "bne", "dispatch" : ["br"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "blt", "dispatch" : ["br"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "bge", "dispatch" : ["br"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "bltu", "dispatch" : ["br"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "bgeu", "dispatch" : ["br"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "jalr", "dispatch" : ["br"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "jal", "dispatch" : ["br"], - "pipe" : ["br"], + "pipe" : "br", "latency" : 1 }, { "mnemonic" : "lui", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "auipc", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "addi", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "nop", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "mv", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "cmov", "dispatch" : ["alu"], - "pipe" : ["cmov"], + "pipe" : "cmov", "latency" : 1 }, { "mnemonic" : "slli", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "slti", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sltiu", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "xori", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "srli", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "srai", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "ori", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "andi", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "add", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sub", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sll", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "slt", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sltu", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "xor", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "srl", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sra", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "or", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "and", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "addiw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "slliw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "srliw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sraiw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "addw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "subw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sllw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "srlw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "sraw", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "lb", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "lh", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "lw", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "ld", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "lbu", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "lhu", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "lwu", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "sb", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "sh", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "sw", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "sd", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "fence", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "fence.i", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "mul", "dispatch" : ["alu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 3 }, { "mnemonic" : "mulh", "dispatch" : ["alu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 3 }, { "mnemonic" : "mulhsu", "dispatch" : ["alu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 3 }, { "mnemonic" : "mulhu", "dispatch" : ["alu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 3 }, { "mnemonic" : "div", "dispatch" : ["alu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 23 }, { "mnemonic" : "divu", "dispatch" : ["alu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 23 }, { "mnemonic" : "rem", "dispatch" : ["alu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 23 }, { "mnemonic" : "remu", "dispatch" : ["alu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 23 }, { "mnemonic" : "mulw", "dispatch" : ["alu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 3 }, { "mnemonic" : "divw", "dispatch" : ["alu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 23 }, { "mnemonic" : "divuw", "dispatch" : ["alu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 23 }, { "mnemonic" : "remw", "dispatch" : ["alu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 23 }, { "mnemonic" : "remuw", "dispatch" : ["alu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 23 }, { "mnemonic" : "amoadd.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amoxor.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amoor.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amoand.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amomin.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amomax.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amominu.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amomaxu.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amoswap.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "lr.w", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "sc.w", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "amoadd.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amoxor.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amoor.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amoand.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amomin.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amomax.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amominu.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amomaxu.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "amoswap.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "lr.d", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "sc.d", "dispatch" : ["alu"], - "pipe" : ["int"], + "pipe" : "int", "latency" : 1 }, { "mnemonic" : "ecall", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "ebreak", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "uret", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "sret", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "mret", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "dret", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "sfence.vma", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "wfi", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "csrrw", "dispatch" : ["alu"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "csrrs", "dispatch" : ["alu"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "csrrc", "dispatch" : ["alu"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "csrrwi", "dispatch" : ["alu"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "csrrsi", "dispatch" : ["alu"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "csrrci", "dispatch" : ["alu"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "cflush.d.l1", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "cdiscard.d.l1", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "cflush.i.l1", "dispatch" : ["rob"], - "pipe" : ["sys"], + "pipe" : "sys", "latency" : 1 }, { "mnemonic" : "fadd.s", "dispatch" : ["fpu"], - "pipe" : ["faddsub"], + "pipe" : "faddsub", "latency" : 4 }, { "mnemonic" : "fsub.s", "dispatch" : ["fpu"], - "pipe" : ["faddsub"], + "pipe" : "faddsub", "latency" : 4 }, { "mnemonic" : "fmul.s", "dispatch" : ["fpu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 4 }, { "mnemonic" : "fdiv.s", "dispatch" : ["fpu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 30 }, { "mnemonic" : "fsgnj.s", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fsgnjn.s", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fsgnjx.s", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fmin.s", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fmax.s", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fsqrt.s", "dispatch" : ["fpu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 24 }, { "mnemonic" : "fadd.d", "dispatch" : ["fpu"], - "pipe" : ["faddsub"], + "pipe" : "faddsub", "latency" : 4 }, { "mnemonic" : "fsub.d", "dispatch" : ["fpu"], - "pipe" : ["faddsub"], + "pipe" : "faddsub", "latency" : 4 }, { "mnemonic" : "fmul.d", "dispatch" : ["fpu"], - "pipe" : ["mul"], + "pipe" : "mul", "latency" : 4 }, { "mnemonic" : "fdiv.d", "dispatch" : ["fpu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 63 }, { "mnemonic" : "fsgnj.d", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fsgnjn.d", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fsgnjx.d", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fmin.d", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fmax.d", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fcvt.s.d", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fcvt.d.s", "dispatch" : ["fpu"], - "pipe" : ["float"], + "pipe" : "float", "latency" : 2 }, { "mnemonic" : "fsqrt.d", "dispatch" : ["fpu"], - "pipe" : ["div"], + "pipe" : "div", "latency" : 63 }, { "mnemonic" : "fle.s", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "flt.s", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "feq.s", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fle.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "flt.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "feq.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.w.s", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.wu.s", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.l.s", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.lu.s", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fmv.x.w", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fclass.s", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.w.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.wu.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.l.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.lu.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fmv.x.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fclass.d", "dispatch" : ["fpu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.s.w", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.s.wu", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.s.l", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.s.lu", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fmv.w.x", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.d.w", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.d.wu", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.d.l", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fcvt.d.lu", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 2 }, { "mnemonic" : "fmv.d.x", "dispatch" : ["alu"], - "pipe" : ["i2f"], + "pipe" : "i2f", "transfer" : true, "latency" : 1 }, { "mnemonic" : "flw", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "fld", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "fsw", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "fsd", "dispatch" : ["lsu"], - "pipe" : ["lsu"], + "pipe" : "lsu", "latency" : 1 }, { "mnemonic" : "fmadd.s", "dispatch" : ["fpu"], - "pipe" : ["fmac"], + "pipe" : "fmac", "latency" : 6 }, { "mnemonic" : "fmsub.s", "dispatch" : ["fpu"], - "pipe" : ["fmac"], + "pipe" : "fmac", "latency" : 6 }, { "mnemonic" : "fnmsub.s", "dispatch" : ["fpu"], - "pipe" : ["fmac"], + "pipe" : "fmac", "latency" : 6 }, { "mnemonic" : "fnmadd.s", "dispatch" : ["fpu"], - "pipe" : ["fmac"], + "pipe" : "fmac", "latency" : 6 }, { "mnemonic" : "fmadd.d", "dispatch" : ["fpu"], - "pipe" : ["fmac"], + "pipe" : "fmac", "latency" : 6 }, { "mnemonic" : "fmsub.d", "dispatch" : ["fpu"], - "pipe" : ["fmac"], + "pipe" : "fmac", "latency" : 6 }, { "mnemonic" : "fnmsub.d", "dispatch" : ["fpu"], - "pipe" : ["fmac"], + "pipe" : "fmac", "latency" : 6 }, { "mnemonic" : "fnmadd.d", "dispatch" : ["fpu"], - "pipe" : ["fmac"], + "pipe" : "fmac", "latency" : 6 } ] diff --git a/core/Decode.cpp b/core/Decode.cpp index 6b25f5d2..90e8f751 100644 --- a/core/Decode.cpp +++ b/core/Decode.cpp @@ -82,9 +82,11 @@ namespace olympia sparta::allocate_sparta_shared_pointer(instgroup_allocator); // Send instructions on their way to rename for(uint32_t i = 0; i < num_decode; ++i) { - insts->emplace_back(fetch_queue_.read(0)); + const auto & inst = fetch_queue_.read(0); + insts->emplace_back(inst); + inst->setStatus(Inst::Status::RENAMED); - ILOG("Decoded: " << fetch_queue_.read(0)); + ILOG("Decoded: " << inst); fetch_queue_.pop(); } diff --git a/core/Dispatch.cpp b/core/Dispatch.cpp index 3f81241b..f69a995e 100644 --- a/core/Dispatch.cpp +++ b/core/Dispatch.cpp @@ -186,9 +186,11 @@ namespace olympia ++(unit_distribution_context_.context(target_unit)); ++(weighted_unit_distribution_context_.context(target_unit)); + ex_inst_ptr->setStatus(Inst::Status::DISPATCHED); ILOG("Sending instruction: " << ex_inst_ptr << " to " << disp->getName()); dispatched = true; + break; } else { diff --git a/core/ExecutePipe.cpp b/core/ExecutePipe.cpp index 22e69e85..5560721d 100644 --- a/core/ExecutePipe.cpp +++ b/core/ExecutePipe.cpp @@ -70,7 +70,8 @@ namespace olympia { // FIXME: Now every source operand should be ready const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file_); - if(scoreboard_views_[reg_file_]->isSet(src_bits)){ + if(scoreboard_views_[reg_file_]->isSet(src_bits)) + { // Insert at the end if we are doing in order issue or if the scheduler is empty ILOG("Sending to issue queue" << ex_inst); if (in_order_issue_ == true || ready_queue_.size() == 0) { @@ -101,17 +102,21 @@ namespace olympia } } else{ - scoreboard_views_[reg_file_]->registerReadyCallback(src_bits, ex_inst->getUniqueID(), - [this, ex_inst](const sparta::Scoreboard::RegisterBitMask&) - {this->getInstsFromDispatch_(ex_inst);}); - ILOG("Registering Callback: " << ex_inst); + scoreboard_views_[reg_file_]-> + registerReadyCallback(src_bits, ex_inst->getUniqueID(), + [this, ex_inst](const sparta::Scoreboard::RegisterBitMask&) + { + this->getInstsFromDispatch_(ex_inst); + }); + ILOG("Instruction NOT ready: " << ex_inst << " Bits needed:" << sparta::printBitSet(src_bits)); } } - void ExecutePipe::issueInst_() { + void ExecutePipe::issueInst_() + { // Issue a random instruction from the ready queue sparta_assert_context(unit_busy_ == false && ready_queue_.size() > 0, - "Somehow we're issuing on a busy unit or empty ready_queue"); + "Somehow we're issuing on a busy unit or empty ready_queue"); // Issue the first instruction InstPtr & ex_inst_ptr = ready_queue_.front(); auto & ex_inst = *ex_inst_ptr; @@ -134,18 +139,21 @@ namespace olympia } // Called by the scheduler, scheduled by complete_inst_. - void ExecutePipe::completeInst_(const InstPtr & ex_inst) { - ILOG("Completing inst: " << ex_inst); - + void ExecutePipe::completeInst_(const InstPtr & ex_inst) + { ex_inst->setStatus(Inst::Status::COMPLETED); + ILOG("Completing inst: " << ex_inst); // set scoreboard - const auto & dests = ex_inst->getDestOpInfoList(); - if(dests.size() > 0){ - sparta_assert(dests.size() == 1); // we should only have one destination - core_types::RegFile reg_file_complete = olympia::coreutils::determineRegisterFile(dests[0]); - const auto & dest_bits = ex_inst->getDestRegisterBitMask(reg_file_complete); - scoreboard_views_[reg_file_complete]->setReady(dest_bits); + if(SPARTA_EXPECT_FALSE(ex_inst->getPipe() == InstArchInfo::TargetPipe::I2F)) { + sparta_assert(reg_file_ == core_types::RegFile::RF_INTEGER, + "Got an I2F instruction in an ExecutionPipe that does not source the integer RF"); + const auto & dest_bits = ex_inst->getDestRegisterBitMask(core_types::RegFile::RF_FLOAT); + scoreboard_views_[core_types::RegFile::RF_FLOAT]->setReady(dest_bits); + } + else { + const auto & dest_bits = ex_inst->getDestRegisterBitMask(reg_file_); + scoreboard_views_[reg_file_]->setReady(dest_bits); } // We're not busy anymore @@ -197,4 +205,4 @@ namespace olympia } } -} \ No newline at end of file +} diff --git a/core/Fetch.cpp b/core/Fetch.cpp index 136e9a47..3119f4b9 100644 --- a/core/Fetch.cpp +++ b/core/Fetch.cpp @@ -21,6 +21,7 @@ namespace olympia const FetchParameterSet * p) : sparta::Unit(node), num_insts_to_fetch_(p->num_to_fetch), + skip_nonuser_mode_(p->skip_nonuser_mode), my_clk_(getClock()) { in_fetch_queue_credits_. @@ -43,7 +44,9 @@ namespace olympia auto cpu_node = getContainer()->getParent()->getParent(); auto extension = sparta::notNull(cpu_node->getExtension("simulation_configuration")); auto workload = extension->getParameters()->getParameter("workload"); - inst_generator_ = InstGenerator::createGenerator(getMavis(getContainer()), workload->getValueAsString()); + inst_generator_ = InstGenerator::createGenerator(getMavis(getContainer()), + workload->getValueAsString(), + skip_nonuser_mode_); fetch_inst_event_->schedule(1); } diff --git a/core/Fetch.hpp b/core/Fetch.hpp index 66662e2c..6a34e9ef 100644 --- a/core/Fetch.hpp +++ b/core/Fetch.hpp @@ -53,7 +53,8 @@ namespace olympia "Num to fetch must be greater than 0"); } - PARAMETER(uint32_t, num_to_fetch, 4, "Number of instructions to fetch") + PARAMETER(uint32_t, num_to_fetch, 4, "Number of instructions to fetch") + PARAMETER(bool, skip_nonuser_mode, false, "For STF traces, skip system instructions if present") }; /** @@ -91,6 +92,10 @@ namespace olympia // Number of instructions to fetch const uint32_t num_insts_to_fetch_; + + // For traces with system instructions, skip them + const bool skip_nonuser_mode_; + // Number of credits from decode that fetch has uint32_t credits_inst_queue_ = 0; diff --git a/core/Inst.hpp b/core/Inst.hpp index 9b8dd4af..7e7a4c9c 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -3,7 +3,6 @@ #pragma once #include "sparta/memory/AddressTypes.hpp" -#include "sparta/resources/SharedData.hpp" #include "sparta/resources/Scoreboard.hpp" #include "sparta/resources/Queue.hpp" #include "sparta/pairs/SpartaKeyPairs.hpp" @@ -32,33 +31,31 @@ namespace olympia class Inst { public: - class RenameData{ - public: - // - using SourceReg = std::pair; - - void setDestination(uint32_t destination){ - dest_ = destination; - } - void setOriginalDestination(uint32_t destination){ - original_dest_ = destination; - } - void setSource(uint32_t source){ - src_.push_back(source); - } - const std::vector & getSource() const { - return src_; - } - uint32_t getDestination() const { - return dest_; - } - uint32_t getOriginalDestination() const { - return original_dest_; - } - private: - uint32_t dest_; - uint32_t original_dest_; - std::vector src_; + class RenameData + { + public: + // A register consists of its value and its register file. + struct Reg { + uint32_t val = 0; + core_types::RegFile rf = core_types::RegFile::RF_INVALID; + }; + using RegList = std::vector; + + void setOriginalDestination(const Reg & destination){ + original_dest_ = destination; + } + void setSource(const Reg & source){ + src_.emplace_back(source); + } + const RegList & getSourceList() const { + return src_; + } + const Reg & getOriginalDestination() const { + return original_dest_; + } + private: + Reg original_dest_; + RegList src_; }; // Used by Mavis @@ -74,14 +71,13 @@ namespace olympia __FIRST = FETCHED, DECODED, RENAMED, + DISPATCHED, SCHEDULED, COMPLETED, RETIRED, __LAST }; - using InstStatus = sparta::SharedData; - /*! * \brief Construct an Instruction * \param opcode_info Mavis Opcode information @@ -96,7 +92,6 @@ namespace olympia const sparta::Clock * clk) : opcode_info_ (opcode_info), inst_arch_info_ (inst_arch_info), - status_("inst_status", clk, Status::FETCHED), status_state_(Status::FETCHED) { } @@ -106,7 +101,6 @@ namespace olympia const Status & getStatus() const { return status_state_; - //return status_state_.getEnumValue(); } bool getCompletedStatus() const { @@ -114,10 +108,8 @@ namespace olympia } void setStatus(Status status) { - //status_state_.setValue(status); status_state_ = status; - status_.write(status); - if(getStatus() == olympia::Inst::Status::COMPLETED) { + if(getStatus() == Status::COMPLETED) { if(ev_retire_ != 0) { ev_retire_->schedule(); } @@ -128,15 +120,17 @@ namespace olympia return inst_arch_info_->getTargetUnit(); } + InstArchInfo::TargetPipe getPipe() const { + return inst_arch_info_->getTargetPipe(); + } + void setOldest(bool oldest, sparta::Scheduleable * rob_retire_event) { ev_retire_ = rob_retire_event; is_oldest_ = oldest; - - if(status_.isValidNS() && status_.readNS() == olympia::Inst::Status::COMPLETED) { - ev_retire_->schedule(); - } } + bool isMarkedOldest() const { return is_oldest_; } + // Set the instructions unique ID. This ID in constantly // incremented and does not repeat. The same instruction in a // trace can have different unique IDs (due to flushing) @@ -208,7 +202,6 @@ namespace olympia uint64_t program_id_ = 0; // Supplied by a trace Reader or execution backend bool is_speculative_ = false; // Is this instruction soon to be flushed? sparta::Scheduleable * ev_retire_ = nullptr; - InstStatus status_; Status status_state_; // Rename information @@ -232,6 +225,9 @@ namespace olympia case Inst::Status::RENAMED: os << "RENAMED"; break; + case Inst::Status::DISPATCHED: + os << "DISPATCHED"; + break; case Inst::Status::SCHEDULED: os << "SCHEDULED"; break; @@ -248,8 +244,10 @@ namespace olympia } inline std::ostream & operator<<(std::ostream & os, const Inst & inst) { - os << "uid: " << inst.getUniqueID() << " " << inst.getStatus() << " " - << std::hex << inst.getPC() << std::dec << " '" << inst.getDisasm() << "' "; + os << "uid: " << inst.getUniqueID() + << " " << std::setw(10) << inst.getStatus() + << " " << std::hex << inst.getPC() << std::dec + << " pid: " << inst.getProgramID() << " '" << inst.getDisasm() << "' "; return os; } @@ -289,4 +287,4 @@ namespace olympia extern InstAllocator inst_allocator; extern InstArchInfoAllocator inst_arch_info_allocator; -} \ No newline at end of file +} diff --git a/core/InstArchInfo.cpp b/core/InstArchInfo.cpp index 8cd38d87..9db223b7 100644 --- a/core/InstArchInfo.cpp +++ b/core/InstArchInfo.cpp @@ -15,6 +15,20 @@ namespace olympia {"unknown", InstArchInfo::TargetUnit::UNKNOWN}, }; + const InstArchInfo::TargetPipeMap InstArchInfo::execution_pipe_map = { + {"br", InstArchInfo::TargetPipe::BR}, + {"cmov", InstArchInfo::TargetPipe::CMOV}, + {"div", InstArchInfo::TargetPipe::DIV}, + {"faddsub", InstArchInfo::TargetPipe::FADDSUB}, + {"float", InstArchInfo::TargetPipe::FLOAT}, + {"fmac", InstArchInfo::TargetPipe::FMAC}, + {"i2f", InstArchInfo::TargetPipe::I2F}, + {"int", InstArchInfo::TargetPipe::INT}, + {"lsu", InstArchInfo::TargetPipe::LSU}, + {"mul", InstArchInfo::TargetPipe::MUL}, + {"sys", InstArchInfo::TargetPipe::SYS} + }; + void InstArchInfo::update(const nlohmann::json& jobj) { // Get the dispatch target @@ -31,6 +45,17 @@ namespace olympia sparta_assert(tgt_unit_ != TargetUnit::UNKNOWN, "Unknown target unit (dispatch) for " << jobj["mnemonic"].get()); + if (jobj.find("pipe") != jobj.end()) { + auto pipe_name = jobj["pipe"].get(); + const auto itr = execution_pipe_map.find(pipe_name); + sparta_assert(itr != execution_pipe_map.end(), + "Unknown pipe target: " << pipe_name << " for inst: " << jobj["mnemonic"].get()); + tgt_pipe_ = itr->second; + } + sparta_assert(tgt_pipe_ != TargetPipe::UNKNOWN, + "Unknown target pipe (execution) for " << jobj["mnemonic"].get()); + + if (jobj.find("latency") != jobj.end()) { execute_time_ = jobj["latency"].get(); } diff --git a/core/InstArchInfo.hpp b/core/InstArchInfo.hpp index 7fb28ca0..552454ba 100644 --- a/core/InstArchInfo.hpp +++ b/core/InstArchInfo.hpp @@ -46,9 +46,28 @@ namespace olympia }; static constexpr uint32_t N_TARGET_UNITS = static_cast(TargetUnit::UNKNOWN); + enum class TargetPipe : std::uint16_t{ + BR, + CMOV, + DIV, + FADDSUB, + FLOAT, + FMAC, + I2F, + INT, + LSU, + MUL, + SYS, + UNKNOWN + }; + static constexpr uint32_t N_TARGET_PIPES = static_cast(TargetPipe::UNKNOWN); + using TargetUnitMap = std::map; static const TargetUnitMap dispatch_target_map; + using TargetPipeMap = std::map; + static const TargetPipeMap execution_pipe_map; + // Called by Mavis during its initialization explicit InstArchInfo(const nlohmann::json& jobj) { @@ -62,6 +81,9 @@ namespace olympia //! Return the target unit for this instruction type TargetUnit getTargetUnit() const { return tgt_unit_; } + //! Return the target unit for this instruction type + TargetPipe getTargetPipe() const { return tgt_pipe_; } + //! Return the execution time (latency) of the instruction uint32_t getExecutionTime() const { return execute_time_; } @@ -70,6 +92,7 @@ namespace olympia private: TargetUnit tgt_unit_ = TargetUnit::UNKNOWN; + TargetPipe tgt_pipe_ = TargetPipe::UNKNOWN; uint32_t execute_time_ = 0; bool is_load_store_ = false; }; diff --git a/core/InstGenerator.cpp b/core/InstGenerator.cpp index f24e3da5..096bcd3b 100644 --- a/core/InstGenerator.cpp +++ b/core/InstGenerator.cpp @@ -6,7 +6,8 @@ namespace olympia { std::unique_ptr InstGenerator::createGenerator(MavisType * mavis_facade, - const std::string & filename) + const std::string & filename, + const bool skip_nonuser_mode) { const std::string json_ext = "json"; if((filename.size() > json_ext.size()) && filename.substr(filename.size()-json_ext.size()) == json_ext) { @@ -17,7 +18,7 @@ namespace olympia const std::string stf_ext = "stf"; // Should cover both zstf and stf if((filename.size() > stf_ext.size()) && filename.substr(filename.size()-stf_ext.size()) == stf_ext) { std::cout << "olympia: STF file input detected" << std::endl; - return std::unique_ptr(new TraceInstGenerator(mavis_facade, filename)); + return std::unique_ptr(new TraceInstGenerator(mavis_facade, filename, skip_nonuser_mode)); } // Dunno what it is... @@ -114,7 +115,8 @@ namespace olympia //////////////////////////////////////////////////////////////////////////////// // STF Inst Generator TraceInstGenerator::TraceInstGenerator(MavisType * mavis_facade, - const std::string & filename) : + const std::string & filename, + const bool skip_nonuser_mode) : InstGenerator(mavis_facade) { std::ifstream fs; @@ -134,10 +136,9 @@ namespace olympia // value. Required for traces that stay in machine mode the entire // time constexpr bool FILTER_MODE_CHANGE_EVENTS = true; - constexpr bool SKIP_NONUSER_MODE = false; constexpr size_t BUFFER_SIZE = 4096; reader_.reset(new stf::STFInstReader(filename, - SKIP_NONUSER_MODE, + skip_nonuser_mode, CHECK_FOR_STF_PTE, FILTER_MODE_CHANGE_EVENTS, BUFFER_SIZE)); @@ -180,7 +181,8 @@ namespace olympia catch(std::exception & excpt) { std::cerr << "ERROR: Mavis failed decoding: 0x" << std::hex << opcode << " for STF It PC: 0x" - << next_it_->pc() << " STFID: " << next_it_->index() << ": err: " + << next_it_->pc() << " STFID: " << std::dec + << next_it_->index() << " err: " << excpt.what() << std::endl; throw; } diff --git a/core/InstGenerator.hpp b/core/InstGenerator.hpp index 9141b27f..e6988fe7 100644 --- a/core/InstGenerator.hpp +++ b/core/InstGenerator.hpp @@ -37,7 +37,8 @@ namespace olympia virtual ~InstGenerator() {} virtual InstPtr getNextInst(const sparta::Clock * clk) = 0; static std::unique_ptr createGenerator(MavisType * mavis_facade, - const std::string & filename); + const std::string & filename, + const bool skip_nonuser_mode); virtual bool isDone() const = 0; protected: @@ -64,8 +65,12 @@ namespace olympia class TraceInstGenerator : public InstGenerator { public: + // Creates a TraceInstGenerator with the given mavis facade + // and filename. The parameter skip_nonuser_mode allows the + // trace generator to skip system instructions if present TraceInstGenerator(MavisType * mavis_facade, - const std::string &); + const std::string & filename, + const bool skip_nonuser_mode); InstPtr getNextInst(const sparta::Clock * clk) override final; diff --git a/core/LSU.cpp b/core/LSU.cpp index be3ed6d7..c9b1013e 100644 --- a/core/LSU.cpp +++ b/core/LSU.cpp @@ -48,8 +48,17 @@ namespace olympia (CREATE_SPARTA_HANDLER_WITH_DATA(LSU, handleFlush_, FlushManager::FlushingCriteria)); - // Pipeline events config + // Allow the pipeline to create events and schedule work ldst_pipeline_.performOwnUpdates(); + + // There can be situations where NOTHING is going on in the + // simulator but forward progression of the pipeline elements. + // In this case, the internal event for the LS pipeline will + // be the only event keeping simulation alive. Sparta + // supports identifying non-essential events (by calling + // setContinuing to false on any event). + ldst_pipeline_.setContinuing(true); + ldst_pipeline_.registerHandlerAtStage(static_cast(PipelineStage::MMU_LOOKUP), CREATE_SPARTA_HANDLER(LSU, handleMMULookupReq_)); @@ -101,7 +110,7 @@ namespace olympia // Receive new load/store instruction from Dispatch Unit void LSU::getInstsFromDispatch_(const InstPtr & inst_ptr) - { + { core_types::RegFile reg_file = core_types::RF_INTEGER; const auto & srcs = inst_ptr->getSourceOpInfoList(); if(srcs.size() > 0){ @@ -117,7 +126,7 @@ namespace olympia LoadStoreInstInfoPtr inst_info_ptr = sparta::allocate_sparta_shared_pointer(load_store_info_allocator, mem_info_ptr); lsu_insts_dispatched_++; - + // Append to instruction issue queue appendIssueQueue_(inst_info_ptr); @@ -219,6 +228,8 @@ namespace olympia const MemoryAccessInfoPtr & mem_access_info_ptr = ldst_pipeline_[stage_id]; + ILOG(mem_access_info_ptr); + bool isAlreadyHIT = (mem_access_info_ptr->getMMUState() == MemoryAccessInfo::MMUState::HIT); bool MMUBypass = isAlreadyHIT; @@ -312,6 +323,8 @@ namespace olympia const MemoryAccessInfoPtr & mem_access_info_ptr = ldst_pipeline_[stage_id]; const InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr(); + ILOG(mem_access_info_ptr); + const bool phyAddrIsReady = mem_access_info_ptr->getPhyAddrStatus(); const bool isAlreadyHIT = @@ -389,7 +402,7 @@ namespace olympia out_biu_req_.send(cache_pending_inst_ptr_); succeed = true; - + biu_reqs_++; } else { @@ -420,6 +433,8 @@ namespace olympia const InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr(); bool isStoreInst = inst_ptr->isStoreInst(); + ILOG(mem_access_info_ptr); + core_types::RegFile reg_file = core_types::RF_INTEGER; const auto & dests = inst_ptr->getDestOpInfoList(); if(dests.size() > 0){ @@ -436,7 +451,7 @@ namespace olympia // Update instruction status inst_ptr->setStatus(Inst::Status::COMPLETED); - + lsu_insts_completed_++; // Remove completed instruction from issue queue @@ -597,24 +612,17 @@ namespace olympia // Check for ready to issue instructions bool LSU::isReadyToIssueInsts_() const { - bool isReady = false; - // Check if there is at least one ready-to-issue instruction in issue queue for (auto const &inst_info_ptr : ldst_inst_queue_) { if (inst_info_ptr->isReady()) { - isReady = true; - break; + ILOG("At least one instruction is ready to be issued: " << inst_info_ptr); + return true; } } - if (isReady) { - ILOG("At least one more instruction is ready to be issued!"); - } - else { - ILOG("No more instruction is ready to be issued!"); - } + ILOG("No instructions are ready to be issued"); - return isReady; + return false; } @@ -951,4 +959,4 @@ namespace olympia } } -} // namespace olympia \ No newline at end of file +} // namespace olympia diff --git a/core/LSU.hpp b/core/LSU.hpp index ef4752b9..0b768ab3 100644 --- a/core/LSU.hpp +++ b/core/LSU.hpp @@ -157,18 +157,18 @@ namespace olympia bool getPhyAddrStatus() const { return phyAddrIsReady_; } const MMUState & getMMUState() const { - return mmu_access_state_.getEnumValue(); + return mmu_access_state_; } void setMMUState(const MMUState & state) { - mmu_access_state_.setValue(state); + mmu_access_state_ = state; } const CacheState & getCacheState() const { - return cache_access_state_.getEnumValue(); + return cache_access_state_; } void setCacheState(const CacheState & state) { - cache_access_state_.setValue(state); + cache_access_state_ = state; } // This is a function which will be added in the addArgs API. @@ -185,10 +185,10 @@ namespace olympia bool phyAddrIsReady_; // MMU access status - sparta::State mmu_access_state_; + MMUState mmu_access_state_; // Cache access status - sparta::State cache_access_state_; + CacheState cache_access_state_; // Scoreboards using ScoreboardViews = std::array, core_types::N_REGFILES>; @@ -274,7 +274,6 @@ namespace olympia // This is a function which will be added in the SPARTA_ADDPAIRs API. uint64_t getInstUniqueID() const { const MemoryAccessInfoPtr &mem_access_info_ptr = getMemoryAccessInfoPtr(); - return mem_access_info_ptr == nullptr ? 0 : mem_access_info_ptr->getInstUniqueID(); } @@ -448,7 +447,7 @@ namespace olympia // Setup Scoreboard Views void setupScoreboard_(); - + // Receive new load/store Instruction from Dispatch Unit void getInstsFromDispatch_(const InstPtr &); @@ -666,5 +665,39 @@ namespace olympia } return os; } + + + inline std::ostream & operator<<(std::ostream & os, + const olympia::LSU::LoadStoreInstInfo & ls_info) + { + os << "lsinfo: " + << "uid: " << ls_info.getInstUniqueID() + << " pri:" << ls_info.getPriority() + << " state: " << ls_info.getState(); + return os; + } + + inline std::ostream & operator<<(std::ostream & os, + const olympia::LSU::LoadStoreInstInfoPtr & ls_info) + { + os << *ls_info; + return os; + } + + inline std::ostream & operator<<(std::ostream & os, + const olympia::LSU::MemoryAccessInfo & mem) + { + os << "memptr: " << mem.getInstPtr(); + return os; + } + + inline std::ostream & operator<<(std::ostream & os, + const olympia::LSU::MemoryAccessInfoPtr & mem_ptr) + { + os << *mem_ptr; + return os; + } + + class LSUTester; } // namespace olympia diff --git a/core/ROB.cpp b/core/ROB.cpp index 5942f5d7..16dcf3d0 100644 --- a/core/ROB.cpp +++ b/core/ROB.cpp @@ -71,9 +71,6 @@ namespace olympia void ROB::retireEvent_() { retireInstructions_(); - if (reorder_buffer_.size() > 0) { - ev_retire_.schedule(sparta::Clock::Cycle(1)); - } } // An illustration of the use of the callback -- instead of @@ -135,6 +132,7 @@ namespace olympia } // Will be true if the user provides a -i option if (SPARTA_EXPECT_FALSE((num_retired_ == num_insts_to_retire_))) { + rob_stopped_simulation_ = true; getScheduler()->stopRunning(); break; } @@ -155,17 +153,36 @@ namespace olympia } else { - ILOG("set oldest: " << ex_inst); - ex_inst.setOldest(true, &ev_retire_); break; } } + + if(false == reorder_buffer_.empty()) { + const auto & oldest_inst = reorder_buffer_.front(); + if(oldest_inst->getStatus() == Inst::Status::COMPLETED) { + ILOG("oldest is marked completed: " << oldest_inst); + ev_retire_.schedule(); + } + else if(false == oldest_inst->isMarkedOldest()) { + ILOG("set oldest: " << oldest_inst); + oldest_inst->setOldest(true, &ev_retire_); + } + } + if(retired_this_cycle != 0) { out_reorder_buffer_credits_.send(retired_this_cycle); last_retirement_ = getClock()->currentCycle(); } } + void ROB::dumpDebugContent_(std::ostream& output) const + { + output << "ROB Contents" << std::endl; + for(const auto & entry : reorder_buffer_) { + output << '\t' << entry << std::endl; + } + } + // Make sure the pipeline is making forward progress void ROB::checkForwardProgress_() { @@ -173,9 +190,17 @@ namespace olympia { sparta::SpartaException e; e << "Been a while since we've retired an instruction. Is the pipe stalled indefinitely?"; + e << " currentCycle: " << getClock()->currentCycle(); throw e; } ev_ensure_forward_progress_.schedule(retire_timeout_interval_); } + void ROB::onStartingTeardown_() { + if ((reorder_buffer_.size() > 0) && (false == rob_stopped_simulation_)) { + std::cerr << "WARNING! Simulation is ending, but the ROB didn't stop it. Lock up situation?" << std::endl; + dumpDebugContent_(std::cerr); + } + } + } diff --git a/core/ROB.hpp b/core/ROB.hpp index fd263dcd..f6a828cc 100644 --- a/core/ROB.hpp +++ b/core/ROB.hpp @@ -86,6 +86,11 @@ namespace olympia InstQueue reorder_buffer_; + // Bool that indicates if the ROB stopped simulation. If + // false and there are still instructions in the reorder + // buffer, the machine probably has a lock up + bool rob_stopped_simulation_{false}; + // Ports used by the ROB sparta::DataInPort in_reorder_buffer_write_{&unit_port_set_, "in_reorder_buffer_write", 1}; sparta::DataOutPort out_reorder_buffer_credits_{&unit_port_set_, "out_reorder_buffer_credits"}; @@ -117,6 +122,8 @@ namespace olympia void retireInstructions_(); void checkForwardProgress_(); void handleFlush_(const FlushManager::FlushingCriteria & criteria); + void dumpDebugContent_(std::ostream& output) const override final; + void onStartingTeardown_() override final; }; } diff --git a/core/Rename.cpp b/core/Rename.cpp index 6f089127..b3b2d630 100644 --- a/core/Rename.cpp +++ b/core/Rename.cpp @@ -22,7 +22,7 @@ namespace olympia uop_queue_("rename_uop_queue", p->rename_queue_depth, node->getClock(), getStatisticSet()), num_to_rename_per_cycle_(p->num_to_rename), - rename_histogram_(*getStatisticSet(), "rename_histogram", "Rename Stage Histogram", + rename_histogram_(*getStatisticSet(), "rename_histogram", "Rename Stage Histogram", [&p]() { std::vector v(p->num_to_rename+1); std::iota(v.begin(), v.end(), 0); return v; }()) { uop_queue_.enableCollection(node); @@ -57,7 +57,7 @@ namespace olympia setup_map(core_types::RegFile::RF_INTEGER, p->num_integer_renames); setup_map(core_types::RegFile::RF_FLOAT, p->num_float_renames); - + static_assert(core_types::RegFile::N_REGFILES == 2, "New RF type added, but Rename not updated"); } @@ -118,39 +118,40 @@ namespace olympia { sparta_assert(inst_ptr->getStatus() == Inst::Status::RETIRED, "Get ROB Ack, but the inst hasn't retired yet!"); - core_types::RegFile rf = core_types::RegFile::RF_INTEGER; auto const & dests = inst_ptr->getDestOpInfoList(); - auto const & original_dest = inst_ptr->getRenameData().getOriginalDestination(); - if(dests.size() > 0){ + if(dests.size() > 0) + { sparta_assert(dests.size() == 1); // we should only have one destination - rf = olympia::coreutils::determineRegisterFile(dests[0]); - --reference_counter_[rf][original_dest]; + auto const & original_dest = inst_ptr->getRenameData().getOriginalDestination(); + --reference_counter_[original_dest.rf][original_dest.val]; // free previous PRF mapping if no references from srcs, there should be a new dest mapping for the ARF -> PRF // so we know it's free to be pushed to freelist if it has no other src references - if(reference_counter_[rf][original_dest] <= 0){ - freelist_[rf].push(original_dest); + if(reference_counter_[original_dest.rf][original_dest.val] <= 0){ + freelist_[original_dest.rf].push(original_dest.val); } } - const auto & srcs = inst_ptr->getRenameData().getSource(); + const auto & srcs = inst_ptr->getRenameData().getSourceList(); // freeing references to PRF - for(auto src: srcs){ - --reference_counter_[rf][src]; - if(reference_counter_[rf][src] <= 0){ + for(const auto & src: srcs) + { + --reference_counter_[src.rf][src.val]; + if(reference_counter_[src.rf][src.val] <= 0) + { // freeing a register in the case where it still has references and has already been retired // we wait until the last reference is retired to then free the prf // any "valid" PRF that is the true mapping of an ARF will have a reference_counter of at least 1, // and thus shouldn't be retired - freelist_[rf].push(src); + freelist_[src.rf].push(src.val); } } if(credits_dispatch_ > 0 && (uop_queue_.size() > 0)){ ev_schedule_rename_.schedule(); } - ILOG("Get Ack from ROB in Rename Stage! Retired instruction: " << inst_ptr); + ILOG("Retired instruction: " << inst_ptr); } - + // Handle incoming flush void Rename::handleFlush_(const FlushManager::FlushingCriteria & criteria) { @@ -167,13 +168,13 @@ namespace olympia if(!uop_queue_regcount_data_.empty()){ // if we have entries, use the most recent entered instruction counts current_counts = uop_queue_regcount_data_.back(); - } + } for(auto & i : *insts) { // create an index count for each instruction entered const auto & dests = i->getDestOpInfoList(); if(dests.size() > 0){ sparta_assert(dests.size() == 1); // we should only have one destination - const auto rf = olympia::coreutils::determineRegisterFile(dests[0]); + const auto rf = olympia::coreutils::determineRegisterFile(dests[0]); current_counts.cumulative_reg_counts[rf]++; } else{ @@ -192,21 +193,26 @@ namespace olympia ev_schedule_rename_.schedule(); } } - void Rename::scheduleRenaming_(){ + void Rename::scheduleRenaming_() + { + current_stall_ = StallReason::NOT_STALLED; + // If we have credits from dispatch, schedule a rename session this cycle uint32_t num_rename = std::min(uop_queue_.size(), num_to_rename_per_cycle_); num_rename = std::min(credits_dispatch_, num_rename); - if(credits_dispatch_ > 0){ + if(credits_dispatch_ > 0) + { RegCountData count_subtract; bool enough_rename = false; - for(u_int32_t i = num_rename; i > 0 ; --i){ + for(uint32_t i = num_rename; i > 0 ; --i) + { if(enough_rename){ // once we know the number we can rename // pop everything below it uop_queue_regcount_data_.pop_front(); } else{ - int enough_freelists = 0; + uint32_t enough_freelists = 0; for(int j = 0; j < core_types::RegFile::N_REGFILES; ++j){ if(uop_queue_regcount_data_[i-1].cumulative_reg_counts[j] <= freelist_[j].size()){ enough_freelists++; @@ -220,23 +226,30 @@ namespace olympia } } // decrement the rest of the entries in the uop_queue_reg_count_data_ accordingly - if(enough_rename){ + if(enough_rename) + { count_subtract = uop_queue_regcount_data_.front(); uop_queue_regcount_data_.pop_front(); - for(unsigned int i = 0; i < uop_queue_regcount_data_.size(); ++i){ - for(int j = 0; j < core_types::RegFile::N_REGFILES; ++j){ - uop_queue_regcount_data_[i].cumulative_reg_counts[j] -= count_subtract.cumulative_reg_counts[j]; + for(uint32_t i = 0; i < uop_queue_regcount_data_.size(); ++i){ + for(uint32_t j = 0; j < core_types::RegFile::N_REGFILES; ++j) + { + uop_queue_regcount_data_[i].cumulative_reg_counts[j] -= + count_subtract.cumulative_reg_counts[j]; } } ev_rename_insts_.schedule(); } else{ + current_stall_ = StallReason::NO_RENAMES; num_to_rename_ = 0; } } else{ + current_stall_ = StallReason::NO_DISPATCH_CREDITS; num_to_rename_ = 0; } + ILOG("current stall: " << current_stall_); + rename_histogram_.addValue((int) num_to_rename_); } void Rename::renameInstructions_() @@ -250,6 +263,7 @@ namespace olympia { // Pick the oldest const auto & renaming_inst = uop_queue_.read(0); + renaming_inst->setStatus(Inst::Status::RENAMED); ILOG("sending inst to dispatch: " << renaming_inst); // TODO: Register renaming for sources @@ -259,13 +273,13 @@ namespace olympia const auto rf = olympia::coreutils::determineRegisterFile(src); const auto num = src.field_value; auto & bitmask = renaming_inst->getSrcRegisterBitMask(rf); - uint32_t prf = map_table_[rf][num]; + const uint32_t prf = map_table_[rf][num]; reference_counter_[rf][prf]++; - renaming_inst->getRenameData().setSource(prf); + renaming_inst->getRenameData().setSource({prf, rf}); bitmask.set(prf); ILOG("\tsetup source register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << rf << "' scoreboard"); + << sparta::printBitSet(bitmask) + << " for '" << rf << "' scoreboard"); } // TODO: Register renaming for destinations @@ -276,9 +290,9 @@ namespace olympia const auto num = dest.field_value; auto & bitmask = renaming_inst->getDestRegisterBitMask(rf); - uint32_t prf = freelist_[rf].front(); + const uint32_t prf = freelist_[rf].front(); freelist_[rf].pop(); - renaming_inst->getRenameData().setOriginalDestination(map_table_[rf][num]); + renaming_inst->getRenameData().setOriginalDestination({map_table_[rf][num], rf}); map_table_[rf][num] = prf; // we increase reference_counter_ for destinations to mark them as "valid", // so the PRF in the reference_counter_ should have a value of 1 @@ -286,22 +300,21 @@ namespace olympia // PRF for that ARF anymore and there are no sources referring to it // so we can push it to freelist reference_counter_[rf][prf]++; - renaming_inst->getRenameData().setDestination(prf); bitmask.set(prf); ILOG("\tsetup destination register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << rf << "' scoreboard"); + << sparta::printBitSet(bitmask) + << " for '" << rf << "' scoreboard"); } // Remove it from uop queue insts->emplace_back(uop_queue_.read(0)); uop_queue_.pop(); - } + } // Send insts to dispatch out_dispatch_queue_write_.send(insts); credits_dispatch_ -= num_to_rename_; - // Replenish credits in the Decode unit + // Replenish credits in the Decode unit out_uop_queue_credits_.send(num_to_rename_); num_to_rename_ = 0; } @@ -310,4 +323,4 @@ namespace olympia } } -} \ No newline at end of file +} diff --git a/core/Rename.hpp b/core/Rename.hpp index 78929256..3cba78bc 100644 --- a/core/Rename.hpp +++ b/core/Rename.hpp @@ -90,8 +90,8 @@ namespace olympia // histogram counter for number of renames each time scheduleRenaming_ is called sparta::BasicHistogram rename_histogram_; // map of ARF -> PRF - uint32_t map_table_[core_types::N_REGFILES][32]; - + uint32_t map_table_[core_types::N_REGFILES][32]; + // reference counter for PRF std::array, core_types::N_REGFILES> reference_counter_; // list of free PRF that are available to map @@ -103,6 +103,39 @@ namespace olympia }; std::deque uop_queue_regcount_data_; + + /////////////////////////////////////////////////////////////////////// + // Stall counters + enum StallReason { + NO_DECODE_INSTS, // No insts from Decode + NO_DISPATCH_CREDITS, // No credits from Dispatch + NO_RENAMES, // Out of renames + NOT_STALLED, // Made forward progress (dipatched + // all instructions or no + // instructions) + N_STALL_REASONS + }; + + StallReason current_stall_ = NO_DECODE_INSTS; + friend std::ostream&operator<<(std::ostream &, const StallReason &); + + // Counters -- this is only supported in C++11 -- uses + // Counter's move semantics + std::array stall_counters_{{ + sparta::CycleCounter(getStatisticSet(), "stall_no_decode_insts", + "No Decode Insts", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_no_dispatch_credits", + "No Dispatch Credits", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_no_renames", + "No Renames", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", + "Rename not stalled, all instructions renamed", + sparta::Counter::COUNT_NORMAL, getClock()) + }}; + //! Rename setup void setupRename_(); @@ -129,6 +162,28 @@ namespace olympia }; + inline std::ostream&operator<<(std::ostream &os, const Rename::StallReason & stall) + { + switch(stall) + { + case Rename::StallReason::NO_DECODE_INSTS: + os << "NO_DECODE_INSTS"; + break; + case Rename::StallReason::NO_DISPATCH_CREDITS: + os << "NO_DISPATCH_CREDITS"; + break; + case Rename::StallReason::NO_RENAMES: + os << "NO_RENAMES"; + break; + case Rename::StallReason::NOT_STALLED: + os << "NOT_STALLED"; + break; + case Rename::StallReason::N_STALL_REASONS: + sparta_assert(false, "How'd we get here?"); + } + return os; + } + //! Rename's factory class. Don't create Rename without it class RenameFactory : public sparta::ResourceFactory { @@ -144,4 +199,4 @@ namespace olympia ScoreboardTreeNodes sb_tns_; }; class RenameTester; -} \ No newline at end of file +} diff --git a/test/core/common/SourceUnit.hpp b/test/core/common/SourceUnit.hpp index 983f966f..c77ccaaa 100644 --- a/test/core/common/SourceUnit.hpp +++ b/test/core/common/SourceUnit.hpp @@ -49,7 +49,7 @@ namespace core_test registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(SourceUnit, inCredits<0>, uint32_t)); if(params->input_file != "") { - inst_generator_ = olympia::InstGenerator::createGenerator(mavis_facade_, params->input_file); + inst_generator_ = olympia::InstGenerator::createGenerator(mavis_facade_, params->input_file, false); } } diff --git a/test/core/dispatch/expected_output/big_core.out.EXPECTED b/test/core/dispatch/expected_output/big_core.out.EXPECTED index af628940..94f35d1c 100644 --- a/test/core/dispatch/expected_output/big_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Sunday Sun Nov 27 12:06:57 2022 -#Elapsed: 0.002185s +#Start: Thursday Thu Jun 29 15:34:40 2023 +#Elapsed: 0.00178s {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: alu0 got 10 credits, total: 10 @@ -73,84 +73,84 @@ {0000000000 00000000 top.source_unit info} Sending group: 0x00000000 UID(0) PID(0) add {0000000001 00000001 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add {0000000001 00000001 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000001 00000001 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 'add 3,1,2' -{0000000001 00000001 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 FETCHED 0 'add 3,1,2' to alu0 +{0000000001 00000001 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 pid: 0 'add 3,1,2' +{0000000001 00000001 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000001 00000001 top.source_unit info} inCredits: Got credits from dut: 1 {0000000001 00000001 top.source_unit info} Sending group: 0x00000000 UID(1) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(0) add -{0000000002 00000002 top.alu0 info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked +{0000000002 00000002 top.alu0 info} sinkInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 FETCHED 0 'add 3,1,2' to alu0 +{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 pid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000002 00000002 top.source_unit info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.source_unit info} Sending group: 0x00000000 UID(2) PID(0) add {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(0) add -{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 1 FETCHED 0 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000003 00000003 top.dispatch info} receiveCredits_: alu0 got 2 credits, total: 10 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 'add 3,1,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 FETCHED 0 'add 3,1,2' to alu0 +{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 pid: 0 'add 3,1,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000003 00000003 top.source_unit info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.source_unit info} Sending group: 0x00000000 UID(3) PID(0) add {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(3) PID(0) add -{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 2 FETCHED 0 'add 3,1,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000004 00000004 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 'add 3,1,2' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 FETCHED 0 'add 3,1,2' to alu0 +{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 pid: 0 'add 3,1,2' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000004 00000004 top.source_unit info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.source_unit info} Sending group: 0x00000000 UID(4) PID(0) add {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add -{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 3 FETCHED 0 'add 3,1,2' ' sinked +{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000005 00000005 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 'add 3,1,2' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 FETCHED 0 'add 3,1,2' to alu0 +{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 pid: 0 'add 3,1,2' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000005 00000005 top.source_unit info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.source_unit info} Sending group: 0x00000000 UID(5) PID(0) add {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(5) PID(0) add -{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 4 FETCHED 0 'add 3,1,2' ' sinked +{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000006 00000006 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 5 FETCHED 0 'add 3,1,2' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 FETCHED 0 'add 3,1,2' to alu0 +{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 5 FETCHED 0 pid: 0 'add 3,1,2' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000006 00000006 top.source_unit info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.source_unit info} Sending group: 0x00000000 UID(6) PID(0) add {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(6) PID(0) add -{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 5 FETCHED 0 'add 3,1,2' ' sinked +{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000007 00000007 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000007 00000007 top.dispatch info} acceptInst: alu0: dispatching uid: 6 FETCHED 0 'add 3,1,2' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 FETCHED 0 'add 3,1,2' to alu0 +{0000000007 00000007 top.dispatch info} acceptInst: alu0: dispatching uid: 6 FETCHED 0 pid: 0 'add 3,1,2' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000007 00000007 top.source_unit info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.source_unit info} Sending group: 0x00000000 UID(7) PID(0) add {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(7) PID(0) add -{0000000008 00000008 top.alu0 info} sinkInst_: Instruction: 'uid: 6 FETCHED 0 'add 3,1,2' ' sinked +{0000000008 00000008 top.alu0 info} sinkInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000008 00000008 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000008 00000008 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 'add 3,1,2' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 FETCHED 0 'add 3,1,2' to alu0 +{0000000008 00000008 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 pid: 0 'add 3,1,2' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000008 00000008 top.source_unit info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.source_unit info} Sending group: 0x00000000 UID(8) PID(0) add {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add -{0000000009 00000009 top.alu0 info} sinkInst_: Instruction: 'uid: 7 FETCHED 0 'add 3,1,2' ' sinked +{0000000009 00000009 top.alu0 info} sinkInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000009 00000009 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 8 FETCHED 0 'add 3,1,2' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 FETCHED 0 'add 3,1,2' to alu0 +{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 8 FETCHED 0 pid: 0 'add 3,1,2' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000009 00000009 top.source_unit info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.source_unit info} Sending group: 0x00000000 UID(9) PID(0) add {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(9) PID(0) add -{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 8 FETCHED 0 'add 3,1,2' ' sinked +{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000010 00000010 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000010 00000010 top.dispatch info} acceptInst: alu0: dispatching uid: 9 FETCHED 0 'add 3,1,2' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 FETCHED 0 'add 3,1,2' to alu0 +{0000000010 00000010 top.dispatch info} acceptInst: alu0: dispatching uid: 9 FETCHED 0 pid: 0 'add 3,1,2' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000010 00000010 top.source_unit info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.source_unit info} Sending group: 0x00000000 UID(10) PID(0) add {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(10) PID(0) add {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000011 00000011 top.alu0 info} sinkInst_: Instruction: 'uid: 9 FETCHED 0 'add 3,1,2' ' sinked +{0000000011 00000011 top.alu0 info} sinkInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000011 00000011 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000012 00000012 top.dispatch info} receiveCredits_: alu0 got 0 credits, total: 10 diff --git a/test/core/dispatch/expected_output/medium_core.out.EXPECTED b/test/core/dispatch/expected_output/medium_core.out.EXPECTED index 13030a31..67ea2a94 100644 --- a/test/core/dispatch/expected_output/medium_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Sunday Sun Nov 27 12:06:57 2022 -#Elapsed: 0.004451s +#Start: Thursday Thu Jun 29 15:34:54 2023 +#Elapsed: 0.001519s {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: alu0 got 10 credits, total: 10 @@ -25,84 +25,84 @@ {0000000000 00000000 top.source_unit info} Sending group: 0x00000000 UID(0) PID(0) add {0000000001 00000001 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add {0000000001 00000001 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000001 00000001 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 'add 3,1,2' -{0000000001 00000001 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 FETCHED 0 'add 3,1,2' to alu0 +{0000000001 00000001 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 pid: 0 'add 3,1,2' +{0000000001 00000001 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000001 00000001 top.source_unit info} inCredits: Got credits from dut: 1 {0000000001 00000001 top.source_unit info} Sending group: 0x00000000 UID(1) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(0) add -{0000000002 00000002 top.alu0 info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked +{0000000002 00000002 top.alu0 info} sinkInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 FETCHED 0 'add 3,1,2' to alu0 +{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 pid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000002 00000002 top.source_unit info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.source_unit info} Sending group: 0x00000000 UID(2) PID(0) add {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(0) add -{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 1 FETCHED 0 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000003 00000003 top.dispatch info} receiveCredits_: alu0 got 2 credits, total: 10 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 'add 3,1,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 FETCHED 0 'add 3,1,2' to alu0 +{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 pid: 0 'add 3,1,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000003 00000003 top.source_unit info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.source_unit info} Sending group: 0x00000000 UID(3) PID(0) add {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(3) PID(0) add -{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 2 FETCHED 0 'add 3,1,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000004 00000004 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 'add 3,1,2' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 FETCHED 0 'add 3,1,2' to alu0 +{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 pid: 0 'add 3,1,2' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000004 00000004 top.source_unit info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.source_unit info} Sending group: 0x00000000 UID(4) PID(0) add {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add -{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 3 FETCHED 0 'add 3,1,2' ' sinked +{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000005 00000005 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 'add 3,1,2' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 FETCHED 0 'add 3,1,2' to alu0 +{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 pid: 0 'add 3,1,2' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000005 00000005 top.source_unit info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.source_unit info} Sending group: 0x00000000 UID(5) PID(0) add {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(5) PID(0) add -{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 4 FETCHED 0 'add 3,1,2' ' sinked +{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000006 00000006 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 5 FETCHED 0 'add 3,1,2' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 FETCHED 0 'add 3,1,2' to alu0 +{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 5 FETCHED 0 pid: 0 'add 3,1,2' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000006 00000006 top.source_unit info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.source_unit info} Sending group: 0x00000000 UID(6) PID(0) add {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(6) PID(0) add -{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 5 FETCHED 0 'add 3,1,2' ' sinked +{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000007 00000007 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000007 00000007 top.dispatch info} acceptInst: alu0: dispatching uid: 6 FETCHED 0 'add 3,1,2' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 FETCHED 0 'add 3,1,2' to alu0 +{0000000007 00000007 top.dispatch info} acceptInst: alu0: dispatching uid: 6 FETCHED 0 pid: 0 'add 3,1,2' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000007 00000007 top.source_unit info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.source_unit info} Sending group: 0x00000000 UID(7) PID(0) add {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(7) PID(0) add -{0000000008 00000008 top.alu0 info} sinkInst_: Instruction: 'uid: 6 FETCHED 0 'add 3,1,2' ' sinked +{0000000008 00000008 top.alu0 info} sinkInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000008 00000008 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000008 00000008 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 'add 3,1,2' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 FETCHED 0 'add 3,1,2' to alu0 +{0000000008 00000008 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 pid: 0 'add 3,1,2' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000008 00000008 top.source_unit info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.source_unit info} Sending group: 0x00000000 UID(8) PID(0) add {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add -{0000000009 00000009 top.alu0 info} sinkInst_: Instruction: 'uid: 7 FETCHED 0 'add 3,1,2' ' sinked +{0000000009 00000009 top.alu0 info} sinkInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000009 00000009 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 8 FETCHED 0 'add 3,1,2' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 FETCHED 0 'add 3,1,2' to alu0 +{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 8 FETCHED 0 pid: 0 'add 3,1,2' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000009 00000009 top.source_unit info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.source_unit info} Sending group: 0x00000000 UID(9) PID(0) add {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(9) PID(0) add -{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 8 FETCHED 0 'add 3,1,2' ' sinked +{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000010 00000010 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000010 00000010 top.dispatch info} acceptInst: alu0: dispatching uid: 9 FETCHED 0 'add 3,1,2' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 FETCHED 0 'add 3,1,2' to alu0 +{0000000010 00000010 top.dispatch info} acceptInst: alu0: dispatching uid: 9 FETCHED 0 pid: 0 'add 3,1,2' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000010 00000010 top.source_unit info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.source_unit info} Sending group: 0x00000000 UID(10) PID(0) add {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(10) PID(0) add {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000011 00000011 top.alu0 info} sinkInst_: Instruction: 'uid: 9 FETCHED 0 'add 3,1,2' ' sinked +{0000000011 00000011 top.alu0 info} sinkInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000011 00000011 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000012 00000012 top.dispatch info} receiveCredits_: alu0 got 0 credits, total: 10 diff --git a/test/core/dispatch/expected_output/small_core.out.EXPECTED b/test/core/dispatch/expected_output/small_core.out.EXPECTED index 1f36406c..50ef93ea 100644 --- a/test/core/dispatch/expected_output/small_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Sunday Sun Nov 27 12:06:57 2022 -#Elapsed: 0.005484s +#Start: Thursday Thu Jun 29 15:35:07 2023 +#Elapsed: 0.001755s {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: alu0 got 10 credits, total: 10 @@ -19,84 +19,84 @@ {0000000000 00000000 top.source_unit info} Sending group: 0x00000000 UID(0) PID(0) add {0000000001 00000001 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add {0000000001 00000001 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000001 00000001 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 'add 3,1,2' -{0000000001 00000001 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 FETCHED 0 'add 3,1,2' to alu0 +{0000000001 00000001 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 pid: 0 'add 3,1,2' +{0000000001 00000001 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000001 00000001 top.source_unit info} inCredits: Got credits from dut: 1 {0000000001 00000001 top.source_unit info} Sending group: 0x00000000 UID(1) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(0) add -{0000000002 00000002 top.alu0 info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked +{0000000002 00000002 top.alu0 info} sinkInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 FETCHED 0 'add 3,1,2' to alu0 +{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 pid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000002 00000002 top.source_unit info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.source_unit info} Sending group: 0x00000000 UID(2) PID(0) add {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(0) add -{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 1 FETCHED 0 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000003 00000003 top.dispatch info} receiveCredits_: alu0 got 2 credits, total: 10 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 'add 3,1,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 FETCHED 0 'add 3,1,2' to alu0 +{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 pid: 0 'add 3,1,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000003 00000003 top.source_unit info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.source_unit info} Sending group: 0x00000000 UID(3) PID(0) add {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(3) PID(0) add -{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 2 FETCHED 0 'add 3,1,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000004 00000004 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 'add 3,1,2' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 FETCHED 0 'add 3,1,2' to alu0 +{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 pid: 0 'add 3,1,2' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000004 00000004 top.source_unit info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.source_unit info} Sending group: 0x00000000 UID(4) PID(0) add {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add -{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 3 FETCHED 0 'add 3,1,2' ' sinked +{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000005 00000005 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 'add 3,1,2' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 FETCHED 0 'add 3,1,2' to alu0 +{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 pid: 0 'add 3,1,2' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000005 00000005 top.source_unit info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.source_unit info} Sending group: 0x00000000 UID(5) PID(0) add {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(5) PID(0) add -{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 4 FETCHED 0 'add 3,1,2' ' sinked +{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000006 00000006 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 5 FETCHED 0 'add 3,1,2' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 FETCHED 0 'add 3,1,2' to alu0 +{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 5 FETCHED 0 pid: 0 'add 3,1,2' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000006 00000006 top.source_unit info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.source_unit info} Sending group: 0x00000000 UID(6) PID(0) add {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(6) PID(0) add -{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 5 FETCHED 0 'add 3,1,2' ' sinked +{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000007 00000007 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000007 00000007 top.dispatch info} acceptInst: alu0: dispatching uid: 6 FETCHED 0 'add 3,1,2' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 FETCHED 0 'add 3,1,2' to alu0 +{0000000007 00000007 top.dispatch info} acceptInst: alu0: dispatching uid: 6 FETCHED 0 pid: 0 'add 3,1,2' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000007 00000007 top.source_unit info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.source_unit info} Sending group: 0x00000000 UID(7) PID(0) add {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(7) PID(0) add -{0000000008 00000008 top.alu0 info} sinkInst_: Instruction: 'uid: 6 FETCHED 0 'add 3,1,2' ' sinked +{0000000008 00000008 top.alu0 info} sinkInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000008 00000008 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000008 00000008 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 'add 3,1,2' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 FETCHED 0 'add 3,1,2' to alu0 +{0000000008 00000008 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 pid: 0 'add 3,1,2' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000008 00000008 top.source_unit info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.source_unit info} Sending group: 0x00000000 UID(8) PID(0) add {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add -{0000000009 00000009 top.alu0 info} sinkInst_: Instruction: 'uid: 7 FETCHED 0 'add 3,1,2' ' sinked +{0000000009 00000009 top.alu0 info} sinkInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000009 00000009 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 8 FETCHED 0 'add 3,1,2' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 FETCHED 0 'add 3,1,2' to alu0 +{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 8 FETCHED 0 pid: 0 'add 3,1,2' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000009 00000009 top.source_unit info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.source_unit info} Sending group: 0x00000000 UID(9) PID(0) add {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(9) PID(0) add -{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 8 FETCHED 0 'add 3,1,2' ' sinked +{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000010 00000010 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000010 00000010 top.dispatch info} acceptInst: alu0: dispatching uid: 9 FETCHED 0 'add 3,1,2' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 FETCHED 0 'add 3,1,2' to alu0 +{0000000010 00000010 top.dispatch info} acceptInst: alu0: dispatching uid: 9 FETCHED 0 pid: 0 'add 3,1,2' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 3,1,2' to alu0 {0000000010 00000010 top.source_unit info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.source_unit info} Sending group: 0x00000000 UID(10) PID(0) add {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(10) PID(0) add {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000011 00000011 top.alu0 info} sinkInst_: Instruction: 'uid: 9 FETCHED 0 'add 3,1,2' ' sinked +{0000000011 00000011 top.alu0 info} sinkInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 0 'add 3,1,2' ' sinked {0000000011 00000011 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000012 00000012 top.dispatch info} receiveCredits_: alu0 got 0 credits, total: 10 diff --git a/test/core/rename/expected_output/big_core.out.EXPECTED b/test/core/rename/expected_output/big_core.out.EXPECTED index e8370865..e4e40281 100644 --- a/test/core/rename/expected_output/big_core.out.EXPECTED +++ b/test/core/rename/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Thursday Thu Apr 13 11:02:46 2023 -#Elapsed: 0.069944s +#Start: Friday Fri Jun 30 14:11:58 2023 +#Elapsed: 0.002374s {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: alu0 got 10 credits, total: 10 @@ -71,7 +71,8 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 FETCHED 0 'add 3,1,2' +{0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard @@ -79,128 +80,137 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 FETCHED 0 'add 3,1,2' to alu0 -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 FETCHED 0 'add 4,3,2' +{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to alu0 +{0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [2,32] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add -{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked -{0000000003 00000003 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' ' sinked {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 FETCHED 0 'add 4,3,2' to alu0 -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 FETCHED 0 'mul 13,12,11' +{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to alu0 +{0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 0 RETIRED 0 'add 3,1,2' +{0000000004 00000004 top.rename info} getAckFromROB_: Retired instruction: uid: 0 RETIRED 0 pid: 1 'add 3,1,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 1 FETCHED 0 'add 4,3,2' ' sinked -{0000000004 00000004 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 1 FETCHED 0 'add 4,3,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' ' sinked {0000000004 00000004 top.dispatch info} receiveCredits_: alu0 got 2 credits, total: 10 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 FETCHED 0 'mul 13,12,11' to alu0 -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 FETCHED 0 'sub 14,13,12' +{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to alu0 +{0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,34] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(4) PID(5) sub -{0000000005 00000005 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 1 RETIRED 0 'add 4,3,2' +{0000000005 00000005 top.rename info} getAckFromROB_: Retired instruction: uid: 1 RETIRED 0 pid: 2 'add 4,3,2' {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(3) PID(4) sub -{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 2 FETCHED 0 'mul 13,12,11' ' sinked -{0000000005 00000005 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 2 FETCHED 0 'mul 13,12,11' ' sinked +{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' ' sinked +{0000000005 00000005 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' ' sinked {0000000005 00000005 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 'sub 14,13,12' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 FETCHED 0 'sub 14,13,12' to alu0 -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 FETCHED 0 'sub 5,4,3' +{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' to alu0 +{0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 5 'sub 5,4,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [32-33] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(5) PID(6) lw -{0000000006 00000006 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 2 RETIRED 0 'mul 13,12,11' +{0000000006 00000006 top.rename info} getAckFromROB_: Retired instruction: uid: 2 RETIRED 0 pid: 3 'mul 13,12,11' {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(5) sub -{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 3 FETCHED 0 'sub 14,13,12' ' sinked -{0000000006 00000006 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 3 FETCHED 0 'sub 14,13,12' ' sinked +{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' ' sinked +{0000000006 00000006 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' ' sinked {0000000006 00000006 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 'sub 5,4,3' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 FETCHED 0 'sub 5,4,3' to alu0 -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 FETCHED 0 'lw 5,4,3' +{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 4 RENAMED 0 pid: 5 'sub 5,4,3' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' to alu0 +{0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 6 'lw 5,4,3' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [32-33] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(6) PID(7) sw -{0000000007 00000007 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 3 RETIRED 0 'sub 14,13,12' +{0000000007 00000007 top.rename info} getAckFromROB_: Retired instruction: uid: 3 RETIRED 0 pid: 4 'sub 14,13,12' {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(5) PID(6) lw -{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 4 FETCHED 0 'sub 5,4,3' ' sinked -{0000000007 00000007 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 4 FETCHED 0 'sub 5,4,3' ' sinked +{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' ' sinked +{0000000007 00000007 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' ' sinked {0000000007 00000007 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000007 00000007 top.dispatch info} acceptInst: lsu: dispatching uid: 5 FETCHED 0 'lw 5,4,3' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 FETCHED 0 'lw 5,4,3' to lsu -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 FETCHED 0 'sw 3' +{0000000007 00000007 top.dispatch info} acceptInst: lsu: dispatching uid: 5 RENAMED 0 pid: 6 'lw 5,4,3' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' to lsu +{0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 7 'sw 3' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(7) PID(8) div -{0000000008 00000008 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 4 RETIRED 0 'sub 5,4,3' +{0000000008 00000008 top.rename info} getAckFromROB_: Retired instruction: uid: 4 RETIRED 0 pid: 5 'sub 5,4,3' {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(6) PID(7) sw -{0000000008 00000008 top.lsu info} sinkInst_: Instruction: 'uid: 5 FETCHED 0 'lw 5,4,3' ' sinked -{0000000008 00000008 top.lsu info} sinkRetireInst_: Instruction: 'uid: 5 FETCHED 0 'lw 5,4,3' ' sinked +{0000000008 00000008 top.lsu info} sinkInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' ' sinked +{0000000008 00000008 top.lsu info} sinkRetireInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' ' sinked {0000000008 00000008 top.dispatch info} receiveCredits_: alu0 got 0 credits, total: 10 {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000008 00000008 top.dispatch info} acceptInst: lsu: dispatching uid: 6 FETCHED 0 'sw 3' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 FETCHED 0 'sw 3' to lsu -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 FETCHED 0 'div 20,10,15' +{0000000008 00000008 top.dispatch info} acceptInst: lsu: dispatching uid: 6 RENAMED 0 pid: 7 'sw 3' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 7 'sw 3' to lsu +{0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 8 'div 20,10,15' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [10] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [10,15] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(8) PID(9) fadd.s -{0000000009 00000009 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 5 RETIRED 0 'lw 5,4,3' +{0000000009 00000009 top.rename info} getAckFromROB_: Retired instruction: uid: 5 RETIRED 0 pid: 6 'lw 5,4,3' {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(7) PID(8) div -{0000000009 00000009 top.lsu info} sinkInst_: Instruction: 'uid: 6 FETCHED 0 'sw 3' ' sinked -{0000000009 00000009 top.lsu info} sinkRetireInst_: Instruction: 'uid: 6 FETCHED 0 'sw 3' ' sinked +{0000000009 00000009 top.lsu info} sinkInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 7 'sw 3' ' sinked +{0000000009 00000009 top.lsu info} sinkRetireInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 7 'sw 3' ' sinked {0000000009 00000009 top.dispatch info} receiveCredits_: lsu got 2 credits, total: 10 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 'div 20,10,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 FETCHED 0 'div 20,10,15' to alu0 -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 FETCHED 0 'fadd.s ' +{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 7 RENAMED 0 pid: 8 'div 20,10,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' to alu0 +{0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 9 'fadd.s ' {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(9) PID(10) beq -{0000000010 00000010 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 6 RETIRED 0 'sw 3' +{0000000010 00000010 top.rename info} getAckFromROB_: Retired instruction: uid: 6 RETIRED 0 pid: 7 'sw 3' {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(9) fadd.s -{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 7 FETCHED 0 'div 20,10,15' ' sinked -{0000000010 00000010 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 7 FETCHED 0 'div 20,10,15' ' sinked +{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' ' sinked +{0000000010 00000010 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' ' sinked {0000000010 00000010 top.dispatch info} receiveCredits_: lsu got 0 credits, total: 10 {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000010 00000010 top.dispatch info} acceptInst: fpu0: dispatching uid: 8 FETCHED 0 'fadd.s ' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 FETCHED 0 'fadd.s ' to fpu0 -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 FETCHED 0 'beq ' +{0000000010 00000010 top.dispatch info} acceptInst: fpu0: dispatching uid: 8 RENAMED 0 pid: 9 'fadd.s ' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' to fpu0 +{0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 10 'beq ' {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 -{0000000011 00000011 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 7 RETIRED 0 'div 20,10,15' +{0000000011 00000011 top.rename info} getAckFromROB_: Retired instruction: uid: 7 RETIRED 0 pid: 8 'div 20,10,15' {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(9) PID(10) beq -{0000000011 00000011 top.fpu0 info} sinkInst_: Instruction: 'uid: 8 FETCHED 0 'fadd.s ' ' sinked -{0000000011 00000011 top.fpu0 info} sinkRetireInst_: Instruction: 'uid: 8 FETCHED 0 'fadd.s ' ' sinked +{0000000011 00000011 top.fpu0 info} sinkInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' ' sinked +{0000000011 00000011 top.fpu0 info} sinkRetireInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' ' sinked {0000000011 00000011 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: br0: dispatching uid: 9 FETCHED 0 'beq ' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 FETCHED 0 'beq ' to br0 -{0000000012 00000012 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 8 RETIRED 0 'fadd.s ' -{0000000012 00000012 top.br0 info} sinkInst_: Instruction: 'uid: 9 FETCHED 0 'beq ' ' sinked -{0000000012 00000012 top.br0 info} sinkRetireInst_: Instruction: 'uid: 9 FETCHED 0 'beq ' ' sinked +{0000000011 00000011 top.dispatch info} acceptInst: br0: dispatching uid: 9 RENAMED 0 pid: 10 'beq ' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 10 'beq ' to br0 +{0000000012 00000012 top.rename info} getAckFromROB_: Retired instruction: uid: 8 RETIRED 0 pid: 9 'fadd.s ' +{0000000012 00000012 top.br0 info} sinkInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 10 'beq ' ' sinked +{0000000012 00000012 top.br0 info} sinkRetireInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 10 'beq ' ' sinked {0000000012 00000012 top.dispatch info} receiveCredits_: fpu0 got 1 credits, total: 10 {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000013 00000013 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 9 RETIRED 0 'beq ' +{0000000013 00000013 top.rename info} getAckFromROB_: Retired instruction: uid: 9 RETIRED 0 pid: 10 'beq ' {0000000013 00000013 top.dispatch info} receiveCredits_: br0 got 1 credits, total: 10 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process diff --git a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED index cef9f8b7..46d0534f 100644 --- a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED +++ b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Thursday Thu Apr 13 11:02:15 2023 -#Elapsed: 0.087617s +#Start: Friday Fri Jun 30 14:11:31 2023 +#Elapsed: 0.002329s {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: alu0 got 10 credits, total: 10 @@ -71,7 +71,8 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 FETCHED 0 'add 3,1,2' +{0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard @@ -79,131 +80,143 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 FETCHED 0 'add 3,1,2' to alu0 -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 FETCHED 0 'add 4,3,2' +{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to alu0 +{0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [2,32] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add -{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked -{0000000003 00000003 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' ' sinked {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 FETCHED 0 'add 4,3,2' to alu0 -{0000000004 00000004 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 0 RETIRED 0 'add 3,1,2' -{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 1 FETCHED 0 'add 4,3,2' ' sinked -{0000000004 00000004 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 1 FETCHED 0 'add 4,3,2' ' sinked +{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to alu0 +{0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NO_RENAMES +{0000000004 00000004 top.rename info} getAckFromROB_: Retired instruction: uid: 0 RETIRED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' ' sinked {0000000004 00000004 top.dispatch info} receiveCredits_: alu0 got 2 credits, total: 10 {0000000004 00000004 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 FETCHED 0 'mul 13,12,11' +{0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [3] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000005 00000005 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 1 RETIRED 0 'add 4,3,2' +{0000000005 00000005 top.rename info} getAckFromROB_: Retired instruction: uid: 1 RETIRED 0 pid: 2 'add 4,3,2' {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul {0000000005 00000005 top.dispatch info} receiveCredits_: alu0 got 0 credits, total: 10 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 'mul 13,12,11' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 FETCHED 0 'mul 13,12,11' to alu0 -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 FETCHED 0 'sub 14,13,12' +{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to alu0 +{0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,12] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [4] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(4) PID(5) sub {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(3) PID(4) sub -{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 2 FETCHED 0 'mul 13,12,11' ' sinked -{0000000006 00000006 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 2 FETCHED 0 'mul 13,12,11' ' sinked +{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' ' sinked +{0000000006 00000006 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' ' sinked {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 'sub 14,13,12' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 FETCHED 0 'sub 14,13,12' to alu0 -{0000000007 00000007 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 2 RETIRED 0 'mul 13,12,11' -{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 3 FETCHED 0 'sub 14,13,12' ' sinked -{0000000007 00000007 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 3 FETCHED 0 'sub 14,13,12' ' sinked +{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' to alu0 +{0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NO_RENAMES +{0000000007 00000007 top.rename info} getAckFromROB_: Retired instruction: uid: 2 RETIRED 0 pid: 3 'mul 13,12,11' +{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' ' sinked +{0000000007 00000007 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' ' sinked {0000000007 00000007 top.dispatch info} receiveCredits_: alu0 got 2 credits, total: 10 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 FETCHED 0 'sub 5,4,3' +{0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 5 'sub 5,4,3' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [32-33] for 'integer' scoreboard {0000000007 00000007 top.rename info} renameInstructions_: setup destination register bit mask [13] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(5) PID(6) lw -{0000000008 00000008 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 3 RETIRED 0 'sub 14,13,12' +{0000000008 00000008 top.rename info} getAckFromROB_: Retired instruction: uid: 3 RETIRED 0 pid: 4 'sub 14,13,12' {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(5) sub {0000000008 00000008 top.dispatch info} receiveCredits_: alu0 got 0 credits, total: 10 {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000008 00000008 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 'sub 5,4,3' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 FETCHED 0 'sub 5,4,3' to alu0 -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 FETCHED 0 'lw 5,4,3' +{0000000008 00000008 top.dispatch info} acceptInst: alu0: dispatching uid: 4 RENAMED 0 pid: 5 'sub 5,4,3' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' to alu0 +{0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 6 'lw 5,4,3' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [32-33] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [14] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(6) PID(7) sw {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(5) PID(6) lw -{0000000009 00000009 top.alu0 info} sinkInst_: Instruction: 'uid: 4 FETCHED 0 'sub 5,4,3' ' sinked -{0000000009 00000009 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 4 FETCHED 0 'sub 5,4,3' ' sinked +{0000000009 00000009 top.alu0 info} sinkInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' ' sinked +{0000000009 00000009 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' ' sinked {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000009 00000009 top.dispatch info} acceptInst: lsu: dispatching uid: 5 FETCHED 0 'lw 5,4,3' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 FETCHED 0 'lw 5,4,3' to lsu -{0000000010 00000010 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 4 RETIRED 0 'sub 5,4,3' -{0000000010 00000010 top.lsu info} sinkInst_: Instruction: 'uid: 5 FETCHED 0 'lw 5,4,3' ' sinked -{0000000010 00000010 top.lsu info} sinkRetireInst_: Instruction: 'uid: 5 FETCHED 0 'lw 5,4,3' ' sinked +{0000000009 00000009 top.dispatch info} acceptInst: lsu: dispatching uid: 5 RENAMED 0 pid: 6 'lw 5,4,3' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' to lsu +{0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NO_RENAMES +{0000000010 00000010 top.rename info} getAckFromROB_: Retired instruction: uid: 4 RETIRED 0 pid: 5 'sub 5,4,3' +{0000000010 00000010 top.lsu info} sinkInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' ' sinked +{0000000010 00000010 top.lsu info} sinkRetireInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' ' sinked {0000000010 00000010 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000010 00000010 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 FETCHED 0 'sw 3' +{0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 7 'sw 3' {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.decode info} Sending group: 0x00000000 UID(7) PID(8) div -{0000000011 00000011 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 5 RETIRED 0 'lw 5,4,3' +{0000000011 00000011 top.rename info} getAckFromROB_: Retired instruction: uid: 5 RETIRED 0 pid: 6 'lw 5,4,3' {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(6) PID(7) sw {0000000011 00000011 top.dispatch info} receiveCredits_: lsu got 1 credits, total: 10 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: lsu: dispatching uid: 6 FETCHED 0 'sw 3' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 FETCHED 0 'sw 3' to lsu -{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 FETCHED 0 'div 20,10,15' +{0000000011 00000011 top.dispatch info} acceptInst: lsu: dispatching uid: 6 RENAMED 0 pid: 7 'sw 3' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 7 'sw 3' to lsu +{0000000011 00000011 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 8 'div 20,10,15' {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [10] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [10,15] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup destination register bit mask [5] for 'integer' scoreboard {0000000011 00000011 top.decode info} inCredits: Got credits from dut: 1 {0000000011 00000011 top.decode info} Sending group: 0x00000000 UID(8) PID(9) fadd.s {0000000012 00000012 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(7) PID(8) div -{0000000012 00000012 top.lsu info} sinkInst_: Instruction: 'uid: 6 FETCHED 0 'sw 3' ' sinked -{0000000012 00000012 top.lsu info} sinkRetireInst_: Instruction: 'uid: 6 FETCHED 0 'sw 3' ' sinked +{0000000012 00000012 top.lsu info} sinkInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 7 'sw 3' ' sinked +{0000000012 00000012 top.lsu info} sinkRetireInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 7 'sw 3' ' sinked {0000000012 00000012 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000012 00000012 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 'div 20,10,15' -{0000000012 00000012 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 FETCHED 0 'div 20,10,15' to alu0 -{0000000012 00000012 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 FETCHED 0 'fadd.s ' +{0000000012 00000012 top.dispatch info} acceptInst: alu0: dispatching uid: 7 RENAMED 0 pid: 8 'div 20,10,15' +{0000000012 00000012 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' to alu0 +{0000000012 00000012 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000012 00000012 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 9 'fadd.s ' {0000000012 00000012 top.decode info} inCredits: Got credits from dut: 1 {0000000012 00000012 top.decode info} Sending group: 0x00000000 UID(9) PID(10) beq -{0000000013 00000013 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 6 RETIRED 0 'sw 3' +{0000000013 00000013 top.rename info} getAckFromROB_: Retired instruction: uid: 6 RETIRED 0 pid: 7 'sw 3' {0000000013 00000013 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(9) fadd.s -{0000000013 00000013 top.alu0 info} sinkInst_: Instruction: 'uid: 7 FETCHED 0 'div 20,10,15' ' sinked -{0000000013 00000013 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 7 FETCHED 0 'div 20,10,15' ' sinked +{0000000013 00000013 top.alu0 info} sinkInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' ' sinked +{0000000013 00000013 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' ' sinked {0000000013 00000013 top.dispatch info} receiveCredits_: lsu got 1 credits, total: 10 {0000000013 00000013 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000013 00000013 top.dispatch info} acceptInst: fpu0: dispatching uid: 8 FETCHED 0 'fadd.s ' -{0000000013 00000013 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 FETCHED 0 'fadd.s ' to fpu0 -{0000000013 00000013 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 FETCHED 0 'beq ' +{0000000013 00000013 top.dispatch info} acceptInst: fpu0: dispatching uid: 8 RENAMED 0 pid: 9 'fadd.s ' +{0000000013 00000013 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' to fpu0 +{0000000013 00000013 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000013 00000013 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 10 'beq ' {0000000013 00000013 top.decode info} inCredits: Got credits from dut: 1 -{0000000014 00000014 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 7 RETIRED 0 'div 20,10,15' +{0000000014 00000014 top.rename info} getAckFromROB_: Retired instruction: uid: 7 RETIRED 0 pid: 8 'div 20,10,15' {0000000014 00000014 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(9) PID(10) beq -{0000000014 00000014 top.fpu0 info} sinkInst_: Instruction: 'uid: 8 FETCHED 0 'fadd.s ' ' sinked -{0000000014 00000014 top.fpu0 info} sinkRetireInst_: Instruction: 'uid: 8 FETCHED 0 'fadd.s ' ' sinked +{0000000014 00000014 top.fpu0 info} sinkInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' ' sinked +{0000000014 00000014 top.fpu0 info} sinkRetireInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' ' sinked {0000000014 00000014 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000014 00000014 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000014 00000014 top.dispatch info} acceptInst: br0: dispatching uid: 9 FETCHED 0 'beq ' -{0000000014 00000014 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 FETCHED 0 'beq ' to br0 -{0000000015 00000015 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 8 RETIRED 0 'fadd.s ' -{0000000015 00000015 top.br0 info} sinkInst_: Instruction: 'uid: 9 FETCHED 0 'beq ' ' sinked -{0000000015 00000015 top.br0 info} sinkRetireInst_: Instruction: 'uid: 9 FETCHED 0 'beq ' ' sinked +{0000000014 00000014 top.dispatch info} acceptInst: br0: dispatching uid: 9 RENAMED 0 pid: 10 'beq ' +{0000000014 00000014 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 10 'beq ' to br0 +{0000000015 00000015 top.rename info} getAckFromROB_: Retired instruction: uid: 8 RETIRED 0 pid: 9 'fadd.s ' +{0000000015 00000015 top.br0 info} sinkInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 10 'beq ' ' sinked +{0000000015 00000015 top.br0 info} sinkRetireInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 10 'beq ' ' sinked {0000000015 00000015 top.dispatch info} receiveCredits_: fpu0 got 1 credits, total: 10 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 9 RETIRED 0 'beq ' +{0000000016 00000016 top.rename info} getAckFromROB_: Retired instruction: uid: 9 RETIRED 0 pid: 10 'beq ' {0000000016 00000016 top.dispatch info} receiveCredits_: br0 got 1 credits, total: 10 {0000000016 00000016 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process diff --git a/test/core/rename/expected_output/medium_core.out.EXPECTED b/test/core/rename/expected_output/medium_core.out.EXPECTED index 72451e19..41106920 100644 --- a/test/core/rename/expected_output/medium_core.out.EXPECTED +++ b/test/core/rename/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Thursday Thu Apr 13 10:49:19 2023 -#Elapsed: 0.007518s +#Start: Friday Fri Jun 30 14:12:15 2023 +#Elapsed: 0.001604s {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: alu0 got 10 credits, total: 10 @@ -23,7 +23,8 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 FETCHED 0 'add 3,1,2' +{0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard @@ -31,128 +32,137 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 FETCHED 0 'add 3,1,2' to alu0 -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 FETCHED 0 'add 4,3,2' +{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to alu0 +{0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [2,32] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add -{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked -{0000000003 00000003 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' ' sinked {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 FETCHED 0 'add 4,3,2' to alu0 -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 FETCHED 0 'mul 13,12,11' +{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to alu0 +{0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 0 RETIRED 0 'add 3,1,2' +{0000000004 00000004 top.rename info} getAckFromROB_: Retired instruction: uid: 0 RETIRED 0 pid: 1 'add 3,1,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 1 FETCHED 0 'add 4,3,2' ' sinked -{0000000004 00000004 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 1 FETCHED 0 'add 4,3,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' ' sinked {0000000004 00000004 top.dispatch info} receiveCredits_: alu0 got 2 credits, total: 10 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 FETCHED 0 'mul 13,12,11' to alu0 -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 FETCHED 0 'sub 14,13,12' +{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to alu0 +{0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,34] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(4) PID(5) sub -{0000000005 00000005 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 1 RETIRED 0 'add 4,3,2' +{0000000005 00000005 top.rename info} getAckFromROB_: Retired instruction: uid: 1 RETIRED 0 pid: 2 'add 4,3,2' {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(3) PID(4) sub -{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 2 FETCHED 0 'mul 13,12,11' ' sinked -{0000000005 00000005 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 2 FETCHED 0 'mul 13,12,11' ' sinked +{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' ' sinked +{0000000005 00000005 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' ' sinked {0000000005 00000005 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 'sub 14,13,12' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 FETCHED 0 'sub 14,13,12' to alu0 -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 FETCHED 0 'sub 5,4,3' +{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' to alu0 +{0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 5 'sub 5,4,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [32-33] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(5) PID(6) lw -{0000000006 00000006 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 2 RETIRED 0 'mul 13,12,11' +{0000000006 00000006 top.rename info} getAckFromROB_: Retired instruction: uid: 2 RETIRED 0 pid: 3 'mul 13,12,11' {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(5) sub -{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 3 FETCHED 0 'sub 14,13,12' ' sinked -{0000000006 00000006 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 3 FETCHED 0 'sub 14,13,12' ' sinked +{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' ' sinked +{0000000006 00000006 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' ' sinked {0000000006 00000006 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 'sub 5,4,3' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 FETCHED 0 'sub 5,4,3' to alu0 -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 FETCHED 0 'lw 5,4,3' +{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 4 RENAMED 0 pid: 5 'sub 5,4,3' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' to alu0 +{0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 6 'lw 5,4,3' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [32-33] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(6) PID(7) sw -{0000000007 00000007 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 3 RETIRED 0 'sub 14,13,12' +{0000000007 00000007 top.rename info} getAckFromROB_: Retired instruction: uid: 3 RETIRED 0 pid: 4 'sub 14,13,12' {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(5) PID(6) lw -{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 4 FETCHED 0 'sub 5,4,3' ' sinked -{0000000007 00000007 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 4 FETCHED 0 'sub 5,4,3' ' sinked +{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' ' sinked +{0000000007 00000007 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' ' sinked {0000000007 00000007 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000007 00000007 top.dispatch info} acceptInst: lsu: dispatching uid: 5 FETCHED 0 'lw 5,4,3' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 FETCHED 0 'lw 5,4,3' to lsu -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 FETCHED 0 'sw 3' +{0000000007 00000007 top.dispatch info} acceptInst: lsu: dispatching uid: 5 RENAMED 0 pid: 6 'lw 5,4,3' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' to lsu +{0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 7 'sw 3' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(7) PID(8) div -{0000000008 00000008 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 4 RETIRED 0 'sub 5,4,3' +{0000000008 00000008 top.rename info} getAckFromROB_: Retired instruction: uid: 4 RETIRED 0 pid: 5 'sub 5,4,3' {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(6) PID(7) sw -{0000000008 00000008 top.lsu info} sinkInst_: Instruction: 'uid: 5 FETCHED 0 'lw 5,4,3' ' sinked -{0000000008 00000008 top.lsu info} sinkRetireInst_: Instruction: 'uid: 5 FETCHED 0 'lw 5,4,3' ' sinked +{0000000008 00000008 top.lsu info} sinkInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' ' sinked +{0000000008 00000008 top.lsu info} sinkRetireInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' ' sinked {0000000008 00000008 top.dispatch info} receiveCredits_: alu0 got 0 credits, total: 10 {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000008 00000008 top.dispatch info} acceptInst: lsu: dispatching uid: 6 FETCHED 0 'sw 3' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 FETCHED 0 'sw 3' to lsu -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 FETCHED 0 'div 20,10,15' +{0000000008 00000008 top.dispatch info} acceptInst: lsu: dispatching uid: 6 RENAMED 0 pid: 7 'sw 3' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 7 'sw 3' to lsu +{0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 8 'div 20,10,15' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [10] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [10,15] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(8) PID(9) fadd.s -{0000000009 00000009 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 5 RETIRED 0 'lw 5,4,3' +{0000000009 00000009 top.rename info} getAckFromROB_: Retired instruction: uid: 5 RETIRED 0 pid: 6 'lw 5,4,3' {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(7) PID(8) div -{0000000009 00000009 top.lsu info} sinkInst_: Instruction: 'uid: 6 FETCHED 0 'sw 3' ' sinked -{0000000009 00000009 top.lsu info} sinkRetireInst_: Instruction: 'uid: 6 FETCHED 0 'sw 3' ' sinked +{0000000009 00000009 top.lsu info} sinkInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 7 'sw 3' ' sinked +{0000000009 00000009 top.lsu info} sinkRetireInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 7 'sw 3' ' sinked {0000000009 00000009 top.dispatch info} receiveCredits_: lsu got 2 credits, total: 10 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 'div 20,10,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 FETCHED 0 'div 20,10,15' to alu0 -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 FETCHED 0 'fadd.s ' +{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 7 RENAMED 0 pid: 8 'div 20,10,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' to alu0 +{0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 9 'fadd.s ' {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(9) PID(10) beq -{0000000010 00000010 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 6 RETIRED 0 'sw 3' +{0000000010 00000010 top.rename info} getAckFromROB_: Retired instruction: uid: 6 RETIRED 0 pid: 7 'sw 3' {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(9) fadd.s -{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 7 FETCHED 0 'div 20,10,15' ' sinked -{0000000010 00000010 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 7 FETCHED 0 'div 20,10,15' ' sinked +{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' ' sinked +{0000000010 00000010 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' ' sinked {0000000010 00000010 top.dispatch info} receiveCredits_: lsu got 0 credits, total: 10 {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000010 00000010 top.dispatch info} acceptInst: fpu0: dispatching uid: 8 FETCHED 0 'fadd.s ' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 FETCHED 0 'fadd.s ' to fpu0 -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 FETCHED 0 'beq ' +{0000000010 00000010 top.dispatch info} acceptInst: fpu0: dispatching uid: 8 RENAMED 0 pid: 9 'fadd.s ' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' to fpu0 +{0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 10 'beq ' {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 -{0000000011 00000011 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 7 RETIRED 0 'div 20,10,15' +{0000000011 00000011 top.rename info} getAckFromROB_: Retired instruction: uid: 7 RETIRED 0 pid: 8 'div 20,10,15' {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(9) PID(10) beq -{0000000011 00000011 top.fpu0 info} sinkInst_: Instruction: 'uid: 8 FETCHED 0 'fadd.s ' ' sinked -{0000000011 00000011 top.fpu0 info} sinkRetireInst_: Instruction: 'uid: 8 FETCHED 0 'fadd.s ' ' sinked +{0000000011 00000011 top.fpu0 info} sinkInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' ' sinked +{0000000011 00000011 top.fpu0 info} sinkRetireInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' ' sinked {0000000011 00000011 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: br0: dispatching uid: 9 FETCHED 0 'beq ' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 FETCHED 0 'beq ' to br0 -{0000000012 00000012 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 8 RETIRED 0 'fadd.s ' -{0000000012 00000012 top.br0 info} sinkInst_: Instruction: 'uid: 9 FETCHED 0 'beq ' ' sinked -{0000000012 00000012 top.br0 info} sinkRetireInst_: Instruction: 'uid: 9 FETCHED 0 'beq ' ' sinked +{0000000011 00000011 top.dispatch info} acceptInst: br0: dispatching uid: 9 RENAMED 0 pid: 10 'beq ' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 10 'beq ' to br0 +{0000000012 00000012 top.rename info} getAckFromROB_: Retired instruction: uid: 8 RETIRED 0 pid: 9 'fadd.s ' +{0000000012 00000012 top.br0 info} sinkInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 10 'beq ' ' sinked +{0000000012 00000012 top.br0 info} sinkRetireInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 10 'beq ' ' sinked {0000000012 00000012 top.dispatch info} receiveCredits_: fpu0 got 1 credits, total: 10 {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000013 00000013 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 9 RETIRED 0 'beq ' +{0000000013 00000013 top.rename info} getAckFromROB_: Retired instruction: uid: 9 RETIRED 0 pid: 10 'beq ' {0000000013 00000013 top.dispatch info} receiveCredits_: br0 got 1 credits, total: 10 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process diff --git a/test/core/rename/expected_output/small_core.out.EXPECTED b/test/core/rename/expected_output/small_core.out.EXPECTED index 0af7ac1f..672ecdbf 100644 --- a/test/core/rename/expected_output/small_core.out.EXPECTED +++ b/test/core/rename/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Thursday Thu Apr 13 10:49:19 2023 -#Elapsed: 0.013037s +#Start: Friday Fri Jun 30 14:12:22 2023 +#Elapsed: 0.002573s {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: alu0 got 10 credits, total: 10 @@ -17,7 +17,8 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 FETCHED 0 'add 3,1,2' +{0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard @@ -25,128 +26,137 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 0 FETCHED 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 FETCHED 0 'add 3,1,2' to alu0 -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 FETCHED 0 'add 4,3,2' +{0000000002 00000002 top.dispatch info} acceptInst: alu0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to alu0 +{0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [2,32] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add -{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked -{0000000003 00000003 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 0 FETCHED 0 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' ' sinked +{0000000003 00000003 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' ' sinked {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 1 FETCHED 0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 FETCHED 0 'add 4,3,2' to alu0 -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 FETCHED 0 'mul 13,12,11' +{0000000003 00000003 top.dispatch info} acceptInst: alu0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to alu0 +{0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 0 RETIRED 0 'add 3,1,2' +{0000000004 00000004 top.rename info} getAckFromROB_: Retired instruction: uid: 0 RETIRED 0 pid: 1 'add 3,1,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 1 FETCHED 0 'add 4,3,2' ' sinked -{0000000004 00000004 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 1 FETCHED 0 'add 4,3,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' ' sinked +{0000000004 00000004 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' ' sinked {0000000004 00000004 top.dispatch info} receiveCredits_: alu0 got 2 credits, total: 10 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 2 FETCHED 0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 FETCHED 0 'mul 13,12,11' to alu0 -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 FETCHED 0 'sub 14,13,12' +{0000000004 00000004 top.dispatch info} acceptInst: alu0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to alu0 +{0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,34] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(4) PID(5) sub -{0000000005 00000005 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 1 RETIRED 0 'add 4,3,2' +{0000000005 00000005 top.rename info} getAckFromROB_: Retired instruction: uid: 1 RETIRED 0 pid: 2 'add 4,3,2' {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(3) PID(4) sub -{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 2 FETCHED 0 'mul 13,12,11' ' sinked -{0000000005 00000005 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 2 FETCHED 0 'mul 13,12,11' ' sinked +{0000000005 00000005 top.alu0 info} sinkInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' ' sinked +{0000000005 00000005 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' ' sinked {0000000005 00000005 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 3 FETCHED 0 'sub 14,13,12' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 FETCHED 0 'sub 14,13,12' to alu0 -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 FETCHED 0 'sub 5,4,3' +{0000000005 00000005 top.dispatch info} acceptInst: alu0: dispatching uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' to alu0 +{0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 5 'sub 5,4,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [32-33] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(5) PID(6) lw -{0000000006 00000006 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 2 RETIRED 0 'mul 13,12,11' +{0000000006 00000006 top.rename info} getAckFromROB_: Retired instruction: uid: 2 RETIRED 0 pid: 3 'mul 13,12,11' {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(5) sub -{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 3 FETCHED 0 'sub 14,13,12' ' sinked -{0000000006 00000006 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 3 FETCHED 0 'sub 14,13,12' ' sinked +{0000000006 00000006 top.alu0 info} sinkInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' ' sinked +{0000000006 00000006 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 3 DISPATCHED 0 pid: 4 'sub 14,13,12' ' sinked {0000000006 00000006 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 4 FETCHED 0 'sub 5,4,3' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 FETCHED 0 'sub 5,4,3' to alu0 -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 FETCHED 0 'lw 5,4,3' +{0000000006 00000006 top.dispatch info} acceptInst: alu0: dispatching uid: 4 RENAMED 0 pid: 5 'sub 5,4,3' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' to alu0 +{0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 6 'lw 5,4,3' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [32-33] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(6) PID(7) sw -{0000000007 00000007 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 3 RETIRED 0 'sub 14,13,12' +{0000000007 00000007 top.rename info} getAckFromROB_: Retired instruction: uid: 3 RETIRED 0 pid: 4 'sub 14,13,12' {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(5) PID(6) lw -{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 4 FETCHED 0 'sub 5,4,3' ' sinked -{0000000007 00000007 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 4 FETCHED 0 'sub 5,4,3' ' sinked +{0000000007 00000007 top.alu0 info} sinkInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' ' sinked +{0000000007 00000007 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 4 DISPATCHED 0 pid: 5 'sub 5,4,3' ' sinked {0000000007 00000007 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000007 00000007 top.dispatch info} acceptInst: lsu: dispatching uid: 5 FETCHED 0 'lw 5,4,3' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 FETCHED 0 'lw 5,4,3' to lsu -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 FETCHED 0 'sw 3' +{0000000007 00000007 top.dispatch info} acceptInst: lsu: dispatching uid: 5 RENAMED 0 pid: 6 'lw 5,4,3' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' to lsu +{0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 7 'sw 3' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(7) PID(8) div -{0000000008 00000008 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 4 RETIRED 0 'sub 5,4,3' +{0000000008 00000008 top.rename info} getAckFromROB_: Retired instruction: uid: 4 RETIRED 0 pid: 5 'sub 5,4,3' {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(6) PID(7) sw -{0000000008 00000008 top.lsu info} sinkInst_: Instruction: 'uid: 5 FETCHED 0 'lw 5,4,3' ' sinked -{0000000008 00000008 top.lsu info} sinkRetireInst_: Instruction: 'uid: 5 FETCHED 0 'lw 5,4,3' ' sinked +{0000000008 00000008 top.lsu info} sinkInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' ' sinked +{0000000008 00000008 top.lsu info} sinkRetireInst_: Instruction: 'uid: 5 DISPATCHED 0 pid: 6 'lw 5,4,3' ' sinked {0000000008 00000008 top.dispatch info} receiveCredits_: alu0 got 0 credits, total: 10 {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000008 00000008 top.dispatch info} acceptInst: lsu: dispatching uid: 6 FETCHED 0 'sw 3' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 FETCHED 0 'sw 3' to lsu -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 FETCHED 0 'div 20,10,15' +{0000000008 00000008 top.dispatch info} acceptInst: lsu: dispatching uid: 6 RENAMED 0 pid: 7 'sw 3' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 7 'sw 3' to lsu +{0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 8 'div 20,10,15' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [10] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [10,15] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(8) PID(9) fadd.s -{0000000009 00000009 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 5 RETIRED 0 'lw 5,4,3' +{0000000009 00000009 top.rename info} getAckFromROB_: Retired instruction: uid: 5 RETIRED 0 pid: 6 'lw 5,4,3' {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(7) PID(8) div -{0000000009 00000009 top.lsu info} sinkInst_: Instruction: 'uid: 6 FETCHED 0 'sw 3' ' sinked -{0000000009 00000009 top.lsu info} sinkRetireInst_: Instruction: 'uid: 6 FETCHED 0 'sw 3' ' sinked +{0000000009 00000009 top.lsu info} sinkInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 7 'sw 3' ' sinked +{0000000009 00000009 top.lsu info} sinkRetireInst_: Instruction: 'uid: 6 DISPATCHED 0 pid: 7 'sw 3' ' sinked {0000000009 00000009 top.dispatch info} receiveCredits_: lsu got 2 credits, total: 10 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 7 FETCHED 0 'div 20,10,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 FETCHED 0 'div 20,10,15' to alu0 -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 FETCHED 0 'fadd.s ' +{0000000009 00000009 top.dispatch info} acceptInst: alu0: dispatching uid: 7 RENAMED 0 pid: 8 'div 20,10,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' to alu0 +{0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 9 'fadd.s ' {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(9) PID(10) beq -{0000000010 00000010 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 6 RETIRED 0 'sw 3' +{0000000010 00000010 top.rename info} getAckFromROB_: Retired instruction: uid: 6 RETIRED 0 pid: 7 'sw 3' {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(9) fadd.s -{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 7 FETCHED 0 'div 20,10,15' ' sinked -{0000000010 00000010 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 7 FETCHED 0 'div 20,10,15' ' sinked +{0000000010 00000010 top.alu0 info} sinkInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' ' sinked +{0000000010 00000010 top.alu0 info} sinkRetireInst_: Instruction: 'uid: 7 DISPATCHED 0 pid: 8 'div 20,10,15' ' sinked {0000000010 00000010 top.dispatch info} receiveCredits_: lsu got 0 credits, total: 10 {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000010 00000010 top.dispatch info} acceptInst: fpu0: dispatching uid: 8 FETCHED 0 'fadd.s ' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 FETCHED 0 'fadd.s ' to fpu0 -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 FETCHED 0 'beq ' +{0000000010 00000010 top.dispatch info} acceptInst: fpu0: dispatching uid: 8 RENAMED 0 pid: 9 'fadd.s ' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' to fpu0 +{0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 10 'beq ' {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 -{0000000011 00000011 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 7 RETIRED 0 'div 20,10,15' +{0000000011 00000011 top.rename info} getAckFromROB_: Retired instruction: uid: 7 RETIRED 0 pid: 8 'div 20,10,15' {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(9) PID(10) beq -{0000000011 00000011 top.fpu0 info} sinkInst_: Instruction: 'uid: 8 FETCHED 0 'fadd.s ' ' sinked -{0000000011 00000011 top.fpu0 info} sinkRetireInst_: Instruction: 'uid: 8 FETCHED 0 'fadd.s ' ' sinked +{0000000011 00000011 top.fpu0 info} sinkInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' ' sinked +{0000000011 00000011 top.fpu0 info} sinkRetireInst_: Instruction: 'uid: 8 DISPATCHED 0 pid: 9 'fadd.s ' ' sinked {0000000011 00000011 top.dispatch info} receiveCredits_: alu0 got 1 credits, total: 10 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: br0: dispatching uid: 9 FETCHED 0 'beq ' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 FETCHED 0 'beq ' to br0 -{0000000012 00000012 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 8 RETIRED 0 'fadd.s ' -{0000000012 00000012 top.br0 info} sinkInst_: Instruction: 'uid: 9 FETCHED 0 'beq ' ' sinked -{0000000012 00000012 top.br0 info} sinkRetireInst_: Instruction: 'uid: 9 FETCHED 0 'beq ' ' sinked +{0000000011 00000011 top.dispatch info} acceptInst: br0: dispatching uid: 9 RENAMED 0 pid: 10 'beq ' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 10 'beq ' to br0 +{0000000012 00000012 top.rename info} getAckFromROB_: Retired instruction: uid: 8 RETIRED 0 pid: 9 'fadd.s ' +{0000000012 00000012 top.br0 info} sinkInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 10 'beq ' ' sinked +{0000000012 00000012 top.br0 info} sinkRetireInst_: Instruction: 'uid: 9 DISPATCHED 0 pid: 10 'beq ' ' sinked {0000000012 00000012 top.dispatch info} receiveCredits_: fpu0 got 1 credits, total: 10 {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000013 00000013 top.rename info} getAckFromROB_: Get Ack from ROB in Rename Stage! Retired instruction: uid: 9 RETIRED 0 'beq ' +{0000000013 00000013 top.rename info} getAckFromROB_: Retired instruction: uid: 9 RETIRED 0 pid: 10 'beq ' {0000000013 00000013 top.dispatch info} receiveCredits_: br0 got 1 credits, total: 10 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process