From 784039519c04550dc5781d6204dbab2088a50fb2 Mon Sep 17 00:00:00 2001 From: Aaron CHan Date: Thu, 30 May 2024 22:48:26 -0500 Subject: [PATCH] Testing fixed, cleanup and add vset wait to decode stage instead --- arches/big_core.yaml | 4 +- arches/isa_json/olympia_uarch_rv64v.json | 257 +++++++++++++++++- arches/medium_core.yaml | 40 ++- arches/small_core.yaml | 35 ++- core/CPUTopology.cpp | 3 - core/Decode.cpp | 70 +++-- core/Decode.hpp | 5 +- core/Dispatch.hpp | 16 ++ core/ExecutePipe.cpp | 8 +- core/ExecutePipe.hpp | 2 - core/Fetch.cpp | 66 +---- core/Fetch.hpp | 11 - core/Inst.hpp | 23 +- core/InstArchInfo.cpp | 5 +- core/InstArchInfo.hpp | 8 + core/InstGenerator.cpp | 6 + core/IssueQueue.cpp | 81 ++++-- core/Rename.cpp | 28 +- test/CMakeLists.txt | 1 + .../expected_output/big_core.out.EXPECTED | 209 +++++++------- .../expected_output/medium_core.out.EXPECTED | 217 ++++++++------- .../expected_output/small_core.out.EXPECTED | 227 ++++++++-------- .../dispatch/test_cores/test_big_core.yaml | 45 +-- .../dispatch/test_cores/test_medium_core.yaml | 45 ++- .../dispatch/test_cores/test_small_core.yaml | 35 ++- .../issue_queue/test_cores/test_big_core.yaml | 45 +-- .../test_cores/test_big_core_full.yaml | 45 +-- .../expected_output/hit_case.out.EXPECTED | 46 ++-- .../single_access.out.EXPECTED | 30 +- test/core/lsu/test_cores/test_big_core.yaml | 51 ++-- .../test_big_core_small_rename.yaml | 50 ++-- .../core/lsu/test_cores/test_medium_core.yaml | 40 ++- .../lsu/test_cores/test_medium_core_full.yaml | 40 ++- test/core/lsu/test_cores/test_small_core.yaml | 38 ++- .../lsu/test_cores/test_small_core_full.yaml | 35 ++- .../expected_output/big_core.out.EXPECTED | 47 ++-- .../big_core_small_rename.out.EXPECTED | 45 +-- .../expected_output/medium_core.out.EXPECTED | 47 ++-- .../expected_output/small_core.out.EXPECTED | 47 ++-- .../core/rename/test_cores/test_big_core.yaml | 45 +-- .../rename/test_cores/test_big_core_full.yaml | 45 +-- .../test_big_core_small_rename.yaml | 45 +-- .../test_big_core_small_rename_full.yaml | 45 +-- .../rename/test_cores/test_medium_core.yaml | 40 ++- .../test_cores/test_medium_core_full.yaml | 40 ++- .../rename/test_cores/test_small_core.yaml | 35 ++- .../test_cores/test_small_core_full.yaml | 35 ++- test/core/vector/CMakeLists.txt | 23 ++ test/core/vector/Vector_test.cpp | 237 ++++++++++++++++ test/core/vector/multiple_vset.json | 91 +++++++ .../vector/test_cores/test_big_core_full.yaml | 69 +++++ test/core/vector/vmul_transfer.json | 14 + test/core/vector/vsetivli_vadd_lmul_4.json | 16 ++ test/core/vector/vsetvl_vadd.json | 16 ++ test/core/vector/vsetvli_vadd_sew_32.json | 16 ++ test/core/vector/vsetvli_vl_max_setting.json | 15 + 56 files changed, 1997 insertions(+), 883 deletions(-) create mode 100644 test/core/vector/CMakeLists.txt create mode 100644 test/core/vector/Vector_test.cpp create mode 100644 test/core/vector/multiple_vset.json create mode 100644 test/core/vector/test_cores/test_big_core_full.yaml create mode 100644 test/core/vector/vmul_transfer.json create mode 100644 test/core/vector/vsetivli_vadd_lmul_4.json create mode 100644 test/core/vector/vsetvl_vadd.json create mode 100644 test/core/vector/vsetvli_vadd_sew_32.json create mode 100644 test/core/vector/vsetvli_vl_max_setting.json diff --git a/arches/big_core.yaml b/arches/big_core.yaml index cd83fe13..ce70684d 100644 --- a/arches/big_core.yaml +++ b/arches/big_core.yaml @@ -7,7 +7,7 @@ include: medium_core.yaml top.cpu.core0: fetch.params.num_to_fetch: 8 - decode.params.num_to_decode: 3 + decode.params.num_to_decode: 8 rename.params.num_to_rename: 8 rename.params.num_integer_renames: 64 rename.params.num_float_renames: 64 @@ -34,7 +34,7 @@ top.cpu.core0.extension.core_extensions: ["float", "f2i"], # exe7 ["br"], # exe8 ["br"], # exe9 - ["vint", "vset"] + ["vint", "vset", "vdiv", "vmul"] ] # this is used to set how many units per queue # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive diff --git a/arches/isa_json/olympia_uarch_rv64v.json b/arches/isa_json/olympia_uarch_rv64v.json index cd555671..ac8420e2 100644 --- a/arches/isa_json/olympia_uarch_rv64v.json +++ b/arches/isa_json/olympia_uarch_rv64v.json @@ -1,27 +1,254 @@ [ { - "mnemonic": "vadd.vv", - "pipe" : "vint", - "latency" : 1 + "mnemonic": "vadd.vv", + "pipe" : "vint", + "latency" : 1 }, { - "mnemonic": "vsub.vv", - "pipe" : "vint", - "latency" : 1 + "mnemonic": "vadd.vx", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vadd.vi", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vsub.vv", + "pipe" : "vint", + "latency" : 1 }, { - "mnemonic": "vsetvli", - "pipe": "vset", - "latency": 1 + "mnemonic": "vsub.vx", + "pipe" : "vint", + "latency" : 1 + }, + { + "mnemonic": "vrsub.vi", + "pipe" : "vint", + "latency" : 1 + }, + { + "mnemonic": "vrsub.vx", + "pipe" : "vint", + "latency" : 1 + }, + { + "mnemonic": "vsetvli", + "pipe": "vset", + "latency": 1 + }, + { + "mnemonic": "vsetvl", + "pipe": "vset", + "latency": 1 + }, + { + "mnemonic": "vsetivli", + "pipe": "vset", + "latency": 1 + }, + { + "mnemonic": "vmul.vv", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vmul.vx", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vmulhu.vx", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vmulhu.vv", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vmulh.vv", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vmulh.vx", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vmulhsu.vv", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vmulhsu.vx", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vdiv.vv", + "pipe": "vdiv", + "latency": 23 + }, + { + "mnemonic": "vdiv.vx", + "pipe": "vdiv", + "latency": 23 + }, + { + "mnemonic": "vdivu.vv", + "pipe": "vdiv", + "latency": 23 + }, + { + "mnemonic": "vdivu.vx", + "pipe": "vdiv", + "latency": 23 + }, + { + "mnemonic": "vremu.vv", + "pipe": "vdiv", + "latency": 23 + }, + { + "mnemonic": "vremu.vx", + "pipe": "vdiv", + "latency": 23 + }, + { + "mnemonic": "vrem.vv", + "pipe": "vdiv", + "latency": 23 + }, + { + "mnemonic": "vrem.vx", + "pipe": "vdiv", + "latency": 23 + }, + { + "mnemonic": "vwmul.vv", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vwmul.vx", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vwmulu.vv", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vwmulu.vx", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vwmulsu.vv", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vwmulsu.vx", + "pipe": "vmul", + "latency": 3 + }, + { + "mnemonic": "vwaddu.vv", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwaddu.vx", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwsubu.vv", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwsubu.vx", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwadd.vv", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwadd.vx", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwsub.vv", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwsub.vx", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwaddu.wv", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwaddu.wx", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwsubu.wv", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwsubu.wx", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwadd.wv", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwadd.wx", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwsub.wv", + "pipe": "vint", + "latency": 1 + }, + { + "mnemonic": "vwsub.wx", + "pipe": "vint", + "latency": 1 }, { - "mnemonic": "vsetvl", - "pipe": "vset", - "latency": 1 + "mnemonic": "vsmul.vx", + "pipe": "vmul", + "latency": 3 }, { - "mnemonic": "vsetivli", - "pipe": "vset", - "latency": 1 + "mnemonic": "vsmul.vv", + "pipe": "vmul", + "latency": 3 } + + ] \ No newline at end of file diff --git a/arches/medium_core.yaml b/arches/medium_core.yaml index 8b8b5a86..9fb2f0ed 100644 --- a/arches/medium_core.yaml +++ b/arches/medium_core.yaml @@ -26,7 +26,8 @@ top.cpu.core0.extension.core_extensions: ["int"], # exe2 ["float", "faddsub", "fmac"], # exe3 ["float", "f2i"], # exe4 - ["br"] # exe5 + ["br"], # exe5 + ["vint", "vset", "vdiv", "vmul"] # exe6 ] # this is used to set how many units per queue @@ -40,7 +41,8 @@ top.cpu.core0.extension.core_extensions: ["0"], # iq0 -> exe0 ["1", "2"], # iq1 -> exe1, exe2 ["3", "4"], # iq2 -> exe3, exe4 - ["5"] # iq3 -> exe5 + ["5"], # iq3 -> exe5 + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -48,16 +50,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/arches/small_core.yaml b/arches/small_core.yaml index 7ad9d7d8..09a1cc60 100644 --- a/arches/small_core.yaml +++ b/arches/small_core.yaml @@ -20,7 +20,8 @@ top.cpu.core0.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], # exe0 ["float", "faddsub", "fmac", "f2i"], # exe1 - ["br"] # exe2 + ["br"], # exe2 + ["vint", "vset", "vdiv", "vmul"] # exe3 ] # this is used to set how many units per queue # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive @@ -32,7 +33,8 @@ top.cpu.core0.extension.core_extensions: [ ["0"], # iq0 -> exe0 ["1"], # iq1 -> exe1 - ["2"] # iq2 -> exe2 + ["2"], # iq2 -> exe2 + ["3"], # iq3 -> exe3 ] top.cpu.core0.rename.scoreboards: @@ -40,14 +42,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/core/CPUTopology.cpp b/core/CPUTopology.cpp index e2486dd8..a59af2b1 100644 --- a/core/CPUTopology.cpp +++ b/core/CPUTopology.cpp @@ -383,8 +383,6 @@ void olympia::CoreTopologySimple::bindTree(sparta::RootTreeNode* root_node) pipe_target_end++; const std::string vset_in_decode = core_node + ".decode." + "ports.in_vset_inst"; - const std::string vset_in_fetch = - core_node + ".fetch." + "ports.in_vset_inst"; for (int pipe_idx = pipe_target_start; pipe_idx < pipe_target_end; ++pipe_idx) { std::string unit_name = "exe" + std::to_string(pipe_idx); @@ -406,7 +404,6 @@ void olympia::CoreTopologySimple::bindTree(sparta::RootTreeNode* root_node) const std::string exe_vset_out = core_node + ".execute." + unit_name + ".ports.out_vset"; bind_ports(vset_in_decode, exe_vset_out); - bind_ports(vset_in_fetch, exe_vset_out); break; // break after because there should only be one vset per issue queue } } diff --git a/core/Decode.cpp b/core/Decode.cpp index 5510f55e..70d3d0fa 100644 --- a/core/Decode.cpp +++ b/core/Decode.cpp @@ -122,6 +122,8 @@ namespace olympia VCSRs_.lmul = inst->getLMUL(); VCSRs_.sew = inst->getSEW(); VCSRs_.vl = inst->getVL(); + VCSRs_.vta = inst->getVTA(); + waiting_on_vset_ = false; // schedule decode, because we've been stalled on vset ev_decode_insts_event_.schedule(sparta::Clock::Cycle(0)); } @@ -153,7 +155,7 @@ namespace olympia latency_count_ = 0; - if (num_decode > 0) + if (num_decode > 0 && !waiting_on_vset_) { InstGroupPtr insts = sparta::allocate_sparta_shared_pointer(instgroup_allocator); @@ -170,47 +172,66 @@ namespace olympia uop_queue_.pop(); } else{ - auto & inst = fetch_queue_.read(0); - // if we're waiting on a vset, but it's a scalar instruction - // we can process all scalars after the vset until we reach a vset the decode queue - if(inst->isVset() && inst->getSourceOpInfoList()[0].field_value == 0 && inst->getDestOpInfoList()[0].field_value != 0){ - // set vl to vlmax, no need to block - VCSRs_.vl = Inst::VLMAX; + auto & inst = fetch_queue_.read(0); + + // for vector instructions, we block on vset and do not allow any other processing of instructions until the vset is resolved + // optimizations could be to allow scalar operations to move forward until a subsequent vector instruction is detected + // or do vset prediction + + // mavis_id 214 -> vsetvl + // mavis_id 216 -> vsetivli + if(inst->getOpCodeInfo()->getInstructionUniqueID() == 216){ + // vsetivli with immediates, we can set at decode and continue to process instruction group, no vset stall + VCSRs_.lmul = inst->getLMUL(); + VCSRs_.vl = inst->getVL(); + VCSRs_.vta = inst->getVTA(); + VCSRs_.sew = inst->getSEW(); } - if (!inst->isVset() && inst->isVector()) + else if(inst->isVset() && (inst->getSourceOpInfoList()[0].field_value != 0 || inst->getOpCodeInfo()->getInstructionUniqueID() == 214)) { - // set LMUL, VSET, VL - inst->setVCSRs(VCSRs_); + // block for vsetvl or vsetvli when rs1 of vsetvli is NOT 0 + waiting_on_vset_ = true; + // need to indicate we want a signal sent back at execute + inst->setBlockingVSET(true); + ILOG("Decode stall due to vset dependency: "<< inst); } - if (inst->getLMUL() > 1 && !inst->isVset()) + else{ + if(inst->isVset() && inst->getSourceOpInfoList()[0].field_value == 0 && inst->getDestOpInfoList()[0].field_value != 0) + { + // set vl to vlmax, no need to block, vsetvli when rs1 is 0 + VCSRs_.vl = Inst::VLMAX; + VCSRs_.vta = inst->getVTA(); + VCSRs_.sew = inst->getSEW(); + VCSRs_.lmul = inst->getLMUL(); + } + if (!inst->isVset() && inst->isVector()) + { + // set LMUL, VSET, VL, VTA for any other vector instructions + inst->setVCSRs(VCSRs_); + } + } + if (inst->getLMUL() > 1 && !inst->isVset() && inst->isVector()) { // update num_decode based on UOp count as well num_decode = std::min(uop_queue_credits_, fetch_queue_.size() + uop_queue_.size() + inst->getLMUL()-1); num_decode = std::min(num_decode, num_to_decode_); // lmul > 1, fracture instruction into UOps inst->setUOp(true); // mark instruction to denote it has UOPs - // turn this into a state machine - // send them out based on credit - // state indicating if we're decoding as normal or draining a UOp Queue ILOG("Inst: " << inst << " is being split into " << VCSRs_.lmul << " UOPs"); - // we can process the lmul, we subtract from uop_queue_credits_ - // because num_decode is min of both fetch queue and uop_queue_credits_ - // which doesn't factor in the uop amount per instruction + insts->emplace_back(inst); inst->setStatus(Inst::Status::DECODED); inst->setUOpCount(VCSRs_.lmul); fetch_queue_.pop(); for (uint32_t j = 1; j < VCSRs_.lmul; ++j) { - i++; + i++; // increment decode count to account for UOps // we create lmul - 1 instructions, because the original instruction // will also be executed, so we start creating UOPs at vector // registers + 1 until LMUL MavisType* mavis_facade_ = getMavis(getContainer()); const std::string mnemonic = inst->getMnemonic(); auto srcs = inst->getSourceOpInfoList(); - // determine different modes of agnostic vs undistrubed - // parameter in simulator for setting ^ for (auto & src : srcs) { src.field_value += j; @@ -255,6 +276,10 @@ namespace olympia ILOG("Decoded: " << inst); fetch_queue_.pop(); + if(waiting_on_vset_){ + // if we have a waiting on vset followed by more instructions, we decode vset and stall anything else + break; + } } } } @@ -297,6 +322,11 @@ namespace olympia // Send credits back to Fetch to get more instructions fetch_queue_credits_outp_.send(insts->size()); } + else{ + if(waiting_on_vset_){ + ILOG("Waiting on vset that has register dependency") + } + } // If we still have credits to send instructions as well as // instructions in the queue, schedule another decode session diff --git a/core/Decode.hpp b/core/Decode.hpp index 5d096c8a..e6769fbb 100644 --- a/core/Decode.hpp +++ b/core/Decode.hpp @@ -327,6 +327,8 @@ namespace olympia const std::vector fusion_group_definitions_; Inst::VCSRs VCSRs_; + + bool waiting_on_vset_; ////////////////////////////////////////////////////////////////////// // Decoder callbacks void sendInitialCredits_(); @@ -337,7 +339,9 @@ namespace olympia void handleFlush_(const FlushManager::FlushingCriteria & criteria); uint32_t uop_queue_credits_ = 0; + friend class DecodeTester; }; + class DecodeTester; //! \brief the fusion functor/function objects //! @@ -354,5 +358,4 @@ namespace olympia return false; } }; - } // namespace olympia diff --git a/core/Dispatch.hpp b/core/Dispatch.hpp index be93c8c8..5d8963d3 100644 --- a/core/Dispatch.hpp +++ b/core/Dispatch.hpp @@ -148,6 +148,8 @@ namespace olympia BR_BUSY = InstArchInfo::TargetPipe::BR, // Could not send any or all instructions -- BR busy VINT_BUSY = InstArchInfo::TargetPipe::VINT, + VMUL_BUSY = InstArchInfo::TargetPipe::VMUL, + VDIV_BUSY = InstArchInfo::TargetPipe::VDIV, VSET_BUSY = InstArchInfo::TargetPipe::VSET, NO_ROB_CREDITS = InstArchInfo::TargetPipe::SYS, // No credits from the ROB NOT_STALLED, // Made forward progress (dispatched all instructions or no instructions) @@ -184,6 +186,10 @@ namespace olympia sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_vint_busy", "VINT busy", sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vmul_busy", "VMUL busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vdiv_busy", "VDIV busy", + sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_vset_busy", "VSET busy", sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_sys_busy", "No credits from ROB", @@ -217,6 +223,10 @@ namespace olympia sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_vint_insts", "Total VINT insts", sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vmul_insts", "Total VMUL insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vdiv_insts", "Total VDIV insts", + sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_vset_insts", "Total VSET insts", sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_sys_insts", "Total SYS insts", @@ -316,6 +326,12 @@ namespace olympia case Dispatch::StallReason::VINT_BUSY: os << "VINT_BUSY"; break; + case Dispatch::StallReason::VMUL_BUSY: + os << "VMUL_BUSY"; + break; + case Dispatch::StallReason::VDIV_BUSY: + os << "VDIV_BUSY"; + break; case Dispatch::StallReason::VSET_BUSY: os << "VSET_BUSY"; break; diff --git a/core/ExecutePipe.cpp b/core/ExecutePipe.cpp index 2247fe15..112c6ea4 100644 --- a/core/ExecutePipe.cpp +++ b/core/ExecutePipe.cpp @@ -16,7 +16,6 @@ namespace olympia enable_random_misprediction_(p->enable_random_misprediction && p->contains_branch_unit), issue_queue_name_(p->iq_name), valu_adder_num_(p->valu_adder_num), - vfpu_adder_num_(p->vfpu_adder_num), collected_inst_(node, node->getName()) { p->enable_random_misprediction.ignore(); @@ -68,7 +67,7 @@ namespace olympia uint32_t exe_time = ignore_inst_execute_time_ ? execute_time_ : ex_inst->getExecuteTime(); if (!ex_inst->isVset() && ex_inst->isVector()) { - // have to factor in vlen, sew, valu/vfpu length to calculate how many passes are needed + // have to factor in vlen, sew, valu length to calculate how many passes are needed // i.e if VL = 256 and SEW = 8, but our VALU only has 8 64 bit adders, it will take 4 passes to // execute the entire instruction // if we have an 8 bit number, the 64 bit adder will truncate, but we have each adder support @@ -125,11 +124,12 @@ namespace olympia num_passes_needed_ = 0; } ILOG("Executed inst: " << ex_inst); - if (ex_inst->isVset()) + if (ex_inst->isVset() && ex_inst->isBlockingVSET()) { // sending back VSET CSRs ILOG("Forwarding VSET CSRs back to decode, LMUL: " << ex_inst->getLMUL() << " SEW: " - << ex_inst->getSEW()); + << ex_inst->getSEW() << " VTA: " << ex_inst->getVTA() + << " VL: " << ex_inst->getVL()); out_vset_.send(ex_inst); } auto reg_file = ex_inst->getRenameData().getDestination().rf; diff --git a/core/ExecutePipe.hpp b/core/ExecutePipe.hpp index aa50de8a..1a281454 100644 --- a/core/ExecutePipe.hpp +++ b/core/ExecutePipe.hpp @@ -52,7 +52,6 @@ namespace olympia "test mode to inject random branch mispredictions") PARAMETER(uint32_t, valu_adder_num, 8, "VALU Number of Adders") // # of 64 bit adders, so 8 64 bit adders = 512 bits - PARAMETER(uint32_t, vfpu_adder_num, 8, "VFPU Number of Adders") HIDDEN_PARAMETER(bool, contains_branch_unit, false, "Does this exe pipe contain a branch unit") HIDDEN_PARAMETER(std::string, iq_name, "", "issue queue name for scoreboard view") @@ -102,7 +101,6 @@ namespace olympia const bool enable_random_misprediction_; const std::string issue_queue_name_; uint32_t valu_adder_num_; - uint32_t vfpu_adder_num_; uint32_t num_passes_needed_ = 0; uint32_t curr_num_pass_ = 0; // Events used to issue, execute and complete the instruction diff --git a/core/Fetch.cpp b/core/Fetch.cpp index f5b8d28a..1ea423e9 100644 --- a/core/Fetch.cpp +++ b/core/Fetch.cpp @@ -22,8 +22,7 @@ namespace olympia sparta::Unit(node), num_insts_to_fetch_(p->num_to_fetch), skip_nonuser_mode_(p->skip_nonuser_mode), - my_clk_(getClock()), - fetched_queue_("FetchedQueue", p->fetched_queue_size, node->getClock(), &unit_stat_set_) + my_clk_(getClock()) { in_fetch_queue_credits_. registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveFetchQueueCredits_, uint32_t)); @@ -33,8 +32,6 @@ namespace olympia fetch_inst_event_.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "fetch_random", CREATE_SPARTA_HANDLER(Fetch, fetchInstruction_))); - in_vset_inst_.registerConsumerHandler( - CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, process_vset_, InstPtr)); // Schedule a single event to start reading from a trace file sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Fetch, initialize_)); @@ -65,48 +62,18 @@ namespace olympia InstGroupPtr insts_to_send = sparta::allocate_sparta_shared_pointer(instgroup_allocator); for(uint32_t i = 0; i < upper; ++i) { - if(!waiting_on_vset_ || fetched_queue_.size() < fetched_queue_.capacity()){ - // Note -> should we change this to block after the first vector instruction after - // a vset is detected - InstPtr ex_inst = nullptr; - if(fetched_queue_.size() > 0){ - // if we have already fetched instructions, we should process those first - ex_inst = fetched_queue_.read(0); - fetched_queue_.pop(); - } - else{ - ex_inst = inst_generator_->getNextInst(my_clk_); - } - if(SPARTA_EXPECT_TRUE(nullptr != ex_inst)){ - if ((!waiting_on_vset_) || (waiting_on_vset_ && !ex_inst->isVector())) - { - // we only need to stall for vset when it's - // vsetvl or a vset{i}vl{i} that has a vl that is not the default - // any imms can be decoded here and we don't have to stall vset - // check if indirect vset - // move stalling check to fetch, fetch has to break it up, once one direct vset is detected - if(ex_inst->isVset()){ - if(ex_inst->getSourceOpInfoList()[0].field_value != 0 || ex_inst->getOpCodeInfo()->getInstructionUniqueID() == 315){ - // vl is being set by register, need to block - // vsetvl in mavis -> give it a mavis id, if mavisid == vsetvl number - waiting_on_vset_ = true; - } - } - ex_inst->setSpeculative(speculative_path_); - insts_to_send->emplace_back(ex_inst); - - ILOG("Sending: " << ex_inst << " down the pipe"); - } - else{ - ILOG("Stalling due to waiting on vset"); - // store fetched instruction in queue - fetched_queue_.push((ex_inst)); - break; - } - } - else{ - break; - } + InstPtr ex_inst = inst_generator_->getNextInst(my_clk_); + if(SPARTA_EXPECT_TRUE(nullptr != ex_inst)){ + ex_inst->setSpeculative(speculative_path_); + insts_to_send->emplace_back(ex_inst); + + ILOG("Sending: " << ex_inst << " down the pipe"); + // we break after vset to break up instruction group + if(ex_inst->isVset()) { break; } + + } + else{ + break; } } @@ -130,13 +97,6 @@ namespace olympia } } - void Fetch::process_vset_(const InstPtr & inst) - { - waiting_on_vset_ = false; - ILOG("Recieved VSET from ExecutePipe, resuming fetching"); - // schedule fetch, because we've been stalled on vset - fetch_inst_event_->schedule(sparta::Clock::Cycle(0)); - } // Called when decode has room void Fetch::receiveFetchQueueCredits_(const uint32_t & dat) { credits_inst_queue_ += dat; diff --git a/core/Fetch.hpp b/core/Fetch.hpp index f57a0fdf..3087a2a6 100644 --- a/core/Fetch.hpp +++ b/core/Fetch.hpp @@ -56,7 +56,6 @@ namespace olympia PARAMETER(uint32_t, num_to_fetch, 4, "Number of instructions to fetch") PARAMETER(bool, skip_nonuser_mode, false, "For STF traces, skip system instructions if present") - PARAMETER(uint32_t, fetched_queue_size, 8, "Size of the fetched queue for holding instructions we have to wait on vset for") }; /** @@ -89,8 +88,6 @@ namespace olympia sparta::DataInPort in_fetch_flush_redirect_ {&unit_port_set_, "in_fetch_flush_redirect", sparta::SchedulingPhase::Flush, 1}; - // Incoming vset - sparta::DataInPort in_vset_inst_{&unit_port_set_, "in_vset_inst", 1}; //////////////////////////////////////////////////////////////////////////////// // Instruction fetch // Number of instructions to fetch @@ -113,8 +110,6 @@ namespace olympia // instructions or a perfect IPC set std::unique_ptr> fetch_inst_event_; - // waiting on vset flag - bool waiting_on_vset_ = false; //////////////////////////////////////////////////////////////////////////////// // Callbacks @@ -135,12 +130,6 @@ namespace olympia // Are we fetching a speculative path? bool speculative_path_ = false; - - // queue to hold fetched instructions that have to be stalled due to vset - // this is not to hold all fetched instructions!!! - // we have to hold because we generate instructions using getNextInst() - // and if we're waiting on vset, we have to hold the instructions until the vset is processed - InstQueue fetched_queue_; }; } diff --git a/core/Inst.hpp b/core/Inst.hpp index 90ec371c..ba6bb6d6 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -73,12 +73,13 @@ namespace olympia RegList src_; Reg data_reg_; }; - static const uint32_t VLMAX = 512; // vector length max of 512 bits + static const uint32_t VLMAX = 1024; // vector length max of 1024 bits // Vector CSRs struct VCSRs{ uint32_t vl = VLMAX; // vector length uint32_t sew = 8; // set element width uint32_t lmul = 1; // effective length + bool vta = false; // vector tail agnostic, false = undisturbed, true = agnostic }; // Used by Mavis using PtrType = sparta::SpartaSharedPointer; @@ -201,6 +202,10 @@ namespace olympia // UOpIDs start at 1, because we use 0 as default UOpID on initialization bool isUOp() const { return uopid_ > 0; } + void setBlockingVSET(bool is_blocking_vset){ is_blocking_vset_ = is_blocking_vset; } + + bool isBlockingVSET() const { return is_blocking_vset_; } + // Set the instruction's Program ID. This ID is specific to // an instruction's retire pointer. The same instruction in a // trace will have the same program ID (as compared to @@ -225,21 +230,27 @@ namespace olympia // Set the instruction's target PC (branch target or load/store target) void setTargetVAddr(sparta::memory::addr_t target_vaddr) { target_vaddr_ = target_vaddr; } - // Set lmul from immediate (vsetivli, vsetvli) + // Set lmul from vset (vsetivli, vsetvli) void setLMUL(uint32_t lmul) { VCSRs_.lmul = lmul; } - // Set sew from immediate (vsetivli, vsetvli) + // Set sew from vset (vsetivli, vsetvli) void setSEW(uint32_t sew) { VCSRs_.sew = sew; } - // Set sew from immediate (vsetivli, vsetvli) + // Set VL from vset (vsetivli, vsetvli) void setVL(uint32_t vl) { VCSRs_.vl = vl; } + // Set VTA (vector tail agnostic) + // vta = true means agnostic, set destination values to 1's or maintain original + // vta = false means undisturbed, maintain original destination values + void setVTA(bool vta) { VCSRs_.vta = vta; } + void setVCSRs(const VCSRs & inputVCSRs) { // setter if you want to set all 3 vector CSRs at once. VCSRs_.lmul = inputVCSRs.lmul; VCSRs_.sew = inputVCSRs.sew; VCSRs_.vl = inputVCSRs.vl; + VCSRs_.vta = inputVCSRs.vta; } void setUOpParent(sparta::SpartaWeakPointer & uop_parent){ @@ -260,6 +271,8 @@ namespace olympia uint32_t getVL() const { return VCSRs_.vl; } + uint32_t getVTA() const { return VCSRs_.vta; } + uint64_t getUOpDoneCount(){ return uop_done_count_; } sparta::SpartaWeakPointer getUOpParent() { return uop_parent_; } @@ -418,6 +431,8 @@ namespace olympia uint64_t uop_count_ = 0; VCSRs VCSRs_; + bool is_blocking_vset_ = false; + sparta::SpartaWeakPointer uop_parent_; // Did this instruction mispredict? bool is_mispredicted_ = false; diff --git a/core/InstArchInfo.cpp b/core/InstArchInfo.cpp index 11ec7312..e0b7e97a 100644 --- a/core/InstArchInfo.cpp +++ b/core/InstArchInfo.cpp @@ -12,7 +12,8 @@ namespace olympia {"i2f", InstArchInfo::TargetPipe::I2F}, {"f2i", InstArchInfo::TargetPipe::F2I}, {"int", InstArchInfo::TargetPipe::INT}, {"lsu", InstArchInfo::TargetPipe::LSU}, {"mul", InstArchInfo::TargetPipe::MUL}, {"vint", InstArchInfo::TargetPipe::VINT}, - {"vset", InstArchInfo::TargetPipe::VSET}, {"sys", InstArchInfo::TargetPipe::SYS}}; + {"vset", InstArchInfo::TargetPipe::VSET}, {"vmul", InstArchInfo::TargetPipe::VMUL}, + {"vdiv", InstArchInfo::TargetPipe::VDIV}, {"sys", InstArchInfo::TargetPipe::SYS}}; void InstArchInfo::update(const nlohmann::json & jobj) { @@ -38,7 +39,7 @@ namespace olympia is_load_store_ = (tgt_pipe_ == TargetPipe::LSU); is_vset_ = {tgt_pipe_ == TargetPipe::VSET}; - is_vector_ = {tgt_pipe_ == TargetPipe::VSET || tgt_pipe_ == TargetPipe::VINT}; + is_vector_ = {tgt_pipe_ == TargetPipe::VSET || tgt_pipe_ == TargetPipe::VINT || tgt_pipe_ == InstArchInfo::TargetPipe::VDIV || tgt_pipe_ == InstArchInfo::TargetPipe::VMUL}; } } // namespace olympia diff --git a/core/InstArchInfo.hpp b/core/InstArchInfo.hpp index a63e114f..519f311a 100644 --- a/core/InstArchInfo.hpp +++ b/core/InstArchInfo.hpp @@ -49,6 +49,8 @@ namespace olympia LSU, MUL, VINT, + VMUL, + VDIV, VSET, SYS, UNKNOWN @@ -129,6 +131,12 @@ namespace olympia case InstArchInfo::TargetPipe::VINT: os << "VINT"; break; + case InstArchInfo::TargetPipe::VMUL: + os << "VMUL"; + break; + case InstArchInfo::TargetPipe::VDIV: + os << "VDIV"; + break; case InstArchInfo::TargetPipe::VSET: os << "VINT"; break; diff --git a/core/InstGenerator.cpp b/core/InstGenerator.cpp index 927bc8c7..7c01d09c 100644 --- a/core/InstGenerator.cpp +++ b/core/InstGenerator.cpp @@ -145,6 +145,12 @@ namespace olympia inst->setSEW(sew); } + if (jinst.find("vta") != jinst.end()) + { + const bool vta = jinst["vta"].get() > 0 ? true: false; + inst->setVTA(vta); + } + if (jinst.find("vl") != jinst.end()) { const uint64_t vl = jinst["vl"].get(); diff --git a/core/IssueQueue.cpp b/core/IssueQueue.cpp index ee353a94..13d2cdff 100644 --- a/core/IssueQueue.cpp +++ b/core/IssueQueue.cpp @@ -100,29 +100,66 @@ namespace olympia // FIXME: Now every source operand should be ready auto reg_file = core_types::RegFile::RF_INTEGER; const auto srcs = ex_inst->getRenameData().getSourceList(); - if (srcs.size() > 0) - { - reg_file = srcs[0].rf; - } - const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file); - if (scoreboard_views_[reg_file]->isSet(src_bits)) - { - // Insert at the end if we are doing in order issue or if the scheduler is - // empty - ILOG("Sending to issue queue " << ex_inst); - // will insert based on if in_order_issue_ is set - // if it is, will be first in first out, if not it'll be by age, so by UniqueID (UID) - ready_queue_.insert(ex_inst); - ev_issue_ready_inst_.schedule(sparta::Clock::Cycle(0)); + + if(srcs.size() > 1 && srcs[0].rf != srcs[1].rf && ex_inst->isVector()){ + // we have a vector-scalar operation, 1 vector src and 1 scalar src + // need to check both + uint32_t ready = 0; + for(auto src: srcs){ + reg_file = src.rf; + const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file); + if (scoreboard_views_[reg_file]->isSet(src_bits)) + { + ready++; + } + else + { + // temporary fix for clearCallbacks not working + scoreboard_views_[reg_file]->registerReadyCallback( + src_bits, ex_inst->getUniqueID(), + [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) + { this->handleOperandIssueCheck_(ex_inst); }); + ILOG("Instruction NOT ready: " << ex_inst + << " Bits needed:" << sparta::printBitSet(src_bits) << " rf: " << reg_file); + // we break to prevent multiple callbacks from being sent out + break; + } + } + // we wait till the final callback comes back and checks in the case where both RF are ready at the same time + if(ready == srcs.size()){ + // all register file types are ready + ILOG("Sending to issue queue " << ex_inst); + // will insert based on if in_order_issue_ is set + // if it is, will be first in first out, if not it'll be by age, so by UniqueID (UID) + ready_queue_.insert(ex_inst); + ev_issue_ready_inst_.schedule(sparta::Clock::Cycle(0)); + } } - else - { - scoreboard_views_[reg_file]->registerReadyCallback( - src_bits, ex_inst->getUniqueID(), - [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) - { this->handleOperandIssueCheck_(ex_inst); }); - ILOG("Instruction NOT ready: " << ex_inst - << " Bits needed:" << sparta::printBitSet(src_bits)); + else{ + if (srcs.size() > 0) + { + reg_file = srcs[0].rf; + } + const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file); + if (scoreboard_views_[reg_file]->isSet(src_bits)) + { + // Insert at the end if we are doing in order issue or if the scheduler is + // empty + ILOG("Sending to issue queue " << ex_inst); + // will insert based on if in_order_issue_ is set + // if it is, will be first in first out, if not it'll be by age, so by UniqueID (UID) + ready_queue_.insert(ex_inst); + ev_issue_ready_inst_.schedule(sparta::Clock::Cycle(0)); + } + else + { + scoreboard_views_[reg_file]->registerReadyCallback( + src_bits, ex_inst->getUniqueID(), + [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) + { this->handleOperandIssueCheck_(ex_inst); }); + ILOG("Instruction NOT ready: " << ex_inst + << " Bits needed:" << sparta::printBitSet(src_bits) << " rf: " << reg_file); + } } } diff --git a/core/Rename.cpp b/core/Rename.cpp index bc62a8b3..735efb32 100644 --- a/core/Rename.cpp +++ b/core/Rename.cpp @@ -205,7 +205,15 @@ namespace olympia sparta_assert(oldest_inst->getUniqueID() == inst_ptr->getUniqueID(), "ROB and rename inst_queue out of sync"); } - inst_queue_.pop_front(); + if(inst_ptr->hasUOps()){ + // pop all UOps from inst_queue_ to relaign ROB and rename inst_queue + for(uint32_t i = 0; i < inst_ptr->getLMUL(); i++){ + inst_queue_.pop_front(); + } + } + else{ + inst_queue_.pop_front(); + } } else { @@ -492,6 +500,23 @@ namespace olympia } else { + if(renaming_inst->isVector() && !renaming_inst->isVset() && !renaming_inst->getVTA()){ + // if vector instruction is undisturbed and has a mask, so vta = false, we need to set the original destination as a source as well + // need to set before destination rename, because we need the original destination + + // TODO: Once we implement masks, add logic to check if vta is false and mask is being applied, then we need the original destination + // because if we always add 3rd source for undisturbed, then we're adding extra dependency, slowing the pipeline down + + // we set for source bitmask because we need to wait for previous destination to be written to before reading (RAW) hazard + auto & bitmask = renaming_inst->getSrcRegisterBitMask(rf); + const uint32_t prf = map_table_[rf][num]; + reference_counter_[rf][prf]++; + renaming_inst->getRenameData().setSource({prf, rf, dest.field_id}); + bitmask.set(prf); + + ILOG("\tsetup vector undisturbed source register bit mask " + << sparta::printBitSet(bitmask) << " for '" << rf << "' scoreboard"); + } auto & bitmask = renaming_inst->getDestRegisterBitMask(rf); const uint32_t prf = freelist_[rf].front(); freelist_[rf].pop(); @@ -510,6 +535,7 @@ namespace olympia scoreboards_[rf]->clearBits(bitmask); ILOG("\tsetup destination register bit mask " << sparta::printBitSet(bitmask) << " for '" << rf << "' scoreboard"); + } } // Remove it from uop queue diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 82e365e1..e4364e7a 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -33,4 +33,5 @@ add_subdirectory(core/rename) add_subdirectory(core/lsu) add_subdirectory(core/issue_queue) add_subdirectory(core/branch_pred) +add_subdirectory(core/vector) add_subdirectory(fusion) diff --git a/test/core/dispatch/expected_output/big_core.out.EXPECTED b/test/core/dispatch/expected_output/big_core.out.EXPECTED index 037a35d2..26aa7002 100644 --- a/test/core/dispatch/expected_output/big_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:28 2024 -#Elapsed: 0.017899s +#Start: Thursday Thu May 30 21:52:26 2024 +#Elapsed: 0.004124s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,21 +46,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -63,182 +70,182 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq2 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq2 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] -{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq2 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq2 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] -{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq2 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq2 of target type: INT {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] -{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe2 -{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe2 +{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq0 of target type: INT {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 4 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add, 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add, 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000006 00000006 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe4 -{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe4 +{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe2 -{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe2 +{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe4 -{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe4 +{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 7 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe2 -{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe2 +{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe4 -{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe4 +{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/medium_core.out.EXPECTED b/test/core/dispatch/expected_output/medium_core.out.EXPECTED index bc042b8f..fdcde4b8 100644 --- a/test/core/dispatch/expected_output/medium_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:34 2024 -#Elapsed: 0.004375s +#Start: Thursday Thu May 30 21:52:22 2024 +#Elapsed: 0.003758s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -16,12 +16,17 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq4 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 {0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.execute.exe4 info} ExecutePipe: ExecutePipe construct: #4 {0000000000 00000000 top.execute.exe5 info} ExecutePipe: ExecutePipe construct: #5 +{0000000000 00000000 top.execute.exe6 info} ExecutePipe: ExecutePipe construct: #6 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -34,21 +39,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -56,191 +63,191 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe1 -{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe1 +{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq1 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq1 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 2 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] -{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' +{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq1 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq1 of target type: INT {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 2 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] -{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe1 -{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe1 +{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe1 -{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe1 +{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe1 -{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe1 +{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe1 -{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe1 +{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/small_core.out.EXPECTED b/test/core/dispatch/expected_output/small_core.out.EXPECTED index 4e70d90a..4cc6d524 100644 --- a/test/core/dispatch/expected_output/small_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:37 2024 -#Elapsed: 0.004805s +#Start: Thursday Thu May 30 21:52:17 2024 +#Elapsed: 0.004074s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -15,9 +15,14 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq2 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq3 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 +{0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -28,21 +33,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -50,218 +57,218 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe0 -{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe0 +{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(23) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(13) PID(0) add -{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' +{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' stall: INT_BUSY +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' stall: INT_BUSY {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(24) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(14) PID(0) add -{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq0 of target type: INT -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' stall: INT_BUSY +{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq0 of target type: INT +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' stall: INT_BUSY {0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(25) PID(0) add -{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(15) PID(0) add -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' stall: INT_BUSY +{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' stall: INT_BUSY {0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq0 of target type: INT -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' stall: INT_BUSY +{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq0 of target type: INT +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' stall: INT_BUSY {0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(27) PID(0) add -{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] +{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(17) PID(0) add -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq0 of target type: INT -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' stall: INT_BUSY +{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq0 of target type: INT +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' stall: INT_BUSY {0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq0 of target type: INT +{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq0 of target type: INT {0000000011 00000011 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000011 00000011 top.decode info} inCredits: Got credits from dut: 1 {0000000011 00000011 top.decode info} Sending group: 0x00000000 UID(29) PID(0) add -{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000012 00000012 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(19) PID(0) add {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe0 -{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe0 +{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe0 -{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe0 +{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/test_cores/test_big_core.yaml b/test/core/dispatch/test_cores/test_big_core.yaml index 56fcd1c5..4119f823 100644 --- a/test/core/dispatch/test_cores/test_big_core.yaml +++ b/test/core/dispatch/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/dispatch/test_cores/test_medium_core.yaml b/test/core/dispatch/test_cores/test_medium_core.yaml index fe70dec9..a723a59e 100644 --- a/test/core/dispatch/test_cores/test_medium_core.yaml +++ b/test/core/dispatch/test_cores/test_medium_core.yaml @@ -1,6 +1,9 @@ + # -# Set up the pipeline for a 3-wide machine +# Set up the pipeline for a 2-wide machine # +#top.cpu: +# dispatch.num_to_dispatch: 2 top.extension.core_extensions: pipelines: @@ -10,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -25,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/dispatch/test_cores/test_small_core.yaml b/test/core/dispatch/test_cores/test_small_core.yaml index b154fa01..0d993d95 100644 --- a/test/core/dispatch/test_cores/test_small_core.yaml +++ b/test/core/dispatch/test_cores/test_small_core.yaml @@ -7,13 +7,15 @@ top.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -21,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/issue_queue/test_cores/test_big_core.yaml b/test/core/issue_queue/test_cores/test_big_core.yaml index ec35e30b..4119f823 100644 --- a/test/core/issue_queue/test_cores/test_big_core.yaml +++ b/test/core/issue_queue/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/issue_queue/test_cores/test_big_core_full.yaml b/test/core/issue_queue/test_cores/test_big_core_full.yaml index 66c1ec15..18315cad 100644 --- a/test/core/issue_queue/test_cores/test_big_core_full.yaml +++ b/test/core/issue_queue/test_cores/test_big_core_full.yaml @@ -13,7 +13,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index abf3ec67..619d9ce5 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,16 +3,16 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Jan 27 08:59:40 2024 -#Elapsed: 0.004092s +#Start: Thursday Thu May 30 21:50:32 2024 +#Elapsed: 0.012536s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 {0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received {0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested {0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,21 +48,21 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Requested -{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Requested +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested +{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested {0000000051 00000051 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000051 00000051 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000051 00000051 top.l2cache info} getReqFromICache_: Request received from ICache on the port @@ -77,15 +77,15 @@ {0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received +{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index bf6d8619..5af68b58 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,16 +3,16 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Jan 27 08:59:40 2024 -#Elapsed: 0.003294s +#Start: Thursday Thu May 30 21:50:19 2024 +#Elapsed: 0.015993s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 {0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received {0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested {0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received diff --git a/test/core/lsu/test_cores/test_big_core.yaml b/test/core/lsu/test_cores/test_big_core.yaml index e83682c6..4119f823 100644 --- a/test/core/lsu/test_cores/test_big_core.yaml +++ b/test/core/lsu/test_cores/test_big_core.yaml @@ -1,10 +1,6 @@ - # -# Set up the pipeline for a 2-wide machine +# Set up the pipeline for a 8-wide machine # -#top.cpu: -# dispatch.num_to_dispatch: 2 - top.extension.core_extensions: pipelines: [ @@ -17,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -25,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/lsu/test_cores/test_big_core_small_rename.yaml b/test/core/lsu/test_cores/test_big_core_small_rename.yaml index c0642231..bf1aaf72 100644 --- a/test/core/lsu/test_cores/test_big_core_small_rename.yaml +++ b/test/core/lsu/test_cores/test_big_core_small_rename.yaml @@ -4,10 +4,13 @@ # #top.cpu: # dispatch.num_to_dispatch: 2 - top: +top: rename.params.num_integer_renames: 34 rename.params.num_float_renames: 34 +# +# Set up the pipeline for a 8-wide machine +# top.extension.core_extensions: pipelines: [ @@ -20,7 +23,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -28,25 +32,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_medium_core.yaml b/test/core/lsu/test_cores/test_medium_core.yaml index 979835d6..a723a59e 100644 --- a/test/core/lsu/test_cores/test_medium_core.yaml +++ b/test/core/lsu/test_cores/test_medium_core.yaml @@ -13,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -28,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_medium_core_full.yaml b/test/core/lsu/test_cores/test_medium_core_full.yaml index a5d0ae4a..36e40fe3 100644 --- a/test/core/lsu/test_cores/test_medium_core_full.yaml +++ b/test/core/lsu/test_cores/test_medium_core_full.yaml @@ -21,14 +21,16 @@ top.cpu.core0.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -36,16 +38,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_small_core.yaml b/test/core/lsu/test_cores/test_small_core.yaml index 2704eaf3..0d993d95 100644 --- a/test/core/lsu/test_cores/test_small_core.yaml +++ b/test/core/lsu/test_cores/test_small_core.yaml @@ -1,22 +1,21 @@ - # # Set up the pipeline for a 2-wide machine # -#top.cpu: -# dispatch.num_to_dispatch: 2 top.extension.core_extensions: pipelines: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -24,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_small_core_full.yaml b/test/core/lsu/test_cores/test_small_core_full.yaml index da6e5864..6ff1c99c 100644 --- a/test/core/lsu/test_cores/test_small_core_full.yaml +++ b/test/core/lsu/test_cores/test_small_core_full.yaml @@ -23,13 +23,15 @@ top.cpu.core0.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.cpu.core0.rename.scoreboards: @@ -37,14 +39,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] diff --git a/test/core/rename/expected_output/big_core.out.EXPECTED b/test/core/rename/expected_output/big_core.out.EXPECTED index 4af48d33..7980baa7 100644 --- a/test/core/rename/expected_output/big_core.out.EXPECTED +++ b/test/core/rename/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:40:26 2024 -#Elapsed: 0.012103s +#Start: Thursday Thu May 30 21:48:01 2024 +#Elapsed: 0.005546s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,10 +46,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,43 +59,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED index 98fa8906..58a03b81 100644 --- a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED +++ b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:59 2024 -#Elapsed: 0.005573s +#Start: Thursday Thu May 30 21:48:06 2024 +#Elapsed: 0.006134s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,10 +46,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,39 +59,39 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NO_RENAMES diff --git a/test/core/rename/expected_output/medium_core.out.EXPECTED b/test/core/rename/expected_output/medium_core.out.EXPECTED index e0bf8a0f..36538f41 100644 --- a/test/core/rename/expected_output/medium_core.out.EXPECTED +++ b/test/core/rename/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:39:26 2024 -#Elapsed: 0.013707s +#Start: Thursday Thu May 30 21:47:56 2024 +#Elapsed: 0.00499s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -16,12 +16,17 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq4 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 {0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.execute.exe4 info} ExecutePipe: ExecutePipe construct: #4 {0000000000 00000000 top.execute.exe5 info} ExecutePipe: ExecutePipe construct: #5 +{0000000000 00000000 top.execute.exe6 info} ExecutePipe: ExecutePipe construct: #6 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -34,10 +39,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -45,43 +52,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/small_core.out.EXPECTED b/test/core/rename/expected_output/small_core.out.EXPECTED index 0d97e3a5..40837ecb 100644 --- a/test/core/rename/expected_output/small_core.out.EXPECTED +++ b/test/core/rename/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:39:15 2024 -#Elapsed: 0.019968s +#Start: Thursday Thu May 30 21:47:47 2024 +#Elapsed: 0.004745s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -15,9 +15,14 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq2 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq3 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 +{0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -28,10 +33,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -39,43 +46,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/test_cores/test_big_core.yaml b/test/core/rename/test_cores/test_big_core.yaml index ec35e30b..4119f823 100644 --- a/test/core/rename/test_cores/test_big_core.yaml +++ b/test/core/rename/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/rename/test_cores/test_big_core_full.yaml b/test/core/rename/test_cores/test_big_core_full.yaml index 66c1ec15..18315cad 100644 --- a/test/core/rename/test_cores/test_big_core_full.yaml +++ b/test/core/rename/test_cores/test_big_core_full.yaml @@ -13,7 +13,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/rename/test_cores/test_big_core_small_rename.yaml b/test/core/rename/test_cores/test_big_core_small_rename.yaml index dcbcfb37..bf1aaf72 100644 --- a/test/core/rename/test_cores/test_big_core_small_rename.yaml +++ b/test/core/rename/test_cores/test_big_core_small_rename.yaml @@ -23,7 +23,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -31,25 +32,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_big_core_small_rename_full.yaml b/test/core/rename/test_cores/test_big_core_small_rename_full.yaml index 07581a69..9423dee8 100644 --- a/test/core/rename/test_cores/test_big_core_small_rename_full.yaml +++ b/test/core/rename/test_cores/test_big_core_small_rename_full.yaml @@ -23,7 +23,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -31,25 +32,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_medium_core.yaml b/test/core/rename/test_cores/test_medium_core.yaml index 979835d6..a723a59e 100644 --- a/test/core/rename/test_cores/test_medium_core.yaml +++ b/test/core/rename/test_cores/test_medium_core.yaml @@ -13,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -28,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_medium_core_full.yaml b/test/core/rename/test_cores/test_medium_core_full.yaml index 85f39c74..36e40fe3 100644 --- a/test/core/rename/test_cores/test_medium_core_full.yaml +++ b/test/core/rename/test_cores/test_medium_core_full.yaml @@ -21,14 +21,16 @@ top.cpu.core0.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -36,16 +38,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_small_core.yaml b/test/core/rename/test_cores/test_small_core.yaml index b154fa01..0d993d95 100644 --- a/test/core/rename/test_cores/test_small_core.yaml +++ b/test/core/rename/test_cores/test_small_core.yaml @@ -7,13 +7,15 @@ top.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -21,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_small_core_full.yaml b/test/core/rename/test_cores/test_small_core_full.yaml index 20feb903..927db2d4 100644 --- a/test/core/rename/test_cores/test_small_core_full.yaml +++ b/test/core/rename/test_cores/test_small_core_full.yaml @@ -20,13 +20,15 @@ top.cpu.core0.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.cpu.core0.rename.scoreboards: @@ -34,14 +36,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/vector/CMakeLists.txt b/test/core/vector/CMakeLists.txt new file mode 100644 index 00000000..b4d3c3e3 --- /dev/null +++ b/test/core/vector/CMakeLists.txt @@ -0,0 +1,23 @@ +project(Vector_test) + +add_executable(Vector_test Vector_test.cpp ${SIM_BASE}/sim/OlympiaSim.cpp) +target_link_libraries(Vector_test core common_test ${STF_LINK_LIBS} mavis SPARTA::sparta) + +file(CREATE_LINK ${SIM_BASE}/mavis/json ${CMAKE_CURRENT_BINARY_DIR}/mavis_isa_files SYMBOLIC) +file(CREATE_LINK ${SIM_BASE}/arches ${CMAKE_CURRENT_BINARY_DIR}/arches SYMBOLIC) + +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/test_cores ${CMAKE_CURRENT_BINARY_DIR}/test_cores SYMBOLIC) + +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetivli_vadd_lmul_4.json ${CMAKE_CURRENT_BINARY_DIR}/vsetivli_vadd_lmul_4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetvl_vadd.json ${CMAKE_CURRENT_BINARY_DIR}/vsetvl_vadd.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetvli_vadd_sew_32.json ${CMAKE_CURRENT_BINARY_DIR}/vsetvli_vadd_sew_32.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetvli_vl_max_setting.json ${CMAKE_CURRENT_BINARY_DIR}/vsetvli_vl_max_setting.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/multiple_vset.json ${CMAKE_CURRENT_BINARY_DIR}/multiple_vset.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vmul_transfer.json ${CMAKE_CURRENT_BINARY_DIR}/vmul_transfer.json SYMBOLIC) + + + +sparta_named_test(Vector_test_vsetivli_lmul_4 Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vsetivli_vadd_lmul_4.json) +sparta_named_test(Vector_test_vsetvl_vadd Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vsetvl_vadd.json) +sparta_named_test(Vector_test_vsetvli_vadd_sew_32 Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vsetvli_vadd_sew_32.json) +sparta_named_test(Vector_test_vsetvli_vl_max_setting Vector_test big_core.out -c test_cores/test_big_core_full.yaml --input-file vsetvli_vl_max_setting.json) \ No newline at end of file diff --git a/test/core/vector/Vector_test.cpp b/test/core/vector/Vector_test.cpp new file mode 100644 index 00000000..2c4bee67 --- /dev/null +++ b/test/core/vector/Vector_test.cpp @@ -0,0 +1,237 @@ + +#include "CPUFactory.hpp" +#include "CoreUtils.hpp" +#include "Dispatch.hpp" +#include "MavisUnit.hpp" +#include "OlympiaAllocators.hpp" +#include "OlympiaSim.hpp" +#include "IssueQueue.hpp" +#include "test/core/dispatch/Dispatch_test.hpp" + +#include "sparta/app/CommandLineSimulator.hpp" +#include "sparta/app/Simulation.hpp" +#include "sparta/events/UniqueEvent.hpp" +#include "sparta/kernel/Scheduler.hpp" +#include "sparta/report/Report.hpp" +#include "sparta/resources/Buffer.hpp" +#include "sparta/simulation/ClockManager.hpp" +#include "sparta/sparta.hpp" +#include "sparta/statistics/StatisticSet.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/SpartaTester.hpp" + +#include +#include +#include +#include +#include +TEST_INIT + +//////////////////////////////////////////////////////////////////////////////// +// Set up the Mavis decoder globally for the testing +olympia::InstAllocator inst_allocator(2000, 1000); + +const char USAGE[] = "Usage:\n" + " \n" + "\n"; + +sparta::app::DefaultValues DEFAULTS; + +class olympia::DecodeTester { +public: + void test_waiting_on_vset(olympia::Decode &decode) { + EXPECT_TRUE(decode.waiting_on_vset_ == true); + } + void test_no_waiting_on_vset(olympia::Decode &decode) { + // test waiting on vset is false + EXPECT_TRUE(decode.waiting_on_vset_ == false); + } + void test_VCSRs(olympia::Decode &decode) { + // test VCSRs + EXPECT_TRUE(decode.VCSRs_.lmul == 1); + EXPECT_TRUE(decode.VCSRs_.vl == 256); + EXPECT_TRUE(decode.VCSRs_.vta == 0); + EXPECT_TRUE(decode.VCSRs_.sew == 8); + } + + void test_VCSRs_after(olympia::Decode &decode) { + // test VCSRs + EXPECT_TRUE(decode.VCSRs_.lmul == 4); + EXPECT_TRUE(decode.VCSRs_.vl == 1024); + EXPECT_TRUE(decode.VCSRs_.vta == 0); + EXPECT_TRUE(decode.VCSRs_.sew == 8); + } + + void test_VCSRs_sew_32(olympia::Decode &decode) { + // test VCSRs + EXPECT_TRUE(decode.VCSRs_.lmul == 1); + EXPECT_TRUE(decode.VCSRs_.vl == 512); + EXPECT_TRUE(decode.VCSRs_.vta == 1); + EXPECT_TRUE(decode.VCSRs_.sew == 32); + } + + void test_vl_max(olympia::Decode &decode){ + EXPECT_TRUE(decode.VCSRs_.vl == 1024); + EXPECT_TRUE(decode.VCSRs_.lmul == 8); + EXPECT_TRUE(decode.VCSRs_.vta == 1); + EXPECT_TRUE(decode.VCSRs_.sew == 64); + } + + void test_VCSRs_mul_vset(olympia::Decode &decode){ + EXPECT_TRUE(decode.VCSRs_.vl == 128); + EXPECT_TRUE(decode.VCSRs_.lmul == 1); + EXPECT_TRUE(decode.VCSRs_.vta == 0); + EXPECT_TRUE(decode.VCSRs_.sew == 32); + } +}; + +class olympia::IssueQueueTester { +public: + void test_uop_count(olympia::IssueQueue &issuequeue) { + // 4 UOps + 1 vset instruction, so 5 total + EXPECT_TRUE(issuequeue.total_insts_issued_ == 5); + } + + void test_no_uop_count(olympia::IssueQueue &issuequeue) { + // 2 instructions, no uops + EXPECT_TRUE(issuequeue.total_insts_issued_ == 2); + } + + void no_inst_issued(olympia::IssueQueue &issuequeue) { + EXPECT_TRUE(issuequeue.total_insts_issued_ == 0); + } +}; +void runIQTest(int argc, char **argv) { + DEFAULTS.auto_summary_default = "off"; + std::vector datafiles; + std::string input_file; + bool enable_vector; + + sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); + auto &app_opts = cls.getApplicationOptions(); + app_opts.add_options()("output_file", + sparta::app::named_value>( + "output_file", &datafiles), + "Specifies the output file")( + "input-file", + sparta::app::named_value("INPUT_FILE", &input_file) + ->default_value(""), + "Provide a JSON instruction stream", + "Provide a JSON file with instructions to run through Execute")( + "enable_vector", + sparta::app::named_value("enable_vector", &enable_vector) + ->default_value(false), + "Enable the experimental vector pipelines"); + + po::positional_options_description &pos_opts = cls.getPositionalOptions(); + pos_opts.add("output_file", + -1); // example, look for the at the end + + int err_code = 0; + if (!cls.parse(argc, argv, err_code)) { + sparta_assert( + false, + "Command line parsing failed"); // Any errors already printed to cerr + } + + sparta_assert(false == datafiles.empty(), + "Need an output file as the last argument of the test"); + sparta::Scheduler scheduler; + + uint64_t ilimit = 0; + uint32_t num_cores = 1; + bool show_factories = false; + OlympiaSim sim("simple", scheduler, + num_cores, // cores + input_file, ilimit, show_factories); + + if (input_file.find("vsetivli_vadd_lmul_4.json") != std::string::npos) { + sparta::RootTreeNode *root_node = sim.getRoot(); + cls.populateSimulation(&sim); + olympia::Decode *my_decode = + root_node->getChild("cpu.core0.decode") + ->getResourceAs(); + olympia::DecodeTester decode_tester; + + decode_tester.test_VCSRs(*my_decode); + cls.runSimulator(&sim, 3); + decode_tester.test_no_waiting_on_vset(*my_decode); + decode_tester.test_VCSRs_after(*my_decode); + cls.runSimulator(&sim, 8); + decode_tester.test_VCSRs_after(*my_decode); + cls.runSimulator(&sim); + olympia::IssueQueue *my_issuequeue = + root_node->getChild("cpu.core0.execute.iq5") + ->getResourceAs(); + + olympia::IssueQueueTester issue_queue_tester; + issue_queue_tester.test_uop_count(*my_issuequeue); + } + else if(input_file.find("vsetvli_vadd_sew_32.json") != std::string::npos){ + sparta::RootTreeNode *root_node = sim.getRoot(); + cls.populateSimulation(&sim); + cls.runSimulator(&sim, 8); + olympia::Decode *my_decode = + root_node->getChild("cpu.core0.decode") + ->getResourceAs(); + olympia::DecodeTester decode_tester; + decode_tester.test_VCSRs_sew_32(*my_decode); + cls.runSimulator(&sim); + olympia::IssueQueue *my_issuequeue = + root_node->getChild("cpu.core0.execute.iq5") + ->getResourceAs(); + + olympia::IssueQueueTester issue_queue_tester; + issue_queue_tester.test_no_uop_count(*my_issuequeue); + } + else if(input_file.find("vsetvl_vadd.json") != std::string::npos) + { + sparta::RootTreeNode *root_node = sim.getRoot(); + cls.populateSimulation(&sim); + cls.runSimulator(&sim, 4); + olympia::Decode *my_decode = + root_node->getChild("cpu.core0.decode") + ->getResourceAs(); + olympia::DecodeTester decode_tester; + decode_tester.test_waiting_on_vset(*my_decode); + } + else if(input_file.find("vsetvli_vl_max_setting.json") != std::string::npos){ + sparta::RootTreeNode *root_node = sim.getRoot(); + cls.populateSimulation(&sim); + cls.runSimulator(&sim, 4); + olympia::Decode *my_decode = + root_node->getChild("cpu.core0.decode") + ->getResourceAs(); + olympia::DecodeTester decode_tester; + decode_tester.test_vl_max(*my_decode); + } + else if(input_file.find("multiple_vset.json") != std::string::npos){ + sparta::RootTreeNode *root_node = sim.getRoot(); + cls.populateSimulation(&sim); + olympia::Decode *my_decode = + root_node->getChild("cpu.core0.decode") + ->getResourceAs(); + olympia::DecodeTester decode_tester; + cls.runSimulator(&sim, 21); + decode_tester.test_VCSRs_mul_vset(*my_decode); + } + else if(input_file.find("vmul_transfer.json") != std::string::npos){ + sparta::RootTreeNode *root_node = sim.getRoot(); + cls.populateSimulation(&sim); + cls.runSimulator(&sim, 7); + olympia::IssueQueue *my_issuequeue = + root_node->getChild("cpu.core0.execute.iq5") + ->getResourceAs(); + + olympia::IssueQueueTester issue_queue_tester; + // vmul.vx relies on scalar add, should not process until it's done RAW hazard + issue_queue_tester.no_inst_issued(*my_issuequeue); + } +} + +int main(int argc, char **argv) { + runIQTest(argc, argv); + + REPORT_ERROR; + return (int)ERROR_CODE; +} \ No newline at end of file diff --git a/test/core/vector/multiple_vset.json b/test/core/vector/multiple_vset.json new file mode 100644 index 00000000..e53b6695 --- /dev/null +++ b/test/core/vector/multiple_vset.json @@ -0,0 +1,91 @@ +[ + { + "mnemonic": "vsetvl", + "rs1": 3, + "vtype": "0x18", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + }, + { + "mnemonic": "vsetvli", + "rs1": 0, + "vtype": "0x10", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + }, + { + "mnemonic": "vsetvli", + "rs1": 2, + "vtype": "0x10", + "rd": 1, + "vl": 128, + "vta": 0 + }, + { + "mnemonic": "add", + "rs1": 1, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "sw", + "rs2": 4, + "rs1": 3, + "imm": 5 + }, + { + "mnemonic": "lw", + "rs1": 3, + "rs2": 4, + "rd": 5, + "vaddr" : "0xdeadbeef" + }, + { + "mnemonic": "vadd.vv", + "vs1": 1, + "vs2": 10, + "vd": 22 + }, + { + "mnemonic": "vsetvli", + "rs1": 2, + "vtype": "0x10", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + }, + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 1024, + "vta": 0 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] \ No newline at end of file diff --git a/test/core/vector/test_cores/test_big_core_full.yaml b/test/core/vector/test_cores/test_big_core_full.yaml new file mode 100644 index 00000000..2ea2b8d1 --- /dev/null +++ b/test/core/vector/test_cores/test_big_core_full.yaml @@ -0,0 +1,69 @@ +# +# Set up the pipeline for a 8-wide machine +# +top.cpu.core0: + fetch.params.num_to_fetch: 8 + decode.params.num_to_decode: 3 + rename.params.num_integer_renames: 64 + rename.params.num_float_renames: 64 + rename.params.num_vector_renames: 64 + dispatch.params.num_to_dispatch: 8 + rob.params.num_to_retire: 8 + dcache.params: + l1_size_kb: 64 + +top.cpu.core0.extension.core_extensions: + pipelines: + [ + ["int"], # alu0 + ["int", "div"], # alu1 + ["int", "mul"], + ["int", "mul", "i2f", "cmov"], + ["int"], + ["int"], + ["float", "faddsub", "fmac"], + ["float", "f2i"], + ["br"], + ["br"], + ["vint", "vset", "vdiv", "vmul"] + ] + issue_queue_to_pipe_map: + [ + ["0", "1"], + ["2", "3"], + ["4", "5"], + ["6", "7"], + ["8", "9"], + ["10"] + ] +top.cpu.core0.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + float.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/vector/vmul_transfer.json b/test/core/vector/vmul_transfer.json new file mode 100644 index 00000000..9c435b12 --- /dev/null +++ b/test/core/vector/vmul_transfer.json @@ -0,0 +1,14 @@ +[ + { + "mnemonic": "add", + "rs1": 1, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "vmul.vx", + "vd": 5, + "vs2": 4, + "rs1": 3 + } +] \ No newline at end of file diff --git a/test/core/vector/vsetivli_vadd_lmul_4.json b/test/core/vector/vsetivli_vadd_lmul_4.json new file mode 100644 index 00000000..006fc2c3 --- /dev/null +++ b/test/core/vector/vsetivli_vadd_lmul_4.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 1024, + "vta": 0 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] \ No newline at end of file diff --git a/test/core/vector/vsetvl_vadd.json b/test/core/vector/vsetvl_vadd.json new file mode 100644 index 00000000..4c99b9bc --- /dev/null +++ b/test/core/vector/vsetvl_vadd.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetvl", + "rs1": 0, + "vtype": "0x18", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] \ No newline at end of file diff --git a/test/core/vector/vsetvli_vadd_sew_32.json b/test/core/vector/vsetvli_vadd_sew_32.json new file mode 100644 index 00000000..5b7ff8bf --- /dev/null +++ b/test/core/vector/vsetvli_vadd_sew_32.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetvli", + "rs1": 2, + "vtype": "0x10", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] \ No newline at end of file diff --git a/test/core/vector/vsetvli_vl_max_setting.json b/test/core/vector/vsetvli_vl_max_setting.json new file mode 100644 index 00000000..eb33ef28 --- /dev/null +++ b/test/core/vector/vsetvli_vl_max_setting.json @@ -0,0 +1,15 @@ +[ + { + "mnemonic": "vsetvli", + "rs1": 0, + "vtype": "0x1B", + "rd": 1, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] \ No newline at end of file