From 678bd886874b2607686b6d1aba9772273a0986a1 Mon Sep 17 00:00:00 2001 From: Suraj Shirvankar Date: Wed, 31 Jul 2024 17:01:06 +0200 Subject: [PATCH] Rename function and update tests to match --- core/DCache.hpp | 20 ++++---- .../expected_output/arbitrate.out.EXPECTED | 50 +++++++++---------- test/core/dcache/next_lvl_cache_refill.json | 2 - 3 files changed, 36 insertions(+), 36 deletions(-) diff --git a/core/DCache.hpp b/core/DCache.hpp index bd62f223..36d0349d 100644 --- a/core/DCache.hpp +++ b/core/DCache.hpp @@ -121,13 +121,13 @@ namespace olympia //////////////////////////////////////////////////////////////////////////////// // Events //////////////////////////////////////////////////////////////////////////////// - sparta::UniqueEvent<> uev_mshr_request_{ - &unit_event_set_, "mshr_request", CREATE_SPARTA_HANDLER(DCache, mshrRequest_)}; - + sparta::UniqueEvent<> uev_mshr_request_{&unit_event_set_, "mshr_request", + CREATE_SPARTA_HANDLER(DCache, mshrRequest_)}; sparta::utils::ValidValue l2_mem_access_info_; sparta::utils::ValidValue lsu_mem_access_info_; - void arbitrate_l2_lsu_req_() + + void arbitrateL2LsuReq_() { if (l2_mem_access_info_.isValid()) { @@ -141,18 +141,20 @@ namespace olympia ILOG("Received LSU request " << mem_access_info_ptr); cache_pipeline_.append(mem_access_info_ptr); } - if(l2_mem_access_info_.isValid()){ + if (l2_mem_access_info_.isValid()) + { l2_mem_access_info_.clearValid(); } - if(lsu_mem_access_info_.isValid()){ + if (lsu_mem_access_info_.isValid()) + { lsu_mem_access_info_.clearValid(); } uev_mshr_request_.schedule(1); } - sparta::UniqueEvent<> in_l2_cache_resp_receive_event_{&unit_event_set_, - "in_l2_cache_resp_receive_event", - CREATE_SPARTA_HANDLER(DCache, arbitrate_l2_lsu_req_)}; + sparta::UniqueEvent<> in_l2_cache_resp_receive_event_{ + &unit_event_set_, "in_l2_cache_resp_receive_event", + CREATE_SPARTA_HANDLER(DCache, arbitrateL2LsuReq_)}; //////////////////////////////////////////////////////////////////////////////// // Counters diff --git a/test/core/dcache/expected_output/arbitrate.out.EXPECTED b/test/core/dcache/expected_output/arbitrate.out.EXPECTED index 43b4a73d..12179a3c 100644 --- a/test/core/dcache/expected_output/arbitrate.out.EXPECTED +++ b/test/core/dcache/expected_output/arbitrate.out.EXPECTED @@ -3,39 +3,39 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Sunday Sun Jul 28 19:23:40 2024 -#Elapsed: 0.002382s -{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' ' Requested -{0000000001 00000001 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' -{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' ' Received -{0000000001 00000001 top.dcache info} arbitrate_l2_lsu_req_: Received LSU request memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' +#Start: Wednesday Wed Jul 31 16:59:06 2024 +#Elapsed: 0.002178s +{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' Requested +{0000000001 00000001 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' +{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' Received +{0000000001 00000001 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' {0000000002 00000002 top.dcache info} mshrRequest_: Send mshr req {0000000002 00000002 top.dcache info} handleLookup_: Lookup stage -{0000000002 00000002 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' in Lookup stage +{0000000002 00000002 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in Lookup stage {0000000002 00000002 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeadbeef -{0000000002 00000002 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' performing lookup 0 -{0000000002 00000002 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' +{0000000002 00000002 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' performing lookup 0 +{0000000002 00000002 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' {0000000002 00000002 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeadbee0 -{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' ' Received +{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' Received {0000000003 00000003 top.dcache info} handleDataRead_: Data Read stage -{0000000003 00000003 top.dcache info} handleDataRead_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' in read stage -{0000000003 00000003 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' ' Received -{0000000004 00000004 top.next_lvl info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' ' sinked +{0000000003 00000003 top.dcache info} handleDataRead_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in read stage +{0000000003 00000003 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' Received +{0000000004 00000004 top.next_lvl info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' sinked {0000000004 00000004 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000004 00000004 top.dcache info} handleDeallocate_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' in deallocate stage -{0000000004 00000004 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' -{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested -{0000000009 00000009 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' -{0000000009 00000009 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' -{0000000009 00000009 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' -{0000000009 00000009 top.dcache info} arbitrate_l2_lsu_req_: Received Refill request memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' -{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received +{0000000004 00000004 top.dcache info} handleDeallocate_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in deallocate stage +{0000000004 00000004 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' +{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3' ' Requested +{0000000009 00000009 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' +{0000000009 00000009 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' +{0000000009 00000009 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3' +{0000000009 00000009 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' +{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3' ' Received {0000000010 00000010 top.dcache info} mshrRequest_: Send mshr req {0000000010 00000010 top.dcache info} handleLookup_: Lookup stage -{0000000010 00000010 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' in Lookup stage -{0000000010 00000010 top.dcache info} handleLookup_: Incoming cache refill memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' +{0000000010 00000010 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in Lookup stage +{0000000010 00000010 top.dcache info} handleLookup_: Incoming cache refill memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' {0000000011 00000011 top.dcache info} handleDataRead_: Data Read stage -{0000000011 00000011 top.dcache info} handleDataRead_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' in read stage +{0000000011 00000011 top.dcache info} handleDataRead_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in read stage {0000000011 00000011 top.dcache info} reloadCache_: DCache reload complete! {0000000012 00000012 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000012 00000012 top.dcache info} handleDeallocate_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3,4' in deallocate stage +{0000000012 00000012 top.dcache info} handleDeallocate_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in deallocate stage diff --git a/test/core/dcache/next_lvl_cache_refill.json b/test/core/dcache/next_lvl_cache_refill.json index dc834789..4633535c 100644 --- a/test/core/dcache/next_lvl_cache_refill.json +++ b/test/core/dcache/next_lvl_cache_refill.json @@ -2,14 +2,12 @@ { "mnemonic": "lw", "rs1": 3, - "rs2": 4, "rd": 5, "vaddr" : "0xdeadbeef" }, { "mnemonic": "lw", "rs1": 3, - "rs2": 4, "rd": 5, "vaddr" : "0xdeedbeef" }